User Manual Q&AAnswer
Aug 04, 2025 - 02:03 AM
To generate the F-Tile JESD204C design examples for Intel Agilex devices, follow these steps using the IP catalog in the Intel Quartus Prime Pro Edition software:
1. Create a Project:
- Create a project targeting Intel Agilex F-tile device family and select the desired device.
2. Access IP Catalog:
- In the Intel Quartus Prime Pro Edition software, go to Tools ➤ IP Catalog.
3. Select F-Tile JESD204C Intel FPGA IP:
- In the IP Catalog, select F-Tile JESD204C Intel FPGA IP.
4. Specify Top-Level Name:
- Specify a top-level name and the folder for your custom IP variation. Click OK.
5. Generate Example Design:
- Under the Example Design tab, specify the design example parameters as described in the Design Example Parameters section of the user guide.
- Click Generate Example Design.
6. Compile Design:
- The software will generate all design files in the sub-directories required to run simulation and compilation.
- Open the Intel Quartus Prime Pro Edition project <example_design_directory>/ed/quartus.
- On the Processing menu, click Start Compilation.
By following these steps, you can generate the F-Tile JESD204C design examples for Intel Agilex devices using the IP catalog in the Intel Quartus Prime Pro Edition software.
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