User Manual Q&AAnswer
Mar 07, 2025 - 02:28 AM
To access the error message register (EMR) in your Intel FPGA device using the Error Message Register Unloader FPGA IP Core, follow these steps:
1. Instantiate the Error Message Register Unloader IP core in your design using the parameter editor GUI. You can generate VHDL or Verilog HDL synthesis files for the IP core.
2. Connect the necessary signals to the IP core. The IP core requires the following signals:
- clock: Input clock signal.
- reset: Active-high logic reset signal.
- emr_read (optional): This active-high signal initiates rereading the current EMR content.
- crcerror: Output signal that indicates the detection of a CRC error.
- crcerror_pin: Output signal that should be connected to the CRC_Error pin.
- crcerror_clk: Input clock signal for the CRC Error Verify IP core.
- crcerror_reset: Active-high logic reset signal for the CRC Error Verify IP core.
- emr[N-1:0]: Output data port that contains the device's error message register contents.
- emr_valid: Output signal that is active high when the emr signal contents are valid.
- emr_error: Output signal that is active high when the current EMR output transfer has an error and should be ignored.
- endoffullchip (optional): Output signal that indicates the end of each full-chip error detection cycle for the entire device.
3. Configure the IP core parameters using the parameter editor GUI. The parameters include:
- CRC error check clock divisor: Specifies the error detection clock divisor value to apply to the internal oscillator.
- Enable Virtual JTAG CRC error injection: Enables in-system sources and probes (ISSP) functionality to inject the EMR register content via the JTAG interface without changing the CRAM value.
- Input clock frequency: Specifies the frequency of the Error Message Register Unloader IP core input clock.
- Input clock is driven from Internal Oscillator: Indicates whether the internal oscillator provides the core input clock.
- CRC Error Verify input clock frequency: Specifies the input clock frequency for the CRC Error Verify IP core.
- Completion of full chip Error Detection cycle: Optional signal that can be asserted at the end of each full chip error detection cycle.
4. Generate the necessary files for synthesis and simulation based on your IP variation specifications using the parameter editor GUI.
By following these steps, you can use the Error Message Register Unloader FPGA IP Core to access the error message register in your Intel FPGA device. For more detailed information and specific instructions, refer to the Error Message Register Unloader FPGA IP Core User Guide provided by Intel.
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