Quartz64 - PINE64
RK817 Datasheet Rev 1.01 Rockchip RK817 Datasheet Revision 1.01 Aug.2018 Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 1 RK817 Datasheet Date 2018-8-28 2018-3-12 Revision History Revision Description 1.01 Spec change @ power up sequence 1.0 Initial release Rev 1.01 Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 2 RK817 Datasheet Rev 1.01 Table of Content Table of Content .................................................................................................. 3 Figure Index ....................................................................................................... 5 Table Index 6 Warranty Disclaimer ............................................................................................. 7 Chapter 1 Introduction ....................................................................................... 8 1.2 Feature ................................................................................................... 9 1.3 Typical Application Diagrams .....................................................................10 Chapter 2 Package information ...........................................................................11 2.1 Ordering information ................................................................................11 2.2 Top Marking ............................................................................................11 2.3 Dimension ..............................................................................................12 2.4 Pin Assignment........................................................................................13 2.5 Pinout Number Order ...............................................................................13 Chapter 3 Electrical Characteristics......................................................................16 3.1 Absolute Maximum Ratings .......................................................................16 3.2 Recommended Operating Conditions...........................................................16 3.3 DC Characteristics ...................................................................................16 Chapter 4 Function Description ...........................................................................21 4.1 POWER UP/POWER DOWN.........................................................................21 4.2 SWITCHING CHARGER..............................................................................21 4.3 POWER PATH MANAGEMENT ......................................................................22 4.4 THERMAL FOLDBACK................................................................................22 4.5 BATTERY FUEL GAUGE ..............................................................................22 4.6 BUCK CONVERTERS .................................................................................22 4.7 BOOST CONVERTER .................................................................................23 4.8 LOW DROPOUT REGULATORS (LDOS) .........................................................23 4.9 REAL TIME CLOCK (RTC)...........................................................................23 4.10 RC OSCILLATOR ......................................................................................23 4.11 I2S interface ...........................................................................................23 4.12 Audio CODEC ..........................................................................................23 4.13 Head Phone driver ...................................................................................23 4.14 ClassD driver ..........................................................................................24 4.15 POWER SEQUENCE ..................................................................................24 Chapter 5 Register Description............................................................................25 5.1 Register Summary ...................................................................................25 Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 3 RK817 Datasheet Rev 1.01 5.2 Register Description .................................................................................30 Chapter 6 Thermal Management ....................................................................... 118 6.1 Overview .............................................................................................. 118 6.2 Package Thermal Characteristics .............................................................. 118 Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 4 RK817 Datasheet Rev 1.01 Figure Index Fig. 1-1RK817 Typical Application Diagram ......................................................... 10 Fig. 2-1QFN687mm X 7mm.............................................................................. 12 Fig. 2-2 Pin Assignment QFN7x7-68(Pitch=0.35mm) ........................................... 13 Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 5 RK817 Datasheet Rev 1.01 Table Index Table 4-1Power up/down sequence(x:BUCK3 voltage determined by external divided resistor) .............................................................................................................. 24 Table 6-1 Thermal Resistance Characteristics .................................................... 118 Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 6 RK817 Datasheet Rev 1.01 Warranty Disclaimer Rockchip Electronics Co.,Ltd makes no warranty, representation or guarantee (expressed, implied, statutory, or otherwise) by or with respect to anything in this document, and shall not be liable for any implied warranties of non-infringement, merchantability or fitness for a particular purpose or for any indirect, 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Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 7 RK817 Datasheet Rev 1.01 Chapter 1 Introduction 1.1 Overview The RK817 is a complex power-management integrated circuit (PMIC) integrated CODEC for multi-core system applications powered by a Li-ion or a Li-ion polymer battery cell, or by a 5V input either from an USB port or from an adaptor. The RK817 can provide a complete power management solution with very few external components. The RK817 provides four configurable synchronous step-down converters. The device also contains 9 LDO regulators, one switch-mode charger, a battery fuel gauge, and the power path management function. Power-up/power-down controller is configurable and can support any customized power-up/power-down sequences (OTP based). A real-time clock (RTC) is also integrated to provide a 32.768-kHz output buffer, and real time function. The RK817 supports 32.768-kHz clock generation based on a crystal oscillator. It also includes Audio CODEC, real ground Head phone driver and ClassD driver. The switch-mode charger, together with the power path controller integrated in the RK817, allows supplying power to the loads while it is charging the battery. The charger provides functions such as input current limiting, trickle current charging, constant current (CC)/constant voltage (CV) charging, charging termination, charging over time protection, etc. All these functions can be conveniently configured through the I2C digital interface. When an input current limiting is triggered, the power path controller will distribute the input power in a way that the loads have the higher priority than the battery to take the input power. The difference between the input and output power will be used to charge the battery. In a case that the output power required by the loads exceeds the input power, the power path controller will automatically turn on the battery switch so that the battery can supply extra power to the loads together with the input supply. A "battery fuel gauge" is also integrated in the RK817. Using the proprietary algorithms and the sensed battery current and voltage, the gauge can accurately calculate the battery capacity based on the charging/discharging characteristics of the battery preloaded in the system. The gauge then sends the battery capacity information to the processor through the I2C interface. Other functions that the charger provides includes tiny current charging for an over discharged battery, or so called "dead battery", battery temperature monitoring, safe charging timer and over temperature shut down. The RK817 can dynamically adjust the output voltage of each DC-DC converter, as required by the processor based on the processor's operation status so as to maximize the system efficiency. The output voltages of most channels can be configured through the I2C interface. The inputs of all channels have soft start function, which greatly reduces the inrush current at the startup. The 2MHz switching frequency allows small size inductors to be used for both buck and boost converters. Also, as all the power switches are integrated on chip, no external power switches and Schottky diodes are needed, which reduces the system cost significantly. The RK817 is available in a QFN68 7.0 mm x 7.0 mm package, with a 0.35-mm pin pitch. Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 8 RK817 Datasheet Rev 1.01 1.2 Feature Input range: 3.8V 5.5V for USB input 2.7V - 5.5V for BAT input Switch mode Li-ion battery charger providing charging current up to 3.5A. Power path controller with 4A current path with optional extended external mos. Accurate battery fuel gauge with two separate battery voltage and current ADC Real time clockRTC Low standby current of 16uA (at 32.768KHz clock frequency) Real ground HeadPhone driver 1.3W ClassD PA without external filter inductor OTP Programmable power up/down sequences and voltage High performance Audio CODEC One internal PLL Support microphone input Support I2S as the digital signal interface for both DAC and ADC Support Automatic Level Control(ALC),limiter and noise gating Support programmable digital and analog gains Audio resolution from 16bits to 32bits Sample rate up to 192KHz Provides master and slave work mode, software configurable Support 3 I2S formats (normal, left-justified, right-justified) Support PDM mode(external input PCLK) Power channels: CH1:Synchronous BUCK converter,2.5A max CH2:Synchronous BUCK converter,2.5A max CH3:Synchronous BUCK converter,1.5A max CH4:Synchronous BUCK converter,1.5A max CH5:Synchronous BOOST converter,1.5A max(Can not be used at the same time with the charger function) CH6~CH7,CH9~CH14:LDOs, 400mA max CH8:Low noise, high PSRR LDO,100mA max CH15:OTG Switch,1.5A max(Can not be used at the same time with the charger function) Package:7mmx7mm QFN68 Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 9 RK817 Datasheet Rev 1.01 1.3 TypicalApplication Diagrams USB input /OTG output 4.7uF 22uF USB/OTG MIDU/BOOST 1uF Vsys VCC5 1uF CODEC_IO VLDO1 1uF VLDO2 1uF VLDO3 1uF VCC_IO VCC6 1uF VLDO4 1uF VLDO5 1uF VLDO6 Vsys 1uF VCC7 1uF VLDO7 1uF VLDO8 1uF VLDO9 1uF VREF GNDREF 22pF Optional 22pF 32.768K XIN XOUT PWRON PWRON Vsys RK817 Optional 10uF Gate GATE BAT Exposed GND BAT TS/GPIO SYS SYS SW5 Vsys 0.47uH/5A Vsys VCC1 SW1 10uF 0.47uH/4A 33uF 22uF*2 VFB1 Vsys 10uF VCC2 0.47uH/4A SW2 33uF VFB2 Vsys 10uF VCC3 0.47uH/2.5A SW3 VBUCK3 VFB3 22uF VCC4 SW4 Vsys 10uF 0.47uH/3A VCC_IO 22uF VFB4 SLEEP SLEEP VCC_IO 100K 100K 100K INT RESETB CLK32K VCC_IO Battery pack 10 mohm VLDO 2.2uF 2.2uF 1uF 1uF 1uF SNSP SNSN MIC1P MIC1N CPP CPN VCC_CPVSS VCC_CPVDD VCC_1P8A VCC_1P8D SCL SDA MCLK BCLK LRCLK SDI SDO/PDMDATA PDMCLK 4.7K 4.7K HPR_OUT HPL_OUT HP_SNS Vsys 10uF VCC_SPK_HP SPKP_OUT SPKN_OUT VCC_RTC 1uF SCL SDA (VCC_IO) AP Fig. 1-1RK817 Typical Application Diagram Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 10 RK817 Datasheet Chapter 2 Package information 2.1 Ordering information Orderable Device RK817-1 RoHS status RoHS 2.2 Top Marking Package QFN68(7X7) Rev 1.01 Package Qty 2600ea/inner box* 6 inner boxes/outer box Rockchip RK817-1 ABCXXXXXX DEFG The first pin Rockchip : Brand Name RKXXXX : Chip Name ABC : Subcontractor Code XXXXXX : Die Lot NO # DEFG : Date Code Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 11 RK817 Datasheet 2.3 Dimension Rev 1.01 Fig. 2-1QFN687mm X 7mm DESCRIPTION TOTAL THICKNESS STAND OFF MOLD THICKNESS MATERIAL THICKNESS PACKAGE SIZE EP SIZE LEAD LENGTH LEAD PITCH LEAD WIDTH LEAD OSITION OFFSET LEAD COPLANARITY PACKAGE EDGE PROFILE MOLD FLATNESS EP POSITION OFFSET SYMBOL A A1 A2 A3 D E D1 E1 L e b aaa bbb ccc ddd eee fff Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. MIN 0.70 0 5.39 5.39 0.30 0.1 MILLIMETER NOM 0.75 0.035 0.55 0.203REF 7BSC 7BSC 5.49 5.49 0.4 0.35BSC 0.15 0.07 0.08 0.10 0.10 0.10 0.05 MAX 0.80 0.05 0.57 5.59 5.59 0.50 0.2 12 RK817 Datasheet Rev 1.01 Note: 1. 2. Coplanarity applies to leads, corner leads and die attach pad. Dimension b applies to metalized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension b should not be measure in that radius area. 2.4 Pin Assignment 68 CLK32K 67 RESETB 66 VCC4 65 SW4 64 FB4 63 SNSN 62 SNSP 61 TS/GPIO 60 GATE/GPIO 59 SYS 58 SYS 57 BAT 56 BAT 55 USB/OTG 54 MIDU/BOOST 53 SW5 52 PWRON SCL 1 SDA 2 LDO7 3 VCC7 4 LDO8 5 LDO9 6 INT 7 FB2 8 SW2 9 VCC2 10 VCC1 11 SW1 12 FB1 13 LRCLK 14 BCLK 15 MCLK 16 SDI 17 QFN68 7×7 ePAD 51 XOUT 50 XIN 49 SLEEP 48 VCC_1P8D 47 GNDREF 46 VREF 45 VCC_RTC 44 VCC_1P8A 43 MIC1P 42 MIC1N 41 HPR_OUT 40 HP_SNS 39 HPL_OUT 38 VCC_CPVDD 37 CPP 36 CPN 35 VCC_CPVSS SDO/PDMDATA 18 PDMCLK 19 LDO3 20 LDO2 21 VCC5 22 LDO1 23 VCC3 24 SW3 25 VBUCK3 26 FB3 27 LDO4 28 LDO5 29 VCC6 30 LDO6 31 SPKP_OUT 32 VCC_SPK_HP 33 SPKN_OUT 34 Fig. 2-2 Pin Assignment QFN7x7-68(Pitch=0.35mm) 2.5 Pinout Number Order PIN NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PIN NAME SCL SDA LDO7 VCC7 LDO8 LDO9 INT FB2 SW2 VCC2 VCC1 SW1 FB1 LRCLK BCLK MCLK SDI SDO/PDMDATA PDMCLK LDO3 PIN DESCRIPTION I2C clock input I2C data input and output(Open drain output) LDO7 output Power supply of LDO7/8/9 LDO8 output LDO9 output Interrupt request pin, open drain Output feedback voltage of buck2 Switching node of buck2 Power supply of buck2 Power supply of buck1 Switching node of buck1 Output feedback voltage of buck1 The I2S framing clock The I2S bit clock The I2S main clock input pin The I2S DAC input data The I2S ADC output data/PDM Data for the DSADC PDM CLK for the DSADC OUTPUT LDO3 output Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 13 RK817 Datasheet Rev 1.01 PIN NO 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56,57 58,59 60 61 62 63 64 65 66 PIN NAME LDO2 VCC5 LDO1 VCC3 SW3 VBUCK3 FB3 LDO4 LDO5 VCC6 LDO6 SPKP_OUT VCC_SPK_HP SPKN_OUT VCC_CPVSS CPN CPP VCC_CPVDD HPL_OUT HP_SNS HPR_OUT MICIN MICIP VCC_1P8A VCC_RTC VREF GNDREF VCC_1P8D SLEEP XIN XOUT PWRON SW5 MIDU/BOOST USB/OTG BAT SYS GATE/GPIO TS/GPIO SNSP SNSN FB4 SW4 VCC4 PIN DESCRIPTION LDO2 output Power supply of LDO1/2/3 LDO1 output Power supply of buck3 Switching node of buck3 Output voltage of buck3 Output feedback voltage of buck3 LDO4 output, internal power supply for I2S interface(Pin14~Pin19) LDO5 output Power supply of LDO4/5/6 LDO6 output Positive speaker driver output Power supply for speaker and head phone Negative speaker driver output. Negative power supply for the headphone Negative switching node of the charger pump Positive switching node of the charger pump. Positive power supply for the headphone Left channel output of the headphone Reference ground for the headphone Right channel output of the headphone Negative input of the Microphone Positive input of the Microphone Power supply for internal 1.8V analog circuit Power supply filter Internal reference voltage Reference ground Power supply for internal 1.8V digital circuit Sleep mode control input 32.768KHz crystal oscillator input 32.768KHz crystal oscillator output Power on key input, active low, internal 17k resistor pull high to VCC_RTC Switching node of charger/boost Middle point of USB power supply / boost output USB power supply/OTG output Positive battery terminal DC-DC regulator output to power the system load and charge the battery Control the external PMOS to reduce the conduction resistance or GPIO function by register setting Connect the thermistor from this pin to ground. Or it can be used as an analog input pin of internal ADC if the control bit is set to ADC function or GPIO function by register setting Bat charging and discharging sense current positive pin Bat charging and discharging sense current negative pin Output feedback voltage of buck4 Switching node of buck4 Power supply of buck4 Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 14 RK817 Datasheet PIN NO 67 68 Exposed pad PIN NAME RESETB CLK32K Exposed ground PIN DESCRIPTION Reset pin after power on, active low; 32.768KHz clock output, open drain Ground Rev 1.01 Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 15 RK817 Datasheet Rev 1.01 Chapter 3 Electrical Characteristics 3.1 Absolute Maximum Ratings Parameter Voltage range on pins USB/OTG, MIDU/BOOST, SWx, VCC1~7,VCC_RTC,VCC_SPK_HP,LDOx, SYS, BAT, FBx,VBUCK3,SPKP_OUT,SPKN_OUT Voltage range on pin CLK32K,RESETB, SLEEP,SCL,SDA,INT,PWRON,XIN,SOUT, TS/GPIO,GATE/GPIO, Voltage range on pins LRCLK,BCLK,MCLK,SDI,SDO/PDMCLK,PDMCLK, Voltage range on pins SNSP,SNSN,VREF,VCC_1P8D,VCC_1P8A,MIC1N,MIC1P Voltage range on pins HP_SNS,HPR_OUT,HPL_OUT Voltage range on pins VCC_CPVDD,CPP Voltage range on pins VCC_CPVSS,CPN Storage temperature range, TS Min -0.3 -0.3 -0.3 -0.2 -2.7 -0.3 -2.7 -40 Max 6.5 6.5 6.5 1.98 2.7 2.7 0.3 150 Units V V V V V V V Operating temperature range, TJ -40 125 Maximum Soldering Temperature, TSOLDER 300 Note Exposure to the conditions exceeded absolute maximum ratings may cause the permanent damages and affect the reliability and safety of both device and systems using the device. The functional operations cannot be guaranteed beyond specified values in the recommended conditions. 3.2 Recommended Operating Conditions Parameter Voltage range on pins USB/OTG Power Dissipation Min 4 TYP 5 Max 5.5 2 Units V W 3.3 DC Characteristics Test conditions: USB=5.0V,TA=25°C for typical values, unless otherwise noted. PARAMETERS USB INPUT USB Operating Range USB Input Current Limit USB input VoltageLimit CHARGER Charge current A/D CONVERTER Voltage measuring ADC resolution SYMBOL CONDITION VUSB IUSB Default Max current 0.1V step default=4.4V ICC default=2A MIN 3.8 400 2.8 4 0.5 TYP 5 450 3 MAX UNIT 5.5 V 500 mA 3.2 A 4.7 V 3.5 A 12 bits Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 16 RK817 Datasheet PARAMETERS SYMBOL CONDITION Range of USB/OTG voltage measurement Range of BAT voltage measurement Range of SYS voltage measurement Range of TS voltage measurement Current measuring ADC resolution Range of Current ADC measurement SYS INPUT BAT to SYS Resistance ISYS=200mA , VBAT=4.2V BAT to SYS Current Limit IBATLIM 0.5A step,default=3.5A SYS short CH1BUCK DC-DC CONVERTER(BUCK1) Input supply voltage range Voltage Adjustable Range, 7bit Rated output current Conversion Efficiency(Vin=3.8V,Vout=1V) Iout=2.5A VINPUT1 VFB1 IMAX1 Step=12.5mV(0.5 V< VFB1<1.5) Step=100mV(1.5 V< VFB1<2.4) Iout=0.3A CH2BUCK DC-DC CONVERTER(BUCK2) Input supply voltage range Voltage Adjustable Range, 7bit Rated output current Conversion Efficiency(Vin=3.8V,Vout=1V) Iout=2.5A VINPUT2 VFB2 IMAX2 Step=12.5mV(0.5 V< VFB2<1.5) Step=100mV(1.5 V< VFB2<2.4) Iout=0.3A CH3BUCK DC-DC CONVERTER(BUCK3) Input supply voltage range Feedback Voltage, Default Voltage Adjustable Range, 7bit Rated output current Conversion Efficiency(Vin=3.8V,Vout=1.5V ) Iout=1.5A VINPUT3 VFB3(Default) VFB3 IMAX3 Selection of external resistor divider Step=12.5mV(0.5 V< VFB3<1.5) Step=100mV(1.5 V<VFB3<2.4) Selection of internal resistor divider Iout=0.3A MIN 1 0 1 0 -56.25 2 2.7 0.5 2.7 0.5 2.7 0.784 0.5 TYP 15 Rev 1.01 MAX 6 UNIT V 4.6 V 6 V 1.2 V bits 56.25 mV 0.08 0.12 4 200 A mA 5.5 V 2.4 V 2.5 A 70 % 85 5.5 V 2.4 V 2.5 A 70 % 85 5.5 V 0.8 0.816 V 2.4 V 1.5 A 80 % 88 Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 17 RK817 Datasheet PARAMETERS SYMBOL CONDITION CH4BUCK DC-DC CONVERTER(BUCK4) Input supply voltage range Voltage Adjustable Range, 7bit Rated output current Conversion Efficiency, (Vin=3.8V,Vout=3.3V) Iout=1 .5A Iout=300mA VINPUT4 VFB4 IMAX4 Step=12.5mV(0.5 V< VFB4<1.5) Step=100mV(1.5 V< VFB4<3.4) CH5BOOST DC-DC CONVERTER (BOOST) Input supply voltage range Output Voltage Voltage, Default Rated output current CH6LDO1 VINPUT5 VFB5 VFB5(Default) IMAX5 Step=0.1v,default =5v Input supply voltage range VOUT Rated output current CH7LDO2 VINPUT6 VOUT6 IMAX6 Step=25mV VINPUT6=3.6V, VOUT6=3.3V RegLDO1_MAX=1 VINPUT6=2V, VOUT6=1.8V Input supply voltage range VOUT Rated output current CH8LDO3 VINPUT7 VOUT7 IMAX7 Step=25mV VINPUT7=3.6V, VOUT7=3.3V RegLDO2_MAX=1 VINPUT7=2V, VOUT7=1.8V Input supply voltage range VOUT Power Supply Reject Ratio (f = 10kHz, VOUT9=1.1V) Rated output current CH9 LDO4 VINPUT8 VOUT8 PSRR8 IMAX8 Step=25mV VINPUT8=3.6V, VOUT8=3.3V RegLDO3_MAX=1 VINPUT8=2V, VOUT8=1.8V Input supply voltage range VOUT Rated output current CH10LDO5 VINPUT9 VOUT9 IMAX9 Step=25mV VINPUT9=3.6V, VOUT9=3.3V RegLDO4_MAX=1 VINPUT9=2V, VOUT9=1.8V Input supply voltage range VOUT Rated output current CH11LDO6 VINPUT10 VOUT10 IMAX10 Step=25mV VINPUT10=3.6V,VOUT 10=3.3V RegLDO5_MAX=1 VINPUT10=2V, VOUT10=1.8V Input supply voltage range VINPUT11 MIN 2.7 0.5 2.7 4.7 4.90 2 0.6 2 0.6 2 0.6 2 0.6 2 0.6 2 Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. TYP 1.5 85 95 5.0 1.5 400 200 400 200 65 100 100 400 200 400 200 Rev 1.01 MAX UNIT 5.5 V 3.4 V A % 4.4 V 5.4 V 5.10 V A 5.5 V 3.4 V mA mA 5.5 V 3.4 V mA mA 5.5 V 3.4 V dB mA mA 5.5 V 3.4 V mA mA 5.5 V 3.4 V mA mA 5.5 V 18 RK817 Datasheet PARAMETERS VOUT Rated output current CH12LDO7 Input supply voltage range VOUT Rated output current CH13LDO8 Input supply voltage range VOUT Rated output current CH14LDO9 Input supply voltage range VOUT Rated output current CH15OTG Input supply voltage range Rdson_OTG Rated output current ClassD Audio PA Input supply voltage range THD+N RMS Power PSRR Output Offset Voltage Noise Level Efficiency SYMBOL VOUT11 IMAX11 CONDITION Step=25mV VINPUT11=3.6V, VOUT11=3.3V RegLDO6_MAX=1 VINPUT11=2V, VOUT11=1.8V MIN 0.6 VINPUT12 2 VOUT12 Step=25mV 0.6 IMAX12 VINPUT12=3.6V, VOUT12=3.3V RegLDO7_MAX=1 VINPUT12=2V, VOUT12=1.8V VINPUT13 2 VOUT13 Step=25mV 0.6 IMAX13 VINPUT13=3.6V, VOUT13=3.3V RegLDO8_MAX=1 VINPUT13=2V, VOUT13=1.8V VINPUT14 2 VOUT14 Step=25mV 0.6 IMAX14 VINPUT14=3.6V, VOUT14=3.3V RegLDO9_MAX=1 VINPUT14=2V, VOUT14=1.8V VINPUT15 IMAX15 4.7 VINPUT14 VCC_SPK_HP 2.7 1KHz, Po=0.4Wrms, VCC_SPK_HP =3.8V 8 ohm load, VCC_SPK_HP =3.8V, THD+N=1% 8 ohm load, VCC_SPK_HP =5V, THD+N=1% 8 ohm load, VCC_SPK_HP =5V, THD+N=10% 217Hz, VCC_SPK_HP =200mVpk- pk+3.8V, VCC_SPK_HP =3.8V VCC_SPK_HP =3.8V 0dB Gain, 8ohm, A-weighted VCC_SPK_HP =3.8V,0.4W,8ohm with 68uH, 1KHz TYP 400 200 400 200 400 200 400 200 90 1500 0.1 700 1100 1300 65 +/- 15 100 88 Rev 1.01 MAX 3.4 UNIT V mA mA 5.5 V 3.4 V mA mA 5.5 V 3.4 V mA mA 5.5 V 3.4 V mA mA 5.4 V mohm mA 5.5 V % mW mW mW dB mV uV % Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 19 RK817 Datasheet PARAMETERS Quiescent current SYMBOL DAC to Head phone outputs Full scale output level Signal to Noise Ratio SNR Total Harmonic Distortion + Noise ADC stereo input Full sale input voltage SNR THD+N THD+N I2C interface (7bits I2C address is 0x20) SCL clock frequency fSCL LOGIC INPUT Input LOW-Level Voltage VIL Input HIGH-Level Voltage: VIH1 LRCLK,BCLK,MCLK,SDI,PDMCL K Input HIGH-Level Voltage: VIH2 SCL,SDA,SLEEP,PWRON,TS/GPI O,GATE/GPIO,RESETB LOGIC OUTPUT LOW-Level Output Voltage, VOL 3.0 mA sink current HIGH-Level Output Voltage, VOH1 3.0 mA source current: LRCLK,BCLK,SDO/PDMDATA HIGH-Level Output Voltage, VOH2 3.0 mA source current: TS/GPIO,GATE/GPIO OPEN DRAIN OUTPUT PIN CLK32K,RESETB,INT,SDA CONDITION No load, VCC_SPK_HP =3.8 RL=32ohm RL=300ohm A-weighted RL=32ohm- 60dBFS Fs=48KHz A-weighted RL=32ohm - 3dBFS Fs=48KHz Vpp A-weighted60dBFS,Fs=48KH z A-weighted 997Hz -3dBFS Differential input signal, Fs=48KHz MIN LDO4* 0.7 VCC_1P 8D*0.7 LDO40.4 VCC_RT C-0.4 TYP 4 0.5 0.8 97 -75 1 88 -75 Rev 1.01 MAX UNIT mA Vrms Vrms dB dB V dB dB 1000 KHz 0.4 V VCC_RT V C VCC_RT V C 0.4 V LDO4 V V VCC_RT V Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 20 RK817 Datasheet Rev 1.01 Chapter 4 Function Description 4.1 POWER UP/POWER DOWN The RK817 can be powered by either a battery, or an external power supply through the USB port. When the PMIC is powered by a battery only, pressing the PWRON key powers up the PMIC. All the power channels start up at the default output voltages with a preset power up sequence, which has 2mS intervals between the channels. When the power up process is done, the RESETB turns to high logic level to inform the processor that all the power rails are up and stable. And now the processor can communicate with the PMIC to re-configure the output voltage of each power channel if needed. To power down the PMIC, the processor needs to issue a "power down" signal through the I2C interface. Upon receiving the power down signal, the PMIC first saves all the information on the existing states, and then switches the RESETB to low logic level. At this point, the power channels start to be turned off one after another with the power down sequence. If for any reason the processor fails to issue the power down signal, the PMIC can be powered off by "pressing and holding" the PWRON key. In a case where a battery is the sole power supply and the PMIC is in off state, when an external power supply is plugged into the USB, the PMIC will first check to see if this is a valid power supply. If the power supply from the USB is valid, then the power channels are turned on and the battery is charged. 4.2 SWITCHING CHARGER The RK817 has integrated a switch mode charger, which provides the functions like trickle current charging, constant current charging, constant voltage charging, charging termination, automatic recharging, battery temperature monitoring, charging timer and thermal feedback protection. The values of constant current and constant voltage charging can be set through I2C interface. The input average current limit function allows as large as possible a charging current to be used without having to worry about the input current exceeding the maximum current allowed by the USB port. The input current limits can be configured through I2C interface. For example, when an USB port is used as the input, the input current limit can be configured to either 450mA, or 850mA, to meet the requirements of USB2.0 and USB3.0 respectively. The charger also has a timer function which sets the maximum charging time for trickle, constant current and constant voltage charging, respectively. If the charging does not complete when a preset maximum charging time is reached, the charging is terminated. The battery temperature can be monitored through the TS pin. A battery typically has a thermistor inside. The RK817 sinks a constant current into the thermistor and senses the voltage across the thermistor through an internal ADC. A safe charging temperature range is preset in the PMIC. The charging can proceed normally if the battery temperature falls within the preset range. If, however, the battery temperature goes either above the upper limit or below the lower limit of the preset range, the charging will pause until the battery temperature goes back in the preset range. If the value of the available thermistor is either too large or too small, a normal resistor can be connected in series or in parallel with the thermistor so that the sensed voltage fits the ADC's input range. During Charging, Vsyswill be set to 3.6V when the battery voltage is below 3.6V. This design is to guarantee that when an external power supply is plugged into the USB port to charge the battery while the battery voltage is low, the Vsys is already at 3.6V, which allows the PMIC to start up quickly without having to wait for the Vsys ramping up. Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 21 RK817 Datasheet Rev 1.01 4.3 POWER PATH MANAGEMENT A power path management function is integrated in the RK817, which, together with the accurate input current limit function, can provide intelligent power path control. In a power path control process, the PMIC gives the outputs, or the system loads, the highest priority of using the input power. The battery is getting charged only if the input power is greater than the output power required by the system loads. The intelligent power path control function automatically reduces the charging current when the output power required by the loads increases. In an extreme case where the required output power is greater than the input power, the charging current will be cut off and the battery will join the input power supply to provide power to the load. This is how the intelligent power path control works: As the system power loading increases, the PMIC will draw more input current from the power supply to meet the output power requirement while keep the charging current unchanged. If the system power loading continues to increase to the point where the input current limit is reached, then the PMIC will lower the charging current so that enough power still goes to the load. If the system power loading further increases and due to the input current limit, the input power can not meet the output power requirement, then the battery will start to discharge to supply power to the load together with the USB power supply. If for some reason the USB is unplugged, the battery will automatically switched in to take over the USB power supply and provide full power to the load. The wide power path loop bandwidth allows all the above mentioned power path switching transient to be quick and seamless and therefore no overshoot and notch occur at the system and output voltages. To minimize the loss from the voltage drop along the current path when the battery is charged or discharged, a 100m MOSFET is integrated in the RK817 to serve as a control switch as well as the power switch of the switching mode battery charger. 4.4 THERMAL FOLDBACK Generally speaking, the higher the operating junction temperature is, the shorter the chip's life time. Therefore, keeping the operating junction temperature as low as possible is one of the keys in reliability design. The RK817 provides a thermal feedback protection function for charging process. When the die temperature reaches a preset value, the PMIC will lower the charging current so as to keep the die temperature within an appropriate range. The life time of the PMIC equipped with this function can be reliably prolonged and no overheat damage will occur. 4.5 BATTERY FUEL GAUGE The RK817 provides an accurate battery fuel gauge. A 12-bit battery voltage ADC and a 15-bit battery current ADC are integrated in the RK817 to collect the information on the battery, such as battery voltage, charging/discharging status, battery temperature, etc. Using the proprietary algorithms and the information collected by the ADC, the battery fuel gauge can accurately calculate the battery capacity based on the charging/discharging characteristics of the battery preloaded in the system. The gauge then sends the battery capacity information to the processor through the I2C interface. 4.6 BUCK CONVERTERS The RK817 provides four high current synchronous buck converters, which deliver up to 2.5A, 2.5A, 1.5A and 1.5A, respectively. An enhanced COT architecture is used, which improves the transient response significantly. All output voltages can be adjusted dynamically during operation through DVS (Dynamic Voltage Scaling), which guarantees a linear and gradual voltage ramping up and down. A complete set of protection functions, such as short circuit protection, is implemented in the buck converters too. Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 22 RK817 Datasheet Rev 1.01 The key parameters such as operating mode, output voltage, DVS change rate, and output current limit can be configured through the I2C interface. 4.7 BOOST CONVERTER The synchronous boost converter has 1.5A current capability and is used to power the OTG. The OTG has a built-in current limiting switch, which can effectively protect the boost converter from being damaged if a short circuit occurs at the OTG port. As the USB input port and the OTG output port share a same pin, when the USB port is being used as a power supply and charging the battery, the OTG switch is forbidden to be turned on. Only when there is no external power supply plugged into the USB port, can the OTG be turned on and serve as a power supply. The key parameters such as operating mode, output voltage, and output current limit can be configured through the I2C interface. 4.8 LOW DROPOUT REGULATORS (LDOS) The RK817 also integrates nine LDOs, with 8 LDOs (Ch6, Ch7, Ch9 ~Ch14) capable of providing up to 400mA and one LDO (CH8 ) providing maximum 100mA. The LDO on CH8 is a low noise, high PSRR LDO . The parameters such as output voltage in the different operating modes can be adjusted through the I2C interface. 4.9 REAL TIME CLOCK (RTC) The RK817 integrates a crystal oscillator buffer and a real time clock (RTC). The buffer works with an external 32.768kHz crystal oscillator. With the RTC function, the PMIC provides second/minute/hour/day/month/year information, alarm wake up as well as time calibration. The RK817 provides one channel of 32.768kHz clocks with open drain outputs, where it is default on and is controlled through I2C interface. 4.10 RC OSCILLATOR The RK817 integrates an RC oscillator. If the external crystal oscillator is not connected, the chip will be driven by the internal RC oscillator. Without external crystal oscillator , the system costs can be saved, but the RTC and the fuel gauge will be inaccurate. 4.11 I2S interface The RK817 supports I2S for the digital audio data interface. The I2S/PCM audio digital interface is used to input data to a stereo DAC or output data from a stereo ADC. The I2S/PCM audio interface can be configured to Master mode or Slave mode. In Master Mode, BCLK and LRCLK are configured as output, but MCLK is fixed as input. In Slave Mode, BCLK and LRCLK are configured as input, and the MCLK is still as input. 4.12 Audio CODEC The RK817 integrates a high performance stereo ADC and a high performance stereo DAC. The audio recording path is composed of MIC_PGA and audio ADC. 4.13 Head Phone driver The RK817 integrates a stereo output and with cap-free type headphone amplifier. It doesn't need to connect external capacitance, and can connect to earphone device directly. Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 23 RK817 Datasheet Rev 1.01 4.14 ClassD driver The RK817 integrates a high efficiency stereo Class-D type amplifier capable of delivering 1.3W of power on an 8ohm BTL load from a 5V power supply. It integrates over-current protection. 4.15 POWER SEQUENCE BUCK1 BUCK2 BUCK3 BUCK4 BOOST LDO1 LDO2 LDO3 LDO4 LDO5 LDO6 Range of output voltage 0.5V-2.4V 0.5V-2.4V X(external divided resistor) Or 0.5V-2.4v(internal divided resistor) 0.5V-3.4V 4.7V-5.4V 0.6V-3.4V 0.6V-3.4V 0.6V-3.4V 0.6V-3.4V 0.6V-3.4V 0.6V-3.4V Maximum output current 2.5A 2.5A RK817-1 Default voltage 1.1V 1.1V Start up sequence 1 1 1.5A x 3 1.5A 3.0V 4 1.5A 5.0V OFF 400mA 1.0V 2 400mA 1.8V 2 400mA 1.0V 1 100mA 3.0V 4 400mA 3.0V 4 400mA 3.0V 4 LDO7 LDO8 0.6V-3.4V 0.6V-3.4V 400mA 2.8V OFF 400mA 1.8V OFF LDO9 0.6V-3.4V 400mA 1.5V OFF OTG Equals to BOOST 1.5A 5.0V OFF Table 4-1Power up/down sequence(x:BUCK3 voltage determined by external divided resistor) Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 24 RK817 Datasheet Chapter 5 Register Description 5.1 Register Summary Name RTC_SECONDS RTC_MINUTES RTC_HOURS RTC_DAYS RTC_MONTHS RTC_YEARS RTC_WEEKS RTC_ALARM_SECONDS RTC_ALARM_MINUTES RTC_ALARM_HOURS RTC_ALARM_DAYS RTC_ALARM_MONTHS RTC_ALARM_YEARS RTC_RTC_CTRL RTC_RTC_STATUS RTC_RTC_INT RTC_RTC_COMP_LSB RTC_RTC_COMP_MSB CODEC_DTOP_VUCTL CODEC_DTOP_VUCTIME CODEC_DTOP_LPT_SRST CODEC_DTOP_DIGEN_CLKE CODEC_AREF_RTCFG1 CODEC_AADC_CFG0 CODEC_DADC_VOLL CODEC_DADC_VOLR CODEC_DADC_SR_ACL0 CODEC_DADC_ALC1 CODEC_DADC_ALC2 CODEC_DADC_NG CODEC_DADC_HPF CODEC_DADC_RVOLL CODEC_DADC_RVOLR CODEC_AMIC_CFG0 CODEC_AMIC_CFG1 CODEC_DMIC_PGA_GAIN CODEC_DMIC_LMT1 CODEC_DMIC_LMT2 CODEC_DMIC_NG1 Offset Size 0x0000 B 0x0001 B 0x0002 B 0x0003 B 0x0004 B 0x0005 B 0x0006 B 0x0007 B 0x0008 B 0x0009 B 0x000a B 0x000b B 0x000c B 0x000d B 0x000e B 0x000f B 0x0010 B 0x0011 B 0x0012 B 0x0013 B 0x0014 B 0x0015 B 0x0017 B 0x0018 B 0x001a B 0x001b B 0x001e B 0x001f B 0x0020 B 0x0021 B 0x0022 B 0x0023 B 0x0024 B 0x0027 B 0x0028 B 0x0029 B 0x002a B 0x002b B 0x002c B Reset Value 0x00 0x00 0x09 0x04 0x08 0x17 0x05 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x82 0x00 0x00 0x00 0x03 0x00 0x00 0x00 0x06 0xc8 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0x70 0x00 0x66 0x00 0x00 0x00 Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. Rev 1.01 Description 25 RK817 Datasheet Name CODEC_DMIC_NG2 CODEC_ADAC_CFG1 CODEC_DDAC_POPD_DACST CODEC_DDAC_VOLL CODEC_DDAC_VOLR CODEC_DDAC_SR_LMT0 CODEC_DDAC_LMT1 CODEC_DDAC_LMT2 CODEC_DDAC_MUTE_MIXCTL CODEC_DDAC_RVOLL CODEC_DDAC_RVOLR CODEC_AHP_ANTI0 CODEC_AHP_ANTI1 CODEC_AHP_CFG0 CODEC_AHP_CFG1 CODEC_AHP_CP CODEC_ACLASSD_CFG1 CODEC_ACLASSD_CFG2 CODEC_APLL_CFG0 CODEC_APLL_CFG1 CODEC_APLL_CFG2 CODEC_APLL_CFG3 CODEC_APLL_CFG4 CODEC_APLL_CFG5 CODEC_DI2S_CKM CODEC_DI2S_RSD CODEC_DI2S_RXCR1 CODEC_DI2S_RXCR2 CODEC_DI2S_RXCMD_TSD CODEC_DI2S_TXCR1 CODEC_DI2S_TXCR2 CODEC_DI2S_TXCR3_TXCMD gas_gauge_ADC_CONFIG0 gas_gauge_ADC_CONFIG1 gas_gauge_GG_CON gas_gauge_GG_STS gas_gauge_RELAX_THRE_H gas_gauge_RELAX_THRE_L gas_gauge_RELAX_VOL1_H gas_gauge_RELAX_VOL1_L gas_gauge_RELAX_VOL2_H gas_gauge_RELAX_VOL2_L gas_gauge_RELAX_CUR1_H Offset Size 0x002d B 0x002f B 0x0030 B 0x0031 B 0x0032 B 0x0035 B 0x0036 B 0x0037 B 0x0038 B 0x0039 B 0x003a B 0x003b B 0x003c B 0x003d B 0x003e B 0x003f B 0x0040 B 0x0041 B 0x0042 B 0x0043 B 0x0044 B 0x0045 B 0x0046 B 0x0047 B 0x0048 B 0x0049 B 0x004a B 0x004b B 0x004c B 0x004d B 0x004e B 0x004f B 0x0050 B 0x0055 B 0x0056 B 0x0057 B 0x0058 B 0x0059 B 0x005a B 0x005b B 0x005c B 0x005d B 0x005e B Reset Value 0x00 0x07 0x82 0x00 0x00 0x00 0x00 0x00 0xa0 0xff 0xff 0x00 0x00 0xe0 0x1f 0x09 0x69 0x44 0x04 0x00 0x30 0x19 0x65 0x01 0x01 0x00 0x00 0x17 0x00 0x00 0x17 0x00 0x8c 0x30 0x44 0x00 0x00 0x60 0x00 0x00 0x00 0x00 0x00 Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. Rev 1.01 Description 26 RK817 Datasheet Name gas_gauge_RELAX_CUR1_L gas_gauge_RELAX_CUR2_H gas_gauge_RELAX_CUR2_L gas_gauge_OCV_THRE_VOL gas_gauge_OCV_VOL_H gas_gauge_OCV_VOL_L gas_gauge_OCV_VOL0_H gas_gauge_OCV_VOL0_L gas_gauge_OCV_CUR_H gas_gauge_OCV_CUR_L gas_gauge_OCV_CUR0_H gas_gauge_OCV_CUR0_L gas_gauge_PWRON_VOL_H gas_gauge_PWRON_VOL_L gas_gauge_PWRON_CUR_H gas_gauge_PWRON_CUR_L gas_gauge_OFF_CNT gas_gauge_Q_INIT_H3 gas_gauge_Q_INIT_H2 gas_gauge_Q_INIT_L1 gas_gauge_Q_INIT_L0 gas_gauge_Q_PRES_H3 gas_gauge_Q_PRES_H2 gas_gauge_Q_PRES_L1 gas_gauge_Q_PRES_L0 gas_gauge_BAT_VOL_H gas_gauge_BAT_VOL_L gas_gauge_BAT_CUR_H gas_gauge_BAT_CUR gas_gauge_BAT_TS_H gas_gauge_BAT_TS_L gas_gauge_USB_VOL_H gas_gauge_USB_VOL_L gas_gauge_SYS_VOL_H gas_gauge_SYS_VOL_L gas_gauge_Q_MAX_H3 gas_gauge_Q_MAX_H2 gas_gauge_Q_MAX_L1 gas_gauge_Q_MAX_L0 gas_gauge_Q_TERM_H3 gas_gauge_Q_TERM_H2 gas_gauge_Q_TERM_L1 gas_gauge_Q_TERM_L0 Offset Size 0x005f B 0x0060 B 0x0061 B 0x0062 B 0x0063 B 0x0064 B 0x0065 B 0x0066 B 0x0067 B 0x0068 B 0x0069 B 0x006a B 0x006b B 0x006c B 0x006d B 0x006e B 0x006f B 0x0070 B 0x0071 B 0x0072 B 0x0073 B 0x0074 B 0x0075 B 0x0076 B 0x0077 B 0x0078 B 0x0079 B 0x007a B 0x007b B 0x007c B 0x007d B 0x007e B 0x007f B 0x0080 B 0x0081 B 0x0082 B 0x0083 B 0x0084 B 0x0085 B 0x0086 B 0x0087 B 0x0088 B 0x0089 B Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. Rev 1.01 Description 27 RK817 Datasheet Name Offset Size gas_gauge_Q_OCV_H3 0x008a B gas_gauge_Q_OCV_H2 0x008b B gas_gauge_Q_OCV_L1 0x008c B gas_gauge_Q_OCV_L0 0x008d B gas_gauge_OCV_CNT 0x008e B gas_gauge_SLEEP_CON_SAMP 0x008f B _CUR_H gas_gauge_SLEEP_CON_SAMP 0x0090 B _CUR gas_gauge_CAL_OFFSET_H 0x0091 B gas_gauge_CAL_OFFSET_L 0x0092 B gas_gauge_VCALIB0_H 0x0093 B gas_gauge_VCALIB0_L 0x0094 B gas_gauge_VCALIB1_H 0x0095 B gas_gauge_VCALIB1_L 0x0096 B gas_gauge_IOFFSET_H 0x0097 B gas_gauge_IOFFSET_L 0x0098 B gas_gauge_BAT_R0 0x0099 B gas_gauge_BAT_R1 0x009a B gas_gauge_BAT_R2 0x009b B gas_gauge_BAT_R3 0x009c B gas_gauge_DATA0 0x009d B gas_gauge_DATA1 0x009e B gas_gauge_DATA2 0x009f B gas_gauge_DATA3 0x00a0 B gas_gauge_DATA4 0x00a1 B gas_gauge_DATA5 0x00a2 B gas_gauge_DATA6 0x00a3 B gas_gauge_DATA7 0x00a4 B gas_gauge_DATA8 0x00a5 B gas_gauge_DATA9 0x00a6 B gas_gauge_DATA10 0x00a7 B gas_gauge_DATA11 0x00a8 B gas_gauge_VOL_ADC_B3 0x00a9 B gas_gauge_VOL_ADC_B2 0x00aa B gas_gauge_VOL_ADC_B1 0x00ab B gas_gauge_VOL_ADC_B_7_0 0x00ac B gas_gauge_CUR_ADC_K3 0x00ad B gas_gauge_CUR_ADC_K2 0x00ae B gas_gauge_CUR_ADC_K1 0x00af B gas_gauge_CUR_ADC_K0 0x00b0 B PMIC_POWER_EN0 0x00b1 B PMIC_POWER_EN1 0x00b2 B Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x60 0x7f 0xff 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x0f 0x0f Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. Rev 1.01 Description 28 RK817 Datasheet Name PMIC_POWER_EN2 PMIC_POWER_EN3 PMIC_POWER_SLP_EN0 PMIC_POWER_SLP_EN1 PMIC_POWER_DISCHRG_EN0 PMIC_POWER_DISCHRG_EN1 PMIC_POWER_CONFIG PMIC_BUCK1_CONFIG PMIC_BUCK1_ON_VSEL PMIC_BUCK1_SLP_VSEL PMIC_BUCK2_CONFIG PMIC_BUCK2_ON_VSEL PMIC_BUCK2_SLP_VSEL PMIC_BUCK3_CONFIG PMIC_BUCK3_ON_VSEL PMIC_BUCK3_SLP_VSEL PMIC_BUCK4_CONFIG PMIC_BUCK4_ON_VSEL PMIC_BUCK4_SLP_VSEL PMIC_BUCK4_CMIN PMIC_LDO1_ON_VSEL PMIC_LDO1_SLP_VSEL PMIC_LDO2_ON_VSEL PMIC_LDO2_SLP_VSEL PMIC_LDO3_ON_VSEL PMIC_LDO3_SLP_VSEL PMIC_LDO4_ON_VSEL PMIC_LDO4_SLP_VSEL PMIC_LDO5_ON_VSEL PMIC_LDO5_SLP_VSEL PMIC_LDO6_ON_VSEL PMIC_LDO6_SLP_VSEL PMIC_LDO7_ON_VSEL PMIC_LDO7_SLP_VSEL PMIC_LDO8_ON_VSEL PMIC_LDO8_SLP_VSEL PMIC_LDO9_ON_VSEL PMIC_LDO9_SLP_VSEL PMIC_BOOST_OTG_CONFIG0 PMIC_BOOST_CONFIG1 PMIC_CHRG_OUT PMIC_CHRG_IN PMIC_CHRG_TERM Offset Size 0x00b3 B 0x00b4 B 0x00b5 B 0x00b6 B 0x00b7 B 0x00b8 B 0x00b9 B 0x00ba B 0x00bb B 0x00bc B 0x00bd B 0x00be B 0x00bf B 0x00c0 B 0x00c1 B 0x00c2 B 0x00c3 B 0x00c4 B 0x00c5 B 0x00c6 B 0x00cc B 0x00cd B 0x00ce B 0x00cf B 0x00d0 B 0x00d1 B 0x00d2 B 0x00d3 B 0x00d4 B 0x00d5 B 0x00d6 B 0x00d7 B 0x00d8 B 0x00d9 B 0x00da B 0x00db B 0x00dc B 0x00dd B 0x00de B 0x00df B 0x00e4 B 0x00e5 B 0x00e6 B Reset Value 0x06 0x00 0x0f 0x6f 0xff 0xff 0x00 0x64 0x28 0x28 0x64 0x28 0x28 0x64 0x50 0x50 0x64 0x62 0x62 0x04 0x6c 0x6c 0x10 0x10 0x6c 0x6c 0x10 0x10 0x30 0x30 0x30 0x30 0x30 0x30 0x6c 0x6c 0x58 0x58 0x0b 0x33 0xa2 0xc8 0xc1 Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. Rev 1.01 Description 29 RK817 Datasheet Rev 1.01 Name PMIC_CHRG_TERM_DIG PMIC_BAT_HTS_TS PMIC_BAT_LTS_TS PMIC_CHRG_TO PMIC_CHRG_STS PMIC_BAT_DISCHRG PMIC_CHIP_NAME PMIC_CHIP_VER PMIC_OTP_VER PMIC_SYS_STS PMIC_SYS_CFG0 PMIC_SYS_CFG1 PMIC_SYS_CFG2 PMIC_SYS_CFG3 PMIC_ON_SOURCE PMIC_OFF_SOURCE PMIC_PWRON_KEY PMIC_INT_STS0 PMIC_INT_MSK0 PMIC_INT_STS1 PMIC_INT_MSK1 PMIC_INT_STS2 PMIC_INT_MSK2 PMIC_GPIO_INT_CONFIG Offset Size 0x00e7 B 0x00e8 B 0x00e9 B 0x00ea B 0x00eb B 0x00ec B 0x00ed B 0x00ee B 0x00ef B 0x00f0 B 0x00f1 B 0x00f2 B 0x00f3 B 0x00f4 B 0x00f5 B 0x00f6 B 0x00f7 B 0x00f8 B 0x00f9 B 0x00fa B 0x00fb B 0x00fc B 0x00fd B 0x00fe B Reset Value 0x00 0x00 0xff 0x22 0x00 0x0a 0x81 0x72 0x00 0x00 0x84 0x80 0x00 0x20 0x00 0x00 0x06 0x00 0x00 0x00 0x00 0x00 0x00 0x22 Description Notes:Size:B- Byte (8 bits) access, HW- Half WORD (16 bits) access, W-WORD (32 bits) access 5.2 Register Description RTC_SECONDS Address: Operational Base + offset (0x0000) Bit 7 6:4 3:0 Attr RW RW RW Reset Value Description RESV 0x0 Reserved SEC1 0x0 Set the second digit of the RTC seconds (0- 5) SEC0 0x0 Set the first digit of the RTC seconds (0-9) RTC_MINUTES Address: Operational Base + offset (0x0001) Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 30 RK817 Datasheet Rev 1.01 Bit 7 6:4 3:0 Attr RW RW RW Reset Value Description RESV 0x0 Reserved MIN1 0x0 Set the second digit of the RTC minutes (0- 5) MIN0 0x0 Set the first digit of the RTC minutes (0-9) RTC_HOURS Address: Operational Base + offset (0x0002) Bit 7 6 5:4 3:0 Attr RW RW RW RW Reset Value Description AMPM 0x0 Only used in PM-AM mode, 1: PM. 0:AM RESV 0x0 Reserved HOUR1 0x0 Set the second digit of the RTC hours HOUR0 0x9 Set the first digit of the RTC hours RTC_DAYS Address: Operational Base + offset (0x0003) Bit 7:6 5:4 3:0 Attr RW RW RW Reset Value Description RESV 0x0 Reserved DAY1 0x0 Set the second digit of the RTC days DAY0 0x4 Set the first digit of the RTC days RTC_MONTHS Address: Operational Base + offset (0x0004) Bit 7:5 4 3:0 Attr RW RW RW Reset Value Description RESV 0x0 Reserved MONTH1 0x0 Set the second digit of the RTC months MONTH0 0x8 Set the first digit of the RTC months RTC_YEARS Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 31 RK817 Datasheet Rev 1.01 Address: Operational Base + offset (0x0005) Bit 7:4 3:0 Attr RW RW Reset Value Description YEAR1 0x1 Set the second digit of the RTC years YEAR0 0x7 Set the first digit of the RTC years RTC_WEEKS Address: Operational Base + offset (0x0006) Bit 7:3 2:0 Attr RW RW Reset Value Description 0x00 RESV Reserved WEEK 0x5 Set the second digit of the RTC weeks RTC_ALARM_SECONDS Address: Operational Base + offset (0x0007) Bit 7 6:4 3:0 Attr RW RW RW Reset Value Description RESV 0x0 Reserved ALARM_SEC1 0x0 Set the second digit of the RTC alarm seconds ALARM_SEC0 0x0 Set the first digit of the RTC alarm seconds RTC_ALARM_MINUTES Address: Operational Base + offset (0x0008) Bit 7 6:4 3:0 Attr RW RW RW Reset Value Description RESV 0x0 Reserved ALARM_MIN1 0x0 Set the second digit of the RTC alarm minutes ALARM_MIN0 0x0 Set the first digit of the RTC alarm minutes RTC_ALARM_HOURS Address: Operational Base + offset (0x0009) Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 32 RK817 Datasheet Rev 1.01 Bit 7 6 5:4 3:0 Attr RW RW RW RW Reset Value Description ALARM_PM_AM 0x0 Set alarm PM or AM: only used in PM-AM mode, 1: PM. 0:AM RESV 0x0 Reserved ALARM_HOUR1 0x0 Set the second digit of the RTC alarm hours ALARM_HOUR0 0x0 Set the first digit of the RTC alarm hours RTC_ALARM_DAYS Address: Operational Base + offset (0x000a) Bit 7:6 5:4 3:0 Attr RW RW RW Reset Value Description RESV 0x0 Reserved ALARM_DAY1 0x0 Set the second digit of the RTC alarm days ALARM_DAY0 0x1 Set the first digit of the RTC alarm days RTC_ALARM_MONTHS Address: Operational Base + offset (0x000b) Bit 7:5 4 3:0 Attr RW RW RW Reset Value Description RESV 0x0 Reserved ALARM_MONTH1 0x0 Set the second digit of the RTC alarm months ALARM_MONTH0 0x1 Set the first digit of the RTC alarm months RTC_ALARM_YEARS Address: Operational Base + offset (0x000c) Bit 7:4 3:0 Attr RW RW Reset Value Description ALARM_YEAR1 0x0 Set the second digit of the RTC alarm years ALARM_YEAR0 0x0 Set the first digit of the RTC alarm years RTC_RTC_CTRL Address: Operational Base + offset (0x000d) Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 33 RK817 Datasheet Rev 1.01 Bit 7 6 5 4 3 2 1 0 Attr RW RW RW RW RW RW RW RW Reset Value Description RTC_READ_SEL 0x0 0: Read access directly to dynamic registers 1: Read access to static shadowed registers GET_TIME Rising transition of this register transferred 0x0 dynamic registers into static shadowed registers. SET_32_COUNTER 1: set the 32-kHz counter with COMP_REG 0x0 value. Note: It must only be used when the RTC is frozen. RESV 0x0 Reserved AMPM_MODE 0x0 0: 24 hours mode. 1: 12 hours mode (PM- AM mode) AUTO_COMP 0x0 0: No auto compensation. 1: Auto compensation enabled ROUND_30S When "1" is written, the time is rounded to 0x0 the closest minute in next second. Note: self cleared after rounding (Auto Clr) STOP_RTC 1: RTC is frozen 0: RTC is running. 0x0 Note: RTC_timecan only be changed during RTC frozen. RTC_RTC_STATUS Address: Operational Base + offset (0x000e) Bit 7 6 5 Attr W1C W1C W1C Reset Value Description POWER_UP 0x1 POWER_UP is set by a reset, is cleared by writing "1" in this bit. ALARM Indicates that an alarm interrupt has been generated. 0x0 Note: The alarm interrupt keeps its low level, until the micro-controller write "1" in the ALARM bit EVENT_1D 0x0 One day has occurred Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 34 RK817 Datasheet Rev 1.01 Bit 4 3 2 1 0 Attr W1C W1C W1C RO RW Reset Value Description EVENT_1H 0x0 One hour has occurred EVENT_1M 0x0 One minute has occurred EVENT_1S 0x0 One second has occurred RUN 0: RTC is frozen. 1: RTC is running. 0x1 Note: This bit shows the real state of the RTC. RESV 0x0 Reserved RTC_RTC_INT Address: Operational Base + offset (0x000f) Bit 7:6 5 4 3 2 1:0 Attr RW RW RW RW RW RW Reset Value Description RESV 0x0 Reserved ALARM_EN_PWRON enable the Alarm interrupt to triggle power 0x0 on. 1: enable; 0: disable INT_SLEEP_MASK_EN 1: Mask periodic interrupt while the device is 0x0 in SLEEP mode 0: Normal mode, no interrupt masked. INT_ALARM_EN Enable one interrupt when the alarm value is 0x0 reached 1: Enable 0: Disable INT_TIMER_EN 0x0 1: Enable periodic interrupt; 0: disable periodic interrupt EVERY 0x0 00: every second; 01: every minute; 10: every hour; 11: every day RTC_RTC_COMP_LSB Address: Operational Base + offset (0x0010) Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 35 RK817 Datasheet Rev 1.01 Bit 7:0 Attr RW Reset Value Description RTC_COMP_LSB 0x00 This register contains the number of 32-kHz periods to be added into the 32KHz counter every hour [LSB] RTC_RTC_COMP_MSB Address: Operational Base + offset (0x0011) Bit 7:0 Attr RW Reset Value Description RTC_COMP_MSB 0x00 This register contains the number of 32-kHz periods to be added into the 32KHz counter every hour [MSB] CODEC_DTOP_VUCTL Address: Operational Base + offset (0x0012) Bit 7 6 5 4 3:2 1 Attr RW RW RW RW RW RW Reset Value Description ADC_BYPS ADC volume control bypass 0x0 0:ADC volume control enable 1: ADC volume control bypass DAC_BYPS 0x0 0:DAC volume control enable 1:DAC volume control bypass ADCFade ADC Fade: ADC volume adjust mode 0x0 0:update to new volume immediately; 1:update volume as ADCZDT field describes; DACFade DAC Fade: DAC volume adjust mode 0x0 0:update to new volume immediately; 1:update volume as DACZDT field describes; RESV 0x0 Reserved ADCZDT ADC cross zero detect enable. It works when ADC_BYPS is 0 and ADC_FADE is 1. 0:volume adjusts every sample 0x1 1:volume adjusts only when audio waveform crosses zero or volume-control time-limit condition meets; Note: All codec register reset by `RST'or power down. Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 36 RK817 Datasheet Rev 1.01 Bit 0 Attr RW Reset Value Description DACZDT DAC cross zero detect enable. It works when DAC_BYPS is 0 and DAC_FADE is 1. 0:volume adjusts every sample 0x1 1:volume adjusts only when audio waveform crosses zero or volume-control time-limit condition meets; Note: All codec register reset by `RST'or power down. CODEC_DTOP_VUCTIME Address: Operational Base + offset (0x0013) Bit 7:0 Attr RW Reset Value Description VUCT VUCT: volume control time limit, valid only 0x00 in fade cross zero mode Time limit = VUCT *(1/sample rate) Unit: LRCLK CODEC_DTOP_LPT_SRST Address: Operational Base + offset (0x0014) Bit 7 6 5 4:0 Attr RW RW RW RW Reset Value Description RESV 0x0 Reserved SRST 0x0 soft reset, write 1 to reset read 1: resetting 0: not resetting LP_DET LP_DET: low power detected, valid when DAC automatically power-on and power0x0 down enabled 0:not detected; 1:low power detected; LPT 0x00 LPT: low power detect threshold:power(2,LPT) CODEC_DTOP_DIGEN_CLKE Address: Operational Base + offset (0x0015) Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 37 RK817 Datasheet Bit 7 6 5 4 3 2 1 0 Attr RW RW RW RW RW RW RW RW Reset Value Description ADC_CKE 0x0 ADC clock enable 1:enable; 0:disable; I2STX_CKE 0x0 I2S Tx channel clock enable 1:enable; 0:disable; ADC_EN 0x0 Digital adc channel enable 1:enable; 0:disable; I2STX_EN 0x0 I2S Tx channel enable 1:enable; 0:disable; DAC_CKE 0x0 DAC clock enable 1:enable; 0:disable; I2SRX_CKE 0x0 I2S Rx channel clock enable 1:enable; 0:disable; DAC_EN 0x0 Digital dac channel enable 1:enable; 0:disable; I2SRX_EN 0x0 I2S Rx channel enable 1:enable; 0:disable; Rev 1.01 CODEC_AREF_RTCFG1 Address: Operational Base + offset (0x0017) Bit 7 6 5 4:3 2 Attr RW RW RW RW RW Reset Value Description 0x0 Internal used, don't over write. LDO1P8A_EN_CODEC Enable the LDO 1P8Adefault don't setup. 0x0 For sleep used only. 0:not effect 1:enable REF_ADC_SEL 0x0 Select the ADC reference voltage 0: 1.2V 1: 1.5V VAG_SEL 0x0 Select the VAG voltage 00:0.9V 01:0.72V 10:1.08V 11:1.26V PWD_IBIAS Power down the ibias block in REF_TOP 0x1 0:IBIAS block power on 1:IBIAS block power down Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 38 RK817 Datasheet Rev 1.01 Bit 1 0 Attr RW RW Reset Value Description PWD_VAG_BUF Power down the Vag buffer in REF_TOP 0x1 0:Vag buffer block power on 1:Vag buffer block power down RESV 0x0 Reserved CODEC_AADC_CFG0 Address: Operational Base + offset (0x0018) Bit 7 6 5 4 3 2:0 Attr RW RW RW RW RW RW Reset Value Description ADC_L_PWD Power down ADC left channel 0x1 0: ADC left channel power on 1: ADC left channel power down ADC_R_PWD Power down ADC right channel 0x1 0: ADC right channel power on 1: ADC right channel power down ADC_CLK_EDGE_SEL Select the ADC output data and clock edge relationship 0x0 0: using the ADC falling edge to send the ADC data 1: using the ADC rising edge to send the ADC data RESV 0x0 Reserved ADC_DITH_OFF Disable the dither function of ADC 0x1 0: enable the ADC dither 1:disable the ADC dither ADC_DITH_SEL Select the dither frequency of ADC 000: 1/50 of ADC clock 001: 1/33 of ADC clock 010: 1/20 of ADC clock 0x0 011: 1/15 of ADC clock 100: 1/10 of ADC clock 101: 1/8 of ADC clock 110: 1/6 of ADC clock 111: 1/4 of ADC clock CODEC_DADC_VOLL Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 39 RK817 Datasheet Rev 1.01 Address: Operational Base + offset (0x001a) Bit 7:0 Attr RW Reset Value Description ADCLV ADC path L-channel Digital Volume Register 0db~-95db, 0.375db/step 8'h0: 0db 0x00 8'h1:-0.375db 8'h2:-0.75db 8'h3:-1.125db ... 8'hff:-95db CODEC_DADC_VOLR Address: Operational Base + offset (0x001b) Bit 7:0 Attr RW Reset Value Description ADCRV ADC path R-channel Digital Volume Register 0db~-95db, 0.375db/step 8'h0: 0db 0x00 8'h1:-0.375db 8'h2:-0.75db 8'h3:-1.125db ... 8'hff:-95db CODEC_DADC_SR_ACL0 Address: Operational Base + offset (0x001e) Bit 7 6 5 4 3 Attr RW RW RW RW RW Reset Value Description ALCL ALC L-channel enable: automatic level 0x0 control enable for ADC left channel 0: disable 1:enable ALCR ALC R-channel enable: automatic level 0x0 control enable for ADC right channel 0: disable 1:enable ADC_LV_POL 0x0 ADC path L-channel Digital Volume polarity 0:negative gain; 1:postive gain ADC_RV_POL 0x0 ADC path R-channel Digital Volume polarity 0:negative gain; 1:postive gain RESV 0x0 Reserved Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 40 RK817 Datasheet Rev 1.01 Bit 2:0 Attr RW Reset Value Description ADCSRT ADC sample rate times: sample rate = 8k/11.025k/12k * 0x0 power(2,ADCSRT) note that sample rate base(8K/11.025K/12K) is decided by PLL configuration. CODEC_DADC_ALC1 Address: Operational Base + offset (0x001f) Bit 7:4 3:0 Attr RW RW Reset Value Description ALCARATE 0x0 ALC attack rate =sample rate/( 8*power(2,ALCARATE)) ALCRRATE 0x0 ALC Release rate=sample rate/( 8*power(2,ALCRRATE)) CODEC_DADC_ALC2 Address: Operational Base + offset (0x0020) Bit 7 6:4 3 2:0 Attr RO RW RW RW Reset Value Description NGVALID: noise gate valid status 0x0 0:not in NG status;1: now in NG status; ALCMAX The highest threshold of ALC; 0x0 000~100:0db~-12db,3db/step; 101~111:-18db~-30db,6db/step; RESV 0x0 Reserved ALCMIN The lowest threshold of ALC; 0x0 000~100:0db~-12db,3db/step; 101~111:-18db~-30db,6db/step; CODEC_DADC_NG Address: Operational Base + offset (0x0021) Bit 7 Attr RW Reset Value Description NGCHL: noise gate channel 0x0 0,individual channel(or); 1,both channel(and); Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 41 RK817 Datasheet Rev 1.01 Bit 6 5 4:2 1:0 Attr RW RW RW RW Reset Value Description NGEN: noise gate enable 0x0 0,Noise gate Disable; 1,Noise gate enable; NGBOOST: noise gate boost 0x0 0,Normal noise gate; 1,Boost noise gate; NGGATE: noise gate threshold 0x0 NGBOOST = 0: 000~111(-63~-84,3db/step) NGBOOST = 1: 000~111(-33~-54,3db/step) NGDLY: noise gate delay 0x0 The delay time before the noise gate attacks 00~11:2048~4096~8192~16384 samples CODEC_DADC_HPF Address: Operational Base + offset (0x0022) Bit 7 6 5:4 3:0 Attr RW RW RW RW Reset Value Description HPFL: high pass filter enable for left channel 0x0 0:high pass filter for left channel is disabled 1: high pass filter for left channel is enabled HPFR: high pass filter enable for right channel 0x0 0:high pass filter for right channel is disabled 1: high pass filter for right channel is enabled HPF_CF: high pass filter configure register 0x0 00:3.79Hz; 01:60Hz; 02:243Hz; 03:493Hz RESV 0x0 Reserved CODEC_DADC_RVOLL Address: Operational Base + offset (0x0023) Bit 7:0 Attr RO Reset Value Description ADCRLV 0xff ADC internal gain of left ch CODEC_DADC_RVOLR Address: Operational Base + offset (0x0024) Bit 7:0 Attr RO Reset Value Description ADCRRV 0xff ADC internal gain of right ch CODEC_AMIC_CFG0 Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 42 RK817 Datasheet Rev 1.01 Address: Operational Base + offset (0x0027) Bit 7 6 5 4 3:2 1:0 Attr RW RW RW RW RW RW Reset Value Description MIC_DIFF_EN 0x0 Enable differential mic mode 0:disable 1:enable PWD_MIC MIC Power Down 0x1 0: MIC block power on 1: MIC block power down PWD_PGA_L PGA_L Power Down 0x1 0:PGA_L block power on 1:PGA_L block power down PWD_PGA_R PGA_R Power Down 0x1 0:PGA_R block power on 1:PGA_R block power down MIC_L_BOOST 0x0 Select the gain of left mic input signal 00:0dB, 01:10dB 10:20dB 11:30dB MIC_R_BOOST 0x0 Select the gain of right mic input signal 00:0dB, 01:10dB 10:20dB 11:30dB CODEC_AMIC_CFG1 Address: Operational Base + offset (0x0028) Bit 7 6 5 4 3:2 1:0 Attr RW RW RW RW RW RW Reset Value Description PGA_L_IN_SEL PGA L-channel input select 0x0 0: Positive end of Mic amplifier output 1:internal reference voltage PGA_R_IN_SEL PGA R-channel input select 0x0 0: Negative end of Mic amplifier output 1:internal reference voltage MIC_CHOP_EN 0x0 Enable the chopping function of MIC 0:disable 1:enable PGA_CHOP_EN 0x0 Enable the chopping function of PGA 0:disable 1:enable MIC_CHOP_SEL 0x0 00:200k, 01:400k, 10:800k, 11:Reserved PGA_CHOP_SEL 0x0 00:200k, 01:400k, 10:800k, 11:Reserved Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 43 RK817 Datasheet Rev 1.01 CODEC_DMIC_PGA_GAIN Address: Operational Base + offset (0x0029) Bit 7:4 3:0 Attr RW RW Reset Value Description PGA_L_GAIN Change the gain of PGA block, the value 0x6 changed from -18dB to 27dB. 0000:-18db; 1111:27db, 3db/step PGA_R_GAIN Change the gain of PGA block, the value 0x6 changed from -18dB to 27dB. 0000: -18db; 1111:27db, 3db/step CODEC_DMIC_LMT1 Address: Operational Base + offset (0x002a) Bit 7 6:4 3 2:0 Attr RW RW RW RW Reset Value Description PGA_LMT_EN 0x0 PGA gain limiter enable 0:disable 1:enable MAX_PGA_LMT The highest threshold of LIMITER; 0x0 000~100:0db~-12db,3db/step; 101~111:-18db~-30db,6db/step; RESV 0x0 Reserved MIN_PGA_LMT 0x0 The lowest threshold of LIMITER CODEC_DMIC_LMT2 Address: Operational Base + offset (0x002b) Bit 7:4 3:0 Attr RW RW Reset Value Description ATK_RATE_PGA_LMT LIMITER Attack rate=(power(2,ATK_RATE_PGA_LMT)*(8*clk 0x0 1x)) Clk1x is such as 4.096Mhz,5.6448Mhz,6.144Mhz RLS_RATE_PGA_LMT LIMITER Release rate=(power(2,RLS_RATE_PGA_LMT)*(8*clk 0x0 1x)) Clk1x is such as 4.096Mhz,5.6448Mhz,6.144Mhz Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 44 RK817 Datasheet Rev 1.01 CODEC_DMIC_NG1 Address: Operational Base + offset (0x002c) Bit 7 6 5 4:2 1:0 Attr RW RW RW RW RW Reset Value Description NGCHL_LI 0x0 0:individual channel; 1:both channel; NGEN_LI 0x0 0:Noise gate Disable; 1:Noise gate enable; NGBOOST_LI 0x0 0:Normal noise gate; 1: Boost noise gate; NGGATE_LI NGBOOST_LI = 0: 000~111(-63~- 0x0 84,3db/step) NGBOOST_LI = 1: 000~111(-33~- 54,3db/step) NGDLY_LI The delay time before the noise gate attacks 0x0 00~11:2048~4096~8192~16384, unit: (clk1x * 8) CODEC_DMIC_NG2 Address: Operational Base + offset (0x002d) Bit 7:1 0 Attr RO RO Reset Value Description 0x00 RESV Reserved NGVALID_LI 0x0 Noise gate valid status CODEC_ADAC_CFG1 Address: Operational Base + offset (0x002f) Bit 7 6 5 4 Attr RW RW RW RW Reset Value Description DOUBLE_DACIBIAS 0x0 double DAC internal current resource INC_DAC_SWITCH 0x0 increase the DAC internal switch signal control time STOP_DAC_RSTB 0x0 stop the RSTB clock STOP_DAC_SWITCH 0x0 stop the switch clock in DAC Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 45 RK817 Datasheet Rev 1.01 Bit 3 2 1 0 Attr RW RW RW RW Reset Value Description PWD_DACIBIAS power down the DAC internal current 0x0 resource 0: DACIBIAS powerup 1: DACIBIAS powerdown PWD_DACD Class D DAC power down 0x1 0: Class D DAC power up 1: Class D DAC power down PWD_DACL L channel DAC power down 0x1 0: L channel DAC power up 1: L channel DAC power down PWD_DACR R channel DAC power down 0x1 0: R channel DAC power up 1: R channel DAC power down CODEC_DDAC_POPD_DACST Address: Operational Base + offset (0x0030) Bit 7 6 5 4 3:2 1 Attr RW RW RW RW RW RO Reset Value Description ATCTRL auto-control power on and power down 0x1 0: automatic power control is disabled 1: automatic power control is enabled RESV 0x0 Reserved SMTPO smart power on 0x0 0:smart power on is disabled 1:smart power on is enabled SMTPD smart power down 0x0 0:smart power down is disabled 1:smart power down is enabled RESV 0x0 Reserved DAC_MTST DAC mute status 0x1 0:DAC is not in mute status 1:DAC is in mute status Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 46 RK817 Datasheet Bit 0 Attr RO Reset Value Description DAC_PWRST DAC power status 0x0 0:DAC is powered down 1:DAC is powered on Rev 1.01 CODEC_DDAC_VOLL Address: Operational Base + offset (0x0031) Bit 7:0 Attr RW Reset Value Description DACLV 0x00 DAC path L-channel Digital Volume Register 0db~-95db,0.375db/step CODEC_DDAC_VOLR Address: Operational Base + offset (0x0032) Bit 7:0 Attr RW Reset Value Description DACRV 0x00 DAC path R-channel Digital Volume Register 0db~-95db,0.375db/step CODEC_DDAC_SR_LMT0 Address: Operational Base + offset (0x0035) Bit 7 6 5 4 3 2:0 Attr RW RW RW RW RW RW Reset Value Description LIMEN 0x0 LIMITER enable; 0:disable 1:enable LIMCHL 0x0 0:(left+right)/2 1:independent DAC_LV_POL 0x0 0negative gain; 1:postive gain DAC_RV_POL 0x0 0negative gain; 1:postive gain RESV 0x0 Reserved DACSRT DAC sample rate times 0x0 sample rate = 8k/11.025k/12k * power(2,DACSRT) CODEC_DDAC_LMT1 Address: Operational Base + offset (0x0036) Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 47 RK817 Datasheet Rev 1.01 Bit 7:4 3:0 Attr RW RW Reset Value Description LIMRRATE 0x0 LIMITER Release rate= 8*power(2,LIMRRATE) samples LIMARATE 0x0 LIMITER attack rate=8*power(2,LIMARATE) samples CODEC_DDAC_LMT2 Address: Operational Base + offset (0x0037) Bit 7 6:4 3 2:0 Attr RW RW RW RW Reset Value Description RESV 0x0 Reserved LIMMAX The highest threshold of LIMITER; 0x0 000~100:0db~-12db,3db/step; 101~111:-18db~-30db,6db/step; RESV 0x0 Reserved LIMMIN 0x0 The lowest threshold of LIMITER; CODEC_DDAC_MUTE_MIXCTL Address: Operational Base + offset (0x0038) Bit 7 6:5 4 3 2 1 0 Attr RW RW RW RW RW RW RW Reset Value Description DAC_D_HPF 0x1 0:disable HPF;1:enable HPF; DAC_D_HPF_CF 0x1 00:80HZ; 01:100HZ; 02:120HZ; 03:140HZ CLASS_D_MODE 0x0 1:CLASS D mode, 0:L/R mode CLASSD_MODE_L_SEL 0x0 0(L+R)/2; 1L RESV 0x0 Reserved MIX_ON 0x0 0:mixer disable;1:enable; DACMT DAC mute enable 0x0 0:DAC mute is disabled 1:DAC mute is enable CODEC_DDAC_RVOLL Address: Operational Base + offset (0x0039) Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 48 RK817 Datasheet Rev 1.01 Bit 7:0 Attr RO Reset Value Description DACRLV 0xff DAC internal gain of left ch CODEC_DDAC_RVOLR Address: Operational Base + offset (0x003a) Bit 7:0 Attr RO Reset Value Description DACRRV 0xff DAC internal gain of right ch CODEC_AHP_ANTI0 Address: Operational Base + offset (0x003b) Bit 7:5 4:0 Attr RW RW Reset Value Description RESV 0x0 Reserved 0x00 STEP_CTRL STEP_CTRL for HP power on CODEC_AHP_ANTI1 Address: Operational Base + offset (0x003c) Bit 7:5 4:0 Attr RW RW Reset Value Description RESV 0x0 Reserved 0x00 VOUT_CTRL VOUT_CTRL for HP power on CODEC_AHP_CFG0 Address: Operational Base + offset (0x003d) Bit 7 6 5 4:3 Attr RW RW RW RW Reset Value Description PWD_SOSTAGE 0x1 power down the HP SOSTAGE 0:power up 1:power down PWD_HP_OSTAGE 0x1 power down the HP OSTAGE 0:power up 1:power down PWD_HP_BUF 0x1 power down the HP pre amp stage 0:power up 1:power down INC_HP_AMP 0x0 increase the HP amplitude from 3dB to 9dB, 00:0db 01:3db 10:6db 11: 9db Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 49 RK817 Datasheet Rev 1.01 Bit 2 1:0 Attr RW RW Reset Value Description HP_2STAGE_EN 0x0 Power down the HP two stage opamp 0:disable 1:enable HP_IBIAS_SEL 0x0 HP BIAS current select 00:100% 01:150% 10:200% 11:50% CODEC_AHP_CFG1 Address: Operational Base + offset (0x003e) Bit 7:5 4 3:0 Attr RW RW RW Reset Value Description RESV 0x0 Reserved HP_ANTIPOP_EN 0x1 enable the HP antipop function 0:disable 1:enable HP_ANTIPOP_BIT control the HP antipop gain from -15dB to 0dB 0000: 0dB 0xf 0001:-1dB 0010:-2dB ... 1111:-15dB CODEC_AHP_CP Address: Operational Base + offset (0x003f) Bit 7:6 5 4 3 2 Attr RW RW RW RW RW Reset Value Description RESV 0x0 Reserved HP_CP_CLK_SEL 0x0 0CLK select for head phone charge pump 1MHz :500KHz HP_CP_EN 0x0 HP charge pump enable. 0:disable 1:enable HP_CP_ENDIS_LDO 0x1 HP charge pump discharge ldo enable 0:disable 1:enable HP_CP_HIMAXB 0x0 HP charge pump max current: 0:500mA,1:750mA Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 50 RK817 Datasheet Bit 1:0 Attr RW Reset Value Description HP_CP_VSEL 0x1 HP charge pump voltage select: 00:2.1V,01:2.3V :2.5V,11:2.7V Rev 1.01 CODEC_ACLASSD_CFG1 Address: Operational Base + offset (0x0040) Bit 7 6 5 4 3:2 1:0 Attr RW RW RW RW RW RW Reset Value Description CLASSD_EN 0x0 CLASS D enable 0:disable 1:enable CLASSD_MUTE_EN 0x1 CLASS D mute_ramp function enable 0:disable 1:enable CLASSD_SSC_EN 0x1 CLASS D Spread-Spectrum enable 0:disable 1:enable CLASSD_SSC_SEL 0x0 CLASS D Spread-Spectrum steps select 0: 8 steps 1:16 step CLASSD_MUTE_RATE 0x2 00:0ms;01:16ms;10:32ms;11:64ms CLASSD_SW_RATE 0x1 00:2.5ns;01:5ns;10:7.5ns;11:10ns CODEC_ACLASSD_CFG2 Address: Operational Base + offset (0x0041) Bit 7 6:4 3 2:0 Attr RO RW RO RW Reset Value Description CLASSD_OCP_STS 0x0 IF this bit is high, it need to restart CLASS D. CLASSD_OCPP CLASS D PFET OCP Select 000: 0.5A 0x4 001: 0.625A 010: 0.75A 011: 0.875A 100:1ADefault 101: 1.125A 110: 1.25A 111: 1.375A CLASSD_MUTE_DONE 0x0 When class d mute finished, this bit will be set high. CLASSD_OCPN CLASS D NFET OCP Select 000: 0.5A 0x4 001: 0.625A 010: 0.75A 011: 0.875A 100:1ADefault 101: 1.125A 110: 1.25A 111: 1.375A Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 51 RK817 Datasheet Rev 1.01 CODEC_APLL_CFG0 Address: Operational Base + offset (0x0042) Bit 7:4 3 2 1:0 Attr RW RW RW RW Reset Value Description RESV 0x0 Reserved PLL_CLKIN_SEL 0x0 the PLL input clock select, 0->main clk 1->main clk/2 PLL_OUTDIV_EN 0x1 enable PLL VCO output clock divide 0:disable 1:enable PLL_VCO_BANDSEL 0x0 PLL VCO working band select CODEC_APLL_CFG1 Address: Operational Base + offset (0x0043) Bit 7:6 5:3 2:0 Attr RW RW RW Reset Value Description PLL_RES_SEL 0x0 PLL filter resistor value select PLL_CUR_SEL 0x0 PLL charge-pump working current select PLL_POSDIV_L3 0x0 PLL feedback clock divide value select low 3 bits CODEC_APLL_CFG2 Address: Operational Base + offset (0x0044) Bit 7:0 Attr RW Reset Value Description PLL_POSDIV_H8 0x30 PLL feedback clock divide value select high 8 bits CODEC_APLL_CFG3 Address: Operational Base + offset (0x0045) Bit 7:0 Attr RW Reset Value Description 0x19 PLL_PREDIV_BIT PLL input clock pre-divide value select CODEC_APLL_CFG4 Address: Operational Base + offset (0x0046) Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 52 RK817 Datasheet Rev 1.01 Bit 7:4 3:0 Attr RW RW Reset Value Description PLL_OUTDIV PLL VCO output clock divide value select outdiv<3:2>: 00-> divide 5 01-> divide 10 0x6 10-> divide 3 11-> divide 6 outdiv<1:0>: 00-> divide 3 01-> divide 1 10-> divide 2 11-> divide 1" PLL_CLK_DIV 0x5 PLL divided ratio of PLL_HIGH_clk, 0000->divded 1 and 1111->divided 15 CODEC_APLL_CFG5 Address: Operational Base + offset (0x0047) Bit 7:3 2 1 0 Attr RW RW RW RW Reset Value Description 0x00 RESV Reserved PLL_RESET 0x0 reset the total PLL register 0:release reset 1:set reset PLL_TEST 0x0 check the PLL internal VCO control voltage 0:disable 1:enable PLL_PWD pll power down 0x1 0: PLL power up 1:PLL power down CODEC_DI2S_CKM Address: Operational Base + offset (0x0048) Bit 7:4 3 2 1 Attr RW RW RW RW Reset Value Description SCK_DIV 0x0 F(mclk2x)/F(sclk) - 1 PDM_EN 0x0 I2S SDO output delta-sigma ADC 1bit data. 0:disable; 1:enable. SCK_EN 0x0 i2ssclk clock enable, active in master mode. 0:disable 1:enable SCK_P sclk polarity 0x0 0: normal 1:inverted Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 53 RK817 Datasheet Bit 0 Attr RW Reset Value Description I2S_TX_MST 0x1 I2S TX module as 0: slave mode 1: master mode Rev 1.01 CODEC_DI2S_RSD Address: Operational Base + offset (0x0049) Bit 7:4 3 2:1 0 Attr RW RW RW RW Reset Value Description RESV 0x0 Reserved PDM_LR_SEL 0x0 0L; 1R SCKD_RX sclk divider for rxlrck generator 0x0 00:64 01:128 10:256(01 valid only if lrclk<= 96k, 10 valid only if lrclk<= 48k) RXRL_P I2S Rx lrck polarity 0x0 0: normal 1:inverted CODEC_DI2S_RXCR1 Address: Operational Base + offset (0x004a) Bit 7 6 5:4 3:2 1 0 Attr RW RW RW RW RW RW Reset Value Description RESV 0x0 Reserved TFS_RX 0x0 Rx transfer mode selector: 0: I2S 1:PCM PBM_RX Rx PCM bus mode: 0x0 00: delay0 01:delay1 10: delay2 11:delay3 IBM_RX 0x0 Rx I2S bus mode: 00: normal 01:left 10:right EXRL_RX Rx exchange right/left channel for rx 0x0 0: normal 1:exchange right and left channel LSB_RX 0x0 0: LSB 1:MSB CODEC_DI2S_RXCR2 Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 54 RK817 Datasheet Rev 1.01 Address: Operational Base + offset (0x004b) Bit 7:5 4:0 Attr RW RW Reset Value Description RESV 0x0 Reserved VDW_RX 0x17 valid date width 0x17: 24 bits data width; 0x0F: 16 bits data width; others: reserved CODEC_DI2S_RXCMD_TSD Address: Operational Base + offset (0x004c) Bit 7:6 5 4 3 2:1 0 Attr RW RW RW RW RW RW Reset Value Description RESV 0x0 Reserved RXS 0x0 rx transfer start 0: rx stop 1:rx start RXC 0x0 rx transfer clear, high active RESV 0x0 Reserved SCKD_TX sclk divider for txlrck generator 0x0 00:64 01:128 10:256(01 valid only if lrclk<= 96k, 10 valid only if lrclk<= 48k) TXRL_P 0x0 I2S Txlrck polarity 0:normal 1:inverted CODEC_DI2S_TXCR1 Address: Operational Base + offset (0x004d) Bit 7 6 5:4 Attr RW RW RW Reset Value Description RESV 0x0 Reserved TFS_TX 0x0 Tx transfer mode selector: 0: I2S 1:PCM PBM_TX Tx PCM bus mode: 0x0 00: delay0 01: delay1 10: delay2 Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 55 RK817 Datasheet Rev 1.01 Bit 3:2 1 0 Attr RW RW RW Reset Value Description IBM_TX 0x0 Tx I2S bus mode: 00: normal 01:left 10:right EXRL_TX Tx exchange right/left channel for TX 0x0 0: normal 1:exchange right and left channel LSB_TX 0x0 0: LSB 1:MSB CODEC_DI2S_TXCR2 Address: Operational Base + offset (0x004e) Bit 7:5 4:0 Attr RW RW Reset Value Description RESV 0x0 Reserved VDW_TX 0x17 valid date width 0x17: 24 bits data width; 0x0F: 16 bits data width; others: reserved CODEC_DI2S_TXCR3_TXCMD Address: Operational Base + offset (0x004f) Bit 7 6 5:0 Attr RW RW RW Reset Value Description TXS 0x0 tx transfer start 0: tx stop 1:tx start TXC 0x0 tx transfer clear, high active RCNT_TX 0x00 right justified counter for I2S right justified slave mode only gas_gauge_ADC_CONFIG0 Address: Operational Base + offset (0x0050) Bit 7 6 Attr RW RW Reset Value Description GG_EN 0x1 GG_EN: Gasgauge module enable bit 0:disable 1: enable SYS_VOL_ADC_EN SYS_VOL_ADC_EN: if GG_EN=0, then the 0x0 ADC of SYS voltage controlled by the bit 0:disable 1:enable Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 56 RK817 Datasheet Rev 1.01 Bit 5 4 3 2 1 0 Attr RW RW RW RW RW RW Reset Value Description TS_ADC_EN TS_ADC_EN: if GG_EN=0, the ADC of TS1 0x0 controlled by the bit 0:disable 1:enable USB_VOL_ADC_EN USB_VOL_ADC_EN: if GG_EN=0, the ADC 0x0 of USB voltage by the bit 0:disable 1:enable BAT_VOL_ADC_EN BAT_VOL_ADC_EN: if GG_EN=0, then the 0x1 ADC of BAT voltage controlled by the bit 0:disable 1:enable BAT_CUR_ADC_EN BAT_CUR_ADC_EN: if GG_EN=0, then the 0x1 ADC of BAT current controlled by the bit 0:disable 1:enable RESV 0x0 RESV:Reserve ADC_SLP_RATE 0x0 ADC_SLP_RATE: the ADC sample rate: 0:512; 1:1024 gas_gauge_ADC_CONFIG1 Address: Operational Base + offset (0x0055) Bit 7 6 5:4 3 2 Attr RC RW RW RW RW Reset Value Description VOL_CUR_CALIB_UPD VOL_CUR_CALIB_UPD: The voltage ADC and 0x0 current ADC calibration finished status 0:not finished 1:finished (Write "1" to clear) RESV 0x0 RESV:Reserve VOL_ADC_TSCUR_SEL VOL_ADC_TSCUR_SEL: TS pin flow out 0x3 current in active state 00:20uA 01:40uA 10:60uA 11:80uA TS_FUN TS_FUN: TS pin function selection 0x0 0:source current to TS pin 1:external voltage input directly RESV 0x0 RESV:Reserve Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 57 RK817 Datasheet Rev 1.01 Bit 1:0 Attr RW Reset Value Description RLX_CUR_FILTER RLX_CUR_FILTERRelax mode enter 0x0 threshold filter. 00:4S; 01:1S; 10:2S; 11:8S; gas_gauge_GG_CON Address: Operational Base + offset (0x0056) Bit 7:6 5:4 3:2 1 0 Attr RW RW RW RW RW Reset Value Description RLX_SPT RLX_SPT: relax mode voltage sampling 0x1 interval time T_RELAX: Relax mode enter and quit time 00:8min 01:16min 10:32min 11:48min ADC_OFF_CAL_INTERV ADC_OFF_CAL_INTERV<1:0>: ADC offset 0x0 calibration interval time 00:8min 01:16min 10:32min 11:48min FRAME_SMP_INTERV FRAME_SMP_INTERV<1:0>:Data frame 0x1 sample interval in the sleep state(Unit:S) 00:0S 01:1S 10:2S 11:3S VOL_OUT_MOD 0x0 VOL_OUT_MOD: Voltageoutput mode 0:Average Voltage 1:Instant Voltage CUR_OUT_MOD 0x0 CUR_OUT_MOD: Current output mode 0:Average Current 1:Instant Current gas_gauge_GG_STS Address: Operational Base + offset (0x0057) Bit 7 6 5 Attr RO RO RW Reset Value Description OCV_STS OCV_STS: OCV mode status. 0x0 1: ocv mode; 0: null ocv mode. TERM_UPD 0x0 TERM_UPD: Flag bit for Q_TERM update 0NOT 1:YES QMAX_UPD_SOFT QMAX_UPD_SOFT: software Flag bit for 0x0 QMAX update 0NOT 1:YES Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 58 RK817 Datasheet Rev 1.01 Bit 4 3 2 1 0 Attr RO RO RO RO RO Reset Value Description BAT_CON BAT_CON: battery first connection, edge 0x0 trigger 0:NOT 1:YES RELAX_VOL1_UPD RELAX_VOL1_UPD: battery voltage1 0x0 updated in relax status 0:NOT 1:YES RELAX_VOL2_UPD RELAX_VOL2_UPD: battery voltage2 0x0 updated in relax status 0:NOT 1:YES RELAX_STS 0x0 RELAX_STS: battery coming into relax status 0:NOT 1:YES OCV_UPD 0x0 OCV_UPD: Flag bit for OCV update 0NOT 1:YES gas_gauge_RELAX_THRE_H Address: Operational Base + offset (0x0058) Bit 7:0 Attr RW Reset Value Description RELAX_THRE_CUR 0x00 RELAX_THRE_CUR: relax mode threshold current set.<15:8> gas_gauge_RELAX_THRE_L Address: Operational Base + offset (0x0059) Bit 7:0 Attr RW Reset Value Description RELAX_THRE_CUR 0x60 RELAX_THRE_CUR: relax mode threshold current set. <7:0> gas_gauge_RELAX_VOL1_H Address: Operational Base + offset (0x005a) Bit 7:0 Attr RO Reset Value Description RELAX_VOL1_H 0x00 RELAX_VOL1_H<15:8>: relax 1st mode voltage gas_gauge_RELAX_VOL1_L Address: Operational Base + offset (0x005b) Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 59 RK817 Datasheet Rev 1.01 Bit 7:0 Attr RO Reset Value Description RELAX_VOL1_L 0x00 RELAX_VOL1_L<7:0>: relax 1st mode voltage gas_gauge_RELAX_VOL2_H Address: Operational Base + offset (0x005c) Bit 7:0 Attr RO Reset Value Description RELAX_VOL2 0x00 RELAX_VOL2<15:8>: relax 2nd mode voltage gas_gauge_RELAX_VOL2_L Address: Operational Base + offset (0x005d) Bit 7:0 Attr RO Reset Value Description RELAX_VOL2 0x00 RELAX_VOL2<7:0>: relax 2nd mode voltage gas_gauge_RELAX_CUR1_H Address: Operational Base + offset (0x005e) Bit 7:0 Attr RO Reset Value Description 0x00 RELAX_CUR1 RELAX_CUR1<15:8>:relax 1st mode current gas_gauge_RELAX_CUR1_L Address: Operational Base + offset (0x005f) Bit 7:0 Attr RO Reset Value Description 0x00 RELAX_CUR1 RELAX_CUR1<7:0>: relax 1st mode current gas_gauge_RELAX_CUR2_H Address: Operational Base + offset (0x0060) Bit 7:0 Attr RO Reset Value Description RELAX_CUR2 0x00 RELAX_CUR2<15:8>: relax 2nd mode current gas_gauge_RELAX_CUR2_L Address: Operational Base + offset (0x0061) Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 60 RK817 Datasheet Rev 1.01 Bit 7:0 Attr RO Reset Value Description 0x00 RELAX_CUR2 RELAX_CUR2<7:0>: relax 2nd mode current gas_gauge_OCV_THRE_VOL Address: Operational Base + offset (0x0062) Bit 7:0 Attr RW Reset Value Description OCV_THRE_VOL 0x00 OCV_THRE_VOL:OCV mode threshold. 00:0.5mV; 01:1mV; 02:1.5mV.....FF:127.5mV gas_gauge_OCV_VOL_H Address: Operational Base + offset (0x0063) Bit 7:0 Attr RO Reset Value Description 0x00 OCV_VOL_REG OCV_VOL_REG<15:8>: OCV voltage gas_gauge_OCV_VOL_L Address: Operational Base + offset (0x0064) Bit 7:0 Attr RO Reset Value Description 0x00 OCV_VOL_REG OCV_VOL_REG<7:0>:OCV voltage gas_gauge_OCV_VOL0_H Address: Operational Base + offset (0x0065) Bit 7:0 Attr RO Reset Value Description 0x00 OCV_VOL0_REG OCV_VOL0_REG<15:8>:OCV voltage 0 gas_gauge_OCV_VOL0_L Address: Operational Base + offset (0x0066) Bit 7:0 Attr RO Reset Value Description 0x00 OCV_VOL0_REG OCV_VOL0_REG<7:0>:OCV voltage 0 gas_gauge_OCV_CUR_H Address: Operational Base + offset (0x0067) Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 61 RK817 Datasheet Rev 1.01 Bit 7:0 Attr RO Reset Value Description 0x00 OCV_CUR_REG OCV_CUR_REG<15:8>:OCV current gas_gauge_OCV_CUR_L Address: Operational Base + offset (0x0068) Bit 7:0 Attr RO Reset Value Description 0x00 OCV_CUR_REG OCV_CUR_REG<7:0>:OCV current gas_gauge_OCV_CUR0_H Address: Operational Base + offset (0x0069) Bit 7:0 Attr RO Reset Value Description 0x00 OCV_CUR0_REG OCV_CUR0_REG<15:8>: OCV current 0 gas_gauge_OCV_CUR0_L Address: Operational Base + offset (0x006a) Bit 7:0 Attr RO Reset Value Description 0x00 OCV_CUR0_REG OCV_CUR0_REG<7:0>: OCV current 0 gas_gauge_PWRON_VOL_H Address: Operational Base + offset (0x006b) Bit 7:0 Attr RO Reset Value Description PWRON_VOL_REG 0x00 PWRON_VOL_REG<15:8>: power on bat voltage gas_gauge_PWRON_VOL_L Address: Operational Base + offset (0x006c) Bit 7:0 Attr RO Reset Value Description PWRON_VOL_REG 0x00 PWRON_VOL_REG<7:0>: power on bat voltage gas_gauge_PWRON_CUR_H Address: Operational Base + offset (0x006d) Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 62 RK817 Datasheet Rev 1.01 Bit 7:0 Attr RO Reset Value Description PWRON_CUR_REG 0x00 PWRON_CUR_REG<15:8>: power on bat current gas_gauge_PWRON_CUR_L Address: Operational Base + offset (0x006e) Bit 7:0 Attr RO Reset Value Description PWRON_CUR_REG 0x00 PWRON_CUR_REG<7:0>: power on bat current gas_gauge_OFF_CNT Address: Operational Base + offset (0x006f) Bit 7:0 Attr RW Reset Value Description 0x00 OFF_CNT OFF_CNT<7:0>: power off time gas_gauge_Q_INIT_H3 Address: Operational Base + offset (0x0070) Bit 7:0 Attr RW Reset Value Description 0x00 Q_INIT Q_INIT<31:24>:power off time gas_gauge_Q_INIT_H2 Address: Operational Base + offset (0x0071) Bit 7:0 Attr RW Reset Value Description 0x00 Q_INIT Q_INIT<23:16>:power off time gas_gauge_Q_INIT_L1 Address: Operational Base + offset (0x0072) Bit 7:0 Attr RW Reset Value Description 0x00 Q_INIT Q_INIT<15:8>:power off time gas_gauge_Q_INIT_L0 Address: Operational Base + offset (0x0073) Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 63 RK817 Datasheet Bit 7:0 Attr RW Reset Value Description 0x00 Q_INIT Q_INIT<7:0>:power off time Rev 1.01 gas_gauge_Q_PRES_H3 Address: Operational Base + offset (0x0074) Bit 7:0 Attr RO Reset Value Description 0x00 Q_PRES Q_PRES<31:24>:Coulomp value gas_gauge_Q_PRES_H2 Address: Operational Base + offset (0x0075) Bit 7:0 Attr RO Reset Value Description 0x00 Q_PRES Q_PRES<23:16>:Coulomp value gas_gauge_Q_PRES_L1 Address: Operational Base + offset (0x0076) Bit 7:0 Attr RO Reset Value Description 0x00 Q_PRES Q_PRES<15:8>:Coulomp value gas_gauge_Q_PRES_L0 Address: Operational Base + offset (0x0077) Bit 7:0 Attr RO Reset Value Description 0x00 Q_PRES Q_PRES<7:0>:Coulomp value gas_gauge_BAT_VOL_H Address: Operational Base + offset (0x0078) Bit 7:0 Attr RO Reset Value Description 0x00 BAT_VOL BAT_VOL<15:8>: bat voltage gas_gauge_BAT_VOL_L Address: Operational Base + offset (0x0079) Bit 7:0 Attr RO Reset Value Description 0x00 BAT_VOL BAT_VOL<7:0>:bat voltage Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 64 RK817 Datasheet Rev 1.01 gas_gauge_BAT_CUR_H Address: Operational Base + offset (0x007a) Bit 7:0 Attr RO Reset Value Description 0x00 BAT_CUR BAT_CUR<15:8>:battery current gas_gauge_BAT_CUR Address: Operational Base + offset (0x007b) Bit 7:0 Attr RO Reset Value Description 0x00 BAT_CUR BAT_CUR<7:0>:BAT_CUR: battery current gas_gauge_BAT_TS_H Address: Operational Base + offset (0x007c) Bit 7:0 Attr RO Reset Value Description 0x00 BAT_TS BAT_TS<15:8>:TS ADC value gas_gauge_BAT_TS_L Address: Operational Base + offset (0x007d) Bit 7:0 Attr RO Reset Value Description 0x00 BAT_TS BAT_TS<7:0>: TS ADC value gas_gauge_USB_VOL_H Address: Operational Base + offset (0x007e) Bit 7:0 Attr RO Reset Value Description 0x00 USB_VOL USB_VOL<15:8>USB voltage value gas_gauge_USB_VOL_L Address: Operational Base + offset (0x007f) Bit 7:0 Attr RO Reset Value Description 0x00 USB_VOL USB_VOL<7:0>USB voltage value gas_gauge_SYS_VOL_H Address: Operational Base + offset (0x0080) Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 65 RK817 Datasheet Rev 1.01 Bit 7:0 Attr RO Reset Value Description 0x00 SYS_VOL SYS_VOL<15:8>: SYS voltage value gas_gauge_SYS_VOL_L Address: Operational Base + offset (0x0081) Bit 7:0 Attr RO Reset Value Description 0x00 SYS_VOL SYS_VOL<7:0>SYS voltage value gas_gauge_Q_MAX_H3 Address: Operational Base + offset (0x0082) Bit 7:0 Attr RW Reset Value Description 0x00 Q_MAX Q_MAX<31:24>Qmax value gas_gauge_Q_MAX_H2 Address: Operational Base + offset (0x0083) Bit 7:0 Attr RW Reset Value Description 0x00 Q_MAX Q_MAX<23:16>Qmax value gas_gauge_Q_MAX_L1 Address: Operational Base + offset (0x0084) Bit 7:0 Attr RW Reset Value Description 0x00 Q_MAX Q_MAX<15:8>Qmax value gas_gauge_Q_MAX_L0 Address: Operational Base + offset (0x0085) Bit 7:0 Attr RW Reset Value Description 0x00 Q_MAX Q_MAX<7:0>Qmax value gas_gauge_Q_TERM_H3 Address: Operational Base + offset (0x0086) Bit 7:0 Attr RO Reset Value Description 0x00 Q_TERM Q_TERM<31:24>charge terminal Coulomp value Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 66 RK817 Datasheet Rev 1.01 gas_gauge_Q_TERM_H2 Address: Operational Base + offset (0x0087) Bit 7:0 Attr RO Reset Value Description 0x00 Q_TERM Q_TERM<23:16>charge terminal Coulomp value gas_gauge_Q_TERM_L1 Address: Operational Base + offset (0x0088) Bit 7:0 Attr RO Reset Value Description 0x00 Q_TERM Q_TERM<15:8>charge terminal Coulomp value gas_gauge_Q_TERM_L0 Address: Operational Base + offset (0x0089) Bit 7:0 Attr RO Reset Value Description 0x00 Q_TERM Q_TERM<7:0>charge terminal Coulomp value gas_gauge_Q_OCV_H3 Address: Operational Base + offset (0x008a) Bit 7:0 Attr RO Reset Value Description 0x00 Q_OCV Q_OCV<31:24>:OCV update Coulomp value gas_gauge_Q_OCV_H2 Address: Operational Base + offset (0x008b) Bit 7:0 Attr RO Reset Value Description 0x00 Q_OCV Q_OCV<23:16>:OCV update Coulomp value gas_gauge_Q_OCV_L1 Address: Operational Base + offset (0x008c) Bit 7:0 Attr RO Reset Value Description 0x00 Q_OCV Q_OCV<15:8>:OCV update Coulomp value Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 67 RK817 Datasheet Rev 1.01 gas_gauge_Q_OCV_L0 Address: Operational Base + offset (0x008d) Bit 7:0 Attr RO Reset Value Description 0x00 Q_OCV Q_OCV<7:0>:OCV update Coulomp value gas_gauge_OCV_CNT Address: Operational Base + offset (0x008e) Bit 7:0 Attr RW Reset Value Description 0x00 OCV_CNT OCV_CNT<7:0>: two OCV time interval gas_gauge_SLEEP_CON_SAMP_CUR_H Address: Operational Base + offset (0x008f) Bit 7:0 Attr RW Reset Value Description SLEEP_CON_SAMP_CUR 0x00 SLEEP_CON_SAMP_CUR<15:8>:SLEEP modeWhen the current is greater than the set value, it is sampled once again, until it is less than the set value, and the value is updated to the RELAX register gas_gauge_SLEEP_CON_SAMP_CUR Address: Operational Base + offset (0x0090) Bit 7:0 Attr RW Reset Value Description SLEEP_CON_SAMP_CUR 0x60 SLEEP_CON_SAMP_CUR<7:0>: SLEEP modeWhen the current is greater than the set value, it is sampled once again, until it is less than the set value, and the value is updated to the RELAX register gas_gauge_CAL_OFFSET_H Address: Operational Base + offset (0x0091) Bit 7:0 Attr RW Reset Value Description CAL_OFFSET_REG 0x7f CAL_OFFSET_REG<15:8>: PCB current offset value high bit gas_gauge_CAL_OFFSET_L Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 68 RK817 Datasheet Rev 1.01 Address: Operational Base + offset (0x0092) Bit 7:0 Attr RW Reset Value Description CAL_OFFSET_REG 0xff CAL_OFFSET_REG<7:0>: PCB current offset value low bit gas_gauge_VCALIB0_H Address: Operational Base + offset (0x0093) Bit 7:0 Attr RO Reset Value Description VCALIB0 0x00 VCALIB0<15:8>:Voltage0 offset value for AP to calculate offset error and gain error gas_gauge_VCALIB0_L Address: Operational Base + offset (0x0094) Bit 7:0 Attr RO Reset Value Description VCALIB0 0x00 VCALIB0<7:0>:Voltage0 offset value for AP to calculate offset error and gain error gas_gauge_VCALIB1_H Address: Operational Base + offset (0x0095) Bit 7:0 Attr RO Reset Value Description VCALIB1 0x00 VCALIB1<15:8>:Voltage1 offset value for AP to calculate offset error and gain error gas_gauge_VCALIB1_L Address: Operational Base + offset (0x0096) Bit 7:0 Attr RO Reset Value Description VCALIB1 0x00 VCALIB1<7:0>:Voltage1 offset value for AP to calculate offset error and gain error gas_gauge_IOFFSET_H Address: Operational Base + offset (0x0097) Bit 7:0 Attr RO Reset Value Description IOFFSET 0x00 IOFFSET<15:8>:Current offset value calculated Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 69 RK817 Datasheet Rev 1.01 gas_gauge_IOFFSET_L Address: Operational Base + offset (0x0098) Bit 7:0 Attr RO Reset Value Description IOFFSET 0x00 IOFFSET<7:0>:Current offset value calculated gas_gauge_BAT_R0 Address: Operational Base + offset (0x0099) Bit 7:0 Attr RW Reset Value Description 0x00 BAT_R0 BAT_R0<7:0>:BAT resistance gas_gauge_BAT_R1 Address: Operational Base + offset (0x009a) Bit 7:0 Attr RW Reset Value Description 0x00 BAT_R1 BAT_R1<7:0>:BAT resistance gas_gauge_BAT_R2 Address: Operational Base + offset (0x009b) Bit 7:0 Attr RW Reset Value Description 0x00 BAT_R2 BAT_R2<7:0>:BAT resistance gas_gauge_BAT_R3 Address: Operational Base + offset (0x009c) Bit 7:0 Attr RW Reset Value Description 0x00 BAT_R3 BAT_R3<7:0>:BAT resistance gas_gauge_DATA0 Address: Operational Base + offset (0x009d) Bit 7:0 Attr RW Reset Value Description 0x00 DATA DATA<7:0>:data for AP gas_gauge_DATA1 Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 70 RK817 Datasheet Address: Operational Base + offset (0x009e) Bit 7:0 Attr RW Reset Value Description 0x00 DATA DATA<7:0>:data for AP gas_gauge_DATA2 Address: Operational Base + offset (0x009f) Bit 7:0 Attr RW Reset Value Description 0x00 DATA DATA<7:0>:data for AP gas_gauge_DATA3 Address: Operational Base + offset (0x00a0) Bit 7:0 Attr RW Reset Value Description 0x00 DATA DATA<7:0>:data for AP gas_gauge_DATA4 Address: Operational Base + offset (0x00a1) Bit 7:0 Attr RW Reset Value Description 0x00 DATA DATA<7:0>:data for AP gas_gauge_DATA5 Address: Operational Base + offset (0x00a2) Bit 7:0 Attr RW Reset Value Description 0x00 DATA DATA<7:0>:data for AP gas_gauge_DATA6 Address: Operational Base + offset (0x00a3) Bit 7:0 Attr RW Reset Value Description 0x00 DATA DATA<7:0>:data for AP gas_gauge_DATA7 Address: Operational Base + offset (0x00a4) Rev 1.01 Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 71 RK817 Datasheet Bit 7:0 Attr RW Reset Value Description 0x00 DATA DATA<7:0>:data for AP gas_gauge_DATA8 Address: Operational Base + offset (0x00a5) Bit 7:0 Attr RW Reset Value Description 0x00 DATA DATA<7:0>:data for AP gas_gauge_DATA9 Address: Operational Base + offset (0x00a6) Bit 7:0 Attr RW Reset Value Description 0x00 DATA DATA<7:0>:data for AP gas_gauge_DATA10 Address: Operational Base + offset (0x00a7) Bit 7:0 Attr RW Reset Value Description 0x00 DATA DATA<7:0>:data for AP gas_gauge_DATA11 Address: Operational Base + offset (0x00a8) Bit 7:0 Attr RW Reset Value Description 0x00 DATA DATA<7:0>:data for AP gas_gauge_VOL_ADC_B3 Address: Operational Base + offset (0x00a9) Bit 7:0 Attr RO Reset Value Description VOL_ADC_B OTP VOL_ADC_B<31:24>: default:OTP gas_gauge_VOL_ADC_B2 Address: Operational Base + offset (0x00aa) Register0000 Abstract Rev 1.01 Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 72 RK817 Datasheet Bit 7:0 Attr RO Reset Value Description VOL_ADC_B OTP VOL_ADC_B<23:16> default: OTP gas_gauge_VOL_ADC_B1 Address: Operational Base + offset (0x00ab) Register0000 Abstract Bit Attr Reset Value Description VOL_ADC_B 7:0 RO OTP VOL_ADC_B<15:8> default: OTP gas_gauge_VOL_ADC_B_7_0 Address: Operational Base + offset (0x00ac) Register0000 Abstract Bit Attr Reset Value Description VOL_ADC_B0 7:0 RO OTP VOL_ADC_B<7:0> default: OTP gas_gauge_CUR_ADC_K3 Address: Operational Base + offset (0x00ad) Bit 7:0 Attr RO Reset Value Description CUR_ADC_K OTP CUR_ADC_K<31:24> default: OTP gas_gauge_CUR_ADC_K2 Address: Operational Base + offset (0x00ae) Bit 7:0 Attr RO Reset Value Description CUR_ADC_K OTP CUR_ADC_K<23:16> default: OTP gas_gauge_CUR_ADC_K1 Address: Operational Base + offset (0x00af) Bit 7:0 Attr RO Reset Value Description CUR_ADC_K OTP CUR_ADC_K<15:8> default: OTP Rev 1.01 Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 73 RK817 Datasheet Rev 1.01 gas_gauge_CUR_ADC_K0 Address: Operational Base + offset (0x00b0) Bit 7:0 Attr RO Reset Value Description CUR_ADC_K0 OTP CUR_ADC_K<7:0> default: OTP PMIC_POWER_EN0 Address: Operational Base + offset (0x00b1) Bit 7 6 5 4 3 2 Attr RW RW RW RW RW RW Reset Value Description BUCK4_EN_MASK BUCK4_EN_MASK: MUST write them to "1" if want to change corresponding BUCK4_EN 0x0 bitThe BUCK4_EN_MASK bits should be clear when BUCK4_EN bits have been written. BUCK3_EN_MASK BUCK3_EN_MASK: MUST write them to "1" if want to change corresponding BUCK3_EN 0x0 bitThe BUCK3_EN_MASK bits should be clear when BUCK3_EN bits have been written. BUCK2_EN_MASK BUCK2_EN_MASK: MUST write them to "1" if want to change corresponding BUCK2_EN 0x0 bitThe BUCK2_EN_MASK bits should be clear when BUCK2_EN bits have been written. BUCK1_EN_MASK BUCK1_EN_MASK: MUST write them to "1" if want to change corresponding BUCK1_EN 0x0 bitThe BUCK1_EN_MASK bits should be clear when BUCK1_EN bits have been written. BUCK4_EN BUCK4_EN: BUCK4 enable in active mode OTP 1, Enable 0, Disable the default value is set by otp reset by power down or RST. BUCK3_EN BUCK3_EN: BUCK3 enable in active mode OTP 1, Enable 0, Disable the default value is set by otp reset by power down or RST. Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 74 RK817 Datasheet Rev 1.01 Bit 1 0 Attr RW RW Reset Value Description BUCK2_EN BUCK2_EN: BUCK2 enable in active mode OTP 1, Enable 0, Disable the default value is set by otp reset by power down or RST. BUCK1_EN BUCK1_EN: BUCK1 enable in active mode OTP 1, Enable 0, Disable the default value is set by otp reset by power down or RST. PMIC_POWER_EN1 Address: Operational Base + offset (0x00b2) Bit 7 6 5 4 3 Attr RW RW RW RW RW Reset Value Description LDO4_EN_MASK LDO4_EN_MASK: MUST write them to "1" if 0x0 want to change corresponding LDO4_EN bitThe LDO4_EN_MASK bits should be clear when LDO4_EN bits have been written. LDO3_EN_MASK LDO3_EN_MASK: MUST write them to "1" if 0x0 want to change corresponding LDO3_EN bitThe LDO3_EN_MASK bits should be clear when LDO3_EN bits have been written. LDO2_EN_MASK LDO2_EN_MASK: MUST write them to "1" if 0x0 want to change corresponding LDO2_EN bitThe LDO2_EN_MASK bits should be clear when LDO2_EN bits have been written. LDO1_EN_MASK LDO1_EN_MASK: MUST write them to "1" if 0x0 want to change corresponding LDO1_EN bitThe LDO1_EN_MASK bits should be clear when LDO1_EN bits have been written. LDO4_EN LDO4_EN: LDO4 enable in active mode OTP 1, Enable 0, Disable the default value is set by otp reset by power down or RST. Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 75 RK817 Datasheet Rev 1.01 Bit 2 1 0 Attr RW RW RW Reset Value Description LDO3_EN LDO3_EN: LDO3 enable in active mode OTP 1, Enable 0, Disable the default value is set by otp reset by power down or RST. LDO2_EN LDO2_EN: LDO2 enable in active mode OTP 1, Enable 0, Disable the default value is set by otp reset by power down or RST. LDO1_EN LDO1_EN: LDO1 enable in active mode OTP 1, Enable 0, Disable the default value is set by otp reset by power down or RST. PMIC_POWER_EN2 Address: Operational Base + offset (0x00b3) Bit 7 6 5 4 Attr RW RW RW RW Reset Value Description LDO8_EN_MASK LDO8_EN_MASK: MUST write them to "1" if 0x0 want to change corresponding LDO8_EN bitThe LDO8_EN_MASK bits should be clear when LDO8_EN bits have been written. LDO7_EN_MASK LDO7_EN_MASK: MUST write them to "1" if 0x0 want to change corresponding LDO7_EN bitThe LDO7_EN_MASK bits should be clear when LDO7_EN bits have been written. LDO6_EN_MASK LDO6_EN_MASK: MUST write them to "1" if 0x0 want to change corresponding LDO6_EN bitThe LDO6_EN_MASK bits should be clear when LDO6_EN bits have been written. LDO5_EN_MASK LDO5_EN_MASK: MUST write them to "1" if 0x0 want to change corresponding LDO5_EN bitThe LDO5_EN_MASK bits should be clear when LDO5_EN bits have been written. Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 76 RK817 Datasheet Rev 1.01 Bit 3 2 1 0 Attr RW RW RW RW Reset Value Description LDO8_EN LDO8_EN: LDO8 enable in active mode OTP 1, Enable 0, Disable the default value is set by otp reset by power down or RST. LDO7_EN LDO7_EN: LDO7 enable in active mode OTP 1, Enable 0, Disable the default value is set by otp reset by power down or RST. LDO6_EN LDO6_EN: LDO6 enable in active mode OTP 1, Enable 0, Disable the default value is set by otp reset by power down or RST. LDO5_EN LDO5_EN: LDO5 enable in active mode OTP 1, Enable 0, Disable the default value is set by otp reset by power down or RST. PMIC_POWER_EN3 Address: Operational Base + offset (0x00b4) Bit 7 6 5 Attr RW RW RW Reset Value Description RESV 0x0 RESV:Reserve OTG_EN_MASK OTG_EN _MASK : MUST write them to "1" if 0x0 want to change corresponding OTG_EN bit The OTG_EN_MASK bits should be clear when OTG_EN bits have been written. BOOST_EN_MASK BOOST_EN _MASK : MUST write them to "1" if want to change corresponding BOOST_EN 0x0 bitThe BOOST_EN_MASK bits should be clear when BOOST_EN bits have been written. Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 77 RK817 Datasheet Rev 1.01 Bit 4 3 2 1 0 Attr RW RW RW RW RW Reset Value Description LDO9_EN_MASK LDO9_EN_MASK: MUST write them to "1" if 0x0 want to change corresponding LDO9_EN bitThe LDO9_EN_MASK bits should be clear when LDO9_EN bits have been written. RESV 0x0 RESV: Reserve OTG_EN OTG_EN : OTG enable in active mode OTP 1, Enable 0, Disable the default value is set by otp reset by power down or RST. BOOST_EN BOOST_EN : BOOST enable in active mode OTP 1, Enable 0, Disable the default value is set by otp reset by power down or RST. LDO9_EN LDO9_EN: LDO9 enable in active mode OTP 1, Enable 0, Disable the default value is set by otp reset by power down or RST. PMIC_POWER_SLP_EN0 Address: Operational Base + offset (0x00b5) Bit 7 6 5 Attr RW RW RW Reset Value Description RESV 0x0 RESV:Reserve OTG_SLP_EN OTG_SLP_EN: OTG enable in SLEEP mode OTP 1, Enable 0, Disable the default value is set by otp reset by power down or RST. BOOST_SLP_EN BOOST_SLP_EN: BOOST enable in SLEEP mode OTP 1, Enable 0, Disable the default value is set by otp reset by power down or RST. Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 78 RK817 Datasheet Rev 1.01 Bit 4 3 2 1 0 Attr RW RW RW RW RW Reset Value Description LDO9_SLP_EN LDO9_SLP_EN: LDO9 enable in SLEEP mode OTP 1, Enable 0, Disable the default value is set by otp reset by power down or RST. BUCK4_SLP_EN BUCK4_SLP_EN: BUCK4 enable in SLEEP mode OTP 1, Enable 0, Disable the default value is set by otp reset by power down or RST. BUCK3_SLP_EN BUCK3_SLP_EN: BUCK3 enable in SLEEP mode OTP 1, Enable 0, Disable the default value is set by otp reset by power down or RST. BUCK2_SLP_EN BUCK2_SLP_EN: BUCK2 enable in SLEEP mode OTP 1, Enable 0, Disable the default value is set by otp reset by power down or RST. BUCK1_SLP_EN BUCK1_SLP_EN: BUCK1 enable in SLEEP mode OTP 1, Enable 0, Disable the default value is set by otp reset by power down or RST. PMIC_POWER_SLP_EN1 Address: Operational Base + offset (0x00b6) Bit 7 Attr RW Reset Value Description LDO8_SLP_EN LDO8_SLP_EN: LDO8 enable in SLEEP mode OTP 1, Enable 0, Disable the default value is set by otp reset by power down or RST. Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 79 RK817 Datasheet Rev 1.01 Bit 6 5 4 3 2 1 0 Attr RW RW RW RW RW RW RW Reset Value Description LDO7_SLP_EN LDO7_SLP_EN: LDO7 enable in SLEEP mode OTP 1, Enable 0, Disable the default value is set by otp reset by power down or RST. LDO6_SLP_EN LDO6_SLP_EN: LDO6 enable in SLEEP mode OTP 1, Enable 0, Disable the default value is set by otp reset by power down or RST. LDO5_SLP_EN LDO5_SLP_EN: LDO5 enable in SLEEP mode OTP 1, Enable 0, Disable the default value is set by otp reset by power down or RST. LDO4_SLP_EN LDO4_SLP_EN: LDO4 enable in SLEEP mode OTP 1, Enable 0, Disable the default value is set by otp reset by power down or RST. LDO3_SLP_EN LDO3_SLP_EN: LDO3 enable in SLEEP mode OTP 1, Enable 0, Disable the default value is set by otp reset by power down or RST. LDO2_SLP_EN LDO2_SLP_EN: LDO2 enable in SLEEP mode OTP 1, Enable 0, Disable the default value is set by otp reset by power down or RST. LDO1_SLP_EN LDO1_SLP_EN: LDO1 enable in SLEEP mode OTP 1, Enable 0, Disable the default value is set by otp reset by power down or RST. PMIC_POWER_DISCHRG_EN0 Address: Operational Base + offset (0x00b7) Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 80 RK817 Datasheet Rev 1.01 Bit 7 6 5 4 3 2 1 0 Attr RW RW RW RW RW RW RW RW Reset Value Description RESV 0x1 RESV:Reserve OTG_DISCHG_EN OTG_DISCHG_EN: OTG discharge enable 0x1 when the channel is off 0: Disable 1:enable RESV 0x1 RESV:Reserve LDO9_DISCHG_EN LDO9_DISCHG_EN: LDO9 discharge enable 0x1 when the channel is off 0: Disable 1:enable BUCK4_DISCHG_EN BUCK4_DISCHG_EN: BUCK4 discharge 0x1 enable when the channel is off 0: Disable 1:enable BUCK3_DISCHG_EN BUCK3_DISCHG_EN: BUCK3 discharge 0x1 enable when the channel is off 0: Disable 1:enable BUCK2_DISCHG_EN BUCK2_DISCHG_EN: BUCK2 discharge 0x1 enable when the channel is off 0: Disable 1:enable BUCK1_DISCHG_EN BUCK1_DISCHG_EN: BUCK1 discharge 0x1 enable when the channel is off 0: Disable 1:enable PMIC_POWER_DISCHRG_EN1 Address: Operational Base + offset (0x00b8) Bit 7 6 5 Attr RW RW RW Reset Value Description LDO8_DISCHG_EN LDO8_DISCHG_EN: LDO8 discharge enable 0x1 when the channel is off 0: Disable 1:enable: LDO7_DISCHG_EN LDO7_DISCHG_EN: LDO7 discharge enable 0x1 when the channel is off 0: Disable 1:enable: LDO6_DISCHG_EN LDO6_DISCHG_EN: LDO6 discharge enable 0x1 when the channel is off 0: Disable 1:enable: Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 81 RK817 Datasheet Rev 1.01 Bit 4 3 2 1 0 Attr RW RW RW RW RW Reset Value Description LDO5_DISCHG_EN LDO5_DISCHG_EN: LDO5 discharge enable 0x1 when the channel is off 0: Disable 1:enable: LDO4_DISCHG_EN LDO4_DISCHG_EN: LDO4 discharge enable 0x1 when the channel is off 0: Disable 1:enable: LDO3_DISCHG_EN LDO3_DISCHG_EN: LDO3 discharge enable 0x1 when the channel is off 0: Disable 1:enable: LDO2_DISCHG_EN LDO2_DISCHG_EN: LDO2 discharge enable 0x1 when the channel is off 0: Disable 1:enable: LDO1_DISCHG_EN LDO1_DISCHG_EN: LDO1 discharge enable 0x1 when the channel is off 0: Disable 1:enable PMIC_POWER_CONFIG Address: Operational Base + offset (0x00b9) Bit 7 6 5 4 3 Attr RW RW RW RW RW Reset Value Description LDO_SLP_LP_EN LDO_SLP_LP_EN: Low power function 0x0 enable bit of LDO 0: disable 1:enable BUCK3_FB_RES BUKC3_FB_RES: BUCK3 feedback select 0x0 0: select external feedback resistor; 1: select internal feedback resistor BUCK_3VLDO_BYPASS_EN BUCK_3VLDO_BYPASS_EN:1:3V LDO disable 0x0 and short to VDD enable bit 0: disable 1:enable BUCK_3VLDO_LP_EN BUCK_3VLDO_LP_EN: Low power function 0x0 enable bit of 3VLDO 0: disable 1:enable BUCK4_LP_EN BUCK4_LP_EN: Low power function enable 0x0 bit of BUCK4 0: disable 1:enable Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 82 RK817 Datasheet Rev 1.01 Bit 2 1 0 Attr RW RW RW Reset Value Description BUCK3_LP_EN BUCK3_LP_EN: Low power function enable 0x0 bit of BUCK3 0: disable 1:enable BUCK2_LP_EN BUCK2_LP_EN: Low power function enable 0x0 bit of BUCK2 0: disable 1:enable BUCK1_LP_EN BUCK1_LP_EN: Low power function enable 0x0 bit of BUCK1 0: disable 1:enable PMIC_BUCK1_CONFIG Address: Operational Base + offset (0x00ba) Bit 7:6 5:3 2:0 Attr RW RW RW Reset Value Description BUCK1_RATE BUCK1_RATE<1:0>: BUCK1 voltage change rate after DVS 0x1 00: 3mV/uS; 01: 6.3mV/uS; 10:12.5mV/uS; 11: 25mV/uS reset by power down or RST. BUCK1_ILPK BUCK1_ILPK<2:0>: BUCK1 peak current limit select, MUST linkage adjustment with 0x4 the BUCK1_ILVL<2:0>(write the same code) 000:2A 010:2.25A 010:2.5A 011:2.75A 100:3A 110:3.25A 110:3.5A 111:3.75A reset by power down or RST. BUCK1_ILVL BUCK1_ILVL<2:0>: BUCK1 valley current limit select, linkage adjustment with the 0x4 BUCK1_ILPK<2:0>(write the same code) 000:2A 010:2.25A 010:2.5A 011:2.75A 100:3A 110:3.25A 110:3.5A 111:3.75A reset by power down or RST. PMIC_BUCK1_ON_VSEL Address: Operational Base + offset (0x00bb) Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 83 RK817 Datasheet Rev 1.01 Bit 7 6:0 Attr RW RW Reset Value Description BUCK1_ON_FPWM BUCK1_ON_FPWM: BUCK1 Forced PWM mode selection 0x0 1, Forced PWM mode in active mode; 0, PWM/PFM auto change mode reset by power down or RST. BUCK1_ON_VSEL BUCK1_ON_VSEL<6:0>: BUCK1 active mode voltage select 0000000:0.5V 0000001:0.5125V 0000010:0.525V ... OTP 1010000:1.5V 1010001:1.6V 1010010:1.7V ... 1011000:2.3V 1011001~1111111:2.4V the default value is set by otp reset by power down or RST. PMIC_BUCK1_SLP_VSEL Address: Operational Base + offset (0x00bc) Bit 7 6:0 Attr RW RW Reset Value Description BUCK1_SLP_FPWM BUCK1_SLP_FPWM: 0x0 1, Forced PWM mode in sleep mode. 0, PWM/PFM auto change mode. reset by power down or RST. BUCK1_SLP_VSEL BUCK1_SLP_VSEL<6:0>: BUCK1 SLEEP mode voltage select 0000000:0.5V 0000001:0.5125V 0000010:0.525V ... OTP 1010000:1.5V 1010001:1.6V 1010010:1.7V ... 1011000:2.3V 1011001~1111111:2.4V the default value is set byotp reset by power down or RST. Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 84 RK817 Datasheet Rev 1.01 PMIC_BUCK2_CONFIG Address: Operational Base + offset (0x00bd) Bit 7:6 5:3 2:0 Attr RW RW RW Reset Value Description BUCK2_RATE BUCK2_RATE<1:0>: BUCK2 voltage change rate after DVS 0x1 00: 3mV/uS; 01: 6.3mV/uS; 10:12.5mV/uS; 11: 25mV/uS reset by power down or RST. BUCK2_ILPK BUCK2_ILPK<2:0>: BUCK2 peak current limit select, MUST linkage adjustment with 0x4 the BUCK2_ILVL<2:0>(write the same code) 000:2A 010:2.25A 010:2.5A 011:2.75A 100:3A 110:3.25A 110:3.5A 111:3.75A reset by power down or RST. BUCK2_ILVL BUCK2_ILVL<2:0>: BUCK2 valley current limit select, linkage adjustment with the 0x4 BUCK2_ILPK<2:0>(write the same code) 000:2A 010:2.25A 010:2.5A 011:2.75A 100:3A 110:3.25A 110:3.5A 111:3.75A reset by power down or RST. PMIC_BUCK2_ON_VSEL Address: Operational Base + offset (0x00be) Bit 7 Attr RW Reset Value Description BUCK2_ON_FPWM BUCK2_ON_FPWM: BUCK2 Forced PWM mode selection 0x0 1, Forced PWM mode in active mode; 0, PWM/PFM auto change mode reset by power down or RST. Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 85 RK817 Datasheet Rev 1.01 Bit 6:0 Attr RW Reset Value Description BUCK2_ON_VSEL BUCK2_ON_VSEL<6:0>: BUCK2 active mode voltage select 0000000:0.5V 0000001:0.5125V 0000010:0.525V ... OTP 1010000:1.5V 1010001:1.6V 1010010:1.7V ... 1011000:2.3V 1011001~1111111:2.4V the default value is set by otp reset by power down or RST. PMIC_BUCK2_SLP_VSEL Address: Operational Base + offset (0x00bf) Bit 7 6:0 Attr RW RW Reset Value Description BUCK2_SLP_FPWM BUCK2_SLP_FPWM: 0x0 1, Forced PWM mode in sleep mode. 0, PWM/PFM auto change mode. reset by power down or RST. BUCK2_SLP_VSEL BUCK2_SLP_VSEL<6:0>: BUCK2 SLEEP mode voltage select 0000000:0.5V 0000001:0.5125V 0000010:0.525V ... OTP 1010000:1.5V 1010001:1.6V 1010010:1.7V ... 1011000:2.3V 1011001~1111111:2.4V the default value is set by otp reset by power down or RST. PMIC_BUCK3_CONFIG Address: Operational Base + offset (0x00c0) Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 86 RK817 Datasheet Rev 1.01 Bit 7:6 5:3 2:0 Attr RW RW RW Reset Value Description BUCK3_RATE BUCK3_RATE<1:0>: BUCK3 voltage change rate after DVS 0x1 00: 3mV/uS; 01: 6.3mV/uS; 10:12.5mV/uS; 11: 25mV/uS reset by power down or RST. BUCK3_ILPK BUCK3_ILPK<2:0>: BUCK3 peak current limit select, MUST linkage adjustment with 0x4 the BUCK3_ILVL<2:0>(write the same code) 000:1A 010:1.25A 010:1.5A 011:1.75A 100:2A 110:2.25A 110:2.5A 111:2.75A reset by power down or RST. BUCK3_ILVL BUCK3_ILVL<2:0>: BUCK3 valley current limit select, linkage adjustment with the 0x4 BUCK3_ILPK<2:0>(write the same code) 000:1A 010:1.25A 010:1.5A 011:1.75A 100:2A 110:2.25A 110:2.5A 111:2.75A reset by power down or RST. PMIC_BUCK3_ON_VSEL Address: Operational Base + offset (0x00c1) Bit 7 6:0 Attr RW RW Reset Value Description BUCK3_ON_FPWM BUCK3_ON_FPWM: BUCK3 Forced PWM mode selection 0x0 1, Forced PWM mode in active mode; 0, PWM/PFM auto change mode reset by power down or RST. BUCK3_ON_VSEL BUCK3_ON_VSEL<6:0>: BUCK3 active mode voltage select 0000000:0.5V 0000001:0.5125V 0000010:0.525V ... OTP 1010000:1.5V 1010001:1.6V 1010010:1.7V ... 1011000:2.3V 1011001~1111111:2.4V the default value is set by otp reset by power down or RST. Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 87 RK817 Datasheet Rev 1.01 PMIC_BUCK3_SLP_VSEL Address: Operational Base + offset (0x00c2) Bit 7 6:0 Attr RW RW Reset Value Description BUCK3_SLP_FPWM BUCK3_SLP_FPWM: 0x0 1, Forced PWM mode in sleep mode. 0, PWM/PFM auto change mode. reset by power down or RST. BUCK3_SLP_VSEL BUCK3_SLP_VSEL<6:0>: BUCK3 SLEEP mode voltage select 0000000:0.5V 0000001:0.5125V 0000010:0.525V ... OTP 1010000:1.5V 1010001:1.6V 1010010:1.7V ... 1011000:2.3V 1011001~1111111:2.4V the default value is set by otp reset by power down or RST. PMIC_BUCK4_CONFIG Address: Operational Base + offset (0x00c3) Bit 7:6 5:3 Attr RW RW Reset Value Description BUCK4_RATE BUCK4_RATE<1:0>: BUCK4 voltage change rate after DVS 0x1 00: 3mV/uS; 01: 6.3mV/uS; 10:12.5mV/uS; 11: 25mV/uS reset by power down or RST. BUCK4_ILPK BUCK4_ILPK<2:0>: BUCK4 peak current limit select, MUST linkage adjustment with 0x4 the BUCK4_ILVL<2:0>(write the same code) 000:1A 010:1.25A 010:1.5A 011:1.75A 100:2A 110:2.25A 110:2.5A 111:2.75A reset by power down or RST. Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 88 RK817 Datasheet Rev 1.01 Bit 2:0 Attr RW Reset Value Description BUCK4_ILVL BUCK4_ILVL<2:0>: BUCK4 valley current limit select, linkage adjustment with the 0x4 BUCK4_ILPK<2:0>(write the same code) 000:1A 010:1.25A 010:1.5A 011:1.75A 100:2A 110:2.25A 110:2.5A 111:2.75A reset by power down or RST. PMIC_BUCK4_ON_VSEL Address: Operational Base + offset (0x00c4) Bit 7 6:0 Attr RW RW Reset Value Description BUCK4_ON_FPWM BUCK4_ON_FPWM: BUCK4 Forced PWM mode selection 0x0 1, Forced PWM mode in active mode; 0, PWM/PFM auto change mode reset by power down or RST. BUCK4_ON_VSEL BUCK4_ON_VSEL<6:0>: BUCK4 active mode voltage select 0000000:0.5V 0000001:0.5125V 0000010:0.525V OTP ... 1010000:1.5V 1010001:1.6V 1010010:1.7V ... 1100011~1111111:3.4V the default value is set by otp reset by power down or RST. PMIC_BUCK4_SLP_VSEL Address: Operational Base + offset (0x00c5) Bit 7 Attr RW Reset Value Description BUCK4_SLP_FPWM BUCK4_SLP_FPWM: 0x0 1, Forced PWM mode in sleep mode. 0, PWM/PFM auto change mode. reset by power down or RST. Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 89 RK817 Datasheet Rev 1.01 Bit 6:0 Attr RW Reset Value Description BUCK4_SLP_VSEL BUCK4_SLP_VSEL<6:0>: BUCK4 SLEEP mode voltage select 0000000:0.5V 0000001:0.5125V 0000010:0.525V OTP ... 1010000:1.5V 1010001:1.6V 1010010:1.7V ... 1100011~1111111:3.4V the default value is set by otp reset by power down or RST. PMIC_BUCK4_CMIN Address: Operational Base + offset (0x00c6) Bit 7 6 5 4 3 Attr RW RW RW RW RW Reset Value Description SYSUV_DLY_SEL 0x0 SYSUV_DLY_SEL: Sys under voltage delay time selection 0: 5uS 1:50uS LDO3_UVSD_EN LDO3_UVSD_EN: SYSUV to shutdown the 0x0 LDO3 function 0:Disable 1:enable SYSUV_TRIG_RESETB_EN SYSUV_TRIG_RESETB_EN:SYSUV to trigger 0x0 restart the PMIC function 0:Disable 1:enable I2S_RX_MST I2S RX module as master mode(1)/slave 0x0 mode(0) reset by power down or RST. BUCK4_CMIN_EN BUCK4_CMIN_EN:BUCK4 min Current limit enable 0x0 1, Enable 0, Disable reset by power down or RST. Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 90 RK817 Datasheet Rev 1.01 Bit 2:1 0 Attr RW RW Reset Value Description BUCK4_CMIN_SEL BUCK4_CMIN_SEL<2:1>BUCK4 min Current limit select 0x2 reset by power down or RST. 00:200mA 01:300mA 10:400mA 11:500mA RESV 0x0 RESV: Reserve PMIC_LDO1_ON_VSEL Address: Operational Base + offset (0x00cc) Bit 7 6:0 Attr RW RW Reset Value Description LDO1_IMAX LDO1_IMAX:LDO1 current limit setting 0x0 0: normal, 1: 130% of nominal value reset by power down or RST. LDO1_ON_VSEL LDO1_ON_VSEL: LDO1 active mode voltage select, 0.6V~3.4V(step=25mV) 0000000:0.6V OTP 0000001:0.625V 0000010:0.65V ... 1110000~1111111:3.4V the default value is set by otp reset by power down or RST. PMIC_LDO1_SLP_VSEL Address: Operational Base + offset (0x00cd) Bit 7 6:0 Attr RW RW Reset Value Description RESV 0x0 RESV:Reserve LDO1_SLP_VSEL LDO1_SLP_VSEL:LDO1 SLEEP mode voltage select, 0.6V~3.4V(step=25mV) 0000000:0.6V OTP 0000001:0.625V 0000010:0.65V ... 1110000~1111111:3.4V the default value is set by otp reset by power down or RST. Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 91 RK817 Datasheet Rev 1.01 PMIC_LDO2_ON_VSEL Address: Operational Base + offset (0x00ce) Bit 7 6:0 Attr RW RW Reset Value Description LDO2_IMAX LDO2_IMAX:LDO2 current limit setting 0x0 0: normal, 1: 130% of nominal value reset by power down or RST. LDO2_ON_VSEL LDO2_ON_VSEL: LDO2 active mode voltage select, 0.6V~3.4V(step=25mV) 0000000:0.6V OTP 0000001:0.625V 0000010:0.65V ... 1110000~1111111:3.4V the default value is set by otp reset by power down or RST. PMIC_LDO2_SLP_VSEL Address: Operational Base + offset (0x00cf) Bit 7 6:0 Attr RW RW Reset Value Description RESV 0x0 RESV:Reserve LDO2_SLP_VSEL LDO2_SLP_VSEL:LDO2 SLEEP mode voltage select, 0.6V~3.4V(step=25mV) 0000000:0.6V OTP 0000001:0.625V 0000010:0.65V ... 1110000~1111111:3.4V the default value is set by otp reset by power down or RST. PMIC_LDO3_ON_VSEL Address: Operational Base + offset (0x00d0) Bit 7 Attr RW Reset Value Description LDO3_IMAX LDO3_IMAX:LDO3 current limit setting 0x0 0: normal, 1: 130% of nominal value reset by power down or RST. Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 92 RK817 Datasheet Rev 1.01 Bit 6:0 Attr RW Reset Value Description LDO3_ON_VSEL LDO3_ON_VSEL: LDO3 active mode voltage select, 0.6V~3.4V(step=25mV) 0000000:0.6V OTP 0000001:0.625V 0000010:0.65V ... 1110000~1111111:3.4V the default value is set by otp reset by power down or RST. PMIC_LDO3_SLP_VSEL Address: Operational Base + offset (0x00d1) Bit 7 6:0 Attr RW RW Reset Value Description RESV 0x0 RESV:Reserve LDO3_SLP_VSEL LDO3_SLP_VSEL:LDO3 SLEEP mode voltage select, 0.6V~3.4V(step=25mV) 0000000:0.6V OTP 0000001:0.625V 0000010:0.65V ... 1110000~1111111:3.4V the default value is set by otp reset by power down or RST. PMIC_LDO4_ON_VSEL Address: Operational Base + offset (0x00d2) Bit 7 Attr RW Reset Value Description LDO4_IMAX LDO4_IMAX:LDO4 current limit setting 0x0 0: normal, 1: 130% of nominal value reset by power down or RST. Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 93 RK817 Datasheet Rev 1.01 Bit 6:0 Attr RW Reset Value Description LDO4_ON_VSEL LDO4_ON_VSEL: LDO4 active mode voltage select, 0.6V~3.4V(step=25mV) 0000000:0.6V OTP 0000001:0.625V 0000010:0.65V ... 1110000~1111111:3.4V the default value is set by otp reset by power down or RST. PMIC_LDO4_SLP_VSEL Address: Operational Base + offset (0x00d3) Bit 7 6:0 Attr RW RW Reset Value Description RESV 0x0 RESV:Reserve LDO4_SLP_VSEL LDO4_SLP_VSEL:LDO4 SLEEP mode voltage select, 0.6V~3.4V(step=25mV) 0000000:0.6V OTP 0000001:0.625V 0000010:0.65V ... 1110000~1111111:3.4V the default value is set by otp reset by power down or RST. PMIC_LDO5_ON_VSEL Address: Operational Base + offset (0x00d4) Bit 7 Attr RW Reset Value Description LDO5_IMAX LDO5_IMAX:LDO5current limit setting 0x0 0: normal, 1: 130% of nominal value reset by power down or RST. Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 94 RK817 Datasheet Rev 1.01 Bit 6:0 Attr RW Reset Value Description LDO5_ON_VSEL LDO5_ON_VSEL: LDO5 active mode voltage select, 0.6V~3.4V(step=25mV) 0000000:0.6V OTP 0000001:0.625V 0000010:0.65V ... 1110000~1111111:3.4V the default value is set by otp reset by power down or RST. PMIC_LDO5_SLP_VSEL Address: Operational Base + offset (0x00d5) Bit 7 6:0 Attr RW RW Reset Value Description RESV 0x0 RESV:Reserve LDO5_SLP_VSEL LDO5_SLP_VSEL:LDO5 SLEEP mode voltage select, 0.6V~3.4V(step=25mV) 0000000:0.6V OTP 0000001:0.625V 0000010:0.65V ... 1110000~1111111:3.4V the default value is set by otp reset by power down or RST. PMIC_LDO6_ON_VSEL Address: Operational Base + offset (0x00d6) Bit 7 Attr RW Reset Value Description LDO6_IMAX LDO6_IMAX:LDO6 current limit setting 0x0 0: normal, 1: 130% of nominal value reset by power down or RST. Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 95 RK817 Datasheet Rev 1.01 Bit 6:0 Attr RW Reset Value Description LDO6_ON_VSEL LDO6_ON_VSEL: LDO6 active mode voltage select, 0.6V~3.4V(step=25mV) 0000000:0.6V OTP 0000001:0.625V 0000010:0.65V ... 1110000~1111111:3.4V the default value is set by otp reset by power down or RST. PMIC_LDO6_SLP_VSEL Address: Operational Base + offset (0x00d7) Bit 7 6:0 Attr RW RW Reset Value Description RESV 0x0 RESV:Reserve LDO6_SLP_VSEL LDO6_SLP_VSEL:LDO6 SLEEP mode voltage select, 0.6V~3.4V(step=25mV) 0000000:0.6V OTP 0000001:0.625V 0000010:0.65V ... 1110000~1111111:3.4V the default value is set by otp reset by power down or RST. PMIC_LDO7_ON_VSEL Address: Operational Base + offset (0x00d8) Bit 7 Attr RW Reset Value Description LDO7_IMAX Field0000 Abstract LDO7_IMAX:LDO7 current limit setting 0x0 0: normal, 1: 130% of nominal value reset by power down or RST. Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 96 RK817 Datasheet Rev 1.01 Bit 6:0 Attr RW Reset Value Description LDO7_ON_VSEL LDO7_ON_VSEL: LDO7 active mode voltage select, 0.6V~3.4V(step=25mV) 0000000:0.6V OTP 0000001:0.625V 0000010:0.65V ... 1110000~1111111:3.4V the default value is set by otp reset by power down or RST. PMIC_LDO7_SLP_VSEL Address: Operational Base + offset (0x00d9) Bit 7 6:0 Attr RW RW Reset Value Description RESV 0x0 RESV:Reserve LDO7_SLP_VSEL LDO7_SLP_VSEL:LDO7 SLEEP mode voltage select, 0.6V~3.4V(step=25mV) 0000000:0.6V OTP 0000001:0.625V 0000010:0.65V ... 1110000~1111111:3.4V the default value is set by otp reset by power down or RST. PMIC_LDO8_ON_VSEL Address: Operational Base + offset (0x00da) Bit 7 Attr RW Reset Value Description LDO8_IMAX LDO8_IMAX:LDO8 current limit setting 0x0 0: normal, 1: 130% of nominal value reset by power down or RST. Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 97 RK817 Datasheet Rev 1.01 Bit 6:0 Attr RW Reset Value Description LDO8_ON_VSEL Field0000 Abstract LDO8_ON_VSEL: LDO8 active mode voltage select, 0.6V~3.4V(step=25mV) 0000000:0.6V OTP 0000001:0.625V 0000010:0.65V ... 1110000~1111111:3.4V the default value is set by otp reset by power down or RST. PMIC_LDO8_SLP_VSEL Address: Operational Base + offset (0x00db) Bit 7 6:0 Attr RW RW Reset Value Description RESV 0x0 RESV:Reserve LDO8_SLP_VSEL LDO8_SLP_VSEL:LDO8 SLEEP mode voltage select, 0.6V~3.4V(step=25mV) 0000000:0.6V OTP 0000001:0.625V 0000010:0.65V ... 1110000~1111111:3.4V the default value is set by otp reset by power down or RST. PMIC_LDO9_ON_VSEL Address: Operational Base + offset (0x00dc) Bit 7 Attr RW Reset Value Description LDO9_IMAX LDO9_IMAX:LDO9 current limit setting 0x0 0: normal, 1: 130% of nominal value reset by power down or RST. Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 98 RK817 Datasheet Rev 1.01 Bit 6:0 Attr RW Reset Value Description LDO9_ON_VSEL LDO9_ON_VSEL: LDO9 active mode voltage select, 0.6V~3.4V(step=25mV) 0000000:0.6V OTP 0000001:0.625V 0000010:0.65V ... 1110000~1111111:3.4V the default value is set by otp reset by power down or RST. PMIC_LDO9_SLP_VSEL Address: Operational Base + offset (0x00dd) Bit 7 6:0 Attr RW RW Reset Value Description RESV 0x0 RESV:Reserve LDO9_SLP_VSEL LDO9_SLP_VSEL:LDO9 SLEEP mode voltage select, 0.6V~3.4V(step=25mV) 0000000:0.6V OTP 0000001:0.625V 0000010:0.65V ... 1110000~1111111:3.4V the default value is set by otp reset by power down or RST. PMIC_BOOST_OTG_CONFIG0 Address: Operational Base + offset (0x00de) Bit 7:6 5 4:3 Attr RW RW RW Reset Value Description OTG_ILIM OTG_ILIM: OTG current limit selection 0x0 00: 1A 01:1.5A 10:1.8A 11: 2.1A reset by power down or RST. RESV 0x0 Reserved BOOST_ILMAX BOOST_ILMAX:BOOST inductor peak current 0x1 setting 00:2.5A 01:3A 10:4A 11:5A reset by power down or RST. Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 99 RK817 Datasheet Rev 1.01 Bit 2:0 Attr RW Reset Value Description BOOST_ON_VSEL BOOST_ON_VSEL:BOOST active mode voltage select. OTP 000:4.7V 001:4.8V 010:4.9V 011:5V 100:5.1V 101:5.2V 110:5.3V 111:5.4V the default value is set by otp reset by power down or RST. PMIC_BOOST_CONFIG1 Address: Operational Base + offset (0x00df) Bit 7:5 4:3 2:0 Attr RW RW RW Reset Value Description RESV 0x1 Reserved BOOST_ZCD BOOST_ZCD<1:0>: BOOSTzero current 0x2 detection select 00:50mA 01: 100mA 10:150mA 11:200mA BOOST_SLP_VSEL BOOST_SLP_VSEL:BOOST SLEEP mode voltage select. OTP 000: 4.7V; 001: 4.8V; 010: 4.9V; 011: 5.0V 100: 5.1V; 101: 5.2V; 110: 5.3V; 111: 5.4V the default value is set by otp reset by power down or RST. PMIC_CHRG_OUT Address: Operational Base + offset (0x00e4) Bit 7 6:4 3 2:0 Attr RW RW RW RW Reset Value Description POWERPATH_EN 0x1 PWOERPATH_EN: PWOERPATH enable signal 0:disable 1: enable CHRG_VOL_SEL CHRG_VOL_SEL: charger voltage selection 0x2 000:4.1V 001:4.15V 010:4.2V 011:4.25V 100:4.3V 101:4.35; 110:4.4V; 111:4.45V CHRG_CT_EN CHRG_CT_EN:Charger Thermal foldback 0x0 enable 0:disable 1:enable CHRG_CUR_SEL CHRG_CUR_SEL: charger current selection 0x2 000:1A 001:1.5A 010:2A 011:2.5A 100:2.75A 101:3A 110:3.5A 111:0.5A Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 100 RK817 Datasheet Rev 1.01 PMIC_CHRG_IN Address: Operational Base + offset (0x00e5) Bit 7 6:4 3 2:0 Attr RW RW RW RW Reset Value Description USB_VLIM_EN USB_VLIM_EN: whether the USB input 0x1 voltage limit function is enable 0:disable 1: enable USB_VLIM_SEL USB_VLIM_SEL: the USB input voltage limit 0x4 selection 000:4.0V 001:4.1V 010:4.2V 011:4.3V 100:4.4V 101:4.5V 110:4.6V 111:4.7V USB_ILIM_EN USB_ILIM_EN: whether the USB input 0x1 current limit function is enable 0:disable 1: enable USB_ILIM_SEL USB_ILIM_SEL: the USB input average OTP current limit selection 000:0.45 001:0.08A 010:0.85A 011:1.5A 100:1.75A 101:2A 110:2.5A 111:3A the default value is set by OTP. PMIC_CHRG_TERM Address: Operational Base + offset (0x00e6) Bit 7 6 5:4 3 2 Attr RW RW RW RW RW Reset Value Description SYS_CAN_SD SYS_CAN_SD:whether the system voltage 0x1 can be shutdown in Bat_off mode 0:not 1:yes CHRG_EN CHRG_EN: enable charger 0x1 0:disable 1:enable reset by power down or RST. RESV 0x0 RESV:Reserve BAT_OVP_EN 0x0 BAT_OVP_EN: BAT OVP ENABLE 0:disable 1: enable CHRG_TERM_ANA_DIG CHRG_TERM_ANA_DIG:charger termination 0x1 adjustment selection 0: analog 1:digital Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 101 RK817 Datasheet Rev 1.01 Bit 1:0 Attr RW Reset Value Description CHRG_TERM_ANA_SEL CHRG_TERM_ANA_SEL: analog charging 0x1 termination selection 00:150mA 01:200mA 10:300mA 11:400mA PMIC_CHRG_TERM_DIG Address: Operational Base + offset (0x00e7) Bit 7:0 Attr RW Reset Value Description CHRG_TERM_DIG 0x20 CHRG_TERM_DIG: CHRG TERM DIGITAL CURRENT SELLECT Compared with BAT_CUR<12:5> PMIC_BAT_HTS_TS Address: Operational Base + offset (0x00e8) Bit 7:0 Attr RW Reset Value Description BAT_HTS_TS BAT_HTS_TS: battery high temperature protection in TS 0x00 according to ADC SPEC, high 8bit of ADC value, the external resistor is negative temperature coefficient, so BAT_HTS_TS<BAT_LTS_TS PMIC_BAT_LTS_TS Address: Operational Base + offset (0x00e9) Bit 7:0 Attr RW Reset Value Description BAT_LTS_TS BAT_LTS_TS: battery low temperature protection in TS 0xff according to ADC SPEC,high 8bit of ADC value, the external resistor is negative temperature coefficient, so BAT_HTS_TS<BAT_LTS_TS PMIC_CHRG_TO Address: Operational Base + offset (0x00ea) Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 102 RK817 Datasheet Rev 1.01 Bit 7 6:4 3 2:0 Attr RW RW RW RW Reset Value Description CHRG_TIMER_TRIKL_EN CHRG_TIMER_TRIKL_EN: trickle charging 0x0 timer enable, 0:disable 1:enable CHRG_TIMER_TRIKL CHRG_TIMER_TRIKL: trickle charge timer selection 0x2 000:30min 001:45min 010:60min 011:90min 100:120min 101:150min 110:180min 111:210min CHRG_TIMER_CCCV_EN CHRG_TIMER_CCCV_EN: Constant current 0x0 and Constant voltage charging timer enable, 0:disable 1:enable CHRG_TIMER_CCCV CHRG_TIMER_CCCV:CC CV charge timer 0x2 selection 000:4h 001:5h 010:6h 011:8h 100:10h 101:12h 110:14h 111:16h PMIC_CHRG_STS Address: Operational Base + offset (0x00eb) Bit 7 6:4 3 2 Attr RO RO RO RO Reset Value Description BAT_EXS BAT_EXS:bat exists (only writable at test 0x0 mode) 0:Not exists 1:exists CHG_STS CHG_STS: charging status 000: charge off 001:dead charge 0x0 010:trickle charge 011: CC or CV charge 100:charge TERM 101:USB over voltage 110:BAT temperature error 111:BAT time error BAT_OVP_STS 0x0 BAT_OVP_STS:BAT OVP happen, this bit will be set high. CHRG_IN_CLAMP CHRG_IN_CLAMP: When charger incc, incv 0x0 or constant temperature happen, this bit will be set "1" Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 103 RK817 Datasheet Rev 1.01 Bit 1 0 Attr RO RO Reset Value Description USB_EXS USB_EXS:USB exists (only writable at test 0x0 mode) 0: Not exists, 1: exists USB_EFF USB_EFF:USB is effective (only writable 0x0 at test mode) 0: Not effective, 1: effective PMIC_BAT_DISCHRG Address: Operational Base + offset (0x00ec) Bit 7 6 5:4 3 2:0 Attr RW RO RW RW RW Reset Value Description RESV 0x0 RESV:Reserve BAT_DIS_ILIM_STS 0x0 BAT_DIS_ILIM_STS:When bat discharge current is limited, this bit will be set high. BAT_SYS_CMP_DLY BAT_SYS_CMP_DLY:bat and system 0x0 comparator delay time 00:5uS 10:10uS 01:25uS 11:30uS BAT_DIS_ILIM_EN BAT_DIS_ILIM_EN:the bat discharger 0x1 current limit function enable 0:disable 1:enalbe BAT_DISCHRG_ILIM BAT_DISCHRG_ILIM:battery discharge 0x2 current limit 000:2A 001:2.5A 010:3A 011 3.5A 1xx:4A PMIC_CHIP_NAME Address: Operational Base + offset (0x00ed) Bit 7:0 Attr RO Reset Value Description CHIP_NAME 0x81 CHIP_NAME:CHIP name code<11:4>. RK817: default 81 PMIC_CHIP_VER Address: Operational Base + offset (0x00ee) Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 104 RK817 Datasheet Rev 1.01 Bit 7:4 3:0 Attr RO RO Reset Value Description CHIP_NAME 0x7 CHIP_NAME:CHIP name code<3:0>. RK817: default 7 CHIP_VER 0x2 CHIP_VER:CHIP version code<3:0>, from 1 to 15. PMIC_OTP_VER Address: Operational Base + offset (0x00ef) Bit 7:6 5:4 3:0 Attr RW RO RO Reset Value Description LDO1P8A_VSEL 0x0 LDO1P8A_VSEL: VCC_1P8A voltage select 00: 1.8V 01: 1.6V 10: 1.9V 11:2.0V RESV 0x0 RESV:Reserve OTP_VER OTP OTP_VER: OTP revize version. default OTP. PMIC_SYS_STS Address: Operational Base + offset (0x00f0) Bit 7 6 5 4 3 Attr RO RO RO RO RO Reset Value Description PWRON_STS PWRON_STS: PWRON key status 0x0 0: PWRON not press 1:PWRON button pressed reset by power down or RST PLUG_IN_STS PLUG_IN_STS: USB plug-in event occurs(USB voltage >3.8V after pull down 0x0 20mA current) 0: no USB plug in 1: USB plugged in VB_UV_STS 0x0 VB_UV_STS: Battery under voltage lockout status VB_LO_STS VB_LO_STS: Battery low voltage status 0x0 0: VBAT>VB_LO_SEL 1: VBAT<VB_LO_SEL HOTDIE_STS 0x0 HOTDIE_STS: Hot-die warning Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 105 RK817 Datasheet Rev 1.01 Bit 2 1 0 Attr RO RO RO Reset Value Description TSD_STS 0x0 TSD_STS: Thermal shut down BAT_HI_STS 0x0 BAT_HI_STS:battery higher than USB status bit SYS_OV_STS 0x0 SYS_OV_STS: system over voltage status bit PMIC_SYS_CFG0 Address: Operational Base + offset (0x00f1) Bit 7 6:4 3 2:0 Attr RW RW RW RW Reset Value Description SYS_OV_EN SYS_OV_EN: SYS over voltage function 0x1 enable 0:disable 1:enable VB_UV_SEL VB_UV_SEL:SYS shut down voltage select, 2.7V~3.4V, step=100mV 0x0 000:2.7V; 001:2.8V; 010:2.9V; 011:3.0V 100:3.1V; 101:3.2V; 110:3.3V; 111:3.4V reset by power down or RST VB_LO_ACT VB_LO_ACT: SYS low volatge action 0x1 0: shut down system 1: insert interrupt reset by power down or RST VB_LO_SEL VB_LO_SEL: SYS low voltage threshold,2.8V~3.5V, step=100mV 0x4 000:2.8V; 001:2.9V; 010:3.0V; 011:3.1V 100:3.2V; 101:3.3V; 110:3.4V; 111:3.5V reset by power down or RST PMIC_SYS_CFG1 Address: Operational Base + offset (0x00f2) Bit 7 Attr RW Reset Value Description CLK32KOUT_EN CLK32KOUT_EN: CLK32K output is enable 0x1 1. enable 0. disable reset by power down or RST Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 106 RK817 Datasheet Rev 1.01 Bit 6 5:4 3 2 1 0 Attr RW RW RW RW RW RW Reset Value Description TSD_TEMP TSD_TEMP: Thermal shutdown temperature 0x0 threshold 0: 140; 1: 160 reset by power down or RST HOTDIE_TEMP HOTDIE_TEMP: Hot-die temperature 0x0 threshold 00:85 01:95 10:105 11:115 reset by power down or RST SYS_OV_SD_EN SYS_OV_SD_EN: Shut down the BUCK1~4 0x0 mosfet if the SYS OV happens 0:Disable 1:Enable SYS_OV_SD_TIME SYS_OV_SD_TIME: SYS OV comparator 0x0 delay time selection 0: 8uS 1:30uS USB_OV_SD_EN USB_OV_SD_EN: Shut down the charger 0x0 mosfet if the USB OV happens 0:Disable 1:Enable USB_OV_SD_TIME USB_OV_SD_TIME: USB OV comparator 0x0 delay time selection 0: 8uS 1:60uS PMIC_SYS_CFG2 Address: Operational Base + offset (0x00f3) Bit 7 6 5 Attr RW RW RW Reset Value Description ADC_PHASE ADC_PHASE: ADC phase select 0x0 0: normal 1: reverse CHRG_CLK_SEL CHRG_CLK_SEL: charger clock select 0x1 0:1Meg 1:2Meg HK_BG_SUP_SEL HK_BG_SUP_SEL: house keeping band gap 0x0 supply select 0:VCCRTC 1: Internal LDO Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 107 RK817 Datasheet Rev 1.01 Bit 4 3 2 1 0 Attr RW RW RW RW RW Reset Value Description HK_REF_RES_SEL HK_REF_RES_SEL: house keeping reference 0x0 filter resistor select 0:100% 1:200% HK_REF_LP_EN HK_REF_LP_EN: house keeping reference 0x0 lower power enable 1. enable 0. disable USB_OV_SEL USB_OV_SEL: usb over voltage threshold 0x0 select 0: 6V 1: 5.8V SYS_UV_PRE_DLY SYS_UV_PRE_DLY: SYS under voltage delay 0x0 time select 0:1.5uS 1:5uS USB_OV_DLY USB_OV_DLY: usb over voltage delay time 0x0 select 0: 5uS 1:3uS PMIC_SYS_CFG3 Address: Operational Base + offset (0x00f4) Bit 7:6 5 Attr RW RW Reset Value Description RST_FUN: reset function selection: 00: Restart the PMU. 0x0 01: reset DCDC and LDO. (Do not use this mode when SLEEP.) 1x: Do not use. SLP_POL SLP_POL: SLEEP pin polarity 0x1 0:active low 1:active high reset by power down or RST Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 108 RK817 Datasheet Rev 1.01 Bit 4:3 2 1 0 Attr RW RW RW RW Reset Value Description SLP_FUN SLP_FUN: SLEEP PIN function selection: 00: not effect; 01: sleep function; 0x0 10:shutdown function; 11:restart pmu function. reset by power down or RST DEV_RST DEV_RST: Write 1 will 'RST' the device. 0x0 Note: 'RST' is not only a reset source, but a special function defined by 'RST_FUN' reset by power down or RST DEV_SLP 0x0 DEV_SLP: Write 1 will go to SLEEP state. reset by power down or RST DEV_OFF 0x0 DEV_OFF: Write 1 will shutdown the device. reset by power down or RST PMIC_ON_SOURCE Address: Operational Base + offset (0x00f5) Bit 7 6 5 4 3 2 Attr RO RO RO RO RO RO Reset Value Description ON_PWRON ON_PWRON: PRESS PWRON to turn on PMU 0x0 reset by power down or RST, and load this bit after reset. ON_PLUG_IN 0x0 ON_PLUG_IN:USB PLUG IN to turn on PMU reset by power down or RST ON_RTC 0x0 ON_RTC:RTC timer to turn on PMU reset by power down or RST RESTART_RESETB RESTART_RESETB:PULL LOW the RESETB 0x0 PIN to restart the PMU reset by power down or RST RESTART_PWRON_LP RESTART_PWRON_LP:Long press PWRON to 0x0 restart the PMU reset by power down or RST RESTART_SLP RESTART_SLP:SLEEP PIN ACTIVE to restart 0x0 the PMU reset by power down or RST Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 109 RK817 Datasheet Rev 1.01 Bit 1 0 Attr RW RO Reset Value Description RESTART_DEV_RST RESTART_DEV_RST: I2C write DEV_RST to 0x0 restart PMU reset by power down or RST RESV 0x0 RESV: Reserve PMIC_OFF_SOURCE Address: Operational Base + offset (0x00f6) Bit 7 6 5 4 3 2 1 Attr RO RO RO RO RO RO RO Reset Value Description OFF_SLP OFF_SLP: SLEEP PIN ACTIVE to turn off PMU 0x0 reset by power down or RST, and load this bit after reset. OFF_SYS_OV OFF_SYS_OV:SYS OV to turn off PMU 0x0 reset by power down or RST, and load this bit after reset. OFF_TSD OFF_TSD:TSD to turn off PMU 0x0 reset by power down or RST, and load this bit after reset. OFF_VB_UV OFF_VB_UV:SYS UV to turn off PMU 0x0 reset by power down or RST, and load this bit after reset. OFF_DEV_OFF OFF_DEV_OFF:I2C write DEV_OFF to turn off 0x0 PMU reset by power down or RST, and load this bit after reset. OFF_PWRON_LP OFF_PWRON_LP:long press PWRON to turn 0x0 off PMU reset by power down or RST, and load this bit after reset. OFF_USB_EFF_NOT OFF_USB_EFF_NOT: USB OV or UV to turn 0x0 off PMU when BUCK MODE reset by power down or RST, and load this bit after reset. Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 110 RK817 Datasheet Rev 1.01 Bit 0 Attr RO Reset Value Description OFF_VB_LO OFF_VB_LO:SYS Low (if VB_LO_ACT=0)to 0x0 turn off PMU reset by power down or RST, and load this bit after reset. PMIC_PWRON_KEY Address: Operational Base + offset (0x00f7) Bit 7 6 5:4 3:2 1:0 Attr RW RW RW RW RW Reset Value Description PWRON_ON_TIME OTP PWRON_ON_TIME:0:500mS; 1:100mS default OTP. PWRON_LP_ACT PWRON_LP_ACT: PWRON long press act 0x0 0: turn off 1: turn off and then restart PWRON_LP_OFF_TIME PWRON_LP_OFF_TIME: PWRON long press 0x0 time: 00: 6s, 01: 8s, 10: 10s, 11: 12s PWRON_LP_TM PWRON_LP_TM_SEL<1:0>:PWRON long 0x1 press interrupt time selection: 00: 0.5S 01:1S 10:1.5S 11:2S PWRON_DB_SEL PWRON_DB_SEL<1:0>:PWRON interrupt 0x2 debounce time selection: 00: 32uS 01:10mS 10:20mS 11:40mS PMIC_INT_STS0 Address: Operational Base + offset (0x00f8) Bit 7 6 5 Attr W1C W1C W1C Reset Value Description VB_LO_INT VB_LO_INT: Battery under voltage alarm 0x0 event interrupt status. reset by power down or RST. RTC_PERIOD_INT RTC_PERIOD_INT: RTC period event 0x0 interrupt. reset by power down or RST. RTC_ALARM_INT 0x0 RTC_ALARM_INT: RTC alarm event interrupt. reset by power down or RST. Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 111 RK817 Datasheet Rev 1.01 Bit 4 3 2 1 0 Attr W1C W1C W1C W1C W1C Reset Value Description HOTDIE_INT HOTDIE_INT: Hot die event interrupt 0x0 status. reset by power down or RST. PWRON_LP_INT PWRON_LP_INT: PWRON PIN long press 0x0 event interrupt status. reset by power down or RST. PWRON_INT PWRON_INT: PWRON event interrupt 0x0 status. reset by power down or RST. PWRON_RISE_INT PWRON_RISE_INT:PWRON rising event 0x0 interrupt reset by power down or RST. PWRON_FALL_INT PWRON_FALL_INT:PWRON falling event 0x0 interrupt reset by power down or RST. PMIC_INT_MSK0 Address: Operational Base + offset (0x00f9) Bit 7 6 5 4 3 Attr RW RW RW RW RW Reset Value Description VB_LO_IM VB_LO_IM: Battery under voltage alarm 0x0 event interrupt mask reset by power down or RST. RTC_PERIOD_IM RTC_PERIOD_IM: RTC period event interrupt 0x0 mask reset by power down or RST. RTC_ALARM_IM RTC_ALARM_IM: RTC alarm event interrupt 0x0 mask reset by power down or RST. HOTDIE_IM 0x0 HOTDIE_IM: Hot die event interrupt mask reset by power down or RST. PWRON_LP_IM PWRON_LP_IM: PWRON PIN long press 0x0 event interrupt mask reset by power down or RST. Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 112 RK817 Datasheet Rev 1.01 Bit 2 1 0 Attr RW RW RW Reset Value Description PWRON_IM 0x0 PWRON_IM:PWRON event interrupt mask reset by power down or RST. PWRON_RISE_INT_IM PWRON_RISE_INT_IM:PWRON rising event 0x0 interrupt mask reset by power down or RST. PWRON_FALL_INT_IM PWRON_FALL_INT_IM:PWRON falling event 0x0 interrupt mask reset by power down or RST. PMIC_INT_STS1 Address: Operational Base + offset (0x00fa) Bit 7 6 5 4 3 2 Attr W1C W1C W1C W1C W1C W1C Reset Value Description BAT_DIS_ILIM_INT BAT_DIS_ILIM_INT:Battery discharge 0x0 current over the setting value event interrupt. reset by power down or RST. CHRG_IN_CLMP_INT CHRG_IN_CLMP_INT:Charger USB input 0x0 current limit or USB input voltage limit or chip constant temperature event interrupt (write 1 clear or POWERPATH_EN=0 clear) USB_OV_INT USB_OV_INT:USB over voltage event 0x0 interrupt (write 1 clear or POWERPATH_EN=0 clear) CHRG_TS_INT CHRG_TS_INT:Charger TS over or under 0x0 temperature event interrupt (write 1 clear or POWERPATH_EN=0 clear) CHRG_TIME_INT CHRG_TIME_INT:Charger time error event 0x0 interrupt (write 1 clear or POWERPATH_EN=0 clear) CHRG_TERM__INT CHRG_TERM__INT:Charger finished event 0x0 interrupt (write 1 clear or POWERPATH_EN=0 clear) Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 113 RK817 Datasheet Rev 1.01 Bit 1 0 Attr W1C W1C Reset Value Description PLUG_OUT_INT PLUG_OUT_INT: USB plug out event 0x0 interrupt reset by power down or RST. PLUG_IN_INT 0x0 PLUG_IN_INT: USB plug in event interrupt reset by power down or RST. PMIC_INT_MSK1 Address: Operational Base + offset (0x00fb) Bit 7 6 5 4 3 2 1 0 Attr RW RW RW RW RW RW RW RW Reset Value Description BAT_DIS_ILIM_INT_IM BAT_DIS_ILIM_INT_IM:Battery discharge 0x0 current over the setting value event interrupt mask. reset by power down or RST. CHRG_IN_CLMP_INT_IM CHRG_IN_CLMP_INT_IM:Charger USB input 0x0 current limit or USB input voltage limit or chip constant temperature event interrupt mask. USB_OV_INT_IMUSB_OV_INT_IM:USB over 0x0 voltage event interrupt mask CHRG_TS_INT_IM 0x0 CHRG_TS_INT_IM:Charger TS over or under temperature event interrupt mask CHRG_TIME_INT_IM 0x0 CHRG_TIME_INT_IM:Charger time error event interrupt mask CHRG_TERM_INT_IM 0x0 CHRG_TERM_INT_IM:Charger finished event interrupt mask PLUG_OUT_INT_IM PLUG_OUT_INT_IM: USB plug out event 0x0 interrupt mask reset by power down or RST. PLUG_IN_INT_IM PLUG_IN_INT_IM: USB plug in event 0x0 interrupt mask reset by power down or RST. PMIC_INT_STS2 Address: Operational Base + offset (0x00fc) Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 114 RK817 Datasheet Rev 1.01 Bit 7 6 5 4 3 2 1 0 Attr RC W1C W1C W1C W1C W1C W1C W1C Reset Value Description CHRG_BAT_HI_INT 0x0 CHRG_BAT_HI_INT: BAT HI interrupt. reset by power down or RST. BAT_OVP_INT 0x0 BAT_OVP_INTBAT OVP interrupt. reset by power down or RST. CLASSD_OCP_INT 0x0 CLASSD_OCP_INT:CLASS D OCP interrupt. reset by power down or RST. CLASSD_MUTE_DONE CLASSD_MUTE_DONE_INT:CLASSD_MUTE_D 0x0 ONE interrupt. reset by power down or RST. CODEC_PO_INT CODEC_PO_INT: CODEC ANTI-POP DAC 0x0 SMART POWER ON DONE interrupt. reset by power down or RST. CODEC_PD_INT CODEC_PD_INT: CODEC ANTI-POP DAC 0x0 SMART POWER OFF DONE interrupt. reset by power down or RST. TS_GPIO_INT TS_GPIO_INT: TS_GPIO PIN input signal 0x0 posedge or negedge interrupt. reset by power down or RST. GATE_GPIO_INT GATE_GPIO_INT: GATE_GPIO PIN input 0x0 signal posedge or negedge interrupt. reset by power down or RST. PMIC_INT_MSK2 Address: Operational Base + offset (0x00fd) Bit 7 6 5 Attr RW RW RW Reset Value Description CHRG_BAT_HI_INT_IM CHRG_BAT_HI_INT_IM:BAT HI interrupt 0x0 mask. reset by power down or RST. BAT_OVP_INT_IM 0x0 BAT_OVP_INT_IM:BAT OVP interrupt mask. reset by power down or RST. CLASSD_OCP_INT_IM CLASSD_OCP_INT_IM:CLASS D OCP 0x0 interrupt mask. reset by power down or RST. Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 115 RK817 Datasheet Rev 1.01 Bit 4 3 2 1 0 Attr RW RW RW RW RW Reset Value Description CLASSD_MUTE_DONE_IM CLASSD_MUTE_DONE_IM:CLASSD_MUTE_D 0x0 ONE interrupt mask. reset by power down or RST. CODEC_PO_INT_IM CODEC_PO_INT_IM:CODEC ANTI-POP DAC 0x0 SMART POWER ON DONE interrupt mask. reset by power down or RST. CODEC_PD_INT_IM CODEC_PD_INT_IM:CODEC ANTI-POP DAC 0x0 SMART POWER OFF DONE interrupt mask. reset by power down or RST. TS_GPIO_INT_IM TS_GPIO_INT_IM: TS_GPIO PIN input 0x0 signal posedge or negedge interrupt mask. reset by power down or RST. GATE_GPIO_INT_IM GATE_GPIO_INT_IM: GATE_GPIO PIN input 0x0 signal posedge or negedge interrupt mask. reset by power down or RST. PMIC_GPIO_INT_CONFIG Address: Operational Base + offset (0x00fe) Bit 7 6 5 4 3 Attr RW RW RW RW RW Reset Value Description GATE_GPIO_IO GATE_GPIO_IO: GPIO IO definition 0x0 0: Input 1: Output, pull high to VCC_RTC GATE_GPIO_DATA 0x0 GATE_GPIO_DATA: if GATE pin is GPIO function, it's the data buffer GATE_GPIO_FUN GATE_GPIO_FUN: GATE pin function 0x1 0: GATE function 1:GPIO function TS_GPIO_IO TS_GPIO_IO: TS GPIO IO definition 0x0 0: Input 1: Output, pull high to VCC_RTC TS_GPIO_DATA 0x0 TS_GPIO_DATA: if TS pin is GPIO function, it's the data buffer Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 116 RK817 Datasheet Rev 1.01 Bit 2 1 0 Attr RW RW RW Reset Value Description TS_GPIO_FUN TS_GPIO_FUN: TS pin function 0x0 0: TS function 1:GPIO function INT_POL INT_POL: INT pin polarity 0x1 0: active low 1: active high reset by power down or RST. INT_FC_EN INT_FC_EN:interrupt watchdog function enable 0x0 0:disable 1:enable reset by power down or RST. Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 117 RK817 Datasheet Rev 1.01 Chapter 6 Thermal Management 6.1 Overview For reliability and operability concerns, the absolute maximum junction temperature of RK817 has to be below 125ºC. Depending on the thermal mechanical design (Smartphone, Tablet, Personal Navigation Device, etc), the system thermal management software and worst case thermal applications, the junction temperature might be exposed to higher values than those specified above. Therefore, it is recommended to perform thermal simulations at device level (Smartphone, Tablet, Personal Navigation Device, etc) with the measured power of the worst case UC of the device. 6.2 Package Thermal Characteristics Table 6-1 provides the thermal resistance characteristics for the package used on this device. PACKAGE (QFN7X7-68) RK817 Table 6-1 Thermal Resistance Characteristics POWER(W) (/) (/) 2 21.99 12 (/) 6.58 Note: The testing PCB is based on 4 layers, 114mm x 76 mm, 1.6mm thickness, Ambient temperature is 85°C. Copyright ©2018 Fuzhou Rockchip Electronics Co., Ltd. 118Microsoft Word 2016 Microsoft Word 2016