ALINX 芯驿电子科技（上海）有限公司
User Manual for ALINX models including: FL9627, FL9627 FMC 4 Channel High Speed AD Module, FMC 4 Channel High Speed AD Module, 4 Channel High Speed AD Module, High Speed AD Module, AD Module, Module
6 / 17 . www.alinx.com. FMC 4-channel High Speed AD Module FL9627 User Manual . Figure 2-2 ： Input voltage conversation The following table is a comparison of the analog input signal and the
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DocumentDocumentFMC 4-Channel High Speed AD Module FL9627 User Manual FMC 4-channel High Speed AD Module FL9627 User Manual Table of Contents Part1: FL9627 4-channle High Speed Module General Description............ 3 Part 1.1: FL9627 Module Detail Parameter ......................................... 4 Part 1.2: FL9627 Module Size Dimension ........................................... 4 Part 2: FL9627 Module Function Description.............................................. 5 Part 2.1: FL9627 Module Block Diagram ............................................. 5 Part 2.2: Operational amplifier Circuit on the FL9627 Module ............. 5 Part 2.3: Single-ended to differential and AD conversion..................... 6 Part 2.4: FL9627 digital output timing .................................................. 7 Part 2.5: FL9627 LVDS standard ......................................................... 8 Part 2.6: FL9627 Module FMC LPC pin assignment ........................... 9 Part 3: DEMO program description for AD sampling................................. 13 Part4: Hardware Connection and Testing ................................................. 15 2 / 17 www.alinx.com FMC 4-channel High Speed AD Module FL9627 User Manual Part1: FL9627 4-channel High Speed AD Module General Description ALINX FMC High Speed AD Module FL9627 is a 4-channel 125MSPS, 12-bit analog to digital signal conversion module. The FMC AD conversion module uses two AD9627 chips from Analog Devices. Each AD9627 chip supports two AD input conversions, so the two AD9627 chips support a total of four AD input conversions. The analog signal input has a voltage range of -5V to +5V and the interface is an SMA socket. The module has a standard LPC FMC interface for connecting to the FPGA development board. The FMC connector model is: ASP_134604_01 Figure 1-1: FL9627 module product photo 3 / 17 www.alinx.com FMC 4-channel High Speed AD Module FL9627 User Manual Part 1.1: FL9627 Module Detail Parameter FL9627 FMC 4-channel high speed AD Module detail parameter listed as below: AD Conversion chip: 2 pieces AD9627 AD Conversion channel: 4 channels AD update rate: 125MSPS AD bits: 12 digits Digital interface level standard: LVDS level of +1.8V AD analog signal input range: -5V~+5V; Analog signal input interface: SMA interface Configuration interface: SPI interface Working temperature: -40 °C ~ 85 °C Part 1.2: FL9627 Module Size Dimension Figure 1-2: FL9627 FMC 4-channel High Speed AD Module Size Dimension 4 / 17 www.alinx.com FMC 4-channel High Speed AD Module FL9627 User Manual Part 2: FL9627 Module Function Description Part 2.1: FL9627 Module Block Diagram FMC LPC Connector SPI LVDS Dual AD chip AD9627 125M Clock Differential conversion SPI LVDS Dual AD chip AD9627 AD8138 Op amp AD8055 AD8138 Op amp AD8055 Single-ended to differential AD8138 Op amp AD8055 AD8138 Op amp AD8055 AD1 Input SMA Interface AD2 Input SMA Interface AD3 Input SMA Interface AD4 Input SMA Interface 125M Clock Differential conversion Figure 2-1: FL9627 Module Block Diagram For the circuit design of the AD9627, please refer to the chip manual of the AD9267. Part 2.2: Operational amplifier Circuit on the FL9627 Module The FPGA development board uses a 300Mhz bandwidth AD8055 chip and a voltage divider resistor to reduce the voltage of the -5V~+5V input to -1V~+1V. If the user wants to input a wider range of voltage inputs, simply modify the resistance of the front-end divider resistor. 5 / 17 www.alinx.com FMC 4-channel High Speed AD Module FL9627 User Manual Figure 2-2Input voltage conversation The following table is a comparison of the analog input signal and the voltage of the AD8055 op amp output: AD analog input value AD8055 op amp output -5V 0V +5V -1V 0V +1V Part 2.3: Single-ended to differential and AD conversion The input voltage of -1V~+1V is converted into a differential signal (VIN+ - VIN-) by the AD8138 chip. The common mode level of the differential signal is determined by the CML pin of AD. Figure 2-3Compressed input voltage conversation to differential signal 6 / 17 www.alinx.com FMC 4-channel High Speed AD Module FL9627 User Manual The following table shows the voltage comparison table after the analog input signal to the differential output of the AD8138: AD analog input value AD8055 op amp output AD8138 Differential Output (VIN+-VIN-) -5V -1V +1V 0V 0V 0V +5V +1V -1V If AD is configured as Offset Binary Output Mode, the value of AD conversion is as shown below: In the module circuit design, the VREF value of the AD9627 is 1V, so the final analog signal input and AD conversion data are as follows: AD analog input AD8055 op amp value output AD8138 Differential Output (VIN+-VIN-) AD9627 digital output -5V 0V +5V -1V 0V +1V +1V 0V -1V 11111111111 100000000000 000000000000 From the table we can see that the AD9627 converts the largest digital value when the -5V input, and the digital value converted by the AD9627 is the smallest when the +5V input. Part 2.4: FL9627 digital output timing The digital output of the AD9627 dual AD are configured as a +1.8V LVDS output mode. The two channels (A and B) share a pair of differential clock 7 / 17 www.alinx.com FMC 4-channel High Speed AD Module FL9627 User Manual signals and 12 pairs of differential data signals. The order of data output is alternate output, one AD is output on the rising edge of the clock, and the other AD data is output on the falling edge of the clock. Figure 2-4FL9627 digital output timing Part 2.5: FL9627 LVDS standard From the chip manual of the AD9627, we can see that the level standard of the +1.8V LVDS output by the AD9627 is as follows: The level standard of the +2.5V LVDS input of the FPGA chip is as follows: The differential signal output from the AD9627 fully meets the +2.5V LVDS input level standard of the FPGA. 8 / 17 www.alinx.com FMC 4-channel High Speed AD Module FL9627 User Manual Part 2.6: FL9627 Module FMC LPC pin assignment Only the signals of the power supply and interface are listed below. The signal of GND is not listed. For details, please refer to the schematic. Pin Number C35 C37 D32 C34 D35 D8 G6 G7 H7 H8 C10 C11 D11 D12 H10 H11 C14 C15 G12 G13 H13 9 / 17 Signal Name +12V +12V +3.3V GA0 GA1 CLK1_125M AD1_DCO+ AD1_DCO- AD1_DO+ AD1_DOAD1_D1+ AD1_D1- AD1_D2+ AD1_D2AD1_D3+ AD1_D3AD1_D4+ AD1_D4AD1_D5+ AD1_D5AD1_D6+ Description 12V Power Input 12V Power Input 3.3V Power Input Bit0 of EEPROM address Bit1 of EEPROM address 125M reference clock input for the AD1 chip Data clock output P of AD1 channel A and channel B LVDS Data clock output N of AD1 channel A and channel B LVDS Data 0 Output -P for AD1 Channel A and Channel B LVDS Data 0 Output -N for AD1 Channel A and Channel B LVDS Data 1 Output -P for AD1 Channel A and Channel B LVDS Data 1 Output -N for AD1 Channel A and Channel B LVDS Data 2 Output -P for AD1 Channel A and Channel B LVDS Data 2 Output -N for AD1 Channel A and Channel B LVDS Data 3 Output -P for AD1 Channel A and Channel B LVDS Data 3 Output -N for AD1 Channel A and Channel B LVDS Data 4 Output -P for AD1 Channel A and Channel B LVDS Data 4 Output -N for AD1 Channel A and Channel B LVDS Data 5 Output -P for AD1 Channel A and Channel B LVDS Data 5 Output -N for AD1 Channel A and Channel B LVDS Data 6 Output -P for AD1 Channel A and Channel B LVDS www.alinx.com H14 D14 D15 G15 G16 H16 H17 D17 D18 C18 C19 G9 G10 D9 G19 G18 D20 C22 C23 G21 G22 H22 H23 10 / 17 FMC 4-channel High Speed AD Module FL9627 User Manual AD1_D6AD1_D7+ AD1_D7AD1_D8+ AD1_D8AD1_D9+ AD1_D9AD1_D10+ AD1_D10AD1_D11+ AD1_D11AD1_SPI_CS AD1_SPI_SDIO AD1_SPI_SCLK AD1_SMI_SCLK AD1_SMI_SDFS CLK2_125M AD2_DCO+ AD2_DCOAD2_DO+ AD2_DOAD2_D1+ AD2_D1- Data 6 Output -N for AD1 Channel A and Channel B LVDS Data 7 Output -P for AD1 Channel A and Channel B LVDS Data 7 Output -N for AD1 Channel A and Channel B LVDS Data 8 Output -P for AD1 Channel A and Channel B LVDS Data 8 Output -N for AD1 Channel A and Channel B LVDS Data 9 Output -P for AD1 Channel A and Channel B LVDS Data 9 Output -N for AD1 Channel A and Channel B LVDS Data 10 Output -P for AD1 Channel A and Channel B LVDS Data 10 Output -N for AD1 Channel A and Channel B LVDS Data 11 Output -P for AD1 Channel A and Channel B LVDS Data 11 Output -N for AD1 Channel A and Channel B LVDS SPI communication chip select signal for AD1 chip SPI communication data signal of AD1 chip SPI communication clock signal of AD1 chip AD1 monitor signal serial output clock signal AD1 monitor signal serial output data frame sync signal 125M reference clock input for the AD2 chip Data clock output P of AD2 channel A and channel B LVDS Data clock output N of AD2 channel A and channel B LVDS Data 0 Output -P for AD2 Channel A and Channel B LVDS Data 0 Output -N for AD2 Channel A and Channel B LVDS Data 1 Output -P for AD2 Channel A and Channel B LVDS Data 1 Output -N for AD2 Channel A and Channel B LVDS www.alinx.com C26 C27 G24 G25 H25 H26 D26 D27 G27 G28 H28 H29 G30 G31 H31 H32 G33 G34 H34 D21 D23 D24 G37 11 / 17 FMC 4-channel High Speed AD Module FL9627 User Manual AD2_D2+ AD2_D2AD2_D3+ AD2_D3AD2_D4+ AD2_D4AD2_D5+ AD2_D5AD2_D6+ AD2_D6AD2_D7+ AD2_D7AD2_D8+ AD2_D8AD2_D9+ AD2_D9AD2_D10+ AD2_D10AD2_D11+ AD2_SPI_CS AD2_SPI_SDIO AD2_SPI_SCLK AD2_SMI_SCLK Data 2 Output -P for AD2 Channel A and Channel B LVDS Data 2 Output -N for AD2 Channel A and Channel B LVDS Data 3 Output -P for AD2 Channel A and Channel B LVDS Data 3 Output -N for AD2 Channel A and Channel B LVDS Data 4 Output -P for AD2 Channel A and Channel B LVDS Data 4 Output -N for AD2 Channel A and Channel B LVDS Data 5 Output -P for AD2 Channel A and Channel B LVDS Data 5 Output -N for AD2 Channel A and Channel B LVDS Data 6 Output -P for AD2 Channel A and Channel B LVDS Data 6 Output -N for AD2 Channel A and Channel B LVDS Data 7 Output -P for AD2 Channel A and Channel B LVDS Data 7 Output -N for AD2 Channel A and Channel B LVDS Data 8 Output -P for AD2 Channel A and Channel B LVDS Data 8 Output -N for AD2 Channel A and Channel B LVDS Data 9 Output -P for AD2 Channel A and Channel B LVDS Data 9 Output -N for AD2 Channel A and Channel B LVDS Data 10 Output -P for AD2 Channel A and Channel B LVDS Data 10 Output -N for AD2 Channel A and Channel B LVDS Data 11 Output -P for AD2 Channel A and Channel B LVDS SPI communication chip select signal for AD2 chip SPI communication data signal of AD2 chip SPI communication clock signal of AD2 chip AD2 monitor signal serial output clock signal www.alinx.com FMC 4-channel High Speed AD Module FL9627 User Manual G36 AD2_SMI_SDFS AD2 monitor signal serial output data frame sync signal H37 AD2_SMI_SDO AD2 chip monitor signal serial output data signal H20 AD_SYNC Digital synchronization signal C30 SCL EEPROM I2C clock C31 SDA EEPROM I2C data G39 VADJ VADJ power input H40 VADJ VADJ power input 12 / 17 www.alinx.com FMC 4-channel High Speed AD Module FL9627 User Manual Part 3: DEMO program description for AD sampling We provide the AD acquisition and display routines for the ALINX FPGA development board, in which the differential LVDS clock signals and differential LVDS data signals from the two AD9627 inputs are converted to single-ended signals by the IBUFDS module, respectively. Then converted to A channel 12-bit data and B-channel 12-bit data by the IDDR module. The 12-bit data of the A channel and the B channel are observed by the ILA online debug. After power on, the AD9267 register needs to be configured. Here, the SPI bus is used to configure the register for each AD9267 chip, so that the AD9627 operates in LVDS mode. The functional block diagram of the FPGA AD testing is as follows: ILA FPGA AD1 Register Configuration Table SPI Controller SPI Interface ADC1_DATA_A ADC1_CLK IBUFDS ADC1_CLK_P/N ADC1_DATA_B IDDR ADC1_DATA IBUFDS ADC1_DATA_P/ ADC1_DATA_N AD9627 1 PLL AD1 Register Configuration Table SPI Controller SP ILA ADC2_ ADC2_ AD IBUFDS IDDR ADC IBUFDS ADC2_ ADC2_DATA_P/ ADC2_DATA_N AD9627 Figure 3-1: The functional block diagram of the FPGA AD Testing The following is a brief introduction to the functions of each module used in the FPGA program: 13 / 17 www.alinx.com FMC 4-channel High Speed AD Module FL9627 User Manual 1) lut_config.v The AD9627 register configuration table, where only two register values are configured, one is register 0x14 and the other is register 0x FF. Register 0x14 is configured as an LVDS output format and the output is in offset binary mode. After register 0x14, you need to write 1 to the lowest bit of the 0xFF register to take effect. Specific register meanings refer to the AD9627 chip manual. 2) spi_config.v This module configures the AD9627 chip registers by calling the SPI communication module (adc_spi.v). The configured register address and value are defined in the lut_config.v file. 3) top.v The top module implements the following functions in addition to the submodules above: Calling PLL IP to generate the 125Mhz reference clock required for the AD9627 chip Call IBUFDS to convert LVDS differential clock signals and data signals into single-ended clocks and single-ended data. Call IDDR to realize double-edge A and B channel data conversion 14 / 17 www.alinx.com FMC 4-channel High Speed AD Module FL9627 User Manual to single-edge A channel data and B channel data 4) Xdc constraint file The xdc constraint file defines two AD communication pins and an ILA debug interface. The user can modify the ILA interface signal to observe the signal he wants to observe. Part4: Hardware Connection and Testing The hardware connection between the FL9627 module and the FPGA development board is very simple. Simply plug the FL9627 FMC interface into the FMC interface of the FPGA development board and fix it with screws. The following is the hardware connection of the ALINX AX7325 development board and FL9627: After power on the FPGA development board, the signal generator generates a positive selection wave of -5V~+5V, the frequency is 200Khz, and then downloads the program in the Vivado environment. Figure 4-1: Hardware connection of ALINX AX7325 and FL9627: The interface of hw_ila_1 will appear here, and the AD acquisition data of channel A and channel B of the first AD module will be displayed in the hw_ila_1 15 / 17 www.alinx.com FMC 4-channel High Speed AD Module FL9627 User Manual interface. Click the "Run trigger mode for this ILA core" button and the adc1_data_a_d0 channel will display the positive selection wave. Figure 4-2: The interface of hw_ila_1 Change the signal transmitter to generate a square wave of -5V~+5V, and then click the "Run trigger mode for this ILA core" button. The adc1_data_a_d0 channel will display a square wave. We can see that when +5V is used, the data collected by AD is 04e, and the data collected by AD when -5V is fb3. Figure 3-1: Hardware Connection In the VIVADO software development environment, download the binocular Figure 4-3: Square wave If the user needs to measure the waveform of another AD2, the analog signals needs to be input to channel A or channel B of AD2. Then double-click hw_ila_2 to display the interface of hw_ila_2. 16 / 17 www.alinx.com FMC 4-channel High Speed AD Module FL9627 User Manual Figure 4-4: The interface of hw_ila_2 17 / 17 www.alinx.com