CC2652R SimpleLink™ Multiprotocol 2.4 GHz Wireless MCU datasheet (Rev. F)
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CC2652R
SWRS207F JANUARY 2018 REVISED SEPTEMBER 2019
CC2652R SimpleLinkTM Multiprotocol 2.4 GHz Wireless MCU
1 Device Overview
1.1 Features
1
· Microcontroller Powerful 48-MHz Arm® Cortex®-M4F processor EEMBC CoreMark® score: 148 352KB of in-system Programmable Flash 256KB of ROM for protocols and library functions 8KB of Cache SRAM (Alternatively available as general-purpose RAM) 80KB of ultra-low leakage SRAM. The SRAM is protected by parity to ensure high reliability of operation. 2-Pin cJTAG and JTAG debugging Supports Over-the-Air upgrade (OTA)
· Ultra-low power sensor controller with 4KB of SRAM Sample, store, and process sensor data Operation independent from system CPU Fast wake-up for low-power operation
· TI-RTOS, drivers, Bootloader, Bluetooth® 5 Low Energy Controller, and IEEE 802.15.4 MAC in ROM for optimized application size
· RoHS-compliant package 7-mm × 7-mm RGZ VQFN48 (31 GPIOs)
· Peripherals Digital peripherals can be routed to any GPIO 4× 32-bit or 8× 16-bit general-purpose timers 12-Bit ADC, 200 kSamples/s, 8 channels 2× comparators with internal reference DAC (1× continuous time, 1× ultra-low power) Programmable current source 2× UART 2× SSI (SPI, MICROWIRE, TI) I2C I2S Real-Time Clock (RTC) AES 128- and 256-bit Crypto Accelerator ECC and RSA Public Key Hardware Accelerator SHA2 Accelerator (Full suite up to SHA-512) True Random Number Generator (TRNG) Capacitive sensing, up to 8 channels Integrated temperature and battery monitor
· External system
On-chip Buck DC/DC converter
· Low power
Wide supply voltage range: 1.8 V to 3.8 V
Active-Mode RX: 6.9 mA
Active-Mode TX 0 dBm: 7.3 mA
Active-Mode TX 5 dBm: 9.6 mA
Active-Mode MCU 48 MHz (CoreMark): 3.4 mA (71 A/MHz)
Sensor Controller, Low Power-Mode, 2 MHz, running infinite loop: 30.8 A
Sensor Controller, Active-Mode, 24 MHz, running infinite loop: 808 A
Standby: 0.94 µA (RTC on, 80KB RAM and CPU retention)
Shutdown: 150 nA (wakeup on external events)
· Radio section
2.4 GHz RF transceiver compatible with Bluetooth 5 Low Energy and IEEE 802.15.4 PHY and MAC
Excellent receiver sensitivity: 100 dBm for 802.15.4 (2.4 GHz), 105 dBm for Bluetooth 125-kbps (LE Coded PHY)
Output power up to +5 dBm with temperature compensation
Suitable for systems targeting compliance with worldwide radio frequency regulations
EN 300 328, (Europe)
EN 300 440 Category 2
FCC CFR47 Part 15
ARIB STD-T66 (Japan)
· Wireless protocols Thread, Zigbee®, Bluetooth® 5 Low Energy, IEEE 802.15.4g, IPv6-enabled smart objects (6LoWPAN), Wi-SUN®, proprietary systems, SimpleLinkTM TI 15.4-Stack (2.4 GHz), and Dynamic Multiprotocol Manager (DMM) driver.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
CC2652R
SWRS207F JANUARY 2018 REVISED SEPTEMBER 2019
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· Development Tools and Software CC26x2R LaunchPadTM Development Kit SimpleLinkTM CC13x2 and CC26x2 Software Development Kit (SDK)
1.2 Applications
· 2400 to 2480 MHz ISM and SRD systems (1) with down to 4 kHz of receive bandwidth
· Building automation Building security systems motion detector, electronic smart lock, door and window sensor, garage door system, gateway HVAC thermostat, wireless environmental sensor, HVAC system controller, gateway Fire safety system smoke and heat detector, fire alarm control panel (FACP) Video surveillance IP network camera Elevators and escalators elevator main control panel for elevators and escalators
(1) See RF Core for additional details on supported protocol standards, modulation formats, and data rates.
SmartRFTM Studio for simple radio configuration Sensor Controller Studio for building low-power
sensing applications
· Grid infrastructure Smart meters water meter, gas meter, electricity meter, and heat cost allocators Grid communications wireless communications Long-range sensor applications Other alternative energy energy harvesting
· Industrial transport asset tracking · Factory automation and control · Medical · Electronic point of sale (EPOS) Electronic Shelf
Label (ESL)
1.3 Description
The CC2652R device is a multiprotocol 2.4 GHz wireless microcontroller (MCU) targeting Thread, Zigbee®, Bluetooth® 5 Low Energy, IEEE 802.15.4g, IPv6-enabled smart objects (6LoWPAN), proprietary systems, including the SimpleLinkTM TI 15.4-Stack (2.4 GHz), and concurrent multiprotocol through a Dynamic Multiprotocol Manager (DMM) driver. The device is optimized for low-power wireless communication and advanced sensing in building security systems, HVAC, and medical markets. The highlighted features of this device include:
· Wide flexibility of protocol stack support in the SimpleLinkTM CC13x2 and CC26x2 Software Development Kit (SDK).
· Longer battery life wireless applications with low standby current of 0.94 µA with full RAM retention.
· Industrial temperature ready with lowest standby current of 11 µA at 105 C.
· Advanced sensing with a programmable, autonomous ultra-low power Sensor Controller CPU with fast wake-up capability. As an example, the sensor controller is capable of 1-Hz ADC sampling at 1 µA system current.
· Low SER (Soft Error Rate) FIT (Failure-in-time) for long operation lifetime with no disruption for industrial markets with always-on SRAM parity against corruption due to potential radiation events.
· Dedicated software controlled radio controller (Arm® Cortex®-M0) providing flexible low-power RF transceiver capability to support multiple physical layers and RF standards.
· Excellent radio sensitivity and robustness (selectivity and blocking) performance for Bluetooth® Low Energy (-105 dBm for 125-kbps LE Coded PHY).
The CC2652R device is part of the SimpleLinkTM microcontroller (MCU) platform, which consists of Wi-Fi®, Bluetooth® Low Energy, Thread, Zigbee®, Sub-1 GHz MCUs, and host MCUs that all share a common, easy-to-use development environment with a single core software development kit (SDK) and rich tool set. A one-time integration of the SimpleLinkTM platform enables you to add any combination of the portfolio's devices into your design, allowing 100 percent code reuse when your design requirements change. For more information, visit SimpleLinkTM MCU platform.
2
Device Overview
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CC2652R
SWRS207F JANUARY 2018 REVISED SEPTEMBER 2019
PART NUMBER
Device Information(1)
PACKAGE
BODY SIZE (NOM)
CC2652R1FRGZ
VQFN (48)
7.00 mm × 7.00 mm
(1) For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 9, or see the TI website.
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1.4 Functional Block Diagram
CC26x2R
2.4 GHz
Main CPU
Arm® Cortex®-M4F
Processor
48 MHz 71 µA/MHz (3.0 V)
cJTAG
256KB ROM
Up to 352KB Flash with 8KB Cache
Up to 80KB SRAM with Parity
General Hardware Peripherals and Modules
I2C and I2S
4× 32-bit Timers
2× UART
2× SSI (SPI)
32 ch. µDMA
Watchdog Timer
31 GPIOs AES-256, SHA2-512
ECC, RSA
TRNG
Temperature and Battery Monitor
RTC
LDO, Clocks, and References Optional DC/DC Converter
RF Core
ADC ADC
Digital PLL
DSP Modem
Arm® Cortex®-M0 Processor
16KB SRAM
ROM
Sensor Interface ULP Sensor Controller
8-bit DAC 12-bit ADC, 200 ks/s 2x Low-Power Comparator SPI-I2C Digital Sensor IF Capacitive Touch IF Time-to-Digital Converter
4KB SRAM
Figure 1-1. CC2652R Block Diagram
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Device Overview
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CC2652R
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Table of Contents
1 Device Overview ......................................... 1 1.1 Features .............................................. 1 1.2 Applications........................................... 2 1.3 Description............................................ 2 1.4 Functional Block Diagram ............................ 4
2 Revision History ......................................... 5 3 Device Comparison ..................................... 6 4 Terminal Configuration and Functions.............. 7
4.1 Pin Diagram RGZ Package (Top View) ............ 7 4.2 Signal Descriptions RGZ Package ................. 8 4.3 Connections for Unused Pins and Modules .......... 9 5 Specifications ........................................... 10 5.1 Absolute Maximum Ratings ......................... 10 5.2 ESD Ratings ........................................ 10 5.3 Recommended Operating Conditions............... 10 5.4 Power Supply and Modules ......................... 10 5.5 Power Consumption - Power Modes ............... 11 5.6 Power Consumption - Radio Modes ............... 12 5.7 Nonvolatile (Flash) Memory Characteristics ........ 12 5.8 Thermal Resistance Characteristics ................ 13 5.9 Bluetooth Low Energy - Receive (RX) .............. 14 5.10 Bluetooth Low Energy - Transmit (TX).............. 17
5.11 Zigbee and Thread - IEEE 802.15.4-2006 2.4 GHz
(OQPSK DSSS1:8, 250 kbps) - RX................. 18
5.12 Zigbee and Thread - IEEE 802.15.4-2006 2.4 GHz
(OQPSK DSSS1:8, 250 kbps) - TX ................. 19 5.13 Timing and Switching Characteristics ............... 20 5.14 Peripheral Characteristics ........................... 24 5.15 Typical Characteristics .............................. 32
6 Detailed Description ................................... 47 6.1 Overview ............................................ 47 6.2 System CPU ........................................ 47 6.3 Radio (RF Core)..................................... 48 6.4 Memory.............................................. 49 6.5 Sensor Controller ................................... 50 6.6 Cryptography ........................................ 51 6.7 Timers ............................................... 52 6.8 Serial Peripherals and I/O........................... 53 6.9 Battery and Temperature Monitor................... 53 6.10 µDMA................................................ 53 6.11 Debug ............................................... 53 6.12 Power Management................................. 54 6.13 Clock Systems ...................................... 55 6.14 Network Processor .................................. 55
7 Application, Implementation, and Layout ......... 56 7.1 Reference Designs.................................. 56 7.2 Junction Temperature Calculation .................. 57
8 Device and Documentation Support ............... 58 8.1 Tools and Software.................................. 58 8.2 Documentation Support ............................. 60 8.3 Support Resources.................................. 61 8.4 Trademarks.......................................... 61 8.5 Electrostatic Discharge Caution..................... 61 8.6 Glossary ............................................. 61
9 Mechanical, Packaging, and Orderable
Information .............................................. 61 9.1 Packaging Information .............................. 61
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (July 2019) to Revision F
Page
· Added Wireless protocols to Section 1.1 .......................................................................................... 1 · Changed Section 1.2 ................................................................................................................. 2 · Changed Section 1.3 ................................................................................................................. 2 · Added Section 7.2 .................................................................................................................. 57
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Revision History
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3 Device Comparison
DEVICE CC1312R CC1352P
CC1352R CC2642R CC2652R
CC2652RB
CC2652P CC1310 CC1350 CC2640R2F CC2640R2F-Q1
Table 3-1. Device Family Overview
RADIO SUPPORT
Sub-1 GHz
Multiprotocol Sub-1 GHz Bluetooth 5 Low Energy
Zigbee Thread 2.4 GHz proprietary FSK-based formats +20-dBm high-power amplifier
Multiprotocol Sub-1 GHz Bluetooth 5 Low Energy
Zigbee Thread 2.4 GHz proprietary FSK-based formats
Bluetooth 5 Low Energy 2.4 GHz proprietary FSK-based formats
Multiprotocol Bluetooth 5 Low Energy
Zigbee Thread 2.4 GHz proprietary FSK-based formats
Multiprotocol Bluetooth 5 Low Energy
Zigbee Thread 2.4 GHz proprietary FSK-based formats
Multiprotocol Bluetooth 5 Low Energy
Zigbee Thread 2.4 GHz proprietary FSK-based formats +19.5-dBm high-power amplifier
FLASH (KB)
352
RAM (KB)
80
352
80
352
80
352
80
352
80
352
80
352
80
GPIO 30 26
28 31 31 31
26
Sub-1 GHz
32128 1620 1031
Sub-1 GHz Bluetooth 4.2 Low Energy
128
20
1031
Bluetooth 5 Low Energy 2.4 GHz proprietary FSK-based formats
128
Bluetooth 5 Low Energy 2.4 GHz proprietary FSK-based formats
128
20
1031
20
31
PACKAGE SIZE RGZ (7-mm × 7-mm VQFN48)
RGZ (7-mm × 7-mm VQFN48)
RGZ (7-mm × 7-mm VQFN48)
RGZ (7-mm × 7-mm VQFN48)
RGZ (7-mm × 7-mm VQFN48)
RGZ (7-mm × 7-mm VQFN48)
RGZ (7-mm × 7-mm VQFN48)
RGZ (7-mm × 7-mm VQFN48) RHB (5-mm × 5-mm VQFN32) RSM (4-mm × 4-mm VQFN32) RGZ (7-mm × 7-mm VQFN48) RHB (5-mm × 5-mm VQFN32) RSM (4-mm × 4-mm VQFN32) RGZ (7-mm × 7-mm VQFN48) RHB (5-mm × 5-mm VQFN32) RSM (4-mm × 4-mm VQFN32) YFV (2.7-mm × 2.7-mm DSBGA34) RGZ (7-mm × 7-mm VQFN48)
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Device Comparison
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4 Terminal Configuration and Functions 4.1 Pin Diagram RGZ Package (Top View)
CC2652R
SWRS207F JANUARY 2018 REVISED SEPTEMBER 2019
48 VDDR_RF 47 X48M_P 46 X48M_N 45 VDDR 44 VDDS 43 DIO_30 42 DIO_29 41 DIO_28 40 DIO_27 39 DIO_26 38 DIO_25 37 DIO_24
RF_P 1 RF_N 2 X32K_Q1 3 X32K_Q2 4 DIO_0 5 DIO_1 6 DIO_2 7 DIO_3 8 DIO_4 9 DIO_5 10 DIO_6 11 DIO_7 12
36 DIO_23 35 RESET_N 34 VDDS_DCDC 33 DCDC_SW 32 DIO_22 31 DIO_21 30 DIO_20 29 DIO_19 28 DIO_18 27 DIO_17 26 DIO_16 25 JTAG_TCKC
VDDS2 13 DIO_8 14 DIO_9 15 DIO_10 16 DIO_11 17 DIO_12 18 DIO_13 19 DIO_14 20 DIO_15 21 VDDS3 22 DCOUPL 23 JTAG_TMSC 24
Figure 4-1. RGZ (7-mm × 7-mm) Pinout, 0.5-mm Pitch (Top View)
The following I/O pins marked in Figure 4-1 in bold have high-drive capabilities: · Pin 10, DIO_5 · Pin 11, DIO_6 · Pin 12, DIO_7 · Pin 24, JTAG_TMSC · Pin 26, DIO_16 · Pin 27, DIO_17
The following I/O pins marked in Figure 4-1 in italics have analog capabilities: · Pin 36, DIO_23 · Pin 37, DIO_24 · Pin 38, DIO_25 · Pin 39, DIO_26 · Pin 40, DIO_27 · Pin 41, DIO_28 · Pin 42, DIO_29 · Pin 43, DIO_30
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4.2 Signal Descriptions RGZ Package
PIN
NAME
NO.
DCDC_SW
33
DCOUPL
23
DIO_0
5
DIO_1
6
DIO_2
7
DIO_3
8
DIO_4
9
DIO_5
10
DIO_6
11
DIO_7
12
DIO_8
14
DIO_9
15
DIO_10
16
DIO_11
17
DIO_12
18
DIO_13
19
DIO_14
20
DIO_15
21
DIO_16
26
DIO_17
27
DIO_18
28
DIO_19
29
DIO_20
30
DIO_21
31
DIO_22
32
DIO_23
36
DIO_24
37
DIO_25
38
DIO_26
39
DIO_27
40
DIO_28
41
DIO_29
42
DIO_30
43
EGP
--
JTAG_TMSC
24
JTAG_TCKC
25
RESET_N
35
RF_P
1
RF_N
2
Table 4-1. Signal Descriptions RGZ Package
I/O
TYPE
DESCRIPTION
--
Power
Output from internal DC/DC converter(1)
--
Power
For decoupling of internal 1.27 V regulated digital-supply (2)
I/O
Digital
GPIO
I/O
Digital
GPIO
I/O
Digital
GPIO
I/O
Digital
GPIO
I/O
Digital
GPIO
I/O
Digital
GPIO, high-drive capability
I/O
Digital
GPIO, high-drive capability
I/O
Digital
GPIO, high-drive capability
I/O
Digital
GPIO
I/O
Digital
GPIO
I/O
Digital
GPIO
I/O
Digital
GPIO
I/O
Digital
GPIO
I/O
Digital
GPIO
I/O
Digital
GPIO
I/O
Digital
GPIO
I/O
Digital
GPIO, JTAG_TDO, high-drive capability
I/O
Digital
GPIO, JTAG_TDI, high-drive capability
I/O
Digital
GPIO
I/O
Digital
GPIO
I/O
Digital
GPIO
I/O
Digital
GPIO
I/O
Digital
GPIO
I/O
Digital or Analog GPIO, analog capability
I/O
Digital or Analog GPIO, analog capability
I/O
Digital or Analog GPIO, analog capability
I/O
Digital or Analog GPIO, analog capability
I/O
Digital or Analog GPIO, analog capability
I/O
Digital or Analog GPIO, analog capability
I/O
Digital or Analog GPIO, analog capability
I/O
Digital or Analog GPIO, analog capability
--
GND
Ground exposed ground pad(3)
I/O
Digital
JTAG TMSC, high-drive capability
I
Digital
JTAG TCKC
I
Digital
Reset, active low. No internal pullup resistor
--
RF
Positive RF input signal to LNA during RX Positive RF output signal from PA during TX
--
RF
Negative RF input signal to LNA during RX Negative RF output signal from PA during TX
(1) For more details, see technical reference manual listed in Section 8.2. (2) Do not supply external circuitry from this pin. (3) EGP is the only ground connection for the device. Good electrical connection to device ground on printed circuit board (PCB) is
imperative for proper device operation.
8
Terminal Configuration and Functions
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CC2652R
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Table 4-1. Signal Descriptions RGZ Package (continued)
PIN
I/O
NAME
NO.
VDDR
45
--
VDDR_RF
VDDS VDDS2 VDDS3 VDDS_DCDC X48M_N X48M_P X32K_Q1 X32K_Q2
48
--
44
--
13
--
22
--
34
--
46
--
47
--
3
--
4
--
TYPE
Power
Power Power Power Power Power Analog Analog Analog Analog
DESCRIPTION
Internal supply, must be powered from the internal DC/DC converter or the internal LDO(4)(2)(5) Internal supply, must be powered from the internal DC/DC converter or the internal LDO(6)(2)(5) 1.8-V to 3.8-V main chip supply(1) 1.8-V to 3.8-V DIO supply(1) 1.8-V to 3.8-V DIO supply(1) 1.8-V to 3.8-V DC/DC converter supply 48-MHz crystal oscillator pin 1 48-MHz crystal oscillator pin 2 32-kHz crystal oscillator pin 1 32-kHz crystal oscillator pin 2
(4) If internal DC/DC converter is not used, this pin is supplied internally from the main LDO. (5) Output from internal DC/DC and LDO is trimmed to 1.68 V. (6) If internal DC/DC converter is not used, this pin must be connected to VDDR for supply from the main LDO.
4.3 Connections for Unused Pins and Modules
Table 4-2. Connections for Unused Pins RGZ Package
FUNCTION
SIGNAL NAME
PIN NUMBER
ACCEPTABLE PRACTICE (1)
PREFERRED PRACTICE (1)
GPIO
DIO_n
512
1421 2632
NC or GND
NC
3643
32.768-kHz crystal
X32K_Q1 X32K_Q2
3
NC or GND
NC
4
DC/DC converter(2)
DCDC_SW
33
VDDS_DCDC
34
NC VDDS
NC VDDS
(1) NC = No connect (2) When the DC/DC converter is not used, the inductor between DCDC_SW and VDDR can be removed. VDDR and VDDR_RF must still
be connected and the 22 uF DCDC capacitor must be kept on the VDDR net.
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5 Specifications
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5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
MAX UNIT
VDDS(3) Supply voltage
0.3
4.1 V
Voltage on any digital pin(4)
0.3
VDDS + 0.3, max 4.1 V
Voltage on crystal oscillator pins, X32K_Q1, X32K_Q2, X48M_N and X48M_P
0.3
VDDR + 0.3, max 2.25 V
Voltage scaling enabled
0.3
VDDS
Vin
Voltage on ADC input
Voltage scaling disabled, internal reference
Voltage scaling disabled, VDDS as reference
0.3
1.49 V
0.3
VDDS / 2.9
Input level, RF pins
5 dBm
Tstg
Storage temperature
40
150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to ground, unless otherwise noted. (3) VDDS_DCDC, VDDS2 and VDDS3 must be at the same potential as VDDS. (4) Including analog capable DIOs.
5.2 ESD Ratings
VESD
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
All pins All pins
VALUE ±2000 ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process
UNIT V V
5.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Operating junction temperature(1)
MIN
MAX UNIT
40
105
°C
Operating supply voltage (VDDS)
1.8
3.8
V
Rising supply voltage slew rate Falling supply voltage slew rate(2)
0
100 mV/µs
0
20 mV/µs
(1) For thermal resistance characteristics refer to Section 5.8. For application considerations, refer to Section 7.2. (2) For small coin-cell batteries, with high worst-case end-of-life equivalent source resistance, a 22-µF VDDS input capacitor must be used
to ensure compliance with this slew rate.
5.4 Power Supply and Modules
over operating free-air temperature range (unless otherwise noted)
PARAMETER VDDS Power-on-Reset (POR) threshold VDDS Brown-out Detector (BOD) (1) VDDS Brown-out Detector (BOD), before initial boot (2) VDDS Brown-out Detector (BOD) (1)
Rising threshold Rising threshold Falling threshold
TYP 1.1 - 1.55
1.77 1.70 1.75
UNIT V V V V
(1) For boost mode (VDDR =1.95 V), TI drivers software initialization will trim VDDS BOD limits to maximum (approximately 2.0 V) (2) Brown-out Detector is trimmed at initial boot, value is kept until device is reset by a POR reset or the RESET_N pin
10
Specifications
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CC2652R
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5.5 Power Consumption - Power Modes
When measured on the CC26x2REM-7ID reference design with Tc = 25 °C, VDDS = 3.0 V with DC/DC enabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
TYP UNIT
Core Current Consumption
Reset and Shutdown
Reset. RESET_N pin asserted or VDDS below power-on-reset threshold Shutdown. No clocks running, no retention
150 nA
150
Standby without cache retention
RTC running, CPU, 80KB RAM and (partial) register retention. RCOSC_LF
RTC running, CPU, 80KB RAM and (partial) register retention XOSC_LF
0.94
µA
1.09
µA
Icore Standby
RTC running, CPU, 80KB RAM and (partial) register retention. RCOSC_LF
with cache retention
RTC running, CPU, 80KB RAM and (partial) register retention.
XOSC_LF
3.2
µA
3.3
µA
Idle
Supply Systems and RAM powered RCOSC_HF
675
µA
Active
MCU running CoreMark at 48 MHz RCOSC_HF
3.39 mA
Peripheral Current Consumption
Peripheral power domain
Delta current with domain enabled
97.7
Serial power domain Delta current with domain enabled
7.2
RF Core
Delta current with power domain enabled, clock enabled, RF core idle
210.9
µDMA
Timers
Iperi
I2C
Delta current with clock enabled, module is idle Delta current with clock enabled, module is idle(1) Delta current with clock enabled, module is idle
63.9
81.0
10.1
µA
I2S
Delta current with clock enabled, module is idle
26.3
SSI UART CRYPTO (AES)
Delta current with clock enabled, module is idle Delta current with clock enabled, module is idle(2) Delta current with clock enabled, module is idle(3)
82.9 167.5
25.6
PKA
Delta current with clock enabled, module is idle
84.7
TRNG
Delta current with clock enabled, module is idle
35.6
Sensor Controller Engine Consumption
Active mode
24 MHz, infinite loop
ISCE
Low-power mode
2 MHz, infinite loop
808.5 µA
30.1
(1) Only one GPTimer running (2) Only one UART running (3) Only one SSI running
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5.6 Power Consumption - Radio Modes
When measured on the reference design with Tc = 25 °C, VDDS = 3.0 V with DC/DC enabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
TYP
Radio receive current
2440 MHz
6.9
0 dBm output power setting 2440 MHz
7.3
Radio transmit current
+5 dBm output power setting 2440 MHz
9.6
UNIT mA mA
mA
5.7 Nonvolatile (Flash) Memory Characteristics
Over operating free-air temperature range and VDDS = 3.0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Flash sector size Supported flash erase cycles before failure, full bank(1) Supported flash erase cycles before failure, single sector(2)
Maximum number of write operations per row before sector erase (3)
Flash retention
105 °C
Flash sector erase current Flash sector erase time(4) Flash write current Flash write time(4)
Average delta current
Average delta current, 4 bytes at a time 4 bytes at a time
MIN
TYP MAX UNIT
8
KB
30
k Cycles
60
k Cycles
83
Write Operations
11.4
Years at 105 °C
10.7
mA
10
ms
6.2
mA
21.6
µs
(1) A full bank erase is counted as a single erase cycle on each sector (2) Up to 4 customer-designated sectors can be individually erased an additional 30k times beyond the baseline bank limitation of 30k
cycles (3) Each wordline is 2048 bits (or 256 bytes) wide. This limitation corresponds to sequential memory writes of 4 (3.1) bytes minimum per
write over a whole wordline. If additional writes to the same wordline are required, a sector erase is required once the maximum number of write operations per row is reached. (4) This number is dependent on Flash aging and increases over time and erase cycles
12
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5.8 Thermal Resistance Characteristics
PACKAGE
THERMAL METRIC(1)
RGZ (VQFN)
48 PINS
RJA RJC(top) RJB JT JB RJC(bot)
Junction-to-ambient thermal resistance Junction-to-case (top) thermal resistance Junction-to-board thermal resistance Junction-to-top characterization parameter Junction-to-board characterization parameter Junction-to-case (bottom) thermal resistance
23.4 13.3 8.0 0.1 7.9 1.7
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics. (2) °C/W = degrees Celsius per watt.
UNIT
°C/W (2) °C/W (2) °C/W (2) °C/W (2) °C/W (2) °C/W (2)
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5.9 Bluetooth Low Energy - Receive (RX)
When measured on the CC26x2REM-7ID reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with DC/DC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path. All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
125 kbps (LE Coded)
Receiver sensitivity
Differential mode. BER = 103
Receiver saturation
Differential mode. BER = 103
Frequency error tolerance
Difference between the incoming carrier frequency and the internally generated carrier frequency
Data rate error tolerance
Difference between incoming data rate and the internally generated data rate (37-byte packets)
Data rate error tolerance
Difference between incoming data rate and the internally generated data rate (255-byte packets)
Co-channel rejection(1)
Wanted signal at 79 dBm, modulated interferer in channel, BER = 103
Selectivity, ±1 MHz(1)
Wanted signal at 79 dBm, modulated interferer at ±1 MHz, BER = 103
Selectivity, ±2 MHz(1)
Wanted signal at 79 dBm, modulated interferer at ±2 MHz, BER = 103
Selectivity, ±3 MHz(1)
Wanted signal at 79 dBm, modulated interferer at ±3 MHz, BER = 103
Selectivity, ±4 MHz(1)
Wanted signal at 79 dBm, modulated interferer at ±4 MHz, BER = 103
Selectivity, ±6 MHz(1)
Wanted signal at 79 dBm, modulated interferer at ±6 MHz, BER = 103
Selectivity, ±7 MHz
Wanted signal at 79 dBm, modulated interferer at ±7 MHz, BER = 103
Selectivity, Image frequency(1)
Wanted signal at 79 dBm, modulated interferer at image frequency, BER = 103
Selectivity, Image frequency ±1 MHz (1)
Note that Image frequency + 1 MHz is the Co- channel 1 MHz. Wanted signal at 79 dBm, modulated interferer at ±1 MHz from image frequency, BER = 103
500 kbps (LE Coded)
Receiver sensitivity
Differential mode. BER = 103
Receiver saturation
Differential mode. BER = 103
Frequency error tolerance
Difference between the incoming carrier frequency and the internally generated carrier frequency
Data rate error tolerance
Difference between incoming data rate and the internally generated data rate (37-byte packets)
Data rate error tolerance
Difference between incoming data rate and the internally generated data rate (255-byte packets)
Co-channel rejection(1)
Wanted signal at 72 dBm, modulated interferer in channel, BER = 103
Selectivity, ±1 MHz(1)
Wanted signal at 72 dBm, modulated interferer at ±1 MHz, BER = 103
Selectivity, ±2 MHz(1)
Wanted signal at 72 dBm, modulated interferer at ±2 MHz, BER = 103
Selectivity, ±3 MHz(1)
Wanted signal at 72 dBm, modulated interferer at ±3 MHz, BER = 103
Selectivity, ±4 MHz(1)
Wanted signal at 72 dBm, modulated interferer at ±4 MHz, BER = 103
Selectivity, ±6 MHz(1)
Wanted signal at 72 dBm, modulated interferer at ±6 MHz, BER = 103
Selectivity, ±7 MHz
Wanted signal at 72 dBm, modulated interferer at ±7 MHz, BER = 103
TYP
105 >5
> (300 / 300) > (320 / 240) > (125 / 125)
1.5 8 / 4.5(2) 44 / 39(2) 46 / 44(2) 44 / 46(2) 48 / 44(2) 51 / 45(2)
39
4.5 / 44 (2)
100 >5
> (300 / 300) > (450 / 450) > (175 / 175)
3.5 8 / 4(2) 44 / 37(2) 46 / 46(2) 45 / 47(2) 46 / 45(2) 49 / 45(2)
MAX UNIT
dBm dBm kHz ppm ppm dB dB dB dB dB dB dB dB
dB
dBm dBm kHz ppm ppm dB dB dB dB dB dB dB
(1) Numbers given as I/C dB (2) X / Y, where X is +N MHz and Y is N MHz
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Bluetooth Low Energy - Receive (RX) (continued)
When measured on the CC26x2REM-7ID reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with
DC/DC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path.
All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Selectivity, Image frequency(1)
Wanted signal at 72 dBm, modulated interferer at image frequency, BER = 103
37
dB
Selectivity, Image frequency ±1 MHz (1)
Note that Image frequency + 1 MHz is the Co- channel 1 MHz. Wanted signal at 72 dBm, modulated interferer at ±1 MHz from image frequency, BER = 103
4 / 46(2)
dB
1 Mbps (LE 1M)
Receiver sensitivity
Differential mode. BER = 103
97
dBm
Receiver saturation
Differential mode. BER = 103
>5
dBm
Frequency error tolerance
Difference between the incoming carrier frequency and the internally generated carrier frequency
> (350 / 350)
kHz
Data rate error tolerance
Difference between incoming data rate and the internally generated data rate (37-byte packets)
> (750 / 750)
ppm
Co-channel rejection(1)
Wanted signal at 67 dBm, modulated interferer in channel, BER = 103
6
dB
Selectivity, ±1 MHz(1)
Wanted signal at 67 dBm, modulated interferer at ±1 MHz, BER = 103
7 / 4(2)
dB
Selectivity, ±2 MHz(1)
Wanted signal at 67 dBm, modulated interferer at ±2 MHz,BER = 103
40 / 33(2)
dB
Selectivity, ±3 MHz(1)
Wanted signal at 67 dBm, modulated interferer at ±3 MHz, BER = 103
36 / 41(2)
dB
Selectivity, ±4 MHz(1)
Wanted signal at 67 dBm, modulated interferer at ±4 MHz, BER = 103
36 / 45(2)
dB
Selectivity, ±5 MHz or more(1)
Wanted signal at 67 dBm, modulated interferer at ±5 MHz, BER = 103
40
dB
Selectivity, image frequency(1)
Wanted signal at 67 dBm, modulated interferer at image frequency, BER = 103
33
dB
Selectivity, image frequency ±1 MHz(1)
Out-of-band blocking(3)
Note that Image frequency + 1 MHz is the Co- channel 1 MHz. Wanted signal at 67 dBm, modulated interferer at ±1 MHz from image frequency, BER = 103
30 MHz to 2000 MHz
4 / 41(2) 10
dB dBm
Out-of-band blocking
2003 MHz to 2399 MHz
18
dBm
Out-of-band blocking
2484 MHz to 2997 MHz
12
dBm
Out-of-band blocking
3000 MHz to 12.75 GHz
2
dBm
Intermodulation
Wanted signal at 2402 MHz, 64 dBm. Two interferers at 2405 and 2408 MHz respectively, at the given power level
42
dBm
Spurious emissions, 30 to 1000 MHz(4)
Measurement in a 50- single-ended load.
< 59
dBm
Spurious emissions, 1 to 12.75 GHz(4)
Measurement in a 50 single-ended load.
< 47
dBm
RSSI dynamic range
70
dB
RSSI accuracy
±4
dB
2 Mbps (LE 2M)
Receiver sensitivity
Differential mode. Measured at SMA connector, BER = 103
92
dBm
Receiver saturation
Differential mode. Measured at SMA connector, BER = 103
>5
dBm
Frequency error tolerance
Difference between the incoming carrier frequency and the internally generated carrier frequency
> (500 / 500)
kHz
Data rate error tolerance
Difference between incoming data rate and the internally generated data rate (37-byte packets)
> (700 / 750)
ppm
(3) Excluding one exception at Fwanted / 2, per Bluetooth Specification (4) Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2
(Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan)
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Bluetooth Low Energy - Receive (RX) (continued)
When measured on the CC26x2REM-7ID reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with
DC/DC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX
path.
All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Co-channel rejection(1)
Wanted signal at 67 dBm, modulated interferer in channel,BER = 103
7
dB
Selectivity, ±2 MHz(1)
Wanted signal at 67 dBm, modulated interferer at ±2 MHz, Image frequency is at 2 MHz, BER = 103
8 / 4(2)
dB
Selectivity, ±4 MHz(1)
Wanted signal at 67 dBm, modulated interferer at ±4 MHz, BER = 103
36 / 36(2)
dB
Selectivity, ±6 MHz(1)
Wanted signal at 67 dBm, modulated interferer at ±6 MHz, BER = 103
37 / 36(2)
dB
Selectivity, image frequency(1)
Wanted signal at 67 dBm, modulated interferer at image frequency, BER = 103
4
dB
Selectivity, image frequency ±2 MHz(1)
Note that Image frequency + 2 MHz is the Co-channel. Wanted signal at 67 dBm, modulated interferer at ±2 MHz from image frequency, BER = 103
7 / 36(2)
dB
Out-of-band blocking(3)
30 MHz to 2000 MHz
16
dBm
Out-of-band blocking
2003 MHz to 2399 MHz
21
dBm
Out-of-band blocking
2484 MHz to 2997 MHz
15
dBm
Out-of-band blocking
3000 MHz to 12.75 GHz
12
dBm
Intermodulation
Wanted signal at 2402 MHz, 64 dBm. Two interferers at 2405 and 2408 MHz respectively, at the given power level
38
dBm
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5.10 Bluetooth Low Energy - Transmit (TX)
When measured on the CC26x2REM-7ID reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with DC/DC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path. All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
General Parameters
Max output power
Differential mode, delivered to a single-ended 50 load through a balun
Output power programmable range
Differential mode, delivered to a single-ended 50 load through a balun
Spurious emissions and harmonics
f < 1 GHz, outside restricted bands
Spurious emissions(1)
f < 1 GHz, restricted bands ETSI f < 1 GHz, restricted bands FCC f > 1 GHz, including harmonics
+5 dBm setting
Harmonics (1)
Second harmonic Third harmonic
MIN
TYP
MAX UNIT
5
dBm
26
dB
< 36 < 54 < 55 < 42 < 42 < 42
dBm dBm dBm dBm dBm dBm
(1) Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan).
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5.11 Zigbee and Thread - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - RX
When measured on the CC26x2REM-7ID reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with DC/DC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path. All measurements are performed conducted.
PARAMETER Receiver sensitivity
PER = 1%
TEST CONDITIONS
MIN
TYP
MAX
UNIT
100
dBm
Receiver saturation
PER = 1%
>5
dBm
Adjacent channel rejection
Wanted signal at 82 dBm, modulated interferer at ±5 MHz, PER = 1%
36
dB
Alternate channel rejection
Channel rejection, ±15 MHz or more Blocking and desensitization, 5 MHz from upper band edge
Wanted signal at 82 dBm, modulated interferer at ±10 MHz, PER = 1%
Wanted signal at 82 dBm, undesired signal is IEEE 802.15.4 modulated channel, stepped through all channels 2405 to 2480 MHz, PER = 1%
Wanted signal at 97 dBm (3 dB above the sensitivity level), CW jammer, PER = 1%
57
dB
59
dB
57
dB
Blocking and desensitization, 10 MHz from upper band edge
Wanted signal at 97 dBm (3 dB above the sensitivity level), CW jammer, PER = 1%
63
dB
Blocking and desensitization, 20 MHz from upper band edge
Blocking and desensitization, 50 MHz from upper band edge
Wanted signal at 97 dBm (3 dB above the sensitivity level), CW jammer, PER = 1%
Wanted signal at 97 dBm (3 dB above the sensitivity level), CW jammer, PER = 1%
63
dB
66
dB
Blocking and desensitization, 5 MHz from lower band edge
Wanted signal at 97 dBm (3 dB above the sensitivity level), CW jammer, PER = 1%
60
dB
Blocking and desensitization, 10 MHz from lower band edge
Blocking and desensitization, 20 MHz from lower band edge
Wanted signal at 97 dBm (3 dB above the sensitivity level), CW jammer, PER = 1%
Wanted signal at 97 dBm (3 dB above the sensitivity level), CW jammer, PER = 1%
60
dB
63
dB
Blocking and desensitization, 50 MHz from lower band edge
Wanted signal at 97 dBm (3 dB above the sensitivity level), CW jammer, PER = 1%
65
dB
Spurious emissions, 30 MHz to 1000 MHz
Spurious emissions, 1 GHz to 12.75 GHz
Measurement in a 50- single-ended load Measurement in a 50- single-ended load
66
dBm
53
dBm
Frequency error tolerance
Difference between the incoming carrier frequency and the internally generated carrier frequency
> 350
ppm
Symbol rate error tolerance RSSI dynamic range
Difference between incoming symbol rate and the internally generated symbol rate
> 1000
ppm
95
dB
RSSI accuracy
±4
dB
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5.12 Zigbee and Thread - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - TX
When measured on the CC26x2REM-7ID reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with DC/DC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path. All measurements are performed conducted.
PARAMETER
TEST CONDITIONS
General Parameters
Max output power
Differential mode, delivered to a single-ended 50- load through a balun
Output power programmable range
Differential mode, delivered to a single-ended 50- load through a balun
Spurious emissions and harmonics
f < 1 GHz, outside restricted bands
Spurious emissions(1)(2)
f < 1 GHz, restricted bands ETSI f < 1 GHz, restricted bands FCC f > 1 GHz, including harmonics
+5 dBm setting
Harmonics (1)
Second harmonic Third harmonic
IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps)
Error vector magnitude +5 dBm setting
MIN
TYP
MAX UNIT
5
dBm
26
dB
< -36 < -47 < -55 < 42 < -42 < -42
2
dBm dBm dBm dBm dBm dBm
%
(1) Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan).
(2) To ensure margins for passing FCC band edge requirements at 2483.5 MHz, a lower than maximum output-power setting or less than 100% duty cycle may be used when operating at 2480 MHz.
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5.13 Timing and Switching Characteristics
RESET_N low duration
Table 5-1. Reset Timing
PARAMETER
MIN TYP 1
MAX
UNIT µs
Table 5-2. Wakeup Timing
Measured over operating free-air temperature with VDDS = 3.0 V (unless otherwise noted). The times listed here do not include software overhead.
PARAMETER MCU, Reset to Active(1) MCU, Shutdown to Active(1) MCU, Standby to Active MCU, Active to Standby MCU, Idle to Active
TEST CONDITIONS
MIN
TYP
850 - 3000
850 - 3000
160
36
14
MAX
UNIT µs µs µs µs µs
(1) The wakeup time is dependent on remaining charge on VDDR capacitor when starting the device, and thus how long the device has been in Reset or Shutdown before starting up again.
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5.13.1 Clock Specifications
Table 5-3. 48 MHz Crystal Oscillator (XOSC_HF)
Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.(1)
PARAMETER
MIN
TYP
MAX UNIT
Crystal frequency
48
MHz
ESR
Equivalent series resistance 6 pF < CL 9 pF
ESR
Equivalent series resistance 5 pF < CL 6 pF
LM
Motional inductance, relates to the load capacitance that is used for the crystal (CL in Farads)(2)
CL
Crystal load capacitance(3)
5
Start-up time(5)
20
< 3 × 1024 / CL2 7 (4) 200
60
80
H
9
pF
µs
(1) Probing or otherwise stopping the crystal while the DC/DC converter is enabled may cause permanent damage to the device. (2) The crystal manufacturer's specification must satisfy this requirement for proper operation. (3) Adjustable load capacitance is integrated into the device. (4) On-chip default connected capacitance including reference design parasitic capacitance. Connected internal capacitance is changed
through software in the Customer Configuration section (CCFG). (5) Start-up time using the TI-provided power driver. Start-up time may increase if driver is not used.
Table 5-4. 48 MHz RC Oscillator (RCOSC_HF)
Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN
TYP
MAX
Frequency
48
Uncalibrated frequency accuracy
±1
Calibrated frequency accuracy(1)
±0.25
Start-up time
5
(1) Accuracy relative to the calibration source (XOSC_HF)
UNIT MHz
% % µs
Table 5-5. 2 MHz RC Oscillator (RCOSC_MF)
Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN
TYP
MAX
UNIT
Calibrated frequency
2
MHz
Start-up time
5
µs
Table 5-6. 32.768 kHz Crystal Oscillator (XOSC_LF)
Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN
TYP
MAX
UNIT
Crystal frequency
32.768
kHz
ESR CL
Equivalent series resistance Crystal load capacitance
30
100
k
6
7 (1)
12
pF
(1) Default load capacitance using TI reference designs including parasitic capacitance. Crystals with different load capacitance may be used.
Table 5-7. 32 kHz RC Oscillator (RCOSC_LF)
Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
MIN
TYP
MAX
Calibrated frequency
32.8 (1)
Temperature coefficient
50
UNIT kHz ppm/°C
(1) When using RCOSC_LF as source for the low frequency system clock (SCLK_LF), the accuracy of the SCLK_LF-derived Real Time Clock (RTC) can be improved by measuring RCOSC_LF relative to XOSC_HF and compensating for the RTC tick speed. This functionality is available through the TI-provided Power driver.
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5.13.2 Synchronous Serial Interface (SSI) Characteristics
Table 5-8. Synchronous Serial Interface (SSI) Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER NO.
PARAMETER
MIN
TYP
MAX
S1 S2 (2) S3 (2)
tclk_per tclk_high tclk_low
SSIClk cycle time SSIClk high time SSIClk low time
12
65024
0.5
0.5
(1) When using the TI-provided Power driver, the SSI system clock is always 48 MHz. (2) Refer to SSI timing diagrams Figure 5-1, Figure 5-2, and Figure 5-3.
UNIT
System Clocks (1) tclk_per tclk_per
SSIClk SSIFss
S1 S2
S3
SSITx SSIRx
MSB
4 to 16 bits
LSB
Figure 5-1. SSI Timing for TI Frame Format (FRF = 01), Single Transfer Timing Measurement
S2
S1
SSIClk
S3
SSIFss
SSITx
MSB
LSB
8-bit control
SSIRx
0 MSB
LSB
4 to 16 bits output data
Figure 5-2. SSI Timing for MICROWIRE Frame Format (FRF = 10), Single Transfer
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SSIClk (SPO = 0)
SSIClk (SPO = 1)
SSITx (Master)
SSIRx (Slave)
MSB MSB
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S2
S3
LSB
LSB
SSIFss
Figure 5-3. SSI Timing for SPI Frame Format (FRF = 00), With SPH = 1
5.13.3 UART
Table 5-9. UART Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
UART rate
TYP
MAX
UNIT
3
MBaud
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5.14 Peripheral Characteristics 5.14.1 ADC
Table 5-10. Analog-to-Digital Converter (ADC) Characteristics
Tc = 25 °C, VDDS = 3.0 V and voltage scaling enabled, unless otherwise noted.(1) Performance numbers require use of offset and gain adjustements in software by TI-provided ADC drivers.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
Input voltage range
0
VDDS
Resolution
12
DNL (3)
Sample Rate Offset Gain error Differential nonlinearity
Internal 4.3 V equivalent reference(2) Internal 4.3 V equivalent reference(2)
200 0.24
7.14 >1
INL
Integral nonlinearity
±4
Internal 4.3 V equivalent reference(2), 200 kSamples/s, 9.6 kHz input tone
9.8
Internal 4.3 V equivalent reference(2), 200 kSamples/s, 9.6 kHz input tone, DC/DC enabled
9.8
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone
10.1
ENOB Effective number of bits
Internal reference, voltage scaling disabled, 32 samples average, 200 kSamples/s, 300 Hz input tone
11.1
Internal reference, voltage scaling disabled, 14-bit mode, 200 kSamples/s, 300 Hz input tone (4)
11.3
Internal reference, voltage scaling disabled, 15-bit mode, 200 kSamples/s, 300 Hz input tone (4)
11.6
Internal 4.3 V equivalent reference(2), 200 kSamples/s, 9.6 kHz input tone
65
THD
Total harmonic distortion
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone
70
Internal reference, voltage scaling disabled, 32 samples average, 200 kSamples/s, 300 Hz input tone
72
SINAD, SNDR
Signal-to-noise and distortion ratio
Internal 4.3 V equivalent reference(2), 200 kSamples/s, 9.6 kHz input tone
VDDS as reference, 200 kSamples/s, 9.6 kHz input tone
Internal reference, voltage scaling disabled, 32 samples average, 200 kSamples/s, 300 Hz input tone
60 63 68
Internal 4.3 V equivalent reference(2), 200 kSamples/s, 9.6 kHz input tone
70
SFDR Spurious-free dynamic range VDDS as reference, 200 kSamples/s, 9.6 kHz input tone
73
Internal reference, voltage scaling disabled, 32 samples average, 200 kSamples/s, 300 Hz input tone
75
Conversion time
Serial conversion, time-to-output, 24 MHz clock
50
Current consumption
Internal 4.3 V equivalent reference(2)
0.42
Current consumption
VDDS as reference
0.6
Reference voltage
Equivalent fixed internal reference (input voltage scaling enabled). For best accuracy, the ADC conversion should be initiated through the TI-RTOS API in order to include the gain/offset compensation factors stored in FCFG1
4.3 (2) (5)
Reference voltage Reference voltage
Fixed internal reference (input voltage scaling disabled). For best accuracy, the ADC conversion should be initiated through the TI-RTOS API in order to include the gain/offset compensation factors stored in FCFG1. This value is derived from the scaled value (4.3 V) as follows: Vref = 4.3 V × 1408 / 4095
VDDS as reference, input voltage scaling enabled
1.48 VDDS
UNIT V Bits
ksps LSB LSB LSB LSB
Bits
Bits
dB
dB Clock Cycles
mA mA V
V V
(1) Using IEEE Std 1241-2010 for terminology and test methods (2) Input signal scaled down internally before conversion, as if voltage range was 0 to 4.3 V (3) No missing codes (4) ADC_output = (4n samples ) >> n, n = desired extra bits (5) Applied voltage must be within Absolute Maximum Ratings (see Section 5.1 ) at all times
24
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Table 5-10. Analog-to-Digital Converter (ADC) Characteristics (continued)
Tc = 25 °C, VDDS = 3.0 V and voltage scaling enabled, unless otherwise noted.(1)
Performance numbers require use of offset and gain adjustements in software by TI-provided ADC drivers.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
Reference voltage
VDDS as reference, input voltage scaling disabled
VDDS / 2.82 (5)
200 kSamples/s, voltage scaling enabled. Capacitive input,
Input impedance
Input impedance depends on sampling frequency and sampling
>1
time
UNIT V
M
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5.14.2 DAC
Table 5-11. Digital-to-Analog Converter (DAC) Characteristics
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
General Parameters
Resolution
8
VDDS
Supply voltage
Any load, any VREF, pre-charge OFF, DAC charge-pump ON
1.8
External Load(1), any VREF, pre-charge OFF, DAC chargepump OFF
2.0
Any load, VREF = DCOUPL, pre-charge ON
2.6
Buffer ON (recommended for external load)
16
FDAC
Clock frequency
Buffer OFF (internal load)
16
Voltage output settling time
VREF = VDDS, buffer OFF, internal load VREF = VDDS, buffer ON, external capacitive load = 20 pF(2)
13 13.8
External capacitive load
20
External resistive load
10
Short circuit current
VDDS = 3.8 V, DAC charge-pump OFF
50.8
VDDS = 3.0 V, DAC charge-pump ON
51.7
Max output impedance Vref VDDS = 3.0 V, DAC charge-pump OFF
53.2
ZMAX
= VDDS, buffer ON, CLK
VDDS = 2.0 V, DAC charge-pump ON
48.7
250 kHz
VDDS = 2.0 V, DAC charge-pump OFF
70.2
VDDS = 1.8 V, DAC charge-pump ON
46.3
VDDS = 1.8 V, DAC charge-pump OFF
88.9
Internal Load - Continuous Time Comparator / Low Power Clocked Comparator
DNL
Differential nonlinearity
Differential nonlinearity
Offset error(4) Load = Continuous Time Comparator
Offset error(4) Load = Low Power Clocked Comparator
Max code output voltage variation (4) Load = Continuous Time Comparator
VREF = VDDS, load = Continuous Time Comparator or Low Power Clocked Comparator FDAC = 250 kHz VREF = VDDS, load = Continuous Time Comparator or Low Power Clocked Comparator FDAC = 16 kHz VREF = VDDS = 3.8 V VREF = VDDS = 3.0 V VREF = VDDS = 1.8 V VREF = DCOUPL, pre-charge ON VREF = DCOUPL, pre-charge OFF VREF = ADCREF VREF = VDDS = 3.8 V VREF = VDDS = 3.0 V VREF = VDDS = 1.8 V VREF = DCOUPL, pre-charge ON VREF = DCOUPL, pre-charge OFF VREF = ADCREF VREF = VDDS = 3.8 V VREF = VDDS = 3.0 V VREF = VDDS = 1.8 V VREF = DCOUPL, pre-charge ON VREF = DCOUPL, pre-charge OFF VREF = ADCREF
±1
±1.2
±0.64 ±0.81 ±1.27 ±3.43 ±2.88 ±2.37 ±0.78 ±0.77 ±3.46 ±3.44 ±4.70 ±4.11 ±1.53 ±1.71 ±2.10 ±6.00 ±3.85 ±5.84
MAX
UNIT
3.8 3.8 3.8 250 1000
200
400
Bits
V
kHz 1 / FDAC
pF M µA
k
LSB (3) LSB (3) LSB (3) LSB (3)
(1) Keysight 34401A Multimeter
(2) A load > 20 pF will increases the settling time
(3) 1 LSB (VREF 3.8 V/3.0 V/1.8 V/DCOUPL/ADCREF) = 14.10 mV/11.13 mV/6.68 mV/4.67 mV/5.48 mV (4) Includes comparator offset
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Table 5-11. Digital-to-Analog Converter (DAC) Characteristics (continued)
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
VREF = VDDS = 3.8 V
Max code output voltage variation (4)
Load = Low Power Clocked
Comparator
VREF =VDDS = 3.0 V VREF = VDDS = 1.8 V VREF = DCOUPL, pre-charge ON VREF = DCOUPL, pre-charge OFF
VREF = ADCREF
VREF = VDDS = 3.8 V, code 1
VREF = VDDS = 3.8 V, code 255
VREF = VDDS = 3.0 V, code 1
VREF = VDDS = 3.0 V, code 255
Output voltage range(4) Load = Continuous Time Comparator
VREF = VDDS = 1.8 V, code 1 VREF = VDDS = 1.8 V, code 255 VREF = DCOUPL, pre-charge OFF, code 1
VREF = DCOUPL, pre-charge OFF, code 255
VREF = DCOUPL, pre-charge ON, code 1
VREF = DCOUPL, pre-charge ON, code 255
VREF = ADCREF, code 1
VREF = ADCREF, code 255
VREF = VDDS = 3.8 V, code 1
VREF = VDDS = 3.8 V, code 255
VREF = VDDS = 3.0 V, code 1
VREF = VDDS = 3.0 V, code 255
Output voltage range(4) Load = Low Power Clocked Comparator
VREF = VDDS = 1.8 V, code 1 VREF = VDDS = 1.8 V, code 255 VREF = DCOUPL, pre-charge OFF, code 1
VREF = DCOUPL, pre-charge OFF, code 255
VREF = DCOUPL, pre-charge ON, code 1
VREF = DCOUPL, pre-charge ON, code 255
VREF = ADCREF, code 1
VREF = ADCREF, code 255
External Load (Keysight 34401A Multimeter)
INL DNL
Integral nonlinearity Differential nonlinearity Offset error
Max code output voltage variation
VREF = VDDS, FDAC = 250 kHz VREF = DCOUPL, FDAC = 250 kHz VREF = ADCREF, FDAC = 250 kHz VREF = VDDS, FDAC = 250 kHz VREF = VDDS = 3.8 V VREF = VDDS = 3.0 V VREF = VDDS = 1.8 V VREF = DCOUPL, pre-charge ON VREF = DCOUPL, pre-charge OFF VREF = ADCREF VREF = VDDS = 3.8 V VREF = VDDS = 3.0 V VREF = VDDS = 1.8 V VREF = DCOUPL, pre-charge ON VREF = DCOUPL, pre-charge OFF VREF = ADCREF
MIN
TYP
±2.92
±3.06
±3.91
±7.84
±4.06
±6.94
0.03
3.62
0.02
2.86
0.01
1.71
0.01
1.21
1.27
2.46
0.01
1.41
0.03
3.61
0.02
2.85
0.01
1.71
0.01
1.21
1.27
2.46
0.01
1.41
±1 ±1 ±1 ±1 ±0.20 ±0.25 ±0.45 ±1.55 ±1.30 ±1.10 ±0.60 ±0.55 ±0.60 ±3.45 ±2.10 ±1.90
MAX
UNIT LSB (3)
V
V
LSB (3) LSB (3) LSB (3) LSB (3)
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Table 5-11. Digital-to-Analog Converter (DAC) Characteristics (continued)
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
Output voltage range Load = Low Power Clocked Comparator
VREF = VDDS = 3.8 V, code 1 VREF = VDDS = 3.8 V, code 255 VREF = VDDS = 3.0 V, code 1 VREF = VDDS = 3.0 V, code 255 VREF = VDDS = 1.8 V, code 1 VREF = VDDS = 1.8 V, code 255 VREF = DCOUPL, pre-charge OFF, code 1 VREF = DCOUPL, pre-charge OFF, code 255 VREF = DCOUPL, pre-charge ON, code 1 VREF = DCOUPL, pre-charge ON, code 255 VREF = ADCREF, code 1 VREF = ADCREF, code 255
MIN
TYP
MAX
0.03
3.61
0.02
2.85
0.02
1.71
0.02
1.20
1.27
2.46
0.02
1.42
UNIT V
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5.14.3 Temperature and Battery Monitor
Table 5-12. Temperature Sensor
Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
Resolution
2
Accuracy
-40 °C to 0 °C
±4.0
Accuracy
0 °C to 85 °C
±2.5
Supply voltage coefficient(1)
3.6
(1) The temperature sensor is automatically compensated for VDDS variation when using the TI-provided driver.
Table 5-13. Battery Monitor
Measured on a Texas Instruments reference design with Tc = 25 °C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
Resolution
Range
1.8
Integral nonlinearity (max)
Accuracy
VDDS = 3.0 V
Offset error
Gain error
TYP
MAX
25
3.8
23
22.5
-32
-1
UNIT °C °C °C °C/V
UNIT mV V mV mV mV %
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5.14.4 Comparators
Table 5-14. Continuous Time Comparator
Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER Input voltage range(1)
TEST CONDITIONS
Offset Decision time
Measured at VDDS / 2 Step from 10 mV to 10 mV
Current consumption
Internal reference
MIN
TYP
MAX
UNIT
0
VDDS
V
±5
mV
0.78
µs
8.6
µA
(1) The input voltages can be generated externally and connected throughout I/Os or an internal reference voltage can be generated using the DAC.
Table 5-15. Low-Power Clocked Comparator
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
Input voltage range Clock frequency
0
VDDS
V
SCLK_LF
Internal reference voltage(1)
Using internal DAC with VDDS as reference voltage, DAC code = 0 - 255
0.024 - 2.865
V
Offset Decision time
Measured at VDDS / 2, includes error from internal DAC Step from 50 mV to 50 mV
±5
mV
1
Clock Cycle
(1) The comparator can use an internal 8 bits DAC as its reference. The DAC output voltage range depends on the reference voltage selected. See Table 5-11.
5.14.5 Current Source
Table 5-16. Programmable Current Source
Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
Current source programmable output range (logarithmic range)
Resolution
MIN
TYP MAX UNIT
0.25 - 20
µA
0.25
µA
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5.14.6 GPIO
PARAMETER TA = 25 °C, VDDS = 1.8 V GPIO VOH at 8 mA load GPIO VOL at 8 mA load GPIO VOH at 4 mA load GPIO VOL at 4 mA load GPIO pullup current GPIO pulldown current GPIO low-to-high input transition, with hysteresis GPIO high-to-low input transition, with hysteresis
GPIO input hysteresis
TA = 25 °C, VDDS = 3.0 V GPIO VOH at 8 mA load GPIO VOL at 8 mA load GPIO VOH at 4 mA load GPIO VOL at 4 mA load TA = 25 °C, VDDS = 3.8 V GPIO pullup current GPIO pulldown current GPIO low-to-high input transition, with hysteresis GPIO high-to-low input transition, with hysteresis
GPIO input hysteresis
TA = 25 °C
VIH
VIL
Table 5-17. GPIO DC Characteristics
TEST CONDITIONS
IOCURR = 2, high-drive GPIOs only IOCURR = 2, high-drive GPIOs only IOCURR = 1 IOCURR = 1 Input mode, pullup enabled, Vpad = 0 V Input mode, pulldown enabled, Vpad = VDDS IH = 1, transition voltage for input read as 0 1 IH = 1, transition voltage for input read as 1 0 IH = 1, difference between 0 1 and 1 0 points
IOCURR = 2, high-drive GPIOs only IOCURR = 2, high-drive GPIOs only IOCURR = 1 IOCURR = 1
Input mode, pullup enabled, Vpad = 0 V Input mode, pulldown enabled, Vpad = VDDS IH = 1, transition voltage for input read as 0 1 IH = 1, transition voltage for input read as 1 0 IH = 1, difference between 0 1 and 1 0 points
Lowest GPIO input voltage reliably interpreted as a High Highest GPIO input voltage reliably interpreted as a Low
MIN 0.8*VDDS
TYP
MAX UNIT
1.56
V
0.24
V
1.59
V
0.21
V
73
µA
19
µA
1.08
V
0.73
V
0.35
V
2.59
V
0.42
V
2.63
V
0.40
V
282
µA
110
µA
1.97
V
1.55
V
0.42
V
V 0.2*VDDS V
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5.15 Typical Characteristics
All measurements in this section are done with Tc = 25 °C and VDDS = 3.0 V, unless otherwise noted. See Recommended Operating Conditions, Section 5.3, for device limits. Values exceeding these limits are for reference only.
5.15.1 MCU Current
Active Current vs. VDDS
Running CoreMark, SCLK_HF = 48 MHz RCOSC
6
5.5
5
Current [mA]
4.5
4
3.5
3
2.5
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
Voltage [V]
D001
Figure 5-4. Active Mode (MCU) Current vs. Supply Voltage (VDDS)
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Current [µA]
Current [µA]
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Standby Current vs. Temperature
80 kB RAM Retention, no Cache Retention, RTC On SCLK_LF = 32 kHz XOSC
12
10
8
6
4
2
0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature [°C]
D006
Figure 5-5. Standby Mode (MCU) Current vs. Temperature
Standby Current vs. Temperature
80 kB RAM Retention, no Cache Retention, RTC On SCLK_LF = 32 kHz XOSC VDDS = 3.6 V
12
10
8
6
4
2
0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature [°C]
D007
Figure 5-6. Standby Mode (MCU) Current vs. Temperature (VDDS = 3.6 V)
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5.15.2 RX Current
Current [mA]
RX Current vs. Temperature
BLE 1 Mbps, 2.44 GHz
8.5 8.4 8.3 8.2 8.1
8 7.9 7.8 7.7 7.6 7.5 7.4 7.3 7.2 7.1
7 6.9 6.8 6.7 6.6 6.5
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
Temperature [°C]
90 100
D010
Figure 5-7. RX Current vs. Temperature (BLE 1 Mbps, 2.44 GHz)
Current [mA]
RX Current vs. VDDS
BLE 1 Mbps, 2.44 GHz
11.5
11
10.5
10
9.5
9
8.5
8
7.5
7
6.5
6
5.5
1.8
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
Voltage [V]
D013
Figure 5-8. RX Current vs. Supply Voltage (VDDS) (BLE 1 Mbps, 2.44 GHz)
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5.15.3 TX Current
Current [mA]
TX Current vs. Temperature
BLE 1 Mbps, 2.44 GHz, 0 dBm
9 8.85
8.7 8.55
8.4 8.25
8.1 7.95
7.8 7.65
7.5 7.35
7.2 7.05
6.9 6.75
6.6 6.45
6.3 6.15
6 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80
Temperature [°C]
90 100
D018
Figure 5-9. TX Current vs. Temperature (BLE 1 Mbps, 2.44 GHz)
Current [mA]
TX Current vs. VDDS
BLE 1 Mbps, 2.44 GHz, 0 dBm
12
11.5
11
10.5
10
9.5
9
8.5
8
7.5
7
6.5
6
5.5
5
1.8
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
Voltage [V]
D024
Figure 5-10. TX Current vs. Supply Voltage (VDDS) (BLE 1 Mbps, 2.44 GHz)
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Table 5-18 shows typical TX current and output power for different output power settings.
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txPower 0x7217 0x4E63 0x385D 0x3259 0x2856 0x2853 0x12D6 0x0ACF 0x06CA 0x04C6
Table 5-18. Typical TX Current and Output Power
CC2652R at 2.4 GHz, VDDS = 3.0 V (Measured on CC2652REM-7ID)
TX Power Setting (SmartRF Studio)
Typical Output Power [dBm]
Typical Current Consumption [mA]
5
4.9
9.5
4
3.9
9.0
3
2.8
8.6
2
1.8
8.0
1
0.9
7.6
0
-0.3
7.3
-5
-4.9
6.2
-10
-9.4
5.6
-15
-14.5
5.2
-20
-20.3
4.8
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5.15.4 RX Performance
Sensitivity [dBm]
Sensitivity vs. Frequency
BLE 1 Mbps, 2.44 GHz
-92
-93
-94
-95
-96
-97
-98
-99
-100
-101
-102 2.4
2.408 2.416 2.424 2.432 2.44 2.448 2.456 2.464 2.472 2.48
Frequency [GHz]
D028
Figure 5-11. Sensitivity vs. Frequency (BLE 1 Mbps, 2.44 GHz)
Sensitivity [dBm]
Sensitivity vs. Frequency
IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps)
-95
-96
-97
-98
-99
-100
-101
-102
-103
-104
-105 2.4
2.408 2.416 2.424 2.432 2.44 2.448 2.456 2.464 2.472 2.48
Frequency [GHz]
D029
Figure 5-12. Sensitivity vs. Frequency (250 kbps, 2.44 GHz)
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Sensitivity [dBm]
Sensitivity vs. Temperature
BLE 1 Mbps, 2.44 GHz
-92
-93
-94
-95
-96
-97
-98
-99
-100
-101
-102
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature [°C]
D031
Figure 5-13. Sensitivity vs. Temperature (BLE 1 Mbps, 2.44 GHz)
Sensitivity [dBm]
Sensitivity vs. Temperature
IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps), 2.44 GHz
-95
-96
-97
-98
-99
-100
-101
-102
-103
-104
-105
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature [°C]
D032
Figure 5-14. Sensitivity vs. Temperature (250 kbps, 2.44 GHz)
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Sensitivity [dBm]
Sensitivity [dBm]
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Sensitivity vs. VDDS
BLE 1 Mbps, 2.44 GHz
-92
-93
-94
-95
-96
-97
-98
-99
-100
-101
-102
1.8
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
Voltage [V]
D034
Figure 5-15. Sensitivity vs. Supply Voltage (VDDS) (BLE 1 Mbps, 2.44 GHz)
Sensitivity vs. VDDS
BLE 1 Mbps, 2.44 GHz, DCDC Off
-92
-93
-94
-95
-96
-97
-98
-99
-100
-101
-102
1.8
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
Voltage [V]
D035
Figure 5-16. Sensitivity vs. Supply Voltage (VDDS) (BLE 1 Mbps, 2.44 GHz, DCDC Off)
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Sensitivity [dBm]
-95 -96 -97 -98 -99 -100 -101 -102 -103 -104 -105
1.8
Sensitivity vs. VDDS
IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps), 2.44 GHz
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
Voltage [V]
D036
Figure 5-17. Sensitivity vs. Supply Voltage (VDDS) (250 kbps, 2.44 GHz)
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5.15.5 TX Performance
Output Power [dBm]
Output Power vs. Temperature
BLE 1 Mbps, 2.44 GHz, 0 dBm
2 1.8 1.6 1.4 1.2
1 0.8 0.6 0.4 0.2
0 -0.2 -0.4 -0.6 -0.8
-1 -1.2 -1.4 -1.6 -1.8
-2 -40 -30 -20 -10 0
10 20 30 40 50 60 70 80 90 100
Temperature [°C]
D041
Figure 5-18. Output Power vs. Temperature (BLE 1 Mbps, 2.44 GHz)
Output Power [dBm]
Output Power vs. Temperature
BLE 1 Mbps, 2.44 GHz, +5 dBm
7
6.8
6.6
6.4
6.2
6
5.8
5.6
5.4
5.2
5
4.8
4.6
4.4
4.2
4
3.8
3.6
3.4
3.2
3
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature [°C]
D042
Figure 5-19. Output Power vs. Temperature (BLE 1 Mbps, 2.44 GHz, +5 dBm)
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Output Power [dBm]
Output Power vs. VDDS
BLE 1 Mbps, 2.44 GHz, 0 dBm
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
1.8
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
Voltage [V]
D046
Figure 5-20. Output Power vs. Supply Voltage (VDDS) (BLE 1 Mbps, 2.44 GHz)
Output Power [dBm]
Output power vs. VDDS
BLE 1 Mbps, 2.44 GHz, +5 dBm
7
6.8
6.6
6.4
6.2
6
5.8
5.6
5.4
5.2
5
4.8
4.6
4.4
4.2
4
3.8
3.6
3.4
3.2
3
1.8
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
Voltage [V]
D048
Figure 5-21. Output Power vs. Supply Voltage (VDDS) (BLE 1 Mbps, 2.44 GHz, +5 dBm)
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Output Power [dBm]
Output Power [dBm]
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2 1.8 1.6 1.4 1.2
1 0.8 0.6 0.4 0.2
0 -0.2 -0.4 -0.6 -0.8
-1 -1.2 -1.4 -1.6 -1.8
-2 2.4
Output Power vs. Frequency
BLE 1 Mbps, 2.44 GHz, 0 dBm
2.408 2.416 2.424 2.432 2.44 2.448 2.456 2.464 2.472
Frequency [GHz]
2.48
D058
Figure 5-22. Output Power vs. Frequency (BLE 1 Mbps, 2.44 GHz)
7 6.8 6.6 6.4 6.2
6 5.8 5.6 5.4 5.2
5 4.8 4.6 4.4 4.2
4 3.8 3.6 3.4 3.2
3 2.4
Output Power vs. Frequency
BLE 1 Mbps, 2.44 GHz, +5 dBm
2.408 2.416 2.424 2.432 2.44 2.448 2.456 2.464 2.472
Frequency [GHz]
2.48
D059
Figure 5-23. Output Power vs. Frequency (BLE 1 Mbps, 2.44 GHz, +5 dBm)
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5.15.6 ADC Performance
11.4 11.1
ENOB vs. Input Frequency
Internal Reference, No Averaging Internal Unscaled Reference, 14-bit Mode
10.8
ENOB [Bit]
10.5
10.2
9.9
9.6 0.2 0.3
0.5 0.7 1
2 3 4 5 6 7 8 10
Frequency [kHz]
20 30 40 50 70 100
D061
Figure 5-24. ENOB vs. Input Frequency
ENOB [Bit]
10.2 10.15
10.1 10.05
10 9.95
9.9 9.85
9.8 1
ENOB vs. Sampling Frequency
Vin = 3.0 V Sine wave, Internal reference, Fin = Fs / 10
2 3 4 5 6 7 8 10
20 30 40 50 70 100
Frequency [kHz]
200
D062
Figure 5-25. ENOB vs. Sampling Frequency
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DNL [LSB]
INL [LSB]
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INL vs. ADC Code
Vin = 3.0 V Sine wave, Internal reference, 200 kSamples/s
1.5
1
0.5
0
-0.5
-1
-1.5 0
400 800 1200 1600 2000 2400 2800 3200 3600 4000
ADC Code
D064
Figure 5-26. INL vs. ADC Code
DNL vs. ADC Code
Vin = 3.0 V Sine wave, Internal reference, 200 kSamples/s
2.5
2
1.5
1
0.5
0
-0.5 0
400 800 1200 1600 2000 2400 2800 3200 3600 4000
ADC Code
D065
Figure 5-27. DNL vs. ADC Code
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Voltage [V]
ADC Accuracy vs. Temperature
Vin = 1 V, Internal reference, 200 kSamples/s
1.01
1.009
1.008
1.007
1.006
1.005
1.004
1.003
1.002
1.001
1
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature [°C]
D066
Figure 5-28. ADC Accuracy vs. Temperature
Voltage [V]
ADC Accuracy vs. VDDS
Vin = 1 V, Internal reference, 200 kSamples/s
1.01
1.009
1.008
1.007
1.006
1.005
1.004
1.003
1.002
1.001
1
1.8
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
Voltage [V]
D067
Figure 5-29. ADC Accuracy vs. Supply Voltage (VDDS)
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6 Detailed Description
6.1 Overview
Section 1.4 shows the core modules of the CC2652R device.
6.2 System CPU The CC2652R SimpleLinkTM Wireless MCU contains an Arm® Cortex®-M4F system CPU, which runs the application and the higher layers of radio protocol stacks.
The system CPU is the foundation of a high-performance, low-cost platform that meets the system requirements of minimal memory implementation, and low-power consumption, while delivering outstanding computational performance and exceptional system response to interrupts.
Its features include the following: · ARMv7-M architecture optimized for small-footprint embedded applications · Arm Thumb®-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit
Arm core in a compact memory size · Fast code execution permits increased sleep mode time · Deterministic, high-performance interrupt handling for time-critical applications · Single-cycle multiply instruction and hardware divide · Hardware division and fast digital-signal-processing oriented multiply accumulate · Saturating arithmetic for signal processing · IEEE 754-compliant single-precision Floating Point Unit (FPU) · Memory Protection Unit (MPU) for safety-critical applications · Full debug with data matching for watchpoint generation
Data Watchpoint and Trace Unit (DWT) JTAG Debug Access Port (DAP) Flash Patch and Breakpoint Unit (FPB) · Trace support reduces the number of pins required for debugging and tracing Instrumentation Trace Macrocell Unit (ITM) Trace Port Interface Unit (TPIU) with asynchronous serial wire output (SWO) · Optimized for single-cycle flash memory access · Tightly connected to 8-KB 4-way random replacement cache for minimal active power consumption and wait states · Ultra-low-power consumption with integrated sleep modes · 48 MHz operation · 1.25 DMIPS per MHz
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6.3 Radio (RF Core)
The RF Core is a highly flexible and future proof radio module which contains an Arm Cortex-M0 processor that interfaces the analog RF and base-band circuitry, handles data to and from the system CPU side, and assembles the information bits in a given packet structure. The RF core offers a high level, command-based API to the main CPU that configurations and data are passed through. The Arm CortexM0 processor is not programmable by customers and is interfaced through the TI-provided RF driver that is included with the SimpleLink Software Development Kit (SDK).
The RF core can autonomously handle the time-critical aspects of the radio protocols, thus offloading the main CPU, which reduces power and leaves more resources for the user application. Several signals are also available to control external circuitry such as RF switches or range extenders autonomously.
Multiprotocol solutions are enabled through time-sliced access of the radio, handled transparently for the application through the TI-provided RF driver and dual-mode manager.
The various physical layer radio formats are partly built as a software defined radio where the radio behavior is either defined by radio ROM contents or by non-ROM radio formats delivered in form of firmware patches with the SimpleLink SDKs. This allows the radio platform to be updated for support of future versions of standards even with over-the-air (OTA) updates while still using the same silicon.
6.3.1 Bluetooth 5 low energy
The RF Core offers full support for Bluetooth 5 low energy, including the high-sped 2-Mbps physical layer and the 500-kbps and 125-kbps long range PHYs (Coded PHY) through the TI provided Bluetooth 5 stack or through a high-level Bluetooth API. The Bluetooth 5 PHY and part of the controller are in radio and system ROM, providing significant savings in memory usage and more space available for applications.
The new high-speed mode allows data transfers up to 2 Mbps, twice the speed of Bluetooth 4.2 and five times the speed of Bluetooth 4.0, without increasing power consumption. In addition to faster speeds, this mode offers significant improvements for energy efficiency and wireless coexistence with reduced radio communication time.
Bluetooth 5 also enables unparalleled flexibility for adjustment of speed and range based on application needs, which capitalizes on the high-speed or long-range modes respectively. Data transfers are now possible at 2 Mbps, enabling development of applications using voice, audio, imaging, and data logging that were not previously an option using Bluetooth low energy. With high-speed mode, existing applications deliver faster responses, richer engagement, and longer battery life. Bluetooth 5 enables fast, reliable firmware updates.
6.3.2 802.15.4 (Thread, Zigbee, 6LoWPAN)
Through a dedicated IEEE radio API, the RF Core supports the 2.4-GHz IEEE 802.15.4-2011 physical layer (2 Mchips per second Offset-QPSK with DSSS 1:8), used in Thread, Zigbee, and 6LoWPAN protocols. The 802.15.4 PHY and MAC are in radio and system ROM. TI also provides royalty-free protocol stacks for Thread and Zigbee as part of the SimpleLink SDK, enabling a robust end-to-end solution.
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6.4 Memory
The up to 352-KB nonvolatile (Flash) memory provides storage for code and data. The flash memory is insystem programmable and erasable. The last flash memory sector must contain a Customer Configuration section (CCFG) that is used by boot ROM and TI provided drivers to configure the device. This configuration is done through the ccfg.c source file that is included in all TI provided examples.
The ultra-low leakage system static RAM (SRAM) is split into up to five 16-KB blocks and can be used for both storage of data and execution of code. Retention of SRAM contents in Standby power mode is enabled by default and included in Standby mode power consumption numbers. Parity checking for detection of bit errors in memory is built-in, which reduces chip-level soft errors and thereby increases reliability. System SRAM is always initialized to zeroes upon code execution from boot.
To improve code execution speed and lower power when executing code from nonvolatile memory, a 4way nonassociative 8-KB cache is enabled by default to cache and prefetch instructions read by the system CPU. The cache can be used as a general-purpose RAM by enabling this feature in the Customer Configuration Area (CCFG).
There is a 4-KB ultra-low leakage SRAM available for use with the Sensor Controller Engine which is typically used for storing Sensor Controller programs, data and configuration parameters. This RAM is also accessible by the system CPU. The Sensor Controller RAM is not cleared to zeroes between system resets.
The ROM includes a TI-RTOS kernel and low-level drivers, as well as significant parts of selected radio stacks, which frees up flash memory for the application. The ROM also contains a serial (SPI and UART) bootloader that can be used for initial programming of the device.
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6.5 Sensor Controller
The Sensor Controller contains circuitry that can be selectively enabled in both Standby and Active power modes. The peripherals in this domain can be controlled by the Sensor Controller Engine, which is a proprietary power-optimized CPU. This CPU can read and monitor sensors or perform other tasks autonomously; thereby significantly reducing power consumption and offloading the system CPU.
The Sensor Controller Engine is user programmable with a simple programming language that has syntax similar to C. This programmability allows for sensor polling and other tasks to be specified as sequential algorithms rather than static configuration of complex peripheral modules, timers, DMA, register programmable state machines, or event routing.
The main advantages are: · Flexibility - data can be read and processed in unlimited manners while still ensuring ultra-low power · 2 MHz low-power mode enables lowest possible handling of digital sensors · Dynamic reuse of hardware resources · 40-bit accumulator supporting multiplication, addition and shift · Observability and debugging options
Sensor Controller Studio is used to write, test, and debug code for the Sensor Controller. The tool produces C driver source code, which the System CPU application uses to control and exchange data with the Sensor Controller. Typical use cases may be (but are not limited to) the following: · Read analog sensors using integrated ADC or comparators · Interface digital sensors using GPIOs, SPI, UART, or I2C (UART and I2C are bit-banged) · Capacitive sensing · Waveform generation · Very low-power pulse counting (flow metering) · Key scan
The peripherals in the Sensor Controller include the following: · The low-power clocked comparator can be used to wake the system CPU from any state in which the
comparator is active. A configurable internal reference DAC can be used in conjunction with the comparator. The output of the comparator can also be used to trigger an interrupt or the ADC. · Capacitive sensing functionality is implemented through the use of a constant current source, a timeto-digital converter, and a comparator. The continuous time comparator in this block can also be used as a higher-accuracy alternative to the low-power clocked comparator. The Sensor Controller takes care of baseline tracking, hysteresis, filtering, and other related functions when these modules are used for capacitive sensing. · The ADC is a 12-bit, 200-ksamples/s ADC with eight inputs and a built-in voltage reference. The ADC can be triggered by many different sources including timers, I/O pins, software, and comparators. · The analog modules can connect to up to eight different GPIOs · Dedicated SPI master with up to 6 MHz clock speed
The peripherals in the Sensor Controller can also be controlled from the main application processor.
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6.6 Cryptography
The CC2652R device comes with a wide set of modern cryptography-related hardware accelerators, drastically reducing code footprint and execution time for cryptographic operations. It also has the benefit of being lower power and improves availability and responsiveness of the system because the cryptography operations runs in a background hardware thread. Together with a large selection of open-source cryptography libraries provided with the Software Development Kit (SDK), this allows for secure and future proof IoT applications to be easily built on top of the platform. The hardware accelerator modules are: · True Random Number Generator (TRNG) module provides a true, nondeterministic noise source for
the purpose of generating keys, initialization vectors (IVs), and other random number requirements. The TRNG is built on 24 ring oscillators that create unpredictable output to feed a complex nonlinearcombinatorial circuit. · Secure Hash Algorithm 2 (SHA-2) with support for SHA224, SHA256, SHA384, and SHA512 · Advanced Encryption Standard (AES) with 128 and 256 bit key lengths · Public Key Accelerator - Hardware accelerator supporting mathematical operations needed for elliptic curves up to 512 bits and RSA key pair generation up to 1024 bits.
Through use of these modules and the TI provided cryptography drivers, the following capabilities are available for an application or stack: · Key Agreement Schemes
Elliptic curve DiffieHellman with static or ephemeral keys (ECDH and ECDHE) Elliptic curve Password Authenticated Key Exchange by Juggling (ECJ-PAKE) · Signature Generation Elliptic curve Diffie-Hellman Digital Signature Algorithm (ECDSA) · Curve Support Short Weierstrass form (full hardware support), such as:
· NIST-P224, NIST-P256, NIST-P384, NIST-P521 · Brainpool-256R1, Brainpool-384R1, Brainpool-512R1 · secp256r1 Montgomery form (hardware support for multiplication), such as: · Curve25519 · SHA2 based MACs HMAC with SHA224, SHA256, SHA384, or SHA512 · Block cipher mode of operation AESCCM AESGCM AESECB AESCBC AESCBC-MAC · True random number generation
Other capabilities, such as RSA encryption and signatures as well as Edwards type of elliptic curves such as Curve1174 or Ed25519, can also be implemented using the provided hardware accelerators but are not part of the TI SimpleLink SDK for the CC2652R device.
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6.7 Timers
A large selection of timers are available as part of the CC2652R device. These timers are:
· Real-Time Clock (RTC)
A 70-bit 3-channel timer running on the 32 kHz low frequency system clock (SCLK_LF) This timer is available in all power modes except Shutdown. The timer can be calibrated to compensate for frequency drift when using the LF RCOSC as the low frequency system clock. If an external LF clock with frequency different from 32.768 kHz is used, the RTC tick speed can be adjusted to compensate for this. When using TI-RTOS, the RTC is used as the base timer in the operating system and should thus only be accessed through the kernel APIs such as the Clock module. The real time clock can also be read by the Sensor Controller Engine to timestamp sensor data and also has dedicated capture channels. By default, the RTC halts when a debugger halts the device.
· General Purpose Timers (GPTIMER)
The four flexible GPTIMERs can be used as either 4× 32 bit timers or 8× 16 bit timers, all running on up to 48 MHz. Each of the 16- or 32-bit timers support a wide range of features such as one-shot or periodic counting, pulse width modulation (PWM), time counting between edges and edge counting. The inputs and outputs of the timer are connected to the device event fabric, which allows the timers to interact with signals such as GPIO inputs, other timers, DMA and ADC. The GPTIMERs are available in Active and Idle power modes.
· Sensor Controller Timers
The Sensor Controller contains 3 timers: AUX Timer 0 and 1 are 16-bit timers with a 2N prescaler. Timers can either increment on a clock or on each edge of a selected tick source. Both one-shot and periodical timer modes are available.
AUX Timer 2 is a 16-bit timer that can operate at 24 MHz, 2 MHz or 32 kHz independent of the Sensor Controller functionality. There are 4 capture or compare channels, which can be operated in one-shot or periodical modes. The timer can be used to generate events for the Sensor Controller Engine or the ADC, as well as for PWM output or waveform generation.
· Radio Timer
A multichannel 32-bit timer running at 4 MHz is available as part of the device radio. The radio timer is typically used as the timing base in wireless network communication using the 32-bit timing word as the network time. The radio timer is synchronized with the RTC by using a dedicated radio API when the device radio is turned on or off. This ensures that for a network stack, the radio timer seems to always be running when the radio is enabled. The radio timer is in most cases used indirectly through the trigger time fields in the radio APIs and should only be used when running the accurate 48 MHz high frequency crystal is the source of SCLK_HF.
· Watchdog timer
The watchdog timer is used to regain control if the system operates incorrectly due to software errors. It is typically used to generate an interrupt to and reset of the device for the case where periodic monitoring of the system components and tasks fails to verify proper functionality. The watchdog timer runs on a 1.5 MHz clock rate and cannot be stopped once enabled. The watchdog timer pauses to run in Standby power mode and when a debugger halts the device.
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6.8 Serial Peripherals and I/O
The SSIs are synchronous serial interfaces that are compatible with SPI, MICROWIRE, and TI's synchronous serial interfaces. The SSIs support both SPI master and slave up to 4 MHz. The SSI modules support configurable phase and polarity.
The UARTs implement universal asynchronous receiver and transmitter functions. They support flexible baud-rate generation up to a maximum of 3 Mbps.
The I2S interface is used to handle digital audio and can also be used to interface pulse-density modulation microphones (PDM).
The I2C interface is also used to communicate with devices compatible with the I2C standard. The I2C interface can handle 100 kHz and 400 kHz operation, and can serve as both master and slave.
The I/O controller (IOC) controls the digital I/O pins and contains multiplexer circuitry to allow a set of peripherals to be assigned to I/O pins in a flexible manner. All digital I/Os are interrupt and wake-up capable, have a programmable pullup and pulldown function, and can generate an interrupt on a negative or positive edge (configurable). When configured as an output, pins can function as either push-pull or open-drain. Five GPIOs have high-drive capabilities, which are marked in bold in Section 4. All digital peripherals can be connected to any digital pin on the device.
For more information, see the CC13x2, CC26x2 SimpleLinkTM Wireless MCU Technical Reference Manual.
6.9 Battery and Temperature Monitor
A combined temperature and battery voltage monitor is available in the CC2652R device. The battery and temperature monitor allows an application to continuously monitor on-chip temperature and supply voltage and respond to changes in environmental conditions as needed. The module contains window comparators to interrupt the system CPU when temperature or supply voltage go outside defined windows. These events can also be used to wake up the device from Standby mode through the AlwaysOn (AON) event fabric.
6.10 µDMA
The device includes a direct memory access (µDMA) controller. The µDMA controller provides a way to offload data-transfer tasks from the system CPU, thus allowing for more efficient use of the processor and the available bus bandwidth. The µDMA controller can perform a transfer between memory and peripherals. The µDMA controller has dedicated channels for each supported on-chip module and can be programmed to automatically perform transfers between peripherals and memory when the peripheral is ready to transfer more data.
Some features of the µDMA controller include the following (this is not an exhaustive list): · Highly flexible and configurable channel operation of up to 32 channels · Transfer modes: memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral · Data sizes of 8, 16, and 32 bits · Ping-pong mode for continuous streaming of data
6.11 Debug
The on-chip debug support is done through a dedicated cJTAG (IEEE 1149.7) or JTAG (IEEE 1149.1) interface. The device boots by default into cJTAG mode and must be reconfigured to use 4-pin JTAG.
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6.12 Power Management
To minimize power consumption, the CC2652R supports a number of power modes and power management features (see Table 6-1).
MODE
CPU Flash SRAM Supply System Register and CPU retention SRAM retention 48 MHz high-speed clock (SCLK_HF) 2 MHz medium-speed clock (SCLK_MF) 32 kHz low-speed clock (SCLK_LF) Peripherals Sensor Controller Wake-up on RTC Wake-up on pin edge Wake-up on reset pin Brownout detector (BOD) Power-on reset (POR) Watchdog timer (WDT)
Table 6-1. Power Modes
SOFTWARE CONFIGURABLE POWER MODES
ACTIVE
IDLE
STANDBY
Active
Off
Off
On
Available
Off
On
On
Retention
On
On
Duty Cycled
Full
Full
Partial
Full
Full
Full
XOSC_HF or RCOSC_HF
XOSC_HF or RCOSC_HF
Off
RCOSC_MF
RCOSC_MF
Available
XOSC_LF or RCOSC_LF
Available Available Available Available
On On On Available
XOSC_LF or RCOSC_LF
Available Available Available Available
On On On Available
XOSC_LF or RCOSC_LF
Off Available Available Available
On Duty Cycled
On Paused
SHUTDOWN Off Off Off Off No No
Off
Off
Off
Off Off Off Available On Off Off Off
RESET PIN HELD Off Off Off Off No No
Off
Off
Off
Off Off Off Off On Off Off Off
In Active mode, the application system CPU is actively executing code. Active mode provides normal operation of the processor and all of the peripherals that are currently enabled. The system clock can be any available clock source (see Table 6-1).
In Idle mode, all active peripherals can be clocked, but the Application CPU core and memory are not clocked and no code is executed. Any interrupt event brings the processor back into active mode.
In Standby mode, only the always-on (AON) domain is active. An external wake-up event, RTC event, or Sensor Controller event is required to bring the device back to active mode. MCU peripherals with retention do not need to be reconfigured when waking up again, and the CPU continues execution from where it went into standby mode. All GPIOs are latched in standby mode.
In Shutdown mode, the device is entirely turned off (including the AON domain and Sensor Controller), and the I/Os are latched with the value they had before entering shutdown mode. A change of state on any I/O pin defined as a wake from shutdown pin wakes up the device and functions as a reset trigger. The CPU can differentiate between reset in this way and reset-by-reset pin or power-on reset by reading the reset status register. The only state retained in this mode is the latched I/O state and the flash memory contents.
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The Sensor Controller is an autonomous processor that can control the peripherals in the Sensor Controller independently of the system CPU. This means that the system CPU does not have to wake up, for example to perform an ADC sampling or poll a digital sensor over SPI, thus saving both current and wake-up time that would otherwise be wasted. The Sensor Controller Studio tool enables the user to program the Sensor Controller, control its peripherals, and wake up the system CPU as needed. All Sensor Controller peripherals can also be controlled by the system CPU.
NOTE The power, RF and clock management for the CC2652R device require specific configuration and handling by software for optimized performance. This configuration and handling is implemented in the TI-provided drivers that are part of the CC2652R software development kit (SDK). Therefore, TI highly recommends using this software framework for all application development on the device. The complete SDK with TI-RTOS (optional), device drivers, and examples are offered free of charge in source code.
6.13 Clock Systems
The CC2652R device has several internal system clocks.
The 48 MHz SCLK_HF is used as the main system (MCU and peripherals) clock. This can be driven by the internal 48 MHz RC Oscillator (RCOSC_HF) or an external 48 MHz crystal (XOSC_HF). Radio operation requires an external 48 MHz crystal.
SCLK_MF is an internal 2 MHz clock that is used by the Sensor Controller in low-power mode and also for internal power management circuitry. The SCLK_MF clock is always driven by the internal 2 MHz RC Oscillator (RCOSC_MF).
SCLK_LF is the 32.768 kHz internal low-frequency system clock. It can be used by the Sensor Controller for ultra-low-power operation and is also used for the RTC and to synchronize the radio timer before or after Standby power mode. SCLK_LF can be driven by the internal 32.8 kHz RC Oscillator (RCOSC_LF), a 32.768 kHz watch-type crystal, or a clock input on any digital IO.
When using a crystal or the internal RC oscillator, the device can output the 32 kHz SCLK_LF signal to other devices, thereby reducing the overall system cost.
6.14 Network Processor
Depending on the product configuration, the CC2652R device can function as a wireless network processor (WNP - a device running the wireless protocol stack with the application running on a separate host MCU), or as a system-on-chip (SoC) with the application and protocol stack running on the system CPU inside the device.
In the first case, the external host MCU communicates with the device using SPI or UART. In the second case, the application must be written according to the application framework supplied with the wireless protocol stack.
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7 Application, Implementation, and Layout
NOTE Information in the following Applications section is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
For general design guidelines and hardware configuration guidelines, refer to CC13xx/CC26xx Hardware Configuration and PCB Design Considerations Application Report.
7.1 Reference Designs
The following reference designs should be followed closely when implementing designs using the CC2652R device.
Special attention must be paid to RF component placement, decoupling capacitors and DCDC regulator components, as well as ground connections for all of these.
CC26x2REM-7ID Design Files SPACER The CC26x2REM-7ID reference design provides schematic, layout and production files for the characterization board used for deriving the performance number found in this document.
LAUNCHXL-CC26X2R1 Design Files SPACER The CC26X2R LaunchPad Design Files contain detailed schematics and layouts to build application specific boards using the CC2652R device. This design applies to both the CC2642R and CC2652R devices.
Sub-1 GHz and 2.4 GHz Antenna Kit for LaunchPadTM Development Kit and SensorTag SPACER The antenna kit allows real-life testing to identify the optimal antenna for your application. The antenna kit includes 16 antennas for frequencies from 169 MHz to 2.4 GHz, including: · PCB antennas · Helical antennas · Chip antennas · Dual-band antennas for 868 MHz and 915 MHz combined with 2.4 GHz
The antenna kit includes a JSC cable to connect to the Wireless MCU LaunchPad Development Kits and SensorTags.
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7.2 Junction Temperature Calculation
This section shows the different techniques for calculating the junction temperature under various operating conditions. For more details, see Semiconductor and IC Package Thermal Metrics.
There are three recommended ways to derive the junction temperature from other measured temperatures:
1. From package temperature: (1)
2. From board temperature: (2)
3. From ambient temperature: (3)
P is the power dissipated from the device and can be calculated by multiplying current consumption with supply voltage. Thermal resistance coefficients are found in Section 5.8.
Example:
Using Equation 3, the temperature difference between ambient temperature and junction temperature is calculated. In this example, we assume a simple use case where the radio is transmitting continuously at 0 dBm output power. Let us assume the ambient temperature is 85 °C and the supply voltage is 3 V. To calculate P, we need to look up the current consumption for Tx at 85 °C in Figure 5-9. From the plot, we see that the current consumption is 7.8 mA. This means that P is 7.8 mA × 3 V = 23.4 mW.
The junction temperature is then calculated as:
(4)
As can be seen from the example, the junction temperature is 0.6 °C higher than the ambient temperature when running continuous Tx at 85 °C and, thus, well within the recommended operating conditions.
For various application use cases current consumption for other modules may have to be added to calculate the appropriate power dissipation. For example, the MCU may be running simultaneously as the radio, peripheral modules may be enabled, etc. Typically, the easiest way to find the peak current consumption, and thus the peak power dissipation in the device, is to measure as described in Measuring CC13xx and CC26xx current consumption.
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8 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed as follows.
8.1 Tools and Software
The CC2652R device is supported by a variety of software and hardware development tools.
Development Kit
CC26x2 LaunchPadTM Development Kit SPACER The CC26x2R LaunchPadTM Development Kit enables development of high-performance wireless applications that benefit from low-power operation. The kit features the CC2652R SimpleLink Wireless MCU, which allows you to quickly evaluate and prototype 2.4-GHz wireless applications such as Bluetooth 5 Low Energy, Zigbee and Thread, plus combinations of these. The kit works with the LaunchPad ecosystem, easily enabling additional functionality like sensors, display and more. The built-in EnergyTraceTM software is an energy-based code analysis tool that measures and displays the application's energy profile and helps to optimize it for ultra-low-power consumption. See Table 3-1 for guidance in selecting the correct device for single-protocol products.
Software
SimpleLinkTM CC13X2-CC26X2 SDK SPACER The SimpleLink CC13X2-CC26X2 Software Development Kit (SDK) provides a complete package for the development of wireless applications on the CC13X2 / CC26X2 family of devices. The SDK includes a comprehensive software package for the CC2652R device, including the following protocol stacks: · Bluetooth Low Energy 4 and 5 · Thread (based on OpenThread) · Zigbee 3.0 · TI 15.4-Stack - an IEEE 802.15.4-based star networking solution for Sub-1 GHz and 2.4 GHz · EasyLink - a large set of building blocks for building proprietary RF software stacks · Multiprotocol support - concurrent operation between stacks using the Dynamic Multiprotocol Manager (DMM) The SimpleLink CC13X2-CC26X2 SDK is part of TI's SimpleLink MCU platform, offering a single development environment that delivers flexible hardware, software and tool options for customers developing wired and wireless applications. For more information about the SimpleLink MCU Platform, visit http://www.ti.com/simplelink.
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Development Tools
Code Composer StudioTM Integrated Development Environment (IDE) SPACER
Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment, debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking you through each step of the application development flow. Familiar tools and interfaces allow users to get started faster than ever before. Code Composer Studio combines the advantages of the Eclipse® software framework with advanced embedded debug capabilities from TI resulting in a compelling feature-rich development environment for embedded developers.
CCS has support for all SimpleLink Wireless MCUs and includes support for EnergyTraceTM software (application energy usage profiling). A real-time object viewer plugin is available for TI-RTOS, part of the SimpleLink SDK.
Code Composer Studio is provided free of charge when used in conjunction with the XDS debuggers included on a LaunchPad Development Kit.
Code Composer StudioTM Cloud IDE SPACER
Code Composer Studio (CCS) Cloud is a web-based IDE that allows you to create, edit and build CCS and EnergiaTM projects. After you have successfully built your project, you can download and run on your connected LaunchPad. Basic debugging, including features like setting breakpoints and viewing variable values is now supported with CCS Cloud.
IAR Embedded Workbench® for Arm® SPACER IAR Embedded Workbench® is a set of development tools for building and debugging embedded system applications using assembler, C and C++. It provides a completely integrated development environment that includes a project manager, editor, and build tools. IAR has support for all SimpleLink Wireless MCUs. It offers broad debugger support, including XDS110, IAR I-jetTM and Segger J-LinkTM. A real-time object viewer plugin is available for TI-RTOS, part of the SimpleLink SDK. IAR is also supported out-of-the-box on most software examples provided as part of the SimpleLink SDK.
A 30-day evaluation or a 32 KB size-limited version is available through iar.com.
SmartRFTM Studio SPACER SmartRFTM Studio is a Windows® application that can be used to evaluate and configure SimpleLink Wireless MCUs from Texas Instruments. The application will help designers of RF systems to easily evaluate the radio at an early stage in the design process. It is especially useful for generation of configuration register values and for practical testing and debugging of the RF system. SmartRF Studio can be used either as a standalone application or together with applicable evaluation boards or debug probes for the RF device. Features of the SmartRF Studio include:
· Link tests - send and receive packets between nodes
· Antenna and radiation tests - set the radio in continuous wave TX and RX states
· Export radio configuration code for use with the TI SimpleLink SDK RF driver
· Custom GPIO configuration for signaling and control of external switches
Sensor Controller Studio SPACER
Sensor Controller Studio is used to write, test and debug code for the Sensor Controller peripheral. The tool generates a Sensor Controller Interface driver, which is a set of C source files that are compiled into the System CPU application. These source files also contain the Sensor Controller binary image and allow the System CPU application to control and exchange data with the Sensor Controller. Features of the Sensor Controller Studio include:
· Ready-to-use examples for several common use cases
· Full toolchain with built-in compiler and assembler for programming in a C-like programming language
· Provides rapid development by using the integrated sensor controller task testing and debugging functionality, including visualization of sensor data and verification of algorithms
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CCS UniFlash SPACER CCS UniFlash is a standalone tool used to program on-chip flash memory on TI MCUs. UniFlash has a GUI, command line, and scripting interface. CCS UniFlash is available free of charge.
8.1.1 SimpleLinkTM Microcontroller Platform
The SimpleLink microcontroller platform sets a new standard for developers with the broadest portfolio of wired and wireless Arm® MCUs (System-on-Chip) in a single software development environment. Delivering flexible hardware, software and tool options for your IoT applications. Invest once in the SimpleLink software development kit and use throughout your entire portfolio. Learn more on ti.com/simplelink.
8.2 Documentation Support
To receive notification of documentation updates on data sheets, errata, application notes and similar, navigate to the device product folder on ti.com/product/CC2652R. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
The current documentation that describes the MCU, related peripherals, and other technical collateral is listed as follows.
TI Resource Explorer
TI Resource Explorer SPACER Software examples, libraries, executables, and documentation are available for your device and development board.
Errata
CC2652R Silicon Errata SPACER The silicon errata describes the known exceptions to the functional specifications for each silicon revision of the device and description on how to recognize a device revision.
Application Reports
All application reports for the CC2652R device are found on the device product folder at: ti.com/product/CC2652R/technicaldocuments.
Technical Reference Manual (TRM)
CC13x2, CC26x2 SimpleLinkTM Wireless MCU TRM SPACER The TRM provides a detailed description of all modules and peripherals available in the device family.
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8.3 Support Resources
TI E2ETM support forums are an engineer's go-to source for fast, verified answers and design help -- straight from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
8.4 Trademarks
SimpleLink, SmartRF, LaunchPad, EnergyTrace, Code Composer Studio, E2E are trademarks of Texas Instruments. Arm, Cortex, Arm Thumb are registered trademarks of Arm Limited (or its subsidiaries). Bluetooth is a registered trademark of Bluetooth SIG Inc. Eclipse is a registered trademark of Eclipse Foundation. CoreMark is a registered trademark of Embedded Microprocessor Benchmark Consortium. I-jet is a trademark of IAR Systems AB. IAR Embedded Workbench is a registered trademark of IAR Systems AB. Windows is a registered trademark of Microsoft Corporation. J-Link is a trademark of SEGGER Microcontroller Systeme GmbH. Wi-Fi is a registered trademark of Wi-Fi Alliance. Wi-SUN is a registered trademark of Wi-SUN Alliance Inc. Zigbee is a registered trademark of Zigbee Alliance Inc. All other trademarks are the property of their respective owners.
8.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions.
9 Mechanical, Packaging, and Orderable Information
9.1 Packaging Information
The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Mechanical, Packaging, and Orderable Information
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PACKAGING INFORMATION
Orderable Device CC2652R1FRGZR CC2652R1FRGZT
Status Package Type Package Pins Package Eco Plan
(1)
Drawing
Qty
(2)
ACTIVE
VQFN
RGZ 48 2500 Green (RoHS & no Sb/Br)
ACTIVE
VQFN
RGZ 48 250 Green (RoHS & no Sb/Br)
Lead/Ball Finish
(6)
CU NIPDAU | CU NIPDAUAG
CU NIPDAU | CU NIPDAUAG
MSL Peak Temp Op Temp (°C)
(3)
Level-3-260C-168 HR -40 to 85
Level-3-260C-168 HR -40 to 85
(1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
Device Marking
(4/5)
CC2652 R1F
CC2652 R1F
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Samples
Addendum-Page 1
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PACKAGE OPTION ADDENDUM
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Addendum-Page 2
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TAPE AND REEL INFORMATION
PACKAGE MATERIALS INFORMATION
21-Aug-2019
*All dimensions are nominal
Device
Package Package Pins Type Drawing
CC2652R1FRGZR CC2652R1FRGZT
VQFN RGZ 48 VQFN RGZ 48
SPQ
2500 250
Reel Reel A0 Diameter Width (mm)
(mm) W1 (mm)
330.0 16.4 7.3
180.0 16.4 7.3
B0 (mm)
7.3 7.3
K0 (mm)
1.1 1.1
P1 (mm)
12.0 12.0
W
Pin1
(mm) Quadrant
16.0
Q2
16.0
Q2
Pack Materials-Page 1
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PACKAGE MATERIALS INFORMATION
21-Aug-2019
*All dimensions are nominal Device
CC2652R1FRGZR CC2652R1FRGZT
Package Type VQFN VQFN
Package Drawing Pins
RGZ
48
RGZ
48
SPQ 2500 250
Length (mm) 336.6 210.0
Width (mm) 336.6 185.0
Height (mm) 31.8 35.0
Pack Materials-Page 2
RGZ 48
7 x 7, 0.5 mm pitch
GENERIC PACKAGE VIEW
VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD
Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details.
4224671/A
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RGZ0048A
B
7.1 6.9
PACKAGE OUTLINE
VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD
A
PIN 1 INDEX AREA
1 MAX
0.05 0.00
44X 0.5
13 12
2X 5.5
7.1 6.9
2X 5.5 5.15±0.1
(0.1) TYP
SIDE WALL DETAIL OPTIONAL METAL THICKNESS
C
SEATING PLANE 0.08 C
24 25
SEE SIDE WALL DETAIL
(0.2) TYP
SYMM
PIN1 ID (OPTIONAL)
1 48
SYMM
36
37
48X
0.5 0.3
48X
0.30 0.18
0.1
0.05
CAB C
NOTES:
4219044/B 08/2019
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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RGZ0048A
48X (0.6)
48
48X (0.24)
44X (0.5)
1
2X (6.8) ( 5.15) SYMM
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD
35
34
2X SYMM (5.5)
2X (6.8)
2X (1.26)
(R0.05) TYP
12
21X (Ø0.2) VIA TYP
13
2X (1.26)
2X (5.5)
LAND PATTERN EXAMPLE
SCALE: 15X
2X (1.065)
23
22 2X (1.065)
NOTES: (continued)
0.07 MAX ALL AROUND
0.07 MIN ALL AROUND
EXPOSED METAL
METAL
SOLDER MASK OPENING
NON SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DEFINED
SOLDER MASK DETAILS
SOLDER MASK OPENING EXPOSED METAL
METAL UNDER SOLDER MASK
4219044/B 08/2019
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented.
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RGZ0048A
48X (0.6) 48X (0.24) 44X (0.5)
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8) SYMM
( 1.06)
2X SYMM (5.5)
(R0.05) TYP
2X 2X (6.8) (0.63)
2X (1.26)
2X (0.63) 2X (5.5)
2X (1.26)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 67% PRINTED COVERAGE BY AREA
SCALE: 15X
NOTES: (continued)
4219044/B 08/2019
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
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