Simon Doherty

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Mga Tool sa Pag-develop ng Programmable Logic IC – Mouser Philippines

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Zipcores zip fmc brk user guide a1-3106058

Zipcores FMC-BRK Mezzanine Card Hardware User Guide
ZIP-FMC-BRK Rev. A.1
Hardware User Guide Zipcores FMC-BRK Mezzanine Card
ZIP-FMC-BRK Rev. A.1 March 2023

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Zipcores FMC-BRK Mezzanine Card
Hardware User Guide
ZIP-FMC-BRK Rev. A.1
Table of Contents
Overview.................................................................................................................................................................... 3
Introduction............................................................................................................................................................ 3 Board layout.......................................................................................................................................................... 3 Key features.......................................................................................................................................................... 4
Detailed description................................................................................................................................................. 5
FMC header connectors........................................................................................................................................ 5 User LEDs............................................................................................................................................................. 5 User push-button switches.................................................................................................................................... 6 User 100 MHz clock oscillator............................................................................................................................... 6 FMC power supplies.............................................................................................................................................. 7 User prototyping area............................................................................................................................................ 7 ANSI/VITA 57.1 FMCTM connector........................................................................................................................ 7
Appendices............................................................................................................................................................... 8
Appendix A: Examples of supported FMC base-boards........................................................................................9 Appendix B: FMC Connector pinout (rows H, G, D, C)........................................................................................ 10 Appendix C: List of supporting design files.......................................................................................................... 11 Appendix D: Running the example demo............................................................................................................ 12
Revision history...................................................................................................................................................... 14

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Zipcores FMC-BRK Mezzanine Card
Hardware User Guide
ZIP-FMC-BRK Rev. A.1
Overview
Introduction
The Zipcores FMC-BRK Mezzanine card is a versatile FMC breakout-board and prototyping platform that conforms to the ANSI/VITA 57.1 FMCTM mezzanine standard. The card is compatible with a wide range of base-boards and FMC-compliant systems. Examples include evaluation boards from Xilinx®, Intel®, Avnet® and Digilent®. The card provides passive connectivity to all 160 signals on the FMC (LPC) connector via 4 x standard 0.100" pitch (2.54 mm) headers. This includes 34 x differential LVDS pairs (LA00:33) or 68 x single-ended signals. The differential pairs are balanced for track length and impedance-matched for 100 LVDS termination. The ground pins of the FMC are also connected to an independent ground plane to offer the best possible signal integrity and noise immunity. The card is ideal for the development high-speed LVDS and other high-speed differential interfaces such as those required in displays, cameras, image sensors, ADCs, DACs and general purpose serial connectivity. The FMC card also provides access to the 2 x Gigabit Transceiver Pairs (GTP), GTP clock, 2 x user clock pairs, I2C, JTAG, state flags, power supplies and ground pins. As well as breaking out all the FMC pins, the card also provides easy access to the FMC power supplies as separate PCB through-hole vias. All power pins are independently de-coupled with a 100nF capacitor to the ground plane. Other features on the card include: 8 x indicator LEDs, 4 x push-button switches (with RC de-bouncing) and a single-ended 100 MHz clock oscillator. The LEDs, buttons and oscillator may be powered by either the VADJ or 3.3V supply on the card. In this way, the component I/O can be made compatible with the desired I/O voltage. Finally, the FMC-BRK card provides a standard pitch 0.100" (2.54 mm) prototyping area of 12 x 22 through-holes. This area is ideal for implementing custom circuitry and extending the functionality of the card for different user applications. Figures (1) and (2) show the general board layout and the distribution of main board components.
Board layout

Figure 1: ZIP-FMC-BRK Rev. A board (top view)

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Zipcores FMC-BRK Mezzanine Card
Hardware User Guide
ZIP-FMC-BRK Rev. A.1

Figure 2: ZIP-FMC-BRK Rev. A board (bottom view)

Key features

- Standard ANSI/VITA 57.1 FMCTM LPC connector
- Also compatible with FMC HPC (but only LPC pins used)
- 4 x headers provide passive connectivity to all 160 pins on the FMC connector (rows C, D, G and H)
- All pin and through-hole spacings are standard 0.100" pitch or 2.54 mm
- Access to 34 x differential pairs (LA00:33), 68 x singleended signals or a mixture of either
- Access to 2 x GTP transceiver pairs including GTP clock
- Access to 2 x user-clock differential pairs
- Access to the I2C, JTAG and FMC state flags
- Access to the VADJ, 3.3V and 12V FMC power supplies
- All differential pairs routed with the same track lengths
- All differential signals impedance-matched for LVDS 100 termination

- Dimensions approx 10 x 6.7 cm
- Separate VADJ, 3.3V, 12V and GND through-hole vias
- Separate power pins de-coupled to ground with 100 nF capacitors
- Separate PCB ground-plane for improved signal integrity and noise immunity
- Features large 22 x 12 prototyping area for custom circuitry and user-defined functions
- 8 x user LEDs with 332 series resistors
- 4 x user push-buttons with RC de-bouncing circuit
- 100 MHz low-jitter single-ended clock oscillator
- 2 x M3 mounting holes for securing the FMC connector
- 2 x M3 mounting holes for supporting standoff `legs'
- Compatible with a wide range of FMC base-boards and FMC-compliant systems

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Hardware User Guide
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Detailed description
FMC header connectors
The 160 x FMC signals are routed to four (2 x 20) header connectors as shown in Figure (3) below. A separate 40-pin header is allocated to each row of the FMC connector such that row C maps to J1, row D maps to J2, row G maps to J3 and row H maps to J4. The pin numbering also exactly matches the signal numbering in the VITA 57.1 specification. So, for instance, row C pin 10 on connector J1 is the signal `LA06_P' which corresponds to signal C10 of the VITA specification. A full list of the FMC connector pinouts are also given in Appendix B at the end of this document.

GND GND GND GA0 GND SCL GND LA27_P GND LA18_P_CC GND LA14_P GND LA10_P GND LA06_P GND DP0_M2C_P GND DP0_C2M_P

40 39

38 37

36 35

34 33

32 31

30 29

28 27

26 25

24 23

22 21

20 19

18 17

16 15

14 13

12 11

10 9

3P3V 12P0V 12P0V GND SDA GND LA27_N GND LA18_N_CC GND LA14_N GND LA10_N GND LA06_N GND DP0_M2C_N GND DP0_C2M_N GND

ROW C

3P3V 3P3V 3P3V TRST_L 3P3VAUX
TDI GND LA26_P LA23_N GND LA17_P_CC LA13_N GND LA09_P LA05_N GND LA01_P_CC GND GBTCLK0_M2C_P GND

40 39

38 37

36 35

34 33

32 31

30 29

28 27

26 25

24 23

22 21

20 19

18 17

16 15

14 13

12 11

10 9

GND GND GA1 TMS TDO TCK LA26_N GND LA23_P LA17_N_CC GND LA13_P LA09_N GND LA05_P LA01_N_CC GND GBTCLK0_M2C_N GND PG_C2M

GND GND LA33_P LA31_N GND LA29_P LA25_N GND LA22_P LA20_N GND LA16_P LA12_N GND LA08_P LA03_N GND LA00_P_CC GND CLK1_M2C_P

40 39

38 37

36 35

34 33

32 31

30 29

28 27

26 25

24 23

22 21

20 19

18 17

16 15

14 13

12 11

10 9

VADJ LA33_N GND LA31_P LA29_N GND LA25_P LA22_N GND LA20_P LA16_N GND LA12_P LA08_N GND LA03_P LA00_N_CC GND CLK1_M2C_N GND

ROW D

ROW G

VADJ LA32_N
GND LA30_P LA28_N
GND LA24_P LA21_N
GND LA19_P LA15_N
GND LA11_P LA07_N
GND LA04_P LA02_N
GND CLK0_M2C_P PRSNT_M2C_L

40 39

38 37

36 35

34 33

32 31

30 29

28 27

26 25

24 23

22 21

20 19

18 17

16 15

14 13

12 11

10 9

GND LA32_P LA30_N GND LA28_P LA24_N GND LA21_P LA19_N GND LA15_P LA11_N GND LA07_P LA04_N GND LA02_P CLK0_M2C_N GND VREF_A_M2C

ROW H

Figure 3: FMC signals mapped to 4 x 40-pin header connectors

User LEDs
The FMC card provides 8 x general purpose indicator LEDs. Each LED is in series with a 332 resistor to ground. The input to the LED circuit is a through-hole on the card that allows the LED to be driven using a simple hook-up wire or soldered connection. The maximum recommended driving voltage is 3.3V. Figure (4) below shows the LED circuit of which there are 8 in total.

VIA Hole (input)

332R

LED Green

GND

Figure 4: General purpose LED indicator circuit (active high LED on)

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Hardware User Guide
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User push-button switches
The card features 4 x push-button switches for general purpose use. Each switch is de-bounced with a passive RC circuit. The switches are designed as active-low switches with a button press driving the output low. As with the LED circuits, the switch outputs must be connected using hook-up wire or a soldered connection. The switches may be powered by either the VADJ or 3.3V supply on the card. Again, the switch power supply must be provided by a hook-up wire or soldered connection to the power vias. The power vias for each switch are labelled V1, V2, V3 and V4 on the FMC card. Figure (5) shows the push-button circuit of which there are 4 in total.

VADJ or 3.3V (input power)

VIA Hole

4K75

Push Button

100n

VIA Hole (output)

GND
Figure 5: Push-button switches (active low button press)

User 100 MHz clock oscillator
A precision single-ended clock oscillator is provided on the board part number: SG-8018CB from EPSON. As with the other user circuits on the card, the IC power supply and output are connected using a through-hole via. The 100 MHz oscillator power supply voltage can be anything from 1.62 V to 3.63 V. This means that either the VADJ or 3.3V supply on the FMC card may be used to power the device. Figure (6) shows the circuit diagram of the oscillator1.

VADJ or 3.3V (input power)

VIA Hole V0

VCC

100n

GND OUT
SG-8018CB 100.0000M

GND 15p

GND

Figure 6: 100 MHz precision clock oscillator circuit

VIA Hole (100 MHz output)

1 Note: on some boards the oscillator is replaced by a 50 MHz version of equivalent specification. Part number: SG-8018CB 50.0000M

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FMC power supplies
All the FMC standard power pins are made available on the FMC-BRK mezzanine card. As well as routing power to the FMC breakout header connectors, the card provides the VADJ, 3.3V and 12V power supplies as separate through-hole vias. These extra supplies are de-coupled with 100 nF capacitors to the ground plane. In addition to the separate power pins, a row of 9 x ground pins are provided on the card to allow for easy prototyping.
User prototyping area
The user prototyping area is a grid of 22 x 12 through-holes on the card. The prototyping area is idea for designing custom circuits and adding extra functionality to the FMC-card or main base-board. The area is large enough to support other small development boards, extra connectors or custom connectivity between external peripherals. The holes in the prototyping area are standard 0.100" pitch or 2.54 mm.
ANSI/VITA 57.1 FMCTM connector
The mezzanine card uses a standard ANSI/VITA 57.1 FMC connector. The pinouts of the connector are configured with the Low-Pin-Count (LPC) option occupying rows D/C and G/H. Although the pinouts are designed for the LPC connector, the mezzanine card is also compatible with the High-Pin-Count connector (HPC). Note that in the case of HPC then rows A/B, E/F and K/J will be left unconnected. A detailed specification of the FMC connector may be found on the Samtec® website just here: www.samtec.com/standards/vita/fmc
The FMC standard connector is used in a wide selection of FPGA development boards from vendors such as Xilinx®, Intel®, Avnet® and Digilent®. Xilinx in particular have adopted the FMC standard in all their FPGA and SoC development boards. Appendix A gives some examples of FMC-compatible base-boards. More information can be found on the Xilinx website just here: www.xilinx.com/products/boards-and-kits/fmc-cards.html
A full description of the FMC connector pinout with the mezzanine card is given in Appendix B.

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Appendices

Zipcores FMC-BRK Mezzanine Card
Hardware User Guide
ZIP-FMC-BRK Rev. A.1

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Appendix A: Examples of supported FMC base-boards

ZYNQ-BASED SYSTEMS
Base-board name
ZedBoard www.zedboard.org/product/zedboar d
MicroZed FMC Carrier Card www.zedboard.org/product/microzed-fmc-carrier
PicoZed FMC Carrier Card V2 www.zedboard.org/product/picozed-fmc-carrier-card-v2
Xilinx Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit www.xilinx.com/products/boards-and-kits/zcu104.htm l
Xilinx Zynq-7000 SoC ZC702 Evaluation Kit www.xilinx.com/products/boards-and-kits/ek-z7-zc702-g.htm l
Xilinx Zynq-7000 SoC ZC706 Evaluation Kit www.xilinx.com/products/boards-and-kits/ek-z7-zc706-g.htm l

Supplier

No. of FMCs

Digilent/Avnet 1 x LPC

Avnet

1 x LPC

Avnet

1 x LPC

Xilinx/Avnet 1 x LPC

Xilinx/Avnet 2 x LPC

Xilinx/Avnet 1 x LPC + 1 x HPC

VADJ options 1.8V, 2.5V, 3.3V 1.8V, 2.5V, 3.3V 1.8V, 2.5V, 3.3V 1.2V, 1.5V, 1.8V 2.5V fixed 2.5V fixed

GENERAL FPGA-BASED SYSTEMS
Base-board name
Spartan-7 SP701 FPGA Evaluation Kit www.xilinx.com/products/boards-and-kits/sp701.htm l
Nexys Video Artix-7 FPGA www.store.digilentinc.com/nexys-video-artix-7-fpga-trainer-board-formultimedia-applications/
Xilinx Artix-7 FPGA AC701 Evaluation Kit www.xilinx.com/products/boards-and-kits/ek-a7-ac701-g.htm l
Xilinx Kintex-7 FPGA KC705 Evaluation Kit www.xilinx.com/products/boards-and-kits/ek-k7-kc705-g.htm l
Genesys 2 Kintex-7 FPGA Development Board www.store.digilentinc.com/genesys-2-kintex-7-fpga-development-board/
NetFPGA-1G-CML Kintex-7 FPGA Development Board www.store.digilentinc.com/netfpga-1g-cml-kintex-7-fpga-development-board/
Xilinx Virtex-7 FPGA VC707 Evaluation Kit www.xilinx.com/products/boards-and-kits/ek-v7-vc707-g.htm l
Xilinx Virtex-7 FPGA VC709 Connectivity Kit www.xilinx.com/products/boards-and-kits/dk-v7-vc709-g.htm l
NetFPGA-SUME Virtex-7 FPGA Development Board www.store.digilentinc.com/netfpga-sume-virtex-7-fpga-development-board/

Supplier Xilinx/Avnet Digilent
Xilinx/Avnet Xilinx/Avnet Digilent Digilent Xilinx/Avnet Xilinx/Avnet Digilent

No. of FMCs 1 x LPC 1 x LPC
1 x HPC 1 x LPC + 1 x HPC 1 x HPC 1 x HPC 2 x HPC 2 x HPC 1 x HPC

VADJ options 1.8, 2.5V, 3.3V
1.2V, 1.8V, 2.5V, 3.3V
1.8V, 2.5V, 3.3V
1.8V, 2.5V, 3.3V
1.2V, 1.8V, 2.5V, 3.3V 1.2V, 1.8V, 2.5V, 3.3V 1.2V, 1.5V, 1.8V
1.8V fixed
1.2V, 1.8V, 2.5V, 3.3V

ULTRASCALE-BASED SYSTEMS
Base-board name
Xilinx Kintex UltraScale FPGA KCU105 Evaluation Kit www.xilinx.com/products/boards-and-kits/kcu105.html
Xilinx Kintex UltraScale FPGA KCU1250 Characterization Kit www.xilinx.com/products/boards-and-kits/ck-u1-kcu1250-g.html
Xilinx Kintex UltraScale+ FPGA KCU116 Evaluation Kit www.xilinx.com/products/boards-and-kits/ek-u1-kcu116-g.htm l
Xilinx Virtex UltraScale FPGA VCU108 Evaluation Kit www.xilinx.com/products/boards-and-kits/ek-u1-vcu108-g.html
Xilinx Virtex UltraScale+ FPGA VCU118 Evaluation Kit www.xilinx.com/products/boards-and-kits/vcu118.htm l

Supplier Xilinx/Avnet

No. of FMCs 1 x LPC + 1 x HPC

Xilinx/Avnet 3 x HPC

Xilinx/Avnet 1 x HPC (partial)

Xilinx/Avnet 2 x HPC

Xilinx/Avnet 1 x HPC

VADJ options 1.2V, 1.5V, 1.8V 1.8V fixed 1.8V fixed 1.2V, 1.5V, 1.8V 1.2V, 1.5V, 1.8V

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Appendix B: FMC Connector pinout (rows H, G, D, C)

FMC pin H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 H35 H36 H37 H38 H39 H40

VITA net name VREF_A_M2C PRSNT_M2C_L GND CLK0_M2C_P CLK0_M2C_N GND LA02_P LA02_N GND LA04_P LA04_N GND LA07_P LA07_N GND LA11_P LA11_N GND LA15_P LA15_N GND LA19_P LA19_N GND LA21_P LA21_N GND LA24_P LA24_N GND LA28_P LA28_N GND LA30_P LA30_N GND LA32_P LA32_N GND VADJ

FMC pin G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40

VITA net name GND CLK1_M2C_P CLK1_M2C_N GND GND LA00_P_CC LA00_N_CC GND LA03_P LA03_N GND LA08_P LA08_N GND LA12_P LA12_N GND LA16_P LA16_N GND LA20_P LA20_N GND LA22_P LA22_N GND LA25_P LA25_N GND LA29_P LA29_N GND LA31_P LA31_N GND LA33_P LA33_N GND VADJ GND

FMC pin D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40

VITA net name PG_C2M GND GND GBTCLK0_M2C_P GBTCLK0_M2C_N GND GND LA01_P_CC LA01_N_CC GND LA05_P LA05_N GND LA09_P LA09_N GND LA13_P LA13_N GND LA17_P_CC LA17_N_CC GND LA23_P LA23_N GND LA26_P LA26_N GND TCK TDI TDO 3P3VAUX TMS TRST_L GA1 3P3V GND 3P3V GND 3P3V

FMC pin C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40

VITA net name GND DP0_C2M_P DP0_C2M_N GND GND DP0_M2C_P DP0_M2C_N GND GND LA06_P LA06_N GND GND LA10_P LA10_N GND GND LA14_P LA14_N GND GND LA18_P_CC LA18_N_CC GND GND LA27_P LA27_N GND GND SCL SDA GND GND GA0 12P0V GND 12P0V GND 3P3V GND

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Hardware User Guide
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Appendix C: List of supporting design files

The FMC-BRK card has a number of supporting design files and documents that may be downloaded from the Zipcores website at: www.zipcores.com/downloads.html. Most of the design files are source-code files that are required for building and running the example demo as described in Appendix D. A list of these files and a brief description is given below:

Folders and important files
docs/
zip_fmc_brk_user_guide.pdf zip_fmc_brk_safety_info.pdf zip_fmc_brk_schematic.pdf zip_fmc_brk_assembly.pdf zip_fmc_brk_gerber.pdf zip_fmc_brk_bom.pdf

Description
Folder containing various design documents.
FMC-BRK hardware user guide (this document). FMC-BRK regulatory compliance and safety information. FMC-BRK design schematics. FMC-BRK assembly drawings. FMC-BRK gerber summary. FMC-BRK bill of materials.

const/ fmc_brk_top.xdc

Folder containing the physical constraints for the Xilinx Vivado project.
Example master 'XDC' file that defines all the top-level pinouts and design constrains for the FMC-BRK card when connected to the Xilinx® AC701 base-board. This file may be adapted for use with all Xilinx FPGAs.

vivado/ FMC_BRK_TOP.xpr

This folder contains the Vivado project environment for the demo. Vivado project setup file (double click to invoke project).

vhdl/ fmc_brk_top.vhd fmc_brk_top_bench.vhd
modelsim/
FMC_BRK_TOP.mpf
misc/

This folder contains the top-level VHDL source-code files for the example demo. The main top-level files are: The top-level synthesizable component. The top-level testbench for the VHDL simulation.
This folder contains the Modelsim® simulation environment in order to run a VHDL hardware simulation of the demo. You will need to obtain a copy of Mentor Graphics Modelsim in order to use these files. Modelsim project setup file (double click to invoke project).
This folder contains various data sheets, schematics and design notes for the components on the FMC-BRK card.

Zipcores offers a wide range of IP Cores and custom solutions for the FMC-BRK development board. As well as Xilinx FPGAs, we can provide IP for other FPGAs or SoCs on request. If you have a specific requirement or simply want to discuss a potential solution then please get in touch. Further details may be found by visiting our website or contacting us at: www.zipcores.com/help.php.

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Appendix D: Running the example demo
A simple demo is provided to get started with the FMC-BRK card. The demo generates a series of active-high pulses on the differential output pairs of the card. The pulses are at LVCMOS25 levels and are generated such that LAXX_P and LAXX_N signals are inverted versions of each other. The period of each pulse is also defined according to the pin-number such that: LA00_P/N has a 1.0us period, LA01_P/N has a 1.1us period, LA02_P/N has a 1.2us period etc. In this way, it's easy to locate each LA pin on the card by its waveform. In order to run the demo, the following basic lab setup is recommended:
· Oscilloscope for measuring the output pulse waveforms. (E.g. Tektronix MDO3014). · Hook-up wire (optional) to easily connect the scope probe to the header pins. · Xilinx Artix-7 FPGA AC701 Evaluation Kit (www.xilinx.com/products/boards-and-kits/ek-a7-ac701-g.html). This will be used as the
base board on which the FMC-BRK mezzanine card will be mounted. (Note: other base boards may be supported on request. Please contact us for more details). · Spacers (10 mm) and screws (size M2.5) in order to secure the FMC-BRK card to the base-board. · Xilinx Vivado Software (rev. 2018.3 or later) together with the Xilinx AC701 board definition files. · USB cable for programming the AC701 board.
Once the equipment is set up then the user should invoke the Vivado software and load the project environment ` FMC_BRK_TOP.xpr' which is in the `vivado' folder as described in Appendix C above. The same directory structure should be maintained so that the links and dependencies are correctly resolved. If the project loads correctly, the initial project layout should look something like Figure (7) below:

Figure 7: Initial Vivado project startup for demo

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Once the project is loaded then the next step is to build the bitstream for programming the FPGA. Click on `Generate Bitstream' in the project manager window and wait for the compile process to complete. After the bitstream is generated then open the hardware manager and program the AC701 board.
Figure (8) below shows an example bench setup with the LA32_P and LA32_N pins (H37/H38) being probed on the FMC header connector. Notice that the pulse period is exactly 4.2 us and the pulse trains are inverted versions of each other.

Figure 8: Bench setup showing FMC-BRK card connected to the Xilinx AC701 board

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Revision history

Revision A.0

Change description Initial revision

A.1

Fixed typo in description of pin C39 that was incorrectly labelled (Figure 3).

Now correctly labelled as 3P3V.

Added gerber file description in Appendix C.

Date 25/11/2021
01/03/2023

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