VCK190 Board User Guide ... reference design guide and the information herein should not be used as such. ... Fast-boot module daughter card ... Copyright 2021 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, Kintex, Spartan, ...
For additional information on the Versal. XCVC1902-2VSVA2197 ACAP, see the Versal Prime Series Data Sheet: DC and AC Switching. Characteristics ...
VCK190 Evaluation Board
User Guide
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Revision History
Revision History
The following table shows the revision history for this document.
Initial release.
Section
01/07/2021 Version 1.0 N/A
Revision Summary
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Table of Contents
Revision History...............................................................................................................2
Chapter 1: Introduction.............................................................................................. 5
Overview....................................................................................................................................... 5 Navigating Content by Design Process.................................................................................... 6 Additional Resources.................................................................................................................. 7 Block Diagram..............................................................................................................................8 Board Features............................................................................................................................ 9 Board Specifications................................................................................................................. 12
Chapter 2: Board Setup and Configuration....................................................13
Standard ESD Measures........................................................................................................... 13 Board Component Location.....................................................................................................13 Default Jumper and Switch Settings....................................................................................... 17 Versal ACAP Configuration.......................................................................................................21
Chapter 3: Board Component Descriptions................................................... 23
Overview.....................................................................................................................................23 Component Descriptions......................................................................................................... 23
Appendix A: VITA 57.4 FMCP Connector Pinouts......................................... 69
Overview.....................................................................................................................................69
Appendix B: Xilinx Design Constraints............................................................. 70
Overview.....................................................................................................................................70
Appendix C: Pmod FMC..............................................................................................71
Pin Mapping Pmod to FMC...................................................................................................... 72
Appendix D: Regulatory and Compliance Information...........................74
CE Information...........................................................................................................................74 Compliance Markings............................................................................................................... 75
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Appendix E: Additional Resources and Legal Notices..............................76
Xilinx Resources.........................................................................................................................76 Documentation Navigator and Design Hubs.........................................................................76 References..................................................................................................................................77 Please Read: Important Legal Notices................................................................................... 78
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Chapter 1: Introduction
Chapter 1
Introduction
Overview
The VCK190 evaluation board features the Xilinx® VersalTM ACAP XCVC1902 device. The VCK190 board enables the demonstration, evaluation, and development of the applications listed here, as well as other customer applications.
· Storage acceleration · Data center network acceleration · Passive optical network · Automotive · Aerospace and defense · Industrial, scientific, and medical · Test and measurement · Embedded vision · Machine learning · Audio video broadcast · Wired and wireless
The VCK190 evaluation board is equipped with many of the common board-level features needed for design development, including:
· SFP28 and QSFP28 optical transceiver support · LPDDR4 component and DDR4 UDIMM memory · HDMI · USB · PMOD connectors · CAN and Ethernet networking interfaces · Two FMC+ expansion ports
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Chapter 1: Introduction
· PCIe® (up to Gen4x8)
Models of VCK190 Boards
The following table lists the models for the VCK190 evaluation board. See the VCK190 Evaluation Board product page for details.
The following table lists the models for the VCK190 evaluation board. See the VCK190 Evaluation Board product page for details.
Table 1: Models of VCK190 Evaluation Boards
Kit
EK-VCK190-G-ED EK-VCK190-G-ED-J
Description
Xilinx Versal ACAP VCK190 evaluation kit, encryption disabled, no secure boot support
Xilinx Versal ACAP VCK190 evaluation kit, Japan specific
Versal ACAP Kit Numbering
The Versal ACAP kit numbering is illustrated in the following figure.
Figure 1: Kit Numbering
Product Number
EK - VC K 190 - G -
Kit Type
Options EK Evaluation Kit CK Characterization Kit
Family and series (e.g., Versal ACAP and Core)
Silicon indicator
ROHS Indicator
K = kit Ensures there is no confusion with silicon P/Ns
Examples
VCK190 VMK 180
Options
G ROHS Compliant
ED
-J
Regional Identifier
Options J Japan ED All other customers OEM OEM kit
X23340-121520
Navigating Content by Design Process
Xilinx® documentation is organized around a set of standard design processes to help you find relevant content for your current development task. This document covers the following design processes:
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Chapter 1: Introduction
· Board System Design: Designing a PCB through schematics and board layout. Also involves power, thermal, and signal integrity considerations. For more information, see Versal ACAP Design Process Documentation Board System Design.
Additional Resources
See Appendix E: Additional Resources and Legal Notices for references to documents, files, and resources relevant to the VCK190 evaluation board.
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Chapter 1: Introduction
Block Diagram
The VCK190 block diagram is shown in the following figure.
Figure 2: Block Diagram
SysC, GPIO 1.8V
HDMI, PCIe 3.3V
HDMI
2x zSFP
HSDP
PCIe
Lane 4 Lane 5 Lane 6 Lane 7
GEN4
x8
Lane 0 Lane 1
Lane 2
Lane 3
MIO
GTY0 GTY1 GTY2 GTY3
GTY
Bank 106
GTY0 GTY1 GTY2 GTY3
GTY
Bank 105
GTY0 GTY1 GTY2 GTY3
GTY
Bank 104
GTY0 GTY1 GTY2 GTY3
GTY
Bank 103
CPM
HDIO
HDIO
MRMAC
MRMAC
Versal VC1902 VSVA2197
PMC_MI0[0:25] Bank 500 PMC_MI0[26:51] Bank 501 LP_MI0[0:25] Bank 502
MRMAC MRMAC
GTY
GTY0 GTY1
4
GTY2
Bank 206 GTY3
GTY
GTY0 GTY1
4
GTY2
Bank 205 GTY3
GTY
GTY0 GTY1
4
GTY2
Bank 204 GTY3
GTY
GTY0 GTY1
4
GTY2
Bank 203 GTY3
GTY
GTY0 GTY1
4
GTY2
Bank 202 GTY3
GTY
GTY0 GTY1
4
GTY2
Bank 201 GTY3
GTY
Bank 200
GTY0 GTY1 GTY2 GTY3
XPIO
Triplet 1
700
701
702
XPIO
Triplet 2
703 704 705
XPIO
Triplet 3
706
707
708
XPIO
Triplet 4
709
710
711
4 zQSFP
DDR4 72-bit UDIMM
LPDDR4 2x (1x32)
LPDDR4 2x (1x32)
FMC+_01 FMC+_02
12
12
X23196-121620
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Chapter 1: Introduction
Board Features
The VCK190 evaluation board features are listed here. Detailed information for each feature is provided in Chapter 3: Board Component Descriptions.
· XCVC1902, VSVA2197 package · Form factor: extended height PCIe®, double-slot (heatsink clearance) · Onboard configuration from:
USB-to-JTAG bridge JTAG pod 2 mm 2x7 flat cable connector microSD card (PS MIO I/F) microSD card (System Controller I/F) · External boot module (EBM) configuration option X-EBM-01 dual quad SPI (QSPI) · Clocks ACAP Bank 406 HDMI_REC_CLK_OUT 148.50 MHz ACAP Bank 503 RTC Xtal 32.768 kHz ACAP Bank 503 Si570 REF_CLK 33.3333 MHz ACAP Bank 700 Si570 DDR4_CLK (DIMM) 200 MHz ACAP Bank 705 Si570 DDR4_CLK2 (LPDDR4) 200 MHz ACAP Bank 711 Si570 DDR4_CLK1 (LPDDR4) 200 MHz ACAP Bank GTY103/4 (REFCLK0) PCIe_CLK0/1 100 MHz ACAP Bank GTY105 (REFCLK0) Si570 zSFP_SI570_CLK 156.250 MHz ACAP Bank GTY105 (REFCLK1) Si570 HSDP_SI570_CLK 156.250 MHz ACAP Bank GTY200 (REFCLK0) 8A34001_CLK1_IN 100 MHz IEEE-1588 eCPRI 8A34001 clocks (various) · DDR4 8 GB 72-bit UDIMM XPIO triplet 1 (banks 700, 701, 702) · Two LPDDR4 interfaces (2x32-bit 4 GB components each) XPIO triplets 2 (banks 703, 704, 705) and 4 (banks 709, 710, 711)
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· PL FMCP HSCP (FMC+) connectivity XPIO triplet 3 (banks 706, 707, 708) FMCP1 HSCP full LA[00:33] bus FMCP2 HSCP full LA[00:33] bus
· PL GPIO connections PL UART1 to FTDI PL GPIO DIP switch (4-position) PL GPIO pushbuttons (two) PL GPIO LEDs (four) PL GPIO DC configuration header PL SYSCTLR_GPIO[0:5]
· 44 PL GTY transceivers (11 quads) PCIe 8-lane edge connector (8, banks GTY103, GTY104) HSDP USB3.1 TYPE C (1, bank GTY105) zSFP28 (2, bank GTY105) HDMI (3, bank GTY106) HDMI TX only, RX not used (1, bank GTY106) zQSFP28 (4, bank GTY200) FMCP1 HSCP DP (12, banks GTY201-GTY203) FMCP2 HSCP DP (12, banks GTY204-GTY206) Not used (1, bank GTY105)
· PCI Express endpoint connectivity Gen1 8-lane (x8) Gen2 8-lane (x8) Gen3 8-lane (x8) Gen4 8-lane (x8)
· PS PMC MIO connectivity PS MIO[0:12]: boot configuration header - DC QSPI support
Chapter 1: Introduction
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Chapter 1: Introduction
PS MIO[13:25]: USB2.0 PS MIO[26:36, 50:51]: SD1 I/F PS MIO[37]: ZU4_TRIGGER PS MIO[38:39]: PCIe_WAKE_B, PCIe_PERST_B PS MIO[40:41]: CAN1 PS MIO[42:43]: UART0 to FTDI PS MIO[44:47]: I2C1, I2C0 PS MIO[48:49], PS LPD MIO[0:25]: dual GEM0/1 RGMII Ethernet with stacked RJ-45 · Security: PSBATT button battery backup · SYSMON header · Operational switches (power on/off, PROG_B, boot mode DIP switch) · Operational status LEDs (INIT, DONE, PS STATUS, PGOOD) · Power management · System Controller (XCZU4EG) The VCK190 provides a rapid prototyping platform using the XCVC1902-2VSVA2197 device. See the Versal Architecture and Product Data Sheet: Overview (DS950) for a feature set overview, description, and ordering information.
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Chapter 1: Introduction
Board Specifications
Dimensions (Extended Height PCIe Form-Factor)
Height: 7.477 inches (18.992 cm) Length: 9.50 inches (24.13 cm) (¾ PCIe length) Thickness: 66.87 mil ±10% (1.698 mm ±10%) Note: Reserve two adjacent PCIe slots to accommodate fan-sink height. Note: A 3D model of this board is not available. See the VCK190 evaluation board website for the XDC listing and board schematics.
Environmental
Temperature Operating: 0°C to +45°C Storage: -25°C to +60°C Humidity 10% to 90% non-condensing
Operating Voltage
+12 VDC
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Chapter 2: Board Setup and Configuration
Chapter 2
Board Setup and Configuration
Standard ESD Measures
CAUTION! ESD can damage electronic components when they are improperly handled, and can result in total or intermittent failures. Always follow ESD-prevention procedures when removing and replacing components.
To prevent ESD damage:
· Attach a wrist strap to an unpainted metal surface of your hardware to prevent electrostatic discharge from damaging your hardware.
· When you are using a wrist strap, follow all electrical safety procedures. A wrist strap is for static control. It does not increase or decrease your risk of receiving electric shock when you are using or working on electrical equipment.
· If you do not have a wrist strap, before you remove the product from ESD packaging and installing or replacing hardware, touch an unpainted metal surface of the system for a minimum of five seconds.
· Do not remove the device from the antistatic bag until you are ready to install the device in the system.
· With the device still in its antistatic bag, touch it to the metal frame of the system.
· Grasp cards and boards by the edges. Avoid touching the components and gold connectors on the adapter.
· If you need to lay the device down while it is out of the antistatic bag, lay it on the antistatic bag. Before you pick it up again, touch the antistatic bag and the metal frame of the system at the same time.
· Handle the devices carefully to prevent permanent damage.
Board Component Location
The following figure shows the VCK190 board component locations. Each numbered component shown in the figure is keyed to the table in Board Component Descriptions.
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Chapter 2: Board Setup and Configuration
IMPORTANT! The following figure is for visual reference only and might not reflect the current revision of the board. IMPORTANT! There could be multiple revisions of this board. The specific details concerning the differences between revisions are not captured in this document. This document is not intended to be a reference design guide and the information herein should not be used as such. Always refer to the schematic, layout, and XDC files of the specific VCK190 version of interest for such details.
Figure 3: Evaluation Board Component Locations
00
Round callout references a component on the front side of the board
00
Square callout references a component on the back side of the board
19
18
53
20
21
18 19 51 9
10
55
54
49
7
48
3
50
52
43
4
12
14
8
47
46
13
11 15
28
44 11
45 38
40
1 37
36
33 42 23
34
39 2
41 26
27 27
22
17 16
16
17
32
30 31
35
25
29 5
6 24
X24958-121420
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Chapter 2: Board Setup and Configuration
Board Component Descriptions
The following table identifies the components and references the respective schematic (038-05005-01) page numbers.
CAUTION! Do NOT plug a PC ATX power supply 6-pin connector into the VCK190 board power connector J16. The ATX 6-pin connector has a different pinout than J16. Connecting an ATX 6-pin connector into J16 damages the VCK190 board and voids the board warranty.
Table 2: Board Component Locations
Callout
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Ref. Des.
U1
J45 U25,U26 U150,U151
J212 SW1 J36 U20,J207 U99,J308 U104,J302 U33,U35,U214 U233 J287 J288 P3 U198,J307B(UPR) U134,J307A(LWR) U43,P2A(UPR) U55,P2B(LWR)
Feature
VersalTM ACAP
Notes
XCVC1902-2VSVA2197 The heatsink is not shown in Figure 31
Schematic Page
DDR4 288-pin DIMM SOCKET/ DDR4 DIMM
FCI 10124677-000100ILF/Micron MTA9ADF1G72AZ-3G2E1
LPDDR4 16 GBIT comp. memory (B710/B711 IF)
Micron MT53D512M32D2DS-046
LPDDR4 16 GBIT comp. memory (B709/B710 IF)
Micron MT53D512M32D2DS-046
Fast-boot module daughter card Samtec SEAF-30-05.0-L-08-1-A-K-
connector
TR
ACAP MODE 4-pole DIP switch, active-High
C&K SDA04H1SBD
ACAP JTAG 2 mm 2x7 flat-cable connector
Molex 87832-1420
USB-UART bridge, USB Type-C connector (USB2.0)
FTDI FT4232HL-REEL, Amphenol 12401598E4#2A
USB ULPI transceiver, USB 2.0 type A connector
SMSC USB3320C-EZK, WURTH 629104190121
Versal ACAP SD 3.0 level-
Nexperia IP4856CX25/CZ, ALPS
translator circuit, SD card socket SCHA4B0419
I2C bus switches
TI TCA9548APWR
I2C bus expander
TI TCA6416APWR
zSFP/zSFP+ (1x2 stacked) connector
Tyco 2198318-6
zQSFPConnector
TE 1551920-2
PCIe EndPoint 8-lane edge connector
NA - PCB layout feature
GEM0 SGMII Ethernet PHY, 0x01, RJ45 w/mag
TI DP83867ISRGZ, TE-AMP 2301997-7 dual port
GEM1 SGMII Ethernet PHY, 0x02, RJ45 w/mag
TI DP83867ISRGZ, TE-AMP 2301997-7 dual port
HDMI XMT, TMDS to HDMI level TI SN65DP159RGZ, TE 1888811-1
shifter retimer, 0x22, 0xBC
dual port
HDMI RCV TMDS retimer, 0x0B, TI TMDS181IRGZT, TE 1888811-1
0xB8
dual port
43 27,28 29, 30
31 12 24 25, 99 24 76 44, 45 55 45 47 46 77 78 50 51
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Chapter 2: Board Setup and Configuration
Table 2: Board Component Locations (cont'd)
Callout
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
35
36 37 38 39 40 41 42
Ref. Des.
J51 J53 DS3-DS6,SW6 SW4,SW5 U216,J309 U110,J5 J11 Various J325 DS9-DS17,DS19-DS32 SW13 J16 JP1 U64 J233 U10,SW2 U110,J326 SW15 SW7 U2
U3
U4
U5
U32 U39 U62
Feature
Notes
Schematic Page
FMCP1
Samtec ASP-184329-01
32-36
FMCP2
Samtec ASP-184329-01
37-41
User LEDs and 4-pole DIP switch, active-High
Lumex SML-LX0603GW (green), C&K SDA04H1SBD
53
User pushbutton, active-High E-switch TL3301EP100QG
53
SPDIF IF driver and RCA jack
TI SN74AVC1T45, CUI RCJ-021
79
CAN BUS transceiver, 2x4 CAN header
Nexperia TJA1057GT/3J, SULLINS PBC04DAAN
80
SYSMON 2X6 vertical male pin header
SULLINS PBC06DAAN
12
Power management system (top, [bottom])
Infineon regulators
47-60
PMBus 3-pin header
SULLINS PBC03SAAN
26
Power good LEDs
Lumex SML-LX0603GW-TR, green
83
Power On/Off slide switch
C&K 1201M2S3AQE2
46
Power connector, 2x3, for AC-DC power adapter
MOLEX 39-30-1060 (mini-fit)
46
Power connector, 2x4, for ATX PCIe power
Astron 6652208-T0003T-H-A
46
Fan controller
Maxim MAX6643LBBAEE++
54
Fan header (keyed 4-pin)
Molex 22-11-2032
54
Power-on reset (POR) with pushbutton
TI TPS389001DSER, E-switch TL3301EP100QG
15
Alternate POR source driver and TI SN74LVC07A, SULLINS
2x4 select header
PBC04DAAN
15
GEM0 Ethernet PHY reset pushbutton, active-Low
E-switch TL3301EP100QG
77
GEM1 Ethernet PHY reset pushbutton, active-Low
E-switch TL3301EP100QG
78
DDR4 DIMM CLK, 200 MHz, 3.3V LVDS, 0x60
Silicon Labs SI570BAB000299DG
4
LPDDR4 CLK2, 200 MHz, 3.3V LVDS, 0x60
Silicon Labs SI570BAB000299DG
5
LPDDR4 CLK1, 200 MHz, 3.3V LVDS, 0x60
Silicon Labs SI570BAB000299DG
7
HSDP CLK, 156.25 MHz, 3.3V LVDS, 0x5D
Silicon Labs SI570BAB000544DG
8
ACAP U1 REF CLK, 33.33 MHz, 1.8V CMOS, 0x5D
Silicon Labs SI570JAC000900DG
43
PCIe 1:2 buffer, 100 MHz, 3.3V LVDS
IDT 85411AMLF
49
HDMI jitter atten., 148.50 MHz, 3.3V LVDS, 0x6C
IDT 8T49N241-994NLGI
52
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Chapter 2: Board Setup and Configuration
Table 2: Board Component Locations (cont'd)
Callout
Ref. Des.
Feature
Notes
Schematic Page
43
U142
SYSCTLR clocks 33.33 MHz & 125 Silicon Labs Si5332FD10259-
MHz I2C 0x6A
GM1
101
44
U192
zSFP CLK, 156.25 MHz, 3.3V LVDS, 0x5D
Silicon Labs SI570BAB000544DG
8
45
U205
IEEE-1588 eCPRI input CLK, 100 MHz, 3.3V LVDS, 0x5F
Silicon Labs SI570BAC002038DG
48
46
U219
IEEE-1588 eCPRI CLK, various, 3.3V, 0x58
IDT 8A34001E-000AJG8
104
47
J328-J331
IEEE-1588 eCPRI 8A34001 CLK in and out SMA pairs
Rosenberger 32K10K-400L5
104
48
U125
XCZU4EG System Controller
TI MSP430F5342
85-91
49
SW11
System Controller MODE 4-pole DIP switch, active-High
C&K SDA04H1SBD
89
50
J202
System Controller JTAG 2 mm 2 x 7 flat-cable connector
Molex 87832-1420
89
51
J206
System Controller SD card socket
ALPS SCHA4B0419
96
52
U132
System Controller LPDDR4 16 GBIT comp. memory
Micron MT53D512M32D2DS-046
97
53
U131,J204
System Controller SGMII Ethernet, RJ45 w/magnetics
Marvell 88E1512-A0-NNP2C000, Halo HFJ11-1G01E-L12RL
95
54
SW16
System Controller pushbutton switch, active-High
E-switch TL3301EP100QG
88
55
U129,SW12
System Controller POR with pushbutton
TI TPS389001DSER, E-switch TL3301EP100QG
88
Notes: 1. The VCK190 evaluation board includes a Cofan USA 30-6156-06 heatsink with a thermal resistance of 0.27°C/W.
Default Jumper and Switch Settings
The following figure shows the VCK190 board jumper header and switch locations. Each numbered component shown in the figure is keyed to the applicable table in this section. Both tables reference the respective schematic page numbers.
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Chapter 2: Board Setup and Configuration Figure 4: Board Jumper Header and Switch Locations
11 16
6
14
8 9
2 12
3
5 7
10 1
Jumpers
The following table lists the default jumper settings.
Table 3: Default Jumper Settings
Callout Number
Ref. Des.
Function
SYSMON VREFP
1
J12
1-2: 1.024V VREFP connected to ACAP
2-3: VREFP connected to GND
13 4 15
X23150-121420
Default
Schematic Page
1-2
12
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Chapter 2: Board Setup and Configuration
Table 3: Default Jumper Settings (cont'd)
Callout Number
Ref. Des.
Function
POR_B sense select
2
J26
1-2: VCCO_503
2-3: VCCAUX_PMC
SFP1_TX_DISABLE select
3
J32
ON: enable always
OFF: disable/allows ACAP U1 control
ACAP U1 bank VCC_FUSE select
4
J34
1-2: VCC1V8
2-3: GND
SFP0_TX_DISABLE select
5
J35
ON: enable always
OFF: disable/allows ACAP U1 control
JTAG MUX U14/U15 OE_B
6
J37
1-2: UTIL_3V3 disable
2-3: GND enable
PCIe lane size select
1-2: x1
7
J60
3-4: x4
5-6: x8
SYSCTLR_POR_B enable
8
J203
ON: enable
OFF: disable
System Controller M88E1512 EPHY U131 configuration
1:2: GND (5'b00000)
9
J205
3:4: SYSCTLR_ETH_LED0
5:6: SYSCTLR_ETH_LED0
7:8: SYS_VCC1V8 (5'b00001)
ACAP cooling fan control
10
J234
1-2: MAX6643 U64 control is enabled
2-3: always on
ULPI USB3320 U99 USB conn. J308 shield select
8
J300
1-2: J308 shield directly to GND
2-3: J308 shield capacitor C2762 to GND
IP4856 U104 VERSAL_SD1_REF voltage select
8
J301
1-2: UTIL_3V3
2-3: GND
Default
Schematic Page
1-2
15
ON
45
2-3
17
ON
17
2-3
24
5-6
46
ON
89
7-8
95
2-3
54
1-2
42
1-2
76
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Chapter 2: Board Setup and Configuration
Table 3: Default Jumper Settings (cont'd)
Callout Number
Ref. Des.
Function
Si53340 clock MUX U206 input select
11
J306
ON: CLK1 8a34001_Q2
OFF: U205 USER_SI570_1(100 MHz default)
POR_B source select (OR'd with POR_B)
None: U10 TPS389001 POR only
1-2: U125 SYSCTLR_POR_B
12
J326
3-4: J36 PC4_POR_B
5-6: J212(B) DC_PS_POR_B_OUT
7-8: U20 FTDI_POR_B
Switches
The following table lists the default switch settings.
Table 4: Default Switch Settings
Callout Number
Ref. Des.
Function
13
SW1
ACAP U1 mode 4-pole DIP switch
Switch OFF = 1 = High; ON = 0 = Low
Mode = SW1[4:1] = Mode[3:0]
JTAG = ON,ON,ON,ON = 0000 QSPI32 = ON,ON,OFF,ON = 0010
SD = OFF,OFF,OFF,ON = 1110 Reserved for Xilinx® = OFF,OFF,OFF,OFF = 1111 JTAG MUX select 2-pole DIP switch
Switch OFF = 1 = High; ON = 0 = Low
14
SW3
SW3[1:2] = MUX[S0:S1]
SYSCTLR U125 BANK 44 = ON,ON = 00
FTDI BRIDGE U20 = ON,OFF = 01
ACAP U1 BANK 306 GPIO 4-Pole DIP switch
15
SW6
SW6[4:1] = GPIO_DIP_SW[0:3]
Switch OFF = 0 = Low; ON = 1 = High
ZU4 SYSCTLR U125 Mode 4-Pole DIP switch Switch OFF = 1 = High; ON = 0 = Low
Mode = SW11[4:1] = Mode[3:0]
16
SW11
JTAG = ON,ON,ON,ON = 0000
QSPI32 = ON,ON,OFF,ON = 0010
SD = OFF,OFF,OFF,ON = 1110
Default
Schematic Page
OFF
48
1-2
3-4
15
7-8
Default
0000
Schematic Page
14
01
24
0000
53
0000
89
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Chapter 2: Board Setup and Configuration
Versal ACAP Configuration
The Versal XCVC1902 ACAP boot process is described in the "Platform Boot, Control, and Status" section of the Versal ACAP Technical Reference Manual (AM011). The VCK190 board supports a subset of the modes documented in the technical reference manual via onboard and daughter card boot options. The mode DIP switch SW1 configuration option settings are listed in the following table.
Table 5: Mode Switch SW1 Configuration Option Settings
Boot Mode
Mode Pins [3:0]2
Mode SW1 [4:1]2
Comments
JTAG
00001, 3
ON, ON, ON, ON
Supported with or without boot module attached
QSPI32
0010
ON, ON, OFF, ON
Supported only with boot module X-EBM-01 attached Supports x1, x2, x4, and dual-parallel x8
SD1_3.0
1110
OFF, OFF, OFF, ON Supported with or without boot module attached
Notes: 1. Default switch setting. 2. Mode DIP SW1 poles [4:1] correspond to U1 XCVC1902 MODE[3:0]. 3. Mode DIP SW1 individual switches ON=LOW (p/d to GND)=0, OFF=HIGH (p/u to VCCO)=1.
JTAG
The Vivado®, XilinxSDK, or third-party tools can establish a JTAG connection to the Versal ACAP in the two ways described here:
· FTDI FT4232 USB-to-JTAG/USB-UART device (U20) connected to USB 3.1 type-C connector (J207), which requires: Set boot mode SW1 for JTAG as indicated in the "Mode Switch SW1 Configuration Option Settings" table in Versal ACAP Configuration Set 2-pole DIP SW3[1:2] set to 01 (ON, OFF) for JTAG MUX channel 2 FT4232 U20 bridge
On the 3-pin JTAG MUX, enable header J37 (2-pin jumper block installed on pins 2-3) to enable the JTAG MUX
Power-cycle the VCK190 board or press the power-on reset (POR) pushbutton (SW2) (SW2 is callout 46 in the "Evaluation Board Component Locations" figure in Board Component Location)
· JTAG pod flat cable connector J36 (2 mm 2x7 shrouded/keyed), which requires: Set boot mode SW1 for JTAG as indicated in the "Mode Switch SW1 Configuration Option Settings" table in Versal ACAP Configuration On the 3-pin JTAG MUX, enable header J37 (2-pin jumper block installed on pins 1-2) to inhibit the JTAG MUX (hi-Z mode)
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Chapter 2: Board Setup and Configuration
2-pole DIP SW3[1:2] setting is XX as the MUX is inhibited/turned off In this mode, the FT4232 device (U20) UART functionality continues to be available Power-cycle the VCK190 board or press the power-on reset pushbutton (SW2) (SW2 is
callout 46 in the "Evaluation Board Component Locations" figure in Board Component Location)
QSPI32
This boot mode is supported only with boot module X-EBM-01 attached to the MIO connector (J212). J212 is a 240-pin (8 x 30) MIO connector wired to XCVC1902 U1 bank 500 PMC_MIO[0:12] pins. The supported QSPI configurations are x1, x2, x4, and dual-parallel x8. To boot from a QSPI X-EBM-01 boot module:
1. Store a valid XCVC1902 ACAP boot image file on the X-EBM-01 resident QSPI. 2. Set boot mode SW1 for QSPI32 as indicated in the "Mode Switch SW1 Configuration Option
Settings" table in Versal ACAP Configuration. 3. Power-cycle the VCK190 or press the POR pushbutton SW2. SW2 is callout 35 in the
"Evaluation Board Component Locations" figure in Board Component Location.
SD1_3.0
To boot from a SD card installed in microSD card socket J302:
1. Store a valid XCVC1902 ACAP boot image file on a microSD card. Plug the SD card into the VCK190 board SD socket J302 connected to the XCVC1902 U1 bank 501 MIO SD interface.
2. Set boot MODE SW1 for SD1_3.0 as indicated in the "Mode Switch SW1 Configuration Option Settings" table in Versal ACAP Configuration.
3. Power-cycle the VCK190 or press the POR pushbutton SW2. SW2 is callout 35 in the "Evaluation Board Component Locations" figure in Board Component Location.
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Chapter 3: Board Component Descriptions
Chapter 3
Board Component Descriptions
Overview
This chapter provides a detailed functional description of the board's components and features. The "Board Component Locations" table in Board Component Descriptions identifies the components and references the respective schematic page numbers. Component locations are shown in the "Evaluation Board Component Locations" figure in Board Component Location.
Component Descriptions
Versal ACAP
[Figure 3, callout 1] The VCK190 board is populated with the VersalTM XCVC1902-2VSVA2197 ACAP, which combines a powerful processing system (PS) and programmable logic (PL) in the same device. The PS in a Versal ACAP features the Arm® flagship CortexTM-A72 64-bit dual-core processor and CortexTM-R5F dual-core real-time processor. For additional information on the Versal XCVC1902-2VSVA2197 ACAP, see the Versal Prime Series Data Sheet: DC and AC Switching Characteristics (DS956). See the Versal ACAP Technical Reference Manual (AM011) for more information about Versal ACAP configuration options.
Encryption Key Battery Backup Circuit
The XCVC1902 ACAP U1 implements bitstream encryption key technology. The VCK190 board provides the encryption key backup battery circuit shown in the following figure.
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Chapter 3: Board Component Descriptions Figure 5: Encryption Key Backup Circuit
X23376-112420
The Seiko TS621E rechargeable 1.5V lithium button-type battery B1 is soldered to the board with the positive output connected to the XCVC1902 ACAP U1 VCC_BATT bank pin AG33. The battery supply current IBATT specification is 150 nA maximum when board power is off. Battery B1 is charged from the VCC1V8 1.8V rail through a 2 series diode with the first forward drop to yield between 0.24V to 0.46V over temperature per fixed 5 mA load, R1725, and limiting 1.56V max at the ACAP pin, PSVBATT. The second diode and 4.7 k current limit resistor allows the battery to trickle charge and prevent battery B1 from back powering R1725.
I/O Voltage Rails
The XCVC1902 ACAP PL I/O bank voltages on the VCK190 board are listed in the following table.
Note: The VCK190 board is shipped with VADJ_FMC set to 1.5V by the ZU4 system controller.
Table 6: I/O Voltage Rails
ACAP (U1) Bank
HDIO Bank 306
HDIO Bank 406
XPIO Bank 700
XPIO Bank 701 XPIO Bank 702
Power Supply Rail Net Name
VCC1V8
Voltage
1.8V
VCC3V3
3.3V
VCC1V2_DDR4
1.2V
VCC1V2_DDR4
1.2V
VCC1V2_DDR4
1.2V
Description
GPIO: PB[0:1], DIP_SW[0:3], LED[0:3]; DC_PL_GPIO[0:3]; SYSCTLR_GPIO[0:5]; UART1_TXD/RXD
HDMI status/ctrl(15)IF; HDIO_UART3_TX/RX; HDIO_UART4_TX/RX
DDR4_DIMM1_DQ[32:63], CB[0:7], ADDR/CTRL; DDR4_DIMM1_CLK; Si570 U2 200 MHz
DDR4_DIMM1_DQ[24:31], ADDR/CTRL
DDR4_DIMM1_DQ[0:23], CB[0:7]
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Chapter 3: Board Component Descriptions
Table 6: I/O Voltage Rails (cont'd)
ACAP (U1) Bank
XPIO Bank 703 XPIO Bank 704 XPIO Bank 705 XPIO Bank 706 XPIO Bank 707 XPIO Bank 708 XPIO Bank 709 XPIO Bank 710 XPIO Bank 711 PMC MIO 500
PMC MIO 501 LP MIO 502
Power Supply Rail Net Name
VCC1V1_LP4 VCC1V1_LP4 VCC1V1_LP4 VADJ_FMC VADJ_FMC VADJ_FMC VCC1V1_LP4 VCC1V1_LP4 VCC1V1_LP4 VCCO_500
Voltage
1.1V 1.1V 1.1V 1.5V 1.5V 1.5V 1.1V 1.1V 1.1V 3.3V
VCCO_501
3.3V
VCCO_502
3.3V
Description
LPDDR4_3_DQ[0:7, 16:23], ADDR/CTRL LPDDR4_2_DQ[0:7, 16:23]; LPDDR4_3_DQ[8:15, 24:31] LPDDR4_2_DQ[8:15, 24:31], ADDR/CTRL; Si570 U3 200 MHz 8A34001_GPIO_[0:15]; FMCP1_LA[00:16] FMCP1_LA[17:33]; FMCP2_LA[26:33] FMCP2_LA[00:25] LPDDR4_1_DQ[0:7, 16:23], ADDR/CTRL LPDDR4_0_DQ[0:7, 16:23]; LPDDR4_1_DQ[8:15, 24:31] LPDDR4_0_DQ[8:15, 24:31], ADDR/CTRL; Si570 U4 200 MHz SYSMON IF; PMC_MIO[0:25]_500; ISL60002 U6 1.042V VREF; J1 2x6 SYSMON PIN HDR PMC_MIO[26:51] LPD_MIO[0:25]
DDR4 UDIMM Socket
[Figure 3, callout 1] The VCK190 board XPIO triplet 1 (banks 700/701/702) memory interface supports 288-pin 72bit DDR4 DIMM socket J45.
Figure 6: DDR4 DIMM Memory
XPIO
Triplet 1
700 701 702
DDR4 72-bit UDIMM
X23197-120120
The VCK190 board is shipped with a DDR4 UDIMM installed: · Manufacturer: Micron
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Chapter 3: Board Component Descriptions
· Part number: MTA9ADF1G72AZ-3G2E1
· Description
8 GB 288-pin DDR UDIMM
Single rank
8 Gb (1 Gig x 8), 16 banks
Supports up to 3200 Mb/s
The VCK190 XCVC1902 ACAP DDR interface performance is documented in the Versal Prime Series Data Sheet: DC and AC Switching Characteristics (DS956). The VCK190 DDR4 DIMM interface adheres to the constraints guidelines documented in the PCB guidelines for DDR4 section of the Versal ACAP PCB Design User Guide (UG863). The DDR4 DIMM interface is a 40 impedance implementation. Other memory interface details are also available in the Versal ACAP Memory Resources Architecture Manual (AM007). For more details, see the Micron MTA9ADF1G72AZ-3GE1 data sheet at the Micron website. The ACAP connections for the feature described in this section are documented in the VCK190 board XDC file, referenced in Appendix B: Xilinx Design Constraints.
LPDDR4 Component Memory
[Figure 3, callout 3 and 4] The VCK190 board hosts two LPDDR4 memory systems, each with a component configuration of 2x (1x32-bit component).
Figure 7: LPDDR4 Component Memory
XPIO
Triplet 2
703 704 705
XPIO
Triplet 3
706 707 708
XPIO
Triplet 4
709 710 711
LPDDR4 2x (1x32)
LPDDR4 2x (1x32)
X23198-090919
XCVC1902 U1 XPIO triplet 2 (banks 703/704/704) and triplet 4 (banks 709/710/711) each support two independent 32-bit 2 GB component interfaces (4 GB per triplet).
· Manufacturer: Micron
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Chapter 3: Board Component Descriptions
· Part number: MT53D512M32D2DS-046 WT:D (dual die LPDDR4 SRAM) · Component description
16 Gb (512 Mb x 32)
1.1V 200-ball WFBGA
DDR4-2133
The VCK190 XCVC1902 ACAP PL DDR interface performance is documented in the Versal Prime Series Data Sheet: DC and AC Switching Characteristics (DS956). The VCK190 board LPDDR4 component memory interfaces adhere to the constraints guidelines documented in the PCB guidelines for DDR4 section of Versal ACAP PCB Design User Guide (UG863). The VCK190 DDR4 component interface is a 40 impedance implementation. Other memory interface details are also available in the Versal ACAP Memory Resources Architecture Manual (AM007). For more memory component details, see the Micron MT53D512M32D2DS data sheet at the Micron website. The detailed ACAP connections for the feature described in this section are documented in the VCK190 board XDC file, referenced in Appendix B: Xilinx Design Constraints.
System Reset POR_B
[Figure 3, callout 35]
POR_B is the Versal ACAP processor reset, which can be controlled by:
· SYSCTLR (U125) · PC4 header (J36) · MIO EBM (external boot module on J212) · FTDI USB JTAG chip (U20)
In the following figure, U235 allows directional open drain level shifting for all of these masters, and J326 allows them to be bused together if desired. The fifth channel buffers POR_B out to the EBM (external boot module) as DC_PS_POR_B. The TPS389001 U10 supervisor chip holds POR_B off until power is valid. The VCK190 board POR circuit is shown in the figure.
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Chapter 3: Board Component Descriptions Figure 8: POR_B Reset Circuit
X24949-121420
PMC and LPD MIO
The following table provides MIO peripheral mapping implemented on the VCK190 board. See the Versal ACAP Technical Reference Manual (AM011) for more information on MIO peripheral mapping. The XCVC1902 ACAP Bank 500, 501, and 502 mappings are listed in the table.
Table 7: MIO Peripheral Mapping
PMC MIO[0:25] Bank 500
0
MIO CONN. J212
1
MIO CONN. J212
2
MIO CONN. J212
3
MIO CONN. J212
4
MIO CONN. J212
5
MIO CONN. J212
6
MIO CONN. J212
7
MIO CONN. J212
8
MIO CONN. J212
9
MIO CONN. J212
10
MIO CONN. J212
11
MIO CONN. J212
12
MIO CONN. J212
13 U103.6 USB3320 U99 reset gate
14
USB3320 U99
15
USB3320 U99
16
USB3320 U99
17
USB3320 U99
18
USB3320 U99
PMC MIO[26:51] Bank 501
26
SD1
27
SD1
28
SD1
29
SD1
30
SD1
31
SD1
32
SD1
33
SD1
34
SD1
35
SD1
36
SD1
37
ZU4_TRIGGER
38
PCIE_PERST_B
39
PCIE_PWRBRK_B
40
CAN1_TXD
41
CAN1_RXD
42
UART0
43
UART0
44
I2C1
LPD MIO[0:25] Bank 502
0
GEM0
1
GEM0
2
GEM0
3
GEM0
4
GEM0
5
GEM0
6
GEM0
7
GEM0
8
GEM0
9
GEM0
10
GEM0
11
GEM0
12
GEM1
13
GEM1
14
GEM1
15
GEM1
16
GEM1
17
GEM1
18
GEM1
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Chapter 3: Board Component Descriptions
Table 7: MIO Peripheral Mapping (cont'd)
PMC MIO[0:25] Bank 500
19
USB3320 U99
20
USB3320 U99
21
USB3320 U99
22
USB3320 U99
23
USB3320 U99
24
USB3320 U99
25
USB3320 U99
PMC MIO[26:51] Bank 501
45
I2C1
46
I2C0
47
I2C0
48
GEM0
49
GEM1
50
PCIE_WAKE_B
51
SD1
LPD MIO[0:25] Bank 502
19
GEM1
20
GEM1
21
GEM1
22
GEM1
23
GEM1
24
GEM0, GEM1
25
GEM0, GEM1
PMC MIO[012] Bank 500: MIO Daughter Card (DC) Connector J212
[Figure 3, callout 5]
The VCK190 U1 XCVC1902 bank 500 PMC_MIO[0:12] pins are connected to the 240-pin (8 x 30) MIO connector J212. This interface enables high-speed XCVC1902 configuration using the X-EBM-01 QSPI external daughter card installed on J212.
The detailed ACAP connections for the feature described in this section are documented in the VCK190 board XDC file, referenced in Appendix B: Xilinx Design Constraints. The XCVC1902 MIO connector J212 pinout is listed in the following figure.
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Chapter 3: Board Component Descriptions Figure 9: MIO Connector J212 Pinout
X23377-101619
PMC MIO[13:25] Bank 500: USB 2.0 ULPI PHY
The VCK190 board uses a Standard Microsystems Corporation USB3320 USB 2.0 ULPI transceiver (U99) to support a USB 2.0 type-A connector (J308). A USB cable is supplied in the VCK190 evaluation kit (standard-A connector to host computer, USB 2.0 A connector to VCK190 board connector J308). The USB3320 is a high-speed USB 2.0 PHY supporting the UTMI+ low pin interface (ULPI) interface standard. The ULPI standard defines the interface between the USB controller IP and the PHY device, which drives the physical USB bus. Using the ULPI standard reduces the interface pin count between the USB controller IP and the PHY device.
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Chapter 3: Board Component Descriptions
The USB3320 is clocked by a 24 MHz crystal (X8). See the Standard Microsystems Corporation (SMSC) USB3320 data sheet for clocking mode details. The interface to the USB3320 PHY is implemented through the IP in the XCVC1902 ACAP PS.
The USB3320 ULPI transceiver circuit has a Micrel MIC2544 high-side programmable current limit switch (U100). This switch has an open-drain output fault flag on pin 2, which turns on red LED DS37 if over current or thermal shutdown conditions are detected. DS37 is located just above the U125 system controller component (callout 48 in the figure in Board Component Location). Note: As shown in the following figure, the shield for the USB 2.0 type-A connector (J308) can be tied to GND by a jumper on header J300 pins 1-2 (default). The USB shield can optionally be connected through a series capacitor to GND by installing a capacitor (body size 0402) at location C2762 and jumping pins 2-3 on header J300.
Figure 10: USB3320 USB2.0 Connector J308 Shield Connection Options
X24950-121420
The detailed ACAP connections for the feature described in this section are documented in the VCK190 board XDC file, referenced in Appendix B: Xilinx Design Constraints.
PMC MIO[26:36, 51] Bank 501: Secure Digital (SD) Card IF (J302)
[Figure 3, callout 10]
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Chapter 3: Board Component Descriptions
A secure digital (SD) card connector is provided for booting and file system storage. This interface is used for the SD boot mode and supports SD2.0 and SD3.0 access.
The SDIO interface signals PMC_MIO[26:36, 51] are connected to XCVC1902 ACAP bank 501, which has its VCCO set to 3.3V. Six SD interface nets PMC_MIO[26, 29, 30:33] are passed through a Nexperia IP4856CX25 SD 3.0-compliant voltage level-translator U104 (mounted on an Aries adapter), present between the XCVC1902 ACAP and the SD card connector (J302). The Nexperia IP4856CX25 U104 device provides SD3.0 capability with SDR104 performance. The Aries adapter schematic pinout to IP4856CX25 device pinout cross-reference table is shown in the following table and also on the VCK190 schematic page for this circuit.
The Nexperia SD3.0 level shifter is mounted on an Aries adapter board (located on the bottom of the board under SD socket J302) that has the pin mapping shown in the table.
Table 8: IP4856CX25 U104 Adapter Pinout
Aries Adapter Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
IP4856CX25 Pin Number
C1 C3 D3 D2 E2 E4 B4 C4 A3 A4 B3 A2 D1 B2 B1 E1 E3 A1 E5 D5 C5 D4 B5 A5 C2
IP4856CX25 Pin Name
CLK_IN GND CD
CMD_H CLK_FB
WP VLDO VSD_REF DIR_0 VSUPPLY VCCA DIR_CMD DATA0_H
SEL DATA3_H DATA1_H DIR_1_3 DATA2_H DATA1_SD DATA0_SD CLK_SD CMD_SD DATA3_SD DATA2_SD ENABLE
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Chapter 3: Board Component Descriptions Figure 11: SD Socket J302 Power Control
X24951-121420
Information for the SD I/O card specification can be found at the SanDisk Corporation or SD Association websites. The VCK190 SD card interface supports the SD1 (2.0) and SD2 (3.0) configuration boot modes documented in the Versal ACAP Technical Reference Manual (AM011). For Nexperia IP4856CX25 component details, see the IP4856CX25 data sheet at the Nexperia website. The detailed ACAP connections for the feature described in this section are documented in the VCK190 board XDC file, referenced in Appendix B: Xilinx Design Constraints.
PS MIO[37] ZU4 System Controller GPIO
The ACAP PS bank 501 MIO37 is connected to the ZU4 system controller U125 bank 500 MIO11 pin AE17.
PMC MIO[38:39] PCIe Status
The ACAP PS bank 501 MIO38 (PCIE_PERST_B) and MIO50 (PCIE_WAKE_B) are connected to the PCIe 8-lane edge connector P3 PERST# (pin A11) and WAKE# (pin B11), respectively.
PMC MIO[40:41] CAN1
[Figure 3, callout 25]
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Chapter 3: Board Component Descriptions
The ACAP PS bank 501 MIO40 (TX OUT) and MIO41 (RX IN) support the PS-side CAN bus TX and RX interface wired through the TI SN74AVC2T244 level-translators U107 and U109, respectively, to the NXP TJA1057GT/3J CAN-bus transceiver U110. This transceiver is connected to the 2x4 0.1-inch pitch 8-pin male header J5.
See the NXP TJA1057GT/3J data sheet at the Nexperia website for CAN-bus transceiver details.
The detailed ACAP connections for the feature described in this section are documented in the VCK190 board XDC file, referenced in Appendix B: Xilinx Design Constraints.
PMC MIO[42:43] UART0
[Figure 3, callout 8]
This is the primary Versal ACAP PS-side UART interface. The VCK190 USB Type-C connector J207 only supports USB2.0.
MIO42 (RX_IN) and MIO43 (TX_OUT) are connected to FTDI FT4232HL U20 USB-to-QuadUART bridge port BD through TI SN74AVC4T245 level-shifters U18 and U21. The FT4232HL U20 port assignments are listed in the following table.
Table 9: FT4232HL Port Assignments
Port AD JTAG Port BD UART0 Port CD UART1 Port DD UART2
FT4232HL U34
Versal ACAP U1
VCK190 JTAG chain PS_UART0 (MIO 18-19) PL_UART1 bank 306 U20 system controller UART
The FT4232HL UART interface connections are shown in the following figure.
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Chapter 3: Board Component Descriptions
Figure 12: FT4232HL UART Connections
USB Type-C
PC4 HDR
FMC+
FMC+
xx
xx
xx
xx
xx
xx
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
xx
xx
xx
xx
USB2.0
FTDI
PortA PortB PortC PortD
Versal JTAG Versal PS UART Versal PS UART
SysCon UART
XCVC1902
ACAP
TDO
TDI
PS UART
GTY
PL UART HSDP
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
HSDP Using USB3.0 Pins
ZU4 MPSoC
JTAG PC4 HDR
PS UART
Note: 1. No USB3.0 support.
X23199-090919
For more information on the FT4232HL, see the Future Technology Devices International Ltd website.
The detailed ACAP connections for the feature described in this section are documented in the VCK190 board XDC file, referenced in Appendix B: Xilinx Design Constraints.
PMC MIO[46:47] I2C0, PMC MIO[44:45] I2C1 I2C Bus Overview
The following figure shows an overview of the I2C0 and I2C1 bus connections.
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Chapter 3: Board Component Descriptions
I2C0 U212 L/S U210 L/S
I2C0
Figure 13: I2C0 and I2C1 Bus Connectivity Overview
I2C1
System Controller
PS Bank 501 U125 XCZU4EG
U213 L/S
Versal ACAP
PS Bank 501 U1
U211 L/S
0x20
P00 MAX6643_OT_B P01 MAX6643_FANFAIL_B P04 PMBUS2_INA226_ALERT P07 MAX6643_FULLSPD
P10
GPIO
P11
Expander P12
P13
P14
P15
P16
P17
U233 TCA6416A
FMCP1_FMC_PRSNT_M2C_B FMCP2_FMC_PRSNT_M2C_B FMCP1_FMCP_PRSNT_M2C_B FMCP2_FMCP_PRSNT_M2C_B VCCINT_VRHOT_B 8A34001_EXP_RST_B PMBUS_ALERT PMBUS1_INA226_ALERT
0x74
0
1
2
I2C
3
MUX
4
#1
5
6
7 U35 TCA9548A
DC_I2C FMCP1_IIC FMCP2_IIC DDR4_DIMM1 LPDDR4_SI570_CLK2 LPDDR4_SI570_CLK1 HSDP_SI570 8A34001
0x75
0
1
I2C
2
MUX
3
#2
4
5
6
7 U214 TCA9548A
SFP0_IIC SFP1_IIC QSFP1_I2C NC NC NC NC NC
0x74
0
1
2
I2C
3
MUX 4
5
6
7 U33 TCA9548A
PMBUS PMBUS1_INA226 PCIE_CLK PMBUS2_INA226 NC zSFP_SI570 USER_SI570_1_CLOCK NC
I2C1
X23200-100719
PMC MIO[46:47] I2C0 Bus
[Figure 3, callout 11]
Bus I2C0 connects the XCVC1902 U1 PS bank 501 and the XCZU4EG system controller U125 PS bank 501 to a GPIO 16-bit port expander (TCA6416A U233) and I2C switch (TCA9548A U33). The port expander enables accepting various fan controller, FMCP connector, and power system status inputs. Bus I2C0 also provides access to power system PMBus power controllers and INA226 power monitors, as well as three SI570 components via the U33 TCA9548A switch. TCA6416A U233 is pin-strapped to respond to I2C address 0x20. The TCA9548A U33 switch is set to 0x74.
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The following figure shows the I2C0 bus connectivity.
Figure 14: I2C0 Bus Topology
I2C0
System Controller PS Bank 501
U125 XCZU4EG
Versal ACAP PS Bank 501
U1
U212 L/S
U210 L/S
0x20
P00 MAX6643_OT_B P01 MAX6643_FANFAIL_B P04 PMBUS2_INA226_ALERT P07 MAX6643_FULLSPD
P10
GPIO
P11
Expander P12
P13
P14
P15
P16
P17
U233 TCA6416A
FMCP1_FMC_PRSNT_M2C_B FMCP2_FMC_PRSNT_M2C_B FMCP1_FMCP_PRSNT_M2C_B FMCP2_FMCP_PRSNT_M2C_B VCCINT_VRHOT_B 8A34001_EXP_RST_B PMBUS_ALERT PMBUS1_INA226_ALERT
I2C0
0x74
0
1
2
I2C
3
MUX 4
5
6
7 U33 TCA9548A
PMBUS1 PMBUS1_INA226 PCIE_CLK PMBUS2_INA226 NC zSFP_SI570 USER_SI570_1_CLOCK NC
X23201-100719
The devices on each port of the I2C0 U233 TCA6416A port expander and on each bus of the I2C0 U33 PCA9548A switch are listed in the following two tables. The I2C0 target device I2C addresses are listed in the third table below.
Table 10: I2C0 Port Expander TCA6416A U233 Address 0x20 Connections
TCA6416A U233
Pin
Pin
Name No.
Schematic Net Name
SDA
23 I2C0_SDA
SCL
22 I2C0_SCL
P00
4 MAX6643_OT_B (1)
P01
5 MAX6643_FANFAIL_B (1)
P04
8 PMBUS2_INA226_ALERT (1)
P07
11 MAX6643_FULLSPD (1)
P10
13 FMCP1_FMC_PRSNT_M2C_B
P11
12 FMCP2_FMC_PRSNT_M2C_B
Connected To
Pin No.
Pin Name
Reference Designator
Device
See the "I2C0 Bus Topology" figure. TCA6416AU233 Addr. 0x20
9
OT_B
4
FANFAIL_B
3
ALERT
6
FULLSPD
H2
PRSNT_M2C_L
H2
PRSNT_M2C_L
U64 U64 14x INA226 U64
J51(H) J53(H)
MAX6643 MAX6643 INA226 MAX6643
ASP_184329_01 ASP_184329_01
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Table 10: I2C0 Port Expander TCA6416A U233 Address 0x20 Connections (cont'd)
TCA6416A U233
Pin
Pin
Name No.
Schematic Net Name
P12
15 FMCP1_FMCP_PRSNT_M2C_B
P13
16 FMCP2_FMCP_PRSNT_M2C_B
P14
17 VCCINT_VRHOT_B
P15
18 8A34001_EXP_RST_B
P16
19 IRPS5401_ALERT_B
P17
20 PMBUS1_INA226_ALERT (1)
Connected To
Pin No.
Pin Name
Reference Designator
Z1 HSPC_PRSNT_M2C_L
J51(N)
Z1 HSPC_PRSNT_M2C_L
J53(N)
14
VRHOT_ICRIT#
U152
1
A
U221
-
Not connected
In schematic
3
ALERT
5x INA226
Device
ASP_184329_01 ASP_184329_01
IR35215 SN74LVC1G08
Delete INA226
Table 11: I2C0 Multiplexer TCA9548A U33 Address 0x74 Connections
TCA9548A U33 Pin Name Pin No.
Schematic Net Name
SDA
19
I2C0_SDA
SCL
18
I2C0_SCL
SD0/SC0
4/5
PMBUS_SDA/SCL
SD1/SC1
6/7
PMBUS1_INA226_SDA/SCL
SD2/SC2
8/9
PMBUS2_SDA/SCL
SD3/SC3 SD4/SC4 SD5/SC5 SD6/SC6 SD7/SC7
10/11 13/14 15/16 17/18 19/20
PMBUS2_INA226_SDA/SCL LP_I2C_SM_SDA/SCL zSFP_SI570_SDA/SCL USER_SI570_1_CLOCK_SDA/SCL USER_SI570_2_CLOCK_SDA/SCL
Connected To
Pin No.
Pin Name
Reference Designator
Device
See the "I2C0 Bus Topology" figure; PCA9548A U33 Addr. 0x74
9,10
NA
J98
PMBUS HDR
Miscellaneous power components; see Board Power System for details
4,5
SDA, SCL
5x INA226
INA226
9,10
NA
J104
PMBUS HDR
Miscellaneous power components; see Board Power System for details
4,5
SDA, SCL
14x INA226
INA226
NA
Not connected NA
NA
7,8
SDA, SCL
U192
SI570
7,8
SDA, SCL
U205
SI570
NA
Not connected NA
NA
Table 12: I2C0 Port Expander TCA6416A U233 Address 0x20 Connections
I2C Devices
TCA6416A 16-bit port expander Function MAX6643_OT_B MAX6643_FANFAIL_B N/A
I2C Switch Position
N/A Port P00 P01 P02-P03 NC
I2C Address
I2C0 Bus 0b1110101 Direction IN IN N/A
0x20
N/A N/A N/A
PMBUS2_INA226_ALERT
P04
IN
N/A
N/A
P05-P06 NC N/A
N/A
MAX6643_FULLSPD
P07
OUT
N/A
FMCP1_FMC_PRSNT_M2C_B
P10
IN
N/A
Device
U233 TCA6416A
U64 MAX6643 U64 MAX6643 N/A U166, U168, U172, U173, U174, U176, U177, U178, U180, U182, U184 ,U186, U188, U234 INA226, U125 ZU4EG N/A U64 MAX6643
J51 FMCP HSPC
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Table 12: I2C0 Port Expander TCA6416A U233 Address 0x20 Connections (cont'd)
I2C Devices
FMCP2_FMC_PRSNT_M2C_B FMCP1_FMCP_PRSNT_M2C_B FMCP2_FMCP_PRSNT_M2C_B VCCINT_VRHOT_B 8A34001_EXP_RST_B
PMBUS_ALERT
I2C Switch Position
P11
IN
P12
IN
P13
IN
P14
IN
P15
IN
P16
IN
I2C Address I2C0 Bus
N/A N/A N/A N/A N/A
N/A
PMBUS1_INA226_ALERT
P17
TCA9548A 8-Chan. bus switch
N/A
Function
Port
PMBUS_SDA/SCL
0
PMBUS1_INA226_SDA/SCL
1
IN
N/A
0b1110101
Binary Format
0b00010011-0b00010100, 0b00010110-0b00010111, 0b00011001-0b00100000
0x75 Hex Format
0x13, 0x14, 0x16, 0x17, 0x19-0x20
0b01000000-0b01000101 0x40-0x45
PMBUS2_INA226_SDA/SCL
3
No connect
4
zSFP_SI570_SDA/SCL
5
USER_SI570_1_CLOCK_SDA/SCL
6
No Connect
7
0b01000000-0b01000101 0x40-0x4D
NA 0b1011101 0b1011111 NA
NA 0x5D 0x5F NA
Device
J53 FMCP HSPC J51 FMCP HSPC J53 FMCP HSPC U152 IR35215 U221 SN74LVC1G08 U152, U160, U167, U175, U179, U181, U183, U185, U187, U189, U194, U195 Various Vreg, U125 ZU4EG U65,U161-U165 INA226, U125 ZU4EG
U33 TCA9548A
See tables in Board Power System
U65,U161-U165 INA226; see tables in Board Power System U166, U168, U172, U173, U174, U176, U177, U178, U180, U182, U184, U186, U188, U234 INA226; see tables in Board Power System NA U192 SI570 U205 SI570 NA
PMC MIO[44:45] I2C1 Bus
[Figure 3, callout 11]
Bus I2C1 connects the XCVC1902 U1 PS bank 501, and the XCZU4EG system controller U125 PS bank 501 to two I2C switches (TCA9548A U35 and U214). These I2C1 connections enable I2C communications with other I2C capable target devices. TCA9548A U35 is pin-strapped to respond to I2C address 0x74. TCA9548A U214 is pin-strapped to respond to I2C address 0x75. The following figure shows the I2C1 bus connectivity detailed in the first two tables below. The I2C0 target device I2C addresses are listed in the third table.
For more information on the TCA9548A and TCA6416A, see the Texas Instruments website.
The detailed ACAP connections for the feature described in this section are documented in the VCK190 board XDC file, referenced in Appendix B: Xilinx Design Constraints.
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System Controller PMC Bank 501 U125 XCZU4EG
Versal ACAP PMC Bank 501
U1
Figure 15: I2C1 Bus Topology
U213 L/S
U211 L/S
I2C1 I2C1
0x74
0
1
2
I2C
3
MUX 4
#1
5
6
7 U35 TCA9548A
DC_I2C FMCP1_IIC FMCP2_IIC DDR4_DIMM1 LPDDR4_SI570_CLK2 LPDDR4_SI570_CLK1 HSDP_SI570 8A34001
0x75
0
1
2
I2C
3
MUX 4
#2
5
6
7 U214 TCA9548A
SFP0_IIC SFP1_IIC QSFP1_I2C NC NC NC NC NC
X23202-120120
Table 13: I2C1 TCA9548A U35 Address 0x74 Connections
TCA9548A U35 Pin Name Pin No.
Schematic Net Name
SDA
19
I2C0_SDA
SCL
18
I2C0_SCL
SD0/SC0
4/5
DC_I2C_SDA/SCL
SD1/SC1 SD2/SC2
SD3/SC3
SD4/SC4 SD5/SC5 SD6/SC6
SD7/SC7
6/7
FMCP1_IIC_SDA/SCL
8/9
FMCP2_IIC_SDA/SCL
10/11 DDR4_DIMM1_SDA/SCL
13/14 15/16 17/18
LPDDR4_SI570_CLK2_SDA/SCL LPDDR4_SI570_CLK1_SDA/SCL HSDP_SI570_SDA/SCL
19/20 8A34001_SDA/SCL
Pin No.
Connected To
Pin Name
Reference Designator
Device
See the connections shown in the "I2C1 Bus Topology" figure. TCA9548A U35 Addr. 0x74
D25,D24 5,6 7,8
C31,C30 C31,C30 285,141
7,8 7,8 7,8 7,8 L2,K2 3,1&2
D25,D24 SDA,SCL SDA,SCL SDA, SCL SDA, SCL SDA, SCL SDA,SCL SDA,SCL SDA, SCL SDA, SCL SDIO, SCLK
NA
J212 U34 U32 J51 J53 J45 U2 U3 U4 U5 U219 J310
DC connector M24128-BR SI570 ASP_184329_01 ASP_184329_01 FCI 10124677 SI570 SI570 SI570 SI570 8A34001 2x9 HDR
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Table 14: I2C1 TCA9548A U214 Address 0x75 Connections
TCA9548A U214
Pin Name
Pin No.
SDA SCL SD1/SC1 SD2/SC2 SD3/SC3
19 18 6/7 8/9 10/11
Schematic Net Name
I2C0_SDA I2C0_SCL SFP0_IIC_SDA/SCL SFP1_IIC_SDA/SCL QSFP1_I2C_SDA/SC L
Connected To
Pin No.
Pin Name
Reference Designator
Device
See the connections shown in the "I2C1 Bus Topology" figure. TCA9548A U214 Addr. 0x75
T4,T5 L4,L5 12,11
SDA_T4,SCL_T5 SDA_L4,SCL_L5
SDA, SCL
J287(TOP) J287(BOT)
J288
2198318-6 2198318-6 1551920-2
Table 15: I2C1 Bus Device I2C Addresses
I2C Devices
I2C Switch Position
TCA9548A 8-channel bus switch Function
DC_I2C_SDA/ SCL
FMCP1_IIC_SDA/ SCL FMCP2_IIC_SDA/ SCL DDR4_DIMM1_SDA/ SCL LPDDR4_SI570_CLK2 LPDDR4_SI570_CLK1 HSDP_SI570_SDA/SCL
8A34001_SDA/SCL
TCA9548 8-chan. bus switch SFP0_IIC_SDA/SCL SFP1_IIC_SDA/SCL QSFP1_I2C_SDA/SCL No connect
N/A Port
0
1
2
3 4 5 6 7
N/A 0 1 2
3 - 7
I2C1 Bus
I2C Address
0b1110100
0x74
Binary Format 0b1010100 0b1000010 0b1011101
Hex Format 0x54 0x42 0x5D
0bXXXXXXX
0x##
0bXXXXXXX
0b1010000 0b1100000 0b1100000 0b1100000 0b1011101 0b1011000
TBD 0b1110101
0b1010000 0b1010000 0b1010000
NA
0x##
0x50 0x60 0x60 0x60 0x5D 0x58 TBD 0x75
0x50 0x50 0x50
NA
Device
U35 TCA9548A
DC SE1 on J212 DC SE2 on J212
U32 SI570 J51 FMC HSPC
J53 FMC HSPC J45 FCI socket
U2 SI570 U3 SI570 U4 SI570 U5 SI570 U219 8A34001 J310 2x9 HDR. U214 TCA9548A J287 (BOT) J287 (TOP)
J288 NA
PMC MIO[48] and LPD_MIO[0:11, 24:25]: GEM0 Ethernet
[Figure 3, callout 16]
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A PS Gigabit Ethernet MAC (GEM) implements a 10/100/1000 Mb/s Ethernet interface (see the figure in PMC MIO[49] and LPD_MIO[12:25]: GEM1 Ethernet), which connects to TI DP83867IRPAP U198 Ethernet RGMII PHY before being routed to a vertical dual-stacked RJ45 Ethernet connector J307 (upper receptacle). The RGMII Ethernet PHY is boot strapped to PHY address (0x01) and Auto Negotiation is set to Enable.
LPD MIO[0:11 24:25] LPD MIO[12:23 24:25]
PMC MIO[49] and LPD_MIO[12:25]: GEM1 Ethernet
[Figure 3, callout 17]
A PS Gigabit Ethernet MAC (GEM) implements a 10/100/1000 Mb/s Ethernet interface (see the following figure), which connects to TI DP83867IRPAP U134 Ethernet RGMII PHY before being routed to a vertical dual-stacked RJ45 Ethernet connector J307 (lower receptacle). The RGMII Ethernet PHY is boot strapped to PHY address (0x02) and Auto Negotiation is set to Enable.
The following figure shows the dual Ethernet topology.
Figure 16: Dual RGMII Ethernet
XCVC1902 ACAP
RGMII MDIO
RGMII MDIO
GEM0 U198
DP83867IR 10/100/1000
PHY
GEM1 U134
DP83867IR 10/100/1000
PHY
MII
25 MHz Crystal
MII
25 MHz Crystal
J307 Upper RJ45
J307 Lower RJ45
X23203-100119
Ethernet PHY (Three Resets)
[Figure 3, callout 35]
Each DP83867ISRGZ PHY (GEM0 U198, GEM1 U134) is reset by its GEMx_RESET_B generated by dedicated pushbutton switches and PMC_MIO signals as shown in the following figure. The POR_B signal generated by the TPS389001DSER U10 POR device (activated by pushbutton SW2) is wired in parallel to each Ethernet PHY reset circuit.
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Chapter 3: Board Component Descriptions Figure 17: Ethernet PHY Reset Circuit
X24952-121420
Ethernet PHY LED Interface
[Figure 3, callout 16 and 17]
Each DP83867ISRGZ PHY (GEM0 U198, GEM1 U134) controls two LEDs in the J307 two port connector bezel. The upper port (GEM0) yellow and green LEDs are above the port, and the lower port (GEM1) LEDs are below the port. The PHY signal LED0 drives the green LED, and LED1 drives the yellow LED. The LED2 signal is not used.
The LED functional description is listed in the following table.
Table 16: Ethernet PHY LED Functional Description
DP83867IS PHY Pin
Name
Number
LED_2
45
LED_1
46
LED_0
47
Type
Description
S, I/O, PD S, I/O, PD S, I/O, PD
By default, this pin indicates receive or transmit activity. Additional functionality is configurable using LEDCR1[11:8] register bits.
By default, this pin indicates that 100BASE-T link is established. Additional functionality is configurable using LEDCR1[7:4] register bits.
By default, this pin indicates that link is established. Additional functionality is configurable using LEDCR1[3:0] register bits.
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The LED functions can be repurposed with a LEDCR1 register write available via the PHY's management data interface, MDIO/MDC.
See the TI DP83867 RGMII PHY data sheet at the Texas Instruments website for component details.
The detailed ACAP connections for the feature described in this section are documented in the VCK190 board XDC file, referenced in Appendix B: Xilinx Design Constraints.
JTAG Chain
[Figure 3, callout 7, 8, and 48]
VCK190 JTAG chain · J36 2x7 2 mm shrouded, keyed JTAG pod flat cable connector · J207 USB-C connector connected to U20 FT4232HL USB-JTAG bridge · U125 XCZU4EG System Controller bank 44
Figure 18: JTAG Chain Block Diagram
U125 XCZU4EG BANK 44 TDO TDI SYSTEM
CONTROLLER
J36 JTAG
2 mm 2X7 Header
TDO TDI
U1 ACAP U1 BANK 503 Config
JTAG TDO IF TDI
J53
FMC2 TDO TDI
N.C.
J51
FMC1 TDO TDI
N.C.
U16
B-to-A
JTAG
B
TDO
A
L/S
U239
A-to-B
JTAG
B
TDI
A
L/S
U240
U241
UTIL_3V3
R88 4.70K
R87 4.70K
SW3
12 ON ON ON OFF
UTIL 3v3
SS
SW3
01 00 CH1 SYSCTLR JTAG 01 CH2 FT4232 JTAG
1
2
R97
3
499
1
1
2
2
Set SW3 to
"ON OFF"
R98 499
U15 S1 S0 OEn
1A
1B1
1B2 JTAG
MUX
SYSCTLR_VERSAL_TDO FT4232_TDO
2A
1B1 2B2
SYSCTLR_VERSAL_TDI FT4232_TDI
See Versal ACAP Configuration for information on JTAG programming via:
U20
TDO FT4232HL UART BRIDGE
TDI
J207 U S B
X23204-100719
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· FTDI FT4232 USB-to-JTAG/USB-UART device (U20) connected to USB 3.1 type-C connector (J207)
· JTAG pod flat cable connector J36 (2 mm 2x7 shrouded/keyed)
See the "FT4232HL UART Interface Connections" figure in PMC MIO[42:43] UART0 for an overview of FT4232 U20 JTAG and USB-UART connectivity.
Clock Generation
The VCK190 board provides fixed and variable clock sources for the XCVC1902 U1 ACAP and other function blocks. The following table lists the source devices for each clock.
Table 17: Clock Sources
Callout
36 37 38 39 40 41 42 43 44 45 46 47
Ref. Des.
U2 U3 U4 U5 U32 U39 U62 U142 U192 U205 U219 J328-J331
Feature
Notes
Schematic Page
DDR4 DIMM CLK, 200 MHz, 3.3V Silicon Labs SI570BAB000299DG
4
LVDS, 0x60
LPDDR4 CLK2, 200 MHz, 3.3V
Silicon Labs SI570BAB000299DG
5
LVDS, 0x60
LPDDR4 CLK1, 200 MHz, 3.3V
Silicon Labs SI570BAB000299DG
7
LVDS, 0x60
HSDP CLK, 156.25 MHz, 3.3V
Silicon Labs SI570BAB000544DG
8
LVDS, 0x5D
ACAP U1 REF CLK, 33.33 MHz, Silicon Labs SI570JAC000900DG
43
1.8V CMOS, 0x5D
PCIe jitter atten., 100 MHz, 3.3V IDT 85411AMLF
49
LVDS
HDMI jitter atten., 148.50 MHz, IDT 8T49N241-994NLGI
52
3.3V LVDS, 0x6C
SYSCTLR clocks 33.33 MHz & 125 Silicon Labs Si5332FD10259-
101
MHz I2C 0x6A
GM1
zSFP CLK, 156.25 MHz, 3.3V
Silicon Labs SI570BAB000544DG
8
LVDS, 0x5D
FMCP MGT CLK, 100 MHz, 3.3V Silicon Labs SI570BAC002038DG
48
LVDS, 0x5F
IEEE-1588 eCPRI CLK, various, IDT 8A34001E-000AJG8
104
3.3V, 0x58
IEEE-1588 eCPRI 8A34001 CLK in Rosenberger 32K10K-400L5
104
and out SMA pairs
The connection details for ACAP U1 connected clocks described in this section are documented in the VCK190 board XDC file, referenced in Appendix B: Xilinx Design Constraints.
Programmable DDR4 DIMM SI570 Clock
[Figure 3, callout 36]
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The VCK190 board has an I2C programmable SI570 low-jitter 3.3V LVDS differential oscillator (U2) connected to the GC inputs of U1 DDR4 DIMM interface bank 700. The DDR4_DIMM1_CLK_P and DDR4_DIMM1_CLK _N series capacitor coupled clock signals are connected to XCVC1902 ACAP U1 pins AE42 and AF43, respectively. At power-up, this clock defaults to an output frequency of 200.000 MHz. User applications or the System Controller can change the output frequency within the range of 10 MHz to 945 MHz through the I2C bus interface. Power cycling the VCK190 board reverts this user clock to the default frequency of 200.000 MHz.
· Programmable oscillator: Silicon Labs SI570BAB000299DG (10 MHz-945 MHz range, 200.000 MHz default)
· I2C address 0x60 · LVDS differential output, total stability: 61.5 ppm
Programmable LPDDR4 SI570 Clock2
[Figure 3, callout 37]
The VCK190 board has an I2C programmable SI570 low-jitter 3.3V LVDS differential oscillator (U3) connected to the GC inputs of U1 LPDDR4_2 interface bank 705. The LPDDR4_CLK2_P and LPDDR4_CLK2_N series capacitor coupled clock signals are connected to XCVC1902 ACAP U1 pins AW27 and AY27, respectively. At power-up, this clock defaults to an output frequency of 200.000 MHz. User applications or the System Controller can change the output frequency within the range of 10 MHz to 945 MHz through the I2C bus interface. Power cycling the VCK190 board reverts this user clock to the default frequency of 200.000 MHz.
· Programmable oscillator: Silicon Labs SI570BAB000299DG (10 MHz-945 MHz range, 200.000 MHz default)
· I2C address 0x60 · LVDS differential output, total stability: 61.5 ppm
Programmable LPDDR4 SI570 Clock1
[Figure 3, callout 38]
The VCK190 board has an I2C programmable SI570 low-jitter 3.3V LVDS differential oscillator (U4) connected to the GC inputs of U1 LPDDR4_1 interface bank 705. The LPDDR4_CLK1_P and LPDDR4_CLK1_N series capacitor coupled clock signals are connected to XCVC1902 ACAP U1 pins AK8 and AK7, respectively. At power-up, this clock defaults to an output frequency of 200.000 MHz. User applications or the System Controller can change the output frequency within the range of 10 MHz to 945 MHz through the I2C bus interface. Power cycling the VCK190 board reverts this user clock to the default frequency of 200.000 MHz.
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· Programmable oscillator: Silicon Labs SI570BAB000299DG (10 MHz-945 MHz range, 200.000 MHz default)
· I2C address 0X60 · LVDS differential output, total stability: 61.5 ppm
Programmable HSDP SI570 Clock
[Figure 3, callout 39]
The VCK190 board has an I2C programmable SI570 low-jitter 3.3V LVDS differential oscillator (U5) connected to the GTY_REFCLK1 inputs of U1 GTY bank 105. The HSDP_SI570_CLK_P and HSDP_SI570_CLK _N series capacitor coupled clock signals are connected to XCVC1902 ACAP U1 pins J39 and J40, respectively. At power-up, this clock defaults to an output frequency of 156.250 MHz. User applications or the System Controller can change the output frequency within the range of 10 MHz to 945 MHz through the I2C bus interface. Power cycling the VCK190 board reverts this user clock to the default frequency of 156.250 MHz.
· Programmable oscillator: Silicon Labs SI570BAB000544DG (10 MHz-945 MHz range, 156.250 MHz default)
· I2C address 0x5D · LVDS differential output, total stability: 61.5 ppm
Programmable zSFP SI570 Clock
[Figure 3, callout 44]
The VCK190 board has an I2C programmable SI570 low-jitter 3.3V LVDS differential oscillator (U192) connected to the GTY_REFCLK0 inputs of U1 GTY bank 105. The zSFP_SI570_CLK_P and zSFP_SI570_CLK _N series capacitor coupled clock signals are connected to XCVC1902 ACAP U1 pins L39 and L40, respectively. At power-up, this clock defaults to an output frequency of 156.250 MHz. User applications or the System Controller can change the output frequency within the range of 10 MHz to 945 MHz through the I2C bus interface. Power cycling the VCK190 board reverts this user clock to the default frequency of 156.250 MHz.
· Programmable oscillator: Silicon Labs SI570BAB000544DG (10 MHz-945 MHz range, 156.250 MHz default)
· I2C address 0x5D · LVDS differential output, total stability: 61.5 ppm
Programmable SI570 REF Clock
[Figure 3, callout 40]
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The VCK190 board has an I2C programmable SI570 low-jitter 1.8V CMOS single-ended oscillator (U32). The 33.333 MHz REF_CLK clock signals is connected to XCVC1902 ACAP U1 configuration bank 503 pin AE32. At power-up, this clock defaults to an output frequency of 33.333 MHz. User applications or the System Controller can change the output frequency within the range of 10 MHz to 945 MHz through the I2C bus interface. Power cycling the VCK190 board reverts this user clock to the default frequency of 33.333 MHz.
· Programmable oscillator: Silicon Labs SI570JAC000900DG (10 MHz-945 MHz range, 33.333 MHz default)
· I2C address 0x5D · CMOS single-ended output, total stability: 61.5 ppm
Programmable SI5332 System Controller Clock
[Figure 3, callout 43]
The VCK190 board has an I2C programmable SI5332 low-jitter 6-differential-output clock generator (U142). Each output clock P/N pair has its own independent Vout pin. Two of the six output clocks are used on the VCK190.
OUT0 is a single-ended 33.333 MHz 1.8V LVCMOS clock SYSCTLR_PS_REF_CLK connected to the XCZU4EG System Controller (U125) configuration bank 503 pin R16.
OUT1 is a differential 125.000 MHz 3.3V LVDS clock. The SYSCTLR_GTR_CLK0_SGMII_P and SYSCTLR_GTR_CLK0_SGMII_N series capacitor coupled clock signals are connected to XCZU4EG U125 GTR bank 505 MGTREFCLK0 pins F23 and F24, respectively.
At power-up, OUT0 and OUT1 default the frequencies indicated above. User applications or the System Controller can change the output frequency within the range of 0 MHz to 333.333 MHz through the I2C bus interface. Power cycling the VCK190 board reverts the OUT0 and OUT1 frequencies to their defaults.
· Programmable clock generator: Silicon Labs Si5332FD10259-GM1 (0 MHz-333.333 MHz range)
· Outputs OUT0: 33.3333... MHz [33 + 1/3 MHz] LVCMOS Single (+) 1.8V 50 [100/3 MHz]
OUT1: 125 MHz LVDS slow 3.3V
OUT2: 26 MHz LVDS slow 3.3V
OUT3: Unused
OUT4: Unused
OUT5: Unused
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· I2C address 0x6A
PCIe Clock
[Figure 3, callout 41]
The VCK190 board includes an IDT 85411 (U39) 1:2 clock buffer for the PCIe clock fan out to the Versal ACAP. The 100 MHz PCIE_CLK_P/N clock from the PCIe 8-lane edge connector (P3) drives the U39 clock input.
The U39's buffered outputs are used to create differential clock pairs to the ACAP U1 GTY103/ GTY104 PCIe interface:
· U39's Q0 PCIE_CLK0_P/N are connected to PCIE_TX/RX[0:3] interface GTY103 GTY_REFCLK0 pins W39 (P) and W40 (N), which are A/C coupled
· U39's Q1 PCIE_CLK1_P/N are connected to PCIE_TX/RX[4:7] interface GTY104 GTY_REFCLK0 pins R39 (P) and R40 (N), which are A/C coupled
· 1:2 clock buffer Q0: 100 MHz LVDS
Q1: 100 MHz LVDS
Programmable FMCP MGT SI570 Clock with Buffer
[Figure 3, callout 45]
The VCK190 board has an I2C programmable SI570 low-jitter 3.3V LVDS differential oscillator (U205) driving SI53340 (U206) 2-to-4 clock buffer input CLK0. The clock buffer generates four copies of the input clock. The SI53340 CLK1 second input is driven by 8A34001 (U219) output Q2. The SI53340 input clock select is controlled by 2-pin header J306 with default jumper off, selecting the CLK0 SI570 input. At power-up, SI570 (U205) defaults to an output frequency of 100.000 MHz. User applications or the System Controller can change the output frequency within the range of 10 MHz to 945 MHz through the I2C bus interface. Power cycling the VCK190 board reverts this user clock to the default frequency of 100.000 MHz.
· Programmable oscillator: Silicon Labs SI570BAB000299DG (10 MHz-945 MHz range, 100.000 MHz default)
· I2C address 0x5F · LVDS differential output, total stability: 61.5 ppm
The four SI53340 (U206) outputs are connected as follows:
· Outputs Q0: SI570_8A34001_MUX_BUF0_P/N capacitor coupled to GTY201 FMCP1_DP[0:3]_C2M/M2C interface GTY_REFCLK0 pins AB11 (P) and AB10 (N)
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Q1: SI570_8A34001_MUX_BUF1_P/N capacitor coupled to GTY204 FMCP2_DP[0:3]_C2M/M2C interface GTY_REFCLK0 pins G13 (P) and G12 (N)
Q2: SI570_8A34001_MUX_BUF2_P/N capacitor coupled to GTY205 FMCP2_DP[4:7]_C2M/M2C interface GTY_REFCLK0 pins E13 (P) and E12 (N)
Q3: SI570_8A34001_MUX_BUF3_P/N capacitor coupled to GTY206 FMCP2_DP[8:11]_C2M/M2C interface GTY_REFCLK0 pins C13 (P) and C12 (N)
The connection details for ACAP U1 connected clocks described in this section are documented in the VCK190 board XDC file, referenced in Appendix B: Xilinx Design Constraints.
For more details on the Silicon Labs SI570, SI5332, and SI53340 devices, see the Silicon Labs website.
For more details on the IDT 85411AMLF, 8T49N241, and 8A34001 devices, see the Integrated Device Technology, Inc. website.
For Versal ACAP clocking information, see the Versal ACAP Clocking Resources Architecture Manual (AM003).
IEEE-1588 eCPRI Programmable Synchronization Management Unit
[Figure 3, callout 46]
GTY Transceivers
[Figure 3, callout 1]
The GTY transceivers in the XCVC1902 ACAP U1 are grouped into four channels or quads. The XCVC1902 has four GTY quads (GTYs 103-106) on the right side of the device and seven GTY quads (GTYs 200-206) on the left side of the device.
The VCK190 board provides access to 11 of the 11 GTY quads as shown in the GTY map in the following table.
Table 18: GTY Mapping
HDMI_TX_CLK_LVDS (TX only) HDMI Lane 2 HDMI Lane 1 HDMI Lane 0 HDMI_9T49N241_CLK
ch3
ch2 ch1 ch0 refclk1
HDMI_RX_CLK
refclk0
GTYT_S Quad 106
VCK190 XC10S80 VSVA2197 GTY Mapping
GTYT_S Quad 206
ch3
ch2 ch1 ch0 refclk1
refclk0
FMC2 DP11
FMC2 DP10 FMC2 DP9 FMC2 DP8 FMC2_GBTCLK2 SI570_8A34001_MUX_BU F3
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Table 18: GTY Mapping (cont'd)
SFP1 SFP0 None HSDP (USB-C) HSDP SI570 CLK
zSFP SI570 CLK
PCIe Lane 7 PCIe Lane 6 PCIe Lane 5 PCIe Lane 4 None PCIe Slot Clock 0 (buffered) PCIe Lane 3 PCIe Lane 2 PCIe Lane 1 PCIe Lane 0 NONE PCIe Slot Clock 0 (buffered)
ch3 ch2 ch1 ch0 refclk1
refclk0
ch3 ch2 ch1 ch0 refclk1
refclk0
ch3 ch2 ch1 ch0 refclk1
refclk0
VCK190 XC10S80 VSVA2197 GTY Mapping
PCIe
PCIe
GTYT_M Quad 105
GTYB_M Quad 104
PCIe
MRMAC
GTYT_S Quad 103
CPMG4
MRMAC
CPMG4
PCIe
MRMAC
MRMAC
GTYT_S Quad 205
GTYB_S Quad 204
GTYT_M Quad 203
GTYB_M Quad 202
GTYT_S Quad 201
GTYB_S Quad 200
ch3 ch2 ch1 ch0 refclk1
refclk0
ch3 ch2 ch1 ch0 refclk1
refclk0
ch3 ch2 ch1 ch0 refclk1
refclk0
ch3 ch2 ch1 ch0 refclk1 refclk0 ch3 ch2 ch1 ch0 refclk1
refclk0
ch3 ch2 ch1 ch0 refclk1 refclk0
The GTY connections are shown in the following figure.
FMC2 DP7 FMC2 DP6 FMC2 DP5 FMC2 DP4 FMC2_GBTCLK1 SI570_8A34001_MUX_BU F2 FMC2 DP3 FMC2 DP2 FMC2 DP1 FMC2 DP0 FMC2_GBTCLK0 SI570_8A34001_MUX_BU F1 FMC1 DP11 FMC1 DP10 FMC1 DP9 FMC1 DP8 FMC1_GBTCLK2
None
FMC1 DP7 FMC1 DP6 FMC1 DP5 FMC1 DP4 FMC1_GBTCLK1 None FMC1 DP3 FMC1 DP2 FMC1 DP1 FMC1 DP0 FMC1_GBTCLK0 SI570_8A34001_MUX_BU F0 QSFP4 QSFP3 QSFP2 QSFP1 IEEE-1588 Clock IEEE-1588 Clock
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Figure 19: VCK190 GTY Connections
HDMI
2x zSFP
HSDP
PCIe
Lane 4 Lane 5 Lane 6 Lane 7
GEN4
x8
Lane 0 Lane 1
Lane 2
Lane 3
GTY0 GTY1 GTY2 GTY3
GTY
Bank 106
GTY0 GTY1 GTY2 GTY3
GTY
Bank 105
GTY0 GTY1 GTY2 GTY3
GTY
Bank 104
GTY0 GTY1 GTY2 GTY3
GTY
Bank 103
MRMAC MRMAC
MRMAC MRMAC
GTY
GTY0 GTY1
4
GTY2
Bank 206 GTY3
GTY
GTY0 GTY1
4
GTY2
Bank 205 GTY3
GTY
GTY0 GTY1
4
GTY2
Bank 204 GTY3
GTY
GTY0 GTY1
4
GTY2
Bank 203 GTY3
GTY
GTY0 GTY1
4
GTY2
Bank 202 GTY3
GTY
GTY0 GTY1
4
GTY2
Bank 201 GTY3
GTY
Bank 200
GTY0 GTY1 GTY2 GTY3
4 zQSFP
FMC+_01
FMC+_02
X23205-120120
GTY103/104: PCI Express Card Edge Connectivity
[Figure 3, callout 15]
The 8-lane PCI Express card edge connector P3 supports operation up to Gen4 x8. P3 supports data transfers at the rate of 2.5 GT/s for Gen1 applications, 5.0 GT/s for Gen2 applications, 8.0 GT/s for Gen3 applications, and 16.0 GT/s for Gen4 applications. The PCIe transmit and receive signal data paths have a characteristic impedance of 85 ±10%. The PCIe_EP_REFCLK_P/N PCIe reference clock (routed as a 100 differential pair) received from J18 is routed to IDT 85411AMLF U39 1:2 buffer, which retransmits the clock as PCIe_CLK0 and PCIe_CLK1. U39 output Q0 PCIe_CLK0_P/N is routed to GTY103 (PCIe_EP_TX/RX[3:0]_P/N) and output Q1 PCIe_CLK1_P/N is routed to GTY104 (PCIe_TX/RX[7:4]_P/N).
For additional information about the Versal ACAP PCIe functionality, see the Versal ACAP Integrated Block for PCI Express LogiCORE IP Product Guide (PG343). Additional information about the PCI Express standard is available at the PCI-SIG website.
The detailed ACAP connections for the feature described in this section are documented in the VCK190 board XDC file, referenced in Appendix B: Xilinx Design Constraints.
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GTY105: HSDP and 2x zSFP
GTY105 channel 1 is not used. The GTY105 channel 0 high-speed debug port is a new feature that will be supported in the future. GTY105 REFCLK1 receives the HSDP_SI570_CLK from Si570 U5 (default frequency 156.25 MHz). GTY105 channel 2 is wired to SFP0 and channel 3 is wired to SFP1. The two zSFPs are implemented in a dual-port stacked connector J287 (SFP0 lower, SFP1 upper). Each SFP has an I2C connection to the I2C1 bus through the I2C multiplexer (TCA9548PWR U214) as documented in PMC MIO[44:45] I2C1 Bus. GTY105 REFCLK0 receives the zSFP_SI570_CLK from Si570 U192 (default frequency 156.25 MHz).
zSFP/zSFP+ Module Connector
[Figure 3, callout 13] The VCK190 board hosts dual-port zSFP/zSFP+ J287, which accepts zSFP or zSFP+ modules. The following figure shows the zSFP/zSFP+ module connector circuitry typical of the two implementations.
Figure 20: zSFP/zSFP+ Module Connector
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The following table lists the zSFP+ module control and status connections.
Table 19: zSFP0- zSFP1 Module Control and Status Connections
zSFP Control/ Status Signal
SFP0_TX_FAULT SFP0_TX_DISABLE SFP0_MOD_DETECT
SFP0_RS01 SFP0_RS11 SFP0_LOS
Test point J276 Jumper J35
Test point J31 PU R1420/PD R1426 PU R1421/PD R1427
Test point J33
Board Connection
High = Fault Low = Normal operation Off = SFP disabled On = SFP enabled High = Module not present Low = Module present PU R25 = Full RX bandwidth PD R30 = Reduced RX bandwidth PU R227 = Full RX bandwidth PD R142 = Reduced RX bandwidth High = Loss of receiver signal Low = Normal operation
zSFP Module
zSFP0 J287 lower
SFP1_TX_FAULT
Test point J30
High = Fault Low = Normal operation
SFP1_TX_DISABLE
Jumper J32
Off = SFP disabled On = SFP enabled
SFP1_MOD_DETECT SFP1_RS01
Test point J277 PU R1428/PD R1431
High = Module not present Low = Module present PU R182 = Full RX bandwidth PD R190 = Reduced RX bandwidth
zSFP1 J287 upper
SFP1_RS11
PU R1429/PD R1432
PU R185 = Full RX bandwidth PD R202 = Reduced RX bandwidth
SFP1_LOS
Test point J278
High = Loss of receiver signal Low = Normal operation
Notes:
1. The RS0/RS1 PU/PD resistors are not populated. There are pull-down resistors built into the SFP/zSFP modules that select the lower bandwidth mode of the module.
For additional information about the enhanced SFP+ module, see the SFF-8431 specification at the SNIA website.
The zSFP connector I2C interfaces are connected to the I2C bus via the TCA9548 I2C multiplexer U214 (see PMC MIO[46:47] I2C0 Bus and PMC MIO[44:45] I2C1 Bus for more details).
The detailed ACAP connections for the feature described in this section are documented in the VCK190 board XDC file, referenced in Appendix B: Xilinx Design Constraints.
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GTY200: QSFP1
The GTY200 channels 0:3 are wired to QSFP1 J288. The GTY200 REFCLK0 drives 8A34001_CLK1_IN, and REFCLK1 receives the 8A34001_Q1_OUT to and from the 8A34001 clock device U219.
QSFP Module Connector
[Figure 3, callout 14] The following figure shows the QSFP module connector circuitry implementation.
Figure 21: QSFP Module Connector
X24954-121420
The QSFP connector 3.3V control nets are wired to ACAP U1 bank 406.
The QSFP connector I2C interface is connected to the I2C bus via the TCA9548 I2C multiplexer U214 (see PMC MIO[44:45] I2C1 Bus for more details).
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The detailed ACAP connections for the feature described in this section are documented in the VCK190 board XDC file, referenced in Appendix B: Xilinx Design Constraints.
GTY106: HDMI TX and RX
HDMI Video Output (TX)
[Figure 3, callout 18 and 19]
The VCK190 board provides an HDMITM video output using a TI SN65DP159RGZ HDMI retimer at U43. The HDMI output is provided on a TE Connectivity 1888811-1 right-angle dual-stacked HDMI type A receptacle at P2 (upper port). The SN65DP159RGZ device is a dual mode DisplayPort to transition-minimized differential signal (TMDS) retimer supporting digital video interface (DVI) 1.0 and HDMI 1.4b and 2.0 output signals. The SN65DP159RGZ device supports the dual mode standard version 1.1 type 1 and type 2 through the DDC link or AUX channel. The SN65DP159RGZ device supports data rates up to 6 Gb/s per data lane to support Ultra HD (4K x 2K/60 Hz) 8-bits per color high-resolution video and HDTV with 16-bit color depth at 1080p (1920 x 1080/60 Hz). The SN65DP159RGZ device can automatically configure itself as a redriver at data rates <1 Gb/s, or as a retimer at more than this data rate. This feature can be turned off through I2C programming. The HDMI video transmit/receive block diagram is shown in the following figure.
The ACAP U1 bank 406 user logic can implement a clock recovery circuit and output the series resistor coupled HDMI_REC_CLK_OUT (pin L19) for jitter attenuation. The jitter attenuated U62 Q2 HDMI_8T49N241_OUT_P/N series capacitor coupled output clock is connected to the HDMI_TX/RX[0:3] interface GTY106 GTY_REFCLK1 pins E39 (P) and E40 (N).
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Figure 22: HDMI Interface Block Diagram
HDMI IP
HDMI_0 HDMI_1 HDMI_2 TX_CLK_LVDS
DRIVER (SN65DP159)
TMDS_0 TMDS_1 TMDS_2 TMDS_CLK
HDMI_OUT
I2C_SRC I2C_CTL_HDMI_OUT
8T49N241
I2C_SNK
EDID EEPROM
HDMI_8T49N241_OUT
HDMI_0 HDMI_1 HDMI_2
RX_GTH_REFCLK
TMDS181 and Termination
Network
TMDS_0 TMDS_1 TMDS_2
TMDS_CLK
HDMI_IN
I2C_HDMI_IN
X23206-091019
The VCK190 board accepts HDMI video input on the TE Connectivity 1888811-1 right-angle dual-stacked HDMI type-A receptacle P2 (lower port). The HDMI TMDS signals are input to TI TMDS181 retimer U55, which then drives the series capacitor coupled HDMI RX signals to U1 XCVC1902 GTY bank 106. The VCK190 HDMI RX interface supports up to 4K 60 Hz resolutions. See the Xilinx HDMI IP documentation for more details about resolutions, color spaces, and optional HDCP features supported by the U1 Versal ACAP.
The HDMI clock recovery is detailed in PCIe Clock.
For Xilinx HDMI IP details, see the HDMI 1.4/2.0 Transmitter Subsystem Product Guide (PG235) and the HDMI Transmitter and Receiver Subsystem Answer Record 70514.
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See the HDMI Transmitter and Receiver Subsystem Answer Record 70514 for HDMI-compliant references.
For more details on the TI SN65DP159RGZ and TMDS181 HDMI retimers, see the component data sheets on the Texas Instruments website. For more details on the IDT 8T49N241, see the component data sheet on the Integrated Device Technology, Inc. website.
The detailed ACAP connections for the feature described in this section are documented in the VCK190 board XDC file, referenced in Appendix B: Xilinx Design Constraints.
GTY201 GTY203: FMCP1 and GTY203 GTY206: FMCP2
FPGA Mezzanine Card Interface
[Figure 3, callout 20 and 21]
The VCK190 evaluation board supports the VITA 57.4 FPGA mezzanine card (FMC+ or FMCP) specification by providing a subset implementation of the high pin count connectors at J51 (FMCP1) and J53 (FMCP2). FMC+ connectors use a 14 x 40 form factor, populated with 560 pins. The connector is keyed so that a mezzanine card, when installed on the VCK190 evaluation board, faces away from the board.
The FMCP1 DP[0:11] are connected across ACAP U1 GTY201-GTY203. The FMCP2 DP[0:11] are connected across ACAP U1 GTY204-GTY206. The FMCP1 and FMCP2 LA[0:33] bus and differential CLK pairs are connected across the banks 706, 707, and 708 triplet.
The detailed ACAP connections for the feature described in this section are documented in the VCK190 board XDC file, referenced in Appendix B: Xilinx Design Constraints.
FMC+ Connector Type
The Samtec SEAF series, 1.27 mm (0.050 in) pitch mates with the SEAM series connector. For more information about the SEAF series connectors, see the Samtec, Inc. website.
The 560-pin FMC+ connector defined by the FMC specification (see Appendix A: VITA 57.4 FMCP Connector Pinouts) provides connectivity for up to:
· 160 single-ended or 80 differential user-defined signals · 24 transceiver differential pairs · 6 transceiver (GBTCLK) differential clocks · 4 differential (CLK) clocks · 1 differential (REFCLK) clock (both C2M and M2C pairs) · 1 differential (SYNC) clock (both C2M and M2C pairs)
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· 239 ground and 17 power connections For more information about the VITA 57.4 FMC+ specification, see the VITA FMC Marketing Alliance website.
FMCP1 Connector J51
[Figure 3, callout 20] The HSPC connector J51 implements a subset of the full FMCP connectivity: · 68 single-ended or 34 differential user-defined pairs (34 LA pairs: LA[00:33]) · 12 transceiver differential pairs · 3 transceiver differential clocks · 2 differential clocks · 239 ground and 15 power connections
FMCP2 Connector J53
[Figure 3, callout 20] The HSPC connector J53 implements a subset of the full FMCP connectivity: · 68 single-ended or 34 differential user-defined pairs (34 LA pairs: LA[00:33]) · 12 transceiver differential pairs · 3 transceiver differential clocks · 2 differential clocks · 1 differential (REFCLK) clock C2M pair · 1 differential (SYNC) clock C2M pair · 239 ground and 15 power connections See the FPGA Mezzanine Card (FMC) VITA 57.4 specification for additional information on the FMCP HSPC connector. The detailed ACAP connections for the feature described in this section are documented in the VCK190 board XDC file, referenced in Appendix B: Xilinx Design Constraints.
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VADJ_FMC Power Rail
The VCK190 evaluation board implements the ANSI/VITA 57.4 IPMI support functionality. The power control of the VADJ_FMC power rail is managed by the ZU4 U125 System Controller. This rail powers both FMCP HSPC J51 and J53 VADJ pins, as well as the XCVC1902 U1 VCCO on the FMCP interface banks 706, 707, and 708. The valid values of the VADJ_FMC rail are 0, 1.2V, or 1.5V. At power on, the System Controller detects if an FMC module is installed on J51 or J53. The following sequence of actions then take place:
· If no card is attached to a FMCP connector, the VADJ_FMC voltage is set to 1.5V · When an FMC card is attached, its IIC EEPROM is read to find a VADJ voltage supported by
both the VCK190 board and the FMC module, within the available choices of 0, 1.2V, or 1.5V · If no valid information is found in an attached FMC card IIC EEPROM, the VADJ_FMC rail is
set to 0.0V
The System Controller user interface allows the FMC IPMI routine to be overridden and an explicit value can be set for the VADJ_FMC rail. The override mode is useful for FMC mezzanine cards that do not contain valid IPMI EPROM data defined by the ANSI/VITA 57.4 specification.
User I/O
[Figure 3, callout 22 and 23]
The VCK190 board provides these GPIO bank 306 user and general purpose I/O capabilities:
· Four user LEDs (callout 22) GPIO_LED[0:3]: DS6, DS5, DS4, DS3
· 4-position user DIP switch (callout 23) GPIO_DIP_SW[0:3]: SW6
· Two user pushbuttons and CPU reset switch (callouts 24 and 25) GPIO_PB[0:1]: SW4, SW5
The detailed ACAP connections for the feature described in this section are documented in the VCK190 board XDC file, referenced in Appendix B: Xilinx Design Constraints.
Power and Status LEDs
[Figure 3, callout 29]
The following table defines the power and status LEDs. For user-controlled GPIO LED details, see User I/O.
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Table 20: Power and Status LEDs
Ref. Des.
DS1 DS2
Schematic Net Name
DONE PS_ERR_OUT
DS3 DS4 DS5 DS6 DS9 DS10 DS11 DS12 DS13 DS14 DS15 DS16 DS17 DS19 DS20 DS21 DS22 DS23 DS24 DS26 DS27 DS28 DS29 DS30 DS32 DS33 DS34 DS35 DS36 DS37 DS39
GPIO_LED_3 GPIO_LED_2 GPIO_LED_1 GPIO_LED_0 VCCINT_PGOOD VCC_SOC_PGOOD VCC_PMC_PGOOD VCC_RAM_IO_PGOOD VCC_PSLP_PGOOD VCC_PSFP_PGOOD VCCAUX_PMC_PGOOD VCCAUX_PGOOD DIMM1_VTERM_0V60_PGOOD UTIL_3V3_PGOOD VCCO_MIO_PGOOD VCC3V3_PGOOD VCC1V8_PGOOD VCC1V2_DDR4_PGOOD VCC1V1_LP4_PGOOD VADJ_FMC_PGOOD MGTYAVTT_PGOOD MGTYAVCC_PGOOD UTIL_1V13_PGOOD MGTYVCCAUX_PGOOD UTIL_2V5_PGOOD SYSCTLR_INIT_B SYSCTLR_DONE SYSCTLR_ETH_WOL VCC12_SW USB3320 ERROR MAX8869 RST_B
LED Color
Green Red
Green Green Green Green Green Green Green Green Green Green Green Green Green Green Green Green Green Green Green Green Green Green Green Green Green
Red Green Green Green
Red Green
Description
ACAP U1 bit file download is complete PS_ERR_OUT is asserted for accidental loss of power, an error in the PMU that holds the CSU in reset, or an exception in the PMU USER GPIO LED USER GPIO LED USER GPIO LED USER GPIO LED VCCINT 0.80 VDC power on VCC_SOC 0.80V power on VCC_PMC 0.80V power on VCC_RAM_IO 0.80V power on VCC_PSLP 0.80V power on VCC_PSFP 0.80V power on VCCAUX_PMC 1.5 VDC power on VCCAUX 1.5 VDC power on DDR4 DIMM VTERM 0.6 VDC power on UTIL_3V3 3.3 VDC power on VCCO_MIO 1.8 VDC power on VCC3V3 3.3 VDC power on VCC1V8 1.8 VDC power on VCC1V2_DDR4 1.2 VDC power on VCC1V1_LP4 1.1 VDC power on VADJ_FMC 1.5V (Nom.) power on MGTYAVTT 1.2 VDC power on MGTYAVCC 0.88 VDC power on UTIL_1V13 1.13 VDC power on MGTVCCAUX 1.5 VDC power on UTIL_2V5 2.5 VDC power on
12 VDC power on
GEM0/1 VDDA1P0 is 8% or lower
The following figure shows the board's power good LEDs.
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Figure 23: Power Good Indicator LEDs
X24955-121420
Cooling Fan Connector
[Figure 3, callout 34] The VCK190 cooling fan connector is shown in the following figure. The VCK190 uses the Maxim MAX6643 (U64) fan controller, which autonomously controls the fan speed by controlling the pulse width modulation (PWM) signal to the fan based on the die temperature sensed via the ACAP's DXP and DXN pins. The fan rotates slowly (acoustically quiet) when ACAP U1 is cool and rotates faster as the ACAP heats up (acoustically noisy). The fan speed (PWM) versus the ACAP die temperature algorithm along with the over temperature set point and fan failure alarm mechanisms are defined by the strapping resistors on the MAX6643 device. The over temperature and fan failures alarms can be monitored either by any available processor in ACAP U1 by polling the I2C expander U233 on the I2C bus or via the ZU4 U125 System Controller. The VCK190 board provides a fan controller bypass header J234 to permit the fan to be always on. Always on (J234 pins 2 and 3 jumpered) is the default jumper setting shown in the figure. Note: When J234 pins 1 and 2 are jumpered to enable fan controller functionality, at initial board power on it is normal for the fan controller to energize the fan at full speed for a few seconds.
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Chapter 3: Board Component Descriptions Figure 24: 12V Fan Header
X24956-121420
System Controller
[Figure 3, callout 48]
The VCK190 board includes an onboard System Controller. A host PC resident system controller board user interface application is provided on the VCK190 evaluation board website. This board user interface application enables the query and control of select programmable features such as clocks, FMC functionality, and power system parameters. The VCK190 website also includes a tutorial on the board user interface application and board setup instructions.
A brief summary of these instructions is provided here.
1. Ensure the Silicon Labs VCP USB-UART drivers are installed. See the Silicon Labs CP210x USB-to-UART Installation Guide (UG1033).
2. Download the board user interface host PC application from the VCK190 evaluation board website.
3. Connect a USB cable to VCK190 USB-UART USB-C connector (J207). 4. Power-cycle the VCK190. 5. Launch the board user interface application.
The board user interface application UI is shown in the following figure.
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Chapter 3: Board Component Descriptions Figure 25: System Controller User Interface
On first use of the SCUI, select FMCSet VADJBoot-up tab and click USE FMC EEPROM Voltage. The SCUI buttons gray out during command execution and return to their original appearance when ready to accept a new command.
See the VCK190 Software Install and VCK190 Board Setup Tutorial (XTP619) and the System Controller Tutorial (XTP618) (which includes instructions for changing VCK190 clocks) for more information on installing and using the system controller UI.
Switches
[Figure 3, callout 6 and 30]
The VCK190 board includes power and configuration switches:
· SW13 power on/off slide switch · SW1 U1 ACAP PS bank 503 4-pole mode DIP switch
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Chapter 3: Board Component Descriptions
Power On/Off Slide Switch
[Figure 3, callout 30] The VCK190 board power switch is SW13. Sliding the switch actuator from the off to the on position applies 12VDC power from either the 2x3 6-pin Mini-Fit power input connector J16 (power from an external 120VAC-to-12VDC power adapter) or the 2x4 8-pin ATX power supply PCIe-type connector JP1.
IMPORTANT! Power to the VCK190 is mutually exclusive and only one of the two power connectors J16 or JP1 should be used to provide board power. The green LED DS36 illuminates when the VCK190 board power switch is on. See Board Power System for details on the onboard power system. CAUTION! Do NOT plug a PC ATX power supply 6-pin connector into the VCK190 board power connector J16. The ATX 6-pin connector has a different pinout than J16. Connecting an ATX 6-pin connector into J16 damages the VCK190 board and voids the board warranty. The following figure shows the power connector J16, power switch SW13, and LED indicator DS36.
Figure 26: Power Input
Board Power System
[Figure 3, callout 27]
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Chapter 3: Board Component Descriptions
The VCK190 evaluation board uses power management ICs (PMIC) and power regulators from Infineon Integrated Circuits to supply the core and auxiliary voltages listed in the following tables. See schematic 038-05005-01.
Table 21: Power System - PMBus Regulators and INA226 Map
Schematic Page
Rail Name
PMBus Regulators and INA226 Map
Regulator Type
U#
Vout (V)
57
VCCINT VCC_SOC
IR35215 PMIC (6 Phase)
U152
0.80 0.80
VCC_PSLP
0.80
VCC_PSFP
0.80
61
VCCAUX
IRPS5401 (4 Phase + LDO)
U160
1.5
VCC_RAM_IO
0.80
VCCINT_PMC
0.80
VCCO_MIO
1.8
63
VCC3V3 VCC1V8
IRPS5401 (4 Phase + LDO)
U167
3.3 1.8
VCCAUX_PMC
1.5
UTIL_1V13
1.13
UTIL_2V5
2.5
65
VCC1V2_DDR4
IRPS5401 (4 Phase + LDO)
U175
1.2
VCC1V1_LP4
1.1
MGTYVCCAUX
1.5
69
VADJ_FMC
IR38164
U185
1.5
70
MGTYAVCC
IR38164
U187
0.88
71
MGTYAVTT
IR38164
U189
1.2
Iout (A)
190 18 1 2 3 4 0.5 2 0.5 6 0.5 1 1 4 4 0.5 10 6 10
I2C Address
0x16
0x17
0x1C
0x1D 0x1E 0x1F 0x20
INA226 U#
INA226 I2C
Address
PMBUS1(1), PMBUS2(2)
U65
0x40(1)
U161 0x41(1)
U165 0x44(1)
U164 0x45(1)
U166 0x40(2)
U162 0x43(1)
U163 0x42(1)
U172 0x45(2)
U174 0x47(2)
U173 0x46(2)
U168 0x41(2)
NA
NA
NA
NA
U176 0x48(2)
U177 0x49(2)
U234 0x4D(2)
U184 0x4A(2)
U186 0x4B(2)
U188 0x4C(2)
RECOMMENDED: To ensure reliable operation, Xilinx recommends running the report_power command in the Vivado tools for designs targeting this board. The reported rail current requirements should do not exceed the values listed in the following table.
The total device power should remain under 125W. To assist the Vivado tools in reporting when power exceeds this amount, add this XDC constraint:
set_operating_conditions-design_power_budget 125 ;# (125W max power)
Table 22: Device Rail Maximum Current
VCCINT
Device Rail
Maximum Current (Amps)
190
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Table 22: Device Rail Maximum Current (cont'd)
Device Rail
VCC_SOC + VCC_IO VCC_PSLP VCC_PSFP VCCAUX VCC_RAM VCC_PMC VCCAUX_PMC MGTYVCCAUX MGTYAVCC MGTYAVTT VCCO 3.3V VCCO 1.5V* (assuming VADJ_FMC programmed to 1.5V) VCCO 1.1V VCCO 1.8V + VCCO_501 + VCCO_502 + VCCO_503
Maximum Current (Amps)
18 1 2 1.5 4 0.5 0.5 0.5 6 10 0.5 10
4 2
Table 23: Power System - Non-PMBus Regulators and INA226 Map
Schematic Page 72 73 74 102
103
Rail Name
DIMM1_VTERM UTIL_3V3 UTIL_5V0
SYS_VCC0V85 SYS_VCC1V8 SYS_VCC1V1 SYS_MGTAVCC SYS_VCC1V2
Non-PMBus Regulators and INA226 Map
Regulator Type
U#
Vout (V)
IR3897
U80
0.6
IR3889
U190
3.3
IR3889
U191
5
TPS62480RNCR
U143
0.85
TPS62097RWKR
U144
1.8
TPS7A8300ARGRR
U145
1.1
TPS62097RWKR
U146
0.9
TPS62097RWKR
U147
1.2
Iout (A)
4 22 15 6 2 2 2 2
I2C Address
NA NA NA NA NA NA NA NA
INA226 U#
NA NA NA NA NA NA NA NA
INA226 I2C
Address NA NA NA NA NA NA NA NA
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Chapter 3: Board Component Descriptions
Table 23: Power System - Non-PMBus Regulators and INA226 Map (cont'd)
Non-PMBus Regulators and INA226 Map
8A34001_VCC_GPI O_DC
LP38798SD-ADJ/NOPB
U223
3.3
0.8
NA
NA
NA
8A34001_VDDA LP38798SD-ADJ/NOPB
U225
8A34001_VDDO_Q1 _10_7
LP38798SD-ADJ/NOPB
U226
8A34001_VDD_CLK 0
LP38798SD-ADJ/NOPB
U227
106
8A34001_VDDO_Q0 _9_6
LP38798SD-ADJ/NOPB
U228
3.3
0.8
NA
NA
NA
3.3
0.8
NA
NA
NA
3.3
0.8
NA
NA
NA
3.3
0.8
NA
NA
NA
8A34001_VDD_CLK 1
LP38798SD-ADJ/NOPB
U229
3.3
0.8
NA
NA
NA
8A34001_VDDO_Q2 _4_11
LP38798SD-ADJ/NOPB
U230
3.3
0.8
NA
NA
NA
8A34001_VDDO_Q8 _3_5
LP38798SD-ADJ/NOPB
U236
3.3
0.8
NA
NA
NA
8A34001_VDD_FOD LP38798SD-ADJ/NOPB
U231
107
8A34001_VDDD LP38798SD-ADJ/NOPB
U232
1.8
0.8
NA
NA
NA
1.8
0.8
NA
NA
NA
More information about the power system regulator components can be found at the Infineon Integrated Circuits website.
The FMCP HSPC (J51 and J53) VADJ pins are wired to the programmable rail VADJ_FMC. The VADJ_FMC rail is programmed to 1.50V by default. The VADJ_FMC rail also powers the XCVC1902 FMCP interface banks 706, 707, and 708 (see the table in I/O Voltage Rails). Documentation describing PMBus programming for the Infineon power controllers is available at the Infineon Integrated Circuits website. The PCB layout and power system design meet the recommended criteria described in the Versal ACAP PCB Design User Guide (UG863).
Monitoring Voltage and Current
Twenty rails have a TI INA226 PMBus power monitor circuit with connections to the rail series current sense resistor. This arrangement permits the INA226 to report the sensed parameters separately on the PMBus. The rails equipped with the INA226 power monitors are shown in the power system table in Board Power System.
As described in PMC MIO[46:47] I2C0 Bus, the I2C0 bus provides access to the PMBus power controllers and the INA226 power monitors via the U33 TCA9548A bus switch. All PMBus controlled Infineon regulators are tied to the PMBUS_SDA/SCL PMBus, while the INA226 power monitors are split across PMBUS1_INA226_SDA/SCL and PMBUS2_INA226_SDA/SCL.
The I2C0 bus topology figure and I2C0 port expander TCA6416A U233 address 0x20 connections table in PMC MIO[46:47] I2C0 Bus document the I2C0 bus access path to the Infineon PMBus controllers and INA226 power monitor op amps. Also, see schematic 038-05005-01. These power system components are also accessible to the ZU4 U125 system controller (bank 501) and the ACAP U1 (bank 501).
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Appendix A: VITA 57.4 FMCP Connector Pinouts
Appendix A
VITA 57.4 FMCP Connector Pinouts
Overview
The following figure shows the pinout of the FPGA plus mezzanine card (FMCP) high pin count (HSPC) connector defined by the VITA 57.4 FMC specification. For a description of how the VCK190 evaluation board implements the FMCP specification, see FPGA Mezzanine Card Interface.
Figure 27: FMCP HSPC Connector Pinout
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Appendix B: Xilinx Design Constraints
Appendix B
Xilinx Design Constraints
Overview
The Xilinx® design constraints (XDC) file template for the VCK190 board provides for designs targeting the VCK190 evaluation board. Net names in the constraints listed correlate with net names on the latest VCK190 evaluation board schematic. Identify the appropriate pins and replace the net names with net names in the user RTL. See the Vivado Design Suite User Guide: Using Constraints (UG903) for more information. The HSPC FMCP connectors J51 and J53 are connected to ACAP U1 banks powered by the variable voltage VADJ_FMC. Because different FMC cards implement different circuitry, the FMC bank I/O standards must be uniquely defined by each customer.
IMPORTANT! See the VCK 190 board documentation ("Board Files" check box) for the XDC file.
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Appendix C: Pmod FMC
Appendix C
Pmod FMC
The Pmod FMC-XM119 board is for accessing Pmod standard devices or general purpose I/O from the base development board. The Pmod standard uses 100 mil space, 25 mil square, and pin header style connectors. The following figure shows a basic block diagram of the main components on the Pmod FMC. The basic function of this board is to provide a Pmod compatible standard connected to the PL I/O of the VersalTM ACAP. For more information, see the Digilent Pmod Interface Specification.
Figure 28: Pmod FMC Block Diagram
3.3 V Level Shifters
FMC+
Pmod Connectors
Pmod1 Pmod2 Pmod3
Level Shifter Level Shifter Level Shifter
1.5V I/O (Versal ACAP)
XX2244776655--110022662200
The FMC-XM119 board provides three Pmod 12 pin connectors. There are voltage level translators on the I/O side from the ACAP because of voltage compatibility with the bank fixed voltages. See the Versal ACAP SelectIO Resources Architecture Manual (AM010) for details on bank voltages.
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Appendix C: Pmod FMC
The voltage translators shown in the figure are the TXS0108E 8-bit bidirectional level shifter voltage translators for open drain and push-pull applications. The input voltage for the I/O to the level translator is controlled from the VADJ, which operates in the range of 1.5V to 3.3V. With the Versal ACAP, the I/O voltage on the XPIO (which is the primary I/O of the FMC) is a maximum of 1.5V, so the default setting for using this FMC Pmod card is VADJ = 1.5V on the XPIO I/O. On the output side of the level translator, this is converted to a 3.3V signal because the Pmod specification is at 3.3V. 5V is also supported per the Pmod specification, but this voltage is not supported without modification to the output power supplies of the level translator, which are fixed at 3.3V for the XM119 FMC board.
Figure 29: TXS0108E Bidirectional Voltage Level Translator
X24766-102620
Note: This level translator was specifically chosen to allow bidirectional signaling at lower frequencies, such as for I2C. The Pmod board is generic and can work with both the VCK190 and VMK180 development kits. The pinouts are identical between the boards, and usage should be straightforward.
Pin Mapping Pmod to FMC
The pin mapping is straightforward. The ACAP pins are connected to the input to the level translators, which map to the output pins on the Pmod connector at 3.3V. See Figure 29 for details.
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Appendix C: Pmod FMC
Figure 30: Pmod FMC Pin Mapping
X24767-102620
This pin mapping can translate between the VCK190 and VMK180 boards. There is no difference in pin mapping. The signal voltage is controlled by the VADJ, which is set by the system controller. The default is 1.5V for VADJ and this should never be changed. This must match the I/O standard voltage, otherwise it is possible to cause damage to the I/O. The I/O standard used is typically SSTL15 (see Figure 29), but any 1.5V standard can be used for Pmod compliance. The TXS0108E level translator has a minimum signal voltage of 1.4V, which means only 1.5V I/O standards can be used with this PMOD FMC board.
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Appendix D: Regulatory and Compliance Information
Appendix D
Regulatory and Compliance Information
This product is designed and tested to conform to the European Union directives and standards described in this section.
For Technical Support, open a Support Service Request.
CE Information
CE Directives 2006/95/EC, Low Voltage Directive (LVD) 2004/108/EC, Electromagnetic Compatibility (EMC) Directive
CE Standards EN standards are maintained by the European Committee for Electrotechnical Standardization (CENELEC). IEC standards are maintained by the International Electrotechnical Commission (IEC).
CE Electromagnetic Compatibility EN 55022:2010, Information Technology Equipment Radio Disturbance Characteristics Limits and Methods of Measurement EN 55024:2010, Information Technology Equipment Immunity Characteristics Limits and Methods of Measurement This is a Class A product. In a domestic environment, this product can cause radio interference, in which case the user might be required to take adequate measures.
CE Safety IEC 60950-1:2005, Information technology equipment Safety, Part 1: General requirements EN 60950-1:2006, Information technology equipment Safety, Part 1: General requirements
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Appendix D: Regulatory and Compliance Information
Compliance Markings
In August of 2005, the European Union (EU) implemented the EU Waste Electrical and Electronic Equipment (WEEE) Directive 2002/96/EC and later the WEEE Recast Directive 2012/19/EU. These directives require Producers of electronic and electrical equipment (EEE) to manage and finance the collection, reuse, recycling and to appropriately treat WEEE that the Producer places on the EU market after August 13, 2005. The goal of this directive is to minimize the volume of electrical and electronic waste disposal and to encourage re-use and recycling at the end of life. Xilinx has met its national obligations to the EU WEEE Directive by registering in those countries to which Xilinx is an importer. Xilinx has also elected to join WEEE Compliance Schemes in some countries to help manage customer returns at end-of-life. If you have purchased Xilinx-branded electrical or electronic products in the EU and are intending to discard these products at the end of their useful life, please do not dispose of them with your other household or municipal waste. Xilinx has labeled its branded electronic products with the WEEE Symbol to alert our customers that products bearing this label should not be disposed of in a landfill or with municipal or household waste in the EU.
This product complies with Directive 2002/95/EC on the restriction of hazardous substances (RoHS) in electrical and electronic equipment.
This product complies with CE Directives 2006/95/EC, Low Voltage Directive (LVD) and 2004/108/EC, Electromagnetic Compatibility (EMC) Directive.
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Appendix E: Additional Resources and Legal Notices
Appendix E
Additional Resources and Legal Notices
Xilinx Resources
For support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx Support.
Documentation Navigator and Design Hubs
Xilinx® Documentation Navigator (DocNav) provides access to Xilinx documents, videos, and support resources, which you can filter and search to find information. To open DocNav: · From the Vivado® IDE, select HelpDocumentation and Tutorials. · On Windows, select StartAll ProgramsXilinx Design ToolsDocNav. · At the Linux command prompt, enter docnav. Xilinx Design Hubs provide links to documentation organized by design tasks and other topics, which you can use to learn key concepts and address frequently asked questions. To access the Design Hubs: · In DocNav, click the Design Hubs View tab. · On the Xilinx website, see the Design Hubs page. Note: For more information on DocNav, see the Documentation Navigator page on the Xilinx website.
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Appendix E: Additional Resources and Legal Notices
References
The most up to date information related to the VCK190 board and its documentation is available on these websites:
VCK190 Evaluation Kit
VCK190 Evaluation Kit -- Master Answer Record 72739
These documents provide supplemental material useful with this guide:
1. Versal Architecture and Product Data Sheet: Overview (DS950) 2. Versal Prime Series Data Sheet: DC and AC Switching Characteristics (DS956) 3. Versal ACAP Technical Reference Manual (AM011) 4. Versal ACAP SelectIO Resources Architecture Manual (AM010) 5. Versal ACAP PCB Design User Guide (UG863) 6. Versal ACAP Memory Resources Architecture Manual (AM007) 7. Versal ACAP GTY Transceivers Architecture Manual (AM002) 8. Tera Term Terminal Emulator Installation Guide (UG1036) 9. Vivado Design Suite User Guide: Using Constraints (UG903) 10. Vivado Design Suite User Guide: Programming and Debugging (UG908) 11. Versal ACAP Integrated Block for PCI Express LogiCORE IP Product Guide (PG343) 12. Versal ACAP System Monitor Architecture Manual (AM006) 13. Versal ACAP Clocking Resources Architecture Manual (AM003) 14. HDMI 1.4/2.0 Transmitter Subsystem Product Guide (PG235) 15. HDMI Transmitter and Receiver Subsystem Answer Record 70514 16. Silicon Labs CP210x USB-to-UART Installation Guide (UG1033) 17. VCK190 Software Install and Board Setup Tutorial (XTP619) 18. VCK190 System Controller Tutorial (XTP618) 19. Micron Technology (MTA9ADF1G72AZ-3GE1, MT53D512M32D2DS) 20. Standard Microsystems Corporation (SMSC) (USB3320) 21. SanDisk Corporation 22. SD Association 23. Silicon Labs (SI570, SI5332, SI53340) 24. Texas Instruments (TCA9548A, TCA6416A, DP83867)
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Appendix E: Additional Resources and Legal Notices
25. PCI Express standard
26. Samtec, Inc. (SEAF series connectors, LPAF connectors)
27. VITA FMC Marketing Alliance (FPGA Mezzanine Card (FMC) VITA 57.1, 57.4 specifications)
28. Maxim Integrated Circuits (MAX6643)
29. Infineon Integrated Circuits (IR35215, IRPS5401, IR38164, IR3897)
30. Future Technology Devices International Ltd. (FT4232HL)
31. Integrated Device Technology, Inc. (IDT) (85411AMLF, 8T49N241, 8A34001)
32. SNIA Technology Affiliates (SFF-8431)
33. Nexperia/NXP Semiconductors (SC18IS602)
Please Read: Important Legal Notices
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Appendix E: Additional Resources and Legal Notices
AUTOMOTIVE APPLICATIONS DISCLAIMER
AUTOMOTIVE PRODUCTS (IDENTIFIED AS "XA" IN THE PART NUMBER) ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE ("SAFETY APPLICATION") UNLESS THERE IS A SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262 AUTOMOTIVE SAFETY STANDARD ("SAFETY DESIGN"). CUSTOMER SHALL, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TEST SUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION WITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY.
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© Copyright 2021 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. AMBA, AMBA Designer, Arm, ARM1176JZ-S, CoreSight, Cortex, PrimeCell, Mali, and MPCore are trademarks of Arm Limited in the EU and other countries. The DisplayPort Icon is a trademark of the Video Electronics Standards Association, registered in the U.S. and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. HDMI, HDMI logo, and High-Definition Multimedia Interface are trademarks of HDMI Licensing LLC. The USB-IF logos are trademarks of Universal Serial Bus Implementers Forum, Inc. All other trademarks are the property of their respective owners.
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