TPA3110D2: 15W Filter-Free Stereo Class-D Audio Power Amplifier with SpeakerGuard
Overview and Features
The Texas Instruments TPA3110D2 is a highly efficient, 15-W (per channel) Class-D audio power amplifier designed for driving bridged-tied stereo speakers. It offers advanced EMI suppression technology, allowing the use of inexpensive ferrite bead filters at the outputs while meeting EMC requirements. The amplifier features SpeakerGuard™ speaker protection, including an adjustable power limiter and a DC detection circuit. It can drive stereo speakers as low as 4 Ω and boasts 90% efficiency, eliminating the need for external heat sinks during typical music playback.
Key Features:
- 15-W/ch into 8-Ω Loads at 10% THD+N from a 16-V Supply
- 10-W/ch into 8-Ω Loads at 10% THD+N from a 13-V Supply
- 30-W into a 4-Ω Mono Load at 10% THD+N from a 16-V Supply
- 90% Efficient Class-D Operation
- Wide Supply Voltage Range: 8 V to 26 V
- Filter-Free Operation
- SpeakerGuard™ Speaker Protection (Adjustable Power Limiter, DC Protection)
- Robust Short Circuit and Thermal Protection with Auto-Recovery
- Excellent THD+N and Pop-Free Performance
- Four Selectable, Fixed Gain Settings
- Differential Inputs
Applications
- Televisions
- Consumer Audio Equipment
Description
The TPA3110D2 is a Class-D audio power amplifier optimized for driving stereo speakers. Its advanced EMI suppression technology enables the use of simple ferrite bead filters, meeting EMC standards. The integrated SpeakerGuard™ system provides adjustable power limiting and DC detection for speaker protection. The amplifier's high efficiency (90%) minimizes heat dissipation, often negating the need for an external heatsink. It also includes comprehensive protection against output shorts to GND, VCC, and output-to-output, along with thermal protection, all featuring auto-recovery.
Device Information
| Part Number | Package | Body Size (Nominal) |
|---|---|---|
| TPA3110D2 | HTSSOP (28) | 9.70 mm x 4.40 mm |
For all available packages, refer to the orderable addendum.
Simplified Application Schematic
Illustrates a typical stereo BTL application setup. It shows the TPA3110D2 IC connected to an audio source, with inputs (LINP, LINN, RINP, RINN), control pins (SD, FAULT, GAIN0, GAIN1, PLIMIT, PBTL), power supplies (PVCC, GVDD, AVCC), grounds (AGND, PGND), and outputs (OUTPL, OUTNL, OUTPR, OUTNR). A ferrite bead filter is shown in the output path. The schematic also indicates recommended external components like capacitors and resistors for filtering and power supply decoupling.
Pin Configuration and Functions
The TPA3110D2 is available in a 28-Pin HTSSOP package with a PowerPAD™.
| Pin No. | Name | Type | Description |
|---|---|---|---|
| 1 | SD | I | Shutdown logic input. TTL logic levels with compliance to AVCC. |
| 2 | FAULT | O | Open drain output indicating short circuit or DC detect fault status. |
| 3 | LINP | I | Positive audio input for left channel. Biased at 3 V. |
| 4 | LINN | I | Negative audio input for left channel. Biased at 3 V. |
| 5 | GAIN0 | I | Gain select LSB. TTL logic levels with compliance to AVCC. |
| 6 | GAIN1 | I | Gain select MSB. TTL logic levels with compliance to AVCC. |
| 7 | AVCC | P | Analog supply. |
| 8 | AGND | -- | Analog signal ground. Connect to the thermal pad. |
| 9 | GVDD | O | High-side FET gate drive supply (nominal 7V). Also used for PLIMIT function. |
| 10 | PLIMIT | I | Power limit level adjust. Connect a resistor divider from GVDD to GND to set power limit. |
| 11 | RINN | I | Negative audio input for right channel. Biased at 3 V. |
| 12 | RINP | I | Positive audio input for right channel. Biased at 3 V. |
| 13 | NC | -- | Not connected. |
| 14 | PBTL | I | Parallel BTL mode switch. |
| 15 | PVCCR | P | Power supply for right channel H-bridge. |
| 16 | PVCCR | P | Power supply for right channel H-bridge. |
| 17 | BSPR | I | Bootstrap I/O for right channel, positive high-side FET. |
| 18 | OUTPR | O | Class-D H-bridge positive output for right channel. |
| 19 | PGND | -- | Power ground for the H-bridges. |
| 20 | OUTNR | O | Class-D H-bridge negative output for right channel. |
| 21 | BSNR | I | Bootstrap I/O for right channel, negative high-side FET. |
| 22 | BSNL | I | Bootstrap I/O for left channel, negative high-side FET. |
| 23 | OUTNL | O | Class-D H-bridge negative output for left channel. |
| 24 | PGND | -- | Power ground for the H-bridges. |
| 25 | OUTPL | O | Class-D H-bridge positive output for left channel. |
| 26 | BSPL | I | Bootstrap I/O for left channel, positive high-side FET. |
| 27 | PVCCL | P | Power supply for left channel H-bridge. |
| 28 | PVCCL | P | Power supply for left channel H-bridge. |
Specifications
The datasheet provides detailed specifications including Absolute Maximum Ratings, Recommended Operating Conditions, ESD Ratings, Thermal Information, DC Characteristics, and AC Characteristics. These tables define the device's operational limits, performance parameters, and behavior under various conditions.
Absolute Maximum Ratings Summary:
- Supply Voltage (VCC): -0.3 V to 30 V
- Interface Pin Voltage: -0.3 V to VCC + 0.3 V (with slew rate limit)
- Operating Free-Air Temperature (TA): -40°C to 85°C
- Storage Temperature (Tstg): -65°C to 150°C
Recommended Operating Conditions Summary:
- Supply Voltage (VCC): 8 V to 26 V
- High-level Input Voltage (VIH): ≥ 2 V
- Low-level Input Voltage (VIL): ≤ 0.8 V
- Operating Free-Air Temperature (TA): -40°C to 85°C
Thermal Information Summary:
Key thermal resistances are provided, such as Junction-to-ambient thermal resistance (RJA) of 30.3 °C/W for the PWP (HTSSOP) 28-pin package.
Detailed Description
Modulation Scheme
The TPA3110D2 employs a modulation scheme that enables filter-free operation with inductive loads. It switches outputs between 0V and the supply voltage. The output voltage across the load is kept at 0V for most of the switching period, reducing switching current and I²R losses.
Ferrite Bead Filter Considerations
For EMI suppression, a ferrite bead filter is recommended. Careful selection of ferrite material is crucial for effectiveness in the 10-100 MHz range. The impedance of the ferrite bead, combined with a small capacitor (e.g., 1000 pF), helps reduce the signal's frequency spectrum. The document also discusses the importance of bead size for peak currents and suggests specific part numbers. Snubber networks can provide additional EMC improvements.
Gain Setting
The amplifier's gain is set via the GAIN0 and GAIN1 input pins. The input impedance varies with the gain setting, ranging from 9 kΩ to 60 kΩ. The slew rate of these pins, along with pins 1 and 14, should be limited to 10 V/ms, or a 100 kΩ series resistor should be used.
Differential Inputs
The differential input stage cancels noise present on both input lines. The device supports both differential and single-ended audio sources. For optimal transient performance, the impedance at both differential inputs should be matched.
PLIMIT (Power Limit)
The PLIMIT pin (pin 10) allows limiting the output power to levels below the maximum determined by the supply rail. A voltage at the PLIMIT pin, set by a resistor divider from GVDD, effectively creates a "virtual" voltage rail. This virtual rail is four times the PLIMIT pin voltage, and it helps calculate the maximum output power.
PBTL Select
The PBTL pin (pin 14) enables parallel BTL (mono) operation. When tied high, it synchronizes the left and right channel outputs. The input signal should be applied to the right channel, and the speaker connected between the left and right outputs. For normal BTL stereo operation, the PBTL pin should be connected to ground.
Protection Features
The TPA3110D2 includes several protection mechanisms:
- Thermal Protection: Prevents damage by shutting down the device when the internal die temperature exceeds 150°C. This is not a latched fault and recovers automatically when the temperature drops.
- DC Detect: Protects speakers from DC current caused by input capacitor faults or shorts. A DC detect fault is reported on the FAULT pin and causes a shutdown. Clearing requires cycling the PVCC supply.
- Short-Circuit Protection: Protects against output stage overcurrent conditions. The FAULT pin indicates the fault, and the outputs enter a Hi-Z state. The latch can be cleared by cycling the SD pin. Automatic recovery can be achieved by connecting FAULT to SD.
Device Functional Modes
The SD (Shutdown) pin controls a low-current standby mode for power conservation. Pulling SD low mutes outputs and enters low-current state. It should never be left unconnected. For best power-off pop performance, the device should be in shutdown mode before power is removed.
Application and Implementation
Stereo Class-D Amplifier with BTL Output and Single-Ended Inputs
This section presents a typical application schematic for a stereo BTL configuration with power limiting. It details component selection for input filtering, power supply decoupling, and output filtering, including recommended capacitor values and placement for optimal performance and noise reduction.
Mono PBTL Application
A separate schematic is provided for the mono PBTL configuration, where the Power Limiter is typically not used.
Design Procedure
Guidance is provided on selecting input capacitors (C1) to set the bass response, considering input resistance variations with gain. Recommendations are given for bootstrap capacitors (BSN, BSP) for the high-side gate drive, and the use of low-ESR capacitors is emphasized for optimal performance.
Power Supply Recommendations
The TPA3110D2 operates from an 8-V to 26-V supply. Adequate power supply decoupling is crucial for achieving low total harmonic distortion (THD). This involves using a network of capacitors targeting different noise frequencies. Recommendations include ceramic capacitors (220 pF - 1000 pF) placed close to PVCC pins for high-frequency noise, larger capacitors (0.1 µF - 1 µF) for mid-frequency noise, and electrolytic capacitors (220 µF or greater) for lower frequencies and transient current storage. A 10-µF capacitor is recommended for AVCC.
Layout Guidelines
Proper PCB layout is essential for meeting EMC requirements due to the fast switching edges of Class-D amplifiers. Key recommendations include:
- Placing high-frequency decoupling capacitors close to PVCC and AVCC terminals.
- Using short, tight current loops for outputs and filter components to minimize antenna effects.
- Grounding AVCC decoupling to analog ground (AGND) and PVCC decoupling to power ground (PGND), with a central connection at the thermal pad.
- Placing output filters (ferrite bead or LC) close to the output terminals.
- Soldering the thermal pad directly to the PCB for optimal thermal performance, using thermal vias to connect to a copper plane.
An example PCB layout is provided, illustrating the placement of decoupling capacitors, thermal pad connections, and ground planes.
Typical Characteristics
The datasheet includes extensive graphical data illustrating the TPA3110D2's performance across various operating conditions. These graphs cover key parameters such as:
- Distortion: Total Harmonic Distortion (THD) and Total Harmonic Distortion + Noise (THD+N) versus frequency and output power, under different supply voltages (VCC) and load impedances (ZL).
- Efficiency: Efficiency versus output power for various VCC and load configurations, both with and without LC filters.
- Power and Current: Maximum output power versus PLIMIT voltage, output power versus supply voltage (BTL and PBTL), and supply current versus total output power.
- Signal Integrity: Crosstalk versus frequency and Supply Ripple Rejection Ratio (KSVR) versus frequency.
- Frequency Response: Gain and Phase versus frequency.
These detailed plots provide critical insights for design and performance evaluation.
Device and Documentation Support
Texas Instruments offers various resources for the TPA3110D2:
- Development Support: TINA-TI Reference Design and TINA-TI Spice Model.
- Documentation Support: Application reports on topics like PowerPAD™ packages, thermal calculations, EMI management, power supply design, and EVM user guides.
- Community Resources: Access to the TI E2E™ Online Community for technical support and collaboration.
Mechanical, Packaging, and Orderable Information
This section details the mechanical dimensions, packaging options (HTSSOP with PowerPAD™), tape and reel information, and orderable part numbers. It also includes important notices and disclaimers regarding product usage and TI's liability.
