Index of /components/sgs/ dataBooks
DESIGNERS' GUIDE TO POWER PRODUCTS
APPLICATION MAN UAl
2nd EDITION
PRINTED ON RECYCLED PAPER
JUNE 1993
USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED
SGS-THOMSON PRODUCTS ARE NOT AUl'HORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF SGS-THOMSON Microelectronics. As used herein:
1. Life support devices or systems are those which (a) are intended for surgical implant into the body, or (b) supPort or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided with the product, can be reasonably expected to result in significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can reasonably be expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
TABLE OF CONTENTS
INTRODUCTION
Page 4
GENERAL INDEX
7
APPLICATION NOTES
TECHNOLOGY AND BASIC. . . . . . . . . . . . . . . . . . .. 11 SMART POWER DEVELOPMENT SYSTEM . . . . . . . . . .. 87 STEPPER MOTORS . . . . . . . . . . . . . . . . . . . . . . . 99 DC AND BRUSH LESS MOTORS . . . . . . . . . . . . . . . .. 205 DRIVERS AND INTELLIGENT POWER SWITCHES . . . . . .. 333 POWER SUPPLY . . . . . . . . . . . . . . . . . . . . . . . .. 393 POWER MOS AND IGBTs . . . . . . . . . . . . . . .. . . . .. 713 SCRs AND TRIACS . . . . . . . . . . . . . . . . . . . . . . .. 863 MONITOR AND TV CIRCUITS . . . . . . . . . . . . . . . . . . 993 THERMAL MANAGEMENT . . . . . . . . . . . . . . . . . . . . 1213
INTRODUCTION
THE BRIGHTER POWER This book has been written for those interested in taking advantage of the most recent advances in power integrated circuits. Smart power integrated circuits together with power discrete devices form the heart of modern power electronics. SGS-THOMSON is well established in the field of power electronics, both for power discretes and power integrated circuits. In particular, the company is a world leader in power integrated circuits. Ever since rankings were published for the fast-growing power IC and smart power IC markets SGS-THOMSON has been number one. Moreover, the company has a share almost twice that df the nearest competitor in both power IC markets. Our long term experience in bipolar discretes has led to reliable rugged devices using state-of-the-art bipolar structures and both single and double implanted planar edge termination techniques that meet today's demand for very high switching speeds and high breakdown voltages. These techniques are not confined to bipolar transistor fabrication. High voltage Power MOS using high efficiency edge structures and platinum ion implanted IGBTs use flexible processes that produce a range of rugged high voltage devices ideal for switch mode applications. SGS-THOMSON's leadership in power IC technology has its roots in its pioneering work at the end of the '60s, when the first ICs combining power circuits a.nd control circuits were first created. Initially this technology was used in applications such as audio amplifiers, voltage regulators and TV deflection circuits. Later it was extended to applications such as motor and solenoid driving.
Thanks to an advanced 2nd generation BCD smart power process, SGS-THOMSON integrates highly complex power subsystems on a single chip. This Ie, designed for a hard disk drive, controls and drives both the spindle motor and the head positioner. It includes more than 10,000 transistors.
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4
INTRODUCTION
In the early eighties another major step forward was taken when SGS-THOMSON introduced a new power IC technology that combined bipolar CMOS and DMOS power transistors on the same chip. Unlike other "smart power" technologies, this allowedthe integration of isolated DMOS transistors so any number could be placed on one chip and interconnected in any way. Recently a shrink version of this technology has been introduced. Thanks to 2.51lm geometries this version makes it possible to integrate very complex LSI power circuits on one chip. One example of the new generation is a single chip that controls and drives three motors in a fax machine. Another circuit drives the head positioning and spindle motor actuators of a 2.5" hard disk drive. This power IC, made with the 2nd generation BCD process, integrates highly complex power subsystems on a single chip. It includes more than 10,000 transistors. In addition to the BCD technology, VIPower ICs have been developed. These unique monolithic power ICs are based on discrete transistors with current flowing vertically through the silicon and have integrated control circuits constructed on-chip. Three sub-families of power ICs have been derived from this technology. Included in these sub-families are bipolar output ignition drivers rated at 450V, 8.5A and Power MOSFET output high-side drivers with an RDS(on) as low as 30mQ and V(BR)DSS of 60V and low-side drivers rated at 450V, 0.75Q. Because most SGS-THOMSON power ICs are innovative the company places great emphasis on application support. For many products there are sophisticated application development tools - hardware and software - for use with the lab PC. The company also regularly publishes application documentation. This volume is a follow-on from the Smart Power Application Manual, reflecting the broader scope of power electronics. It includes application notes and other useful material about SGS-THOMSON power ICs, power technologies and power discretes. SGS-THOMSON's innovative smart power processes are made to fit the needs of today. By providing complex functions in small, rugged and easy to use packages the task of system design is made easier and the system reliability is improved.
A variety of high voltage Power MOS in power packages to suit today's environments.
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GENERAL INDEX
TECHNOLOGY AND BASICS
Page
AN446 - Smart Power Processes for LSI Circuits ........................................ 13
AN447 - Smart Power Technology Evolves to Higher Levels of Complexity .................... 19
AN449 - New Levels of Integration in Automotive Electronics ............................... 25
AN471 - Smart Power Technologies for Powertrain & Body Electronics ....................... 35
AN451 - High-Current Motor Driver ICs Bring Automotive Multiplex Closer .................... 47
AN483 - Mixed Wire Bonding Technology for Automotive Smart Power ICs .................... 53
AN474 - How Design Rules Influence High-Frequency Switching Behaviour of Power Mosfets ..... 57
AN475 - Gate Charge Characteristics Lead to Easy Drive Design for Power MOSFet Circuits ..... 67
AN370 - Analysis and Optimisation of High Frequency Power Rectification .................... , 75
SMART POWER DEVELOPMENT SYSTEM
AN450 - PC Based Development System Cuts Design Time of Smart Power IC Applications. . . . . .. 89
STEPPER MOTORS
AN460 - Stepper Motor Drive Consideration, Common Problems & Solution
101
AN379 - Using the L6204,a Bipolar Stepper and DC Motors Driver in BCD Technology ........... 113
AN266 - Bipolar Stepper Motor Control ................................................ 121
AN279 - Short Circuit Protection on L6203 ............................................. 133
AN280 - Controlling Voltage Transients in Full Bridge Drivers Applications ..................... 137
AN234 - A High Efficiency, Mixed-Technology Motor Driver ................................. 145
AN235 - Stepper Motor Driving ...................................................... 151
AN468 - Constant-Current Chopper Drive Ups Stepper-Motor Perfomance .................... 167
AN469 - Using the L6506 for Current Control of Stepper Motors ............................ 173
AN238 - High Power, Dual Bridge ICs Ease Stepper Motor Driver Design ..................... 179
AN470 - The L297 Stepper Motor Controller ............................................ 187
DC AND BRUSHLESS MOTORS
AN457 - Twin-Loop Control Chip Cuts Cost of DC Motor Positioning ......................... 207 AN380 - How to Drive DC Motors with Smart Power ICs .................................. 215 AN452 - A Load Current Sensing in Switch-Mode Bridge Motor Driving Circuits ................. 231 AN454 - A Solid State Blinker for Automotive Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 237 AN455 - Rear Mirrors Multiplexing Using L9946 .......................................... 241 AN456 - 6A Door Lock Motor Driver for Automotive .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 249 AN281 - Driving DC Motors ......................................................... 255 AN240 - Applications of Monolithic Bridge Drivers ........................................ 263 AN241 - Speed Control of DC Motors with the L292 Switch-Mode Driver ...................... 273 AN242 - The L290-L291-L292 DC Speed/Position Control ................................. 281 AN282 - An Economic Motor Drive With Very few Components .............................. 305 AN424 - Versatile and Cost Effective Induction Motor Drive with Digital Three Phase Generation ... 309 AN481 - Motor Control Design using Vertical Smart Power ICs .............................. 323
7
GENERAL INDEX
DRIVERS AND INTELLIGENT POWER SWITCHES
Page
AN453 - How the TDE1897/98 Behave in Extreme Overload Conditions ........... "...... " ..... 335
AN243 - Switch-Mode Drivers for Solenoid Driving .... " .. " ... " .. " ..... " .. " ..... " ..... " ... 341
AN292 - Fully Protected High Voltage Interface For Electronic Ignition .. " ..................... 353
AN813 - Transistorized Power Switches with Improved Efficency ............................ 359
AN482 - Electronic Ignition with VB020 and L497 ........................................ 365
AN268 - Intelligent Autoprotected Drivers ........................................ ',' ..... 369
AN270 - Interfaces Dedicated to Processes Control ................. " ............ " ....... 379
AN271 - High-Side Monolithic Switch in Multipower-BCD Technology ......................... 385
POWER SUPPLY
AN458 - Designing with the L4963 Discontinuous Mode Power Switching Regulator ............. 395 AN487 - Introduction to a 10A Monolithic Switching Regulator in Multipower-BCD Technology ...... 413 AN364 - Switch-Mode Base Driver Circuit with the L4974 Smart Power IC ..................... 425 AN433 - Ultra Fast Nica Battery Charging using ST621 0 Microcontroller ..................".... 429 AN244 - Designing with the L296 Power Switching Regulator .............................. 435 AN245 - Designing Multiple-Output Power Supplies with the L296 and L4960 .................. 477 AN246 - UC3842 Provides Low-Cost Current-Mode Control ................................ 487 AN247 - A 25W Off-Line Flyback Switching Regulator . " ................................... 503 AN362 - Flexible Low Cost High Efficiency 130W SMPS using SGSD00055 and TEA2018A ....... 509 AN250 - A Second-Generation IC Switch Mode Controller Optimized for High Frequency
PowerMOS Drive .......................................................... 515 AN352 - 200kHz 15W Push-Pull DC/DC Converter ....................................... 527 AN357 - High-Voltage Transistors with PowerMOS Emitter Switching ......................... 533 AN361 - A Transistor for a 100kHz Converter: ETD ....................................... 539 AN366 - An Innovative High Frequency High Current Transistor Chopper ...................... 547 AN367 - A Power Stage for a 20kHz, 10 KW Switched Mode Power Supply for the Industrial
380/440V Mains .............. " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 555 AN368 - Power Semiconductors for High Frequency AD/DC Converters Supplied on the
380/440V Mains ......................................................... " 565 AN369 - Optimized Power Stages for High Frequency 380/440V Medium Power Switch
Mode Supplies ............................................................. 571 AN376 - TEA2260/61 High Performance Driver Circuits for SMPS " .......................... 579 AN406 - TEA20'18A/19 Flyback Switch-Mode Power Supply Implementation .......... , ........ 613 AN389 - An Automatic Line Voltage Switching Circuit , .. , .. , ............................... 651 AN390 - How to Use the AVS Kit ..................................................... 657 AN253 - Power Suppy Design Basics .................................................. 661 AN290 - Very L~w-Drop Regulators Enhance Supply Performance .......................... 667 AN255 - A Designers Guide to the L200 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . · . . . . .. 677 AN256 - Dual Regulators Simplify Micro System Suppy Design ... ; .......... , .............. 697 AN254 - Low-Drop Voltage Regulators for Automotive Electronics , .......................... 705
8
GENERAL INDEX
POWER MOS AND IGBTs
Page
AN476 - Safe Behavior of IGBTs Subjected to dV/dt ...................................... 715
AN477 - Static and Dynamic Behavior of Parallel IGBTs .............. , .................... 725
AN478 - How Short Circuit Capabilities Govern the Desired Characteristics of IGBTs ............. 739
AN479 - Switching with IGBTs: How to Obtain Better Performance ........................... 749
AN480 - Series Connection of MOSFET, Bipolar and IGBT Devices .......................... 759
AN351 - Novel Protection and Gate Drives for MOSFETs used in Dridge-Leg Configuration ....... 771
AN356 - Use of the Internal MOSFET Diode in Bridge-Legs for High Frequency Applications ...... 777
AN358 - Environment Design Rules of MOSFET in Medium Power Application ................. 787
AN359 - Compact High Performance Brush DC Motor Servo Drives using MOSFETs ............ 797
AN463 - Switching with MOSFETs and IGBTs: from 50Hz to 200kHz ......................... 807
AN464 - Insulated Gate Bipolar Transistors in HF Resonant Converters ....................... 825
AN465 - Bipolar Junction Transistors Power MOSFETs or IGBTs in Resonant Converters ......... 837
AN466 - Analysis of Losses in IGBTs .................................................. 849
AN461 - A New Isolated Gate Drive for Power MOSFETs and IGBTs ......................... 857
SCRs AND TRIACs
AN301 - The TRIAC ............................................................... 865 AN302 - Thyristors and Triacs, An Important Parameter: The Holding Current .................. 887 AN303 - Thyristors and Triacs, An Important Parameter: Latching Current ..................... 893 AN306 - Design of a Static Relay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 903 AN307 - Use of a Triacs on Inductive Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 907 AN308 - Control by a Triac for an Inductive Load: How to Select a Suitable.Circuit ............... 913 AN328 - Protect your Triacs ............................ : ............................ 925 AN392 - Power Control with ST621 0 MCU and Triac ...................................... 929 AN436 - Triac Control by Pulse Transformer ............................................ 939 AN437 - New Triacs : is the Snubber Circuit Necessary? ................................... 945 AN438 - Triacs + Microcontroller Safety Precautions for Development Tool ..................... 953 AN439 - Inprovement in the Triac Commutation .......................................... 957 AN440 - Triac Drive Circuit for Operation in Quadrants I and III .............................. 967 AN441 - Triacs for Microwave Oven ................................................... 973 AN442 -.Triacs and Microcontrollers: The Easy Connection ................................. 981 AN443 - Series Operation of Fast Rectifiers ...................... '....................... 983 AN444 - Transistor Protection by Transil: Dissipation Power and Surge Current Duration .......... 991
9
GENERAL INDEX
MONITOR AND TV CIRCUITS
Page
AN373 - Vertical Deflection Circuits for TV & Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .. 995
AN374 - TDA81 02A HorizontallVertical Processor for TIL - VDU ........................... 1019
AN377 - TEA5101A - RGB High Voltage Video Amplifier Basic Operation and Applications ....... 1035
AN393 - TV EIW Correction Circuits .................................................. 1059
AN407 - TEA2028fTEA2029 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1095
AN408 - TEA5170 Secondary Controller for Master - Slave Structure . . . . . . . . . . . . . . . . . . . . . . .. 1151
AN409 - TEA2164 Master-Slave SMPS for TV Video Applications. . . . . . . . . . . . . . . . . . . . . . . . . .. 1165
AN410 - TEA2037 Horizontal & Vertical Deflection Circuit .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1195
THERMAL MANAGEMENT
AN467 - The Powerdip ( 16+2+2, 12+3+3) Packages .................................... 1215 AN261 - Designing with Thermal Impedance . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. 1229 AN262 - Thermal Management in Surface Mounting ..................................... 1243 AN257 - Thermal Characteristics of the Multiwatt Package ................................ 1257 AN258 - Thermal Characteristics of the Pentawatt-Heptawatt Packages . . . . . . . . . . . . . . . . . . . . .. 1265 AN264 - Resistance to Soldering Heat and Thermal Characteristics of Plastic SMDS . . . . . . . . . . .. 1273 AN260 - Handling and Mounting ICs in Plastic Power Packages ............................ 1283 AN314 - T0220AB-T03-TOPLESS: Thermal Resistance and Mechanical Assembly ............ 1287
10
TECHNOLOGY AND BASICS
11
APPLICATION NOTE
SMART POWER PROCESSES FOR LSI CIRCUITS
by Carlo Cini
Over the years smart power technology has advanced to ever-increasing power and voltage le-
vels. At the same time, almost unnoticed there has been a remarkable increase in the smartness
of circuits -- the amount of complexity that can be integrated practically on one chip.
Today, for example, it is possible to integrate circuits like the one shown in figure 1, which contains two 1A motor drives, a 3A solenoid driver, a 1A switchmode power supply and a micro interface (this chip will be described in more detail later). Clearly the possibility of integrating so much of a system has a dramatic effect on the way system engineers approach partitioning; complexity is no longer limited by technology, but by economic factors.
The technologies that allow such circuits to be made are generally known as "BCD" technologies because they combine bipolar, CMOS and DMOS process structures. First introduced by SGS in 1986, they allow IC designers to use bipolar components when high precision is needed (in references etc), CMOS for high density digital and analog, and power DMOS for low dissipation output stages.
Low dissipation is, in fact, one of the key advan-
tages of BCD technology. A DMOS powertransistor in switchmode operation dissipates very little power so it is possible to deliver high power to the load without expensive power packaging and cooling systems (the power that can be dissipated inside an IC is determined by the package). Equally important is the fact that low dissipation power stages make it feasible to place several power stages on the same chip. This, together with the high density CMOS, makes high complexity circuits feasible.
BCD TECHNOLOGY
The first commercial process to combine bipolar, CMOS and power DMOS was the MultipowerBCD process introduced by SGS-THOMSON in 1986. A 60V technology, this was created by merging vertical DMOS technology with a conventional junction-isolated bipolar IC process (figure 2).
Figure 1: A High Complexity Smart Power IC Containing Multiple Drivers.
AN446/0392
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13
APPLICATION NOTE
Figure 2: Cross Section of the Multipower-BCD Process.
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NPN
LPNP
An important characteristic of this technology is
that it provided all of the contacts on the top surface of the die and completely isolated the pow~r DMOS transistors. This was important because It allowed the integration of any kind of power stage: high side, low side, half bridge or bri~ge. Moreover, multiple power stages could be Integrated on one chip.
Having bipolar, CMOS and DMOS structures
available gives the designer freedom to choo~e
the most appropriate for each P?rt o.f th~ CI.rCUIt.
Bipolar structures are used primarily In linear
functions where high precision is needed: low o~f
sets low drift and predriving stages.
so on; CMOS
it can also be is useful both
ufsoer fuhli~Inh
density logic and high density analog Circuits
where high precision is not needed.
DMOS power stages have several important ?dvantages over their bipolar equivalents. Most Important is the low dissipatio~", which is be.cause DMOS devices need no driVing current In DC conditions and operate very efficiently in high-
speed switching applications. Other advantages include the freedom from second breakdown and the presence of an intrinsic freewheeling diode, which is useful with inductive loads.
Since the original 60V process was introduced
several other process variations have been introduced: a 1OOV version, a 250V version and a n~w family of shrink processes called BCD-II, which use a 2.5u geometry. The evolution of these can
be continuous and to give an idea of the improvement made and forecasted there are two values
(Ron x area and number of transistors per square millimieter which express clearly the strength of a
technology. For the power components there is the Ron x Area parameter which indicates for a given area the reduction in ON re.sistan?~, and hence the improvement in the electrical effiCiency,
or rather, the reduction of the power dissipated.
This parameter appears to improve by a factor of two every four years. In the signal section the most common parameter is the number of ~ransis tors per square millimeter. Here ,Progress IS ~o~e marked than in the power section because It IS possible to exploit the knowhow existing in VLSI technology where the microlithography is the dominating factor and not the current.
A high voltage (>600V) version is also close to introduction. The 60V and 100V versions cover the majority of applications today, in industrial, computer peripheral, automotive and consumer products. At present the main applications for 250V technology are in lamp ballasts and power s~p plies, though it is expected that when new high pressure gas discharqe I~ml?s ar.e adopted by th,e automotive industry CirCUits In thiS technology Will be appropriate, The expected uses of 50~V technology are mainly in offline power supplies and home automation,
EXAMPLE PRODUCTS
We will now examine some typical BCD IC exemplify the remarkable versatility of the technology. Figure 3 shows the block diagram ?f a Chip int.roduced in 1988 for a portable typewriter application -- the chip shown in figure 1.
This circuit integrates 15 power DMOS transistors and about 4000 other transistors. On this chip are all of the power subsystems needE!d in the ~vpew riter: a 1A motor drive for the carnage posltlon,er, a 1A motor drive for paper feed, a 1A motor drive for the daisy wheel, a 3A solenoid driver for the hammer and a 1A/5V switchmode supply that power the micro..In <;tddition the ch,ip includes all of the interface CirCUits, control logiC and protection circuits. One interesting characteristic of this circuit is that most of the functions are programmed by loading internal registers .. It is ~ven possible to program output stage configurations,
- - - - - - - - - - - - - - ""1' 2/6
~ S[iS-THOMSON _ _ _ _ _ _ _ _ _ _ __
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14
APPLICATION NOTE
Figure 3: Block Diagram of the Chip Shown in Figure 1.
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32 02
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38 08 24 WR CS 23
MICRO PROCESSOR INTERFACE
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HS01 HS02 LS01A 11 LS01B LS02A 12 LS02B 18
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an interesting concept that makes the device more flexible than one would expect from such a complex and highly-specific solution.
With the introduction of the shrink version, BCDII, circuits of this complexity have become smaller
and less expensive. Figure 4 shows a recent example of a custom circuit in BCD-II technology for a computer peripheral application that includes a servo positioning system, motor controller and
various other functions that were not integrated on other ICs on the board.
Figure 4: Complex Smart Power Chip Realized with Shrunk BCD-II Process.
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3/6 ---------------------------
15
APPLICATION NOTE
Though most BCD circuits use switchmode
DMOS power stages it is also possible to use the technology in linear applications, as illustrated in fig4re 5, which shows a quad linear regulator chip. Designed for a car radio, this circuit contains four regulators (10V/60mA, 8V/50mA, 5V/300mA, 5V/600mA) with bipolar PNP pass transistors. BCD technology was chosen in this case for several reasons: low cur-rent drain, compact die size and the possibility of having an uninterrupted positive output even in the presence of a negative dump transient.
The circuit shown in figure 6 is an example of a multiple power chip. for the automotive market. This chip is used in rearview mirror units .and drives the three motors (mirror adjust up/down, adjust left/right and fold) plus the defroster heating element. Mixed bonding is employed in this circuit.
Figure 7 shows a practical high voltage ICfabricated in BCD250 technology for a compact fluorescent lamp ballast application. A DMOS bridge output stage is clearly visible.
Figure 6: Multiple Smart Power Chip for Car Mirror Control.
4-/-6--------------------------- ~~~~~~~:oo~~ -----------------------------
16
APPLICATION NOTE
FAST DEVELOPMENT
The design of a BCD smart powerlC, even. a complex one, is surprisingly s~ort. From th~ onginal idea to having a part working perfectly In the application takes typically six to ten months. These parts may not meet the original spec 100% or SGS-THOMSON's yield standards, but they are good enough to use in production. Very complex ICs can be developed in roughly the same time because it is possible to divide the work between several designers. Unlike digital chips, in fact, a smart power IC is often designed
by a single ?esign engineer. T~is f.ast development is possible because such CIrCUitS almost always use just well known and p~edictable. elements -- mainly library cells -- which are simply interconnected. And unlike linear power ICs, the DMOS power stages usually operate in switchniode, which makes their behavior more predictable. The low power dissipation of power DMOS also helps because it minimizes unwanted thermal interaction~.
In some cases the designer may also opt to use automatic layout techniques. This method is fast,
Figure 8: Example of Layout Generated Using Automatic Software Tools.
17
APPLICATION NOTE
though it is not used where die size has to be reduced using manual layout. The circuit shown in figure 8 is an example of a BCD circuit laid out using automatic design tools.
Further time is saved by the application of 100% layout verification using CAD. This practically eliminates the risk of the first silicon not working because of a layout error.
PACKAGES
In power ICs, where dissipation is a fundamental limit, packaging very often determines both the performance and the cost of ICs. Fortunately for users of automatic assembly equipment in this area radically new packaging concepts are not expected in the near future.· All of the ICs described here are, in fact, housed either in DIP, chip carrier or power packages like the Multiwatt 15-lead power tab package.
For high complexity types, where the pin count is generally high, plastic-leaded chip carrier PLCC packages are very popular. By modifying the lead
frame, replacing all of the leads on one side bya triangular head spreader, it is possible to dissipate as much as 2.5W in a 44-lead PLCC. This is the package used for the chip in figure 1.
Where the highest output power is needed packages like the Multiwatt are used. To cope with the high currents involved in some circuits a mixed bonding technique has been developed for this package, using thick aluminum wires for the high current connections and thin gold wires for the others. An example of this is shown in figure 9, a 10A switching regulator IC. Thick aluminum could not be used for all connections because the large bonding pads required would waste too much silicon area; the use of multiple gold wires for power connections would compromise reliability.
BCD technology is often described as "mixed", primarily because it mixes bipolar, CMOS and digital. But it can also be described as mixed because it mixes analog and digital, because it mixes signal and power, because it mixes thick and thin metallization, and because of the mixed bonding technique.
Figure 9: An example of a power IC using mixed wire bonding.
6-/-6--------------------------- ~~~~~~~~:~~A -----------------------------
18
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APPLICATION NOTE
SMART POWER TECHNOLOGY EVOLVES TO HIGHER LEVELS OF COMPLEXITY
by Bruno Murari
Smart power devices are the shooting stars in power semiconductors, because it's possible to integrate digital and analog functions together with multiple power stages on the same silicon chip. The trend towards higher density will continue.
Since it was first introduced in 1986, mixed bipolar/CMOS/DMOS 'smart power technology has evolved rapidly, extending voltage capability and integrating highly complex subsystems on single chips containing thousands of transistors.
Integrated circuit fabrication technologies that combine bipolar, CMOS and power DMOS structures on the same chip have had a significant impact on "smart power" integrated circuit design. Since the dissipation of power DMOS stages in sWltchmode operation is very low it is possible to
produce ICs capable of delivering substantial power to the load without the usual heatsinks, cooling fans and so on. Moreover, because it permits the integration of high-density CMOS and multiple DMOS power stages the traditional con-
straints on complexity are removed and circuits containing complete subsystems have been produced. An example of this is shown in figure 1 a custom IC that integrates a motor control system, servo positioning system, a step up converter, microprocessor interface and other circuits.
Figure 1: An example of the complexity now possible in smart power ICs. This custom LSI device developed by SGS-THOMSON for a computer peripheral application that integrates a servo positioning system, DC motor controller/driver and various other "glue" functions" not ihtegrated in the other ICs on the board.
AN447/0291
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19
APPLICATION NOTE
BCD TECHNOLOGY
A power IC technology combining bipolar, CMOS and power DMOS was first introduced by SGSTHOMSON in 1986. Called Multipower-BCD, this was a 60V process created by merging a conventional junction-isolated bipolar IC process with vertical DMOS technology. The result is a process requiring 12 masks in the standard version - no more complex than modern bipolar technologies.
Where this process departed significantly from previous smart power processes is that it employs isolated DMOS power devices. The significance of this is that designers are not limited to a single power DMOS transistor per chip, but can have any number (hence "Multipower") and connect them in any way. Thus it is possible to integrate any power stage configuration (low side, high side, half bridge or bridge), or even to have several complete power stages on the same chip.
Clearly the combined BCD process gives circuit designers the possibility of choosing the optimal technology for each circuit function: bipolar is the first choice for linear functions where high precision and low offsets are required; CMOS is best for complex analog and digital signal functions because of its high density; and power DMOS is ideal for power stages.
It is the possibility of integrating power DMOS stages that gives BCD technology its greatest advantage: low dissipation. Unlike bipolar ,power transistors, power DMOS devices need no driving current in DC conditions and operate very efficie'ntly in fast switching operations.
This low dissipation can be exploited to' increase the amount of useful power that can be achieved with a given package. For example, both SGSTHOMSON's L296 bipolar power switching regulator and the functionally similar L4970 BCD type are assembled in the Multiwatt package, but the bipolar version delivers up to 160W while its BCD counterpart delivers up to 400W.
An alternative way to profil'from low dissipation is to use less costly low power packages in place of high power packages. Very often a bipolar power IC in a power packag'e can be replaced by a BCD part in a DIP, or even PLCC or SO, package. This can bring substantial savings not only because power packages are more costly, but also because they'are more costly to mount on the board and are not well suited to automatic assembly. For example, a 4A bipolar switching regulator IC in the Multiwatt package can be replaced by a BCD switching regulator in a DIP package (figure 2) which delivers almost the same current.
·Figure 2:The low dissipation of power DMOS can be exploited to make power ICs in low power packages, which are less expensive and easier to mount. This DIP-packaged switching regulator delivers 3.5A, replacing a Multiwatt packaged bipolar IC.
Recently SGS~THOMSON has introduced a "shrink" version of the original BCD proCess called BCD-II - which greatly increases the circuit and current density that can be achieved (figure 3). The original Multipower-BCD process family used 4 micron lithography. In the BCD-II versions this is reduced to 2.5 microns. Consequently the current density and component density are approximately doubled, In the case of the 60V version, the shrink increases signal compone~ density from 650 transistors/mm to 1500 tr/mm ; at the sam~ time the RON.Ar~a is reduced from 0.9 ohms/mm to 0.5 ohms/mm..
-~ - - - - - - - - - - - - - Iiii ~~~~m~~~:U!~©N$ -----~--------
20
APPLICATION NOTE
Figure 3: A shrink version of the Multipower-BCD technology has now been introduced. Called BCD-II, this version doubles the component density, making high complexity devices much less expensive.
5 G 0 o 5 GO
SGD DGS BE C B C E
P-CH N-CH 1-_ _---11 LI_ _ _ _-ll l----.J LI_ _ _ _ _-11 LI_ _ _ L-_ _ _ _---l
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NPN
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STANDARD BCD PRODUCTS
The first BCD chips to be marketed were the L6202 and L6203 DMOS bridge driver ICs - actually the same die assembled in DIP (L6202) and Multiwatt (L6203) packages. Both of these devices have an ON resistance of 0.3 ohms, which gives a maximum continuous current of about 1.SA (DIP version) and 3A (Multiwatt version).
These were followed by a variety of power ICs for computer peripheral, industrial and automotive applications. Typical examples include switching regulator ICs, lamp drivers for automotive applications and motor drivers of various types.
All of the early chips and many introduced more recently are standard devices in the sense that they are normally used in various end products, like standard Iinears or standard logic. In the late eighties, however, designers began to apply BCD technology to make power ICs with a complexity that can truly be called LSI.
LSI COMPLEXITY IN POWER ICs
We have seen that BCD technology allows an arbitrary number of complete power stages on one chip and the dissipation of each is low enough to ensure that the cumulative dissipation of these power stages is within the limit of practical packages. Moreover, high density CMOS allows signal level circuits of LSI complexity to be added on the same chip.
An interesting consequence of these factors is that BCD technology allows the IC designer to build complex systems on a single chip. Moreover, the technological limit on complexity is beyond the complexity of a wide range of end products.
The first example of a circuit that exploits the
possibilities of LSI smart power is the L6280, a device introduced in 1989 for a portable typewriter application (figure 4). This IC integrates two 1A motor drivers, a 3A solenoid driver, a SV/1 A SMPS and microprocessor interfacing circuitry all of the power subsystems of the typewriter. The L6280 behaves like a microprocessor peripheral, latching commands from the bus. All of the functions can be controlled by software - even the output stage configurations.
Surprisingly, perhaps, the overall dissipation of this complex IC is so low - less than 1.SW - a power package was not needed. In fact the L6280 is assembled in a PLCC 44 chip carrier, though the 11 pins on one side are all connected together and used to conduct heat to the PCB tracks.
Since then the same approach has been applied to other applications of comparable or greater complexity. One example is a custom chip designed for a computer peripheral application (figure 1) that integrates a motor control circuit, a servo positioning system, a step up converter, a microprocessor interface and various other glue circuits needed on the board. There are 12 power transistors and roughly 4000 other transistors in this IC. Such a solution is extremely effective because of the increasing trend towards very compact solutions.
BCD technology can also be applied in areas where the emphaSis is more on "smart". than on power. An example of this is the telephone set. Using Multipower-BCD technology it has been possible to realize a single-chip telephone that includes a pulse/tone dialler, voice circuit, ringer and monitor amplifier. Modest power capability is needed for the ringing transducer and the monitor loudspeaker, but half of the chip is occupied by the complex CMOS logic. A total of 16,000 transistors are integrated in this circuit.
---------------- ~~~~~~&~:~~~ ----------------3/5 21
APPLICATION NOTE
Figure 4: Designed for a portable typewriter application, the L6280 integrates two motor drivers, a
solenoid driver, a power supply and complex control logic.
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MICRO PROCESSOR INTERFACE
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The introduction of the shrunk BCD-II technology both increases the amount of logic that can be integrated at a reasonable cost. This improvement in microlithography also allows an improvement in current density of the power DMOS transistors an interesting advantage over bipolar technology where current density depends on emitter area and cannot be improved in this way.
It is also interesting to compare the potential complexity increases for various technologies (figure 5). Clearly there has been a much greater .increase in the complexity of pure digital circuits (about eight decades) than in analog circuits (four decades). In fact pure analog ICs containing thousands of components are extremely rare. A consequence of these curves is that there is a tendency to use digital techniques whenever possible because it allows a greater reduction in area. The possibility of having dense digital circuits on a BCD chip allows designers power IC designers to take advantage of this trend.
At present the capabilities of the technology in terms of complexity generally exceed the demands of system designers, few of which have learned to exploit fully the level of integration now possible. Another important consideration is that LSI smart power devices will· invariably be full custom and developed for a specific end use with
IC designers and system designers working together; at this level of complexity standard products are unlikely.
To create a complex smart power IC the system designer has to understand the capabilities and limits of IC technology and consider a highly-integrated solution from the outset. With today's level of certainty in power IC design this is not a risky choice.
Given the need to embody system knowhow in silicon it is evident that some system designers would prefer to do their own design, using a cell library approach. SGScTHOMSON uses such a design technique in house but we believe that it is too early to offer this on the market because the deSign of power ICs is not as mechanical as low power ICs and the silicon design experience of a skilled designer is very important. The main difficulty lies in avoiding unwanted interaction between power sections and signal sections where a power IC designer really earns his salary. Another non-trivial complication is that there is a difference between designing a circuit which works and designing one that can be produced and tested in large volumes. Often, in fact, the development of testing hardware and software can be more troublesome than the design of the IC itself.
4-/-5------------------------- ~~~~~~~:9~ ---------------------------
22
APPLICATION NOTE
Figure 5: BCD technology allows power IC designers to take advantage of the much greater level of integration achieved in digital technology. Analog functions are replaced by digital equivalents in complex circuits.
Complexity (Nr.of tr.)
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1965
1970
1975
1980 1985
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1990
1995
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_ _______________________ r== SGS-THOMSON ________________________5_/5 ~"'!/I Iliin©rnI@~!Jl©vlil(Qxlilnlt:$
23
APPLICATION NOTE
NEW LEVELS OF INTEGRATION IN AUTOMOTIVE ELECTRONICS
by Riccardo Ferrari, Marco Morelli
One of the fastest growth areas today in electronics is in the automotive field. In this note the authors describe the particular needs of this field and some typical dedicated ICs developed by SGS- THOMSON.
INTRODUCTION
Since the early seventies, more and more functions have been added to our cars not only with the purpose of guaranteeing a better comfort to drivers and passengers, but also to reduce operating costs and finally to ensure compliance with new regulations concerning noise and pollution are concerned. Because of all these needs, cars have to house more and more modules designed to perform more or less complex operations (Fig. 1).
This growth makes more and more evident the need to reduce the room taken by each module, with the double target of minimizing the cost of the particular function and increasing the number of functions in a specific car; in parallel, by increasing the number of modules, it becomes mandatory to increase the reliability of each of them, otherwise the reliability of the total car would be badly affected.
All these issues recently pushed the manufacturers of automotive systems to refer very often to producers of integrated circuits asking for the de-
velopment of monolithic devices capable of replacing effectively a number of discrete components, passive parts included; anyway the trend to a total integration is not over by just designing
onto a simple piece of silicon a complete function, but it carries on implementing in the same device a number of auxiliary services, that would add a substantial cost if achieved by discrete components, that can easily find place on a few extra square millimeters of silicon.
To that purpose the example given by the alternator regulator, subject of a specific description in the following pages, is particularly enlightening. Figure 2 shows briefly the evolution of the alternator regulator paralleled with the evolution of the silicon technology; it is evident that the key issue to pursue the monolithic design of very complex functions in the automotive environment is the availability of process capable to host on the same chip high density signal circuitry, together with power stages managing currents of several amperes; a process with these characteristics is usually called "smart power" process.
Figure 1: Electronics in present and future automobiles.
SAFETY & CONVENIENCE
Rear Window Defoooer Climate Control Kevless Entrv Automatic Door Lock light Drimmer Traction Control Antiskid Braking Window Control Memory Seat Heasted Windshield Voice Controlled Trunk Airbag Restraints
AN449/0392
BODY CONTROL
Cruise Control Intermittent Wipar Antitheft Devices Electr. Suspension Electr. Steering Multiplex Wiring Module to Module Communications Load Sensit. BrakinQ Hard/Soft Ride Control
POWER TRAIN
lanition Spark Timino Voltaae Reaulator Alternator Idle Speed control Turbo Control Emission System Transmiss. Control Diagnostics
DRIVER INFORMATION
DiQital Gauaes DiQital Clock Multitons Alarms EnQine DiaQn. Results Service Reminders Miles to Empty Shift Indicator Head-up Display CRT DisjJlay Audio Annunciator
1/9
25
APPLICATION NOTE
Figure 2: Alternator regulator evolution.
SEMICONDUCTOR TECHNOLOGY EVOLUTION TRANSISTORS, DIODES
ANALOG IC's
ALTERNATOR REGULATOR EVOLUTION
MONOFUNCnON
I
I DISCRETE COMPONENTS INSERTION TECHNIQUE
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CERAMIC LAYER SINGLE PACKAGE
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SMART POWER IC's
MULTIFUNCTION
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MONOLITHIC
I
TECHNOLOGY OVERVIEW
Ov~r the years S~S-THOMSONhas developed various technologies that allow the realization of smart power circuits. The simplest way to classify the.se technologies is to refer to the process type, whlc:h can be purely bipolar or mixed, that is, including on a single piece of silicon both MOS structures (of control and power) and bipolar
Figure 3: Integrated DMOS structures.
structures.
Another method (figure 3) is to examine the way i~ which !he curren! flows through the power seclion;. hOrizontal, with the current entering and leaVing through the upper surface, or vertical, where the current enters through the upper surface and leaves through the lower surface' for this lower connection, instead of wire, the tie' bar
: s·
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MANY POWER VDMOS DEVICES ANY CONFIGURATION
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2/9
-----------------------------
~~~~;~~~:~~
--------~-------------------
26
APPLICATION NOTE
MULTIPOWER BCD/60 VS. BCD6011
Junction isolation Field oxide VDMOS R on* Area (Q*mm2) LDMOS R on* Area (Q*mm2) CMOS tr. density (mm-2) CMOS thres. voltage (V) min. NPN area (miI2) min. PNP area (miI2) Number of masks
BCD20/60 down
Tapered oxide 0.9 0.6 650 1.3 11 15
12/14
BCD6011 up and down Locos + field implant
0.5 0.25 1500
1 4 5 13/15
of the package is used.
The choice of one technology rather than another depends o~ various ~Iements. By simplifying as far as possible the criteria, we can say that vertical techn<;>logies can guarantee, for a given area, lower resistances but they have the limitation of b~inQ able to include just one power device per circuit (or more than one, but always with the collectors or drains short-circuited). Horizontal technologies instead make it possible to have power structures that are completely independent. It is therefore evident that a vertical technology will giv.e excell~nt results in the design of a light sWitch, while a hOrizontal technology will be equally well suited to the design of a multiple actuator.
Finally we have to underline that the continuous evolution of the silicon technologies has already made available, for the design activity, second generation processes, offering to the user both
Figure 4: Mixed bonding technology.
higher component density in the signal section and higher current density in the power area, so that in some cases the limit to achieve very low values of resistance does not come from the silicon, but from the bonding wires. An example of comparison between a first generation smart power technology - today in full industrial production - and a second generation one - today available for new designs - is given in Table 1: the way is open to processes -that will allow the design - on the same chip-actuators - of several amperes together with microcontroller of not negligible power.
It is important at this point to underline that a smart power circuit does not consist of just silicon technology, but relies heavily on package technology. In fact it is well known that a signal device is bonded using gold wires with a diameter of 25 microns; however, gold wires can be used effectively up to diameters of 50 microns, which allows
- - - - - - - - - - - - Gil SGS~1lI0MSON
3/9
·I,
~a©~@~~~i:1lIiil@Liila©@
27
APPLICATION NOTE Figure 5: Power packages.
reliable operations with currents up to 2A, provided that the wire is surrounded by resin (the current capacity drops by 50% for wires in free air - that is, in the case of hermetic packages).
When, however, one has to deal with very high currents (more than 5A in single-point injection actuators, and more than 10A for window lift motors) gold wires are no longer suitable for obvious cost reasons so it is necessary to turn to alu' minum wires with a diameter from 180 microns to 375 microns; clearly in this case it will be necessary to have adequately dimensioned bonding pads on the die, with a significant waste of silicon area.
Optimization is obtained with a mixed bonding technology where signal pads are bonded with thin gold wires and power pads with thick aluminum wires (figure 4). A further optimization is obtained by orienting the pads in the pad-tobond-post direction.
Finally, another key area for a real industrial implementation of a smart power device is packaging; SGS-Thomson has a reputation of unparalleled excellence in the development and in the production of packaging techniques to meet power dissipation even in the presence of high pin count, and several innovative SGS-Thomson packages have been adopted as worldwide industry standards; in Figure 5 several types are displayed, including hermetic metal can, particularly suitable for components, such as the alternator regulators, that have to operate at a rather high temperature, with junction temperature that may exceed 150°C, in an extremely severe envi-
ronment, since the regulator is usually exposed to any kind of dangerous element, such as grease, sand, dust, salt water and so on. A quite original power package for surface mounting, combining a low Rth j·case (less than 3°C) with a small geometry, is under development in our laboratory.
THREE EXAMPLES
THE ALTERNATOR REGULATOR.
We have already briefly mentioned the evolution of the alternator regulator, but it is worth covering with some more details the history of this function.
Since the simple realization of so-called monofunction regulators by means of discrete components - diodes, transistors and resistors - the progress of the technology allowed the design of a monolithic component, still monofunction: in parallel, to provide the driver with more information about the status of the charging function, multifunction regulators were designed, but the power. remained external, on a separate component.
A further improvement came with the assembly technology on a ceramic substrate, housed in a single package, but still several chips of silicon were needed.
Now SGS-Thomson has reached the maximum level of integration by designing a monolithic multifunction regulator and offering to the customer a device that minimizes the assembly operations and maximizes the reliability because of the single piece of silicon and the minimum number of connections between the silicon itself and
4/9 -----------------------------
~~~~~~~:~~
-----------------------------
28
APPLICATION NOTE
Figure 6: Block diagram of alternator regulator.
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the rest of the system: nevertheless the accuracy of the regulation and the number of possible malfunctions monitored by the circuit are well above what offered so far by the market.
The main characteristics of the device are summarized in Table 2 and the block diagram of the circuit is displayed in Figure 6_
The choice of the technology required a particular care and was driven by the following factors:
1)A circuit for the regulation of the alternator voltage, even if equipped with a complex diagnostic, is however a circuit where the power section, including the field drive in low side configuration and the free wheeling diode plus a big active zener diode, takes a significant share - qbout one third of the total, (see Figure7); therefore a bipolar process has been selected.
2)On the other side, about 600 small signal devices had to be integrated, and because of that a technology with a good intensity was mandatory, otherwise the total economy of the program would have been affected.
3)Finally an alternator regulator must be able to withstand very severe voltage transients, as fixed by ISO 7637/1, with voltages up to 270V and energy up to 50 joule, that arise on the
car electrical network, for instance, if a sudden misconnection of the alternator occurs_
Table 2: MONOLITHIC ALTERNATOR REGULATOR
" Low side configuration D No external component D Accuracy on regulated voltage better than
1% D Precise temperature coefficient .. Self-oscillating analog regulation loop D Minimized field current at alternator stopped
(500 mA max) · Maximum field current trimmed at 5A, with
1.5V saturation voltage " Full Diagnostic: alternator stopped
Broken belt Extravo Itage Broken wire alternator-battery " Protected against short circuit (current limitation and thermal shutdown) .. Protected against short circuit of fault lamp driver II Protected against extravoltages according to ISO 7637/1
------------------------------
~~~~~~~~~:~~~
5/9 ------------------------------
29
APPLICATION NOTE
Figure 7
Considering all of the above, SGS-Thomson has selected a high voltage process, internally named BSOII, fully bipolar, horizontal, with lithography of 3Jlm, and more than 100V of breakdown voltage in the VCBO condition. The device is encapsulated in an hermetic package, TO-3 multi leads, with bonding wires of 5 mils, able to carry continuous current up to 7 amperes (see again Figure 6).
Figure 8: Injector driver.
THE PEAK & HOLD INJECTOR DRIVER
Let us now consider the U140, another component designed by SGS-Thomson to make available to the user a complex function on a simple chip; it is an actuator to drive in low side configuration the fuel injector in "single point" injection system.
As it is well known, quite essential for a good efficiency of the injection system is the capability to fix in the best way the time while the injector is opened, since that time is directly proportional to
- VBAT
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:--
DIAGNOSTICS
: - I;J SHORT CIRCUIT TO GROUND I;J SHORT CIRCUIT TO BATTERY
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_____________________________ 6_1_9___________________________ ~~~~~g~:~~
30
APPLICATION NOTE
the quantity of fuel transferred to the intake manifold.
Particularly important to fix the fuel volume are the opening and the closing time of the nozzle, since both must be extremely fast; now, a single point injector needs a consistent current in the apening phase - up to. 5A at the "PEAK" - but ance opened, less current is enough to maintain the status - "HOLD" -. At the end af the cycle, finally the driving current must be switched aff in a time as short as passible. The U140 meets all the abave mentianed requirements: in addition, in the "HOLD" phase a further reduction af the current is achieved by switching an and aff the driver stage (Figure 8), so. reducing the pawer cansumption and, as a consequence, the junctian temperature.
A special mentian shall be paid to the transition from "HOLD" to. the "OFF" condition; as already said, it is quite important to reduce as much as possible this time; in the U140 that is achieved by discharging the inductor through an active zener set at a quite high voltage (about 70V), and that guarantees the closing of the injector in less than 50 sec. The same diode is set at 3V .in the HOLD time. No external component is required by this circuit, that interfaces directly the microcontroller of the engine management system; by the way, the microntroller has just to fix the start and the end of the injection time, since the U140 is totally
autonomous in fixing the current levels in the different phases, as well as the sampling of the holding current. (Figure 9).
The device incorporates a very sophisticated diagnostic (see again Figure 8), and transfers to the microcontroller all the relevant information on the status af the load.
The advantages of this monolithic devices are quite evident, if compared with existing salutions which need not less than 15 components including at least one IC and two discrete transist?rs, but are nat limited to cost and room reduction, and to a consistent increase of the reliability: as a matter of fact the monolithic design allows to get, practically at zero cost, a very accurate value of the voltage af the recirculation diode, improving the accuracy an the ON time of the injector, and, last but not least, a diagnostic covering all the possible failure modes of the load.
The circuit is realized with SGS-Thamson's BCD technalagy, a mixed process including Bipolar, CMOS, and DMOS structures an the same chip; the input section is therefore able to. i.nterfa.ce d.irectly a microcontroller, and the low Side driver IS designed with a DMOS having an ROSON of less than 0.5 ohm. As already explained the recirculatian diode is set at 70 valt in the transition from HOLD to OFF; because af that we selected the
--------------
""11 ~ St:iS.11fOMSON iltll©rnl@~IbIl©1rWO@~II!:$
_ _ _ _ _ _ _ _ _ _ _ _7_/9
31
APPLICATION NOTE
Table 3: MONOLITHIC PEAK AND HOLD INJECTOR DRIVER
· Low side configuration · Peak current function of battery voltage to provide a constant charging time
· Fast recirculation voltage independent from battery voltage
· Slow recirculation at max 3V · Off time and peak current in hold condition internally fixed
· Full diagnostic: - open load - short circuit to ground and battery - thermal warning .
BCD100, an option with a minimum breakdown Drain,Source voltage of 1OOV.
All the main features of this innovative device are listed in Table 3.
REARVIEW MIRROR DRIVING
While we are on the subject of higher levels of integration it is useful to mention the development of circuits for the multiplex wiring system, which replaces conventional cabling with a common bus and "intelligent" switches.
The intelligent switch circuits are key components for the multiplex system, and one of these is a multiple driver IC,the L9946, developed by SGSTHOMSON for rearview mirror driving applications.
This IC integrates all of the control functions and power circuits needed in the electronic external rear-view mirror unit now being adopted for high end cars and is the first chip to integrate these functions. (see Figure 10).
Figure 10
An important feature is that the IC is controlled. directly by a microprocessor -- all of the 'posslbl~ drive conditions· are controlled by loading 4-blt commands and the L9946 generates the appropriate motor control signals.
No external power circuits are needed because the L9946 drives directly the two motors used for mirror orientation (Ilp/down and left/right), the motor that "folds" the mirror for. maneuvering and the demister heating element. In a typical application the chip is used in multiplex door wiring system where the door is connected to the body by three wires and all door functions controlled remotely using smart chips.
Inside the chip are four DMOS half bridge power stages which drive the three bidirectional DC motors, plus a DMOS high side driver that drives the demister element. Control logic integrated on the chip decides how these transistors are to be
EN
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8/9
.~ ...,I
SIiS·THOMSON il\loa:UiI@rn~rna:~UiI@~oa:$
_ _ _ _ _ _ _ _ _ _ _ __
32
APPLICATION NOTE
Table 4: MULTIPLE HALF-BRIDGE DRIVER
· 4.75A TOTAL OUTPUT CURRENT · VERY LOW CONSUMPTION IN OFF STATE · OVERLOAD DIAGNOSTIC · OPEN LOAD DIAGNOSTIC · GROUNDED CASE
switched to achieve the desired motion -- including rapid braking. Two of the half bridges are rated at 1A output current; the other two half bridges and the high side driver are capable of delivering up to 4.75A.
In common with many other dedicated automotive ICs the L9946 incorporates diagnostic functions. Conditions such as overload and open load are signalled to the control micro so that appropriate action can be taken. In addition there is a standby pin that allows the micro to put the L9946 into a dormant state when it is not needed.
CONCLUSIONS
We think we have demonstrated that the industrial availability of processes capable to match, on the same silicon, high power and complex control functions is the key element to the integration of completed functions on a single chip of silicon. The examples described demonstrate that SGS-
Thomson has developed a technology portfolio that can offer different answers for different applications, always optimizing the trade-off among the various needs.
On the other side, all the above considerations would have a merely academic interest if they were not associated with a convenient cost. It is clear that the monolithic integration of complex functions implies the use of not negligible areas of silicon, and that even in presence of high density processes.
It is therefore important to devote adequate resources to the diffusion technique, to increase the yield of each process.
Today's chips, up to 30mm2 (and all the thee examples are below that limit) can be produced at prices competitive with an equivalent discrete solution, and in the second half of the 90'S2the target will be expanded up to areas of 40mm , giving a green light to the monolithic design of complete modules.
----------------------------- ~~~~;~g~:~~ ----------------------------9/-9
33
APPLICATION NOTE
SMART POWER TECHNOLOGIES FOR
POWERTRAIN &BODY ELECTRONICS
by R. Ferrari
Smart power ICs are becoming increasing by common in automotive powertrain and body elec-
tronics. This note provides a general introduction to the subject.
As is well known, electronics is slowly but progressively invading every part of the automotive environment (figure 1); entering first in the car radio, it has extended progressively and is now present in all of the subsystems of an automobile. For those people who prefer a "historical" approach, the evolution of auto electronics has been divided into three main sections, each subdivided into various phases, correlated with the state of the art in general electronics at that time. Today, at the beginning of the 90's we are in the SMART
POWER phase, and it is precisely that which we intend to discuss briefly here (see fig. 2).
We will look at, first of all, some definitions: smart power or intelligent power indicates those families of integrated circuits which include both logic control circuits and components capable of delivering a significant amount of power to a generic load. In numbers, a circuit can be considered smart power if it is able to deliver more than 0.5A to the load, or of withstanding more than 50V, or able to supply a power of at least 1W to the load.
Over the years SGS-THOMSON has developed various technologies that allow the realization of smart power circuits (figure 3). The simplest way
to classify these technologies is to refer to the process type, which can be purely bipolar or mixed, that is, including on a single piece of silicon both MOS structures (of control and power) and bipolar structures. Another method (figure 4) is to examine the way in which the current flows through the power section; horizontal, with the current entering and leaving through the upper surface, or vertical, where the current enters through the upper surface and leaves through the lower surface; for this lower connection instead of wire the tie bar of the package is used.
The choice of one technology rather than another depends on various elements (figure 5) but simplifying as far as possible the criteria, we can say that vertical technologies can guarantee, for a given area, lower resistances but they have the limitation of being able to include just one power device per circuit (or more than one, but always with the collectors or drains short-circuited); while
Figure 1: Electronics in present and future automobiles.
SAFETY & CONVENIENCE
Rear Window Defogger Climate Control Keyless Entry Automatic Door Lock Light Drimmer Traction Control Antiskid Braking Window Control Memory Seat Heasted Windshield Voice Controlled Trunk Airbag Restraints
BODY CONTROL
Cruise Control Intermittent Wipar Antitheft Devices Electr. Suspension Electr. Steering Multiplex Wiring Module to Module Communications Load Sensit. Braking Hard/Soft Ride Control
POWER TRAIN
Ignition Spark Timing Voltage Regulator Alternator Idle Speed control Turbo Control Emission System Transmiss. Control Diagnostics
AN471/0392
DRIVER INFORMATION Digital Gauges Digital Clock Multitons Alarms Engine Diagn. Results Service Reminders Miles to Empty Shift Indicator Head-up Display CRT Display Audio Annunciator
1/11
35
APPLICATION NOTE
Figure 2.
PROGRESS OF ELECTRONICS TECHNOLOGIES
Source· Mitsubishi Motors Corp
Third Generation (System-Wide Control)
·Powertrain/traction system control
I
""8rake, suspension and steering system control *Digital Audio
Second Generation · Electronic ongino control ." Instrum.panel & TripComputer ." Electron.controlled suspension ." Anti-lock brake
." Multiplexing and Two-power-source system · Self-diagnostic device ~ Automobile communication, navigation
I LARGE EEpROM
." Audio System First Goneratlon ( Introduction period )
I SMART SENSOR
." Solid state radio
." Speed control · Electric ignition
SMART POWER
· Digital clock
." Alternator
16 BIT MICRO
4/8 BIT MICRO
DIGITALICs
ANALOG ICs
r TRANSISTORS
DIODES
60
70
80
90
2000
Figure 3: Smart Power Technologies Matrix.
WITH REFERENCE TO:
PROCESS
c
U R R HORIZONTAL E
N T
BIPOLAR
BHP B5011
MIXED
BCD60 (I,ll) B100
F
L
VERTICAL
M1
0
W
MO, M2
2/11
-----------------------------
~~~~~~~~:~~~
-----------------------------
36
Figure 4: Integrated DMOS structures.
APPLICATION NOTE
N-
I
1132t1URAR/ at
10R MORE HV LDMOS DEVICES WITH COMMON SOURCE
G
tf9211URAR [-B2
MANY POWER VDMOS DEVICES ANY CONFIGURATION
1..
1 OR MORE HC VDMOS DEVICES WITH COMMON DRAIN
'='= - - - - - - - - - - - - - -
. .. , /
SliiClH©iISl@·IlIHDl.O~©'MITI1SJ@OIIlND©$
3/11
--------------
37
APPLICATION NOTE Figure 5: Smart Power Technology Matrix selection criteria.
Figure 6.
4-/1-1----------------------- ~~~~~~g~:~~ -------------------------
38
Figure 7: Bonding wire features.
WIRE
DIAMETER (micron)
GOLD
25
GOLD
51
ALUMINIUM
178
ALUMINIUM
254
ALUMINIUM
381
horizontal technologies make it possible to have power structures that are completely independent (figure 6). It is therefore evident that a vertical technology will give excellent results in the design of a light switch, while a horizontal technology will be equally well suited to the design of a multiple actuator.
It is important at this point to underline that a smart power circuit does not consist of just silicon technology, but relies heavily on package technology. In fact it is well known that a signal device is bonded using gold wires with a diameter of 25 microns; however, gold wire can be used effectively up to diameters of 50 microns, which allows reliable operation with currents up to 2A, provided that the wire is surrounded by resin (the current capacity drops by 50% for wires in free air - that is, in the case of hermetic packages,
When, however, one has to deal with very high
Figure 8.
APPLICATION NOTE
RESISTANCE (mOhm/mm)
45 11
1 0.5 0.2
D.C. CAPABILITY (Ampere) in plastic package
1.25 2.50
15 28 43
currents (more than 5A in single-point injection actuators,. and more than 10A for windowlif1 motors) gold wires are no longer usable for obvious cost reasons so it is necessary to turn to aluminum wires (figure 7) with a diameter from 180 microns to 375 microns; clearly in this case it will be necessary to have adequately dimensioned bonding pads on the die, with a significant waste of silicon area.
Optimization is obtained with a mixed bonding technology where signal pads are bonded with thin gold wires and power pads with thick aluminum wires (figure 8). A further optimization is obtained by orienting the pads in the pad-tobond-post direction. But while we are speaking of power it is also important to speak of packages (figure 9). These packages are part of a long tradition of TO-220 type packages (with 3, 5 and 7 pins) but recently new needs in assembly are bringing important evolutions of the classic tab
-----------------------------
~~~~~~~~:~~~
5/11
-----------------------------
39
APPLICATION NOTE
packages. Devices completely encapsulated in completely isolated packages - called Isowattare already in production; in these devices isolation up to 1000V is obtained with a minimum reduction in the junction-to-case thermal resistance.
On the other hand, the practice of using clips, rather than screws, for mounting packages is becoming always more common, both to save space and to obtain better long-term reliability in thermal conduction. This has led to the. TABLESS isolated package which accumulates the previous
Figure 9: Power package Matrix.
two needs, while for surface mounting a non-isolated package with a junction-case thermal resistance less than 3'C/W is in development in our laboratories and will be available in industrial quantities in 1991.
Now that we have examined the means that technology places at our disposition, both in diffusion and in assembly, we can now examine what typi, cal structures smart power processes will allow us to make, and which kind of circuit will normally be driven by each structure (figure 10).
NOT ISOLATED
FULLY ISOLATED
SCREW MOUNTING
CLIP MOUNTING
& SMD
Figure 10: Intelligent power actuators basic configuration.
HIGH SIDE LOIJ SIDE HALF BRIDGE
Figure 11: Intelligent power actuators basic protection.
DVERTEMPERATURE
v
OVERCURRENT
V
FULL BRIDGE
OVERVOLTAGE
v
SIJITCH-OFF BV
CURRENT
SIJITCH-OFF, BV
THERMAL PROTECTION LIMITATION OVERVOLTAGE PROTECTION
6-/1-1--------------------------- ~~~~~~~~:oo~~ -----------------------------
40
I.The typical, so-called High Side configuration, in which the actuator is located between the supply and the load, is traditionally used in the supply of resistive loads,. typically lamps, but is also suitable for mono-directional motors.
2.when the actuator is between the load and the ground of the supply system we have a "low side" configuration, very common for driving inductive loads such as, for example, the solenoids that control the opening of valves (injectors, ASS system, automatic transmission), but also ignition coils.
3.Finally, when we have to drive a motor that rotates in both directions it will be necessary to use a bridge structure; the choice between integrating the whole bridge or just half of it clearly depends on the current involved. Today's technology allows us to realize efficiently a complete bridge to drive a door lock motor, while it is necessary to use two half bridges if the load is a windowlift.
In all of these structures there will always be integrated a certain number of protection circuits, to guarantee survival of the device in the presence of possible failures in the surrounding ambient (figure 11).
Figure 12.
APPLICATION NOTE
These include, to name a few, the automatic shutdown when the silicon reaches a critical temperature (which can be caused not only by a short circuit in the load or its connections, but also by the degradation of thermal contact between the device and its heatsink). Today, in certain applications such as fuel injection this automatic shutdown tends to be replaced with a warning signal, which informs the control unit when a critical situation has been reached, leaving the unit itself to decide what to do (for example, reduce performance to guarantee functionality).
Another very common structure is output current limiting, even in the case of a load short circuit. Usually the intervention of the limitation circuit is accompanied by a diagnostic signal that is made available for the control system. Finally, in some devices a circuit is included that is able to detect overvoltages in the supply system, disabling the output stage and placing it in the best conditions to support the overvoltage.
Given the above, we will now describe a practical case with the aim of identifying how the design time can be optimized through a suitable interaction between the system designer and the silicon manufacturer.
The circuit shown in figure 12 is a dual low-side actuator designed to drive two independent loads with currents up to 3A each (typically injectors). The technology employed is mixed (bipo-
----------------------------- ~~~~~~&~:~~~ ---------------------------7-/1-1 41
APPLICATION NOTE Figure 13: Expertise partitioning when designing a smart power actuator.
POWER 1
DIAGNOSTIC I CONTROL POWER I
POWER 2
\
SYSTEM KNOW-HOW
SILICON KNOW-HOW
lar/CMOS/OMOS) with a horizontal current flow (BC060); if we pass from the photograph to a topographical diagram of the silicon (figure (3) it becomes immediately evident that the chip is divided into a limited number of macroblocks, for each of which it is easy to attribute project leadership. In fact it will be an essential task of the system designers to define the criteria for the driving of the actuator as it is to define the malfunctions for which the activation of a diagnostic signal is necessary. On the other hand it is indisputable that only the silicon designer can optimize the. design of the power section and take advantage of structures already available in his library to realize those functions which are necessary and also repeated frequently in different devices.
The system designer, too, can take considerable advantage from the use of cell libraries so the total design time can b~ reduced to a minimum (7 -9 months from the start of the design to working silicon), reducing significantly the gap traditionally existing between a dedicated circuit (full custom) and a semicustom circuit obtained from gate arrays or standard cells.
A brief glance at another two circuits, each representative of a technology described above.
In the first we see a highly-innovative circuit for use in ignition systems. This is the VB020 (figure (4), a circuit realized in mixed vertical technology (M2) able to drive directly the primary of the ignition coil, combining a darlington with a vertical current flow with a driver circuit and TTUCMOS compatible control circuit (figure (5). In the device are integrated circuits to limit the collector voltage (fixed at 450V max).
We conclude this series of examples with the
L9937 (figure (5), a bridge circuit designed to drive a door lock motor and therefore capable of delivering continuous currents of 6A with starting peaks up to 12A. The device is realized in horizontal bipolar technology and, as appears in the
photograph, is almost entirely occupied by four large power transistors that constitute the output stages of the circuit. In this case, too, you can see the mixed bonding (gold for the signal wires, aluminum for power wires) and the pads oriented to optimize silicon area. In the block diagram (figure (6) you can see a chain of diodes which has the function of monitoring the temperature of the chip.
This brief introduction to smart power technologies would not be complete if it did not dedicate a few words to the price that the customer must pay to buy circuits of this type. In fact a typical question that semiconductor companies frequently hear is "How much does a square millimeter of smart power silicon cost?". Since the price of a square millimeter of silicon depends on the total area of the chip I believe that it can be a pleasant surprise to discover that even for fairly sizable chips - that is, up to 25/Smm2 - the price of each mm2 increases very little (about 25%). The curve of figure 17 gives the trend for areas
between 5 and 50mm2 and, though based on a theoretical calculation, follows closely the present commercial reality. Obviously the graph reflects the current state of the art; if only three years ago the elbow of the of the curve had been moved violently to the left without arriving at saying that the evolution will continue indefinitely with the same speed, it is however reasonable to expect in the next few years a further extension of the linear zone at least towards the 40mm2 region. As for the meaning of "1 mm2 of silicon", several
8-/1-1--------------------------- ~~~~~~~~:~~n -----------------------------
42
APPLICATION NOTE
Figure 14: Fully integrated high voltage darlington for electronic ignition.
'" PRIMARY COIL VOLTAGE UP TO 450V
· COIL CURRENT LIMIT
INTERNALLY SET
TTL/CMOS
COM-
PATIBLE INPUT
· BUILT-IN COLLECTOR-EMITTER VOLT- YIN AGE CLAMPING
'" OVERVOLTAGE PROTECTION OF THE DRIVING CIRCUIT
· FULLY INSULATED FIVE LEAD POWER
PACKAGE
HV(
~:...-.---t3
DRIVER
GND
Figure 15.
-------------------------~~~~;~~~:9n -----------------------9-/1-1
43
APPLICATION NOTE
Figure 16: Full bridge motor driver.
· 6A OUTPUT CURRENT
· LOW SATURATION VOLTAGE
· VERY LOW CONSUMTION IN OFF STATE
· OVERLOAD DIAGNOSTIC OUTPUT
· INTERNAL TEMPERATURE SENSOR
· GROUNDED CASE
VB
VO
oun
'--~_--u OUT2
GNO D--+----+---+-_I-+-l-+~--+---I
aT D---1HHHHif---'
DF tN1 rN2 EN
Figure 17: Smart power silicon.
PRICE/mm2
1192~N4?1-81
2.13
1.8
UNIT
II
1.6
113cUS5
j
1.4
1.2
~ ~
~ V
1.13
113
213 313 413 59 69 79
CHIP SIZE (Kmils2l
BC06B: 1 mm2 · 65B CMOS TRANSISTORS 1 mm2 · 8B 8IP TRANSISTORS 1 mm2 · B.90hm OMOS
--10/11 ------------ ~~~~~~~::9~ --------------
44
Figure 18: Smart power devices.
~ 58
~9B42
f192AN4?1-B2
413 313
~ L552 i'--U0·~
c USB 213
~ TDA2GGS
· ACTUAL/THEORETICAL
113
""" ~1
8 28% 313% 48% 58% 68% 78%
% OF POWER SECTION ON TOTAL AREA
APPLICATION NOTE
possibilities are given at the foot of the table.
There is another way to evaluate the price of a smart power circuit, and this is to estimate the price for each ampere delivered to the load. This method of calculation is less rigorous and can be plotted as a graph assuming as size reference the percentage of silicon dedicated to power compared to the total area of the chip. The line shown in the figure 18 graph indicates that one ampere costs approximately 30 cents but can rise to 45 cents for circuits containing particularly complex control and diagnostic logic, and it can fall to 15 cents for devices consisting essentially of only power stages. It must be underlined that two consumer devices (L552 and TDA2005 - both audio power amplifiers) for which we can assume stable specifications, mature technologies and ample markets, lie exactly on the curve. This should be indicative of the final trend for automotive devices which are as yet young devices in a young market.
11/11 45
APPLICATION NOTE
HIGH CURRENT MOTOR DRIVER ICs BRING AUTOMOTIVE MULTIPLEX CLOSER
by Riccardo Ferrari &Sandra Storti
Smart power ICs delivering up to 25A complete the family of power components needed in automotive multiplex systems, making it possible to drive even a windowlitt motor directly. With these ICs the large-scale adoption of partial multiplex schemes moves much closer.
One of the essential prerequisites for the largescale introduction of multiplex wiring systems for vehicles is the availability of high power ICs capable of driving lamps, motors, solenoids and relays. These ICs must be able to survive in an exceptionally hostile environment, they must be highly reliable and - since so many are needed in each vehicle - they must be inexpensive.
Many power ICs suitable for this emerging market have already been introduced, but a gap was left at the high current end of the range, where ICs delivering 20A or more are needed to drive loads like windowlift motors.
Today SGS-THOMSON has filled this gap with
new power ICs that exploit technologies that make it possible to build very high current ICs that are both reliable and economical. Two such ICs are the L9936 half-bridge motor driver and the L9937 full bridge motor driver.
The L9936 (figure 1a) contains a half-bridge circuit capable of delivering 20A dc current, which is sufficient to drive directly a windowlift motor. Since the motor is bidirectional two of these devices. are used to make a complete drive stage. Designed for lighter loads, the L9937 (figure 1b) contains a full bridge delivering up to 6A continuous (12A peak for starting). A single L9937 device drives a bidirectional dc motor.
Figure 1a: Capable of delivering 25A, the L9936 half bridge driver is a smart power IC suitable for driving windowlift motors in automotive multiplex wiring systems.
VB
VO
IN1 IN2
OF
aT
AN451/1191
OUT
GNO
1/6
47
APPLICATION NOTE
Figure 1b: A full bridge driver, the L9937 delivers 6A (1 OA peak) and is used in motor driving applications such as doorlock driving.
VB
VD
OLJT1
L..-_+-_----'n OLJT2
GND ~-~--*--~~~-+-1--~-+-~~-~
aT ~-. . . ._ ....-.!---'
DF IN1 IN2 EN
Both of these ICs are fabricated using an en-
hanced bipolar power process and a new mixed bonding technology. Bipolar technology has been
adopted for these circuits - rather than the ''BC~'' mixed bipolar/CMOS/OMOS technology used for other multiplex switches - for several reasons. First of all, when very high currents are
involved the resistance of the silicon is no longer dominant - half of the series resistance is caused by the metallization tracks on the surface
of the chip and the bonding wires. Consequently there is nothing to be gained by using OMOS technology to further reduce the output transistor
resistance. Figure 2 shows the contributions to the saturation resistance of a power NPN transistor in the BHP20 process used for these ICs. The use of thick metal (6 microns) significantly reduces voltage drop with high load currents in this technology.
Another reason for using bipolar technology is that the. substrate currents generated in the substrate when 20A load current recirculates would affect low-level CMOS logic. In the L9936 and L9937 high-level bipolar logic is used in the control stages to avoid this danger, giving excellent noise immunity. Interfacing to this high-level logic
duce
multiplex wiring repair. The sim
lion between the three by the adoptio
Cruqialft"the successor multiplex'WlidngJ theneq(J.9:sary reliability and perforrpftncf:!; be adopt(J.don volume produced V?ni()i?s in
. 2-/-6--------------------------- ~~~~;~~~:~~~ -----------------------------
48
APPLICATION NOTE
Figure 2: In very high current ICs the voltage drop of the metallization and the bonding wires becomes significant. This example, a power transistor realized with the BHP20 process (used for the L9936 and L9937) indicates typical values. Because of this problem it is more important to optimize the metal resistances than that of the silicon.
POWER NPN
= ISOLATED AREA 5.7 mm'
MAXIMUM CURRENT = 20A R SAT = 30 mO
CONTRIBUTION TO R SAT:
· WIRES
6 mO
· METAL
10 mO
· SILICON 14 mO N+
THIS IS OBTAINED BY:
· USING DOUBLE METAL
p
THICKNESS (0.7 + 5 ~m)
is performed in the bus interface chip which will
be placed between the L9936/7 and the multiplex bus. Since these interface chips are system dependent they are always developed for a specific application, rather than being standard parts like
the power ICs.
The mixed wire bonding technology used in the new ICs is clearly visible in the photo, figure 3. Because of the high current it is not possible to use the standard thin gold wires employed in
Figure 3: The mixed bonding technology used in the L9936 - shown here after bonding but before encapsulation - reconciles the conflicting requirements of current and silicon area. Thick aluminum wires are used for the power connections; thin gold wires for the signal connections.
-----------------------------
~~~~;~~~:~~
3/6
-----------------------------
49
APPLICATION NOTE
standard ICs. Thick gold wires are out of the question, partly because of cost, but also because they are too rigid to bond to the chip without damaging it.
One alternative, widely used in simple power ICs, is to use thick aluminum wires. However, a thick aluminum bonding wire needs a large bonding pad on the die. In a simple device like a 3-terminal regulator this is not a problem because there are few such pads, but for more complex ICs with eight or more connections the wasted silicon area would be excessive.
Figure 4: After molding and cropping the finished part looks like this. This eight-lead version of the Multiwatt package first developed by SGS-THOMSON in 1979 - has wider lead spacing to suit the large high current PCB tracks.
Another alternative, still used by some com-
panies, is to use two or more thin gold wires in
parallel for each power connection. This solution, however, is costly because more gold wire is needed and it is prone to reliability problems because it is extremely difficult to verify each bond. Moreover, for the currents used in multiplex applications so many parallel wires would be needed this method would be totally impractical.
SGS-THOMSON has developed and industrialized a different solution: a mixed bonding technology where thin gold wires (50um) are used for signal connections and thick aluminum wires (250um) are used for power connections. The two bonding wire types can be clearly seen in figure 3. Note also that the bonding pads for the aluminum wires are oriented in the direction of the wire to avoid needless waste of silicon area.
Because gold and aluminum are bonded using different techniques this has necessitated a twostep bonding operation. Moreover, because of the combination of different bonding metals the leadframe has to be plated with a special gold alloy. This plating is selective, being applied only to the bond area, partly for economy and partly to avoid gold on the external leads, which could contaminate soldering baths, causing reliability problems on PC boards.
Different bonding techniques are used to weld the two types of wire to the surface of the chip. For the thin gold wires the thermosonic method is used where an electric discharge first creates a small ball on the free end of the wire; this ball is then pressed onto the bonding pad and vibrated rapidly (in the ultrasonic range), causing the gold ball and silicon surface to weld together.
The thicker aluminum wires are bonded using the simpler ultrasonic method, where the wire is simply pressed onto the surface of the chip then vibrated rapidly to weld the wires to the pad. Because more vigorous vibrations are used in this technique the aluminum wires are bonded first, followed by the gold wires.
130g. Moreover, the wire must break leaving the bonds intact - if a bond detaches before the wire breaks the part fails the test.
The L9936 is housed in a new eight-lead version of the successful Multiwatt package, originally developed bySGS-THOMSON in 1979 (figure 4). This version has eight leads in line at 0.1" centers, rather than the usual two rows of leads. This makes the Multiwatt-8 package suitable for very high current devices where wide PCB tracks are needed. An ii-lead Multiwatt package is used for the L9937.
The new package also has a larger die flag - to accommodate today's large chip sizes - which has necessitated the addition of new antistress features in the frame design. These features ensure a dependable adhesion between frame and resin - essential for humidity resistance - and isolate the die flag mechanically from the external tab to ensure that the die is not damaged if the tab is deformed during mounting.
In a typical application both the L9936 and L9937 are used with a customer specific interface chiP. which handles bus interface and protocol handling functions. Two different approaches at the system level are used today (figure 5). In the first case each load has its own interface, connected directly to the multiplex bus. An alternative is to combines several load units into a single module; this approach is very attractive in situations like door multiplex where there is a high concentration of loads in a distinct and fairly compact assembly.
To guarantee automotive-level reliability the bonds are pull tested on a sample of parts. In this test the wires are pulled to determine their break-
ing strength. Gold wires must resist a force of at least 15g; aluminum wires must resist a pull of
Figure 6 shows a generic door multiplex solution of the second type, illustrating the role of the new high current bipolar driver ICs. In this example an L9937 drives the door lock motor, two L9936's drive the windowlift motor, a VN02 high side
_____________________________ 4_1_6___________________________ ~~~~~~~~~~n
50
APPLICATION NOTE
driver IC drives a hazard warning light (the light on the edge of the door that turns on whenever the door is opened) and an L9946 multiple halfbridge IC drives the three rear-view mirror motors (two for mirror adjustment and one for "folding" of the whole mirror unit for car washes and so on) and the mirror de-icing heater. All of these integrated circuits are available today.
Pure bipolar technology is used only for the very high current ICs. For all of the other parts a mixed bipolar+CMOS+OMOS technology has been chosen because of the higher efficiency of DMOS power stages and because it allows the integra-
tion of complex parts. The L9946 multiple half bridge, for example, has a four high power half bridges plus a microprocessor interface all on the
Figure 5: Two approaches are being used for multiplex systems. In the first each load has it~. own bus interface; in the second loads are grouped together and share a common electroniCs module. This approach is used in door multiplex systems, where the loads are all close together and multiplex wiring used primarily to reduce the number of wires passing from the body to the door.
~ ~ ~.~ .....
..........
... . . ..
....
MASTER
~ ~ ~.~ -....
........
........
... .
POldER ACTUATOR
BUS TRANS
POldER ACTUATOR
MICROCONTR
POldER
ACTUATOR
j
POWER SUPPLY
MASTER
f19Bf1f1STER-B1
----------------------------- ~~~~~~~v~:~~©~ ----------------------------5/-6 51
APPLICATION NOTE
Figure 6: A typical door multiplex solution will use a mixture of high current bipolar power ICs and BCD power ICs. Solutions of this type will be on production models in 1991.
HAZARD WARNING LIGHT
~
WINDOWLIFT MOTOR
-0-
VN02 HIGH
SIDE DRIVER
L9936 25AHALF BRIDGE
L9936 25A HALF BRIDGE
DOOR LOCK MOTOR
-0-
L9937 6ABRIDGE
MIRROR MOTORS AND HEATER
~ I II
L9946 MULTIPLE HALF BRIDGE
same chip.
BIMOS
CUSTOM INTERFACE
ST9040/E40 8/16 BIT MICROCONTROLLER
L4936 MULTIFUNCTION VOLTAGE REGULATOR
LDP25A BY239
TRANSIENT SUPPRESSORS
J1850 BUS
L9150 BUS INTERFACE
6-/-6 ----------------------------~~~~~~~~:~~n ------------------------------
52
APPLICATION NOTE
MIXED WIRE BONDING TECHNOLOGY FOR AUTOMOTIVE SMART POWER ICs
by R. Ferrari and A; Massironi
By using a mixture of gold and aluminum bonding wires in the same IC, SGS- THOMSON has found a reliable way to correct very high current ICs that avoids wasting die area.
One of the essential prerequisites for the largescale introduction of multiplex wiring systems for vehicles is the availability of high power integrated circuits (ICs) capable of replacing relays, driving directly lamps, motors and solenoids. These ICs must be rugged and highly reliable yet inexpensive. Many power ICs suitable for this market are already available but a gap was left at the high current - roughly 4A+ - end of the range; ICs delivering 20A or more are needed for loads like windowlift motors.
One of the main problems in high current IC design lies in the thin wires that connect the silicon chip itself to the external connections of the IC
package. These. bonding wires are typically fine gold wires (up to SOum thick) which cannot carry more than a few amperes of current.
Increasing the thickness of the gold wires is ruled out partly because of cost, and also because they are too rigid to weld to the surface of the chip without damaging it. It is possible in theory to use two or more gold wires in parallel for each connection but this solution is generally impractical because the large number of bonding pads waste space on the chip (the cost of a silicon chip is proportional to its area), the cost of the wire is excessive and because testing each bond is difficult.
Figure 1: Part of an almost completed strip of integrated circuits utilizing the new mixed bonding technology. The gold and aluminum wires connecting the silicon chip - the small gray rectangle with the gold-plated external connections can be clearly seen.
AN483/1090
1/3
53
APPLICATION NOTE Figure 2: After the wire bonding operation the
completed frame assembly is encapsulated in black plastic resin and the parts of the metal frame that served as a mechanical support are removed. The finished parts are then tested and marked with the type number and lot tracing information.
Figure 3.
One alternative, widely used in simple power ICs, is to use thick (250um) aluminum wires. However, a thick aluminum bonding wire needs a large bonding pad on the die. In a simple device like a 3-terminal voltage regulator this is not a problem because there are few such pads, but for more complex ICs with eight or more connections the wasted silicon area would be excessive.
SGS-THOMSON has developed and industrialized an effective and efficient solution to this problem; a mixed bonding technology where thin gold wires are used for low current connections and thick aluminum wires used for power connections. Figure 1 shows a bonded frame of a 20A windowlift motor driver that uses this method; the two types of bonding wire can be clearly seen. Figure 2 shows the same IC after encapsulation with black molding resin and removal of the support elements of the frame.
Because of the use of aluminum bonding wires a selective gold alloy plating of the leadframe is necessary; gold is one of the few metals that will weld reliably to aluminum. Apart from reasons of cost, gold plating is used selectively -- rather than the simpler overall plating -- because of gold were used on the external lead part of the frame it would contaminate the circuit board soldering bath, leading to possible.reliability problems.
Different bonding techniques are used to weld the
V__3______________~___________ ~~~~~~~~:~~ _____________________________ 54
two types of wire to the surface of the silicon chip. For the thin gold wires the thermosonic method is used where an electric discharge first creates a small ball on the free end of the wire, this ball is then pressed on to the bonding pad and vibrated rapidly (in the ultrasonic range), causing the gold ball and silicon surface to weld together.
The thicker aluminum wires are bonded using the simpler ultrasonic method, where the wire is simply pressed onto the surface of the chip then vibrated rapidly to weld the wire to the pad. Because more vigorous vibrations are used in this technique the aluminum wires are bonded first, followed by the gold wires. On the production lines two separate machines are used in tandem.
Reliability is an important consideration in automotive ICs therefore it is essential that wire bonds be secure throughout the lifetime of the circuit. To ensure that bonds are correctly executed some parts are subjected to a pull test, where the wires are pulled to determine their breaking strength. Gold wires must resist a force of at least 15g; the
APPLICATION NOTE
thicker aluminum wires must resist a pull of 130g. In both cases the wire must break; the bonds must not detach.
These pull tests are also repeated on statistical samples after accelerated life testing where parts are subjected to humidity, thermal cycling, and other stresses.
Mixed bonding technology can be used in various different power IC packages, though the photos here show the Multiwatt-8 package. This type has eight leads in line at 0.1" centers - wider than is usual - to suit high current circuits where wide circuit board tracks are used. The metal frame design of such packages reflects the care taken to ensure reliability in line with the needs of the auto market. For example, the die-mounting zone of the frame is isolated mechanically by notches and groove from the external mounting tab area. This ensures that deformation caused by overtightening the mounting screw will not subject to stress that could adversely affect reliability.
----------------------------- ~~~~;~~~~~n ----------------------------3/-3 55
APPLICATION NOTE
HOW DESIGN RULES INFLUENCE THE HIGH FREQUENCY SWITCHING BEHAVIOUR OF POWER MOSFETs
by A. Galluzzo, M. Melito, M. Paparo
ABSTRACT
Starting from the basic structure of a Power MOSFET this paper describes the electrical equivalent circuit, it analyses in detail the relationship between the physical structure and the switching behaviour of the device, mainly in the high frequency range, introducing RDS(on), CI and COSS gate charge concepts. A comparison of power losses of devices rated at different BV DSS of die size is carried out. The influence of the state-of-the-art Power
MOSFET structure on the ruggedness of the devices (dV/dt induced from the application circuit and unclamped inductive switching) is also briefly analysed. Some future structural modifications improving both switching behaviour and resulting ruggedness are described. Lastly a brief overview of IGBT technology is discussed underlining their advantages and drawbacks compared with Power MOSFET devices.
AN474/0492
1/9
57
APPLICATION NOTE
INTRODUCTION
In spite of their relatively recent introduction on the market Power MOSFET devices are becoming certainly the most successful "high runners" in the Power actuators and industrial application field because of the inherent advantages introduced in terms of switching times and simplicity of the drive. This paper aims to outline some of the factors that are under the control of the Power device designer that enable him to improve the performance of Power MOSFETs for the benefit of system designers while leaving the basic Power MOSFET structure unchanged.
POWER MOSFET EQUIVALENT CIRCUIT
Fig 1 shows the cross section of an N-channel enhancement mode Power MOSFET structure while fig. 2 shows the equivalent electrical schematic of the device including the most important parasitic components playing a crucial role for the switching and ruggedness performance of the device. A Power MOSFET is realized by fabricating thousands of elementary square cells where source regions are connected together by means of a common surface metallization 1.
A polysilicon layer interconnects the gates of all cells. The source region of a cell is inside a P-Iayer which forms the channel region necessary to control the vertical current flow of the device. The following list is a key to the drawing of the simplified model shown in figure 2:
RG = Polysilicon gate resistance
C1 =, Capacitance between gate and source C2 = Capacitance between gate and P
region
C3 = Capacitance between gate and N
epytaxial layer
C4 = Capacitance of the channel depletion zone
C5 = Capacitance of the depletion zone in
the superficial epitaxial layer
C6 = Capacitance of the body-drain junction
In the text, reference is also made to the following capacitances:
CGO : total equivalent capacitance between gate and drain
CGS : total equivalent capacitance between gate and source
Cos: total equivalent capacitance between drain and source
s
Rsource
Gale Rgo\e.
p+
DRAIN
N-
N+
C5
T ',0,oC3
I
~
C4
C1
Fig. 1 - Power MOSFET structure:
Fig. 2 - Power MOSFET equivalent circuit.
-219----------'--- LV ~~~m~~:9J: - - - - - - - - - - - - -
58
APPLICATION NOTE
The parasitic bipolar transistor shown in fig.2 is formed by the body region between the N area of the source and the N epi layer of the drain. The body-source resistor is due to the P-body bulk resistance and the P-body/metal contact resistance. For most of the applications it is sufficient to substitute, on the schematic diagram, a "bodydrain diode" in place of this parasitic bipolar transistor. Device behaviour is straightforward in fact with positive drain-source biasing, as soon as the gate source voltage reaches the threshold voltage (Vth), necessary to invert the P-well region below the gate oxide, the current begins to flow from drain to source regions. The relationship between VDS' VGS and ID is the typical input-output characteristic. In switching applications, once the circuit topology has been established (type of converter, frequency, magnetics etc.), the optimization of the design requires the minimum of power losses possible. During the device's on-state, RDS(on) is the parameter to be taken as low as possible to reduce losses; this parameter is normally defined as follows:
RDS(on)= RCH + RACC + RJFET + REP1 Where: - RCH is the channel total equivalent
resistance, depending on the horizontal layout of the device channel length and channel perimeter, - RACC is due to excess charges within the drain region below the gate oxide, - RCH and RACC are the most dominant contribution for low voltage devices, - RJFET is the resistance of the drain region between the P body regions of two adjacent cells,
- REP1 is due to the intrinsic epy bulk resistance therefore strongly dependent on BVDSS '
SWITCHING BEHAVIOUR
The switching behaviour of a Power MOSFET is affected by the unavoidable parasitic capacitances of the structure. Therefore switching losses can be predicted taking into account the gate charge curve and the output capacitance, CDS' Second order effects due to packaging and assembly will be neglected in the following discussion as they can be taken into account by means of suitable macromodels for computer simulation [2.3] The gate charge curve (fig.3). obtained by injecting a constant gate input current is split into several areas. At the beginning, starting from
VGS = 0, Ci = C1 + C2 + C5.
ID remains equal to IDSS until VGS reaches VTH (region 1); C4 decreases further when VGS increases so that when
VGS = VTH, Ci '" C1 + C4 + C5.
Therefore ID builds-up while VGS increases from VTH up to VTH + ID/gm (region 2). Due to the linear behaviour of the Miller body drain capacitance, VGS remains constant while VD decreases until the device becomes fully ON (region 3 and 4)
Ci = C1 + C4 + C3
In the saturation region (5) a further increase of VGS yields a V DS decrease down to RDS(on) · ID· The gate charge curve is obtained at constant gate current hence the horizontal axis is proportional to the stored charge and to the time necessary to switch on and off under defined driving conditions.
--------------------------~~~~~~::::~-------------------------3/-9 59
APPLICATION NOTE
/
J '0/ ~
V1ll VGS
Vos
{I\ VX ~ VOSAT '0
o1 2 3
q "
Fig. 3 - Load line and dynamic characteristics versus gate charge.
-
VOS CON)
Therefore it follows that a first comparison between two devices rated at the same voltage and ROS(on) can be made by simply looking at their gate charge characteristics. Cos capacitance does not influence the evolution of the gate voltage but is responsible for the power losses during switching. Cos does not generally limit the dV/dt . experienced by the drain region. In fact, for a high voltage device (IRF830) with the following bias conditions:
drain voltage VDO = 400V
gate voltage max VG = 15V
gate external resistor RG = 10 ohm
do = charge variation inside zone 3 of the
gate charge curve the dV/dt imposed by the drain voltage is:
dV/dt = VOo' (VG - VTH)/(do ' RG) =
400 · (15-3.5) = 23 kV/msec 20 · 10-9 · 10
As: 10 =COS' dV/dt and Cos =44 nF (typical)
10 is about 1A
10 = 44' 10-12 · 23' 109 = 1A.
A current of roughly 1 Amp is then required to charge Cos at the dV/dt set by the gate circuit: because the device has a nominal current of 5 Amps, Cos has little influence when an IRF830 is used in standard applications. This means that in most of the cases it is possible to take into account the effects of COs when calculating the power dissipation during both turn-on and turn-off.
The situation in resonant converters is quite different, where the current or voltage is negligible during switching and the previous approach is no longer valid. Cos effects now influence the stored energy.
Fig. 4 shows how ROS(on) and Cos limit the device working frequency in resonant converters.
The power dissipation versus working frequency for devices rated at different breakdown voltage, die size and ROS(on) has been analysed,
It can be observed that a high voltage Power MOSFET dissipation at low frequency is greater than the power dissipation of a medium voltage one with the same die size.
------------- 4/9
-------------
L"'!I
~~~~m~r::oo~l:
60
APPLICATION NOTE
Coss (pF)
f (KHz)
Pd (W)
BVdss · 500 V
100t--c--~-----------r--l"--I
1.5
2.5
3.6
4.5
Ron (ohm)
Fig. 4 -How ROS(on) and Cos limit the device working frequency.
l~~=-~~-u~~~~~u=~~lli
0.001
0.01
0.1
1
10
100
1000
f (Khz)
Vdd· 350 V, ld· 5 A Tc-25C
Fig. 5 - Power Dissipation versus frequency.
A simple explanation can be based on the higher value of Repi of high voltage devices in comparison to medium voltage ones. Increasing the cell packing density, especially for low voltage devices allows reduction of the die size while maintaining the same R OS(on) and gives an improvement in capacitance values and of the power dissipation at high frequency (where the power losses are more significant during switching). Fig. 5 shows that a well defined application requires the right Power MOSFET device. A device with a large ROS(en) will be preferable for the same BV OSS if the target is optimised efficiency at high frequency.
PERFORMANCE vs LAYOUT RULES
For low voltage devices it is possible to improve the RDS(en) and the gate charge curve by optimizing the horizontal layout and dopant profile. Fig. 6 shows the improvement obtained in gate charge characteristics for 3 devices rated at 60V, 20 milliohm, each with different cell packing density and bonding on the cells.
Cell dimension and the distance between adjacent cells are respectively 19/1m and 15/lm for standard devices, 14/lm and 8 /lm for very high density device, 10/lm and 6/lm for ultra high density devices.
The different behaviour is obtained because of better exploitation of the silicon area with reduced cell dimensions and distances which produce a reduced total device area for a
given RDS(en) For high voltage devices the most significant term that contributes to R OS(en) is R epi' Nevertheless, optimization of horizontal layout strongly influences the capacitance values (C1 to C5). Starting from the standard 500V process of 0.35 Mceli/inch 2 performance can be improved by both increasing cell density up to 0.76 Mcell/inch 2 and the oxide thickness of critical cell areas (reducing Cos capacitance) (see fig.7).
---------------~~~~~~~~:~~-------------5-/9
61
APPLICATION NOTE
11 Vg (V)
10
500 V, 1.5 ohm DEVICES
ro
~
~
~
~
~
ro
M
00 m
Og (nC)
-A- STD -+- VHO """'*- UHD
Fig. 6 - Influence of cell packing density on gate charge.
O*--~--~--~--r--~-~
o
10
20
30
40
60
60
Og (nC)
Fig. 7 - Oxide and layout influence on gate charge,
=, .=.. IIIFr arll i- ml
_= --- . OBi ~ ~
.- ~tIII I~ . IU .
... ,
"" L' ~/'.\\1
11
, ~~ ~1 ~
l1 · ~~
-...- . &.' 'J!!!!!!!
· · .--
~ I.I I 1·,.;·;.;
~ .
.-- ..... '-" ....
....
~
Diode' recovery
V = 50V/div I = 5Ndiv DlJdt = 200N~S, dV/dt = 2V/ns
-Oal;i.,, ·ml
I
u
..: ~
l,l;;!j I hi
-. ···.11 . , .
I
~-,
~. I
~
· .11'.1 (.
r. l~
":::::i
~, r-
-- · "~
"t... ........
~ ..... .. -.. .... -. -,-11
II
~ ~
Parasitic turn-on during
Diode recovery I = 10Ndiv
dlJdt = 250N~S, dV/dt = 4V~nS
Fig. 8 - Typical waveforms when failure occurs.
RUGGEDNESS
A very important characteristic of power devices is ruggedness. A Power MOSFET must withstand a static and dynamic dV/dt U.I.S. (unclamped inductive switching) caused by the application and environment. A failure due to static dV/dt occurs when a sudden voltage variation is experienced
between the source and drain of a power MOSFET in the off state; this causes a current flow through both the body-drain capacitance and the body resistance: if the current is big enough the voltage drop across RB causes the parasitic transistor to switch on and the device fails because of the simultaneous
-6/9------------- !fi ~~~~n_~~:~~:: ------------'---
62
APPLICATION NOTE
100 r=ld-,:-(,:"AI)::::-:-c--:--::::-:-c------,-----,---,----------:-~ . ... ......:::::~~ ::::::: .:~ .:r..".
I I NEW BUZll 2.2 Mc/sqi
1~~-~------_*-~~
a
w
~
~
~
~
~
ro
~
Vds (V)
Fig. 9 -Ruggedness improvement.
switches on the whole Power MaS fails because of the current focusing effect. The failure mechanism is almost the same for all described stress. A way to improve the ruggedness of the device is to optimise its vertical and lateral structure reducing RB and the low current gain of the parasitic transistor as much as possible. Fig. 9 shOWS the improved ruggedness obtained by the optimization of body doping in comparison with the first generation Power MOS.
IGBT VERSUS POWER MOS
presence of high voltage and high current with a subsequent hot spot generation. The dynamic dV/dt occurs when fast voltage variation finds the body-drain diode in recovery conduction (after freewheeling behaviour). Now the current flowing through RB is the sum of the recovery current and the current due to the body-drain capacitance. Clearly a lower dV/dt than the previous case can now produce device degradation. Fig. 8 shows a typical waveform during this kind of failure. When the device switches an inductive load and the drain-source voltage overcomes the nominal defined breakdown value, then unclamped inductive switching occurs. When this happens the energy stored in the load inductor discharges rapidly through the device at breakdown voltage, forcing 10 current, to ·flow in the device and increase junction temperature. Under effect of the. temperature change the V BE of the parasitic BJT decreases and can cause switch-on .of the transistor itself, the current flowing in Rb (body bulk). When even a small portion of the parasitic BJT
From the results of measurements referring to switching speed and ruggedness the Power MaS is an almost ideal device due to unipolar conduction, but in some very high voltage applications, the device's ROS(on) becomes a real limitation. For applications at high voltage where ROS(on) losses are of primary importance, IGBTs find a suitable environment. An IGBT has the same structure as the Power MaS and additionally has a P-Iayer under the standard N doped drain. When the device is on the P-N junction so realized injects minority carriers into the drain region modulating its total epi resistivity. This means that the IGBT is a 'high voltage device with an insulated gate having a low voltage drop during the conduction phase. In the structure of the IGBT it is easy to recognize a PNPN (degenerative) structure driven by a power MOS. This implies that a device designer must realize a device with a degenerative current value (ILATCH) greater than the nominal current in all working conditions, to ensure that the PNPN structure never turns-on. This is
-------.,------ 1>...,/ ~~~n'~r:::n - - - - - - - - - - - - -7/9
63
APPLICATION NOTE
lIt I::
Vds· 80 V/div Id · 2 A/div
w:.... ~
Vg· 5 V/div
.
..l~ r .., rj II J'4
Rg · 100 ohm
L · 180 ~h
1G:an
T · 100°C
~,
=.r.:
:::
D. , ·m"· ...
rr:~1lI.I
~
WITHOUT IRRADIATION
WITH IRRADIATION
Fig. 10 - IGBT switching characteristics.
well demonstrated in practice because I LATCH > 5 ID nominal in all conditions. An additional way to design latch free devices is to control transfer characteristic gm so that for a given driving condition drain current never exceeds the permitted IDmax(ID latch}. Currently the state-of-the-art fall time of an IGBT's drain current is longer than that of equiva.lent power MOSFET of same area. In' fact when the power MOSFET in the IGBT structure is switched off, the charge stored in the base of the PNP parasitic transistor can be removed only by intrinsic carrier recombination. Referri ng to fig.1 0 the first portion of t fall is related to power MOSFET switch-off while the tail is due tothe longer recombination time of the carriers. A well known method to speed-up the switching off behaviour of the device is the lifetime killing technique using gold and platinum doping, ion implantation and B irradiation. Fig.10 shows the improvement of
. Ps (kW)
0.1
10
100
1000
f (khz)
Fig. 11 - Power MOSFET versus IGBT.
IGBT's fall time obtained with B irradiation of the device. A comparison of the power handling capability of a 1000V IGBT and a 1000V Power MOS of both 25mm2 is shown in fig.11 where Po is kept constant (1 OW}. It is undoubtedly advantageous to use IGBT's at a frequency below 20kHz to reduce losses and cut silicon costs.
------------- '''1' 8/9 ~~~~~£~:oo~:: ------------~
64
APPLICATION NOTE
The 3rd generation of IGBTs showing a fall time lower than 200nsec will allow the crossover point of fig .11 to move up to 50kHz.
CONCLUSION
State-of-the-art power MOSFETs and IGBTs have been shown to be rugged and reliable as a result of many years of production and technological know-how. Nevertheless, the uninterrupted progress of the technology and the constant relationship with final users and system designers is a challenge for the device designers. They must take into account second order effects and new demands to provide continuous improvement of field controlled devices both in terms of performance and lower cost With the aim of reaching better performance the main targets for improving the devices have been defined. These concepts will also be applied to the production of new devices. Detailed design rule variation will produce significant improvements in low voltage devices; increasing cell density and tuning dopant profiles. For medium-high voltage devices switching losses will be greatly reduced by varying the differentiating oxide
thickness in conjunction with the covered active regions of the device layout. These new design rules will therefore lead to better power conversion efficiency and greater ruggedness. The predicted, reduced switch-off time as low as 0.2msec,obtained by new life-time control techniques (tested on 500V laboratory devices) will allow IGBTs to be cost effective competitors to power MOSFETs in the high voltage, medium frequency range (30 to 50kHz).
REFERENCES
1] F. FRISINA, U. MORICONI, "High Density POWER MOSFETS", SGS-Thomson internal report, 1987
2] M. MELITO, F. PORTUESE, A. SINERI, " COSMOS: A Tool for Optimization of Layout and Process Parameters in Power MOS Design", The Electrochemical Society, 175th meeting, Los Angeles, May 1989
3] R. CAPOZZI, M. MELITO, F. PORTUESE, A. SINERI,"Power MOS modtjl for Spice'; SGS-Thomson internal report, 1989.
- - - - - - - - - - - -9/9
-------------~ ~~~~m&r::~~:: 65
APPLICATION NOTE
GATE CHARGE CHARACTERISTICS LEAD TO EASY DRIVE DESIGN FOR POWER MOSFET CIRCUITS
by M. Melito, F. Portuese
ABSTRACT
The traditional method of specifying input impedance for power MOSFETs is not incorrect, but it is incomplete and often leads to confusion when it is used as a design tooi. An alternative method is to use the gate charge curve, which is directly related to the total input impedance and allows a simple evaluation of the drive energy and the switching performance to be made.This paper deals firstly with an analysis of the gate-charge waveform which is related to the device physics and develops an analytical expression, which gives a very good
approximation of the total gate-charge. Secondly, the influence of the electrical parameters, both external to the device (e.g. 10 , V oo ) and the internal ones (Vth' gIs' Ciss ' COSS' Crss ' cell density) are analysed.The paper also highlights how it is possible to extrapolate the actual dynamic behaviour of the device easily from this curve. Finally, an evaluation criterion is suggested that allows a comparison to be made between the actual performances, both static and dynamic, of devices with similar nominal characteristics.
AN475/0492
1/8
67
APPLICATION NOTE
GATE CHARGE MEASUREMENT
During the switching of a POWER MOSFET, the gate current has the typical behaviour of current in an RC circuit, see figure 1. The transient lasts for some tens of nanoseconds or more, due essentially to the RC time constant and the maximum current available in the driving circuit. If the current in the gate, Ig' is constant and small enough, the switching time can be increased to a level where the voltage and the current waveforms are free from the parasitic effects caused by the stray
r'\
\ Ig
\
~
/ Vg
~
inductances that are usually associated with high frequency power switching. In this way it is possible to isolate the influence of the external factors and analyse only the internal parameters. The test circuit and the related waveforms are shown in figure 2.
GATE-CHARGE CURVE ANALYSIS
To get a better understanding of the phenomena which occur during switching it is useful to refer to the model of the POWER MOSFET shown in figure 3b. The figure 3a shows the cross section of a single cell illustrating the parasitic capacitances. The gate-charge waveform is strictly related to the modulation of the gate-source equivalent capacitances during switching. This is due to the variation of the intrinsic capacitance of the device with gate and/or drain voltage. Figure 4 shows the load line and Cgs' Cgd variation during each phase of switching. Figure 5 shows a typical gate-charge curve: the capacitances influencing the shape and the length of each zone are marked.
Fig. 1 - Ig' Vgs waveforms
'0: SA/OIV
o
IJ
\
Vos: lO'V/olv \ 'I
/
/
I \ VG: 2V/DI~
'-1-
5 US/DIV
Fig. 2 - Test circuit and related waveforms.
V
IG: CONSTANT
Q: 7, NC/OIV
2/8
------------------------~.~~~~;~~::~~ -------------------------
68
APPLICATION NOTE
C1: Capacitance between gate and source (both Wand metal)
C2 : Capacitance between gate and P zone. C3 : Capacitance between gate and epi N. C4 : Capacitance of the depiction zone in the
superficial epi. Cs: Capacitance of the depietion zone in the
superficial epi. C6 : Capacitance of the body-drain junction. Fig. 3 - Cross section of a Power MOSFET cell and its electrical equivalent.
v =Vth y,
~ I
I
I
I
...l.-
I I ~
~ l®
Vds {1jo\t~l
c"
C,
C",
o1 2 l
Fig. 4 - Load line and capacitances modulation.
----------------------------- ~~~~~~~~:~?~ ---------------------------3-/-8
69
APPLICATION NOTE
Vg IV) 10 8 6
(4+(2+(3
VdIV) 100
80
C9J
60
C3
4
I
I
2
I
I
I
Q,1 I Q..21
(U
0
40
20
0.4 1
0
0. 9 (n()
0 v, ...r..
Cs
VJJ
Vd,
Fig. 5 - Gate charge curve
Fig. 6 - Cgd modulation
In the first zone the equivalent capacitance is nearly equal to Ciss because Vd is constant and the variation of V9 has no influence. The charge supplied to the gate can be approximated by the expression:
01 = (C 1 + C2 + Cs ) · Vgm = Ciss · Vgm
where Vgm is the gate to source voltage required to just carry the desired Id and it can be easily deduced using the output characteristic. In the horizontal zone the equivalent capacitance seems to be infinite, in fact Vgs remains constant though charge is supplied to the gate. This phenomenon, known as the Miller effect, is due to the modulation of the capacitance Cgd by Vds' The waveform of this capacitance variation is typical of a MOS structure switching from being strongly inverted to the accumulatiqn status, see figure 6. The only difference is due to the fact that modulation of the depletion zone is caused not only by the voltage but also by lateral injection of the charge coming from the channel.
Looking at the drain voltage, figure 4 and figure 5, a slope variation can be observed occurring at a voltage, V x, physically corresponding to the transition from a highly charged P zone to simple depletion of the MOSFET capacitor that exists between the deep body cells. The first slope is related to Cs '" CrSS' the second to C3, the polarity of Vgd being so that Cs » C3. So the charge supplied to the gate during the Miller effect can be split into two parts:
02 = Cs · (Vdd - Vx) '" Crss · (Vdd - Vx) 0 3 = C3 · (Vx-Vd(sat))
being Vx = Vgm + Vth-epy + Repy' Id and Vd(sat) the voltage drain corresponding to the "knee"
of the output characteristic with Vgs = Vgm'
The slope of the final part is associated with the oxide capacitances. (V th-epy is the threshold voltage of the MOSFET capacitor · existing between the P zone; Repy is the resistance of the drain due to the epi). The charge supplied during this phase is:
04 = (C 1 + C2 + C3 ) · (Vg(max) - Vgm)
--4/8 ----------- ~ ~~~;m~~r::~~~ ------------
70
APPLICATION NOTE
V,m
P2ZZ2Z22222222722722272Z2/272227772722222/J
v V
2
.. ..........·......................··.··..............- ...................._....
0~--~----4-----~--~--~
o
20
40
60
80 100
Qg(nC)
Fig. 7 - Vx evaluation.
Fig. 8 - Gate charge curves as a function of Id and Vdd'
V V
10 ....................1·....-..·.....~..... .... ..~.............-.... ~-...... . ........
!................ 11.0 MCI~gil:
:
:
8 ....................
!. 12:2 M~'g&U--·..·~ ...................
6· ..·..........-....~ ......-....~ ..·..............·..1·..·..............~....................
4 r··..·..·...·t.·..·...·..+.·...!~:·s.··~·~·'.·s.~·~L.
2 .--..r· ....·....r· .·....·.·.rI .·..·.··_·,r..·.·...·
o
o
20
40
60
80
100
QgrnC)
Fig. 9 - Influence of cell density on gate charge.
EFFECTS OF THE PHYSICAL AND ELECTRICAL PARAMETERS ON THE GATE-CHARGE CURVE
The previous discussion has shown that the total charge supplied to the gate is influenced by several parameters, which are essentially:
a) electrical parameters (V dd' Id) b) structural parameters (cell density,
capacitances, Vth, gls) The electrical parameters are imposed by the external circuit and depend on the application; the structural parameters are typical of the
10
8
6
Crss
13 gfs o1 Crs5
4
2
20
30
40
50
Og(nC)
Fig 10 - Comparison of gate charge curves of two devices with different values of CiSS' gfs and
Crss '
device and can be adjusted during the device deSign stage in order to optimise its performance. Figure 8 shows the influence of Id and Vdd on the shape of the gate-charge curve.
Figure 9 summarizes the effects of the structural parameters: the gate..charge curves of devices having the same static characteristics (RdS(on)' BVdss' Id) and different
- - - - - - - - - - - - - l:ii ~~~~m~¥r::~~:: --------~---- 5/8
71
APPLICATION NOTE
Fig. 11 - Gate charge curve of IRF832. Vg5 = 2V/div. Vd = 1OOV/div. Og = 5nC/div.
Fig. 12 -IRF832 turn-off. Vg5= 5V/div. Vd = 100V/ div. Id = lA/div. t = 500ns/div. Rg = 180 Ohms.
14~~~--------------------~.
12 10
8 6 4
2 ~ 1.~_09_~ tot
10 20 ]0 ~o 5U 60
Qg(nC)
Fig. 13 - Driving energy and gate charge.
08 GIS/Qg
·
*
0.6 + +
o. O.S Mc/sql + 1.3 Mc/sqi
0.1
.. 2.2 Mc/sql
-- 0
0.2
0
0
a
"
"
o
O~-L--~~~~-J--~
o 100 200 300 ~OO 500 600
OVdS5
260 Kc/sql 720 I(c/sql
Fig. 14 - Comparison of technologies.
cell densities. are shown. Figure 10 shows the influence of the capacitances and of the transconductance on the same curve.
Use of the gate-charge curve
The gate-charge curve analysis is useful for obtaining important information about device switching characteristics; The following example evaluates the switching time of the SGS-THOMSON IRF832 as an example.
Figure 11 and figure 12 show. respectively. the gate charge curve and the turn-off of the IRF832 measured under similar conditions of Id and Vdd' Note that the horizontal axes of the gate-charge graph are in nanocoulombs (0 = Ig * t. Ig=const.) while the vertical axes
are in voits. Referring to figure 5 and figure
11. the values of the single contribution to gate charge are:
0 1 = 5nC
-6/-8----------------------- lifi ~~~~m~~:~~~ -------------------------
72
APPLICATION NOTE
O2 = 11 nC 0 3 = 13 nC 0 4 = 18nC
During ta, Cgs is constant so this time is easy to evaluate using the usual calculation for RC circuits:
ta = Rg · Cgs · In(Vgs(to)/Vgs(ta)) substituting:
Rgs = 180,
Cgs = dO/dV = 18nC /4.7V = 3829pF,
Vgs(to) = 10V, Vgs(ta) = 5.3V
ta = 438ns. From ta to te, Ig is constant and its value is Ig = Vgm /Rgs = 29.4mA hence:
tb = Oilg = 442 ns
te = Oilg = 374 ns
During td Cgd is constant and using the previous expression:
td = Rg · CgS · In (Vgs(te)/V9S(lh)) = 96ns
Note Cgs = Ciss
lI(RCn Og)
Looking at figure 12 it is possible to see that the calculated times are very close to the measured ones. The gate charge curve is also helpful because it allows the driving energy to be calculated. The area under the gate-charge curve represents, in fact, the total amount of energy needed to turn-on the device while Vgmax · 0g_lol is the total energy that the driving circuit has to supply, see figure 13. In order to obtain fast switching with low driving energy and low energy dissipation during the cross-over, the optimum device should have low Og and high gls. To obtain low power dissipation during the on state, the optimum device should have low RdsonIt is useful to define two merit coefficients to give a measure of device performance:
K1 = gl/Og K2 = (Rds(on) · Og)"1
Devices having analogous nominal characteristics (BV dss' Id) but manufactured using different technologies can be quickly compared, see figure 14 and figure 15. Note that the two coefficients are not dependent on device die size because of their definition. They both depend on switching features (Og) but K1 is related to the saturation zone (gls) of the Power MOSFET out characteristics whilst K2 is related to the linear characteristic
(Ron)·
o 0.5 Mc/sqi
0.1
.+ 1.3 Mc/sql 2.2 Mc/sqi
o 280 Kc/sqi
x 120 Kc/sqi
x o 0.0 1 "--'--'--'---'-->------'
o 100 200 300 400 500 600
8Vdss
Fig. 15 - Comparison of technologies.
CONCLUSION
The gate charge curve supplies useful information about the actual behaviour when the device switches. From the user's point of view, these curves allow the correct design of the drive circuit and correct choice of the device which best satisfies the design criteria. The use of two merit coefficients allows a quick comparison of devices having similar
-------------~~~~~~~~:~~-------------7-/8
73
APPLICATION NOTE
nominal characteristics but manufactured using different technologies.
REFERENCES
1. F FRISINA, U. Moriconi, "High Density Power MOSFETs", SGS-THOMSON internal report 1987.
2. M.MELlTO, F.PORTUESE, A.SINERI. "COSMOS: A Tool for Optimisation of Layout and Process Parameters in Power
Design", The Electrochemical Society 175th meeting, Los Angeles, May 1989.
3. R.CAPOZZI, M.MELlTO, F.PORTUESE, A.SINERI, "Power Mos Model for Spice", SGS-THOMSONinternal report. 1989.
4. A.GALLUZZO, M.MELlTO, M.PAPARO "How Design Rules Influence the High Frequency Switching Behaviour of Power MOSFETs", PEC, Long Beach, February '90.
8/8
------------
r==
. ..."
SIl'AGJDlIS::f.iniI@t~~OrnffMlfiiSl@IIO!DIIN::®
_ _ _ _~------
74
APPLICATION NOTE
ANALYSIS AND OPTIMISATION OF HIGH FREQUENCY POWER RECTIFICATION
How can the performance of power electronics be improved? Today, in many cases, it is the job of the designer. The fast rectifier switching behaviour depends on the operating conditions. The analysis and the optimisation of these conditions can be an important source of improvement in performance.
1. SWITCH-OFF OF FAST RECOVERY RECTIFIERS
It is possible to define theoretically two types of switch-off1.
1.1. FREE-WHEEL MODE (figures 1 & 2)
When the rectifier switches-off it is always in parallel with a voltage source. In this case the assumption is that the parasitic inductances are negligible. This type of behaviour can be met in the majority or rectifier applications such as free-wheel rectifiers in step-down and step-up converters, full wave rectifiers, etc ... (figure 2). Generally, a rectifier in freewheel mode is always 'in parallel with a voltage source when it turns-off.
1.2. RECTIFIER MODE (figures 1 & 3)
An inductance defines the dlF/dt (decreasing slope of the rectifier current) and when the rectifier switchesoff it is always in series with this inductance. This type
By J.M. PETER
of behaviour can be met in some applications such as rectifiers in flyback converters and many functions in thyristor circuits, (figure 3). Generally speaking a rectifier in the rectifier mode is always in series with an inductance L and this inductance L defines the dIF/dt. The fundamental difference between these two modes is that in the rectifier mode there is a stored energy 1/2L1RM2 due to the series inductance. After the turn-off this energy is dissipated in the rectifier and/or in the associated circuits.
1.3. TURN-OFF LOSSES
Free-wheel mode
WOFF is the energy dissipated in the rectifier during
turn-off.
f t2 Vldt (refer to figure 1)
WFR=
t1
Low voltage « 200V) fast rectifiers have a high internal capacity and the minority carriers have a very short life time. High voltage fast rectifier have a thicker N silicon layer and the minority carriers have longer life time and consequently different behaviour during the turn-off condition blocking state. (Higher IRM and fiRM - more damping).
AN37010689
1/12
75
APPLICATION NOTE
Figure 1 : Fast Rectifier: the two turn-off modes. a) Free-wheel Mode.
b) Rectifier Mode.
_....;.._.... dlF/dt
o t1 t2
dlF/dt FIXED BY THE TRANSISTOR (or by the external circuit)
LOW LOSSES IN THE RECTIFIER WOFF = K . VR . IRM TIRM (0.15 < K < 0.35)
NO OSCILLATIONS AND OVERVOLTAGE
dlF/dt FIXED BY THE INDUCTANCE dlF/dt = VRIL
HIGH LOSSES IN THE RECTIFIER WOFF = K· VR . IRM . TIRM + 1/2 L}RM When a snubber is used some of the energy is dissipated in the snubber.
ALWAYS OVERVOLTAGE AND OSCILLATIONS IN SOME CONDITIONS
5A1div. 50V/div. 0.05J.1s/div. BYT30 -1000-IF = 3A -dlF/dt = -75A1J.1s - VR = 100V - TeAsE = 25°C
2/12
76
APPLICATION NOTE
According to the experimental results the turn-off energy loss (W)FR in the free-wheel mode can be written:
(W)FR = K X VR X IRM X tlRM (1)
Max Voltage Rating (V)
K
Rectifier mode
Losses in this mode, (W)REC, are the sum of the stored energy 1/2 L IRM2 and the recovery energy (W)FR :
(W)REC = (W)FR + 112 L IRM2 (2)
In some cases, oscillations can occur. This depends on the damping due to the current tail effect after switch-off. When oscillations occur energy is dissipated during the oscillations partly in the rectifier and partly in the circuit. When snubbers are used a significant part of the energy is dissipated in the snubber.
2. PRACTICAL SWITCH·OFF BEHAVIOUR '--
The two cases, free-wheel mode and rectifier mode are simplified cases that are easy to simulate in a laboratory characterisation. In practical equipment there is always a possible overlap between the two theoretical modes, because:
Figure 2 : Rectifiers in Free Wheel Mode.
K(I) is a constant that depends on the thickness of the N type silicon layer.
1. No circuit is without parasitic inductances. 2. The rise time (or the fall time) of the switch is
not infinitely fast when compared with the rate of change of current, dlF/dt. Experimental results show that in all cases the following formula can be used:
(W)OFF= (W)FR + 1/2 Ls IRM2 (3)
Where Ls = series inductance
This important relationship is a useful tool for the designer, giving him the main parameters that influence the turn-off energy. N.B. : The following relationship (4) is only true for
the pure rectifier mode. (W)OFF = OR X VR (4)
Where OR = recovered charge
(1) K is experimental- Defined for SGS-THOMSON Microelec-
tronics fast rectifiers.
Figure 3 : Rectifiers in Rectifier Mode.
'11
L . _ ~.-+-
Vl[~I]-n.[J
L_ V2.J
--([J--
--,
·L
·
L
}-~
l_~D_
3/12
77
APPLICATION NOTE
Figure 4 : Switch-off Behaviour of the Ultrafast BYT12-400V Rectifier (current rating 12A - voltage rating
400V).
Conditions: IF = 13A dlF/dt =- 150AIIlS VR = 1OOV Tease = 25°C.
In the case of rectifier mode: l = O,6IlH. The tum-off lost energy calculated by the current and voltage is :
(W)FR = 3flJ free-wheel mode.
(W)REC = 1011J rectifier mode.
The storage energy in the inductance is : 1/2 l IRM2 = 7.5I1J.
a) Free wheel mode.
b) Rectifier mode.
The use of this equation for a lot of practical circuits can be considered as a first approximation. It leads to over estimated losses, if the rectifier does not operate in pure "rectifier mode".
3. CHARACTERISTICS OF FAST RECTIFIERS
:',',0 characteristics of fast rectifiers are the result of
...
V RRM
200
Type
Tj = 100'C dlF/dt =- 50Alfjs
VF
IRM(A)
tIRM(fjS) (V)
BYWB1 1.B
0.05 0.66 + 0.0071
Operating conditions
IRM increases with dlF/dt (figure 5).
IRM increases with Tj (figure 6).
The important points that emerge are: 1. High voltage fast rectifiers are not so fast as low voltage fast rectifiers, (comparing devices of equal current rating). 2. Tj and dlF/dt have a strong influence on the reverse recovery current.
a trade off between: Speed (IRM)
- Max voltage rating (VRRM) - Forward voltage drop (VF).
Example: 12A fast rectifiers.
400
BYT12-400 3.7
BOO
BYT12-BOO 6
1000
BYT12-1000 7.B
0.075 11 + 0.021
0.160 1.3 + 0.031
4. EXAMPLES
0.200 1.3 + 0.031
4.1. FlYBACK CONVERTER (figure 7)
The behaviour is as a pure rectifier; the rectifier is driven by a current source, the inductor, l.
For a frequency less than 100kHz the switching losses are small in comparison to the conduction losses, because dlF/dt defined by Vall is always small, (see table figure 7).
4/12
78
APPLICATION NOTE
Figure 5: Switch-off Behaviour of the Fast Rectifier BYT12P 1000 (current rating 12A voltage rating 1000V). Influence of the dlF/dt.
IRM(A)
30 r---------,---,---,-----,---,
~v~
20 t----+----t----j~ ,,~00 -v----,..--.J----j
",0<:"!!~0\0
10 1---+---- ~"c't· ~'_+.."._+----_+--_l
o
10
5A1div, 50ns/div, Tj = 25C C
Figure 6 : Switch-off Behaviour of the Fast Rectifier BYT12 1000 Influence of Ti.
One Curve Ti = 250 , one curve Tj = 600 ·
1OOV/C, 2A/div, 50ns/div Free·wheel mode
%
1OOV/C, 2A/div, 50ns/div Rectifier mode
250
0«/
200
./ VI
150
V ~ V
ioo
~--":-J.--
~
-.::-~ ?
25 50
75 100 125 150
T(Vj)(OC)
5/12
79
APPLICATION NOTE
How can the designer reducethelosses ?
1. The ratio I peakllAvG, is very unfavourable in this type of circuit. It is essential when the peak voltage is less than 200V that the "high efficiency ultra fast" family which have very low conduction losses are used. When the peak voltage is greater than 200V one solution is to use a rectifier with higher current rating.
Example: In the same circuit at 12A with:
BYTI2-800: conduction losses =7.6W, a 12A
rectifier.
BYT30-800 : conduction losses = 6W, a 30A
rectifier 2. Reduce the junction temperature. If Tj is de-
creased from 100 to 75°C the switching losses are reduced by 20%.
4.2. SMALL CURRENT RECTIFIER (figure 8)
A transformer with a leakage inductance measured
on the secondary side Ls = IIlH supplies a fast diode
D. The average output current is 0.8A and the output voltage is 48V.
The designer wants to use the popular diode BA157. This is not possible because the total power dissipation is 1.15W at 40kHz. At this frequency he can only use a popular 2A current rated diode (for O.8A rectified current) and at 200kHz there is no solution with popular diodes (see table in figure 8).
How can the designer reduce the losses? 1. Choose a diode in the "high efficiency family". For
example he can use the BYW100 for 40kHz to 200kHz, (see table figure 8). 2. Reduce the leakage inductance :with a leakage inductance Ls = O.IIlH, BY218 at 200kHz
(1.24W, L1Tj = 93°C).
4.3. FULL WAVE OUTPUT RECTIFIER
There are two different full wave rectifying circuits.
4.3.1. VOLTAGE SOURCE - CURRENT OUTPUT
Current and voltage behaviour are indicated in figure 9. The inductanceLs is the leakage inductance of the insulation transformer.
The 4 rectifiers operate in an intermediate mode between "free wheel" and "rectifier", because there are some 1/2 Ls IRM2 losses.
4.3.2. CURRENT SOURCE - VOLTAGE OUTPUT (figure 10).
In this circuit, each rectifier operates in "free wheel" mode. The series inductance does not introduce additionallosses. (This assummes there is no parasitic inductance between the rectifiers and the capacitor C).
How can the designer reduce the losses?
Figure 7 : Flyback Rectifier Output Average Current 4A. Below 100kHz the switching losses are negligible, in comparison with the conduction losses. The reason is limited dlF/dt, consequently limited IRM.
j (~-f; 20A
-11
----+~T----+-~t/T=-O.4
Pure .. rectifier mode"
IAVG + 4A
Rectifier
Vo (V)
Conduction Losses (W) Switching Losses a 50kHz (W) Switching Losses a 200kHz (W)
6/12 80
12 BYWB1-100 "High Efficiency" .
3.2 0.006 0.05
48
BYT12-400
6 0.05 0.5
100 BYT12-BOO
7.6 0.B1 5.5
APPLICATION NOTE
Figure 8 : The Popular Diodes BA 157 - BY218 are not Fast Enough for High Frequency Rectifying. The BYW100 is well adapted.
--0.8A 48V
1.6A
_
'---.J.------ '-
I<._ _l __·
t/1'=O.5
1<_ _ _ _ _ _ _1 ' ' - - _ - + 1
DIODE
IRM a 100"C dl/dt =- 20A/fiS (A)
tlRM a 100"C dlldt = - 20A/fiS (A)
(W)FR (IlJ) 1/2 Ls I~M (fIJ)
Conduction Losses (W) Switching Losses a 40kHz (W) Switching Losses a 200kHz (W)
Total Diode Losses a 40kHz (W) " Tj a 40kHz ("C)
Total Diode Losses a 200kHz (W) " Tj a 200kHz (''C)
BA157 Popular
2.8 0.14 2.08 3.9
0.944 0.2 1.3
1.15 115'
1.97 191"
BY218 Popular
2.8 0.14 2.08 3.9
0.744 0.2 1.3
0.44 71°
1.77 132 0
BYW100-200 High Efficiency
0.75 0.05 0.01 0.28
0.592 0.012 0.06
0.6 60°
0.65 65 0
a) Voltage source - current output Reduce the transformer leakage inductance. Table of figure 11 shows that in the case of the 400V 1OA 200kHz bridge circuit the suppression
of the inductance Ls can save 4 x 16.5W = 66W.
Replace in the same circuit the high voltage .fast rectifier BYT12-600 by 3 "high efficiency" BYW81-200 in series (see figure 12 - table). The total losses decrease from 186W to 58W. This result is very important as it shows it is more efficient to use several "high efficiency" ultra fast rectifiers instead of a single high voltage one for high frequency operation.
b) Both Use of sinusoidal current (resonant converter) instead of rectangular waveforms. Figure 11 shows that for the same conditions (400V - 10A 200kHz) the switching losses with a sinusoidal
current are only 4 x 7.5 =30W (4 x 22 = 88W with
rectangular wave forms).
4.4. STEP UP CONVERTER
The rectifier operates in free wheel mode. The main losses in this case occur in the transistor during the
turn-on (similar to the step down converter). Figure 13 shows that with 600V output at 40kHz, if the rectifier switching losses are reasonable, the transistor turn-on losses are too high. How can the desig ner reduce these turn-on losses? (fig. 13).
a) Decrease the rectifier junction temperature by more efficient cooling. If the BYT12-800 junction temperature decreases from 100 to 70°C, the transistor turn-on losses decrease from 39.5W to 33W.
b) To replace one BYT12-800 by 4 high efficiency BYW81-200 in series. The total balance is a reduction in losses from 39.5 to 16.6W in the transistor with same losses in the rectifier.
IN SUMMARY Two major actions reduce switching losses caused by fast recovery rectifiers:
1. APPROPRIATE CHOICE OF COMPONENT · The fastest rectifier compatible with the peak voltage in the application.
7/12
81
APPLICATION NOTE
· If the peak voltage VR exceeds 4DDV the designer must analyse carefully the switching losses: - These losses are proportional to 12RM x VR.
A 8DDV fa$trectifier has an IRM approximately two times higher than a 4DDV fast rectifier (same current rating).
Figure 9 : Voltage Source, Output Current Full Bridge Circuit.
ru + Va
CURRENT OUTPUT (CONSTANT)
INPUT [ (02 03)
I (D! 04) V (02 03)
8/12
82
Figure 10 : Current Source, Output Voltage Full Bridge Circuit
APPLICATION NOTE
CURRENT SOURCE
V (D2 D3)
(Dl D4) " ' " -I
9/12
83
APPLICATION NOTE
Figure 11 : Switching Losses (per leg) in a full Wave 200kHz Bridge Circuit. Output 10A. In case of voltage source, current output, the (leakage) inductance Ls introduces Lsl2RM losses.
In case D, the losses are smaller (6 x 4 = 24W instead of 22 x 4 = 88W) because dl/dt is smal-
ler, consequently IRM is smaller.
Ls = O.5iJH (48V) 1iJH (200V) 1.5pH (400V)
1--
Va
48
Rectifier BYW81-100
200kHz
200 BYT12-300
400 BYT12-600
[ll
(A) 1_
O.76W
5.6W
38.5W
O.16W
2W
22W
O.16W
2W
22W
O.04W
O.6W
6W
10/12
84
APPLICATION NOTE
Figure 12: Switching Losses (per leg) in the Full Wave 400V 200kHz Bridge Circuit with two Different "rectifiers". Replacing the high voltage BYT12 - 600 rectifier by 3 "high efficiency" ultra fast BYW81 - 200 in series reduces the total losses dramatically. This is why the IRM from BYW81 is very low and the voltage drop of this high efficiency rectifier is very low.
Rectifier
BYT12-600 3xBYW81-200
Conduction Losses
8
11
(W)
Switching Losses (W)
38.5
3.5
Total Losses pe r Leg (W)
46.5
14.5
F = 200kHz
Va = 400V
IAVG = 10A dlF/dt = - 120AliJs
tiT =0.5
Figure 13 : In the Step-up (or step down) Converter the Majority of Losses Occur in the Transistor, Specially when a High Voltage Rectifier is used. In some case replacing a high voltage rectifier by several faster rectifiers in series (and consequently with a lower voltage rating) can minimize the total losses despite the increase of the rectifier conduction losses.
+
lOA
tiT = 0.5
Reclifler current
VR
I
="2 [ (W)ON
dUdt + (I + IRM) tIRM]
I + lOA Transistor turn-on currenl
11/12
85
APPLICATION NOTE
Figure 13 (continued).
Vo Rectifier (dr/dt = 120A//.Is) IRM (A) (Tj = 100') trRM (/.Is) . Rectifier Conduction Losses (W)
Rectifier Switching Losses a 40kHz (W)
Total Rectifier Losses a 40kHz (W)
Transistor Turn-on Losses a 40kHz (W)
48 BYWS1-100
3.S 0.04 3.65 0.04
3.7
1.32
The rectifier voltage drop increases with the rating voltage.
Example: BYW81 "high efficiency" 200V rating VF
= 0.85V (max).
BYT12-600 600V rating VF = 1.8 (max).
IMPORTANT CONSEQUENCES:
If the switching frequency is greater than 40kHz in many cases it will be more efficient to replace one high voltage (600 - 800 - 1OOOV) rectifier by a series of ultrafast rectifiers (200V or 400V). Despite the increase of conduction losses, a dramatic reduction of 5,witching losses results in a decrease in the total losses.
2. OPTIMAL OPERATING CONDITIONS
2.1. In many cases parasitic inductance gives additional losses. A reduction of those parasitic inductances Ls decreases not only the voltage spikes but also the switching losses.
2.2. Junction temperature plays an important role. The switching losses are approximately proportional to Tj. Improving the rectifier cooling is, very-important for all high frequency rectifiers.
2.3. For full wave rectifying circuits, with an isolation transformer the switching losses are always lower in case of :
300" BYT12-400
6 0.06 6.5 0.6
7.1
1
600 BYT12-S00
10.5 0.12
S 6.7
14.7
0.7
600 4 x BYTS1-200
3.S
14.6 0.5
15.1
39.5
Current source ~ rectifying ~ voltage source
than: Voltage source ~ rectifying ~ current source
because the impedance due to the transformer leakage inductance is integrated in the current source, and does not play any part in the additional losses. 2.4. The use of the resonant circuit with sinusoidal current waveforms results in a significant reduction in the switching losses due to the limited dlF/dt or to the smaller VR re-applied voltage.
CONCLUSION
Reducing the switching losses in high frequency converters is team work.
The manufacturer has improved the fast recovery rectifier characteristics. The designer has now some tools to analyse, with a greater accuracy, the rectifier behaviour and choose the optimal solution in order to minimize the losses.
REFERENCE
111 "Switching behaviour of fast diodes in the con-
verter circuits" - p.63 to 78 in the hand book SGS-THOMSON Microelectronics "Transistors & Diodes in Power Processing".
12/12
86
SMART POWER DEVELOPMENT SYSTEM
87
.r..=,l= S~D©G[RlS@r-n1[lHJ~©O'ITMOO@S[KO!]DN©~
APPLICATION NOTE
PC-BASED DEVELOPMENT SYSTEM CUTS DESIGN TIME OF SMART POWER IC APPLICATIONS
by Thomas L. Hopkins
A Smart Power Development System allows the designer to evaluate a smart power device in the final application, such as emulator systems allows designers to evaluate and debug microprocessors.
As smart power integrated circuits become more complex they are approaching the realm where they can be considered power peripheral chips. These new devices can no longer be evaluated with a simple bench set up using a few switches and a function generator. Before the device will operate in an application, one or more registers must be programmed to set the operating conditions of the device. To speed development of applications using these devices a PC based system, the Smart Power Development System, has been developed. The SPDS allows the user to quickly develop and evaluate the device performance in a real application. This paper discusses the SPDS and shows a typical application for a stepper motor drive circuit, the L6223A.
The current generation of smart power integrated circuits contain more logic than their predeces-
Figure 1: PC-Based SPDS
sors and many, like the L6280 and L6223A, con-
tain one or more registers that must be programmed for the device to operate. This adds a new dimension to the users task who must now develop software to drive the devices before he
can start to evaluate the device operation. In addition such tasks as calculating the power dissipation and required heat sink for a power integrated circuit is a more complicated task than for discrete devices.
To assist the user in evaluating such devices the Smart Power Development System (SPDS) was developed. This PC based system consists of three parts: 1) a general purpose interface card that interfaces to the PC bus, 2) a dedicated printed circuit board for each device supported, and 3) a dedicated software package for each device supported. The block diagram of the SPDS is shown in figure 1.
HWPCI-ST
<=l ~~~ ~a~~ I
Ic{}= c{}=j 111111111111
[][][] LJJ
AN450/0190
EVALUATION BOARD
1/9
89
APPLICATION NOTE
PC INTERFACE
To allow the PC to easily drive a variety of applications, a general purpose interface ?ard was needed. The interface card chosen, Similar to the Burr-Brown· PCI 2000 Series, provides 32 I/O lines, 4 counter/timer channels, and a rate generator, as shown in figure 2.
The 32 I/O lines are general purpose parallel lines that may be programmed, in groups of 8, as either output or input lines. The 32 I/O lines plus their associated control registers are mapped, as eight bit registers, into the user address spac~ of the PC and are easily addressed by the app!lcation program. In the SPDS system these 32 lines are used as parallel outputs to drive the dedicated application board.
The rate generator provides a stable timebase for
Figure 2: SPDS Interface Card
operation of the system. The frequency. of the rate generator output is given by the equation:
8MHz
Fout
where N1 and N2 are integers between 2· and 65535. In this configuration, the output frequency can then range from 2 MHz to approximately .002 Hz. This clock signal is used by the four counter timer channels that provide the variable step rate timing used in stepper motor applications or the period of output patterns in pattern generator type applications.
This flexible configuration allows the PC interface to be independent of the device. being evaluated and provides a general ~urpose Interface that can drive many types of applications.
M I/O Port 1
U CHD-CH15
I/O Port 2
Q
LJ CHD-CH15
out J 4
Timer x4
Gate Clock Out
2/9
~ SCiS-THOMSON _ _ _ _ _ _ _ _ _ _ _ __
- - - - - - - - - - - - - - . .""!IIi1Al~~,,@~~~©'IT"@Iil~©i!l
90
DEDICATED HARDWARE
Each device, or family of devices, supported by the SPDS has a dedicated application board that connects to the PC interface card and includes the dedicated circuitry around the evaluation de-
Figure 3: Dedicated Board for L6223A
APPLICATION NOTE
vice. In the case of the L6223A the dedicated board includes two configurations for the L6223A driving a unipolar stepper m~tor, a s.ingl.e device application and a dual device application: The schematic diagram for the L6223A Dedicated Board is shown in Figure 3.
-------------
"''''!I ~ SCS·THOMSON [i;ln©oo@~~~©voo@lIIln!:$
_ _ _ _ _ _ _ _ _ _ __3/9
91
APPLICATION NOTE
This allows the user to choose the configuration that best suits his application depending on the current level required by the motor.[2] The software then allows the user to select which of the two implementations will be driven for evaluation.
Other dedicated boards support devices in bipolar stepper motor driver applications, DC motor driver applications, and solenoid driver applications.
routine calculates the step timing required to raise the step mot.or fr?m zero up to the final speed. The calculation IS made from the mechanical characteristics of the application.
The required inputs include the characteristics of the motor, specifically the static Torque (Tstat), the slope of the Torque vs Speed curve (Tslope) and the number of steps per revolution. The torque characteristics for a typical stepper motor are shown in Figure 4. In the simple model for a step-
SOFTWARE
Each of the SPDS systems includes a software package dedicated specifically to the devices. Although the features vary depending on the applicatio.n and. the specific devices, the L6223A package IS typical. The L6223A package includes: 1) calculation of the acceleration and deceleration ramps for a stepper motor, 2) a driver routine for real ti!TIe operation and 3) a simulation package that simulates the thermal behavior of the device or devices.
ACCELERATION AND DECELERATION RAMPS
per motor the torque decreases approximately linea~ly as the speed increases from zero up to the maximum motor speed where the Torque falls to zero.[1] This curve can be approximated by a
straight line having a static Torque (Tstat) and a slope (Tslope) as shown in Figure 4. Here the approximation for the torque curve allows for a Torque utilization factor of less then unitY.[1] In addition to the motor characteristics the program needs the mechanical characteristics of the system, as referred to the motor shaft. The two required values are the frictional Torque (Tfrie) and the total Inertia (Jtot). From these values the program calculat.es the period of each step during
The acceleration/deceleration ramp section the program is unique to step motor applications. This
the acceleration ramp. These values are then saved and used by the real time program to drive the motor.
Figure 4: Typical stepper motor torque characteristics
Pullout Torque (NM)
3,-----------------------------------------~
2.5
2
0.5
O L -_ _ _ _ _ _ _ _ _ _- L_ _ _ _~~~_ _ _ __ L_ _ _ _ _ _ _ _ _ _ _ _L __ _ _ _ _ _ _ _ _ __L~
o
246
8
Step Rate (Thousands Steps/Sec.)
._-- From Specification --I-- Design Target
-4/9 ------------- LV ~~~~mgr::i!~~ --------------
92
Figure 5: SPDS entry screen
APPLICATION NOTE
TEXT MOVEMENT Number
of 2 Filename: DEFTEST.DIM
RotBtion ~en~e (FW / BW )
FW
Acceleration current (100% 85% 70% 55% 40%)
100
Frequency (10 or 20 Khz )
20
Number of ~tep~ before the intermedie current
10
Intermedia current
(100% 85% 70% 55% 40%)
85
Frequency (10 or 20 Khz )
20
Number of ~tep~ of con~tent ~peed
199
Co~tBnt speed current (100% 85% 70% 55% 40%)
55
Frequency (10 or ?n Khz )
20
Oeceleration current (100% 85% 70% 55% 40%)
70
Frequency (10 or 20 Khz)
20
St~nd by current ( OPen or CLo~e loop)
CL
Stand by current
100% 85% 70% 55% 40%
40
Frequency (10 or 20 Khz)
20
Half or Full (H / F )
F
Time of ~tand by
(m.~ec)
200
FI to next movement.
ESC to go back
REAL TIME OPERATION
One major advantage of the SPDS is the ability to operate the devices in a real time application without having to first write a driver routine. In the real time operation section of the program the user defines a sequence of movements and the motion profile and operating parameters for each movement. This is done using a simple text entry screen, as shown in Figure 5. Each movement is
Figure 6: Stepper movements
divided into five segments, as shown in Figure 6. Using the motion text entry screen, the user may
define the operating conditions of the driver chip for each segment of the movement. The entry screen allows the user to select one of five current levels and the chopping frequency, both of
which are selected by programming the internal shift register in the L6223A [3], for each segment of the movement.
Speed
Coil current 100%_
86% --'::7""00-:Yo-_55%---
40% -
o
DA/OPLO
- U DNCLEV
u
------------------
~~~~~~~~~:~~~
5/9
----------------------------
93
APPLICATION NOTE
The entry screen also allows the user to define the number of steps in the first segment and the third segment of the movement. The number of steps in the second and fourth segment of the movement are defined by the acceleration ramp and deceleration ramps being used.
The final segment of the movement is the standby period, which is really the period where there is no movement between two movements. The user is allowed to select the period and operating conditions during standby. Utilizing the programmability of the L6223A,the user may select either open loop or closed loop operation during this time as well as the current level and the chopping frequency.
The user may define any number of movements in a sequence and then set the parameters of each movement. Once this definition is completed, the SPDS will continually execute the sequence programmed in real time. In the execute mode the SPDS displays some of the operating parameters of the system, as shown in Figure 7 and 11. During the execution the user may modify the step timing of either the acceleration or deceleration ramps and observe the affect on the mechanical behavior of the system.
Figure 7: Operating parameter display
Once the user is satisfied with the system operation all of the values of the acceleration ramp, deceleration ramp and motion profile can be saved on the disk for future use.
SAFE (and SAVE) DESIGN BY SIMULATION
The final section of the SPDS system allows the user to evaluate the thermal behavior of the device in the application. In this section the movement is simulated based on the average velocity, as shown in Figure 8. Using the input electrical parameters of the application and motor, the program calculates the chopping duty cycle and the effect on power dissipation due to the step rate. To these values are added the quiescent losses, which are assumed to be constant, to get find the power dissipation in the device. The program also accounts for variation in the RDSon with die temperature.
The simulation outputs two representations of the information. The first, shown in Figure 9, shows the power dissipation and required thermal impedance from the junction to ambient (Rthi-a) to limit the maximum junction temperature to a specified value versus the peak coil current (Ip). For
F 1
- Ace/Dec re~olution
10
lJ·eec
. F2 Ace/Dec reeolution a 50 1-' .. ~ec
F3 Ace/Dec re:=;olution 100 )J.:sec
F4 F5
. Stand-By re~oluti on . Stand-By·re501ution
I m. sec 10 m.~ec
I Type S to START Any key" to STOP
=> T"ce 1
ITdee I
II
- 5200 I'."ec
.
490
~lJ·sec
> Time increment
~ Time +1
< Time decrement - Time -I
iStand-by
- ! 200 m. sec
ESC to go back
6/9
-----------------------------
~~~~~~~:~~
-----------------------------
94
Figure 8: Stepper motor movement simulation
APPLICATION NOTE
Vmax Speed
J Vavg
Simulation
I(
I
I -I I
Motion Standby
L
Figure 9: Power dissipation and required thermal impedance
(UJ ("ClUJ Ptot RthJ-a 3.5G 55
2.72 44 1.88 33
1.114 22
Ip= 11.'199 II
\
Ptot= 11.918 W Rthj-a.= 42'C/W
Ptat
CONDITIONs :
Tj= 11111 'c
Ta: (,0 "C
f (oscl=2I1HHz
Sil1sle L6223 Fu II Step
Total' On board' heahink copper area:
A= 5.127 emt
11.211 11
Rthj-a (AJ
.~~~---.~--~~--~~---------------+
r - - - - 0.111 II.J2 Grid
0.55 11.77
1.1111
Step FINE
ip
re~uired values of thermal impedance less than 55 C/W (the thermal impedance of the package in free air) the power dissipation is calculated assuming a constant thermal impedance of 55°C/W. For any give!] value of current, selected by moving the cursor, the calculated value for Pd and
Rthj-a are shown on the top of the graph. The program also calculates the number of square inches of copper required on the printed circuit board to achieve the required thermal impedance, for
values that are achievable in this manner. When the power dis~ipation exceeds the level that may be dissipated in this configuration, a message that an external heat sink is required is displayed.
The second output (see fig. 10) of the simulation program calculates the power dissipation and die temperature assuming constant values of Rthj-a. For this simulation, three values of thermal impedance are chosen; the thermal impedance of
--------------------------- ~~~~~~~~:~~©~ ----------------------------7/-9
95
APPLICATION NOTE Figure 10: Power dissipation and die temperature
[UI Peak Unh=! 35 'l.
ptot
Ip = B.SSo n
3.82
2.32
IjJB= 95 ·C Pd:l8= 1.175 \I
Tj4B= 189 ·C Pd48= 1.228 \I
r-
/
TjSS= 131 ·C PdSS= 1.296 II
COHDITIOHs
Ta= bll"C {(osc) =2IlHHz Single Lb223
1.&1
Full step
Hth=3S'C/U
lUll
Rth=46'C/W
Rth=SS"C/II
S.28
[AJ
_ _ _ _l _ _ _ _ . ____....l.....-_ _ _ _ _ _ _- L -_ _ _- - - ' - - ._ _,_........l_ _ _ _ _ _ _ _·_ _ ._ _ _ _ ~
1--------_·- 6.111 0.32
B.S5 0.77
1.06
Grid
Step COnRSE
Ip
904 ESC to
Figure 11: Acceleration ramp timing
.-:-
I
TIM E ( 1 TI ME( 2 TI ME( 3 TIME ( 4 TIME ( 5 TIME( (, TI ME( 7 TIME( 8 TIME( 9
T.lME( 10 TI ME ( 11
) * 6200
--)~ 4540
) 3130 ) 2540
.)- 2200
) 1970
)- 1790 )~ 1660 )- 1550 ) ~ 1470
)- 1390
IJsec IJsec IJsec IJsec IJsec jJsec
IJsec iJsec iJsec iJsec IJsec
Number of TI MEs Fin,,] SPEED
Current SPEED FUll STEP
: 21 : 1023.62 : 161 .20
Help SlIve
Delete
Page Up/Down
Chllnge ESC to go b"ck
the ~ackage in free .air (55°C/W), the minimum practical value of thermal impedance using only copper on the PCB (40oC/W) and the minimum
practical value using an external clip on heat sink (30oC/W).[4] Each of the graphs are interrupted when the die temperature exceeds 150°C the maximum rating of the device. When the cJrrent
level selected by the cursor would cause the device to exceed the maximum rating, a message is displayed that the device will go into thermal shut down at that level.
CONCLUSION
The Smart Power Development System allows the user to quickly evaluate a smart power device in the final application, much as emulator systems allow user to evaluate and debug microprocessors. The system contains two key components that allow the user to 1) quickly define the operation of the device and evaluate it in a real time application and 2) verify that the device will operate within the its. safe operating limits. For compli-
8/9 -,-------,-----c------
LW·~~~~1:gr::n!?n
96
cated devices that require the user to program one or more internal registers before the device will operate, the system can greatly reduce the time required to evaluate the system, without requiring the user to write any specific software.
REFERENCES
1)A. Leenouts, The Art and Practice of Step Motor Control, Intertec Communications Inc., Ventura Ca., 1987
APPLICATION NOTE
2)T. Hopkins, "A Single Chip Driver for Unipolar Stepper Motors", Proceedings of Motor-Con '89 (PCIM 89). Long Beach Ca, October 1989, pp 437-445
3)"L6223A Data Sheet", Industrial and Computer Peripheral ICs databook 2nd Edition, 1992, pp 449 to 479.
4)T. Hopkins, "Designing with Thermal Impedance" Proceedings of the Fourth Annual IEEE Semiconductor Thermal and Temperature Measurement Symposium, San Diego, Ca., Feb. 1988.
b..., _ _ _ _ _ _ _ _ _ _ _ _ _ ~ SGS.1HOMSON _ _ _ _ _ _ _ _ _ _ _ _ _9_/9 I U<II~Ii:~@~~~rmr"@lil~©$ 97
STEPPER MOTORS
99
APPLICATION NOTE
STEPPER MOTOR DRIVER CONSIDERATIONS
COMMON PROBLEMS & SOLUTIONS
by Thomas L. Hopkins
This note explains how to avoid same of the more common pitfalls in motor drive design. It is based on the author's experience in responding to enquiries from the field.
INTRODUCTION
Over the years while working with stepper motor users, many of the same questions keep occurring from novice as well as experienced users of stepper motors. This application note is intended as a collection of answers to commonly asked questions about stepper motors and driver design. In addition the reference list contains a number of other application notes, books and articles that a designer may find useful in applying stepper motors.
Throughout the course of this discussion the reader will find references to the L6201, L6202 and L6203. Since these devices are the same die . and differ only in package, any reference to one of the devices should be considered to mean any of the three devices.
Motor Selection (Unipolar vs Bipolar)
Stepper motors in common use can be divided into general classes, Unipolar driven motors and
Bipolar driven motors. In the past unipolar motors were common and preferred for their simple drive configurations. However, with the advent of cost effective integrated drivers, bipolar motors are now more common. These bipolar motors typically produce a higher torque in a given form factor [1).
Drive Topology Selection
Depending on the torque and speed required from a stepper motor· there are several motor drive topologies available [5, chapter3). At low speeds a simple direct voltage drive, giving the motor just sufficient voltage so that the internal resistance of the motor limits the current to the allowed value as shown in Figure 1A, may be sufficient. However at higher rotational speeds there is a significant fall off of torque since the winding inductance limits the rate of change of the current and the current can no longer reach it's full value in each step, as shown in Figure 2.
Figure 1: Simple direct voltage unipolar motors drive.
A: L/R DRIUE
8: l.:/nR DRIUE
Us Rs
Us
AN46010392
Lc: Ic-Us/Rc t=Lc/Rc
L~ Ic-Us/CRc+Rsl t=Lc/(Rc+Rs)
f/92L6281-39 1/11
101
APPLICATION NOTE
Figure 2: Direct voltage drive. A -low speed; B - too high speed generates fall of torque.
higher voltage is used and the current limit is set by an external resistor in series with the motor winding such that the sum of the external resistance and the internal winding resistance limits the current to the allowed value. This drive technique increases the current slew rate and typically provides better torque at high rotational speed. However there is a significant penalty paid in additional dissipation in the external resistances.
-.,?.,- - ABC 0
T .... ;;:-,-;,
-
--
__ _
B
- -...- - - -
5-9]73
One solution is to use what is commonly referred to as an UnR drive (Fig. 1B). In this topology a
To avoid the additional dissipation a chopping
controlled current drive may be employed, as shown in Figure 3. In this technique the current through the motor is sensed and controlled by a chopping control circuit so that it is maintained
within the rated level. Devices like the L297, L6506 and PBL3717A implement this type of control. This technique improves the current rise time in the motor and improves the torque at high
speeds while maintaining a high efficiency in the drive [2]. Figure 4 shows a comparison between the winding current wave forms for the same motor driven in these three techniques.
Figure 3: Chopper drive provides better performance.
us
MOTOR WINDING
~ENSE
RESISTOR
119211N468-82
Figure 4: Motor current using UR, U5R and chopper constant current drive.
1.13
13.5
DRIUE
SUPPLY VOLTAGE L/R DRIVE: Vs
Ll5R DRIVE: 5Us CHOPPING DRIVE: 5Vs (not regulated)
1192L6281-48
TIME
5(L/RJ
----------------------------- 2/11
~~~~~~~~:oo~n ----------~-----------------
102
APPLICATION NOTE
In general the best performance, in terms of torque, is achieved using the chopping current control technique [2). This technique also allows easy implementation of multiple current level drive techniques to improve the motor performance. [1)
Driving a Unipolar Motor with the L298N or L6202
Alth.ough it is not the op.timal solution, design constraints sometimes limit the motor selection. In t~e ca~e where th.e designer is looking for a highly Integrated drive stage with improved performance over previous designs but is constraine~ ~o driv~ a unipo.lar wound (6 leaded) motor It IS possible to drive the motor with HBridge drivers like the L29SN or L6202. To drive such a motor the center tap of the motor should be left unconnected and the two ends of the common windings a~e c~nnected to the bridge outputs, as shown In Figure 5. In this configuration the user should notice a marked improvement in torque for the same coil current, or put another way, the same torque output will be achieved with a lower coil current.
A solution where the L29SN or L6202 is used to drive a unipolar motor while keeping the center c<?nnection of each coil connected to the supply Will not work. First, the protection diodes needed from collector to emitter (drain to source) of the
bridge transist~rs will be forward biased by the transformer action of the motor windings, providing an effective short circuit across the supply. Secondly the L29SN, even though it has split supply voltages, may not be used without a high voltage supply on the chip since a portion of the drive current for the output bridge is derived from this supply.
Selecting Enable or Phase chopping
When implementing chopping control of the curren.t in a stepper motor, there are several ways in which the current control can be implemented. A br!dge .output, like the L6202 or L29SN, may be driven In enable chopping, one phase chopping or two phase chopping, as shown in Figure 6. The L297 implements enable chopping or one phase choppi~g, selected by the control input. The L6506 Implements one phase chopping, with the reCIrculation path around the lower half of the bridge, if the four outputs are connected to the 4 inputs of the bridge or enable chopping if the odd numbered outputs are connected to the enable i~puts of th~ brid~e. Selecting the correct chopping mode IS an Important consideration that affects the stability of the system as well as the dissipat!on. Table 1 s.hows a relative comparison o! the different chOPPing modes, for a fixed chopping frequency, motor current and motor inductance.
Figure 5: Driving a unipolar wound motor with a bipolar drive
RESET
ENABLE
IN1o------------4-r~
1 IN2Q------+------~--~ -<)-+---0
H > - + - - - o IN3Q------r-----4-r~
IN4Q------+---+--~--~
5V
I-<>---+-C:::J--o 5 V
fl9211N468-8!
- - - - - - - - - - - - Gil S[iS·THOMSON ·J, 1i<Il~fi::~@~~~fi::VrnJ@II!~fi::~
C.T.
C.1.
SENSE RESISTORS
3/11 103
APPLICATION NOTE
Table 1: Comparative advantages of chopping modes
Chopping Mode
Ripple Current
ENABLE
HIGH
ONE PHASE
LOW
TWO PHASE
HIGH
n As related to L298N, L6203 or L6202.
Motor Dissipation HIGH LOW LOW
Bridge Dissipation * HIGH
LOWEST LOW
Minimum Current LOWER LOW Ipp/2
Figure 6a: Two Phase Chopping,
EN
EN ~~..,---"'
'--"""'-'-- IN2
IN2
IN 1
IN 1 o-'-+«-J
IN1.H IN2.L EN:H
Figure 6b: One Phase Chopping.
EN
EN ~~..,---"'
"'-""--'-- IN 2
I N2
INI
INt
Figure 6c: Enable Chopping.
EN IN 1
EN ~-..,---......
~",",-l-~ IN2 IN 1 ~'-T"----'
IN2
- - 4/11 - - - - - - - - - - - - LW ~~tm~r::U!~~
104
APPLICATION NOTE
RIPPLE CURRENT
Since the rate of current change is related directly to the voltage applied across the coil by the equation:
V=L.<Ji. dt
the ripple current will be determined primarily by the chopping frequency and the voltage across the coil. When the coil is driven on, the voltage across the coil is fixed by the power supply minus the saturation voltages of the driver. On the other hand the voltage across the coil during the recirculation time depends on the chopping mode chosen.
When enable chopping or two phase chopping is selected, the voltage across the coil during recirculation is the supply voltage plus either the VF of the diodes or the RI voltage of the DMOS devices (when using the L6202 in two phase chopping). In this case the slope of the current rise and decay are nearly the same and the ripple current can be large.
When one phase chopping is used, the voltage across the coil during recirculation is Von (Vsat for Bipolar devices or I . RDSon for DMOS) of the transistor that remains on plus VF of one diode plus the voltage drop across the sense resistor, if it is in the recirculation path. In this case the current decays much slower than it rises and the ripple current is much smaller than in the previous case. The effect will be much more noticeable at higher supply Voltages.
In the L6202 and L6203, the internal gate drive circuit works the same in response to either the input or the enable so the switching losses are the same using enable or two phase chopping, but would be lower using one phase chopping. However, the losses due to the voltage drops across the device are not the same. During enable chopping all four of the output DMOS devices are turned off and the current recirculates through the body to drain diodes of the DMOS output transistors. When phase chopping the DMOS devices in the recirculation path are driven on and conduct current in the reverse direction. Since the voltage drop across the DMOS device is less than the forward voltage drop of the diode for currents less than 2A, the DMOS take a significant amount of the current and the power dissipation is much lower using phase chopping than enable chopping, as can be seen in the power dissipation graphs in the data sheet. With these two devices, phase chopping will always provide lower dissipation in the device. For discrete bridges the switching loss and saturation losses should be evaluated to determine which is lower.
MINIMUM CURRENT
The minimum current that can be regulated is important when implementing microstepping, when implementing multilevel current controls, or anytime when attempting to regulate a current that is very small compared to the peak current that would flow if the motor were connected directly to the supply voltage used.
MOTOR LOSSES
The loss2es in the motor include the resistive losses (I R) in the motor winding and parasitic losses like eddie current losses. The latter group of parasitic losses generally increases with increased ripple currents and frequency. Chopping techniques that have a high ripple current will have higher losses in the motor. Enable or two phase chopping will cause higher losses in the motor with the effect of raising motor temperature. Generally lower motor losses are achieved using phase chopping.
POWER DISSIPATION IN THE BRIDGE IC.
In the L298N, the internal drive circuitry provides active turn off for the output devices when the outputs are switched in response to the 4 phase inputs. However when the outputs are switched off in response to the enable inputs all base drive is removed from output devices but no active element is present to remove the stored charge in the base. When enable chopping is used the fall time of the current in the power devices will be longer and the device will have higher switching losses than if phase chopping is used.
With enable chopping or one phase chopping the only problem is loss of regulation for currents below a minimum value. Figure 7 shows a typical response curve for output current as a function of the set reference. This minimum value is set by the motor characteristics, primarily the motor resistance, the supply voltage and the minimum duty cycle achievable by the control circuit. The minimum current that can be supplied is the current that flows through the winding when driven by the minimum duty cycle. Below this value current regulation is not possible. With enable chopping the current through the coil in response to the minimum duty cycle can return completely to zero during each cycle, as shown in figure 8. When using one phase chopping the current may or may not return completely to zero and there may be some residual DC component.
When using a constant frequency control like the L297 or L6506, the minimum duty cycle is basically the duty cycle of the oscillator (sync) since the set dominance of the flip-flop maintains the output on during the time the sync is active. In constant off time regulators, like the PBL3717A,
the minimum output time is set by the propagation delay through the circuit and it's ratio to the selected off time.
_____________ m'l SCiS·THOMSON ____________5_/1_1
·J, 1iIl1©1i'J@~~~C1fUil@IiIIO©§
105
APPLICATION NOTE Figure 7: The transfer function of peak detect current control is nonlinear for low current values.
CURRENT OUT
····· EXPECTED - - ENABLE .CHOPPING ------ PHASE CHOPPING
1192L628!-4t
REF IN
Figure 8: A Minimum current flows through the motor when the driver outputs the minimum duty cycle that is achievable.
CURRENT
ENABLE CHOPPING 18% MINIMUM DUTY CYCLE
ONE PHASE CHOPPING
'% Tchopp
1192L628t-d2 28
48
68
B8
188
For two phase chopping the situation is quite dif-
ferent. Although none of the available control chips implement this mode it is discussed here since it is easy to generate currents that can be catastrophic if two phase chopping is used with peak detecting control techniques. When the peak current is less than 1/2 of the ripple (Ipp) current two phase chopping can be especially dan-
gerous. In this case the reverse drive ability of the two phase chopping technique can cause the current in the motor winding to reverse and the control circuit to lose control. Figure 9 shows the cur-
rent wave form in this case. When the current reaches the peak set by the reference both sides of t~~ bridge are sWitch.ed and the current decays until It reaches zero. Since the power transistors
--6/11 ------------ ~ ~~~;m~~:il~~
106
APPLICATION NOTE
Figure 9: Two phase chopping can loose control of the winding current..
u
SYNC
SENSE VOLTAGE
-,-
~.:;/~................ . REFERENCE VOLTAGE
~
lJINDIHG CURRENT
are now on, the current will begin to increase in a negative direction. When the oscillator again sets the flip-flop the inputs will then switch again and the current will begin to become more positive. However, the effect of a single sense resistor used with a bridge is to rectify current and the comparator sees only the magnitude and not the sign of the current. If the absolute value of the current in the negative direction is above the set value the comparator will be fooled and reset the flip-flop. The current will continue to become more negative and will not be controlled by the regulation circuit. For this reason two phase chopping is not recommended with bridge circuits like the L298N or L6203 and is not implemented in any of the currently available driver IC's. The problem can be avoided by more complex current sense techniques that do not rectify the current feedback.
Chopper Stability and Audio Noise.
One problem commonly encountered when using chopping current control is audio noise from the motor which is typically a high pitch squeal. In constant frequency PWM circuits this occurrence is usually traced to a stability problem in the current control circuit where the effective chopping frequency has shifted to a sub-harmonic of the desired frequency set by the oscillator. In constant off time circuits the off time is shifted to a multiple of the off time set by the monostable. There are two common causes for this occurrence.
The first cause is related to the electrical noise and current spikes in the application that can fool the current control circuit. In peak detect PWM circuits, like the L297 and L6506, the motor current is sensed by monitoring the voltage across the sense resistor connected to ground. When the oscillator sets the internal flip flop causing the bridge output to turn on, there is typically a voltage spike developed across this resistor. This spike is caused by noise in the system plus the reverse recovery current of the recirculating diode that flows through the sense resistor, as shown in
Figure 10. If the magnitude of this spike is high enough to exceed the reference voltage, the comparator can be fooled into resetting the flip-flop prematurely as shown in Figure 11. When this occurs the output is turned off and the current continues to decay. The result is that the fundamental frequency of the current wave form delivered to the motor is reduced to a sub-harmonic of the oscillator frequency, which is usually in the audio range. In practice it is not uncommon to encounter instances where the period of the current wave form is two, three or even four times the period of the oscillator. This problem is more pronounced in breadboard implementations where the ground is not well laid out and ground noise contributes makes the spike larger. When using the L6506 and L298N, the magnitude of the spike should be, in theory, smaller since the diode reverse recovery current flows to ground and not through the sense resistor. However, in applications using monolithic bridge
Figure 10: Reverse recovery current of the recirculation diode flows through the sense resistor causing a spike on the sense resistor.
u
Reverse Recovery Current .....
Recirculation Current ==:>
~ S(iS.THOMSON _ _ _ _ _ _ _ _ _ _ _ _7_/1_1
- - - - - - - - - - - - - - - """"'!I i!iIn"'oo@~~~©1rIil@li!n"'$
107
APPLICATION NOTE
Figure 11: Spikes on the sense resistor caused by reverse recovery currents and noise can trick the current sensing comparator.
SYNC
Motor Current
Vref Vsense
"'1 '
"/'-
I
Expected - - Actual
_ _ _ _L -_ __
drivers, like the L298N, internal parasitic structures' often produce recovery current spikes similar in nature to the diode reverse recovery current and these may flow through the. emitter lead of the device and hence the sense resistor. When using DMOS drivers, like the L6202, the reverse
recovery current always flows through the sense resistor since the internal diode in parallel with the lower transistor is connected to the source of the DMOS device and not to ground.
In constant off time FM control circuits, like the PBL3717A, the noise spike fools the comparator
8/11
----------------
~~~~~~~:~~~
-----------------
108
APPLICATION NOTE
and retriggers the monostable effectively muitiplying the set off time by some integer value.
Two easy solutions to this problem are possible. The first is to put a simple RC low pass filter between the sense resistor and the sense input of the comparator. The filter attenuates the spike so it is not detected by the comparator. This obviously requires the addition of 4 additional components for a typical stepper motor. The second solution is to use the inherent set dominance of the internal flip-flop in the L297 or L6506 [1 ][3] to mask out the spike. To do this the width of the oscillator sync pulse is set to be longer than the sum of the propagation delay (typically 2 to 3Jls for the L298N) plus the duration of the spike (usually in the range of 100ns for acceptable fast recovery diodes), as shown in figure 12. When this pulse is applied to the flip-flop set input, any signal applied to the reset input by the comparator is ignored. After the set input has been removed the comparator can properly reset the flip-flop at the correct point.
The corresponding solution in frequency modulated circuits, is to fix a blanking time during which the monostable may not be retriggered.
T.he best V'!ay to evaluate the stability of the chop-
ping CIrCUIt IS to stop the motor movement (hold
the clock of the L297 low or hold the four inputs constant with the L6506) and look at the current wave forms without any effects of the phase changes. This evaluation should be done for each level of current that will be regulated. A DC curr~nt probe, like the Tektronix AM503 system, provides the most accurate representation of the motor current. If the circuit is operating stability, the current wave form will be synchronized to the sync signal of t~e control circuit. Since the spikes discussed previously are extremely short, in the r~nge of 50 to 150 ns, a high frequency scope With a bandwidth of at least 200 MHz is required to evaluate the circuit. The sync signal to the L297 or. L6506 provides the best trigger for the scope.
The other issue that affects the stability of the constant frequency PWM circuits is the chopping mode selected. With the L297 the chopping signal may be applied to either the enable inputs or the four phase inputs. When chopping is done using the enable inputs the recirculation path for the current is from ground through the lower recirculation diode, the load, the upper recirculation diode and back to the supply, as shown in Figure 6c. This same recirculation path is achieved using two phase chopping, although this may not be implemented directly using the L297 or L6506. In
Figure 12: The set-dominanct latch in the L297 may be used to mask spikes on the sense resistor that occur at switching.
CLOCK
t- LJr-p-AR-A-SI-Tl-C---------LJ~--------
L-~t VREF ~
I I SPIKE VRS
-t I .t
L297 REF
_____________________________ ~~~~~~~~:~~~ ___________________________9/_1_1 109
APPLICATION NOTE
this mode, ignoring back EMF, the voltage across the coil during the on time (t1) when current is increasing and the recirculation time (t2), are:
V1 = Vs - 2 Vsat - VRsense
and
V2 = Vss + 2 VF
The rate of current change is given by (ignoring the series resistance):
V=L~
dt
Since the voltage across the coil (V2) during the recirculation time is more than the voltage (VI) across the coil during the on time the duty cycle will, by definition, be greater than 50% because tl must be greater than t2. When the back EMF of the motor is considered the duty cycle becomes even greater since the back EMF opposes the increase of current during the on time and aides the decay of current.
In this condition the control circuit may be content to operate stability at one half of the oscillator frequency, as shown in Figure 13. As in normal operation, the output is turned off when the current reaches the desired peak value and decays until the oscillator sets the flip-flop and the current again starts to increase. However since tl is longer than t2 the current has not yet reached the peak value before the second oscillator pulse occurs. The second oscillator pulse then has no effect and current continues to increase until the set peak value is reached and the flip-flop is reset by the comparator. The current control circuit is com-
pletely content to keep operating in this condition. In fact the circuit may operate on one of two stable conditions depending on the random time when the peak current is first reached relative to the oscillator period.
The easiest, and recommended, solution is to apply the chopping signal to only one of the phase inputs, as implemented with the L297, in the phase chopping mode, or the L6506.
Another solution that works, in some cases, is to fix a large minimum duty cycle, in the range of 30%, by applying an external clock signal to the sync input of the L297 or L6506. In this configuration the circuit must output at least the minimum duty cycle during each clock period. This forces the point where the peak current is detected to be later in each cycle and the chopping frequency to lock on the fundamental. The main disadvantage of this approach is that it sets a higher minimum current that can be controlled. The current in the motor also tends to overshoot during the first few chopping cycles since the actual peak current is not be sensed during the minimum duty cycle.
EFFECTS OF BACK EMF
As mentioned earlier, the back EMF in astepper motor tends to increase the duty cycle of the chopping drive circuits since it opposes current increased and aids current decay. In extreme, cases where the power supply voltage is low compared to the peak back EMF of the motor, the duty cycle required when using the phase chopping may exceed 50% and the problem with the stability of the operating frequency discussed
Figure 13: When the output duty cycle exceeds 50% the chopping circuit may sinchronize of a sub-harmonic of the oscillator frequency.
SYNC ~
Vref "'..
" ....... >.~.
,,/
Expected Motor Current Actual Motor current
110
above can occur. At this point the constant frequency chopping technique becomes impractical to implement and a chopping technique that uses constant off time frequency modulation like implemented in the PBL3717A, TEA3717, TEA3718, and L6219 is more useful.
Why Won't the motor move
Many first time users of chopping control drives first find that the motor does not move when the circuit is enabled. Simply put the motor is not generating sufficient torque to turn. Provided that the motor is capable of producing the required torque at the set speed, the problem usually lies in the current control circuit. As discussed in the previous section the current sensing circuit can be fooled. In extreme cases the noise is so large that the actual current through the motor is essentially zero and the motor is producing no torque. Another symptom of this is that the current being drawn from the power supply is very low.
Avoid Destroying the Driver
Many users have first ask why the device failed in the application. In almost every case the failure was caused by electrical overstress to the device, specifically voltages or currents that are outside of the device ratings. Whenever a driver fails, a careful evaluation of the operating conditions in the application is in order.
The most common failure encountered is the result of voltage transients generated by the inductance in the motor. A correctly designed application will keep the peak voltage on the power supply, across the collector to emitter of the output devices and, for monolithic drivers, from one output to the other within the maximum rating of the device. A proper design includes power supply filtering and clamp diodes and/or snubber networks on the output [6].
Selecting the correct clamp diodes for the application is essential. The proper diode is matched to the speed of the switching device and main-
APPLICATION NOTE
tains a VF that limits the peak voltage wit~in the allowable limits. When the diodes are not integrated they must be provided externally. The diodes should have switching characteristics that are the same or better than the switching time of the output transistors. Usually diodes that have a reverse recovery time of less than 150 ns are sufficient when used with bipolar output devices like the L298N. The 1N4001 series of devices, for example, is not a good selection because it is a slow diode.
Although it occurs less frequently, excess current can also destroy the device. In most applications the excess current is the result of short circuits in the load. If the application is pron to have shorted loads the designer may consider implementing some external short circuit protection [7].
Shoot through current, the current that flows from supply to ground due to the simultaneous conduction of upper and lower transistors in the bridge output, is another concern. The design of the L298N, L293 and L6202 all include circuitry specifically to prevent this phenomena. The user should not mistake the reverse recovery current of the diodes or the parasitic structures in the output stage as shoot through current.
SELECTED REFERENCES
[1]Sax, Herbert., "Stepper Motor Driving" (AN235)
[2]"Constant Current Chopper Drive Ups StepperMotor Performance" (AN468)
[3]Hopkins, Thomas. "Unsing the L6506 for Current Control of Stepping Motors" (AN469)
[4]'The L297 Steper Motor Controller" (AN470)
[5]Leenouts, Albert. The Art and Practice of Step Motor Control. Ventura CA: Intertec Communications Inc. (805) 658-0933. 1987
[6]Hopkins, Thomas. "Controlling Voltage Transisnts in Full Bridge Drivers" (AN280)
[7]Scrocchi G. and Fusaroli G. "Short Circuit Protection on L6203". (AN279)
----------------------------- ~~~~;~g~:~~ --------------------------1-1-/1-1
111
APPLICATION NOTE
USING THE L6204, A BIPOLAR STEPPER AND DC MOTOR DRIVER IN BCD TECHNOLOGY
by E Balboni
Containing two H-bridge drivers, the L6204 is a compact and simple solution for driving two-phase bi-
polar stepper motors and in applications where two DC motors mustbe driven.
The L6204 is a DMOS dual full bridge driver mainly designed to drive bipolar stepper motors. All the inputs are TTL/CMOS compatible and each bridge can be enabled by its own dedicated
input. The windings current can be regulated by sensing the voltage drop across two low value resistors at the low end of both the bridge: this is the feedback for the current controller. To feed
the gates of the upper DMOS, a peak to peak rectifier charges a capacitor in series with the Power Supply voltage at the optimum DC level defined by
an on-board square wave oscillator. The L6204, with 0.5 A drive capability without extemal heatsink
up to 70De, is packaged in a 20 leads PowerDip
with four heat transfer pins. The Block diagram of
the device is shown in fig.t.
Figure 1: Block diagram of the L6204 single chip dual full bridge driver.
VBOOT
'" ...
I..-. I-
m :::J:::J
:::>
00
'" ...
'm"
I::-:J::I:-J
:::>
00
INt
ENABLE 1 IN2
BOOTSTRAP OSCILLATOR
SENSE 1
IN4
" - - - - - - - 1 - - - - - 4 - . - - < 1 ENABLE 2 IN3
L6204
GNO
SENSE 2 1f9BL62D.t-Bt
AN379/0690
1/7
113
APPLICATION NOTE
GENERAL APPLICATIONS HINTS
The L6204 can be used in a very wide range of applications such as the drive of lamps, solenOids, DC motors or any other inductive loads. The drive of different loads in single-ended configuration is shown in fig.2. The current in the Load Z1, that may be a DC motor, can flow in both the directions but its peak amplitude cannot be controlled. By means of a change of the Duty
Cycle of the input signal it is possible to vary in Open Loop Mode the steady state speed of the DC motor: this is possible because the average current in the winding is dependent from the Duty Cycle. The UR ratio must be a few times shorter than the minimum DC. In a similar way it can be dimmed a lamp connected to the supply (Z2) or to ground (Z3). Very often, when a DC motor is driven, peak current and speed must be booth controlled in a Closed Loop Mode.
Figure 2: The L6204 is not intended only for Bipolar Stepper applications: here above three different driver configurations are shown. Z1 is a DC motor to be driven in both CW and CCW direction. Z2 can be solenoid like a relay or hammer. Z3 can be an alogen lamp which light intensity is controlled by variable Duty Cycle.
100nF D2
D1
}2I12
Us
C3 10nF
28 EN(Zl) <>----03
11 17.14 7 8
EN(Z2:Z3)
r---018
1 } IN.L
+-·--04
L6204
5.6
11
Z1 1 2 19 15.16 9
Hl
13 12
13 1},
L
IN.H
uS/21
IN(ZU IN(Z2) IN(Z3)
(H: l)
(l)
(H)
1198L6284-85
This is achieved by the configuration shown in
fig.3A. The two independent motors (A and B) can be controlled by only one controller (L6506). The sensing resistor (RsA, RsB) generates a voltage proportional to the motor current, that is the
feedback for the current control loop. A second loop, not shown in figure, can control the speed stability while the direction is defined by the Input stat~ Of. t~e L6506. The Enable Input (ENA, ENB) can inhibit one motor or the other while the Power Enable acts on both at the same time. D1 and D2
(BAT41 or equivalent), C3 and C4, generates the bootstrap voltage by rectifiing the wave available
at pin. 11 of the L6204. When more than one driver is used at the same Supply Voltage on a common Printed Circuit Board, the bootstrap voltage can be generated only by one of them (mas-
ter) and used to supply all the other L6204 (slaves) saving diodes and capacitors. R1 C1 (R2
C2) is a snubber network that must be closely connected to the output pins and its use is recommended in all the application circuits using the L6204. The values can be calculated as it follows:
R = Vs/lp and C = Ip/(dV/dt), where Vs is the
maximum Supply Voltage of the Application, Ip is the peak of the load current and dV/dt is the Slew Rate accepted as the optimum compromise be-
tween speed and transient generation/radiation (SR of 200 V/!lS are commonly chosen). The network R5C5 sets the operating frequency according to f = 1/(0.69 R5C5) for R5 2 10Kohm. R3
!3-n9 R4 are used to protect the comparator input inside the L6506 against possible negative transi-
tions across the sensing resistor RsA or RsB. The L6204 can be used with paralleled inputs and outputs to double the current capability of the single bridge; for an optimized solution, however, 1.6 times the nominal current is recommended in-
-2/7 - - - - - - - - - - L.,/ SCiS·1HOMSON - - - - - - - - - - ·], ~oli::rnJ@rn~rnt1lrnJ@OOO!;~
114
APPLICATION NOTE
stead of two. This configuration is shown in fig.2 to drive the load Z1. A more complex circuit, in wich one paralleled L6204 drives a DC motor, is
shown in fig.3B; in this example the two chopper of the L6506 are used to implement two functions: 1) Current Control during speed variation at Ip max = O.SA and 2) Current Control during brake and/or direction change at higher current level that depends from the brake repetition (it must be
in the Max Ratings limit). The divider R6R7 defines the brake current intensity as V17/Rs while the product (Ip max.) x ( Rs) is the limit of the reference voltage V16 for speed control. The Enable function is driven via the L6506 . Since during the brake time the Enable of the L6506 is chopped, the motor current ricirculates via the Supply; because of this a suitable large capacitor must be connected in parallel to C2.
Figure 3A: Bidirectional DC motor drive. The L6204 can drive two motors.
ENABLE A A
CURRENT lIo SPEED A DIR A
Us
C3 1139nF
C5:I: 199nF
D1
D2
C4 19nF
3 17 4
28
11
L6204
14 8 7
ENABLE B B
18 2 19 1
5.6
13
15.16 18 12 9
R3
R4
22K
22K
14 13 16
5
6 18
18
15 11 12
17
L6506
7
8
1
9 2 3 4
CURRENT lIo SPEED B
OIR B
Ucc
POWER ENABLE
N9BL 62B" - 86
----------------------------JC~I ~~~~~~~:~~~ ---------------------------3/-7
115
APPLICATION NOTE
Figure3B: Bidirectional. DC motor drive. The L6204 can drive the !!l0tor in a parall~led configu~ation w~ile the L6506 provides the peak current control both dUring normal rotation and dUring braking time.
R1
11313nF
Us
14 4
18
7
13 213
11313nF ::I: C2
17
L6284
5.6.15.16 2 19 1 18
11 3 8 9 12 113nF
22K 22K
R2 R3 RS R4
Uee 22K R5
3.3 C5 nF
C6 ::I: 11313nF
14 18
1 9 7
18
15 12
13
4
L6586
6
5
17 8
U17
R6
R7
11 2
3 16 U16
Uref (SPEED)
EN DIRECTION
1199L6294-97.
Stepping Motor Driving
The drive of one stepping motor is shown in fig.4, where the controller L297 generates the requested signals to drive the motor in Half-Step Mode or in Full Step Mode. The rotation speed or step change is controlled by a clock signal or a single clock pulse at pin.18 (CK). The Mode depends from the logical state of
the H / F input while the state of the CW/CCW input defines the direction of the rotation. Depending on the numbered state, odd or even, of an internal clock pulse at the moment at wich the Full-Step Mode is selected, the motor is driven with two-phases-on or with one-phase-on respectively. An open collector output (home) indicates the translator state 0101 that occurs only during an odd numbered state of the internal clock.
-------------- "..,,1 4/7
~ SGS·1HOMSON _ _ _ _ _ _ _~_ __
1ibJ~1:1iiI@~~~I:1i'IiiI@Iil~©@
116
APPLICATION NOTE Figure 4: Bipolar stepping motor drive: phase sequence generation and current peak control are achieved
by means of the controller L297.
o STEPPER MOTOR
C1 R1
C2 R2
4
18 7
13
6
16 15 17
5
L6204
14
1
20
18 RS8
2 3 19 9 8 12 11 18nF
R4
22K
Uss
13
22K 14
R3 RSA
4 5 6 7 8 9
180nF
12
I--.
L297
C7 R5 22K
2
16
1 15 18 28 19 18 17 11 3
C5:r: 3. 3nF
I- 4- Z l- LL ~ :3 ....J I-
::l 0
Q) L
W
" W
U
(f) :::c
U
u
0
::l
a:: 0
:::>
w
u z
a::
":3 Iz- W
u 0 E:
>-
U
0
(f)
:::c
ff98L6284-B8
This last is obtained from the oscillator the frequency of which is fixed by the ratio 1/0.69 R5C5 about (R5 2: 10Kohm). The peak of the chopped current is given by the. ratio of the reference voltage at pin.15 and the value of the sensing resis-
tors Rs. When the four phase signals needed at the inputs of the L6204 are generated in any other way than by the L297. (for example, via IlProcessor), the motor driver needs one interface to control the peak current. One possible solution is shown infig.5.
____________ - - - - - - - - - - - - - L"'!I ~~~;m~r::~~~
5~/7
117
APPLICATION NOTE Figure 5: The.L6506 can be used to control the peak current in the windings of a bipolar stepper motor.
The power is supplied by the L6204.
STEPPER MOTOR
4 6
18 7
C6
13
16 15
17
5
ENA
3
L6204
118
2
19
9
12
RS2
R4 22K
22K
15 14 13 12 11
18
R3
RS1
L6506
14 D2 C3
28 C4 D1
8 11 18nF
ENS
Uss
188nF
18
b..
C7
R5 22K
22K Uss
R6
1
C5::J: 3. 3nF
PHASE INPUTS
ff9BL62B4-B9
The motor can be driven in the Full-Step or in Half-Step Mode. The chopped current Ip is controlled at the value Vref/Rs where Vref is the output voltage of the divider R6 R7. The pins 16 ·and 17 (reference input voltage of the controller)
can be driven with two different signals. This arc
rangement allows to keep constant the motor current a~d the torque during the Half-Step Mode revolution of the stepper. This behavior is well explained by the fig. 6.
6-/7-~-----------------------L~I ~~~1tl?~:~~ ---------------------------
118
APPLICATION NOTE Figure 6: Characteristics of the Half - Step Mode drive with constant torque control. It should be noted that
the resultant current is constant while the current in the windings alternates between one-phase-on and two-phase-on with a ratio of .,,[2.
B . Ip
(RESULTANT
HALF STEPS PHASE ON
Uref pin 16{ (PhA)
Uref pin 17{ (PhB)
B
8
8
8123456 78
AB A AS 8 BA A AB B AB PHASE PEAK CURRENT PHASE REDUCED CURRENT
ZERO CURRENT PHASE PEAK CURRENT PHASE REDUCED CURRENT
e ZERO CURRENT
PHASE CURREN{PhA DIRECTION
DEFINED BY
THE INPUTS PhB
"!18L6284-18
------------- ------------- L." ~~~;m~~:~~lt
7/7
119
APPLICATION NOTE
BIPOLAR STEPPER MOTOR CONTROL
This application note is intended to provide design details for the implementation of a stepper motor control, built around the TEA3717.
This integrated circuit has been developed to offer control and current regulation of up to 1A, in one winding of a bipolar motor.
Two TEA3717s and a minimum of external components are sufficient to implement the full control function of a two-phase bipolar stepper motor.
The system can be commanded, according to the desired mode of operation, by either fixed or programmable logic.
FUNCTIONAL DESCRIPTION
The circuit is organized around a H-bridge configurated by four transistors and their integrated free wheel diodes.
The "Phase" input controls the switching of the bridge transistors and also determines the direction
By Pierre PAYET BURIN
of the current flow in the winding. The signal applied to this input is first gated through a Schmidt trigger and then through a delay element so as to avoid a simultaneous conduction of transistors when direction of current in the bridge is reversed.
Regulation of winding current is performed by chopping action on the power supply for a duration toff determined by a monostable.
This monostable is triggered by the output level swing of a comparator, to the input of which a voltage proportional to delivered output current is applied.
The current spikes corresponding to the diodes reverse recovery time are filtered by a low pass filter Rc Cc to not trigger the comparator.
Three comparators are available for this purpose: their thresholds are internally fixed ratios of VR input voltage. Each of them can be selected individually by using hand 10 inputs.
Figure 1 : TEA3717 Block Diagram.
AN266J0189
1/12
121
APPLICATION NOTE
Figure 2 : Typical Operating Sequences.
PhA r
rH, M, l · - - - : f - - - - - ~ - - - - - - - - - - - - - - - - - - - - -
~--...:.-:
: "'-,
fd : toff 'ton;
I
"-
I
I
2
3
4
5
VCH, M.l - - -
n-_. n-- . 11-- ___ 11 Vc
v~···'t;/l--
;~j c __
2
H
1
_ _ Direction of current flow
4
Transistors of the bridge are represented by switches: - switch open: transisto r cut-off - switch closed: transistor saturated
2/12
122
APPLICATION NOTE
CONTROL OF BIPOLAR TWO-PHASE MOTOR The proposed diagram features two TEA3717s each controlling one winding. FUll-step and fraction-of-a-step operation is performed by combined use of phase and current level selection control inputs. Figure 3 : Control of a Bipolar Two-phase Motor.
t'i" 9'"
I
:::
u u
>
o z
~
CJ
~
~
~
1---"'------11·
M '_"
C;;
w
"'
1:
0 a
E
i
~
>
..a
'" >
M
11
u. 0.
~
U. 0.
&l
E
> +
E
C;;
M ::
~
>
o z
CJ
t---1r-------II·
~
~
~
.0 -
.-
~ ~
M
<t
:::
w
l-
S
u. c
; <t « 9
3/12 123
APPLICATION NOTE
Figure 4 : Winding Currents for Rotation in Full-and Micro-steps.
: Currents flowing through motor windings. : Current thresholds selected by 10, I,. : any of IH, 1M or IL values.
10
11
I
1
1
0
0
1
1 L
1
0
1M
0
0
IH
N° of steps
IA
18
1
2 3 4
Full step.
1
1
1
-I
-I -I
-I
1
N° of steps
IA
18
1
I
I
1M
IL
I
a
1M - IL
2
I
-I
1/4 step.
N° of steps
IA
Is
1
2
1/7 step.
I
I
IH 1M
1M I L
IH
IL
IH - IL
1M - IL
IH 1M
I
-I
4/12
124
N° of steps
IA
18
1
I
I
I a
2
I
-I
0
-I
3
-I
-I
-I
0
4
-I
I
0
I
1/2 step.
N° of steps
IA
18
1
I
I
IH
1M
IH
IL
IH - IL
IH - 1M
2
I
-I
1/5 step.
N° of steps
IA
18
1
2
1/8 step.
I
I
IH 1M
1M IL
IH
IL
I
0
IH - IL
1M - IL
IH - 1M
I
-I
N° of steps
IA
18
1
I
I
1M
IL
1M - IL
2
I
-I
1/3 step.
N° of steps
IA
18
1
2
1/6 step.
I
I
IH
1M
1M
IL
I
0
1M - IL
IH - 1M
I
-I
APPLICATION NOTE
FULL-STEP OPERATION:
This is moto's typical mode of operation. Simultaneous power supply to both windings guarantees availability of maximum torque.
"Phase" inputs determine the direction of current
flow in the windings, while inputs 10 and i1 at a con-
stant level, select the level of this current. This is the
simplest type of control implementation.
Figure 5 : Signals to Provide to Controller for Full-step Rotation.
L
PhS 1'-_----'
lOA,S 11A, S
~--------------------~--~~~~~--------------------~~~
2
3
1 . Motor not controlled. 2· Rotation of 7 steps @ IH max. current. 3· Rotation of 6 steps @ IL low current.
HALF-STEP OPERATION:
This mode allows to double the motor resolution and also to eliminate certain vibrations. Power is applied altemately to one winding and then to both. In halfstep position, where only one winding is powered,
torque available on motor spindle is at its lowest
value.
.
Same control signals as those used for full-step
operation are applied to "phase" inputs, and 10, i1 in-
puts are used to annul the current in one winding.
5/12
125
APPLICATION NOTE
Figure 6 : Signals to Provide to Controller for Full-step Rotation.
PhA
PhB
IDA
n
n
n
n
11A
n
n
n
n
lOB ~
n
n
n
n
lIB ~
n
n
n
n
OPERATION (a IH
I PhA
PhB
IDA
11A
n
n
n
n
lOB
lIB ----1l
n
n
n
n
OPERATION ra 1M
I PhA
PhB
IDA
II
n
n
n
IIA
lOB - I I
II
n
n
n
lIB OPERATION ra IL
6/12
126
APPLICATION NOTE
MICRO-STEP OPERATION:
Micro-steps of up to 1/8 are obtained by implementing the flow of different supply current levels through both windings.
This type of operation may be envisaged if a good rotational regularity is required.
Some factors reduce the positioning precision of micro-steps: _ difference between theoretical value and avail-
able value for winding current, _ comparator threshold levels dispersion, _ motor winding characteristics dispersion. These factors don't affect full-step position
Figure 7: Signals to Provide to Controller for Rotation in 1/8th of a Step.
PhA
Phil
118
CHOICE OF OPERATING FREQUENCY
Motor's rotational speed is determinated by the frequency of PhA and Phs signals.
This speed is limited by the mechanical characteristics and the time constant of L, r circuit formed by the winding.
Figure 8 : Phase Currents for two Differerits Speeds.
The rate of current increase in the winding depends on Vmm . Thus, if operation at maximum speed is desired, itwould be a good practice to work with high supply Voltages.
I'hA _ _ _- - '
f ,- fmal(
7/12 127
APPLICATION NOTE
= = h 10 Ph COMMAND
Simultaneous application of control signals to three inputs Ph, hand 10 (or to Ph and one of 1inputs while the other is it at high level), is used for half-step operation or unipolar mode.
It must be ensured that the time t during which Ph = h = 10 = 1 is higher than the time t min required to annul the winding current.
Figure 9: Operation with Ph = 11 = 10.
If while the current is still positive, control signals
Ph : 10 = h = 1 are applied to corresponding inputs,
diode 02 or 03 will conduct and cause 01 and 04
to be turned-off, which prevents the current rise in the winding and disturbs the proper rnotoroperation.
Blocking of 01 and 04 is performed by a built-in pro-
tection unit and prevents the parasitics generated
by the conduction of 02 and 03 to cause any short-
circuit within the bridge.
.. ~
-T .
ro~
~L-______~r-lL________
11
~
'"Mt??:~,t:
a} oorrect operation: T > T min
b) incorrect operatktn : T < Tmin
~03
~
!
!
2
2
if ~
~
1
~
T
3
4
4
5
Normal circuit operation - . . . Direction of current flow.
1b. 2b 3b :
Identical to 1a. 2a Q1 cut-off due of conduction of D3. Slow decrease of current since. VMS - VMA:::: 0 instead of being - Vmm.
4b _ 2b
5b_ 3a 6b_1b.
~l
3
6
8/12 128
APPLICATION NOTE
CHOICE OF TOFF : SWITCHING TIME FOR CURRENT REGULATION
The value of toff determines the quality of the current regulation inane phase.
The larger the toff. the more important is the current ripple.
Value of toff is found from the expression toff = 0.69 Rt.Ct where 1kQ :0; Rt:O; 100kQ
Figure 10: Winding Current@ off (max).
A suitable value of toff for the majority of applications is 30l-1s.
*toff(max)
This is the loff value over which the ripple value becomes excessive Let's k be the desired ripple value and t = Llr. the time constant of motor winding. then: toff(max) is given approximately by : toff(max) ~ kt
tH,M, L tmin
IH, M, L - Imin
k~
IH. M. L toff(max) = kt
I
I
I
',..
It'
toff(max)
L
t~
9/12 129
APPLICATION NOTE
*tolf(min)
This is the limit under which the current regulation IS not guaranteed.
Even if the current continually exceeds the threshold levels IH, 1M or IL, the device will ensure a minimum conduction time ton(min) which is combination of two periods;
- td : comparator trigger time and transistor desaturation time implosed by TEA3717
Figure 11 : Winding Current @ TOFF(MIN).
- t'd ; this is the time required by Vc to reach the comparator threshold level and is determined by low pass filter Rc, Cc.
Therefore, toll must be selected to be long enough to allow the current to fall to a level below IH, 1M or IL.
Supply voltage Vmm and winding characteristics both determine the value of toll(min).
toff totflmin)
toff" Inllimini
Figure 11 Bis: Winding Current, VE and Vc Voltages @TOFF(MIN) .
·
't
.' ·
Innfnllll;
VE and Vc
at
-- vr
-~. - Vc
VCH.M.L __ __ ___ _
. \
.
\
\
\
\
L -_ _ _ _ _ _L -_ _---=l.-_\.\._ _ _ _ _~_ ___>~~ . _______- - - .
10112 130
APPLICATION NOTE
SELECTION OF Rs VALUES
Three values of motor current IH, 1M and IL are determinated by the choice of Rs and VR values.
The value of Rs is calculated such that VCH = Rs.IH
50.42
where VCH =
VR and IH is the maximum motor supply current.
A choice of Rs value around 1Q will guarantee a fast increase of the winding current and offers the possibility of operation with a voltage around 5 V for VR, and thus is suitable for most applications.
Figure 12: Continuous Variation of Current Level.
It is also possible to vary the motor current in a continuous mode: _ by VR adjustment _ by feeding back a portion of the voltage drop
across Rs through a potentiometer whose wiper is connected to the comparator input.
In order to minimize the differential voltage VE - Vc due to comparator's input current, care must be taken to avoid the appearance of a large impedance between E and C terminals. Appropriates values of
P and Rc would be : P = 1 kQ and Rc = 470Q .
TEA3717
c
11/12 131
APPLICATION NOTE
CABLING
Since the essential
toTEtaAk3e71p7arotipcuelraartecsabinlinsgwiptcrhecamuotidoe~sitsios
~s to avo,id the generation of interferences suscep-
tible to disturb the correct operation of the control
electronics,
Recommended precautions are: _ Separated ground connection for Vmm supply
Figure 13: TEA3717 PC Board Layout.
_ Connection link between RS and the TEA3717
must be kept as short as possible _ Decoupling of Vmm by a ceramic capacitor (15 to
150nF) directly connected to the TEA3717 and also by an electrolytic of higher value: 10 to 22~F, _ Decoupling of Vee,
Vmm GND (Veel GND (Vmml
VCC
"n1
::
RS
1
=-~ TEA ~
3717
I
8
9
PI1~
LOGIC
11~
CIRCUITS
LOGIC CIRCUITS
10~
I
I
CORRECT LAYOUT
Vmm GND
VCC
~
1
16
I
Ph~
LOGIC CIRCUITS
11 t--
10 t--
I
r- TEA 3717
8
9
INCORRECT LAYOUT
LOGIC CIRCUITS
I
12/12 132
APPLICATION NOTE
SHORT CIRCUIT PROTECTION ON L6203
With devices like L6203 used as driver often interfacing the external world by means of wires, can be easy to have short circuits.
A short circuit can occur for many reasons: a short on the load, a mistake during the connection of the wires between the device and the load (i.e. L6203 driving a motor), an accidental short between the wires and so on.
The outputs of L6203 are not protected against the short circuit and if a short occurs, the big amount of current flowing through the outputs can destroy the device.
By G. SCROCCHI and G. FUSAROLI
To avoid this risk can be useful to add a circuitry to protect the device: in this case, to have a total protection, we must consider three types of short circuit:
1 - output to output short circuit 2 - output to supply voltage short circuit 3 - output to ground short circuit
The first step is to sense the short circuit current. In output to output (fig 1) or output to supply (fig 2) short circuit can be used the sensing resistor (Rsl) already used to set the current flowing in the load during the normal operation.
Figure 1.
Us
OUTPUT
SHORT - C I RCU IT
rt=====*=::!:'..o LOAD
Figure 2.
1188L62B3-0;'
Us
Us
SHORT - CI RCU IT OUTPUT TO SUPPLY
I.OAD
AN279/0189
1/3 133
APPLICATION NOTE
To sense the output to ground short circuit (fig 3) another sensing resistor (Rsu) must be added between the supply pin and the supply voltage. Figure 3.
Us
The second step is to create a threshold over which the value of the current must be considered as short circuit: for this way a transistor or a diode could be used. The complete protection will be given by the' or ' of
Figure 4.
the signal coming from the upper and the lower sensing circuitry; this signal can be used to act on the ENABLE pin of the L6203 disabling the output stages. A complete protection schematic diagram is shown in fig. 4.
Us
2N29B7A
RSU 11. Hl
2
5
3
INl
+5
7
IN2
L6203
11 EN
DUH
I I
9LDAD
TLS1B6-B5 22.,
I
6
DUT2
0
lB TO L297
lN4148
68
8.1650
0
RSL
t188L6283·18
2/3 134
APPLICATION NOTE
In normal operation the circuit works up to 3N40V. When a short circuit occurs the SCR is triggered and L6203 disabled: due to the SCR memory L6203 is kept disabled until the power is switched off and then on, if the cause of short was removed.
The short circuit is detected when:
Isu > VBE(T1) = ..Q.:.§. = 6A
Rsu 0.1
ISL> VD + VTHSCMT = 0.6 + 0.7 = 7.BA
Rsc
0.165
The effective short circuit peak current is greater than Isu and lsi: this is due to the high dl/dT during the short and to the delay between the short circuit detection and the ENABLE intervention:
Rsu and Rsl must be non inductive resistors.
Figure 5.
R1 and R2 are used to scale the signal when the transistor goes on and in conjunction with C1 to filter the short circuit signals in order to avoid false trig ger of the SCR : this filtering should not be too much heavy to avoid to introduce an excessive delay in the short circuit loop.
Isu and lsi must be calculated at the effective operating temperature being the Vbe and Vd temperature dependent.
Instead of the SCR, a monostable with a long time constant (0.3 ... 0.5 sec) can be used: in the case, every time a short circuit occurs, L6203 is disabled for the monostable time constant and then enabled, if the short is still present L6203 is disabled again, if the short was removed L6203 returns in normal operation (fig 5).
Us
2N2987A
5
3
IN1
IN2
MONOSTADLE ..--+--.-IT' i74HC1231 Q
L5283
11 EN
8.3 to 8.~5ec
6
18 lN41A8
OUT1 OUT2
Icc ~
/\
IISU. ISL)
I EN
n
OUT~
OUT OFF
0~--~=-~~--~~ OUT OFF NBSL 6283 - 11
R1, R1, C1, Rsu, RSL are choosen depending on the application.
The intervention of the protection circuit is determined by
VSE Isu> --
Rsu
VD = VDIODE
VIH = min Vlnput High T+ Monostab
ISL
>
V1H + VD
-:=---
RSL
3/3
135
APPLICATION NOTE
CONTROLLING VOLTAGE TRANSIENTS IN FULL BRIDGE DRIVER APPLICATIONS
In applications that involve fast switching of inductive loads, designers must consider the voltage transients that are generated in such applications. To insure a reliable design, the voltage transients must be limited to a level that is within the safe operating conditions of the switching device. This application note discusses the sources of voltage tran-sients in full bridge applications and techniques that can be used to limit these over-voltage conditions to safe levels. Special attention will be given to applications using monolithic implementations of full bridge circuits like the SGS-THOMSON L6202 and L6203.
by Thomas L. Hopkins
exceed 60V. Therefore, the maximum ratings that must be considered for the application are:
Vsupply
60V
Vds any output 60V
V01 - V02 :
60V
Similar maximum ratings will exist for any full bridge application, with the exception of the differential output voltage limit, which will not exist for discrete implementations.
Figure 1 : DC Motor Drive Circuit using L6203.
MAXIMUM RATINGS
The maximum voltage rating for the bridge driver can be derived from the maximum ratings of the devices used in the output stage and are generally the BVceo or BVdss of the power devices. In addition to the maximum allowable voltage across the output device, additional limits may be needed on the maximum output voltage above supply or below ground, depending on the implementation of the output stage.
As an example of a full bridge circuit, consider the SGS-THOMSON L6202 and L6203. These devices are full bridge drivers implemented with DMOS transistors on a monolithic structure. Using these devices full bridge drive circuits, like shown in figure 1, are easily implemented. The device has a maximum rating for the supply voltage of 60V, which implies a maximum BVdss forthe output devices of 60V. In addition, due to the monolithic implementation, the voltage between the two output terminals must not
CONTTOROL{ LOGIC
e.22uF
L5282/L5283 lis OUT 1 t-.~---, INl
I N2
libl
EN
lib2
ff88L6287-Bli
AN280/0189
1/7
137
APPLICATION NOTE
SOURCES OF VOLTAGE TRANSIENTS
To protect against the over-voltage that may occur as a result of the inductive property of the load, voltage clamps are normally employed to limit the voltage across the output devices. In bridge applications these clamps are normally a diode bridge that clamps the voltage to one diode drop above supply and one diode drop below ground. However, if the diode switches slower than the transistor, there is a short time where neither the transistor nor the diode is conducting and the voltage rise is limited only by the capacitance on the node. The result is that a vol-tage overshoot occurs during the time before the diode turns on. When the bridge is build with DMOS power transistors, the intrinsic body diode is often used as the clamp. This is true for the L6202 and L6203. As can be seen in the figure 2, the turn-off time of the DMOS device in the L6203 is in the range of 25 to 50nS while the turn-on time of the intrinsic drain to source diode is in the range of 150nS. This difference in switching time is characteristic of many DMOS devices.
Figure 2 : Output Switching Waveform for L6203.
the current flowing in these parasitic inductances is rapidly switched, the inductive property of the wire causes a voltage transient. When large currents are rapidly switched, as with DMOS transistors, large voltage transients can be induced across even small parasitic inductances. For an inductive load driven by an H-Bridge the change of current in the power supply lead is equal to twice the load current when the bridge is switched off or the bridge is switched from one diagonal pair of transistors being on the other pair. Here switching the bridge results in a change of direction of current flow in the power leads. The time that it takes to switch the current is essentially the turn off time of the output device. In this case the resu Iting voltage across the inductance is given by the equation:
v= Ldildt= ~ (1) Toff
Figure 3 : Parasitic wiring Inductances in DC Motor Drive Circuit.
WIRE INDUCTANCE IN1
L52B2/L62B3 Us DUT 1 h r - - - - ,
I N2
Ub 1
EN
Ub2
The second main factor contributing to the transients is the parasitic inductance in the wiring or printed circuit board layout. Figure 3 shows the parasitic inductances in the DC motor application. When
2/7 138
APPLICATION NOTE
In fast switching applications, like the L6202, where the switching time is as short as 25nS, the induced voltage spike can become quite large, For example if the DC motor in figure 3 was driven with 4A and the bridge was switched off, a parasitic inductance of only 15nH would produce a 5V spike, Since the current is reversed in both the supply and ground leads the device would see a 1OV spike between the power supply pin and chip ground, if the inductance of both wires were the same,
As a design example, consider a DC motor driver shown in figure 1 with the following system characteristics :
Supply Voltage
Max 46V Min 38V
Peak Motor Current 5A
Chopping Frequency 50kHz
Figure 4 : Enable Input and Motor Current for Examples,
For evaluation, the motor will be driven with a peak current of 4A Figure 4 shows the input signals for the L6202 and the motor current used in the evaluation,
Here the bridge is energized and the load current is allowed to build up to 4A, When the 4A peak is reached, th'e bridge is disabled and the current decays through the intrinsic diodes in the DMOS power stage. All figures in the remainder of this note are taken under these operating conditions,
POWER SUPPLY FILTERING
To reduce the effect of the wiring inductance a good high frequency capacitor can be placed on the board near the bridge circuit to absorb the small amount of inductive energy in the leads, it should be noted that this capacitor is usually required in addition to an electrolytic capacitor, which has poor performance at high frequencies.
Operating Voltages. Figure Sa : Supply Voltage.
3/7 139
APPLICATION NOTE
Figure Sa shows the spike on the power supply pin of the L6203 and the output pins when the bridge was disabled. These waveforms were present when the device was mounted on a printed circuit board where reasonable care was taken in the layout. When a 0.21lF polyester capacitor was connected between the supply and ground pin of the L6203 the voltage spike on the power supply was significantly reduced, as shown in figure 6a.
Figure 5b : V01 - V02.
Figure 6a : Supply Voltage.
Figure 6b : V01 - V02.
Looking at the voltage waveform at the output terminals of the L6202, shown in figure 6b, a large spike is still present. The worst case spike is measured between the output terminals of the device (VOUI1 - Vout2) since the spikes above the supply and below ground are both present. After the voltage spike on the power supply was eliminated, the tran-sients on the output must be related to the mismatch of switching times between the diodes and power transistors. To control these spikes two possible alternatives are present ; 1) use faster diodes, or 2) use an external circuit to slow the voltage rise time across the output when the transistors are turned off. Schottky diodes connected external to the L6203 would more closely match the switching time of the DMOS power transistors, but are expensive and require additional board space.
Operating Voltages with 0.21lF Bypass Capacitor on Supply Pin.
Slowing down the output voltage rise time can be accomplished by connecting a snubber network across the output ter minals of the device. Figure 7 shows the connection for a RC snubbing circuit used with the L6203. With properly selected values the slope of the voltage waveform can be limited to where the diodes have sufficient time to turn on and clamp the remaining inductive energy.
4/7 140
APPLICATION NOTE
SNUBBER DESIGN CONSIDERATIONS The function of the snubber network is to limit the rate of change of the voltage across the motor (output terminals of the L6203) when one of the DMOS devices is turned off. Using the RC snubbing circuit shown in figure 7, the rate of change of the voltage on the output is dominated by the capacitor while the resistor is used primarily to limit the peak current flowing through the power transistor when it turns on. Figure 7 : DC Motor Drive Applications with Snub-
ber Network and Bypass Capacitor.
The time constant of the motor current is much longer than the switching time, due to the inductance of the motor. At the time of switching the DC motor can be assumed to be a constant currentgenerator equal to the peak current at switching. If this
current is switched into the snubber, the voltage across the snubber network will jump to a value equal to the snubber resistance times the motor current. Afterthe initial step, the rate of change is limited by the motor current charging the snubber capacitor.
To properly size the snubber network the resistor is selected such that the maximum motor current will produce a voltage less than the minimum power supply voltage. If the resistor is larger than this value, the snubber will be ineffective since the capacitor will not limit the voltage rise until the voltage has become greater than the power supply. For the de-sign example, the maximum resistance for the snubber is given by the equation:
Rmax = Vsmin/lpeak = 38V/5A= 7.6 Ohm (2)
The snubber capacitor is calculated from the peak current and the target rise time. The capacitance is given by the equation:
C ;; Ipeak dtldv = 5A 150nS/50V = O.015)lF (3)
When the snubber network is installed in the application the voltage transients on the terminals of the L6203 are greatly reduced, as shown in figure 8.
The drawback of a snubber network of this type is that a current spike will flow into the transistor when it is switched on as the capacitor is discharged. The theoretical peak value of this spike is given by the equation:
I = Vsmax/R = 42V/7.50hm = 5.6A (4)
5/7 141
APPLICATION NOTE
Operating Voltages with Snubber Network and Bypass Capacitor.
Figure 8a : Sypply Voltage.
the snubber circuit current plus the .load current. In practice the peak current measured is usually much less than the calculated peak, due to the capacitors internal resistance and inductance and the resistor inductance. Figure 9 shows.the peak current in the snubber network in the design example,
Current in the Snubber Circuit. Figure 9a : Turn on 2.0Ndiv.
Figure 8b : V01 - V02.
This peak current flowing in the snubber is added to the load current when the device is turned on and the total peak current in the transistor is the sum of
The power dissipated in the snubber resistor is the sum of the dissipation during the turn-on and turnoff of the bridge. The resistor dissipation is :
Pd = (11 2RDC) + (122HDC) (5)
where
h = Current at turn-on 12 = Current at turn-off R = Snubber resistor DC = Duty Cycle of current flow
For the design example the power dissipation, not considering the duty cycle is :
Pd = ((2.5f7.5".01) + ((5)27.50.01)
= 0.469 + 1.875
= 2.344 W (6)
6/7 142
APPLICATION NOTE
If the device is chopping for only a portion of the time the dissipation in the resistor will be reduced. Figure 9b : Turn off 2.0Ndiv.
CONCLUSION With the O.2IlF bypass capacitor and the snubber circuit in place the voltage transients measured in
the application have been limited to within safe values for the L6202. As shown in figure 8, the power supply voltage, the voltage across each of the DMOS transistors and the voltage across tbe output of the bridge (Vout1 - Vout2) are all within the maximum rating of the device with some margin.
SUMMARY
To insure reliable performance of a H-bridge drive circuit, the designer must insure that the device operates within the maximum ratings of the device(s) used in the circuit. One of the critical parameters to consider is the maximum voltage capability of the devices. To maintain the reliability, the voltage transients due to switching inductive loads must be maintained within the ratings of the device.
Two techniques used to control the voltage transients in fast switching applications are proper bypass filtering of the power supply and snubbing the outputs to control voltage rise times. Using these two techniques the voltage transients in a DMOS bridge application can be controlled to within safe levels.
717 143
APPLICATION NOTE
A HIGH EFFICIENCY, MIXED-TECHNOLOGY MOTOR DRIVQR
By C. CINI
A new mixed technology called Multipower-BCD allows the integration of bipolar linear circuits. CMOS logic and DMOS power transistors on the same chip. This note describes a H-bridge motor driver IC realized with this technology.
The miniaturization and integration of complex systems and subsystems has led in recent years to the implementation of monolithic circuits integrating logic functions and power sections.
For these applications SG8-THOMSON Microelectronics has developed a new technology called Multipower BCD which allows the integration on the same chip of isolated Power DMOS elements, bipolar transistors and C-MOS logic.
Thanks to high efficiency, fast switching speed and the absence of secondary breakdown, this technology is particularly suitable for fast, high current sole-
noid drivers and high frequency switching motor control. The free-wheeling diode intrinsic to the DMOS structure (necessary if the device drives an inductive load) and the great flexibility available in the choice of the logic and driving section components allow the complete integration of power actuators without further expense in silicon area-and a compact implementation of complex signal functions.
This technology has been applied to produce a switching power driver - the L6202/3 - capable of delivering 4A per phase, which is suitable for speed and position control in D.C. motor applications.
Figure 1 : A Schematic Cross Section of Bipolar, C-MOS, DMOS Structures (BCD).
L _____----' ._ _ _ _-" L._._II_.~ .... J L ______..J
POW EROM e s c 1~1 05
HPN PNPH. V. P- CH
s~ 9351
MOS
MULTIPOWER BCD TECHNOLOGY
Multipower BCD technology combines the well known vertical DMOS silicon gate process, used for discrete POWER MOS devices, and the standard junction isolation, sinker and buried layer process. The architecture of the process is centred around the vertical DMOS silicon gate, a self aligned structure, which guarantees short channel length (1.5 11m) with consequent low RDs(ON) for the device.
AN234/1088
In standard IC technologies the voltage capability is determined essentially by the thickness of the epitaxial layer and it is the same for signal and power components. But if the epi thickness is increased to allow the inclusion of high voltage transistors even the linear dimension of small signal transistors must be increased proportionally. In contrast MULTIPOWER BCD permits the realization of high voltage lateral DMOS structures in an epi-Iayer dimensioned for low voltage bipolar linear elements. Thus
1/6
145
APPLICATION NOTE
it is possible to mix on the same die very dense in switch mode applications. In fact DMOS, as a re-
CMOS logic, high precision bipolar linear circuits, very efficient DMOS power devices and high voltage lateral DMOS structures.
In this way the constraints which limit the complexity of signal processing circuits that can be integrated economically on a high chip are greatly reduced.
The active structures available in Multipower BCD technology are represented in fig. 1.
Within the vertical DMOS is indicated an intrinsic diode that can operate as a fast free-wheeling diode
sult of the way by which it is realized, is almost a symmetrical bidirectional device. That is, itcan operate with the electrical 1-V characteristic shown in the 3rd quadrant of fig. 2 ; that is, as a controlled resistor of value decreasing inversely with the gate source voltage applied to the power to which it is as-
sociated, up to a minimum equal to the RDs(oN) of the device itself, shunted by the body-drain diode intrinsic to the structure that limits the negative excursion of VDS. Of the devices represented in fig. 1 the table 1 lists the electrical characteristics.
Table 1 : Devices in Multipower BCD Technology.
· Vertical DMOS Lateral DMOS P-channel with Drain Extension Bipolar NPN
·· Bipolar PNP C-MOS Nand P-channel
BV DSS > 60 V BVDSS > 100 V BVDSS > 85 V LV cEo > 20 V LVcEO > 20 V BVDSS > 20 V
VTH" 3 V VTH " 3 V VTH" 3 V
B : 35 B : 20
VTH " 3 V
IT> 1 GHz IT> 800 MHz IT> 200 MHz IT> 300 MHz
IT> 7 MHz
Figure 2 : I-V Characteristic of DMOS N-channel Power Device.
The system diagram representing the internal function blocks and external components (outside the dashed line) is shown in fig. 3.
The integrated circuit has 3 Inputs: Enable, Input 1, Input 2. When Enable is "low" all power devices are off ; when it is "high" their conduction state is controlled by the logic signals Input 1 and Input 2 that drive independently a single branch of the. full bridge. When Input 1 (Input 2) is "high" DMOS 1 (DMOS 1') is "on" and DMOS 2 (DMOS 2') is "off", when is "low" DMOS 1 (DMOS 1') is "off" and DMOS 2 (DMOS 2') is "on".
A thermal protection circuit has been included that will disable the device if the junction temperature reaches 150 "C. When the thermal protection is removed the device restarts under the control of the Input and Enable signals.
THE L6202 & L6203 H-BRIDGE DRIVERS
Using this technology a H-bridge IC has been realized which accepts TIL or C-MOS compatible signals and is suitable for high efficiency, high frequency switching control of DC and stepping motor. The power stage consists of four DMOS Nchannel transistors with RDs(oN) '" 0.3 Q .
When this device is supplied with the maximum voltage of 60V it can deliver a DC current of 1.5A in a standard DIP.16 (L6202) and up to 5A in a MULTIWATI package (L6203).
The device can also operate with a peak current of 8A for a time interval essentially determined by the time constant of heat propagation ( < 200ms).
ON-OFF SYNCHRONIZATION CIRCUIT
ON-OFF synchronization of the power devices located on the same leg of the bridge must prevent simultaneous conduction, with obvious advantages in terms of power dissipation and of spurious signals on the ground and on sensing resistors.
Because of the very short turn-on, turn-off times characteristic of POWER MOS devices a dead time (time in which all power transistors are "off") of 40 ns is sufficient to prevent rail-to-rail shorts. The circuit that provides this time interval is shown in fig. 4 with the voltage waveforms that explain how it works. Let us suppose Enable = "high". Because of the delay times introduced by INV1 and INV2, V2 and V3 are two waveforms contained one in the
2/6 146
Figure 3 : L6202-6203 Block Diagram.
OUT 1 OUTl CeOOT 1
APPLICATION NOTE
ENABLEr-~_ _ _ _'-~
5-540'
Figure 4 : A Schematic Representation of ON-OFF Synchronism Circuit.
~
V
t
1
I
V
· t
2
I
..
V
t
3
· ---+1 /+--t'~ dead limp
5- 935311
3/6 147
APPLICATION NOTE
other and of polarity suitable to assure that the turnon of a power transistor happens only after the turnoff of the other. The gate voltages V5 and V6 of DM1 and DM2 are represented in fig. 5. In fig. 3 we can see also the modality of operation of the Enable signal, charge pump and bootstrap circuits.
Figure 5 : POWER MOS Gate Voltage Waveforms.
Concerning POWER MOS driving, it must be noted that it is necessary to assure to all DMOS N-channel a gate-source voltage of about 1OV to guarantee full conduction of the POWER MOS itself. While there are no particular problems for driving the lower POWER MOS device (its terminals is referred to ground) for the upper one it is necessary to provide a gate voltage higher than the positive supply because it has the drain connected to the positive supply itself.
This is obtained using a system that combines a charge pump circuit, that assures DC operation, with a bootstrapping technique suitable to provide high switching frequencies. The circuit that satisfies to all these requirements is represented in the schematic diagram of fig. 6.
In the description of this circuit we can assume that CSOOT is absent and IN commutes from the "Iow" to the "high" level.
Figure 6 : Schematic Representation of Charge PUMP and BOOSTRAP Circuit used to Drive the Gate of the Upper DMOS Device.
In this condition, by means of D1, the circuit charges immediately the DMOS1 gate capacitance to Vs while the charge pump, activated by the signals IN
= "Iow", as it can be seen in fig. 7, must supply only
a voltage of about 1OV.
In the switching operation it will be CSOOT that guar-
antees a faster turn-on of the upper POWER MOS and consequently high commutation frequencies.
In fact during the period in which DMOS2 is "on" CSOOT is charged to a voltage of about 12V.
When Vout raises because DMOS2 is disactivated D2 and D1 became "off" while D3, that remains "on"
416 148
APPLICATION NOTE
connects the gate circuit to CSOOT that raises higher than Vs and makes DMOS1 full "on" in a very short time interval (20 ns). It must be noted that the switch M4 in the fig. 6 circuit, driven by a complementary phase respect to M3 disconnects D4, D5 and D6 from 12 V when M5 goes "on" to assure the "turn-off" of DMOS1. Figure 7 : Charge PUMP Abilitation Signal and
Gate Voltage of DMOS Upper Device.
Figure 8 : Darlington Bipolar and DMOS Power Stages.
LOAD
(a)
5-9355
PERFORMANCE One of the most important features is the very high efficiency achieved. To appreciate the benefits of low power dissipation, and consequently of high efficiency, of a circuit realized in DMOS technology we must refer to the equivalent bipolar solution and also consider separate DC and AC operation.
Consider the typical Darlington power stage frequently used in integrated circuit and a DMOS power stages both represented in fig. S.Neglecting the power dissipation in the driving section, in static conditions, the total dissipation of the two stages when they are "on" is in the case (a) :
Pd(a) = (VCESAT1 + VSE2) X IL
and in the case (b) :
Pd(b) = ROS(ON) x IL2
where IL is the load current.
Because the saturation loss of a power DMOS transistor can be reduced by increasing the silicon area it is possible to satisfy the condition
ROS-ON x IL< (VCESAT1 + VSE2)
and then to obtain lower dissipation.
Conceming to the driving section, an other essential difference must be emphaisised.
While in case (a) during the time in which the power is "ON" it is necessary to supply a current for maintaining 01 saturated, in the case (b) power is dissipated only during the commutation of the gate Voltage.
About AC operation, it must be noted that the greatest advantage, always in terms of power dissipation, is due to the inherently fast turn-on, turn-off times of power MOS devices. In fact, if we suppose that the load is of inductive type and that the current waveform is triangular on the voltage commutation of the output, the total power dissipation is :
Pd = Vs IL TCOM. fSWITCH where: Vs = Supply voltage, IL = Peak load cur-
rent, TCOM. = TTURN-ON = TTURN-OFF,
fSWITCH = Chopper frequency.
Because TCOM. in DMOS case is ~ than in bipolar case at a fixed frequency we have a lower dissipation or at fixed dissipation we can tolerate higher switching frequency.
Considering all these aspects, with a power device consisting of about 2200 cells we have realized DMOS power devices characterized by ROS(ON) 0.3 Q and by switching times tr, tf of 50 ns. Other characteristics of the device when is configured as shown in fig. 9 are listed in table 2.
Fig. 10 shows the supply current with no load, vs. switching frequency.
5/6 149
APPLICATION NOTE Figure 9.
v s
5-9357
Table 2 : Main Features of L6202/6203.
Vs (maximum supply voltage) IL (maximum output current) Efficiency
Power Dissipation td (turn-on, turn-off propagation delay)
Figure 10.
60 V
1.5 A DIP.16
5 A MULTIWATT Package
90 % {I L
= 1.5 A
fChopper = 50 KHz
1.5 W Vs
= 54 V
100 ns
20 15 10
6/6 150
-4~------~------+-------4-------4-------4---~f(KHz)
o
50
100
150
200
250
5-9356
APPLICATION NOTE
STEPPER MOTOR DRIVING
By H. SAX
Dedicated integrated circuits have dramatically simplified stepper motor driving. To apply these ICs designers need little specific knowledge of motor driving techniques, but an under-standing of the basics will help in finding the best solution. This note explains the basics of stepper motor driving and describes the drive techniques used today.
From a circuit designer's point of view stepper motors can be divided into two basic types : unipolar and bipolar.
A stepper motor moves one step when the direction of current flow in the field coil(s) changes, reversing the magnetic field of the stator poles. The difference between unipolar and bipolar motors lies in the may that this reversal is achieved (figure 1) :
Figure 2 : ICs for Unipolar and Bipolar Driving. UNIPOLAR
Figure 1a :BIPOLAR - with One Field Coil and Two Chargeover Switches That are Switched in the Opposite Direction.
Figure 1b : UNIPOLAR - with Two Separate Field Coils and are Chargeover Switch.
a) ~
~
11f-J +~s~
~ BIPOLAR
BIPOLAR
vss
vs
b)
AN235/0788
5-93GB
1/16 151
APPLICATION NOTE
The advantage of the bipolar circuit is that there is only one winding, with a good bulk factor (low winding resistance). The main disapuantages are the two changeover switches because in this case more semiconductors are needed.
The unipolar circuit needs only one changeover switch. Its enormous disadvantage is, however, that a double bifilar winding is required. This means that at a specific bulk factor the wire is thinner and the resistance is much higher. We will discuss later the problems involved.
Unipolar motors are still popular today because the drive circuit appears to be simpler when implemented with discrete devices. However with the integrated circuits available today bipolar motors can be driver with no more components than the unipolar motors. Figure 2 compares integrated unipolar and bipolar devices.
BIPOLAR PRODUCES MORE TORQUE
The torque of the stepper motor is proportional to the magnetic field intensity of the stator windings. It may be increased only by adding more windings or by increasing the current.
A natural limit against any current increase is the danger of saturating the iron core. Though this is of minimal importance. Much more important is the maximum temperature rise of the motor, due to the power loss in the stator windings. This shows one advantage of the bipolar circuit, which, compared to unipolar systems, has only half of the copper resistance because of the double cross section of the wire. The winding current may be increased by the factor --12 and this produces a direct proportional affect on the torque. At their power .Ioss limit bipolar motors thus deliver about 40 % more torque (fig. 3) than unipolar motors built on the same frame.
If a higher torque is not required, one may either reduce the motor size or the power loss.
Figure 3 : Bipolar Motors Driver Deliver More Torque than Unipolars.
TORQUE
BIPOLAR
m {I-U_N_I_P_OL_A_R----..
CONSTANT CURRENT DRIVING
In order to keep the motor's power loss within a reasonable limit, the current in the windings must be controlled.
A simple and popular solution is to give only as much voltage as needed, utilizing the resistance (RL) of the winding to limit the current (fig. 4a). A more complicated but also more efficient and precise solution is the inclusion of a current generator (fig. 4b), to achieve independence from the winding resistance. The supply voltage in Fig. 4b has to be higher than the one in Fig. 4a. A comparison between both circuits in the dynamic load/working order shows visible differences.
Figure 4 : Resistance Current Limiter (a) and Current Generator Limiting.
L ,RL L RL
~C:J
IL=V/RL
L RL L RL
-;~
/~~--~-j~
IL=IC
Figure 5 : At High Step Frequencies the Winding Current cannot Reach its Setting Value because of the Continuous Direction Change.
__-V .. >b--t-- 'L rt~"'
-.
A
-;8L - - -
----.. log
FREQUENCY
SAX3
B
- -'-
5 - 9373
2/16 152
APPLICATION NOTE
It has already been mentioned that this power of the motor is, among others, proportional to the winding current.
In the dynamic working order a stepper motor changes poles of the winding current in the same stator winding after two steps. The speed with which the current changes its direction in the form of an exponential function depends on the specified inductance, the coil resistance and on the voltage. Fig. 5a shows that at a low step rate the winding current IL reaches its nominal value VL/RL before the direction is changed. However, if the poles of the stator windings are changed more often, which corresponds to a high step frequency, the current no longer reaches its saturating value because of the limited change time; the power and also the torque diminish clearly at increasing number of revolutions (fig. 5).
MORE TORQUE AT A HIGHER NUMBER OF REVOLUTIONS
Higher torque at faster speeds are possible if a current generator as shown in Fig. 4b is used. In this application the supply voltage is chosen as high possible to increase the current's rate of change. The current generator itself limits only the phase current and becomes active only the moment in which the coil current has reached its set nominal value. Up to this value the current generator is in saturation and the supply voltage is applied directly to the winding.
Fig. 6, shows that the rate of the current increase is now much higher than in Figure 5. Consequently at higher step rates the desired current can be maintained in the winding for a longer time. The torque decrease starts only at much higher speeds.
Fig. 7 shows the relation between torque and speed in the normal graphic scheme, typical for the stepper motor. It is obvious that the power increases in the upper torque range where it is normally needed, as the load to be driven draws most energy from the motor ·in this range.
EFFICIENCY - THE DECISIVE FACTOR
The current generator combined with the high supply voltage guarantees that the rate of change of the current in the coil is sufficiently high.
At the static condition or at low numbers of revolutions, however, this means that the power loss in the cu rrent generator dramatically increases, although the motor does not deliver any more energy in this range; the efficiency factor is extremely bad.
Help comes from a switched current regulation using the switch-transformer principle, as shown in
fig. 8. The phase winding is switched to the supply voltage until the current, detected across Rs, reaches the desired nominal value. At that moment the switch, formerly connected to + Vs, changes position and shorts out the winding. In this way the current is stored, but it decays slowly because of inner winding losses. The discharge time of the current is determined during this phase by a monostable or pulse oscillator. After this time one of the pole changing switches changes back to + Vs, starting an induction recharge and the clock-regulationcycle starts again.
Figure 6 : With a Step Current Slew, itisnota Problem to Obtain, even at High Step frequencies Sufficient Current in Windings.
+
v
,,- - - - IL=R-l
/ I
I
Il f---------~--------+_-
,
/
, ,
I
I
I
I
I
\
- \ ,, ....
s- 9374
Figure 7 : Constant Current Control of the Stepper Motor Means more Torque at High Frequency.
TORQUE
3/16
153
APPLICATION NOTE
Since the only losses in this technique are the saturation loss of the switch and that of the coil resistance, the total efficiency is very high.
The average current that flows from the power supply line is less than the winding current due to the concept of circuit inversion. In this way also the power unit is discharged. This king of phase current control that has to be done separately for each motor phase leads to the best ratio between the supplied electrical and delivered mechanical energy.
POSSIBLE IMPROVEMENTS OF THE UNIPOLAR CIRCUIT
It would make no sense to apply the same principle to a stabilized current controlled unipolar circuit, as two more switches per phase would be necessary for the shortening out of the windings during the free 'p~~?lld thus the number of components would be the same as for the bipolar circuit ; and more-
over, there would be the well known torque disadvantage.
From the economic point of view a reasonable and justifiable improvement is the ''Bi-Level-Drive'' (fig. 9). This circuit concept works with two supply voltages; with every new step of the motor both windings are connected for a short time to a high supply voltage. This considerably increases the current rate of change and its behaviour corresponds more or less to the stabilized power principle. After a predetermined the switch opens, a no a lower supply voltage is connected to the winding thru a diode.
This kind of circuit by no means reaches the performance of the clocked stabilized power control as per fig. 8, as the factors: distribution voltage oscillation, B.e.m.f., thermal winding resistance, as well as the separate coil current regulation are not considered, but it is this circuit that makes the simple unipolar R/L-control suitable for many fields of application.
Figure 8: With Switch Mode Current Regulation Efficiency is Increased.
/
/
I
I N\A,o'VI\A1'\A:A>"Ib
ASWNAITLCOHGED
4/16 154
5-9376
APPLICATION NOTE
Figure 9 : At Every New Step of the Motor, it is Possible to Increase the Current Rate with a Bilevel Circuit.
5-9377
~ t
START VOLTAGE STOP VOLTAGE
ADVANTAGES AND DISADVANTAGES OF THE HALF-STEP
An essential advantage of a stepper motor operating at half-step conditions is its position resolution
increased by the factor 2. From a 3.6 degree motor
you achieve 1.8 degrees, which means 200 steps per revolution.
This is not always the only reason. Often you are forced to operate at half-step conditions in order to avoid that operations are disturbed by the motor resonance. These may be so strong that the motor has no more torque in certain step frequency ranges and looses completely its position (fig. 10). This is due to the fact that the rotor of the motor, and the changing magnetic field of the stator forms a spring-masssystem that may be stimulated to vibrate. In practice, the load might deaden this system, but only if there is sufficient frictional force.
In most cases half-step operation helps, as the course covered by the rotor is only half as long and the system is less stimulated.
The fact that the half-step operation is not the dominating or general solution, depends on certain disadvantages:
_ the half-step system needs twice as many clock-pulses as the full-step system ; the clock-frequency is twice as high as with the full-step.
_ in the half-step position the motor has only about half of the torque of the full-step.
Figure 10 :The Motor has no More Torque in Certain Step Frequency Ranges with Full Step Driving.
TORQUE
FUll STEP RESONANCE
--log TORQUE
ZERO TORQUE
HALF STEP RESONANCE
--log
5-9378
For this reason many systems use the half-step operation only if the clock-frequency of the motor is within the resonance risk area.
The dynamic loss is higher the nearer the load moment comes to the limit torque of the motor. This effect decreases at higher numbers of revolutions.
5/16
155
APPLICATION NOTE
TORQUE LOSS COMPENSATION IN THE HALF-STEP OPERATION
It's clear that, especially in limit situations, the torque loss in half-step is a disadvantage. If one has to choose the next larger motor or one with a double resolution operating in full-step because of some insufficient torque percentages, it will greatly influence the costs of the whole system.
In this case, there is an alternative solution that does not increase the coats for the bipolar chopping stabilized current drive circuit.
The torque loss in the half-step position may be compensated for by increasing the winding current by the factor..)2 in the phase winding that remains active. This is also permissible if, according to the rnotor data sheet, the current limit has been reached, because this limit refers always to the contemporary supply with current in both windings in the full-step position. The factor ..)2 increase in current doubles the stray power of the active phase. The toal dissipated power is like that of the full-step because the non-active phase does not dissipate power.
The resulting torque in the half-step position amounts to about 90 % of that of the full-step, that means dynamically more than 95 % torque compared to the pure full-step; a neglectable factor.
The only thing to avoid is stopping the motor at limit current conditions in a half-step position because it would be like a winding thermal phase overload concentrated in one.
The best switch-technique for the half-step phase current increase will be explained in detail later on Fig. 11 shows the phase current of a stepping motor in half-step control with an without phase current increase and the pertinent curves of stap frequency and torque.
Figure 11 : Half Step Driving with Shaping Allows to Increase the Motor's Torque to about 95 % of that of the Full Step.
TORQUE
5-9379
HALF STEP
5 - 93 ao
HALF STEP WITH SHAPING (VT" )
6/16
156
APPLICATION NOTE Figure 12 : Only Two Signals for Full Step Driving are Necessary while Four (six if three-state is needed
on the output stages) for half Step.
ILA
J
ILB
J
I~Bu······I·············I~F~
ILA
ILB
ILA
ILB
o
5- 9382
7/16
157
APPLICATION NOTE
DRIVE SIGNALS FOR THE MICRO ELECTRONIC
A direct current motor runs by itself if you supply if with voltage, whereas the stepping motor needs the commutation signal in for of several separated but linkable commands. In 95 % of the applications today, the origin of these digital commands is a microprocessor system.
'In its simplest form, a full-step control needs only two rectangular signals in quadrature. According to which phase is leading, the motor axis rotates clockwise or counter-clockwise, whereby the rotation speed is proportional to the clock frequency.
In the half-step system the situation becomes more complicated. The minimal two control signals become four control signals. In some conditions as many as six signals are needed. If the Tri-state-command forthe phase ranges without current, necessaryfor high motor speeds, may not be obtaified from the 4 control signals. Fig. 12 shows the relationship between the phase current diagram and the control signal for full and half-step.
Since all signals in each mode are in defined relations with each other, it is possible to generate them using standard logic. However, if the possibility to
choose full and half-step is desired, a good logic implementation becomes quite expensive and an application specific integrated circuit would be better. Such an application specific integrated circuit could reduce the number of outputs required from a microprocessor from the 6 required to 3 static and dynamic control line.
A typical control circuit that meets all these requirements is the L297 unit (fig. 13).
Four signals control the motor in all operations:
1. CLOCK:
The clock signal, giving the stepping command
2. RESET:
Puts the final level signals in a defined start position
3. DIRECTION: Determines the sense of rotation of the motor axis.
4. HALF/FULL: Desides whether to operate in full or in half-step.
Another inhibit input allows the device to switch the motor output into the Tri-state-mode in order to prevent undesired movements during undefined operating conditions, such as those that could occur during.
Figure 13 : The L297 avoids the Use of Complicated Standard Logic to Generate Both Full and Half-step Driving Signals Together with Chopper Current Control.
y,-,
D1 to D8 = 2 A fast diodes { VF'; 1.2 V @ i = 2A trr,; 200 ns
8/16 158
ASI
~S2
'::> of,GIt.
APPLICATION NOTE
SWITCH-MODE CURRENT REGULATION
The primary function of the current regulation circuit is to supply enough current to the phase windings of the motor, even at high step rates.
The functional blocks required for a switch mode current control are the same blocks required in switching power supplies; flip-flops, comparators; and an oscillator are required. These blocks can easily be included in the same Ie that generates the phase control signals. Let us consider the implementation of chopper current control in the L297.
The oscillator on pin 16 of the L297 resets the two flip-flops at the start of each oscillator period. The flip-flop outputs are then combined with the outputs of the translator circuit to form the 6 control signals supplied to the power bridge (L298).
When activated, by the oscillator, the current in the winding will raise, following the UR time constant curve, until the voltage across the sense resistor (pin 1, 15 of L298) is equal to the reference voltage input (pin 15, L297) the comparator then sets the flip-flop, causing the output of the L297 to change to an equiphase condition, thus effectively putting a short circuit across the phase winding. The bridge is activated into a diagonally conductive state when the oscillator resets the flip-flop at the start of the next cycle.
Using a common oscillator to control both current regulators maintains the same chopping frequency for both, thus avoiding interference between the two.
The functional block diagram of the L297 and the power stage (L298) are shown in Figure 14 alone with the operating wave forms.
An important characteristics of this circuit implementation is that, during the reset time, the flip-flops are kept reset. The reset time can be selected by selecting the impedance of the RIC network or pin 16. In
this way, the current spike and noise across the sense resistors that may occur during switching will not cause a premature setting of the flip-flop. Thus the recovery current spike of the protection diodes can be ignored and a filter in the sense line is avoided.
THE RIGHT PHASE CURRENT FOR EVERY OPERATING CONDITION
The Chopper principle of the controller unit reveals that the phase current in the motor windings is controlled by two data: the reference voltage at pin 15 of the controller and the value of the sense resis-
tance at pins 1 and 15 of the L298, that is IL =
VREF/Rs. By changing VREF it is very easy to vary the current within large limits. The only question is for which purpose and at which conditions.
More phase current means more motor torque, but also higher energy consumption.
An analysis of the torque consumption for different periods and load position changes shows that there is no need for different energies.
There is a high energy need during the acceleration or break phases, whereas during continuous operation or neutral or stop position less energy has to be supplied. A motor with its phase current continuously oriented at the load moment limit, even with the load moment lacking, consumes needlessly energy, that is completely transformed into heat.
Therefore it is useful to resolve the phase current in at least two levels controllable from the processor. Fig. 18 shows a minimal configuration with two resistance and one small signal transistor as changeover switch for the reference input. With another resistance and transistor it is possible to resolve 2 Bits and consequently 4 levels. That is sufficient for all imaginable causes. Fig. 16 shows a optimal phase current diagram during a positioning operation.
9/16 159
APPLICATION NOTE Figure 14 : Two ICs and very Few External Components Provide Complete Microprocessor to Bipolar Step-
per Motor Interface.
I
J
I
- ~ - - - - -:..- - - - - - - - ----
l_l ______ _____ ~
n
-c __ CONTROL A
CONTROL B
5-9383
10/16 160
APPLICATION NOTE
Figure 15: Because of the Set-dominant Latch Inside the L297 it is Possible to Hide Current Spikes and Noise Across the Sense Resistors thus Avoiding External Filters.
' 'l-- t LCLOCK ur- - --: --.U..---ti~~:i"- J.,
Figure 16: More Energy is needed During The Acceleration and break Phases Compared the Continuous Operation, Neutral or Stop Position.
SPEED
,',A
,
IACCELER.,
I
STOP
TRANSPORT
,6
I
I
I
,
,DECELER.,
J
STOP
5- 9 J 66
11/16
161
APPLICATION NOTE
HIGH MOTOR CLOCK RESETS IN THE HALF-STEP SYSTEM
In the half-step position one of the motor phases has to be without current. If the motor moves from a fullstep position into a half-step position, this means that one motor winding has to be completely discharged. From the logic diagram this means for the high level bridge an equivalent status of the input signals AlB, for example in the HIGH-status. For the coil this means short circuit (fig. 17 up) and consequentlya low reduction of the current. In case of high half-step speeds the short circuit discharge time constant of the phase winding is not sufficient to discharge the current during the short half-step
phases. The current diagram is not neat, the half step is not carried out correctly (fig. 17 center).
For this reason the L297 controller-unit generates an inhibit-command for each phase bridge, that switches the specific bridge output in the half-step position into Tri-state. In this way the coil can start swinging freely over the external recovery diodes and discharge quickly. The current decrease rate of change corresponds more or less to the increase rate of change (fig. 17 below).
In case of full-step operation both inhibit-outputs of the controller (pin 5 and 8) remain in the HIGHstatus.
Figure 17 :The Inhibit Signal Turns Off Immediately the Output Stages Allowing thus a Faster Current Decay (mandatory with half-step operation).
+
+
IL
12/16
162
VS HS VS HS VS +
T +
T
5- 9387
APPLICATION NOTE
Figure 18 : With This Configuration it is Possible to Obtain Half-step with Shaping Operation and Therefore More Torque.
A
I 1
1NH.1
5
6
L297
B
CONTROLLER C L298
1NH.2
8
11
REF
15
REF
0
12
5·gJ8B
MORE TORQUE IN THE HALF-STEP POSITION
A topic that has already been discussed in detail. So we will limit our considerations on how it is carried out, in fact quite simply because of the reference voltage controlled phase current regulation.
With the help of the inhibit-signals at outputs 5 and 8 of the controller, which are alternatively active only when the half-step control is programmed, the reference voltage is increased by the factor 1.41 with a very simple additional wiring (fig. 18), as soon as one of the two inhibit-signals switches LOW. This increases the current in the active motorphase proportionally to the reference voltage and compensates the torque loss in this position. Fig. 19 shows clearly that the diagram of the phase current is almost sinusoidal, in principle the ideal form of the current graph.
To sum up we may say that this half-step version offers most advantages. The motor works with poor resonance and a double position resolution at a torque, that is almost the same as that of the fullstep.
BETTER GLIDING THAN STEPPING
If a stepper motor is supposed to work almost gliding and not step by step, the form of the phase current diagram has to be sinusoidal.
The advantages are very important: _ no more phenomena of resonance _ drastic noise reduction _ connected gearings and loads are treated with care _ the position resolution may be increased further.
However, the use of the L297 controller-unit described until now is no longer possible of the more semplicated form of the phase current diagram the Controller may become simpler in its functions.
Fig. 20 shows us an example with the L6505 unit. This IC contains nothing more than the clocked phase current regulation which works according to the same principle as L297. The four control signals emitting continuously a full-step program are now generated directly by the microprocessor. In order to obtain a sinusoidal phase current course the reference voltage inputs of the Controller are modulated with sinusoidal half-waves.
The microprocessor that controls the direction of the current phase with the control signals also generates the two analog signals.
For many applications a microprocessor with dedicated digital to analog converters can be chosen. Eliminating the need for separate OfA circuits.
About 5 bit have proved to be the most suitable suddivision of the current within one fUll-step. A higher
13/16
163
APPLICATION NOTE
resolution brings no measurable advantages. On the contrary, the converter clock frequency is already very high in case of low motor revolutions and very difficult to process by the processor-software. It is recommended to reduce the DIA resolution at high step frequencies.
In case of higher motor revolutions it is more convenient to operate only in full-step, since harmonic control is no longer an advantage as the current has . only a triangular waveform in the motor winding.
PRECISION OF THE MICRO STEP
Any desired increase of the position resolution between the full step position has its physical limits. Those who think it is possible to resolve a 7.2" stepper motor to I.S" with the same precision as a
I.S" - motor in full-step will be received, as there are several limits:
The rise rate of the torque diagram corresponding to the twisting angle of the rotor for the 7.2" - motor is flatter by a factor of 4 then for the original 1.S" motor. Consequently with friction or load moment, the position error is larger (fig. 21).
For most of the commercial motors there isn't a sufficiently precise, linear relationship between a sinusoidal-current-diagram and an exact micro step angle. The reason is a dishomogeneous magnetic field between the rotor and the two stator fields.
Above all, problems have to be expected with motors with high pole feeling. However, there are special stepper motors in which an optimized micro step operation has already been considered during the construction phase.
Figure 19 :The Half-step with Shaping Positioning is Achieved by Simply Changing Reference Voltages.
A
INHIBIT 1
IL-_ _--IIIL-_ _ _ _ B
C INHIBIT 2
0 L..-_ _
V~REFERENCE
}8 8V
Ii
p. . . .1.4
Tl ·
V 1 '='-="L.:] I
PHASE CURRENT
~
L
12
5-9389
14/16 164
APPLICATION NOTE
Figure 20 : L6506 Unit Gives The Possibility to Modulate Separately the Two Reference Voltage Inputs in Order to obtain a Sinusoidal Phase Current.
r--
flP
I
I DAC
I
t----
DAC
5-9390
A
B
C
LOGIC L6506
o
p
L298 N
CONTROLLER
5- 91, 23
15/16 165
APPLICATION NOTE
Figure 21 : Better Resolution is achieved with Low Degree Motor but More torque is delivered with high Degree Motor.
TORQUE
+
I..S"MOTOR
LOAD TORQUE
+
ROTATION ANGLE
TORQUE
5- 9391
CONCLUSIONS
The above described application examples of modern integrated circuits show that output and efficiency of stepper motors may be remarkably increased without any excessive expense increase like before.
Working in limit areas, where improved electronics with optimized drive sequences allow the use of less expensive motors, it is even possible to obtain a cost reduction.
16/16 166
APPLICATION NOTE
CONSTANT-CURRENT CHOPPER DRIVE UPS STEPPER-MOTOR PERFORMANCE
The most efficient and performant way to drive a stepper motor is to use a "chopper" drive circuit.
This note explains some basic theory then presents practical circuits based on power ICs.
PULSE WIDTH-MODULATED DRIVE IMPROVES MOTOR TORQUE AND SPEED YET ADDS NO COMPLEXITY TO CIRCUIT
Designers opting to use a fractional-horsepower stepper motor in applications such as computer printers can improve the motor's efficiency and its torque and speed characteristics by using a constant-current pulse-widt~-modulated (PWM) chopper-drive circuit. What's more, for high-power drives, dedicated control chips and a constant-current chopper drive can be as simple to use as direct drive.
A basic problem for a directly driven stepper is that the motor winding's time constant (UR) causes the current to increase slowly in the winding during each pulsed input. It may, therefore, never reach full-rated value, especially at high speed, or high pulsing rates, unless the voltage (Vs) across the terminals
is high. In the simplest stepper drive (see fig. 1a), transistor or Darlington switches sequentially activate the windings to drive the motor (see box, "Stepper motor basics").
This type of drive performs poorly because the supply voltage must be low so that the steady-state current is not excessive. As a result, the average winding current - and hence the torque - is very low at high drive motor speed.
Often, this problem is overcome by introducing a series resistance, thereby increasing the overall value by a factor of four - giving an U4R ratio - and also by increasing the supply voltage (see fig. 1b). This arrangement reduces the motor's time constant, which improves torque at high step rates. However such an approach is inefficient, because the series resistor constitutes a substantial waste of power.
Figure 1:
Common unipolar stepping drives (a) produce insufficient torque output becuase their supply voltage must be kept low to limit current. Adding series resistance to an U4R ratio (b) and raising the supply voltage proportionately improves torque output, especially at high step rates.
HIGHER VOLTAGE
.sLJL PULSED INPUTS
AN468/0392
Vs
L
MOTOR
W· INDINGS
L/R
S·WITCHES
R
4R }
3R
119211N468-tlf 1/5
167
APPLICATION NOTE
Figure 2 : A Pulse-width-modulated, or chopper, drive overcomes most of the problems of the simpler direct drive or even linear constant-current drives.
us
MOTOR WINDING
SENSE RESISTOR
ff92RN46B-B2
CONSTANT CURRENT IS BEST Introducing a feedback loop to control the winding current is a better solution. Linear constant-current control is possible but is rarely used because of high power losses in the power stage. However, a pulse: width-modulation scheme - a chopper circuit - not
only solves the UR time-constant problem but cuts power dissipation too (see fig. 2).
A four-phase bifilar/hybrid unipolar stepper motor could use a quad Darlington like the ULN2075B as a chopper driver and a chip like the L6506 as a current controller (see fig. 3).
The L6506, which contains all the chopper circuitry, is simple to use. An external RC network sets the oscillator frequency, and a voltage divider (or trimmer) sets the reference voltages, and hence the phase currents. Normally an oscillator frequency of over 20 KHz is chosen to avoid motor noise. The maximum usable frequency depends on the UR time constant of the motor.
Control signals forthe four-phase inputs can be provided by a micro-computer chip or a simple repetitive sequence from a logic circuit. Note that the L6506 contains just two independent chopper-controlloops ' sufficient for a four-phase unipolar stepping motor because opposing windings never energize together.
DRIVING BIPOLAR MOTORS
Bipolar stepper motors, preferred for their better torque/weight ratio, however, are normally driven by H-bridge output stages. They enable a single-polarity supply to drive each motor winding end sequentially to achieve a polarity-reversal effect on the windings.
Figure 3 : Asimple chopper drive for a unipolar stepping motor, can be assembled with just two chips: a Quad Darlington output driver IC and constant-current feedback controller IC.
lBBnF VSS ENABLE
us
~
INlo-----------r1~r-~~~-O~
J: i88nF
IN2o-----+-----r1~~~~~<H
IN3O-----+-----r1~r-~~~-¢,
2/5
168
Sensei
Ref.l
~:>"-''-'-'.''+-C::J-o
+ SV
VREF
SENSING RESISTORS
APPLICATION NOTE
STEPPER-MOTOR BASICS
In computer-peripheral office-equipment applications, the most popular stepper motors are permanent-magnet types with two-phase bipolar windings or bifilar-wound unipolar windings. Stripped to the essentials, both types consist of a permanent-magnet rotor surrounded by stator poles carrying the windings.
A two-pole motor would have a step angle of 90 '. However, most motors have multiple poles to reduce the step angle to a few degrees.
A bipolar permanent-magnet stepper motor has a single winding for each phase - and the current must be reversed to reverse the stator field. Bifilar/hybrid unipolar motors, however, have two windings wound in opposite directions for each phase, so that the field can be reversed with a single-polarity drive. Unipolar motors were once popular because the drive was simpler. But with today's dual bridge (H-bridge) ICs, it is just as easy to drive a bipolar motor.
In the most popular drive technique - two-phase-on - both phases are always energized. In another method - called the wave drive - one phase is energized at a time.
A third technique combines the two sequences and drives the motor one half-step at a time. Half-stepping is very useful because motor mechanically designed for very small step angles are much more complex - and costly - to built. ltis more economical to use a 1~O-step motor in half steps rather than a 200-step motor in full step.
Recently designers have started microstepping, or driving the motor at one-quarter stepping rather or less. This type of operation can obtain fine step control without using mechanically complex motors with small step angles.
A two-phase bipolar motor needing up to 2Nphase can be driven by a single IC - the L298N dual bridge (see fig. 4). It contains two H-bridges with all the necessary level shifters and gates to directly interface low-level input logic signals.
As before, a complete chopper drive can be built by adding a current-controller chip and the necessary protective diodes, an RC network to define the oscillator frequency and a reference-voltage divider to set the current level. Four-phase signals to the controller are provided by a controlling microcomputer or by another dedicated controller chip - the L297 stepper-motor controller.
Figure 4 : A Dual-bridge IC provides a simple power-stage design solution for a bipolar stepper motor.
USS
1B~."F
~I
T
RESET IN1
-l J
IN2
--l
IN3
t:j
.
IN4
:J
:c :a ~: l+5U
) 22KQ
~
R 'I
3.3nF
L6586
ENABLE
u-fs
1
1
L298N
1.-rC=
-~ vc=
L.-fC-
..... -~vc
18 8nF
·I b.. SURGE SUPPRESSOR DIODES
MOTOR WI NDINGS
SURGE -;;;- SUPPRESSOR DIODES
UREF. .1.
+5U
J SENSING
.1._. RESISTORS
1192AH468-84
3/5 169
APPLICATION NOTE
Containing an internal translator circuit controlled by step-and-direction inputs, the L297 motor controller (see fig. 5) allows operation in three modes: twophase-on, half-step and wave-drive.
The normal two-phase-on mode is selected by a low level on the halflfull input when the device has been reset to start.
Half-step drive is selected by a high level on the halflfull step input. To initialize the wave-drive mode, the user disables the output stage (brings enable low), resets the device, steps the translator one step, brings halfifuillow, and then reenables the outputs.
The L297 also lets the designer select either phase or inhibit chopping. Phase chopping provides lower
ripple and is suitable four unipolar motor, whereas inhibit chopping retums energy to the supply and is better for bipolar motors.
In applications such as printer-paper feed, the motor is often at rest. Since the full torque is not usually necessary to hold the motor in pOSition, designers can save power by switching the current to a lower level between runs. With an L297 or L6506 control chip, this task can be done by simply switching the reference input between two levels.
Where several chopper drives are used in the same system, they should be synchronized prevent intermodulation effects. This is done by connecting the sync pins to one another and omitting the oscillator RC network on all but one device.
Figure 5 : controlled by step, direction, and mode inputs, the L297 stepper-motor controller chip performs some of the functions of a controlling microcomputer.
CW/CCW STEP
HALF/FULL RESET
CONTROL ENABLE
SYNC
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4/5 170
APPLICATION NOTE
HANDLING HIGH CURRENT
For current drives greater than 2AJphase, the two bridges in an L298N Ie can be paralleled by connecting inputs to the corresponding outputs. However, for a more equal distribution of the load and chip heating, driver 1 should be paralleled with driver 4, and driver 2 with driver 3. Additionally, total current should be derated by 0.5 A to allow for the maximum possible imbalance between the current in each bridge. Thus two L298s can drive motors rated at 3.5 AJphase.
A different configuration for microstepping stepper motors is employed in the PBL3717A control circuit. It contains all of the control and power circuitry for
one phase of a motor. An H-bridge output stage can drive motors rated at up to 1AJphase. Two of these devices are needed to drive a two-phase bipolar motor.
The output current level from the PBL3717A is set both by an analog-reference input and two logic inputs (11 and 10), which select one of three preset current levels (the fourth combination disables the outputs stage). This feature implements the microstepping, in which several current levels are used to obtain very small step angles for even more precise control (but at the expense of a less regular torque). Unlike the L297 and L6506, the PBL3717A has a constant off-time chopper driver which is ideal for microstepping.
5/5 171
APPLICATION NOTE
USING THE L6506 FOR CURRENT CONTROL OF STEPPING MOTORS
by Thomas Hopkins
Chopper-type current control circuits improve the performance of motor drives. This note shows how this can be done simply using the L6506 current controller IC.
The L6506 is a linear integrated circuit designed to current is sensed by monitoring the voltage across
sense and control the current in stepping motors and other similar devices. When used in conjunction with power stages like the L293, L298N, or L7180
a sense resistor (Rsense) and using a Pulse Width Modulated control to maintain the current at the desired value.
the chip set forms a constant current drive for inductive loads and performs all the interface functions from the control logic through the power stage.
The L6506 may be used with either two phase bipolar or four phase unipolar motor configurations.
An on-chip oscillator drives the dual chopper and sets the operating frequency. An RC network on pin 1 sets the operating frequency, which is given by the equation:
The circuit in figure 1 shows the L6506 used in conjunction with the L298N in a 2 phase bipolar stepper
f~-----
(1 )
0.69 R1 C1
motor application. The circuit in figure 2 implements a similar 4 phase unipolar application.
forR1>10Kn
The oscillator provides pulses to set the two flip-
CURRENT CONTROL LOGIC
flops, which in turn cause the outputs to activate the power actuator. Once the outputs have been acti-
In these two circuits, the L6506 is used to sense and vated the current in· the load starts to increase,
1:1-;.. .. control the current in each of the load windings. The limited by the inductive characteristic of the load.
Figure 1 : Application Circuit for Bipolar 2 Phase Stepper Motor.
5U
EN.B
11313nF 36U
11313 nF
II II
EN.A
~~
~
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= 5
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6
7
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18 14 13 12
L6586 11
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13
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AN469/1090
1/5
173
APPLICATION NOTE Figure 2 : Application Circuit for Unipolar 4 Phase Stepper Motor.
18BnF USS
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ENABLE
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us
MOTOR WINDINGS
I-o----~:::::J--o +5U
SENSING RESISTORS
1f9211N468-B3
When the current in the load winding reaches the programmed peak value, the voltage across the sense resistor (Rsense) is equal to reference voltage input (Vref) and the corresponding comparator resets its flip-flop. This interrupts the drive and allows the current to decay through a recirculating path until the next oscillator pulse occurs. The peak current in each winding is programmed by selecting the .value of the sense resisJor and Vref and is given by the equation:
Vref
Ipeak =
(2)
Rsense
The minimum output pulse width is determined by the pulse width of the oscillator, or other signal applied to the sync input. The internal oscillator is designed to provide narrow pulses to the sync input but the pulse width should be considered carefully. In some applications it is desirable to set the pulse width of this sync pulseto be just longer than the turn on delay time of the actuator stage. This may be useful in systems where the switching noise or recovery current of the catch diodes, which passes through the sense resistor, causes the comparator to sense a current above the peak current. By mak-
2/5
174
ing the sync pulse wide enough to hold the flip-flop set at the time the switching transient occurs will cause the device to ignore this false data.
When the intemal oscillator is used the pulse width can be modified by changing the value of the capacitor on pin 1.
Increasing the capacitance will widen the pulse width .
The L6506 may be used with either a bridge driver, as shown in figure 1, for bipolar motors or a quad darlington array, as shown in figure 2, for 4 phase unipolar motors. For eigher configuration, half step may be implemented using the 4 phase inputs with the input waveforms shown in figure 3.
The recirculation path for the motor current is through a catch diode for unipolar motors, or a catch diode and one of the lower transistors of the bridge for bipolar motors. Both of these implementations produce a low ripple cu rrent since the voltage across the motor during the recirculation time is much less than the power supply voltage. Figure 4 shows the ripple current for bipolar motor applications using the L6506 and the L298N.
APPLICATION NOTE
Figure 3 : Input Signal for Stepper Motor Drive.
A
c
POR
FULL STEP MODE
A
c
D
POR
HALF STEP MODE
5-9344
When implementing a half step drive, both outputs of the L6506 will be low during the half step of one phase. This means a very long time is required for the current in the "off" winding to decay when driving bipolar motors.
Altern3tely, the power stage (L298N) may be inhibited to put the output in the state and achieve a laster current decay.
Since separate Vret inputs are provided for each channel, each of the loads may be programmed independently allowing the device to be used to implement microstepping or applications with different peak and hold currents. In this type of application, changing the reference voltage (Vret) will change the load current, effectively implementing a transconductance amplifier.
Figure 4 : Ripple Current in Bipolar Motors.
SYNCHRONIZING MULTIPLE DEVICES
Ground noise problems in multiple configurations can be avoided by synchronizing the oscillators. This may be done by connecting the sync pins of each of the devices with the oscillator output of the
master device and connecting the RIC pin of the un-
used oscillators to ground as shown in figure 5. The devices may be synchronized to external circuits by applying synchronizing pulses to the sync pins. It should be noted, however, that the input pulse sets the minimum on time of the outputs and will therefore set a minimum output average current.
SELECTING THE OSCILLATOR COMPONENTS
When selecting the values for the external components for the oscillator one of the primary considerations is the operating frequency. In addition there is another important consideration for these components.
Figure 5 : Synchronizing Multiple Devices.
Ucc R
RIC L6506
asc SYNC
MASTER
asc ---( SYNC
r L6506 RIC
f152f1N465-Bt SLAVE
In many applications the reverse recovery current of the free wheeling diodes and of parasitic elements in the power stage will flow through the sensing resistor in addition to the load current. Also there is sometimes noise- generated in the system when the power stage is swiched on.
3/5
175
APPLICATION NOTE
These two sources of error can fool the current limiting stage and make it appear to operate at a subharmonic of the desired frequency. With the proper selection of the oscillator components this behavior can be avoided. The design of the L6506 is such that the flip-flops used in the device are set dominant so that whenever the sync input is low the Q output of the flip- flop will be high even if the reset is applied by the cOiTlparator at the same time. This characteristic of the flip-flops can be used to make the current sensing immune to the recovery currents and noise spikes that occur when the power devices switch. If the sync pulse is longer than the tum on delay time of the power stage, as shown in figure 6, these two sources of errors will be ignored. Figure 6 : Load Current and Sync Pulse.
To select the proper values forthe oscillator components a more detailed equation for the operating frequency and duty cycle of the oscillator is required. The required equations can be derived from the equivalent circuit for the oscillator section shown in figure 7. As can be seen from figure '7, the full equation for the operating frequency includes not only the external resistance and capacitance but the internal discharge resistor as well. The full equation for the operating frequency is :
The equations for the active time of the sync pulse
(T2), the inactive time of the sync signal (T1) and the duty cycle can also be found by looking at the figure 7 and are:
R1 Ri
T2 = 0.69C1 R1 + Ri
(4)
T1 = 0.69 R1 C1
(5)
T2
DC = T1 + T2
(6)
By substituting equations 4 and 5 into equation 6
and solving for the value of R1 the following equa-
tions for the external components can be derived:
dc - R1 = (
2 ) Ri
(7)
T1
C1 = 0.69 R1
(8)
Looking at equation 4 it can easily be seen that the minimum pulse width of T2 will occurwhen the value of Ri is at its minimum and the value of R1 at its maximum. Therefore, when evaluating equation 7 the minimum value for Ri of 7000 (1 KO -30 %) should be used to guarantee the required pulse width.
For a typical application using the L298, which has a maximum tum on delay of 2.5Ils, with the L6506 consider the following operating points:
f = 20 KHz
T1 + T2 '= 50 Ils
T2 min = 31ls
From equation 6:
DC = 31ls = 0.06 50llS
From equation 7: 1
R1 = ( 0.062) 700 = 10.3KO
From equation 8:
_ 47gs _ C1 - (0.69) (1 0.3K) - 6.6nF
f=
1 R1 .~
(3)
0.69C1 [ R1 + ( R1 + Ri ) 1
4/5 176
Figure 7 : Oscillator Circuit and Waveforms.
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I
555
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APPLICATION NOTE
SYNCU
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1f92I1N469-(J2
5/5
177
APPLICATION NOTE
HIGH-POWER"DUAL-BRIDGE ICs EASE STEPPER-MOTOR-DRIVE DESIGN
In addition to simplifying design problems, a family of dedicated chips improves stepper-motor drive-circuit reliability by significantly reducing the component count.
The L293, L293E and L298N dual-bridge ICs (see box, "inside the dual-bridge ICs") significantly reduce the problems encountered in the design of stepper-motor drive circuitry. They can, for example, simplify the design and increase the efficiency of
constant-current choppers. And with a single chip replacing the transistors and predriver stages, circuit performance improves. Best of all, the devices have applications in complex as well as basic driver networks.
Figure 1: The Simplest Stepper-motor Drive Technique is the Basic LlR Configuration. Adding Series Resistors and Raising the Supply to Make an Ll4R Drive Improves Torque at High Steps rates but Reduces Efficiency.
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IN SERIES WITH EACH WINDING AND RAISE suPPt Y VOL TAGE TO 24V
AN238/0488
1/7
179
APPLICATION NOTE
SIMPLEST DESIGN IS AN LlR DRIVE
The simplest motor-drive configuration (fig. 1) consists of a ~C that performs the translator function in software (see box, "Generating switching sequences") and drives the motor through a L293 dual bridge. Only eight external components are required ; these are diodes that protect the device's output transistors against inductive spikes generated when a winding de-energizes. The L293 handles 1A continuous (for higher current
use and L298N). However, if you plan to run the motor continuously with two phases on, dissipation will be the limiting factor.
You can improve the performance of this basic UR drive by increasing the series resistance and raising the supply voltage to restore the original phase current. At high speeds, torque improves, but efficiency decreases. Normally, you increase each winding's resistance by a factor of four through the addition of a 3R series resistance, resulting in the U4Rdrive.
INSIDE THE DUAL-BRIDGE les
The L293, L293E and L298N (figure) contain two power-transistorbridges, predriverstages, control logic
and protection circuitry. There's a control input for each
bridge and an enable input for each half bridge; inputs connect directly to /lGs, GMOS or TTL. The IGs inte-
grate level shifters with a separate logic-supply pin. For
current sensing, the L293E and L298N have external emitter connections.
A single package drives a 2-phase bipolar stepper
motor, challenging the assumption held by many that unipolar motors are easier to drive.
You can use a bipolar motor - simpler and less expensive than a unipolar motor - without building complex
power stages. Furthermore, you don't have ·to worry
about simultaneous conduction of a half bridge's source and sink transistors - a basic problem with dis-
crete-component bridge circuits. Chip design makes it impossible for both transistors to be on at the same time.
Designers should also discard the mistaken idea that constant-current chopper drivers are complicated and expensive. You can build one with two bridge IGs and
a few passive components.
Dual-bridge driver ICs reduce the parts count of bipolar stepper motors and simplify design. The schematic of the L298N is functionally similar to those of the L293 and L293E.
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5-"132(,
Type
10
10(PEAK)
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L293
1 A
1.5 A
36 V
L293E
1 A
1.5 A
36 V
L298N
2A
2.5 A
46 V
Package 16 DIP 20 DIP
Multiwatt 15
Sensing Connections
One Per Half Bridge One Per Bridge
2/7
180
APPLICATION NOTE
MULTIPLE SUPPLIES BOOST PERFORMANCE
A dual-level supply also improves the performance
of a basic LlR circuit. A high supply voltage yields
good torque characteristics when the motor is running. A lower-than-rated voltage provides some holding torque when the motor is at rest, thereby saving power when the motor is idle.
Fig. 2 shows a suitable voltage-s;yitch circuit. Rx sets the holding current, which can be low because a permanent magnet or hybrid stepper motor provides some holding torque at zero current. However, make certain the L293's motor-supply input never goes below the logic-supply voltage. While there's no danger of damaging the device, it's imposssible to drive the output transistors correctly under such conditions.
The dual bridge's enable inputs offer a means of extending the chip's flexibility. For example, you can connect them directly to the logic supply - no resistors are needed - to enable the chip permanently. As an alternative, use the enable inputs to disable the motor during the power-on reset sequence.
In wave-drive and half-step modes, use the enable inputs to increase torque at high speeds. When a winding de-energizes, flux collapse is a function of the current-decay rate. During this decay, the deenergized winding opposes the efforts of the next winding in sequence, partially cancelling the torque.
You can minimize this effect by disabling a bridge only when the winding it drives is turned off ; because the ~i!~t of an inductor equals ElL, disabling the bridge accelerates the current decay. This action discharges the winding's stored energy through its supply and maintains the terminal voltage E at Vs plus two diode drops. If you were to leave the bridge enabled, the current would flow to ground through one diode and one transistor, and it would lower the terminal Voltage. This scheme doesn't apply with drives with two phases on because no winding ever de-energizes.
Figure 2 : Switching the Supply to a Lower Voltage when the Motor is Idle Saves Current without Compromising Driving Power.
24V
lN493!.
lN4935
v,
5-9335
Figure 3: Maintaining a Constant-average Phase Current this Fixed-ripple Chopper Provides Improved Performance and Efficiency VREF Controls the Phase Current.
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5-9336
3/7
181
APPLICATION NOTE
GENERATING SWITCHING SEQUENCES
In addition to selecting a motor and determining power-
stage design, you must also decide how to generate the switching sequences that step the motor. Programming a !lC or using a special piece of hardware
called a transistor accomplishes this task.
Software translation is more economical, and it is the
first choice for large-volume products. Fig. A shows a basic step procedure (a) that you can integrate into a routine (b) ; the routine executes a clockwise rotation of N steps at a fixed rate. The step rate is defined by a
software loop, but you can also use programmed timer interrupts.
Fig. A: A!lC can generate the phase sequence (a) for a stepper motor. A routine (b). expands a single-step routine into are that executes a move of N steps.
a)
A simpler approach uses the software equivalent of a shift register. For example, you can load a 99 (hex) into a register and take the phases from bits 0 to 3. A Rotate Left instruction yields a clockwise step; a Rotate Right instruction causes a counterclockwise move.
When software translation ties up your !lC, lighten the
load by adding a hardware translator. In applications
involving unidirectional motors, this logic circuit (fig. B) requires only one pulse for each step; you'll also need
a direction signal (b) ifyour motor rotates in both directions. By adding a 7408 to a 2-phase translator, you
can satisfy a wave-drive application (c), while the addition of two OR gates provides fast turn-off in wave-drive mode.
Fig. B : Built a simple 2-phase hardware translator using a dual flip-flop, for single (a) or bidirectional (b) rotation. Add some extra ICs for wave-drive· signals (c) and to provide fast turn-off (d).
a)
(J)
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5--9329 L -_ _ _---J
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4/7 182
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5-9331
5-9332
APPLICATION NOTE
Often a fl C controls the translator, setting the direction line and providing a pulse for each step. Software is thus simplified, and if you use a programmed interrupt
scheme, the flC is free to handle other tasks. Fig. C de-
scribes an absolute-positioning routine for a step with a direction-control translator; Fig. 0 outlines how pro-
grammed timer interrupts are used to relieve the burden on the C.
Figure C : For use with a Hardware Translator this a Absolute-positioning Routine Sets the Direction Line and Sends the Appropriate Number of Step Pulses.
Two special cases call for hardware translation. The first is in a system for which you have already designed in control circuitry to provide step and direction signals. The second case involves single-quantity and smallrun applications, in which the cost ofa few ICs is a small price to pay for simplified software.
Noles: Enter with desired position current position in register or memory location.
YES
NO
Figure D :To Seta motor Step Rate, used Programmed Timer Interrupts in Place of Software Timing Loops.
5-9333
5-9334
· COMPLETE TIMER INTERRUPT SERVICE
5/7 183
APPLICATION NOTE
CHOPPER CIRCUIT OFFERS MORE ENHANCEMENTS
Adding a chopper circuit to maintain a constantaverage phase current improves performance and efficiency. Fig. 3 shown a simple constant-current drive that employs a dual bridge, dual comparator and a few passive components. This circuit requires an L293E, because this dual-bridge IC offers access to the lower emitter connections, thus letting you insert current-sensing resistors.
Operation of this fixed-ripple chopper drive is straightforward. When the IlC or translator activates a bridge, the increasing load current raises the voltage across the sensing resistor until it equals the comparator's reference voltage. The comparator then switches, clamping the translator signals through the diodes to deactivate the bridge. As the current decays, the voltage across the sensing resistor decreases until it equals the comparator's lower threshold. The comparator switches again, allowing the IlC or translator to activate a bridge and restart the cycle. As long as the translator drives the bridge, this sequence repeats to provide a constantaverage phase current with fixed ripple.
Vref adjusts the lower current limit, while the comparator's hysteresis sets the ripple, and hence the peak current. Although a divider establishes the value of Vref in this case, you can employ the dualsupply design approach and switch Vref to a lower value when the motor is idle. In addition, use of a D/A converter establishes Vref for micro-stepping applications. This drive circuit, with its fixed-ripple current characteristics, is well suited for such service.
FIXED-FREQUENCY CHOPPER IS MOTOR INDEPENDENT
Fig. 3's drive has some disadvantages. First, the chopper frequency depends on motor characteristics, and these parameters vary from unit to unit. In addition, it's impossible to synchronize the choppers, and this shortcoming can cause trouble on the ground plane.
Using a flip flop/comparator arrangement (fig. 4) to develop a fixed-frequency chopper overcomes these problems. In this circuit, the NE555 timer generates negative pulses that reset the flip flops to enable the phase-control signals from the transla-
Figure 4 : This Fixed-frequency Constant-current Chopper Driver Enables the Synchronization of Several Drives, thus Minimizing Potential Ground-plane Problems.
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6/7 184
5-9337
APPLICATION NOTE
Figure 5 : A Special Translator-chopper Control Circuit cuts the Drivers Components Count to the Minimum.
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, A
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tor. If these signals are set to energize a winding, the current in that winding rises until the voltage across the sensing resistor switches the comparator, thus setting the flip flop. This disables the phase signals and deactivates the bridge. Current in the winding falls until the next clock pulse resets the flip flop, and the sequence repeats to maintain a constant current.
CONTROLLER IC REDUCES COMPONENT COUNT
If you're using a hardware translation and constantcurrent choppers, you can further reduce the component count by using a controller chip such as the L297 - a 20-pin DIP that houses a translator and a
dual fixed-frequency chopper circuit. Under the control of step and direction inputs, the L297 generates normal, wave-drive and half-step sequences.
As shown in fig. 5, the controller connects directly to adual bridge. External component requirements are minimal: and RC network to set the chopper frequency and a resistive divider to establish the comparator reference voltage (Vret).
To accommodate motors with a phase current as great as 3.5 A, replace the single dual-bridge IC with two devices configured in parallel (input to input, enable to enable, etc) to form a single bridge. It's extremely important that you pair the half bridges - 1 with 4 and 2 with 3 - to ensure optimum current sharing.
Reprinted from EON. 11/24/83 © 1986 Cahners Publishing Company Division of Reed Publishing USA.
7/7
185
APPLICATION NOTE
THE L297 STEPPER MOTOR CONTROLLER
The L297 integrates all the control circuitry required to control bipolar and unipolar stepper motors. Used with a dual bridge driver such as the L298N forms a complete microprocessor-to-bipolar stepper motor
interface. Unipolar stepper motor can be driven with an L297 plus a quad darlington array. This note de-
scribes the operation of the circuit and shows how it is used.
The L297 Stepper Motor Controller is primarily intended for use with an L298N or L293E bridge driver in stepper motor driving applications.
It receives control signals from the system's controller, usually a microcomputer chip, and provides all the necessary drive signals for the power stage. Additionally, it includes two PWM chopper circuits to regulate the current in the motor windings.
With a suitable power actuator the L297 drives two phase bipolar permanent magnet motors, four phase unipolar permanent magnet motors and four phase variable reluctance motors. Moreover, it handles normal, wave drive and half step drive modes. (This is all explained in the section "Stepper Motor Basics").
Two versions of the device are available: the regular
L297 and a special version called L297A. The L297A incorporates a step pulse doubler and is designed specifically for floppy-disk head positioning applications.
ADVANTAGES
The L297 + driver combination has many advantages : very few components are required (so assembly costs are low, reliability high and little space required), software development is simplified and the burden on the micro is reduced. Further, the choice of a two-chip approach gives a high degree of flexibility-the L298N can be used on its own for DC motors and the L297 can be used with any power stage, including discrete power devices (it provides 20mA drive for this purpose).
Figure 1 : In this typical configuration an L297 stepper motor controller and L298 dual bridge driver combine to form a complete microprocessor to bipolar stepper motor interface.
AN470/0392
MCU
r rr'" CHOPPER RATE
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-
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PHASE 0, !litHBIY 1 INHIBIT 2
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1
5V
CURRENT SENSE RESISTORS
LOAD
' - - CURRENT
PROGRA....
5_5936
i STEPPER MOTOR WINDINGS
1117 187
APPLICATION NOTE
For bipolar motors with winding currents upto 2A the L297 should be used with the L298N ; for winding currents up to 1A the L293E is recommended (the L293 will also be useful if the chopper isn't needed). Higher currents are obtained with power transistors or darlingtons and for unipolar motors a darlington array such as the ULN20758 is suggested. The block diagram, figure 1, shows a typical system.
Applications of the L297 can be fou nd almost everywhere ... printers (carriage position, daisy position, paper feed, ribbon feed), typewriters, plotters, numerically controlled machines, robots, floppy disk drives, electronic sewing machines, cash registers, photocopiers, telex machines, electronic carburetos, telecopiers, photographic equipment, paper tape readers, optical character recognisers, electric valves and so on.
The L297 is made with SGS' analog/digital com-
patible h technology (like Zodiac) and is assem-
bled in a 20-pin plastic DIP. A 5V supply is used and all signal lines are TIUCMOS compatible or open collector transistors. High density is one of the key features of the technology so the L297 die is very compact.
THE L298N AND L293E
Since the L297 is normally used with an L298N or L293E bridge driver a brief review of these devices' will make the rest of this note easier to follow.
The L298N and L293E contain two bridge 'driver stages, each controlled by two TIL-level logic inputs and a TIL-level enable input. In addition, the emitter connections of the lower transistors are brought out to external terminals to allow the connection of current sensing resistors (figure 2).
For the L298N SGS' innovative ion-implanted high voltage/high current technology is used, allowing it to handle effective powers up to 160W (46V supply, 2A per bridge). A separate 5V logic supply input is provided to reduce dissipation and to allow direct connection to the L297 or other control logic.
In this note the pins of the L298N are labelled with the pin names of the corresponding L297 terminals to avoid unnecessary confusion.
The L298N is supplied in a 15-lead Multiwatt plastic power package. It's smaller brother, the functionally identical L293E, is packaged in a Powerdip - a copper frame DIP that uses the four center pins to conduct heat to the circuit board copper.
Figure 2 : The L298N contains two bridge drivers (four push pull stages) each controlled by two logic inputs and an enable input. External emitter connections are provided for current sense resistors. The L293E has external connections for all four emitters.
OUT!
QU12
OUTl
OU14
A B INHl
2/17 188
6
SENSE I
15 SENSEZ
~
I
I 10
0
- --D
-INH2
5-5981
APPLICATION NOTE
STEPPER MOTOR BASICS
There are two basic types of stepper motor in common use : permanent magnet and variable reluctance. Permanent magnet motors are divided into bipolar and unipolar types.
BIPOLAR MOTORS
Simplified to the bare essentials, a bipolar permanent magnet motor consists of a rotating permanent magnet surrounded by stator poles carrying the windings (figure 3). Bidirectional drive current is used and the motor is stepped by switching the windings in sequence.
For a motor of this type there are three possible drive sequences. Figure 3 : Greatly simplified, a bipolar permanent
magnet stepper motor consist of a rotaring magnet surrounded by stator poles as shown.
A
D-+-~III
1111111,-r--- c
5 _S937 B
The first is to energize the windings in the sequence AS/CD/SNDC (SA means thatthe winding AS is energized but in the opposite sense). This sequence is known as "one phase on" full step or wave drive
mode. Only one phase is energized at any given moment (figure 4a).
The second possibility is to energize both phases together, so that the rotor always aligns itself between two pole positions. Called "two-phase-on" full step, this mode is the normal drive sequence for a bipolar motor and gives the highest torque (figure 4b).
The third option is to energize one phase, then two, then one, etc., so that the motor moves in half step increments. This sequence, known as half step mode, halves the effective step angle of the motor but gives a less regular torque (figure 4c).
For rotation in the opposite direction (counter-clock-
wise) the same three sequences are used, except
of course that the order is reserved.
As shown in these diagrams the motor would have a step angle of 90 0 · Real motors have multiple poles to reduce the step angle to a few degrees but the number of windings and the drive sequences are unchanged. A typical bipolar stepper motor is shown in figure 5.
UNIPOLAR MOTORS
A unipolar permanent magnet motor is identical to the bipolar machine described above except that bifilar windings are used to reverse the stator flux, rather than bidirectional drive (figure 6).
This motor is driven in exactly the same way as a bipolar motor except that the bridge drivers are replaced by simple unipolar stages - four darlingtons or a quad darlington array. Clearly, unipolar motors are more expensive because thay have twice as many windings. Moreover, unipolar motors give less torque for a given motor size because the windings are made with thinner wire. In the past unipolar motors were attractive to designers because they simplify the driver stage. Now that monolithic push pull drivers like the L298N are available bipolar motors are becoming more popular.
All permanent magnet motors suffer from the counter EMF generated by the rotor, which limits the rotation speed. When very high slewing speeds are necessary a variable reluctance motor is used.
3/17 189
APPLICATION NOTE
Figure 4 : The three drive sequences for a two phase bipolar stepper motor. Clockwise rotation is shown. Figure 4a : Wave drive (one phase on).
A-
o{~~~.e0
/'
B-
B+
Figure 4b : Two phase on drive.
5-5952
B-
B.
B.
B-
Figure 4c : Half step drive.
A+
oo&w.~e°
B-
A+
~
~e
B-
B+
B+
AO
D~+y c
BO
A-
A+
D~-e
B+
A+
+Jt:\-
~e
B-
4/17
190
APPLICATION NOTE
Figure 5 : A real motor. Multiple poles are normally employed to reduce the step angle to a practical value. The principle of operation and drive sequences remain the same.
PM
STATOR A
phase-on is AC/CB/BO/OA and the half step sequence is NAC/C/BC/B/BO/O/OA. Note that the step angle for the motor shown above is 15 ., not 45 ·. As before, pratical motors normally employ multiple poles to give a much smaller step angle. This does not. however, affect the principle of operation of the drive sequences.
Figure 7 : A variable reluctance motor has a soft iron rotor with fewer poles than the stator. The step angle is 15 · for this motor.
A
c
STATOR
Figure 6 : A unipolar PM motor uses bifilar windings to reverse the flux in each phase.
A
.D I . I
VARIABLE RELUCTANCE MOTORS A variable reluctance motor has a non-magnetized soft iron rotor with fewer poles than the stator (figure 7). Unipolar drive is used and the motor is stepped by energizing stator pole pairs to align the rotor with the pole pieces of the energized winding. Once again three different phase sequences can be used. The wave drive sequence is NC/B/O ; two-
GENERATING THE PHASE SEQUENCES
The heart of the L297 block diagram, figure 8, is a block called the translator which generates suitable phase sequences for half step, one-phase-on full step and two-phase-on full step operation. This block is controlled by two mode inputs - direction (CWI CCW) and HALFI FULL - and a step clock which advances the translator from one step to the next.
Four outputs are provided by the translator for subsequent processing by the output logic block which implements the inhibit and chopper functions.
Internally the translator consists of a 3-bit counter plus some combinational logic which generates a basic eight-step gray code sequence as shown in figure 9. All three drive sequences can be generated easily from this master sequence. This state sequence corresponds directly to half step mode, selected by a high level on the HALFI FULL input.
5/17 191
APPLICATION NOTE
The output waveforms for this sequence are shown in figure 10.
Note that two other signals, INH1 and INH2 are generated in this sequence. The purpose of these signals is explained a little further on.
The full step modes are both obtained by skipping alternate states in the eight-step sequence. What happens is that the step clock bypasses the first stage of the 3-bit counter in the translator. The least significant bit at this counter is not affected there-
fore the sequence generated depends on the state of the translator when full step mode is selected (the HALF/ FULL input brought low).
If full step mode is selected when the translator is at any odd-numbered state we get the two-phase-on full step sequence shown in figure 11.
By contrast, one-phase-on full step mode is obtained by selecting full step mode when the translator is at an even-numbered state (figure 12).
Figure 8 : The L297 contains translator (phase sequence generator), a dual PWM chopper and output control logic.
A INHI B C INH2 0
HALF IFULl cr-+-----.-o-f
STEP
RESET
TRANSLATOR
DIRECTION (CW/CCW) o--+-~"'o Q
C FFJ
I - - - - - - + - - u ENABLE
1-------+--oCON~
+-----+--0 SYNC
GND
SENS 1 Vref SENS 2
osc.
Figure 9 : The eight step master sequence of the translator. This corresponds to half step mode. Clockwise rotation is indicated.
lD01 1000 4
51010
[:]
0001 2
6 0010
OlDl I
8
7
HOME 0100 0110
6/17
192
APPLICATION NOTE
Figure 10: The output waveforms corresponding to the half step sequence. The chopper action in not shown.
Figure 11 : State sequence and output waveforms for the two phase on sequence. INH1 and INH2 remain high throughout.
CLOCK
1001
A ---.I
3
B -,
c
D
I
L
L-
r--
lNHI 0-------------------______________________ _
lNH2 0------------------------------------------
7/17 193
APPLICATION NOTE Figure 12: State Sequence and Output Waveforms for Wave Drive (one phase on).
1000
lD~
"OO,~' 00.
o 8 [2]
0100
CLOCK
A --II
B
C
0 "I
iNHT
INH 2
n
n
n
n
.-
IL
S_S8LJ
INH1 AND INH2
In half step and one-phase-on full steQ modes two other signals are generated: INH 1 and INH2. These are inhibit signals which are coupled to the L298N's enable inputs and'serve to speed the current decay. when a winding is switched off.
Since both windings are energized continuously in two-phase-on full step mode no winding is ever switched off and these signals are not generated.
To see what these signals do let's look at one half of the L298N connected to the first phase of a twophase bipolar motor (figure 13). Remember that the L298N's A and B inputs determine which transistor in each push pull pair will be on. INH1, on the other hand, turns off all four transistors.
Assume that A is high, B low and current flowing
through 01, 04 and the motor winding. If A is now
brought low the current would recirculate through
D2, 04 and Rs, giving a slow decay and increased
dissipation in Rs. If, on a other hand, A is brought low and INH1 is activated, all four transistors are turned off. The current recirculates in this case from ground to Vsvia D2 and D3, giving a faster decay thus allowing faster operation of the motor. Also, since the recirculation current does not flow through Rs, a less expensive resistor can be used.
Exactly the same thing happens with the second winding, the other half of the L298 and the signals C, D and INH2.
The INH1 and INH2 signals are generated by OR functions:
A+ B= INH1
C+ D = INH2
However, the output logic is more complex because inhibit lines are also used by the chopper, as we will see further on.
OTHER SIGNALS
Two other signals are connected to the translator block: the RESET input and the HOME output
RESET is an asynchronous reset input which restores the translator block to the home position (state 1, ABCD = 0101). The HOME output (open collector) signals this condition and is intended to the ANDed with the output of a mechanical home position sensor.
Finally, there is an ENABLE input connected to the outQut logic. A low level on this input brings INH1, INH2, A, B, Cand D low. This input is useful to disable the motor driver when the system is initialized.
LOAD CURRENT REGULATION
Some form of load current control is essential to obtain good speed and torque characteristics. There are several ways in which this can be done - switching the supply between two voltages, pulse rate modulation chopping or pulse width modulation chopping.
8/17 194
APPLICATION NOTE
Figure 13: When a winding is switched off the inhibit input is activated to speed current decay. If this were not done the current would recirculate through 02 and 04 in this example. Dissipation in Rs is also reduced.
Vs
INHI SENSI
,--;o--l-----O B
DRIVE CURRENT---·-~ RECIRCULATION - - - - - ......
The L297 provides load current control in the form of two PWM choppers, one for each phase of a bipolar motor or one for each pair of windings for a unipolar motor. (In a unipolar motor the A and B windings are never energized together so thay can share a chopper; the same applies to C and D).
Each chopper consists of a comparator, a flip flop and an extemal sensing resistor. A common on chip oscillator supplies pulses at the chopper rate to both choppers.
In each chopper (figure.14) the flip flop is set by each pulse' from the oscillator, enabling the output and allowing the load current to increase. As it increases the voltage across the sensing resistor increases, and when this voltage reaches Vref the flip flop is reset, disabling the output until the next oscillator pulse arrives. The output of this circuit (the flip flop's
o output) is therefore a constant rate PWM signal.
Note that Vref determines the peak load current.
Figure 14 : Each chopper circuit consists of a comparator, flip flop and external sense resistor. A common oscillator clocks both circuits.
--ulJl.J FROM osc
9/17 195
APPLICATION NOTE
PHASE CHOPPING AND INHIBIT CHOPPING
The chopper can act on either the phase lines (ABCD) or on the inhibit lines INH1 and INH2. An input named CONTROL decides which. Inhibit chopping is used for unipolar motors but you can choose between phase chopping and inhibit chopping for bipolar motors. The reasons for this choice are best explained with another example.
First let's examine the situation when the phase lines are chopped.
As before, we are driving a two phase bipolar motor and A is high, B low (figure 15). Current therefore flows through 01, winding, 04 and Rs. When the voltage across Rs reaches Vref the chopper brings B high to switch off the winding.
The energy stored in the winding is dissipated by current recirculating through 01 and D3. Current decay through this path is rather slow because the
voltage on the winding is low (VCEsat Ql +V03) (figure 16).
Why is B pulled high, why push A low? The reason is to avoid the current decaying through Rs. Since the current recirculates in the upper half of the bjdge, current only flows in. the sensing resistor when the winding is driven. Less power is therefore dissipated in Rs and we can get away with a cheaper resistor.
This explain why phase chopping is not suitable for unipolar motors: when the A winding is driven the chopper acts on the B winding. Clearly, this is no use at all for a variable reluctance motor and would be slow and inefficient for a bifilar wound permanent magnet motor.
The alternative is to tie the CONTROL ingut to ground So that the chopper acts on INH1 and INH2. Looking at the same example, A is high and Blow. 01 and 04 are therefore conducting and current flows through 01, the winding, 04 and Rs, (figure 17).
Figure 15 : Phase Chopping. In this example the current X is interrupted by activating B, giving the recirculation path Y. The alternative, de-activating A, would give the recirculation path Z, increasing dissipation in Rs.
Vs
!
I
_-D--+-~-"'O B
r;·- ._._ .....I
! :1I . O------------------r---~
5EN51
· i'
x-·-·-~
y------
z ...... ..
5-5943
10/17
196
APPLICATION NOTE
Figure 16: Phase Chopping Waveforms. The example shows AB winding energized with A positive with respect to B. Control is high.
A
B
SENSE RESISTOR CURRENT
LOAD CURRENT __
ICHOPPER OSC. PERIOD
NOTE THAT CURRENT IN SENSE RESISTOR IS .INTERMITTENT
Figure 17 : Inhibit Chopping. The drive current (01, winding, 04) in this case is interrupted by activating INH1. The decay path through 02 and 03 is faster than the path Y of Figure 15.
·Vs I t ___ ,
INHI SENSI
DRIVE CURRENT-.-.-~ RECIRCULATION - - - - - ...
_-D-+-~--{JB
11/17 197
APPLICATION NOTE
In this case when the voltage accross Rs reaches VREFthe chopper flipflop is reset and INH1 activated (brought low). INH1, remember, turns off all four transistors therefore the current recirculates from ground, through D2, the winding and D3 to Vs. Discharged across the supply, which can be up to 46V, the current decays very rapidly (figure 18). The usefu Iness of this second faster decay option is fairly obvious ; it allows fast operation with bipolar motors and it is the only choice for unipolar motors. But why do we offer the slower alternative, phase chopping? The answer is that we might be obliged to use a low chopper rate with a motor that does not store much energy in the windings. If the decay is very fast the average motor current may be too low to give an useful torque. Low chopper rates may, for example, be imposed if there is a larger motor in the same system. To avoid switching noise on the ground plane all drivers should be synchronized and the chopper rate is therefore determined by the largest motor in the system. Multiple L297s are synchronized easily using the SYNC pin. This pin is the squarewave output of the on-chip oscillator and the clock input for the choppers. The first L297 is fitted with the oscillator components and outputs a sqarewave signal on this pin (figure 19). Subsequent L297s do not need the oscillator components and use SYNC as a clock input. An external clock may also be injected at this terminal if an L297 must be synchronized to other system components.
Figure 18 : Inhibit Chopper Waveforms. Winding AB is energized and CONTROL is low.
CHOP CHOP
JLJl..JlSl..JU'
~~~~~OR
CURRENT
CL URRENT _ O _ _ _ _A _ _ _ _O _ _ _ _ ~ _ _ _ _
FAST DECAV
Figure 19 : The Chopper oscillator of multiple L297s are synchronized by connecting the SYNC Inputs together.
11 SYNC
L297
VS
OSC
5V
rz R 16
~
5_S8l.711
IC
---
I
SYNC L297 OSC
16
--
THE L297A
The L297A is a special version of the L297 developed originally for head positioning in floppy disk drives. It can, however, be used in other application-
s.
Compared to the standard L297 the difference are the addition of a pulse doubler on the step clock input and th~availability ofthe output of the direction flip flop (block diagram, figure 20). To add these functions while keeping the low-cost 20-pin package the CONTROL and SYNC pins are not available on this version (they are note needed anyway). The chopper acts on the ABCD phase lines.
The pulse doubler generates a ghost pulse internally for each input clock pulse. Consequently the translator moves two steps for each input pulse. An external RC network sets the delay time between the input pulse and ghost pulse and should be chosen so that the ghost pulses fall roughly halfway between input pulses, allowing time for the motor to step.
This feature is used to improve positioning accuracy. Since the angular position error of a stepper motor is noncumulative (it cancels out to zero every four steps in a four step sequence motor) accuracy is improved by stepping two of four steps at a time.
12/17
198
APPLICATION NOTE
Figure 20 : The L297A, includes a clock pulse doubler and provides an output from the direction flip flop (DIR-MEM).
HALFIFULL 0--+--------1
STEP RESET CCW/CCW
A INHI B C INH2 0
L297A
...----+--0 ENABLE
OIR-MEM
DOUBLER
GNO
HOME SENS 1 Vre! SENS 2
OSC.
APPLICATION HINTS
Bipolar motors can be driven with an L297, an L298N or L293E bridge driver and very few external components (figure 21). Together these two chips form a complete microprocessor-to-stepper motor interface. With an L298N this configuration drives motors with winding currents up to 2A ; for motors up to 1A per winding and L293E is used. If the PWM choppers are not required an L293 could also be used (it doesn't have the external emitter connections for sensing resistors) but the L297 is underutilized. If very high powers are required the bridge driver is replaced by an equivalent circuit made with discrete transistors. For currents to 3.5A two L298N's with paralleled outputs may be used.
For unipolar motors the best choice is a quad darlington array. The L702B can be used if the choppers are not required but an ULN2075B is preferred.
This quad darlington has external emitter connections which are connected to sensing resistors (figure 22). Since the chopper acts on the inhibit lines, four AND gates must be added in this application.
Also shown in the schematic are the protection diodes.
In all applications where the choppers are not used it is important to remember that the sense inputs must be grounded and VREF connected either to Vs or any potential between Vs and ground.
The chopper oscillator frequency is determined by the RC network on pin 16. The frequency is roughly 1/0.7 RC and R must be more than 10 Kn. When the L297A's pulse doubler is used, the delay time is determined by the network Rd Cd and is approximately 0.75 Rd Cd .Rd should be in the range 3 kQ to 100 kn (figure 23).
13/17 199
APPLICATION NOTE
Figure 21 : This typical application shows an L297 and L298N driving a Bipolar Stepper Motor with phase currents up to 2A.
Vs
( !>v
( 36V
c~
Un' :J:
GNO
R1
-c:J-
12 lin
OSC
: t~CL 100nF
c~ --I~nF
_,..470
;,F
r
01 02 D~ 04
~~ ~~
~~
CW/CCW 1 16
"
12 A
~
9 !>
8
4 I
01
)
(LOCII 18
8 Ii
1
~
HALF/ML 19
C 1
10
3 02
f STEPPER
--
L297
L298N
MOTOR
RESET 20
0 9
12
1] 03
WINDINGS
ENABLE 10
INH I !>
Ii
Yr{,f 15
8 INH2
11
l "I 11 I 3 13
SENSEI SENSEI
1
CONIROl
HO..,E
SYNC.
14~f--
15
05 06 01 oa
_ -- -- A~ ~~ A.. A~
-"- ....
5- 5646/4
RS1 RS2 ~ 0.5 Q D1 to D8 ~ 2 Fast Diodes
VF ,; 1.2 @ I ~ 2 A trr ,; 200 ns
14/17
200
APPLICATION NOTE
Figure 22 : For Unipolar Motors a Quad Darlington Array is coupled to the L297. Inhibit chopping is used so the four AND gates must be added.
Us.24U
A INH1
8 5ENS1
.
2 x 8ZW84-48
.
2 x 8ZW84-48
J: 188nF
1
8
9
ULN
20758
Rs1
16 0
IHH2
C
15 SENS2
Rs2
N92I1N4?B-Bt
Figure 23 : The Clock pulse doubler inserts a ghost pulse 'to seconds after the Input clock pulse. Rd Cd is clasen to give a delay of approximately half the Input clock period.
'fRd ~
L297A
Cdf
--
CLOCK
PULSE DOUBLER OUTPUT
~ I ,
U ,
U I
I , , I
U
,
W U LJ
I
I
'S-':l6'B
15/17
201
APPLICATION NOTE
PIN FUNCTIONS - L297
N°
Name
Function
1
SYNC Output of the On-chip Chopper Oscillator.
The SYNC connections of all L297s to be synchronized are connected together and the
oscillator components are omitted on all but one. If an external clock source is used it is
injected at this terminal.
2
GND Ground Connection.
3
HOME Open collector output that indicates when the L297 is in its initial state (ABCD = 0101).
The transistor is open when this signal is active.
4
A
Motor phase A drive signal for power stage.
5
INH1
Active low inhibit control for driver stages of A and B phases. When a bipolar bridge is
used this signal can be used to ensure fast decay of load current when a winding is
de-energized. Also used by chopper to regulate loadcurrent if CONTROL input is low.
6
B
Motor phase B drive signal for power stage.
7
C
Motor phase C drive signal for power stage.
8
INH2 Active low inhibit control for drive stages of C and D phases. Same functions as INH1.
9
D
Motor phase D drive signal for power stage.
10 ENABLE Chip enable input. When low (inactive) INH1, INH2, A, B, C and D are brought low.
11 CONTROL Control input that defines action of ch~. When low chopper acts on INH1 and INH2 ; when high chopper acts on phase lines ABCD.
12
Vs
5 V Supply Input.
13
SENS2 Input for load current sense voltage from power stages of phases C and D.
14
SENS 1 Input for load current sense voltage from power stages of phases A and B.
15
Vref
Reference voltage for chopper circuit. A voltage applied to this pin determines the peak.
load current.
16
OSC An RC network (R to Vcc , C to ground) connected to this terminal determines the chopper
rate. This terminal is connected to ground on all but one device in synchronized multi -
L297 configurations. f '" 1/0.69 RC, R> 10 kQ.
17 CWICCW Clockwiselcounter clockwise direction control input. Physical direction of motor rotation also depends on connection of windings. Synchronized internally therefore direction can be changed at any time.
18
CLOCK Step Clock. An active low pulse on this input advances the motor one increment. The step
occurs on the rising edge of this signal.
19 HALF/FULL Half/full Step Select Input. When high selects half step operation; when low selects full step operation. One-phase-on full step mode is obtained by selecting FULL when the L297's translator is at an even-numbered state. Two-phase-on full step mode is set by selecting FULL when the translator is at an odd numbered position. (the home position is designated state 1).
20
RESET Reset Input. An active low pulse on this input restores the translator to the home position
(state 1, ABCD =0101).
16/17
202
APPLICATION NOTE
PIN FUNCTIONS - L297A Pin function of the L297A are identical to those of the L297 except for pins 1 and 11.
N°
Name
Functions
1 DOUBLER An RC network connected to this pin determines the delay between an input clock pulse and the corresponding ghost pulse.
11 DIR-MEM Direction Memory. Inverted output of the direction flip-flop. Open collector output.
Figure 24 : Pin connections.
SYNC
GND
HOME
A
4
INH1
B
C INH 2 D
ENABLE
L297
REID
19 HALF/FULL
CLOcii
CW/CCW OSC Vr~f
SENS 1 SENS 2
Vs
CONTROL
!J-~aJg
DOUBLER
GND
HOME
A
INH1
5
B
C
INH,
8
D
ENABLE
20
RESET
19 HALF/FULL
18 17
L297A 16
CLOCK CW/CCW
OSC
15
Vref
. "
SENS I
SENS 2
Vs
DlR-MEM
S-'l>B40
17/17
203
DC AND BRUSHLESS MOTORS!
205
APPLICATION NOTE
TWIN-LOOP CONTROL CHIP CUTS COST OF DC MOTOR POSITIONING
by H. Sax, A. Salina
Using a novel controllC that works with a simple photoelectric sensor, DC motors can now com-
pare with stepper motors in positioning applications where cost is critical. The chip contains two complete control circuits, so that two motors can be controlled with one IC.
Since the introduction of integrated power drive stages, stepper motors have been the most popular choice for positioning drives in cost-critical applications like printer carriage control. Though DC motors are cheaper, require less power and provide more holding torque, they were rejected because they needed a costly shaft angle encoder to achieve comparable performance.
Today, however, it is possible to build a cheap, fast and efficient DC motor positioning drive that uses a simple optical encoder. What makes this possible is an integrated circuit - the SGSTHOMSON type L6515 - that embodies a twinloop control system and uses a novel tacho conversion scheme which works effectively without high precision sensors.
The new IC is designed to work in a system shown schematically in figure 1. Actually the device contains two complete control circuits because most applications involve two motors. For simplicity only one half is shown. The system is
controlled by a micro and uses a high-power bridge IC as the output stage to drive the motor. On the motor shaft is an optical encoder that provides two sinusoidal or triangular outputs 90° out of phase.
Two closed-loop operating modes are used: speed control and position control. At the beginning of a positioning action the system operates in speed control mode. The microcontroller applies a speed demand word to the L6515's DAC, normally calling for maximum speed. The motor current rises rapidly, accelerating the motor to the desired speed, which is maintained by a tacho feedback voltage derived from the sensor signals.
A counter in the micro monitors the squared sensor outputs, counting pulses to determine the distance travelled. As the target position is reached the micro reduces the speed demand word stepby-step, thus decelerating the motor. Eventually, when the speed demand word is zero and the final position very close, the micro closes the po-
Figure 1: A highly integrated control circuit using novel circuit techniques makes it possible to design a dc motor pOSitioning system that competes with stepper motors. This device is used with a bridge power stage and optical encoder.
SPEED DEMAND
~--~
WDRD
~----~
BRIDGE DRIVER IC
ru
PWM
MCU
COUNT
Jl.rIIU1...
LrI
1/2 OF
L6515
.r
DIRECTION
\
SQUARED TACHO SIGNAL FOR
POSITIDN COUNTING
TACHO FEEDBACK
fl92f1N45?-B2
AN457/0392
1/8
207
APPLICATION NOTE
Figure 2: Unlike conventional tacho converters the L6515 uses this circuit which does not depend on a high-precision mechanism because it exploits the crossover points between the sine and cosine signals from the encoder.
n92I1N45?-B1
S1
sition loop - where one of the sensor outputs is connected directly to the error amplifier - forcing the motor to stop and hold in a position corresponding to a zero crossing of the sensor signal.
This combination of closed loop speed control, pulse counting and closed loop position control gives very fast and precise positioning.
GENERATING THE TACHO SIGNAL
Systems working on this basic principle have been used before, but ,they used a conventional tacho conversion scheme where the encoder outputs are converted to a voltage proportional to speed by differentiation and synchronous rectification. To make this scheme work the encoder signals must be exactly sinusoidal or the tacho output will not be sufficiently precise. This in turn calls for great mechanical precision in the encoder construction and electronic brightness control for the light source. Such encoders are intrinsically expensive.
One alternative is to design a purely digital system, where the controller simply processes pulses from a simple encoder. However, this would require an encoder with a large number of steps/rotation to keep the loop stable at low speeds and guarantee the necessary precision. Also, at high speeds the pulse rate would overload low cost microcontrollers.
A completely new approach has been chosen for the L6515 which solves this problem. Rather than depend on the magnitude of the signals, this method relies on sensing the tN/llt between crossovers in the encoder signals (figure 2).
How this works can be seen in the waveforms of figure 3. First the two encoder signals are in-
Figure 3: Waveforms and truth table for the tacho conversion circuit in figure 2.
~ . . . . . . . . POlA POlB
UREF
",
. ~ ~.
, ~
-........ ~
~
... ' .
.,....._ ... :',_~.:
t
~~_ .. "' .....
POlA ' PDlB '
t C1
I
i
r
t C2
I
I
I
TRUTH TABLE, S1 - S7
C1
C2 CLOSED
S71N POSITION
L
H
S1
H
H,
S2
H
L
83
L
L
84
TSPO T8PO TSPO TSPO
2_/_ 8 _ _ _ _----:_ _ _ _ _ 'r'l SGS-THOMSON _ _ _ _ _ _ _ _ _ _ __ A.,~ ~DCI!I@rnl.lEC'ii'DlWlDCiII
208
APPLICATION NOTE
Figure 4:Th~ system ope~ates with a simple, inexpensive optical encoder which has only one adjustment, which ensures that the maxima of the sine and cosine waveforms are within a certain tolerance. All other tolerances are guaranteed by the construction of the encoder.
;. L2·· .. ···················· 'LP2':
U AMPLITUDE
Rl
LP3 : 4.3 r----------------JL--------
LP6 :
3.B r-.f--~~~~---,r---~~
39
SEl
: K198P :
2.Br---~+_--~--~~--~----;-.
M M1:
5
+ .
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LPl : Ll
.......... _-_ .... _-- ...· ------ .. -!
1.B~~+++_--~~.__,~--~--1.3r---+++_---,~-------------
8
PHASE ERROR
"92I1N457-94
± 20·
verted, giving a total of four signals. One of these is selected by the switches S1 to S4 depending on the outputs of the two comparators which cross-compare the sine and cosine signals. The selected encoder signal is then differentiated and the output inverted or not depending on the two comparator outputs.
The beauty of this approach is that it is independent of the encoder waveforms - they can e~~n b.e triangular. Th.e only requirement for precIsion IS that the maxima of the sine and cosine waveforms must be within a certain tolerance, ensuring sufficient precision in the crossover points. This can be achieved in practice with a simple mechanical adjustment.
Figure 4 shows an encoder used in this system and how it is attached to the motor. For an encoder of this type and a resolution of less than 100 steps/revolution no other adjustments are necessary because the mechanical construction guarantees all of the other tolerances.
CLOSING THE POSITION LOOP
As we have seen above, the tacho loop is augmented by a position loop for the final precise positioning and holding. How the two loops are connected in shown in figure 6.
The eight bits from the microcontroller consist of five bits for the magnitude of the speed demanded, one bit for its sign (and hence the motor direction) and two bits which select which half of the Ie is addressed. If a speed demand word of 00000 is loaded one of the two switches S5 or S6 is closed, depending on the direction selected. Thus one of the encoder signals is connected directly to the summing point of the error amplifier input and the motor will be brought to a halt at the zero crossover of the encoder signal. It will remain in this position until a new position operation is initiated.
At the output of the error amplifier is the pulsewidth-modulation circuit which drives an external power stage (figure 8).
In basic outline this circuit is very simple: the error
~ ~~~;m&r::oo~l: __________________________3_/8
209
APPLICATION NOTE Figure 5: Application Circuit
16
REF
12 .5
13
'5
17
~ )t ...
05C~
19
29
'5
33
L6515
23 24 25 26 27
28
34
21
"
30 31
28 22
32
37
38 39
48
.41 42
43 35 36 .5
. ENCODER
LOAD
~ ~a:::=)
1192L5515-1 J
a. Figure 6: Shown schematically, the complete system has main, velocity loop where the tacho signal
and the output of a DAC are compared in an error amplifier which drives a PWM output stage. For final positioning S5 or S6 is closed, forming a position loop.
TO OTHER CHANNEL
4/8
210
!192ffNJ5?-f35
APPLICATION NOTE
Figure 7:Because there is a single sense resistor connected to the lower legs of the bridge the current feedback voltage does not reflect the polarity of the motor current. Before the feedback signal can be added to the error signal its polarity must be restored.
LOAD CURREI'IT
A
8
POSITIUE LOAD CURREI'IT
f-----~--_:___--t
i !
I I'IEGATIUE LOAD
I
j ....... j
....
.
CURREI'IT
I
URS f--------1:----+-- t
A
B
tUs
tUs
A
8
I
I .
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A
B
tUs
tUs
Rs
Rs
"92I1H45?-86
Rs
Rs
---------------------------
~~~~~~~~:~~
5/8
---------------------------
211
APPLICATION NOTE
Figure 8: The pulse width modulator is formed by an oscillator (9) and a comparator (4). Switch S8 and (1) restore the correct polarity to the voltage from the current sense resistor.
9
OAC
TACHO
FTB
~ 56
Rp
FTB ~ 55
R5
:I
-
. I
-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.~
amplifier output sets the threshold of the comparator 4, thus transforming the triangular wave from the oscillator into a rectangular signal whose duty cycle depends on the error amplifier output amplitude.
Feedback is provided by the sensing resistor Rs, which provides a voltage proportional to 1M.
The whole loop works in current mode which controls the torque 6f the motor.
Figure 9:The gain of the current loop is set by R5, while the maximum current can be set independently by the sense resistor, Rs.
Us-BEMF
,-----
,- '-
I
M-
--
RM
-
! ~ WITHOUT LIMITING
~
r--r---+-. MAX CURRENT 5ET BY Rs
SLOPEtTRANSCONOUCTANCEI SET BY Rs
----------,r--------++
ERROR CURRENT
IOAC-ITACHO
ff92I1N45?-88
6/8
----------------
~~~~~~~~~:~
----------------------------
212
APPLICATION NOTE
Figure 10:There are six distinct phases in an elementary positioning operation. These waveforms show the corresponding speed demand word, actual motor speed and motor current.
+
f192f1N45?-99
However, in practice it is necessary to reconstruct the polarity of the feedback voltage because the voltage across Rs is always of the same polarity, regardless of the direction of the drive current. This is performed by the inverter in the feedback path which is switched by S8 depending on the direction of the drive signal, which controls the current direction.
When the motor is accelerating rapidly to the set speed the current control loop saturates so the load current could increase to the point where the power stage or motor may be damaged.
To prevent this a limiting circuit formed by stages 6, 7 and 8 has been included. Normally the flip flop is reset periodically by the Rs oscillator and remains in the reset state; consequently the EXOR gate is "transparent", having no effect on the PWM output. When, however, the current exceeds a positive or negative threshold the flip flop will be set, thus the EXOR gate will invert the PWM output thus reversing the bridge drive, causing the current to drop rapidly.
Figure 8 shows the loop characteristics of the system and how they are controlled.
The loop gain is set by the resistor R5, while the maximum current is set independently by the sensing resistor Rs. These components can be set to accommodate a wide variety of motors and conditions.
Now that the circuit functions have been explained it is possible to follow in detail the functioning of the device. A basic positioning operation would consist of six steps (figure 10):
A.Acceleration, where the current is at a maximum limited by stages 6/7/8 (indicated in figure 8)
B.End-of-acceleration, where the current is reduced under control of stages 3/4
C.Constant speed, where tacho feedback controls the current at a low value
D.Deceleration, where the current is limited by stages 6/7/8
E.End-of-deceleration, where the current is controlled by 3/4
F.Positioning, where either S5 or S6 is closed.
In practice phase D will be replaced by a series of decelerations to bring the motor speed down smoothly to zero at the destination point. Figure 10 shows the corresponding waveforms.
HIGH POWER BRIDGE ICs The L6515 control IC is designed to be used with monolithic high power bridge driver ICs which are widely used today for DC and stepper motor driving. These devices are very simple to use because they are controlled by logic level inputs and include basic protection circuits to prevent damage in case of a fault in the controller or software. Suitable types for output currents from 500mA to 4A are listed in Table 1. Note that bridge drivers
- - - - - - - - - - - - - - ".,1 r== SIiVGIDS©l.i1JmHl~O©llMliSJ@iO!DNC$
7/8
--------------
213
APPLICATION NOTE
Figure 11 : In a real positioning operation the deceleration of the motor is controlled smoothly by a progressive reduction of the speed demand word.
IDAC
1
N> "
'"j=Ly "
N-STEPS
!1 !\
nI,. pos SW ITCH -/~
FTB
v
t
using DMOS power stages make it possible to obtain 1.5A output current using a DIP package, which is very compact and convenient for assembly. Also, single power ICs containing two bridges are available, so it is possible to make a positioning system for two motors with just two ICs.
The same BCD technology used to make smart power bridges like the L6202 and L6204 is also employed in the L6515, even though there are no power stages in the device. This technology is, in fact, highly suitable for this IC because it combines high density logic with the precision of bipolar circuits. Moreover, it also allows the inclusion of very low resistance MOS transistors which are needed in the tacho conversion switching circuits.
SOFTWARE
Software to control the L6515 must initialize the system at each reset then manage each positioning operation.The initialization routine is very
Table 1: High Power Bridge Driver ICs
simple; bringing the two latch control inputs R & S high together resets both of the latches at the DAC inputs. (see Figure 5).
At the same time the position counters in the micro will be zeroed. If the mechanical subsystem is in an unknown position the motor will have to be driven at a moderate speed to a known position during this phase. In a printer, for example, it can be driven towards an endstop.
For each positioning operation the micro will have to determine a suitable profile - in particular when to begin deceleration. Then, once the first speed demand word has been latched into a DAC it will have to count the squared encoder pulses, usually with an interrupt routine. At specific distances from the end point reduced speed demand words will be loaded and then when the final position has been reached a zero speed demand word will be loaded; this automatically activates the position loop.
TYPE
L6204 L6201 L6202 L298N L6203
HIGH-POWER BRIDGE DRIVER ICs
FUNCTION
TECHNOLOGY OCCURRENT
DUAL BRIDGE BRIDGE BRIDGE DUAL BRIDGE BRIDGE
DMOS DMOS DMOS BIPOLAR DMOS
0.5A 1 A 1.5 A 2A 4A
PACKAGE
20 - PIN POWERDIP 20 - PIN SO 20 - PIN POWERDIP 15 - PIN MULTIWATT 11 - PIN MULTIWATT
8_/_ 8 _ _- - - - - - - - -
r== SCS-mOMSON
....,/ liIlu©liil@rn~rn©1rll@iilU©~
_ _ _ _ _ _ _ _ _ _ _ __
214
APPLICATION NOTE
HOW TO DRIVE DC MOTORS WITH SMART POWER ICs·
by Herbert Sax
There are many ways to control DC motors. Open-loop current control acts directly on torque and thus protects the electronics, the motor and the load. Open-loop variable voltage control makes sense if the motor and electronics are not overloaded when the motor stalls. Open-loop
variable voltage control with a current limiting circuit constitutes the simplest way of varying speed. However, a closed-loop system is needed if precision is called for in selecting speeds.
No other motor combines as many positive characteristics as the direct current design: high efficiency, ease of control & driving, compactness without sacrificing performance and much more. And DC motors can be controlled in many ways - open loop current control, variable voltage control or closed-loop speed control - providing great flexibility in operational characteristics.
Before we turn to a detailed discussion of the various methods of control, it is worthwhile recalling a few basics.
DC MOTOR BASICS
Generally speaking, the electric equivalent circuit of a motor (figure 1) consists of three components: EMF, Land RM.
Figure 1: Electrical equivalent circuit of a DC motor, consisiting of EMF, the winding inductance L and the winding resistance RM.
RM
L EMF
1M Us
L...-----1~/·IIJj-f1-9-Bn-H-3-8....JB-Bt
The EMF is the motor terminal voltage, though the motor is always a generator, too. It is of no significance whether the unit operates as a motor
AN380/0591
or a generator as far as the terminal voltage is concerned. The EMF is strictly proportional to the speed and has an internal resistance of zero. Its polarity represents the direction of motion, independent of the motor voltage applied.
The winding inductance, L, is the inevitable result of the mechanical design of the armature. Since it hinders the reversal of current flow in the armature, to the detriment of torque as speed increases, the winding inductance is an interference factor for the motor. It also obstructs rapid access to the generator voltage (EMF).
Motors of coreless, bell armature or pancake design are considerably less susceptible to winding inductance. The smaller mass of these motors improves their dynamic performance to a significant extent. On the positive side, the winding inductance can be used to store current in pulse-width modulation (PWM) drive systems.
The winding resistance. RM, is purely an interference variable because losses that reduce the degree of efficiency increase as the load torque on the motor shaft increases, the latter being proportional to the current 1M. It is also due to the winding resistance that the speed of the motor drops as load increases while the terminal voltage Vs remains constant.
Some of the mathematical relationships are shown below in simplified form:
EMF = VS-(IM.RM)
Motor current 1M = (Vs - EMF)/RM
TN Eft' . IClency
=
EMF· 1M Vs' 1M
=
POUT
The drive torque at the motor shaft is proportional to the motor current 1M. Figure 2 shows the relationships graphed in a form commonly used for DC motors. It is because of bearing and brush friction that the efficiency tends towards zero at low load torques.
1115 215
APPLICATION NOTE
Figure 2: Relationship between speed, efficiency and motor current of a DC motor.
11'\,. I RPM
power ICs and illustrating open-loop variable volt-
age or current control and closed loop speed control are discussed here. All of these circuits permit the motor to run in both directions. The modifications needed for unidirectional operation are slight and generally involve a simplification of the design.
n!lBIIH3BB-B2
LOAD TORQUE-+
These basics show that essentially there are only two parameters governing how an electrical change can be made to act on the motor shaft:
a) with the current to vary the torque
b )with the mapping of the EMF on the speed
On account of the winding resistance RM, open loop variable voltage control exercises no more than an indirect effect on torque and speed and can therefore be used only for simple functions (speed variation).
A number of sample applications using smart
OPEN·LOOP VARIABLE VOLTAGE CONTROL
In technical terms variable voltage control is the simplest to implement. Its main scope of application is in simple transport or drive functions where exact speed control is not essential. Applications of this kind are found, for example,in the automobile industry for driving pumps, fans, wipers and power window lifts.
The circuit shown in figure 3 is an example of a variable speed motor with digital direction control. The motor voltage can be controlled via an analog input. If the polarity of the control signal is the variable that determines the motor's direction of rotation - as is usually the case in servo systems, for example- the design shown in figure 4 can be used.
One of the operational amplifiers is responsible for the VMNiN voltage and the other has an gain of 1, so that the voltage losses Vs - VM are divided evenly between the two parts of the bridge.
Equivalents to the circuits in figures 3 and 4 are shown in figure 5 and figure 6; these latter circuits, however, are switch mode and their efficiency is thus improved to a considerable extent.
Figure 3: Circuit for driving a variable-speed motor. Where the enable function is needed, the type L6242 can be used.
+Us
L
+UIN
R
19K
R1+R2
UM.UIN · - - - -
R2
119B/lN3BB-B3
-- 2/15 ------------ LV ~~~~m&r;,:~~~ --------------
216
Figure 4: A typical circuit for driving servo system.
1K 18K
R2
±UIN
R2
1K 18K 18K UM.UINRo1-
R2
-Us
I1SBAH3SB-B4
Figure 5: Equivalent circuit to that in Figure 3, but using PWM.
SU
APPLICATION NOTE
L
ruu
L6506
-SU
R
ruu
-12U
1BeK
3313
1. 5nF. :r:::
+UIN~------------------------~
Figure 6: Equivalent circuit to that in Figure 4, but using PWM.
r---~--c:::l-----, L M3 2 4
IfSBIIH3SB-BS
-Us
2.SU 2.SU ±UIN ~------------------~--~
e.1uF
~M
I1!1Bf/H3SB-B6
--------------------------- LW ~~~~~:~~i!~~ ---------------3/15
217
APPLICATION NOTE
OPEN-LOOP CURRENT CONTROL
Open-loop co~trol is called for whenever a motor
has to supply a constant or variable torque. Applications include the head motors in tape recorders or the motors used to tension threads when textile fibers are wound onto spools. The speed of the motor at any given time is of no significance. In applications of this nature the motor shaft will often rotate in the direction opposite to that determined by the current.
Two conditions are particularly important in a current controlled application. The circuit will not operate unless VMmax ~ EMF + (1M RM), if the motor shaft is running in the same direction as the drive. The equation applicable to a counter rotating motor shaft is:
-VMmax -EMF s; 1M RM
Open-loop current control is often used in con-
junction with open-loop variable voltage control or closed loop speed control. Such an arrangement would be designed to:
· limit torque to protect the load and the motor
· protect the power ICs against overload
· obtain acceleration and deceleration characteristics independent of speed.
Figure 7 shows the simplest form of open-loop current control with a positive & negative supply. Transferring the circuit to a bridge eliminates the ground at one end of the shunt Rs and a way of differentially sampling the sense resistor voltage must be found. One solution is shown in figure 8. As in figure 4, the second half of the bridge operates as a voltage inverter.
Figure 7: Current control circuit with bipolar voltage supply in its simplest form.
+Us
b.
-Us
±UIN R2 R1
1198I1N388-8?
1M . -UIN- 0R-1
Rs
R2
Figure 8: This circuit permits differentiated sampling of the voltage at the sense resistor.
+Us
R2 R1
10K
1198f1N3B8-BB
U1N R1
1M . - -
Rs
R2
- - 4/15 - - - - - - - - - - - - ~ ~~~~m&r;,:I!~~ - - - - - - - - - - - - - -
218
APPLICATION NOTE
When the principle behind ~he circuit sho,,:,n i~ figure 8 is transferred to a sWltchmode circuit (figure 9) a considerable degree of complexity is called fo; to reduce power loss. For this reason the circuit is shown.in slightly simplified form.
Operational amplifier 1 reconstructs the curre~t proportional voltage VRS to ground as shown In figure 7. Two sense resistors are needed, as.otherwise it would not be possible to detect the direction of the current in the bridge.
Operating as a PI controller and converting the error signal in a PWM via comparator 3, OP2 compares the reference and. fe~dback values. One major advantage of a circuit such ~s t~at shown in figure 9 is its high transfer Iineanty maintained even in the vicinity of the zero current crossing. Open-loop current control also functions .
with a generator, the motor returning its own kinetic energy and that of the load to the supply voltage in a controlled mann~r. ~raking i.s a c~se in point, and for this reason circuits of this design are usually found in servo positioning drives that demand precise current control over a wide operating range.
CLOSED-LOOP SPEED CONTROL
Many circuits, often of completely different dec sign, have been developed for closed-loop speed control. The most suitable system has to be chosen on the basis of the requirements that a drive concept has to meet. These requirements also determine how the speed will be sensed and processed.
Figure 9: Operating principle of th.e circuit of figure 8 transferred to a PWM arrangement.
+us
tUrN
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- - - - - - - - - - - - - - . ., , / ~O~lll@~~~II:1flll@OOO~$
219
APPLICATION NOTE
The table provides an overview of the most common principles of sensing and processing and
their influence on control characteristics and system costs.
CHARACTERISTICS
CONTROL ACCURACY
HIGH MEDIUM
LOW
EXTENDED CONTROL RANGE POSSIBLE
CONTROL REACTION
FAST SLOW
GOOD CONTROL CHARACTERISTICS AT LOW SPEEDS
SUITABLE FOR SERVO DRIVES
SYSTEM COST
HIGH MEDIUM
LOW
PRINCIPLE OF SPEED SENSING
SIGNAL PROCESSING AC REFERENCE
DC
V-I
EMF
··· ·· ··· ·· ·· ··· ·· ·· . ·· Tacho Control Sense
AC Tacho
ommu tation Sense
P
PI
PID PLL' Digital
Control Control Control Control Sensor
· ·
· ·
· ·
·
·
·
·
· ·
· ·
· ·
.
· ·
CLOSED-LOOP CONTROL PROCESSES
DC Tachogenerator
~ince a co~trol circuit with a DC tacho-generator Yields a direct voltage that is proportional to speed, th~ circuit itself is less complex than all other designs. Nonetheless, high precision - a constant voltage with low ripple - signifies high cost. On the other hand, the actual electronic control circuit is simplicity itself, as figure 10 shows. The bridge extension for a simple supply voltage
is identical to that shown in figure 8.
A closed loop current control system providing braking and acceleration independent of the supply voltage and the internal motor resistance is easy to superimpose on the circuit (figure 11).
~imil.ar,ly li,ttle difficulty i,s involved in modifying the circuit In figure 10 to Yield a switched bridge, because the process entails no more than converting the control error signal into a PWM output (figure 12).
Figure 10: Control with DC tachogenerator: a direct speed proportional DC voltage is generated,
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±urN
t
Us-EMF
1M
RM
:c
-RPM
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220
APPLICATION NOTE Figure 11: In this circuit, accel~ration and braking behavior is independent of the supply voltage and the
motor's Internal resistance.
+us
+RPM
t
urN
. - ±Uomax Rl
IMmax -
Rs
R2
-RPM
t19BflN3BB-tt
Figure 12: PWM conversion of the control error signal.
-Us
>urN
1198I1H388-12
V-I Control (Internal Resistance Compensation)
V-I control is based in the principle that the volt-
age drop incr.eases
a~titthhelomadototor riqnuteerncaalnrebseistcaonmcpeen1M~attheadt
by Increasing the motor voltage VM (figure 13).
However, compensation is less than complete be-
cause the winding resistance RM is heavily de-
pendent on the temperature, and brush resis-
tance modulation makes itself felt as an additional interference variable.
In. practice this means that the voltage drop is slightly under compensated and positive feedback is reduced even further as frequencies get higher. The control action result improves with the ratio of EMF to IM.RM. A sample circuit in which the effect of the positive feedback loop can clearly be seen is shown in figure 14.
_ _ _ _ _ _ _ _ _ _ _ _ Gi,/ SCS-11fOMSON _ _ _ _ _ _ _ _ _ _ _7_/1_5
· h
I'llln©;oorn~rnC1TIlJ@ll'Jn©@
221
APPLICATION NOTE
The desired speed is set with the aid of R1 and R2. The relationship is expressed as:
EMF = VIN . R1/R2
The value selected for Rs is one tenth of RM and VRS is amplified by a factor of 10 in OP2 (R5 = R4/10). The output voltage of OP2 is then identical with the voltage drop at RM. When R1 = R3, the inter-
Figure 13: The principle of V-I control.
nal resistance is compensated by 90%. Residual control instabilities can be cancelled out by C1.
The circuit can also be extended to a bridge, although this entails relocating resistor Rs (figure 15). It is surprising that the V-I controller circuitry is again simplified to a considerable extent if amplification is not needed. The V-I control concept can be adapted for a PWM motor control system; the functional layout is rather complex, however, as figure 16 shows. Even so, it is worthwhile in many instances because DC tacho-generators are expensive.
t19BIIN38B-i3
1M CONTROLS UM
Figure 14: Example circuit in which the positive feedback loop can clearly be seen.
tUIN
+Us
-Us R2 R1
R3
URS Rs
M
C1
R5
t19BIIN38B-t4
-- 8/15 ------------ LV ~~~~~~~:>!~~ --------------
222
Figure 15: Circuit as in figure 14, expanded to include a bridge.
APPLICATION NOTE
R2
R1 tUrN
. ±UIN
RM R1
EMF-~-
Rs R2
+Us
R R
R
f19BflN3BB-15
Figure 16: The principle of V-I control transferred to a PWM motor circuit: complexity is increased significantly.
tUrN
N9BIUO{38B-t5
-------------- --------------l:;j ~~~~m~~r::oo~~
9/15
223
APPLICATION NOTE
EMF Sensing The EMF can also be sensed directly, rather than be simulated as in the V-I control setup, when the
current 1M is zero (EMF = VM-IM.RM). To achieve
this the motor current must be switched off as
quickly as possible. Motor inductance represents an obstacle since the energy it stores must first
be dissipated before an EMF measurement can be made at the motor terminals. This is the rea-
stored in a capacitor until the next sampling phase. The number of cycling cycles per second depends on the dynamic behavior of the load torque. The interval between any two EMF mea-
surements should be of a duration such that the kinetic energy of the drive system bridges a load change without a significant speed drop. Figure 18 illustrates a layout using a current-controlled
output stage that has a high impedance output when the input is open.
son why only coreless motors of bell armature or
pancake design are suitable. Figure 17 is a block
diagram showing how the EMF can be sensed. In the major partial time t1. the fl.lotor car~ies current. This is followed by a time window t2 In which
the motor is de-energized and the motor induc-
tance discharges. There then follows a short sampiing phase t3 in which the EM F is sensed and
The circuit for sensing EMF is particularly well suited to switch mode motor control schemes. The
monolithic switching output stages available today
already have an enable input for releasing the motor, but the concept will usually accommodate this option even if discrete output stages are used. An example circuit is shown in simplified form in figure 19.
Figure 17: Principle by which the EMF can be sensed.
+Us
U
tUrN
UM
EMF
-Us t2:1~
t3
MIG
CJ:
. t1 t2 ·t3:
t
f19BflN3BB-f?
Figure 18: Driver circuit with current controlled output stage with high impedance output when input is open.
tUrN
HCF4066
HOLD AMPLIFIER : ........... .
119BflN3BB-tB
LW _10_/_15_ _ _ _ _ _ _ _ _ _ _ _ _
~~~;m~::oo~l: ----------~---
224
Figure 19: Circuit as in figure 18, but with PWM output stage.
APPLICATION NOTE
tUIN
R2
EMF · UIN · - · -
R2 R4
115Bf1N38B - t 5
AC Te,=hogenerator
Economic and with a signal that is easy ·to pro-
cess, the AC tachogenerator is the .most frequently used means of sensing the speed of a DC motor. Problems arise, however, when the tachogenerator frequency is low, due either to a low speed or a lack of poles on the generator. However, multiple pole tachogenerators are expensive regardless of whether they are magnetic or optical. Most circuits convert the speed proportional tach a frequency back into a DC signal in an fN converter (Fig. 20).
However, some circuits make use of the proportional relationship between speed and AC voltage amplitude when the tachogenerator is inductive (figure 21). Accuracy is wanting to a certain extent in this arrangement.
Since the output signal of an AC tachogenerator contains no information concerning the direction of rotation, the control loop functions in only one quadrant. For the same reason it is common practice to control the reference in a single quadrant. A separate digital signal determines the direction of rotation. Figure 22 shows a typical
Figure 20: The tachogenerator frequency can be converted back into a DC signal in an fN converter.
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225
APPLICATION NOTE
PWM circuit.
Comparator 1 converts the sinusoidal tachogenerator signal into a squarewave voltage that triggers the monostable. The ON time is constant, which means that the DC average. increases proportionally as the tachogenerator frequency increases. The error amplifier OP1 also functions as an integrator (C1) and compares the DC reference with the DC average of the monostable output. A DC signal superimposed by a triangular wave AC voltage component can be detected at the output of OP1 .
An analog power operational amplifier can also be used instead of the switch mode output stage. In an arrangement like this, the output of the error amplifier OP1 drives the VIN input of the output stage as shown in figure 3.
Figure 21: Alternatively, the proportionality between speed and AC amplitude can be used if the tachnogenerator is inductive.
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Figure 22: In this PWM circuit the comparator 1 converts the sinusoidal tachogenerator signal into a squarewave.
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226
COMMUTATION Sensing
Commutation sensing is a process that exploits the inherent ripple of the EMF of the motor current as an AC tachogenerator. However, only motors with few poles yield an adequate signal-tonoise margin. Three-pole motors with an AC component equal to approx 30% of the DC value are most suitable (figure 23).
The rapid current reversal is differentiated and used as an equivalent tachogenerator signal (figure 24). The rest of the circuit follows the pattern shown in figure 22, although only one output stage of the type shown in figure 3 is used. A sWitch mode output stage would interfere with the ripple sensing so is not recommended. One drawback of commutation sensing is the exceptionally low tachometer frequency. A three pole motor, for
Figure 23: Principle of commutation sensing.
APPLICATION NOTE
example, produces a frequency of 200Hz at a speed of 2000 rpm.
Since the AC component of the OP1 error amplifier output signal (figure 22) should not be more than 10% of the DC component at rated speed and nominal load torque, the integrator time constant C1 R1 is very large. Control response is sluggish and no longer suitable for rapid load changes.
Assistance can be obtained by superimposing V-I control which has high-speed response to relieve the tachogenerator control loop and accelerate transient response by a considerable margin. Figure 25 shows a sample circuit for a bridge.
Superimposed V-I control can also be used with a real AC tachogenerator to improve the transient load response.
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Figure 24: The fastest current reversal is commutated and used as a substitute tachogenerator signal.
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APPLICATION NOTE Figure 25: Example circuit for a bridge.
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Processing the Tachogenerator Signal The control principle (figure 26) applied in pro-
Figure 26: P, I, PI and PIO controllers.
cessing the speed feedback and reference signals in a controlled system depends on a number of factors (table page 6).
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228
APPLICATION NOTE
The criteria governing the selection of a P controller, an I controller, a PI controller or a PIO controller .are ~s follows: .stability of the control loop, reaction time, transient response, load behavior, speed range and control factor. For example, if the reference signal is a frequency it would make sense to use an AC tachogenerator as the feedback value sensor and process both signals on a purely digital level. Powerful microcontrollers or digital signal processors are used.
In special cases that demand a control error of zero - for example, when two drive shafts have to be phase synchronized as well as running at
the same speed - PLL control is the only option. A system of this nature compares reference and feedback value for phase as well as frequency. In turn, of course, the AC tachogenerator must meet extreme requirements regarding phase stability since any jitter would be interpreted as a control error, producing a spurious response in the system.
PLL speed control systems are used in video recorders, floppy and hard disk drives and in a number of industrial drive systems. Figure 27 shows a typical PLL speed control circuit. The frequency comparator is phase comparator 2 of the HCF4046 CMOS PLL circuit.
Figure 27: Typical PLL circuit for controlling speed.
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APPLICATION NOTE
LOAD CURRENT SENSING IN SWITCHMODE BRIDGE MOTOR DRIVING CIRCUITS
by Herbert Sax
Switchmode drive circuits with pulse-width modulation control of the current are widely used in motor driving because they give the best performance. In such circuits it is important to sense the load current precisely. This note proliides practical solutions to this problem.
When it comes to controlling or driving electromagnetic actuators precise sensing of the load current is one of the key functions of any system. A switchmode bridge, however, does not lend itself to direct measurement of the load current in series with the actuator because the high common-mode levels that result from pulse-width modulation are far from conducive to low-cost measuring circuits. Even so, however, these problems can be overcome without resorting to costly isolating amplifiers. Most of the functions needed can be integrated in smart power circuits; some have already been implemented.
CURRENT CONTROL OF A DC MOTOR
In the final analysis, the voltage reference determines the complexity of a circuit for sensing the
load current of a DC motor bridge. The simplest arrangement calls for a measuring shunt at the common source pin of the lower branch of a power MOSFET bridge (Fig.1 A).
On virtually all the smart power bridges in widespread use this pin is accessible and is adequate for straightforward current limitation functions.
During the load inductor'S charge phase, the current that also drives the motor has no alternative but to flow diagonally to the shunt through the two transistors T1 and T2 and can therefore be sensed. Once the load current reaches its nominal value, it should be stored by the most efficient possible means.
The best way of achieving this aim is to short circuit the terminals, in other words to turn on transistors T2 and T3.
Figure 1A: Switch Mode Current Control Circuit for Load Current Limitation.(DMOS Bridge Configuration)
AN452/0392
115
231
APPLICATION NOTE Figure 1B: Switch Mode Current Control Circuit for Load Current Limitation.(Bipolar Bridge Configuration)
A significant difference now becomes apparent between the new DMOS smart power bridges (Fig.1 A) and the conventional bipolar configurations (Fig.1 B). Since active MOSFET transistors and their body diode are reverse conductive, the load current circulates in the lower circuit and is no longer accessible at Rs. Neither the bridge nor the controller circuit is at risk - always supposing that the current in the short-circuited free-wheeling circuit drops - and the circuit illustrated in Fig. 1A represents the classic solution for simple clocked current limitation functions.
BRAKING
When a DC motor brakes, the counter EMF it generates feeds the motor inductor. When the two lower bridge transistors T2 and T3 are ON and forming what amounts to a terminal short circuit the current increases rapidly to a value equal to EMF/RM.
Dangers arise if the short circuit current is allowed to exceed the maximum current rating of the bridge. Transistors having a large surface area can help avert damage, but they are costly irrespective of whether the board carries discrete components or smart power chips. It must also be borne in mind that merely short circuiting the terminals leads to a situation in which the motor's kinetic energy is largely converted into heat by the winding resistance, the time the motor needs to come to rest is uncontrolled.
SENSING THE BRAKING CURRENT
Consequently the aim must be to render the current measurable during braking. There are two approaches to this problem, both using current measuring shunts connected to ground on one side for the sake of simplcity.
The first arrangement is based on a bridge having interconnected source pins and will be described
below. The alternative is a circuit with two separate shunts in the source pins of the lower bridge transistors, as shown in Fig 2.
During the charge phase of the load inductor, the current that causes the motor to turn in a given direction flows diagonally through T1, T2 and RS1. In the free-wheeling phase T2 and T3 are conductive and the situation is as shown in Fig 1A. Despite the fact that during this free-wheeling phase the current is sensed as a positive voltage at RS1 and a negative voltage at RS2, the information is ignored because the current is dropping. This no longer applies in the braking phase, when the start-stop input goes low.
At this point a higher current in the free-wheeling circuit activates comparator camp 2. Through the equivalence circuit EC1, the comparator disables T3 and makes T1 go conductive, thus inverting the left side of the bridge for a maximum of one oscillator period. The kinetically generated energy of the counter-EMF stored in the motor inductor is returned to the power input (Vs). This process is repeated periodically.until the EMF divided by the motor resistance RM yields a braking current that is less than VREF/RS1. This controlled return of energy has one major advantage in that the braking current and thus the braking time can be influenced, while on the other hand, a large proportion of the motive energy is recovered and the winding resistance has to dissipate much less heat.
Sadly, however, the configuration shown in Fig. 2 is not feasible with all smart power bridges with DMOS power transistors. Not infrequently the source pins of the lower half of the bridge are interconnected on the chip, either because a limited number of pins are available or because the metal resistance would be too high. In cases of this nature the only resort is to connect two les in parallel and form a bridge from two half bridges. Of course this entails an additional advantage in that since conductive losses are lower, too.
2-/-5--------------------------- ~~~~~~~~:9~ -----------------------------
232
Figure 2: Same As Figure 1a but Including Braking Energy Recovery.
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APPLICATION NOTE
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SOLUTIONS FOR SERVO SYSTEMS
Circuits such as those shown in figs 1 and 2 are used primarily to protect the motor an? se~ico~ ductor bridge from overload. Torque limitation IS often another major concern in stepper motor drive systems and with DC motors. AlthouQh the current can be varied within adequate limits by varying the reference voltage, the tolerance factor becomes larger as the values become smaller because only one-sided peaks can be measured, Instead of mean values. If the current fluctuates close to or across zero, another strategy affording greater precision is needed.
Servo systems, being closed-loop control sy.stems with position and speed sensors, are heavily reliant on accurate current sensing In a form that is perfectly reliable in the current reversal ranQe close to zero. This further entails adopting a different drive strategy.
Since a short-circuited free-wheeling circuit in which both lower transistors are conductive would produce severe non-linearities in the current
Figure 3: Current Sensing by Reconstructor.
reversal range close to zero, it is to be avoided at
all costs. Free-wheeling in this case means selec-
tively inverting the bridge, thus causing the cur-
rent to drop along a largely linear path, b~t no
more than five to ten percent before the onglnal
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Since there are only two conductive states (either T1 and T2 or T3 and T4), the current always flo~s through Rs, irrespective of whether the circuit in-
corporates two separate shunts or one common shunt.
Fig. 3 illustrates the current curves and t~eir effect on the sense resistors Rs. Reconstructing the load current requires only an operational amplifier
that operates as a subtractor. Via resistor R1, !he capacitors suppress the peaks that occur d.unng changeover. Since the comm'!n-mode I.n.terference level is high, fast operational ampli.fl~rs
are the obvious first choice if high signal precIsion is required.
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APPLICATION NOTE Figure 4: Current Sensing in the Load Circuit.
Fig. 4 shows another circuit that is feasibl.e for all situations in Which, since they cannot be Inserted in the source circuit, the shunts have to be connected directly in series with the load, with all the disadvantages that this entails.
Although a single resistor suffices in theory, an operational amplifier provides· the speed and common-mode suppression characteristics that make it virtually the ideal choice. Nonetheless, the results can be improved considerably by sensing the current on both sides of the load. Since measurement is symmetrical, the useful signals and the sense resistors are added together, while the counter-phase edges are subtracted, thus significantly reducing the commonmode load on the operational amplifier. This is true in so far as the matrix resistors are capable of satisfying the very high requirements.
CURRENT RECONSTRUCTION
Bridges with a common source output show a~ interesting current pattern. The load current IS a positive signal during the charge phase of t~e coil, while it is negative in the in'(erted state, In other words during the free-wheeling phase. The only way to reconstruct this current is to periodically invert the sense voltage VRS.
Two of the many solutions to this problem are shown in Fig. S. The VRS signal is applied to the output alternately as a direct or inverted signal (Fig. SA), or the operational amplifier can ~ork in the inverting or non-inverting mode, depending on the position of the switch: In both ca~es lat~ral MOS transistors or even Simple smail-Signal bipolar transistors are perfectly adequate as switches. The RC filter at the output smooths switching peaks without distorting the time constant of the current control loop.
Figure SA: Recovery of the Load Current Map.(Directllnverted Solution)
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APPLICATION NOTE Figure 58: Accovery of the Load Current Map. (Inverting/non Inverting Solution)
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PRACTICAL EXAMPLE
Fig. 6 shows part of the circuit for a DC motor positioning system as use in a typewriter to control four movements. It consists of a controller circuit driving a smart power DMOS bridge with a single current sensing output.
Motor current can reach a maximum of 1A and is influenced by two control loops. The inner loop limits the current by positive or negative peak sampling of the reconstructed current information. An exclusive OR gate inverts the bridge phase for a maximum of one oscillator period, thus causing the current to change its direction. This loop is not delayed and therefore reacts very quickly. The second loop operates in a conventional circuit as a transconductance amplifier and converts an input error signal into a proportional current. If the difference between the measured value and the set point is large enough to force the error amplifier into saturation, the inner circuit limits the acceleration of braking current to the permissible
maximum.
POTENTIAL APPLICATIONS
The example circuits for sensing current and processing the signals shown in Figs. 1 to 6 are easily adaptable to other electromagnetic actuators that receive a bidirectional feed. Microstepping motors are a case in point, one in which inexpensive but nonetheless precise current control is very much desired by every user. As power MOSFETS in the guise of discrete components or smart power ICs become more popular, the techniques of sensing current in the source circuit either directly by means of shunts or in directly as sense FETs become correspondingly more important. The unavoidable errors caused by the base current of the bipolar transistors used to date thus become a thing of the past. Although the gate source capacitance remains a potential source of interference, its effect can be suppressed by analog or digital filters.
Figure 6:Part of a DC Motor Positioning Control Circuit.
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----------------------------- ~~~~;~~:~~g ----------------------------5/-5
235
APPLICATION NOTE
A SOLID STATE BLINKER FOR AUTOMOTIVE APPLICATIONS
by Sergio Ciscato
Using dedicated power ICs today it is possible to make a car blinker circuit without relays. The benefits are simpler cablinng and better reliability.
Present car direction indicator system generally use a dedicated integrated circuit as the SGSTHOMSON L9686 in conjunction with a relay to control the flashing of the lamps. A high current electromechanical switch is necessary to turn on the right or the left direction indicator lamps; to provide the emergency blinker feature a 3-pole power switch is needed too (see Fig. 1). The first disadvantage of this system is the high
Figure 1: Traditional System
number of power connections between the master module and the switches; in addition, the high currents flowing through the switches and across the relay contacts decrease their lifetime and consequently the reliability of the system. Thanks to smart power devices is is possible to implement a solid state car direction indicator system (see Fig. 2), that solves these problems.
Figure 2: New Solid State System
EMERGENCY
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APPLICATION NOTE
CIRCUIT DESCRIPTION
The control device in the. system described here is the L9686, but the relay is replaced by two L9821 High Side Drivers; this device delivers up
to 25A peak output current with RON = 100mQ,
short circuits and thermal protection.
When a power devices is turned on, the local supply voltage can drop several volt below its nominal value because of the line inductance. This voltage drop could cause disturbances to the control logic that in some cases could produce
Figure 3: Rising Edge of the Output Current
undamped oscillations on the suplly line itself. To avoid these oscillations and to prevent EMI disturbances, the L9821 was chosen as the power device in this applications because of a feature that limits the output current slew rate (dildt) during the switching edges. Fig. 3 and Fig. 4 show the rising and the falling edges of the output current of an L9821 device loaded with two 21 W lamps; the current level in the first case is higher than in the second one because of the inrush current of the bulbs (see Fig. 5).
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Figure 5: Output Current Waveform
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Fig. 6 shows the complete schematic diagram of t~e master mo~ul.e: when 81 is closed (left or right) the L9686 s Internal oscillator starts and pin 3 goes high; then the input voltage of one of the two L9821 devices goes high too, resulting in the lamps switching on. After a time equal to half of the oscillation period pin 3 of the L9686 returns low and the lamps are threfore switched off. The flashing cycle stops and the circuit is reset to the initial conditions when 81 is open. The flashing frequency depends on the external RC networkR1 and C1 according to the following formula:
Fn = 1/ (1.5 x R1 xC1 (typ.)
R3. a~d C2 provid~ hysteresis to avoid spurious sWitching of the oscillat?r comparator at every lamp :urn o~; thiS ~yster~sls .IS not necessary if the _9686 IS us.ed In conjunction with a relay, because )f the relatively long delay time of this last one. 'lshunt senses the current flowing in the right or the eft lamps (depending on the 81 position): when )ne of the I~mps is defective the voltage drop :!cross Rshun! IS reduced to a half and the failure is ndicated by doubling the flashing frequency. 82 :!lIows the emergency blinker function: when it is ;Iosed the L9686 device drives, through the diodes )1 and D2, both the L9821 smart switches and hen both the right and the left lamps.
rhe emrgency blinker operation is monitored by he flashing of both the dashboard lamps L1 and _2 while in normal operation only L2 flashes.
)VERVOLTAGE PROTECTION
\n L9821 device can withstand up to 60V load lump transient. If a centralized overvoltage pro-
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tection is not provided on the alternator it is possible to increase the load dump capability of this. application by placing a dedicated protection device, such as a Transil, between the supply voltage and the ground terminals. This transil must withstand the double battery, a condition often requested for the automotive equipment, so a good choice is a device with at least 26V breakdown Voltage. The same protection device allows the described application to withstand all the other voltage transients. If a centralized load dump protection device is already present on the alternator a small protection zener diode is sufficient to clamp the low energy overvoltage transients due to the disconnection of the several loads in the car. In this cas~ the breakd~wn voltage of the local protection device must be higher than the clamping voltage of the centralized diode.
ADVANTAGES Fig. 2 shows a possible wiring diagram of the described system in a car; the master module has 10 connections, compared to the four of the conventional system showed in Fig. 1, but from the comparison between the two possibilities we can see some advantages:
.. centralized wiring at the master module .. less power connections .. less power wire length .. no power switches .. no multipolar switch for the emergency blinker .. short circuit protection between the lamps and
ground .. inrush current limiting of the smart switches in-
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APPLICATION NOTE
REAR MIRRORS MULTIPLEXING USING L9946
by L. Valsecchi & S. Vergani
The application of the L9946 device in a real-world automotive multiplex system is described. After a brief introduction to the multiplex concept, the hardware and software key points are discussed. It turns out that L9946 is very we/! suited for this kind of relatively complex applications.
THE MULTIPLEX CONCEPT
In this section a brief introduction to the basic multiplex (MUX) concepts is given. Generally speaking, a MUX is composed by a number of units connected through a serial bus. There is a set of meaningful serial messages and each unit can recognise a subset of messages relevant to it. Once a relevant message is received, the unit performs an action according to the information contained in the message. Usually an acknowledge technique is used, so that a bidirectional information flow between units can be established. It is possible to draw a rough distinction between MUX systems based on the communication strategy. In increasing complexity order, a MUX can be classified as follows.
1) MASTER-SLAVE:
One unit is qualified as master unit, and it is the only one that can autonomously start a transmission. The other units (slaves) can transmit only after the reception of a message out of a defined set.
2) QUASI MULTI-MASTER:
As before, one unit acts like a master, but some slave units can start an autonomous transmission to the master. This happens usually when a significant event has occurred (e.g. a key has been pressed).However, the slave units cannot communicate each other directly. The messages flow is under the total control of the master unit.
3) MULTI-MASTER:
Every units can commuicate each other, and there is no more a well defined master unit.ln fact, the control, at a given time, is owned by the unit currently autonomously transmitting.
The format of the serial messages, as well as the characteristics of the physical interface of the bus line are defined by a series of rules called the PROTOCOL SPECIFICATION. These rules also
AN455/0392
define in details the behaviour of the transmitting and receiving units when a situation of bus contention (i.e. when two units try to access the bus simultaneously) occurs.
The ISO (International Organization for Standardization) has standarized, at various levels, three protocols called CAN, VAN, J1850. This means that documents exist as a reference to achieve the compatibility between two systems using the same protocol.
In fact, especially for slow speed data bus, custom protocols have been developed.
There are definite advantages in using a MUX system in the automotive field. First, the number of wires required to perform the same functions is dramatically reduced. For example,with the MUX approach, to connect a keyboard unit to other units such as window lift motor control, rear mirror control etc., only three (or four if a differential bus is used) wires are required, independently of the number of keys or motors used. This leads to a reduction of costs of the harness of the vehicle.
Flexibility is another feature common to well designed multiplex systems.
The multiplex architecture allows a high degree of freedom in the choice of the physical location of the units inside the vehicle. For example, as long as the serial bus line is provided, a control keyboard can be placed indifferently in the door or on the dashboard without changing the vehicle wiring.
Furthermore, if a certain computational power (i.e. a microcontroller) is located in the peripheral units, the functional behaviour of the whole system can be defined by software so that upgrading and modification can be accomplished without changing the hardware.
Also, a sophisticated diagnostic strategy can be implemented. Usually one or more units collect diagnostic information that can be read by a tester connected to the system when a car technical assistance is required. Such a tester generally includes a menu driven diagnosis procedure, lead-
1/8
241
APPLICATION NOTE
ing to easier fault detection and thus to shorter repair time.
REAR MIRRORS MULTIPLEX SYSTEM INTRODUCTION The application described here is an example of how the L9946 can be used as a mirror controller in a MUX system.
To explain in all the details a MUX system design is beyond the scope of this application note. However, the key points in hardware and software design will be discussed in depth.
GENERAL DESCRIPTION This MUX is composed by a keyboard unit, a left mirror unit and a right mirror unit. . The electronics is intended to be placed inside the external rear mirror case, and inside the physical keyboard. To achieve this, when possible, devices available in small SO package have been chosen. In this way, using surface . mounting technique, very compact PCB layout can be obtained. The three units are connected through a differential bus. Including power supply line and ground return, only four connection wires are required, obtaining a substantial saving compared to the traditional solution, that requires eight wires. The system block diagram is shown in fig. 1. The functions implemented are:
Figure 2: Mirror Unit Block Diagram
Figure 1: System Block Diagram
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- mirror plate movements - open I fold - wiper The commands available are activated by 6 push buttons located in the keyboard unit. An additional three-way selector allows to switch between the left or the right mirror. When this selector is in its central position, the only function available is a simultaneusly mirroropen/fold movement.
MIRROR UNIT DESCRIPTION The block diagram of the mirror unit is shown in fig. 2. The schematic diagram of the mirror unit is shown in fig. 3. The only difference between the left and right mirror unit is the position of a jumper that configures the address of the unit.
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APPLICATION NOTE
In the following sections the main functional blocks are described.
Protections The units must be protected against a number of possible anomalous voltages on the power supply line coming from the battery. This anomalous conditions are: 1} Reverse battery 2} Load dump 3} Short negative spikes
Voltage Regulator (L4949) This device provides the five volts necessary for the microcontroller and to the bus line interface. It also provides to the microcontroller the correct power on reset signal.
Microcontroiler (ST6210) The microcontroller (uC) choosenfor this application is the ST621 0(1 K8 EPRPOM, 64 bytes RAM).This is a 20 pin device, available in S020 package. The ST6 family is intended for low-medium complexity applications. The heaviest task for the uC in this, or similar, application is the protocol handling, i.e. the reception and the transmission of the serial messages on the bus. Due to the low computational power and speed of this uC, the protocol was chosen to be relatively slow (3.3 kbits/sec) and the bit encoding was chosen in such a way that the decoding algorithm is tailored to optimize the hardware uC resource usage. In this case the uC also drives the L9946 and protects it against overcurrent and/or overtemperature reading back the dignostic signals DG1 and DG2.
Figure 4: Keyboard Unit Block Diagram
Mirror Actuator (L9946)
The L9946 in this application is used to drive the four mirror motors: two. for the plate movements, one for the open/fold movement and one for the wiper motor. In this particular application the wiper can be driven by· the high-side driver thanks to a mechanical solution built into the mirror that performs automatically the wiper alternative movement.
Bus Line Interface
This is the circuitry that realize the physical interface between the unit and the bus line. Since the functioning of the whole system relies on the correctness of the exchanged messages, the bus line interface must be designed very carefully. A complete discussion of the needed design criteria is far beyond the scope of this application note.
A list of desirable features is:
a} High noise rejection
b} Line faults (short to GND or VCC, wire cut) detection and real time recover.
c) High RF noise immunity
d} Low RF emission
The solution implemented here is a differential bus line driven by two complementary MOS devices.
The passive components around the MOS polarize and protect the devices against shorts, spikes and negative voltages applied to the bus lines.
Capacitances placed on the bus lines filter out RF noise, also reducing the bandwidth'of the bus channel in order to avoid too sharp edges during bus transitions, i.e. RF emission and subsequently possible interferencies with other equipment (dash- /' board instrumentation, car radios etc.)
The three comparators in the RX section allow a full fault detection and recovery. This means that transmission and reception can continue also if one line is shorted to GND or Vce or cut.
KEYBOARD ~__V1 ST6210
TWO WIRES BUS
ff!l2RN4SS-B6
BUS LINE INTERFACE
4/8
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APPLICATION NOTE
KEYBOARD UNIT DESCRIPTION
The block diagram and .the schematic diagram of the keyboard unit are shown respectively in fig. 4 and fig. 5.
Many blocks in the architecture of this unit are very similar or identical to those used in the mirror unit.
This blocks are protections, voltage regulator and the bus line interface. The uC used is the same adopted in the mirror units.
A 4 X 2 matrix-organized keypad is connected to the unit. The schematic diagram of the physical keyboard is shown in fig. 6.
Since the physical keyboard rows and columns are directly connected to the uC pins, it must be placed very close to the electronics to avoid induced noise. A software debouncing strategy has Figure 6: Keyboard Schematic Diagram .
been implemented so that a key transition is validated only if the new state has been stable for at least fifty milliseconds.
SOFTWARE DESCRIPTION
Introduction
Two different programs have been written, one for the mirror units and one for the keyboard unit. The software was developed using the ST6 hardware emulator, and the ST6 macroassembler and linker. The mirror unit and keyboard unit programs are respectively about 1340 and 1280 bytes long. The main difficult in this software development was to overcome the uC limitations (using some software tricks) without affecting the overall program's readability.
.-----------~----------------~---M-IR-R-O-R---------~ (AIGREY SELECTOR
I WIPER Pi
I RETRACT P2
LEFT ~ RIGHT
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(BIUIOLET .--------r--~-------r--~--------r_~-------o
~ MIRROR DOWN
I P5
~~ MIRROR UP
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f192I1H4SS-8?
6/8
---------------------------
~~~~~~~~:~~
---------------------------
246
APPLICATION NOTE
Mirror Unit's Software Description
The software developed for this unit can be divided, at the functional level, into 3 main sections.
1) PROTOCOL HANDLER SECTION
This routines perform the serial bus message reception and transmission ..
The reception procedure starts when a vaiidSOM (see BUS PROTOCOL DESCRIPTION paragraph) is detected. The reception ends successfully when the following conditions are obeyed:
a)Ten correct bits (i.e. with the right timing between two edges) are decoded.
b)The received checksum field matches the checksum calculated upon the preceding eight received bits.
If an error occurs, the reception is aborted and the unit starts to wait for a new valid SOM.
The transmission routine starts when the unit must send a message on the bus line. The ST6 timer is used to obtain the desired time between the edges.
Keyboard Unit Software Description
In the sotfware for this unit the protocol handler section is the same code used in the mirror units.
The keyboard units acts like the master of the system.
The matrix keyboard is scanned every five milliseconds. If no key status variation is detected, every fifty milliseconds a stop message is sent to the slave units as a polling. The slave units should answer to this messages. If this is not the case, the master unit knows that one or both slaves are disconnected or broken.
When a key is pressed, a debouncing procedure is started. If the pressure remains at least for fifty millisecond the corresponding command message is sent to the unit selected by the position of the three-way selector.
If this selector is in its central position, only the fold/open command is enabled, and the subsequent command is sent to both slave units.
The keyboard unit keep sending the command until the key is released. Then, the normal nooperation polling is executed.
2) MESSAGES DECODING AND ACTUATIONS
This section performs the message decoding and the actual driving of the L9946.
Once a correct message is received, the mirror unit compares the received address field with its own address. If they are equal, the data field of the message is decoded and the corresponding action or series of actions are undertaken.
The data fields recognized by the mirror units and their meaning are:
a1110 : wiper on
10000 : wiper off
01010 : fold/open
00010: up movement
00100 : down movement
001 to: left movement
01000 : right movement
10010 : stop motors
Immediately after the action has started, the mirror unit transmits an acknowledge message to the master unit (i.e. the keyboard unit). This message is the echo of the acknowledged reception.
BUS PROTOCOL DESCRIPTION
1. GENERAL
The information between the units is passed in messages transmitted serially on the bus connected to all the units.
When the bus is in the idle state, i.e. no message is transmitted, its state is called "passive state". It is driven in the "active state" by a transmitting unit at the start of a message for the "start of message" time.The state is passive for the first (most significant bit) information time, active for the next bit time and so on until the message is finished (terminated) in the passive state. The value of the bit is determined by the time elapsed between two consecutive transition of the bus state. This bit encoding is called VPWM (variable pulse width modulation).
2. MESSAGE SYMBOL WAVEFORMS
The following sections show the nominal timing requirements of the VPWM message simbols generated by the software protocol handler as they appear on one wire of the bus. On the other bus wire the signal is inverted.
3) L9946 PROTECTION
The L9946DGl and DG2 pins are connected to uC interrupts lines so that a fast switch off is executed when an overcurrent or an overtemperature occurs in the device.
2.1. START OF MESSAGE
This symbol appears at the start of every mess-
age when a transmitter drives the bus in the ac-
11<-1___ ->l,1 tive state to start the message.
"SOM""
8:..::G.::.Bu=-:sc::.e.=.c_ _
t192AN4S5-01
________________________ ~~~~~~~~:~~ ___________________________7_/_8 247
APPLICATION NOTE
2.2. DATA BIT
Each data bit is represented by the time between two consecutive transitions. These are both passive and active bit states that are used alternately.
2.2. "0" BIT The two "0" bit waveforms are:
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n92f1N455-B2
2.3. "1" BIT The two "1" bit waveforms are:
-------.l.L· "1"
~ ~
~ 0 r
11<-.
48Busec
f132Aff455-B3
3. MESSAGE FORMAT
A message consists of a start of message (SOM) field, an address (ADR) field (3 bits), a data (DATA) field (5 bits) and a checksum (CHK) field (2 bits), for a total of 10 bits transmitted.
With the timing given in the above sections, the average transmission bit rate is 3.3 Kbps.
The SOM is the signal on wich every receiving unit starts the reception procedure.
Once a successful reception has been completed, the DATA field is decoded and the related action undertaken only if the ADR field matches with the wired address assigned to the receiving unit.
The CHK field is a way to detect some type of errors occurred during the DATA field bits transmission. During the reception procedure, a checksum value is calculated, and the reception is valid only if this value is equal to the contents of the received CHK field.
The algorithm used to calculate the checksum is the following.
a) Count the number of "1" bits in the DATA and ADR fields.
b) Take the two less significant bits of this number.
c) Complement these bits.
8/8
-----------------------------
~~~~~~~~:~~~
-----------------------------
248
APPLICATION NOTE
6A DOOR LOCK MOTOR DRIVER FOR AUTOMOTIVE
by Stefano Vergani
An application of the L9937 device (Full Bridge Motor Drive) is described. The interface between the L9937 and a j.lC is discussed. A complete protections circuitry description is also given.
Figure 1.
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The L9937 device is a full bridge for bidirectional motor driver applications realized in bipolar technology; it can deliver up to 6A output current with low saturation voltage. Two diagnostic informations are provided to monitor overload conditions and the internal temperature, and the device is assembled in the MULTIWATT-11 package with the case connected to the ground terminal. The L9937 is particularly suitable to drive bidirectional DC motors in j.lC based systems. Fig. 1 shows a possible application circuit, with an analog interface between the power devices and the j.lC.
AN456/0191
In the following, the functions of each block of the analog interface are described.
1 - Overvoltage And Reverse Battery Protection L9937 is particularly· suitable to drive the door lock motors in automotive applications. Fig. 2 shows the circuit schematics; due to the hostile automotive environment, it is necessary a transil (suggested type LDP24A) between VD and GND, to protect the L9937 against overvoltages higher than 50V. The diode D1 suggested type BY239200A) supplies the voltage VD necessary for the correct device's operation at the same time it protects the device against the reverse battery.
1/5
249
APPLICATION NOTE Figure 2
OF 11'11 IN2 EN
1192L993?-82f1
2 - Switch-off Sequence Referring to Fig. 2 and supposing i.e. T1 and T4 ON, T2 and T3 OFF (this means EN=H IN1=H IN2=L), the following steps have to be observed to allow a correct recirculation of the current in the motor at the switch off (Ref, Fig. 3):
a) switch off T1 and wait for 100llS about in this condition (EN = L IN1 = H IN2 = L)
b) after the a.m, delay switch ON T2 (EN = L IN1 = H IN2 = H)
c) switch off both T2 and T4 after the motor stop (EN = L IN1= L IN2 = L)
Step a) allows the recirculation of the motor cur-
Figure 3: Switch-off Sequence
· TURN-OFF
rent due to the inductive component of the motor itself between DS1 and T4; the 100llsec delay
time is needed to avoid the cross-conduction in the left half bridge. In step b) the motor is short circuited to GND (T2 and T4 ON) and this allows the dynamic braking.
In step c) T1, T2, T3 and T4 are OFF to allow a very low current consumption of the bridge. If the dynamic braking is not requested, step b) can be omitted. In any case the lower power tran-
sistor of an half bridge must be kept ON, after the switph off of the upper transistor of the other half bridge, for a time longer than T = 5 ',RLlLL, where RI and LI are the resistance and the Inductance of
the load.
EN .......... lJ...-___________+ t
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BRAKING
~.~:~:.~-~~----~.:
11!J2L993?-B3
_2/_5_________________________ L~1 ~~~~~:oo~~-----------~------------
250
3 - Input Driving Voltage To allow a correct operation of L9937 over the full t~mperature ra~ge, the driving voltage at the input pins must be higher than 5.5V, with 4mA current capability.
4 - Short Circuit Protection It is possible to protect L9937 against short circuit to ground and across the motor in the full bridge application. The circuit schematics shown in Fig. 4 uses two voltage comparators (U1A, U1B) to detect the Vce of the upper power transistors. U2A and U2B are open drain NAND gates (Le. part no. HCC40107) and U3A1B/C/D are non inverting buffer to drive the L9937 (Le. part no. 74HC4050). U1 A and U1 B sense the differential voltage VDOUT2 and VO-OUT1 respectively. Referring to Fig. 4, chosen R1=100K and R2=20K, the values of R3 and R4 may be calculated according to the following formula:
R3 = (Vo- VCETH) - 0.166 Vo) * R4
0.166Vo
where:
Vo = bridge power supply VCETH = collector to emitter detection threshold.
Figure 4
APPLICATION NOTE
Choosing:
VCETH = 2V @ Vo = 12V and R4 = 1K, the above formula gives R3 = 4K.
When al~ signals from IlC are at low level (motor
off), the Inputs to the bridge are low too' in these
conditions the output voltage of the two bompara-
tors is high and therefore the outputs of U2A1U2B
are free. yvhen the fIC sends, for example, IN2
and EN high, OUT2 of the bridge goes high and
OUT1 goes low.
~t this point the output of U1A pulls down the
Input of U2A before that the delay capacitor C1 is
c~arged (through R5) up to the U2A threshold; in
thiS way the U2A output remains free and the
bridge drives the motor.
If a short circuit occurs, the Vce of the upper
power transistor increases above the threshold
and then the U2A output pulls down the enable
input of L9937. At the SOME time the SC signal
to fIC, high in normal conditions, goes low; at this
point the fIC executes the switch-off sequence.
We have just explained what happens when a
short circuit occurs during the motor running
phase. Another faulting condition occurs switch-
!ng (:In the bridge. whe~ a short circuit is present;
In thiS case the bridge IS driven for a time depend-
ing on the time constant R5 · C1 = R6 · C2.
Choosing R5 = R6 = then the time constant
3.3K and C1 = C2 will be T = 3.3fIsec,
=th1ant Fi~
5~sec about delay time. Longer delay time
might allow the short circuit current to reach
values beyond the absolute maximum ratings.
!--_t_-oUOO
11!12L!1!13?-84f1
TO L9937
____________ -------------L'11 ~~~~~gr::oo~lt
..:.31-..:,5
251
APPLICATION NOTE
5 - Thermal Protecti.on
The L9937 has 5 built-in diodes series-connected
that can be used to implement a thermal protection for the device. Fig. 5 shows the relationship between the voltage across the diodes and the temperature at 1OO~A diode current.
Figure 5
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1185L5536 -81
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..............
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2 -58 -25 8 25 58 75 188 125 · C
Fig. 6 shows the simplest solution to do a thermal protection; an AID converter of the ~C is used to detect the voltage drop across the 5 diodes. The 15K resistor sets the current in the diodes and the 1OOnF capacitor acts as a filter against the noise. When the ~C detects a voltage lower than the low threshold chosen according to the diagram in Fig. 5, it executes the switch-off sequence and rejects any command to the bridge until the diodes voltage increases beyond the high threshold. The recommended hysteresis value is 30'C.
Figure 6
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N92L993?-B511
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R3 and R4 (left side and right side) in Fig. 4; C is connected to the node between R1 and R2 in Fig. 4).
When Vo reaches 18V the comparator output pulls down A and 8, causing the intervention of the hardware protection showed in Fig. 4; atthe same time the OVV signal is sent to ~C, which executes the switch off sequence. The ~C must reject any command to the bridge during the overvoltage conditions. With the values shown in Fig. 7, a 1V hysteresis
is provided. It is possible to enhance the performances of the system just described avoiding the braking of the motor also for short duration voltage transients; to do this the ~C, once received the overvoltage diagnostic signal (OVV), put at low level the enable of the L9937, confirming the hardware switch-off of the motor; in this condition an output
of the half bridge is in high impedance state and the other one is low, allowing the recirculation of the current and the free running of the motor.
The system holds this condition until OVV is active; when the OVV signal is released the ~C
resets the hardware protection, sending EN = IN1 =
IN2 = L and then restore the previous command to
the bridge. It is mandatory, however, to wait for the complete current recirculation of the motor before to reset the hardware protection; in facts, when EN = IN1 ~ IN2 = L both the L9937 outputs are in high impedance conditions.
7 - Diagnostic Feedback Output
6 · Overvoltage Protection
At point 1 we suggest a way to proted the L9937 against the voltage transients. This protection allows the device to withstand overvoltages only if the bridge is not operating. To protect the device against the overvoltages in all the operating conditions it is possible to implement the circuit shown in Fig. 7.
DF piri is an open drain output to monitor overcurrent and overtemperature conditions.
The overcurrent detection threshold is inversely. dependent from the temperature of the chip. Typical application of this function is to send the DF signal, with an external pull-up to Vcc, to a digital input of the ~C; when the DF signal goes at low level, the ~C executes the switch-off sequence.
(Note: A-8 are connected to the nodes between
-4/5------------- L", ~~~~m~r::oo~::-------------
252
L9937 IN A BODY MULTIPLEX ENVIRONMENT All the functions described above can be implemented in a custom integrated circuit together with a bus transceiver and a protocol handler.
Figure 8: "Class A" Wired Peripheral Application
APPLICATION NOTE
It is then possible to obtain a very small size module that 'can be integrated directly in the actuator. Fig. 8 shows a typical application of these modules as peripheral units in a "Class A" wired Multiplex System,
............... --- ..... .
ANALOG INTERFACE BUS RXITX PROT.HANDL.
ANALOG INTERFACE BUS RXITX PROT.HANDL.
ANALOG INTERFACE BUS RXITX PROT.HANDL.
1f92L993?-B?
BUS
-------------- --------------L"fl ~~~;~~::O!~n
5/5
253
APPLICATION NOTE
INTRODUCTION
Driving DC motors with integrated circuits seems at first to be rather simple. Yet by analyzing the actual application it is possible to see if there exist conditions causing stresses to the IC during operation which in the end can cause failure. With proper de-
Figure 1.
DRIVING DC MOTORS
By G. Maiocchi
sign and analysis in critical applications it is possible to avoid conditions which lead to IC damage.
GENERAL CONSIDERATIONS Figure 1 illustrates driving a DC motor using a power MaS bridge.
Us
TO THE CHOPPING CONTROLLER ---~
CURRENT DIRECTION
-----. Cl.C4.0N C2.C3.0FF +- - - C2. Q3.0N C1. C4.0FF
N89L6283-12
By driving the four MaS in the correct sequence the direction of current flow through the motor is reversed, consequently reversing the direction of the motor's rotation. The motor torque is a function of the current amplitude, the motor's internal parameters, and the external load. The resistive torque is dependent on the motor's internal friction. The current level can be controlled with current chopping. The controller checks the current level by monitoring the sense resistor voltage and then drives the appropriate power MOS. On the other
hand this means that when current does not flow in the sense resistor (which we will examine during recirculation) it is not possible to measure the current level and thus limit it. Figure 2 shows a more general application circuit which includes an external control loop. Data relating to the actual motor speed is transmitted to the controller by the system which stabi!izes the current in the bridge as a fun,ction of the requested rotation velocity. In this case also the current is limited through chopping.
AN281/0189
1/8
255
APPLICATION NOTE
Figure 2.
DRIUE (
OUTPUT
CONTROLLER
FEEDBACK (
INPUT
11'11 OUTt 11'12 EN OUT2 CURRENT FEEDBACK
Rs
1189L6283-13
SPEED FEEDBACK
Electrically a DC motor can be viewed as a series RL network with a voltage generator V(ro). The generator represents the back electromotive force (BEMF) generated by the motor's rotation and which opposes the electromotive force of the supply.
The value of the BEMF is a function of the motor's angular velocity. If the motor has no external load and its velocity is not limited, it will accelerate up to the velocity w such that V(w) equals the supply voltage Vs. In this situation the two EMF's cancel each other and thus the motor torque responsible for acceleration will go away. In reality V(ro) is always slightly less than Vs in which case a small motor torque is necessary to compensate resistive torque due to internal friction.
Thus it can be seen that the motor's BEMF can reach elevated values which in some cases can cre-
Figure 3a : Two Phase Chopping.
ate application problems due to a certain type of stress.
RECIRCULATION CURRENT
Part of the energy delivered to the circuit by the supply is stored in the motor's inductance. When an inductive load is driven, during chopping and during inversion of the diagonal of the bridge, there is always some. recirculation current which allows this energy to discharge.
The following figures show the resulting current paths based on the type of chopping method used. In the first two cases, "two'phase" and "enable" chopping, the current decays quickly and, is thus, fast recirculaiion. When "one-phase" chopping is implemented the current requires a longer time period to decay and, is thus, slow recirculation.
2/8
256
Figure 3b : Enable Chopping.
APPLICATION NOTE
~o.,
~-----t--
Figure 3c : One Phase Chopping.
~".,
'--------+--
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IN1 =H
IN2 =H EN =H
~.,
DYNAMIC BEHAVIOUR
The driving of a DC motor will be analyzed dynamically during different motion phases. Fundamental to the working conditions of the IC is the type of load which the motor is driving. In fact if the load is frictional, the deceleration phase is not particularly serious for the IC since the load itself is supplying a braking torque. However, when the load is inertial it will appear to the IC to be a motor torque generator.
This could take the IC into critical operating conditions which can incur failure.
- Acceleration Phase: The current rises, delivering a torque which allows the motor to accelerate, up to the maximum velocity or till it is stabilized by the controlloop. The type of load essentially determines the required current.
-Constant Velocity: In this case the required velocity is less than the maximum. The current is limited by chopping. This can be done by turning ON and
OFF a MOS of the diagonal which is in conduction.
- Deceleration: When a DC motor must be decelerated, the type of load being driven becomes important. As previously stated, in the case of a frictional load, the load is essentially braking the motor. Thus, in general, it could be sufficient to cancel the motor torque by opening the bridge (i.e. disable the driver). In the case of an inertial load, however, the braking torque is provided by the driver. It is this situation that is of most concern. Since every change of direction involves a braking phase, a detailed analysis of this situation will be done.
ROTATION INVERSION
Initially the current flows in one direction as shown in figure 4. Figure 5 illustrates the situation when the diagonal is switched. The motor's inductance discharges the stored energy by fast recirculation through diodes D2 and D3.
3/8 257
APPLICATION NOTE Figure 4.
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o~
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The inertial load of the motor, which can be viewed as a flywheel, has stored energy during the phase prior to inverting the diagonal. This energy is reo turned to the motor providing a motor torque which keeps the motor rotating. Greater still is the fly· wheel's moment of inertia, greater than the motor torque that it provides to the motor. The discharge time is longer because the flywheel must discharge its energy. Also associated with the motor's rotation is the BEMF. Thus, in order to stop the motor a brak-
Figure 6.
ing torque must be applied. This is generated when, following completion of slow recirculation, the current begins to flow in the opposite direction from the previous state.
It is precisely at this point which effectively the braking phase begins. When the sense voltage rises to the preset level chopping is triggered. In figure 6 chopping results in slow recirculation (in practice the motor is short-circuited).
Us
~F
D~
NB9L62B3-16
4/8
258
APPLICATION NOTE
As it can be seen, the BEMF is dropped across the relatively low resistances of the motor, the diode in line and the MOS that is ON. The sense resistor does not enter into this. If the motor's rotational velocity remains high the recirculation current could be very large, enough to damage the IC. Actually the current does not rise instantaneously to the steady state value of : I = V(m)/(Rm + Rd + Rdson). Rather, the current follows the graph shown in figure 7. In fact, when chopping begins the sense current goes to zero, thus tuming MOS M2 ON again~ The motor current flows through the sense resistor, re-enabling the
Figure 7.
chopping. The cycle repeats in an iterative manner with a recirculation current that continues to rise. Due to the inertial load and the BEMF it generates and the recirculation current as described above, the current in the sense resistor will be greater than the desired value set by 1m = Vref/Rsense. When the current reaches the maximum level (see previous paragraph) the current will fall to the preset level controlled by the chopping, the inertial load having discharged its energy from the previous phase. This elevated current level is temporary, but can be damaging to the IC.
I
I
I I
I
I I
II II
II II
II II
II II
II II
II II
II II
I I I
I I
.... ~
t
t.t
f189L 6283 - 1?
[caption for figure 71 I = recirculation current
delta t =time interval during which current flows through Rsense.
Braking the motor by short-circuiting it involves an accurate study of the mechanical system during the design phase. Knowing the value of the BEMF generated by the motor during braking, the motor resistance, and the equivalent resistance of the
MOS and diode involved during recirculation it is possible to determine the recirculation current and if it is less than or greater than the maximum value that the IC can tolerate.
5/8
259
APPLICATION NOTE Figure 8.
Us
DIRECTIDNS~~;========1)-1-_ _i - 1 >
ENABLE
+5V
n89L6283-18~
If the recirculation current is too high it will be necessary to brake the motor with an alternative method. Using fast recirculation in combination with slow recirculation it is possible to brake the motor. Even if this is less than an efficient manner it avoids causing damage to the IC due to overcurrent. The basic circuit is shown in figure 8. Figure 9 is the application circuit which the Application Lab of Agrate, experimented with. This circuit uses an L6203 as the power driver. As seen in figure 8, as long as the recirculation current does not reach too high a value slow recirculation is used (one-phase chopping). Above a critical threshold slow recirculation is replaced with fast recirculation achieved by enable chopping. The slow and fast recirculations are triggered by two different reference voltages which determine the two current level thresholds. The higher current level for triggering fast recirculation is set little below the max current level available by the IC.
Figure 10 is the current waveform observed on the oscilloscope during few diagonal inversions. In this figure we can see the general trend of the motor current during three inversions of the rotation. A more detailed view of what really happens to the motor current is showed in fig. 11. Before the rotation inversion the motor is sinking its steady state current
(about ±250mA in this application, the sign depend-
ing from the current flow direction). At the rotation inversion, first the current rises, as previous described, to the current level defined by Iref2. At this moment ENABLE chopping is activated starting the fast recirculation and the current level is clamped at this reference current level. When the motor has dissipated a sufficient rate of its inertial energy, the current falls down, first to the level defined by Iref1 (slow recirculation) for all that interval time that is required to dissipate the remaining inertial energy and then to its steady state working level.
6/8 260
Figure 9.
uc:c-su
APPLICATION NOTE
Us,,35Umax
DIRECTION
U5pced=2Umax Speed ENRBLE
ION/OFF)
Uc:c .. 5U
R1 2.2K
:J: 3.3nF
14 Ref 1
4
12
L6585
2
13
5
IN 1
3
11 EN
7 IN 2
")
J" " "
3
19 R4
L52B3
18K
17
15 R3 18
lBK R5
15nF D2
8.SQ
6
ffBBL6283-S6
Figure 10. VERT.2NDIV HOR.100ms/DIV
Three diagonal inversion of a unloaded DC motor
This scheme prevents damage to the IC due to overcurrent. However, failure due to overvoltage is still possible. An inertial load will return energy to the supply. If the power supply is the type which cannot sink current but can only source current, then the eflergy from the motor will load the power supply capacitor to a voltage above Vs. If the capacitor value is not large enough, during recirculation the capacitor voltage will rise rapidly. Meanwhile, the lower ac-
tive diode is below ground during recirculation. .There is a differential voltage between the overvoltage and the point below ground. If this exceeds the absolute maximum voltage of the IC, damage can occur. Overvoltage can be limited with an appropriate value of power supply capacitor. For the below ground condition of the lower diodes, the sources of the upper MOS can be clamped to ground with schotky diodes.
7/8 261
APPLICATION NOTE
When Vs is relatively low it may be sufficient to control the differential voltage drop by just limiting the overvoltage with the power supply capacitor and not
Figure 11.
having to use the schottky diodes. The feasibility of this solution should nevertheless be verified experimentally in the specific application.
" , , IMOTOR
IMAX
I "
",/
TENOENTIAL TREND
IR EF2
vrv -~
I REFl
V
II
-"'"
CLOCK
t
NB9L62B3-19
8/8
262
APPLICATION NOTE
APPLICATIONS OF MONOLITHIC BRIDGE DRIVERS
High power monolithic bridge drivers are an attractive replacement for discrete transistors and half bridges in applications such as DC motor and stepper motor driving. This application guide describes three such devices - the L293, L293E and L298 - and presents practical examples of their application.
The L293, L293E and L298 each contain four pushpull power drivers which can be used independently or, more commonly, as two full bridges. Each driver is controlled by a TTL-level logic input and each pair of drivers is equipped with an enable input which controls a whole bridge. All three devices feature a separate logic supply input so that the logic can be run on a lower supply voltage, reducing dissipation. This logic supply is internally regulated.
Additionally, the L293E and L298 are provided with external connections to the lower emitters of each
bridge to allow the connection of current sense resistors. The L293E has separate emitter connections for each channel ; the L298 has two, one for each bridge.
Figure 1 shows the internal structure of the L293, L293E and L298. The L293 and L293E are represented as four push pull drivers while the intemal schematic is given for the L298. Though they are drawn differently the L293E and L298 are identical in structure; the L293 differs in that it does not have extemal emitter connections.
Figure 1 : The L293, L293E and L298 contain four push pull drivers. Each driver is controlled by a logic input and each pair (a bridge) is controlled by an enable input. Additionally, the L293E has external emitter connections for each driver and the L298 has emitter connections for each bridge.
ENABLE A INI OUTI
OUT 2 IN 2
v.
L293 16
ENABLE A IN,
V55 IN4 OUT4
OUT' SENSE'
S-!l792
OUTl INl
ENABLE B
SENSE 2 OUT 2
IN2 V.
S-!l661
Vss IN 4
OUT 4 SENSE 4
SENSE 3 OUT 3
IN 3 ENABLEB
AN240/1288
1/10
263
APPLICATION NOTE Figure 1 (continued).
12
In4
In3 EnB
The L293 is packaged in a 12 + 4 lead POWERDIP package (a 16-pin DIP with the four center leads used to conduct heat to the PC board copper) and handles 1A per channel (1.5 peak) at voltages up to 36 V.
The L293E, also rated at 1 N36 V, is mounted in a 16 + 4 lead POWERDIP package. A 15-lead MULTIWATT plastic power package is used for the L298N which handles up to 2A per channel at voltages to 46 V.
All three devices includes on-chip thermal protection and feature high noise immunity. The high switching speed makes them particularly suitable for switch mode control.
PARALLELING OUTPUTS
Higher output currents can be obtained by paralleling the outputs of both bridges. For example, the outputs of an L298N can be connected in parallel to make a single 3.5 A bridge. To ensure that the current is fairly divided between the bridges they must be connected as shown in figure 2. In other words, channel one should be paralleled with channel four and channel two paralleled with channel three. Apart from this rule the connection is very straightforward - the inputs, enables, outputs and emitters are simply connected together.
The outputs of an L293 or L293E can also be paralleled - in this case too channel 1 must be paralleled with channel 4 and channel 2 with channel 3.
But if two bridges are needed this is not a good idea because an L298N may be used. However, if only
Figure 2 : For higher currents outputs can be paralleled. Take care to parallel channel 1 with channel 4 and channel 2 with channel3.
Vs
Vss
IN! IN Z
5-5873/2
2/10 264
APPLICATION NOTE
one bridge is required an L293 connected as a single bridge may be cheaper than an underutilized L298N.
SHORT CIRCUIT PROTECTION
L293 and L298N drivers can be damaged by short circuits from the output to ground or to the supply. Short circuits to ground are by far the most common and can be protected against by the circuit shown in figure 3. When the output is short circuited the input is pulled
low after a delay of roughly 10 ~s, a period determined by the RC time constant. The upper transistor of the output stage is thus turned off, interrupting the short circuit current. When the short is removed the circuit recovers automatically. This is shown by the waveforms of figure 4.
Note that if the short circuit is removed while V1 is high the output stays low because the capacitor C is charged to VIH. The system is reset by the falling edge of V1, which discharges C.
Figure 3: This circuit protects a driver from output short circuits to ground.
R:l0Kn
Figure 4 : Waveforms illustrating the short circuit protection provided by the circuit of fig. 3.
J)r v ooce Tsc ~l0.us
~==O~L _---LI_+====VOL=====I
t
SHORT CIRCUIT
SHORT CIRCUIT REMOVED
_ ~ ~B65
DC MOTOR DRIVING
In application where rotation is always in the same sense a single driver (half bridge) can be used to drive a small DC motor. The motor may be connected either to supply or to ground as shown in figure 5.
The only difference between these two alternatives is that the control logic is inverted - a useful fact to
remember when minimising control logic.
Each device can drive four motors connected in this way. The maximum motor current is 1A for the L293 and 2A for the L298N. However if several motors are driven continuously care should be taken to avoid exceeding the maximum power dissipation of the package.
3/10
265
APPLICATION NOTE
Each motor in this configuration is controlled by its own logic input which gives two alternatives : run and fast stop (the motor shorted by one of the transistors).
The enable/inhibit inputs also allow a free running motor stop by turning off both transistors of the driver. Since these inputs are common to two channels (one bridge) this feature can only be used when both channels are disabled together.
A full bridge configuration is used to drive DC motors in both directions (figure 6). Using the logic inputs of the two channels the motor can be made to run clockwise, run anticlockwise or stop rapidly..
Figure 5 : For rotation in one direction DC motors are driven by one channel and can be connected to supply or ground.
Figure 6 : A bridge is used for bidirectional drive of DC motors.
c
+Vss
L_-'===:;:::;:;;:;;;:::;;~=:f--D Vinh
s- 5165
.L4.5,12 ,13
A.
I 16 +Vss I
L_---.:==::;:::=:;::::~===:f--OVinh
5-5163/1
Vinh A
M1
B
M2
H H Fast Motor Stop H Run
H L Run
L Fast Motor Stop
L
X
Free Running Motor Stop
X
Free Running Motor Stop
L = Low
H = High
X = Don'l Care
Again, the enable/inhibit input is used for a free runni[lg stop - it turns off all four transistors of the bridge when low. A very rapid stop may be achieved by reversing the current, though this requires more careful design to stop the motor dead. In practice a tachometer dynamo and closed loop control are usually necessary. Like the previous circuit, this configuration is suitable for motors with currents up to 1A (L293/L293E) or 2A (L298N).
The motor speed in these examples can be controlled by switching the drivers with pulse width modulated squarewaves. This approach is particularly suitable for microcomputer control.
For undirectional drive with a single channel. the
Inputs
Function
C = H ; D=L Turn Right
Vinh = H C = L; D=H Turn Left
C=D
Fast Motor Stop
V inh = L C =X; D=X Free Running Motor Stop
L = Low
H = High
X = Don't Care
PWM control signal can be applied to either the channel input or the appropriate enable input. In both cases the recirculation path is through the suppression diode and motor, giving a fairly slow decay. From a practical point of view it is preferable to control the channel input because the circuit response is faster. This is very convenient because each channel has an independent input.
The situation is different for bidirectional motors driven by a bridge. In this case the two alternatives have different effects. If the channel inputs are driven by the PWM signal, with suitable logic, the re~ circulation path is through a diode, the motor and a ~ransistor (figure 7a), givind a slow decay. On the other hand, if the enable input is controlled the recirculation path is from ground to supply through two diodes and the winding. This path gives a faster decay (figure 7b).
Figure 8 shows a practical example of PWM motor speed control. This circuit includes the oscillator and modulator and allows independent regulation of the speeds of the two motors. The channel inputs are used to control the direction.
An interesting feature of this circuit is that it takes advantage of the threshold of the enable/inhibit input to economise on comparators. The TBA820M audio amplifier generates triangle waves, the DC
4/10
266
APPLICATION NOTE
level of which is varied from a to 5 V by means of
P1 and P2.
Since the switching threshold of the L293's enable/inhibit inputs is roughly 2 V the duty cycle of the output current (and hence the motor speed) is controiled by the setting of the potentiometer.
In this circuitthe switching frequency is set by R1/C1 and the amplitude of the oscillator signal is set by the divider R2/R3.
Figure 7a : If the current shown by the solid line is interrupted by bringing A low the current recirculates rou nd the dotted path. Decay is slow.
Vs
A ---.----/
INH --~--------++---------~
Figure 7b : If the enable input is brought low to interrupt the current indicated by the solid line the current recirculates from ground to Vs and the decay is faster.
A-_--;
J----<t--- 8
INH --~-------+++---------~
5110
267
APPLICATION NOTE
Figure 8 : This circuit illustrates PWM control of the motor speed. The speed of each motor is controlled independently.
05 O.ZZ,uF
THRESHOLD
\~.5vpp
Vp1
triangle
.......... 18 KHz
s - '16311
STEPPER MOTOR DRIVING
Monolithic bridge drivers are extremely useful for stepper motor driving because they simplify the use of bipolar motors. This is an important point since a bipolar stepper motor costs less than an equivalent unipolar motor (it has fewer windings) and gives more torque per unit volume, other things being equal.
The basic configuration for bipolar stepper motor driving is shown in figure 9. In this example it is assumed that a suitable translator (phase sequence generator) is connected to the four channel inputs.
Either an L293 or an L298N can be used in this circuit ; an L293E would be wasted compared to an L293 because load current regulation, and hence the sense resistor connection, is not used.
But load current requlation is highly desirable to exploit the performance characteristics of the motor. Using an L293E or L298N this can be implemented
by adding an LM339 quad comparator as shown in figure 10.
This is another circuit that requires an external translator but .it provides independent PWM chopper regulation of the current in each winding.
Looking at motor phase one, the comparator output is initially high, enabling the bridge through pin 1.
The current in the motor winding rises until the voltage across the sensing resistor R2 produces a voltage at the inverting input of the comparator equal to the voltage on the non-inverting input (370 mY). This value is produced by the divider R1 O/R 11 and by the hysteresis determined by R6 and RB.
At this point the comparator switches, disabling the bridge. The current in the winding recirculates through 05 and 06 until the voltage across R2 falls below the lower threshold of the comparator. The comparator then switches again and the cycle repeats.
6/10 268
APPLICATION NOTE
Figure 9 : A single device can be used to drive a two phase bipolar stepper motor.
06
02
The peak current in each winding is determined by Vret (in this case it is 0.5 A) and the switching rateand hence the average current - depends on the hysteresis of the comparator and R4C4. With the component values shown the switching frequency is roughly 20 kHz. The figure 10 circuit uses only half of the LM339 quad comparator. With the adition of a few extra passive components we can take advantage of the spare comparators to implement short circuit protection. Figure 11 shows how this is done. As before, comparators 1 and 2 regulate the current in the windings but in this case the connection is different because the inhibiVenable inputs are used for the short circuit protection. The PWM choppers act on the channel inputs through the four clamp diodes 09, 010, 011 and 012. This is a simple trick which allows us to use the channel inputs both for the step sequencing and the choppers. Comparators 3 and 4 realize the short circuit protection function. Again looking at phase one, compara-
tor 3 operates as a flip flop. Its output is connected to the bridge enable inputs (pins 1 and 11) and is normally high, enabling the drivers. If the output current (sensed by RS1) reaches double the nominal value the comparator CP3 switches, inhibiting the two bridges.
The comparator remains in this state until the Vss supply (5 V) is interrupted. The outputs of comparators 3 and 4 are ORed together so that a short circuit on one phase disables both bridges.
For this circuit VA should be less than 300 mV (VA is the voltage on the + input of CP1). From the value chosen for VA and the desired phase cu rrent the sense resistor RS1 (and RS2) is chosen. The current ripple should be at least 30 mA to avoid spurious triggering of CP1 and CP2.
The component values indicated are for a motor with a resistance of 37 Q/phase, inductance of 80 mH/phase and a current of 280 rnA/phase. Vret is
243 mV giving VA = 274 mV when the output is high
and 243 mV when the output is low. Since RS1 = 1 Q. the current is the winding reaches 274 mA peak and has a ripple of roughly 30 mA. The switching frequency depends on the hysteresis of the comparators and the motor characteristics. For this example the frequency is about 15 kHz.
Stepper motor drive circuits can be simplified using the L297 stepper motor controller which contains a translator to generate the phase sequences plus a dual PWM chopper to regulate the phase currents.
The L297 connects directly to the L293E or L298N as shown in figure 12. This example drives a bipolar stepper motor with winding currents up to 2.5 A. For lower currents an L293E is used and more powerful motors can be driven by two L298N's with paralleled bridges, giving up to 3.5 A.
In this configuration the motor is controlled through the L297. A step clock moves the motor one increment, the CW/CCW input controls the direction and the HALF/FULL input selects half step or normal operation. The input Vret is connected to a suitable voltage reference and sets the peak winding current in the motor. The choppers in the L297 can operate on the phase lines or the inhibit lines, depending on the state of the logic input called CONTROL.
For a more detailed description of the L297 see "Introducing the L297 Stepper Motor Controller".
7/10 269
APPLICATION NOTE Figure 10: Two comparators provide chopper current regulation in this bipolar stepper motor drive circuit.
c' 0.' pF
J:
cfOO t'F
i
0 "'Vs
L293E
::I:
20
+ 5V
l _ _ _ _ _-+-_--f'O
11
4.7Kfl
'--_ _ _ _ _ _....
56ll Rl0
5- 4 869/1
8/10
270
APPLICATION NOTE Figure 11 : With a quad comparator both current regulation and short circuit protection can be obtained.
r-----------------------------------------------------~--------._--~~~.v.
v,~_._+------------------_f~_,
02
0'
~---------------+~--4_----------~.5V r-~t-----------------4_~--+__.---------Ov.
05
04
03
07
'--11---_ _ _ _+_-1'0 l293E
11
.sv
10KA R5
R9 10Kfi
9/10
271
APPLICATION NOTE
Figure 1.2 : An L297 stepper motor controller and a L298N driver together from a complete microprocessorto-stepper motor interface. This circuit drives bipolar stepper motors with winding currents up to 2 A.
5V
36V
R
3.3
C nF
:::I:
OSC 16
12 A 4
DI
9 5
B
4 2
01
CLOCK 18
HALF/FULL 19
RESET 20
L297
B 6
C
9 D
10
3 02
L298N
12
13 03
ENABLE Vref
10
15 11 1
INH 1
5
6
8 iNHi 11
SENSEI SENSE 2
14°4 15
D5
CONTROL
HOME
SYNC.
Rsz
RS1 R Sz =0.Sfi 01 toDS = ZA FAST DIODES
D2 D3 D4
STEPPER MOTOR
11 WINDINGS
D6 D7 D8
S-~84611.
10/10 272
APPLICATION NOTE
SPEED CONTROL OF DC MOTORS WITH THE L292 SWITCH-MODE DRIVER
Power dissipation in DC motor drive systems can be reduced considerably with an L292 switchmode driver.
This application guide describes two speed control systems based on this device; one voltage controlled
and one controlled by a 6-bit binary word. Both examples are designed for 60 W motors equipped with tacho
dynamos.
The L292 is a monolithic power IC which functions effectively as a power transconductance amplifier. It delivers a load current proportional to an input voltage, handling up to 2 A at 18-36 V with abridge output stage. Completely self-contained, it incorporates internal switch mode circuitry and all the active components to form a current feedback loop.
The L292 is designed primarily for use with an L290 and L291 in DC motor servopositioning applications. However, the L292 can be useful in a wide range of applications as the two examples here show. The first is a simple tachometer feedback circuit, the speed of which is controlled by a DC voltage ; direction is controlled by the polarity of this Voltage. The second circuit is controlled digitally and includes an L291 D/A converter.
SYSTEM WITH DC CONTROL
In this system the control quantity is a dc voltage variable between
+ ViM and - ViM
Since the quantity under control is the speed of the motor, it is required that it varies linearly in function of the control Voltage.
A simplified circuit diagram of the system is shown in fig. 1.
The current 11, proportional to the set voltage Vi, and the current 12, proportional to the speed of the motor, are fed to the sum point of the error amplifier. Assuming that the motor does not drain current, the system is in a steady-state condition whenever 11 = - 12 ; as a matter of fact, in this case the output from the error amplifier Va is OV. During transients, the voltage Va will assume a value Va = - R3 (11 + 12) and consequently, since the L292 integrated circuit operates as a transconductance (Gm), a mean current 1m = Gm . Va will flow in the motor determining an acceleration proportional to it.
Figure 1 : Simplified Circuit Diagram of DC control System.
R2
Vj
RI
CALCULATION OF R1, R2, R3
Let us calt-:
ViM the maximum control voltage value
nM the maximum speed allowed for the motor
Kg
voltage constant of the dynamo
By imposing that the balance condition be met in correspondance to the maximum rotation speed the following equation is obtained:
ViM
Kg. nM
11 = - 12; ~ = - R2
Since R2 is the impedance which the tachometer dynamo is loaded on to and its value is recommended by the manufacturer, it is possible from the previous relationship to determine the value of R1.
Resistor R3 determines the system gain. It's best to keep the gain as high as possible (and consequently R3 as high as possible) to obtain a high response speed of the system, even of for small variations in the control voltage. On the other hand, an excessive gain would cause excessive overshoot around the· balance conditions at the end of transients. Consequently, a trade-off must be made between the two opposing requirements in selecting the final gain.
AN241/1088
1/8
273
APPLICATION NOTE
The value for R3 should be theoretically determined by studying the transfer function, by knowing the electrical and mechanical constants of the motor as well as the load applied to it.
A complete diagram of the circuit actually realized is shown in fig. 2, while fig. 3, shows the character-
istic n = f (Vi) obtained.
Resistor R2 drawn in the simplified circuit diagram has been split here in two parts and, in addition, a capacitor has been interposed to ground to filter the signal coming from the tachometer dynamo.
The curve n. 1 in fig. 3 refers to the operation of the motor in no-load condition, with a current drain of 200 mA ; the curve n. 2 refers to a motor loaded so as to drain a current of 1A. By disregarding the discontinuity around the origin, it can be noted that the characteristics are linear over the whole control voltage range.
By analyzing the curves around the origin, it can be noted that the motor stands still as long as the input signal does not exceed a certain threshold level,
Figure 2 : Complete Circuit Diagram.
which is as much higher as the current drained by the motor is higher.
Let us call Gm the transconductance of L292, and I the starting current of the motor; the voltage which must be available at the input of L292 in order that the motor starts turning is :
-----v- I
mA
Vo = Gm with Gm= 220
(typical value)
The corresponding control voltage will be :
R1
I
R1
Vi=Vo ' f=l3 = ~.
R3
and it is as much lower as the gain of the error amplifier is higher.
The presence of a control voltage interval in which the motor stands still, can be useful when it is required that, for a certain position of potentiometer P1 (see fig. 2), the motor speed be zero. An other method to hold the motor still is to use the inhibits of L292, for instance by grounding pin 13.
R2
· v.
1.2kJl
].3 kll
1nF
2/8
274
D1": D4
VF :S 1.2 V @ I = 2 A trr:s 200 ns
APPLICATION NOTE
It can be noted from fig. 3 that, by keeping the control voltage Vi constant, the speed varies according to the motor current drain.
Let us call 61 the current variation; the voltage variation required at the input of L292 is
61
6 Va = G-m-
since the control voltage is constant, to generate this 6 Va it is necessary that the rotation speed be varied by a quantity 6 n such as to have:
R3
6 I
Kg o 6n 0 F\2=6Va=Gm
6 I
R2
6 n = Gm Kg 0
R3
(6 I shall be taken with its sign)
Figure 3 : Output Characteristics of the Circuit in fig. 2.
(rpm)
'6<'"
>2""
In this case too, the variation 6 n is as much lower as the error amplifier gain is higher. With the circuit shown in fig. 26n is approximately 30 turns/min. with
6 I = 800 mA, 6n = 0.037 turns/mA.min approx.
It is possible to adopt a circuit which prevents the variation in the number of turns in function of motor current. The problem is to "sense" the current flowing through the motor and to send a current proportional to it to the sum point of the error amplifier. The complete circuit which includes, beside the voltage feed-back loop, also a current feed-back loop, is illustrated in fig. 4.
In the integrated circuit L292, a current proportional to the mean current drained by the motor flows between pin 5 and pin 7.
An operational amplifier amplifies the voltage drop provoked by this current across a 51 0 Q resistor and sends a current to the sum point which is consequently proportional to the mean current in the motor, the value of which can be made vary by acting on potentiometer P2. By properly adjusting P2, a condition can be achieved in which the speed does not change when the current drained by the motor varies.
The discontinuity around the origin, which was present in the previous circuit (fig. 2), is practically negligible in the circuit shown in fig. 4.
The characteristic n = f (Vi) relevant to the circuit of fig. 4 is shown in fig. 5, and this characteristic does not substantially change over the whole range of currents allowed by the L292 (up to 2A).
In the circuit described above if the motor stall condition is requested. It is preferable to act on the inhibits of the integrated circuit L292, for instance by grounding pin 13, instead of adjusting potentiometer P1 : as a matter of fact, the exact position of this potentiometer is difficult to obtain, since the characteristic crosses the axis Vi in one only point (this mean that n is only 0 for a very narrow interval of Vi).
3/8 275
APPLICATION NOTE
Figure 4 : Complete Circuit with Current Feedback.
1K
Rl
1.1Kn
3.3Kn
:1.1 pF
0.1 n
Figure 5 : Output Characteristics of the Circuit in fig. 4.
(rpm) '600
1200
/
BOO
--:-:---::---:-----:--71'-----::-----.-
-8 -6
_ 2
2
4
6
8
10 Vi(V)
.toOO
."",
Im=200mA;. 2A
_1200
-1600
01 + 04
{ VF'; 1.2 V @ I = 2 A trr ,; 200 ns
movement shall the clockwise or counter-clockwise. For the circuit implementation, the integrated circuits L291 (which includes a D/A converter and two operational amplifiers) and L292 are used.
A simplified circuit diagram is shown in fig. 6.
Figure 6 : Simplified Circuit Diagram (digital control).
Rl
SYSTEM WITH DIGITAL CONTROL In this system the speed information is given to the circuit by a binary code made up of 5 information bits plus one sign bit, which determines whether the
4/8
276
APPLICATION NOTE
The current value i1 depends on the value of Irel and
on the value of inputs b1 through bs, where its sign depends on the bs input.
The maximum value for i1, which is obtained whenever inputs b1 through bs are low, is :
31
Vrel
31
i1 max = Irel ----:r6 = -~
16
In order to have the system in a steady state condition (no current drained by the motor), it must be :
11 = - 12
By imposing the balance condition at the maximum
speed, one obtains: i1 max = - 12 max
V reI
31
-R-1-· ~ =
Figure 7: Complete Circuit Diagram.
where
Kg = dynamo's voltage constant
nM = maximum speed preset for the motor.
The current Iref, and consequently the ratio Vref/R1, must lie within a certain range imposed by the D/A converter actually used.
In our case, this range is 0.3 to 1 mAo The values of R1 and R2 can be determined from the previous relationship. The same considerations made in the description of the DC control system apply for the selection of R3.
A complete diagram of the circuit implemented is indicated in fig. 7, while the input versus output characteristics is shown in fig. 8.
Rl
1.ZKD
Z7Kf'I'
D/A L291
01 03
01704
5 -58701'
{ VF <; 1.2 V @ I = 2 A trr <; 200 ns
5/8 277
APPLICATION NOTE
In the graph of fig. 8 the rotation speed of the motor is represented on ordinates, while the decimal speed code, corresponding to the binary code applied to inputs b1 throug h b5, is represented on abscissae.
The abscissa 1 corresponds to the minimum speed code, i.e. input b1 low and remaining inputs high, since the least significant input is b1 and the active status of inputs is low. The abscissa 31 corresponds to the maximum speed code, i.e. all inputs b1 through b5 low. The negative abscissae have been obtained by changing the status of the bs input. The graph in fig. 8 should have been made up of a number of dots; these dots have been joined together with an ininterrupted line for convenience. This graph has the same features as the graph in fig. 3, i.e. the curve features a discontinuity around the origin, and it lowers as long as the motor current drain increases. In this case too, the circuit in fig. 7 can be modified in order to prevent that the speed vary in function of the motor load, by adding a current loop in the control circuit, by using the remaining operational amplifier available in the integrated circuit L291.
Figure 8 : Output Characteristic of the Circuit in fig. 7.
n (rpm)
2000
1600
1200
eoo
-32 _24 -16
-1200 ·1600 -2000
Spp~d code 16 24 J2
1:lm::.200mA 2:Jm=IA
Since this amplifier has only the inverting input available, while the non-inverting input is grounded, a circuit arrangement as schematically shown in fig. 9 has been adopted in order to have an output signal referred to ground, given an input signal referred to a reference voltage (in L292) of approximately 8 V. Figure 9 : Translator Circuit.
!.-5171
o
Resistors RA and RB must be high-precision resistors in order to have output 0 with no 1m current present. In the practical implementation, resitors with an accuracy of 5 % are used and the ends of a potentiometer are interposed between resitors RB and the output to the sum point of the error amplifier is made through the cursor. The gain of this current loop is propotional to the ratio R3/RB. A complete circuit diagram is shown in fig. 10. Since, for reasons of gain, resistor RB must be.27 kQ and, if connected to pin 7 of L292, should have subtracted too much current by thus affecting the correct operation of L292, it has been connected to pin 11, having the same potential as pin 7. Consequently, the resistance value between pin 11 and ground has been modified, in order to maintain the switching frequency of L292 unchanged. In order to have a correct adjustment of potentiometer P1, it is enough to set the 0 speed code (b1 through b5 high) and turn the cursor until the motor stops. The input versus output characteristic obtained with the circuit of fig. 10 is indicated in fig. 11.
6/8 278
Figure 10 : Complete Circuit with Current Feedback.
APPLICATION NOTE
R2
01 OJ
Figure 11 : Output Characteristic of the Circuit in fig. 10.
n (rpm) 2000
1600
1200 800 .00
-. -32 -2. -16
Spet>d codt> 16 2. 32
-BOO
/
_1200 -1600
-2000
Im:200mA-f2A
D1 7 D4
{ V, S 1.2 V @ I = 2 A Irr S 200 ns
RESPONSE TO INPUT STEP
Measurements have been taken on the circuits described in the previous paragraphs, in order to analyze how the motor speed varies when a step variation is imposed to the input.
For the system DC control, the control voltage has been changed from 0 to the maximum value ViM and down to 0 again. For the digital system the speed code has been changed from 0 (b1 through bs high) to the maximum value (b1 through bslow) and down to 0 again. When the control quantity changes from
o to the maximum value, the output voltage of the
error amplifier (Va, fig. 1 and fig. 6) assumes its maximum value, since the feed-back signal coming from the tachometer dynamo initially O. In these conditions, L292 supplies the motor with the maximum current (2A) and maintains it until the motor speed is sufficiently close to the maximum value.
Since the motor is powered from a constant current, it moves with a constant current, it moves with aconstant acceleration and consequently its speed grows linearly from 0 up to the maximum value over the time interval tao The time needed for the motor to reach the maximum speed also depends, besides
7/8 279
APPLICATION NOTE
the current, on the electrical and mechanical characteristics of the motor and on the moment of inertial of the load applied to the motor. When the control quantity changes from the maximum value to 0, the output of the error amplifier Va assumes the maximum value, but with an opposite sign with respect to the previous case, and the current flowing in the motor is also reversed and tends to brake it, by making the speed linearly decrease from the maximum value down to 0 over the time period tf. The no-load characteristics, relevant to the motor used for the previous tests, are shown in fig. 12. The times ta and tf are not equal to each other, which circumstance is basically due to the frictions which, during the acceleration phase, oppose increase of speed, while during the deceleration phase they contribute to make the speed decrease. As a matter of fact, from the movement equation:
eJ + 0 8 + Tf = KT 1M
where:
J = System moment of inertia
o = Coefficient of viscous friction
Tf = Braking couple
Kt = Motor constant
8 = Angular speed
8 = Angular acceleration
and by disregarding the term De, one obtains:
KT . 1M - Tf
8=
J
'e where from it can be seen that I I is greater if 1M
is negative.
Figure 12 : Pulse Response.
Vi
o
20
40 60 80 t(msec)
\
D
8/8
280
APPLICATION NOTE
THE L290/L291/L292 DC MOTOR SPEED/POSITION CONTROL SYSTEM
The L290, L291 and L292 together form a complete microprocessor-controlled DC motor servopositioning
system that is both fast and accurate. This design guide presents a description of the system, detailed func-
tion descriptions of each device and application information.
The L290, L291 and L292 are primarily intended for use with a DC motor and optical encoder in the configuration shown schematically in figure 1. This system is controlled by a microprocessor, or microcomputer, which determines the optimum speed profile for each movement and passes appropriate commands to the L291 , which contains the system's D/A converter and error amplifiers. the
L291 generates a voltage control signal to drive the L292 switchmode driver which powers the motor. An optical encoder on the motor shaft provides signals which are processed by the L290 tachometer converter to produce tacho voltage feedback and position feedback signals for the L291 plus distance/direction feedback signals for the control micro.
Figure 1 : The L290, L291 and L292 form a complete DC Motor servopositioning System that connects directly to Microcomputer Chips.
DIRECTlDN
SPEED DEMAND
VELOCITY I POSITION
WORD (S BITS) t-~--'-+_f--/M'-I0DE SELECT
MOTOR CURR ENT (CONTROL VOLTAGE
LZ91 DIGITAL-ANALOG f---'-t---,~ CONVERTER PLUS~-'-_--l~
ERROR AND POSITION
AMPLIFIER
-
L292
SWITCHMODE MOTOR DRIVER
MCU
-POSITION FEEDBACK
ABSOLUTE POSITION
r - - - i - - T ACHO VELOCITY FEED BACK
SIGNAL FOR t---f.--+--DAC REFERENCE VOLTAGE
INITIALIZATION
\
.... ~--'-----4--, ---..--
AN242/1088
1/23
281
APPLICATION NOTE
The system operates in two modes to achieve high speed and accuracy: closed loop speed control and closed loop position control. The combination of these two modes allows the system to travel rapidly towards the target position then stop precisely without ringing.
Initially the system operates in speed control mode. A movement begins when the microcomputer applies a speed demand word to the L291 , typically calling for maximum speed. At this instant the motor speed is zero so there is no tacho feedback and the system operates effectively in open loop mode (see figure 2). In this condition a high current peak - up to 2A - accelerates the motor rapidly to ensure a fast start.
As the motor accelerates the tacho voltage rises and the system operates in closed loop speed mode, moving rapidly forwards the target position. The microcomputer, which is monitoring the optical encoder signals (squared by the L290), reduces the speed demand word gradually when the target position is close. Each time the speed demand word is reduced the motor is braked by the speed control loop.
Finally, when the speed code is zero and the target position extremely close, the micro commands the system to switch to position mode. The motor then stops rapidly at the desired position and is held in an electronic detent.
Figure 2 : The System operates in two Modes to achieve High Speed and Accurary. Tachometer Feedback regulates the Speed during a Run and brakes the Motor towards the End. Position Feedback allows a Precise Final Positioning.
MOTOR SPEED
MOTOR AC~ELERATES
RAPIDLY IN INITIAL OPEN LOOP CONDITIONS
VELOCITY FEEDBACK
REGULATES SPEED DURING RUN
I
MOTOR BRAK ED PROGRESSIVELV BV
REDUCING SPEED
DEMAND WORD
r .
) ,
FINAL. PRECISE POSITIONING PERFORMED IN POSITION MODE
2A MOTOR CURRENT
O~~~=============+AH~~h-
-2A
INITIAL HIGH CURRENT PEAK ENSURE S F AS T STARTUP
s- s~51
t
MOTOR BRAKED AS
' - LOOP RESPONDS TO REDUCTIONS IN SPEED
DEMAND WORD
2123 282
APPLICATION NOTE
OPTICAL ENCODER
The optical encoder used in this system is shown schematically in figure 3. It consist of a rotating slotted disk and a fixed partial disk, also slotted.
Light sources and sensors are mounted so that the encoder generates two quasi-sinusoidal signals
with a phase difference of ± 90· . These signals are
referred to as FTA and FTS. The frequency of these signals indicates the speed of rotation and the rela
tive phase difference indicates the direction of rotation. An example of this type is the Sensor Technology STRE 1601, which has 200 tracks. Similar types are available from a number of manufactures including Sharp and Eleprint.
This encoder generates a third signal, FTF, which consists of one pulse per rotation. FTF is used to find the absolute position at initialization.
Figure 3 : The System operates with an Optical Encoder of the Type shown schematically here. It generates two Signals 90 0 out of Phase plus a one Pulse-per-rotation Signal.
CNE PULSE P'OR ROTATION OUTPUT
\ '-~ FTF --'
HOLE TO GENERATE ONE PULSE PER ROTATION SIGNAL
SINEWAVE OUTPUTS WITH
±90· PHASE OIFFERENCE
S 5972
THE L290 TACHOMETER CONVERTER
The L290 tachometer converter processes the three optical encoder signals FTA, FTS, FTF to generate a tachometer voltage, a position signal and feedback signals for the microprocessor. It also generates a reference voltage for the system's D/A converter.
Analytically, the tacho generation function can be expressed as :
dVAS TACHO= - -
dt
FTA IFTAI
dVAA dt
FTS IFTSI
In the L290 (block diagram, figure 4) this function is implemented by amplifying FTA and FTS in A1 and A2 to produce VAA and VAS. VAA and VAS are differentiated by external RC networks to give the signals VMA and VMS which are phase shifted and proportional in amplitude to the speed of rotation. VMA and VMS are passed to multipliers, the second inputs of which are the sign of the other signal before differentiation.
FTA
FTS
The sign (IFTAI or IFTSI ) is provided by the
comparators CS1 and CS2. Finally, the multiplier outputs are summed by A3 to give the tacho signal. Figure 5 shows the waveforms for this process.
This seemingly complex approach has three important advantages. First, since the peaks and nulls of CSA and CSS tend to cancel out, the ripple is very small. Secondly, the ripple frequency is the fourth harmonic of the fundamental so it can be filtered easily without limiting the bandwidth of the speed loop. Finally, it is possible to acquire tacho information much more rapidly, giving agood response time and transient response.
Feedback signals forthe microprocessor, STA, STS and STF, are generated by squaring FTA, FTS and FTF. STA and STS are used by the micro to keep track of position and STF is used at initialization to find the absolute position.
3/23
283
APPLICATION NOTE
Position feedback for the L291 is obtained simply from the output of A 1.
The L290 also generates a reference voltage for the L291 's D/A converter. This reference is derived from VAA and VAS with the function:
Vref""- IVAAI + IVAsl
Since the tacho voltage is also derived from VAA and VAS it follows that the system is self compensating and can tolerate variations in input levels, temperature changes and component ageing wifh no deterioration of performance.
Figure 4 : The L290 processes the Encoder Signals, generating a Tacho Voltage and Position Signal for the L291 plus Feedback Signals for the Microprocessor. Additionally, it generates a Reference Voltage for the L291 's D/A Converter.
STF
FEEDBACK SIGNAlS FOR
MICROPROCESSOR
51B
ISTAO -
OPTICAL ENCODER SIGNALS
rTF FTB FTA
AC NETWORKS
REFERENCE VOLTAGE OUTPUT FOR O/JI,.' CONVERTER IN L 1~1
TACI-tO VOLTAGE 0 0 UTPUT TO !.. 291
POSITION
FEEDBACK TO l291
4/23
284
APPLICATION NOTE
Figure 5 : These Waveforms illustrate the Generation of the Tacho Voltage in the L290. Note that the Ripple is fourth Harmonic. The Amplitude of TACHO is proportional to the Speed of Rotation.
CLOCKWISE
DIRECTION
I
I
ANTICLOCKWISE DIRECTION
I
VAA
VA"
C51
CS'
VM"
C56 CSA TACHO
Figure 6 : The L291 Links the System to the Microprocessor. It contains the system DA converter, main error amplifier and position amplifier.
OIA REFERENCE TACHO VOLTAGE
FROM L290
FROM U9C
POSJTJON FEEDBACH FROM U90
REMovES ,.... FOURTH HARMONlC
RIPPLE
SPEED DEMAND WORD
-....qf--l OAC I - - - - f - l
VELOCITY
LOOP GAIN
J CONTROL
>--f--l--t--~--Q ~gLT~~~2
DRIVER
DIRECTION (SIGN)
POSITION MODE. SHECT
(STROBE)
_______ -
_________ -
r: I
- __I
5 - S'l 54/2
5/23
285
APPLICATION NOTE
THE L291 D/A CONVERTER AND AMPLIFIERS
The L291 , shown in figure 6, links the system to the micro and contains the system's main error amplifier plus a position amplifier which allows independent adjustment of the characteristics of the position loop.
It contains a five bit O/A converter with switchable polarity that takes its reference from the L290. The polarity, which controls the motor direction, is controlled by the micro using the SIGN input.
The main error amplifier sums the O/A converter output and the tacho signal to produce the motor drive signal ERRV. The position amplifier is provided to allow independent adjustment of the position loop gain characteristics and is switched in/out of circuit to select the mode. The final position mode is actually 'speed plus position' but since the tacho voltage is almost zero when position mode is selected the effect of the speed loop is negligible.
THE L292 SWITCHMODE MOTOR DRIVER
The L292 can be considered as a power transconductance amplifier - it delivers a motor current proportional to the control voltage (ERRV) from the L291. It drives the motor efficiently in switch mode and incorporates an internal current feedback loop to ensure that the motor current is always proportional to the input control signal.
The input control signal (see block diagram, figure 7) is first shifted to produce a unipolar signal (the L292 has a single supply) and passed to the error amplifier where it is summed with the current feed-back signal. The resulting error signal is used to modulate the switching pulses that drive the output stage.
External sense resistors monitor the load current, feeding back motor current information to the error amplifier via the current sensing amplifier.
The L292 incorporates its own voltage reference and all the functions required for closed loop current control of the motor. Further, it features two enable inputs, one of which is useful to implement a power on inhibit function.
The L292's output stage is a bridge configuration capable of handling up to 2A at 36V. A full bridge stage was chosen because it allows a supply voltage to the motor effectively twice the voltage allowed if a half bridge is used. A single supply was chosen to avoid problems associated with pumpback energy.
In a double supply configuration, such as the example in figure 8 a, current flows for most of the time through 01 and Ql. A certain amount of power is thus taken from one supply and pumped back into the other. Capacitor Cl is charged and its voltage
can rise excessively, risking damage to the associated electronics.
By contrast, in a single supply configuration like figure 8b the single supply capacitor participates in both the conduction and recirculation phases. The average current is such that power is always taken from the supply and the problem of an uncontrolled increase in capacitor voltage does not arise.
A problem associated with the system used in the L292 is the danger of simultaneous conduction in both legs of the output bridge which could destroy the device. To overcome this problem the comparator which drives the final stage consists of two separate comparators (figure 9). Both receive the same Vt, the triangular wave from the oscillator, signal but on opposite inputs.
6/23
286
APPLICATION NOTE
Figure 7 : The L292 Switchmode Driver receives a Control Voltage from the L291 and delivers a switch mode regulated Current to the Motor.
CURRENT FEEDBACK FRO,.. MOTOR
' - r-c"=O!l:r--<r--('=lO::JC----,
22It.O __________ ..... ______ 7
41nF
C __ ~
CURRENT
CONTROL VOLTAGE
.......
VJ O"--~=I-'---f
FROM l291
SENSE RESISTORS RSZ ...)
I I
t
10F
151\0
J: '.5nF
SWITCHING
J
FREOUENCY ....,.
'--POWER ON INHIBIT
Figure 8 : A Simple Push Pull Output (a) needs a Split Supply and the Device can be damaged by the Voltage Built up on C1. The L292 has a Bridge Output to avoid these Problems. Only one Supply is needed and the Voltage across the Single Capacitor never rises excessively. Moreover, the Motor can be supplied with a Voltage up to twice the Voltage allowed with a Half Bridge.
a
b
7/23
287
APPLICATION NOTE
The other two inputs are driven by VTH, the error amplifier output, shifted by plus or minus R1:I'. This voltage shift, when compared with Vt, results in a delay in switching from one comparator to the other.
Figure 9 : The L292's final Comparator actually consists of two Comparators. This Configuration introduces a Delay to prevent simultaneous Conduction of two Legs.
SOFTWARE AND INTERFACING TO THE MICRO
In a typical system the L290/1/2 system is connected to the control microcomputer through ten I/O lines: seven outputs and three inputs.
The outputs are all connected to the L291 D/A con. verter and consist of the five bit speed demand word, SIGN (which sets the direction) and the speed/position mode select line. Position feedback for the micro comes from the L290 tacho converter and consists of the signals STA, STB (the squared encoder outputs) plus the one-pulse-per rotation signal, STF (figure 11).
Figure 11 : In a typical system the L290/L291/ L292 combination is linked to the micro through seven output lines, two inputs and an interrupt input.
TWO INPUTS
1 -. - - - - 5 1 .
_. --STF
FROM L290
Consequently there will always be a delay between switching off one leg of the bridge and switching on the other. The delay 1: is a function of the integrated resistor R1: (1.5kQ) and an external capacitor C17 connected to pin 10 which also fixes the oscillator frequency. The delay is given by :
1:= R1: C17
In multiple L292 configurations (in a typewriter, for example, there may be two systems) it is desirable to synchronise the switching frequencies to avoid intermodulation. This can be done using the configuration shown in figure 10.
Figure 10 : Ground Plane switching Noise and Modulation Phenomena are avoided in Multi-L292 Systems by synchronizing the Chopper Rate with this RC Network.
L292
L292
MCU
SEVEN OUTPUT LINES
1------ SCI - 5C5
----- r----~
SPEED DEMAND
r - - - - WORD
(--------
TO L29t
I-----~ POSITION MODE
To follow the motor position the micro counts the STA pulses to measure the distance travelled and compares the phase of STA and STB to sense the direction. The most convenient way to do this is to connect the STA line to an interrupt input. An interrupt service routine will then sample STB and increment or decrement the position count depending on the relative phase difference: + 90' if STB is high; -90' if STB is low.
It could be argued that the micro doesn't need to sense the direction of the rotation because it controls the direction. In practice, however, it is better to sense the direction to allow for the possibility that the motor may be moved by externally applied forces.
For each movement the micro calculates the distance to be travelled and determines the correct direction. It then sets the L291 to velocity feedback mode, sets the director appropriately and sets the speed demand word for maximum speed (possibly less if the move is very short).
By means of the STA interrupt service routine it follows the changing position, reducing the speed de-
8123 288
APPLICATION NOTE
mand word to brake the motor when the target position is very close. Finally, the micro orders the L291 to switch to position loop control for the final precise positioning.
When the system is powered up the mechanical subsystem may be in any position so the first step is to initialize it. In applications where the optical encoder never rotates more than one revolution - the daisy wheel of a typewriter, for example -this is simply done by rotating the motor slowly until the STF signal (one-pulse-per-rotation) is detected.
Where the optical encoder rotates more than once the 'one·pulse-per-rotation' signal is not sufficient. An example of this is the carriage positioning servo of Cl. computer printer. In this case the simplest solution is to fit a microswitch on one of the endstops. First the motor is run backwards slowly until the carriage hits the endstop. Then it moves forward'until the STF signal is detected. The beauty of this solution is that the endstop microswitch does not need to be positioned accurately.
Figure 12: Complete Application Circuit of the System.
FRO'"' ENCODER
-20V
c~~
I---'-~c"l~
'"O.2n
L292
eE2 eEl 12 13
ONIH) OFFIll
01 + D4 1A Fast Diodes
VF ,; 1.2V @ I = 2A trr,; 200ns
9/23 289
APPLICATION NOTE Figure 13: P.C. Board and Component layout (1 : 1 scale).
5C1
a:
0
SC2 5C3
Vl Vl
SC4
UJ
u 0aa:.
SC5
SIGN
STR
~ STF
STS
STA
GND
a: FTF
UJ 0
FTA
u 0 z
FTS -12 V
UJ GND
+12 V
Figure 14.
Component
Recommended Value
Purpose
Rl,R2,R3
1 kQ
To filter the noise on the encoder signals.
R4, R5
820 Q
Differentiator Network
R6, R7
R8 R9
Rl1
4.7 kQ
4.7 kQ 5 kQ
22 kQ
To set the D/A input current.
To set the motor speed.
To adjust the motor speed.
To set the position loop gain.
R12
100 kQ
To set the position loop
gain. -.
R13
120 kQ
To set the speed loop
gain.
R14
15 kQ
To set the position loop
gain.
R15, R16
510 Q
To filter the feedback current.
Larger than Recommended Value Offset voltage increase (VAA, VAS). Tacho offset and tacho Signal increase. D/A input current decrease. Motor speed increase. Danger of Oscillation R9 " R13/10 - Position loop gain
decrease.
- Position loop gain decrease.
- Speed loop gain increase.
- Position loop gain increase.
- Danger of oscillation of the motor
Danger of output saturation of the current sensing amplifier R15 + R16" 3.3 kQ.
Smaller than Recommended Value
Tacho offset increase. Tacho signal decrease. D/A input current increase. Motor speed decrease.
- Position loop gain increase.
- Danger of oscillation of the motor shaft.
- Position loop gain increase.
- Danger of oscillation of the motor shaft.
- Speed loop gain decrease.
- Position loop gain decrease.
10/23
290
APPLICATION NOTE
Figure 14 : (continued).
Component
Recommended Value
Purpose
Larger than Recommended Value
R17
22 kG
To set the gain of the err. Increase of the gain at
amplifier.
high frequencies.
R18, R19
0.2 G
To set the transconductance Transconductance decrease
vatue of the L292.
(R18 , RI5). 1m :S 0.44 V.
R20
15 kG
To set the oscillator
Oscillator frequency
frequency.
decrease.
R 21
33 G
Compensation Network
Cl,C2,C3 C4, C6 C5 C7 C8
Cl0,Cl1 C12
C13
C15 C16
100 pF 15 nF 2.2 ~F 0.1 ~F 0.22 ~
0.1 ~F 47 nF
47 nF
0.1 ~F 470 ~F
To filter the noise on the Bandwidth reduction of
encoder signals.
the low pass filter.
Differentiator Network
Tacho signal increase.
By-pass Capacitor
Larger set-up time after power on.
Low-pass filter for the D/A input current.
- Low pass filter for the tacho signal.
- To determine the dominant pole of the speed loop.
Bandwidth reduction of the speed loop.
Supply By-pass Capacitor
To filter the feedback current
- Lower value of the damping factor.
- Danger of Oscillations
To set the gain of the error amplifier C13 - R17 = LM/RM
Supply By-pass Capacitor
Supply By-pass Capacitor
C17
C18 01,02, 03, 04
1.5 nF
1 nF 1 A Fast Diodes
To set the oscillator frequency and the dead time of the output transistors.
Compensation Network
Recirculation Diodes
- Oscillation Frequency Reduction
- Dead time increment.
Smaller than Recommended Value Danger of Oscillations R17 > 5.6 kG Transconductance increase. Osciltator frequency increase. R20 ~ 8.2 kG Increase of the peak current in the output transistors during the communications. Bandwidth increment of the low pass filter. Tacho signal Decrease. Reduced by-pass effect at low frequencies. Increase of the current ripple at low speed. Low filtering at low speed, causing noise on the motor.
Danger of Oscillations. - Higher value of
dumping factor.
Danger of Oscillations Ripple increment on the supply voltage. - Oscillation Frequency
Increment - Dead time reduction. Danger of Oscillations
11/23
291
APPLICATION NOTE
APPLICATION CIRCUITS
The complete circuit is shown in figure 12 ; a suitable layout for evaluation is given in figure 13. Component values indicated are for a typical system using a Sensor Techonology STRE1601 encoder and a motor with a winding resistance of 50 and an inductance of 5mH (this motor is described fully in figure 17). How to calculate values for other motors is explained further on.
Figure 14 explains what each component does and what happens if is varied. Maximum and minimum values are also indicated where appropriate.
This is a preferable to simply adding a discrete driver stagejn place of the L292 because the L292's current control loop is very useful.
Figure 15 shows how four transistors are added to increase the current to 4, 6 or SA, depending on the choice of transistor. When coupled to the L290 and L291 this configuration appears to the system as an L292.
The average motor current, 1m, is found from:
Vi 0.044
Im
=
-Rx
-
ADDING DISCRETE TRANSISTORS FOR HIGHER POWER
In the basic application, the L292 driver delivers 2 A to the motor at 36V. This is fairly impressive for an integrated circuit but not enough for some applications: robots, machine tools etc. The basic system can be expanded to accomodate these applications by adding external power transistors to the L292.
Where Vi is the input voltage and Rx is the value of the sense and resistors R7 and RS.
Suitable transistors for this configuration are indicated below:
I(A) Vi(V Rx(mD) Q1,02 03,04 01 - 04
4 9.1 6 9.1 8 9.1
100 B0708 B0707 2A Fast Diodes 65 B0908 B0907 3A Fast Diodes 50 BOW52A BOW51A 4A Fast Diodes
Figure 15 : For higher power external transistors are added to the L292. This circuit delivers up to 4A, if 2 BDW51A and 2 BDW52A are used it can deliver SA.
l
R7
D.lfi
12/23
292
S-4866/1
APPLICATION NOTE
The circuit shown in figure 16 is suitable for motor currents up to 50A at voltages to 150V. Two sup lies are used; 24V for the L292 and LS141 and 150V for the external transistors and motor. This circuit too behaves just like an L292, except for the higher power, and connects to the L290 and L291 as usual.
The motor current is given by :
Vin X 120 X 10'6 R
Im = - - - - - -
where
Rs
= Rs1
= Rs2
=
Rs 12
x
3
10'
Q
and 390 Q < R < 860Q
This gives a range of transconductance values
(Im/Vin) from 3.0AN (R = 390 Q ) to 8.6AN
(R = 860Q).
In this circuit the L292 drives two transformers whose secondaries drive the power transistors. The coil ratio of the transformers is 1 : 20. To limit the duty cycle at which the transformers operate from 15% to 85%, two zener diodes are inserted between pin 7 and pin 9 of the L292. The LS141 op amp supplies current feedback from the transistor bridge to the L292.
Figure 16 : For higher voltages and currents-up to 150V at 50A, this circuit can be used. It connects to the L290 and L291 , behaving just like and L292.
+Vs lSOV
FREaUENCV lo.7KIl
13/23
293
APPLICATION NOTE
DESIGN CONSIDERATIONS
The application circuit of figure 12 will have to be adapted in most cases to suit the desired performance, motor characteristics, mechanical system characteristics and encoder characteristics. Essentially this adaptation consists of choosing appropriate values for the ten or so components that determine the characteristics of the L290, L291 and L292.
The calculations include: · Calculation of maximum speed and accelera-
tion ; useful both for defining the control algorithm and setting the maximum speed. " Calculation of RB and R9 to set maximum speed. · Laplace analysis of system to set CB, R11, R12, R13 and R14. · Laplace analysis of L292 loop to set the sensing resistors and C12, C13, R15, R16, R17. " Calculation of values for C4 and C6 to set max level of tacho signal. " Calculation of values for R6 and R7 to set D/A reference current. · Calculation of R20 to set desired switching frequency.
MAXIMUM ACCELERATION
For a permanent magnet DC motor the acceleration torque is related to the motor current by the expression:
Ta + Tf = KT 1m
where:
1m
is the motor current
KT
is the motor torque constant
Ta
is the acceleration torque
Tf
is the total system friction torque
The acceleration torque is related to angular acceleration and system inertia by :
Ta = (Jm + Joe + JL) a
where:
Jm
is the moment of inertia of the motor
Joe
is the moment of inertia of the encoder
JL
is the moment of inertia of the load
a
is the angular acceleration
In a system of this type the friction torque TI is normally very small and can be neglected. Therefore, combing these two expressions we can find the angular acceleration from:
KT
a =
. 1m
J m + Joe + JL
It follows that for a given motor type and control loop the acceleration can only be increased by increasing the motor current, 1m.
The characteristics of a typical motor are given in figure 17. From this table we can see that:
KT = 4.3N cm/A
Jm= 65g . cm2
(6.07 oz.in/A) (0.92 x 10-3 oz. in S2)
We also know that the maximum current supplied
by the L292 is 2 A and that the moment of inertia of the STRE 1601 optical encoder, Joe, is 0.3 X10.4 OZ.
in. S2.
= The moment of inertia of the load JL, is unknown but
assume, for example, that Joe + JL 2 J m. Therefore the maximum angular acceleration is :
6.07 x 2
a =
= 6597.Brad/s2
2 x 0.92 x 10-3
Fig. 17- The Characteristics of a Typical DC Motor.
Motor - Parameter
UB B (Vs) C. emf. KE . No (without load) 10m (without load) T f (friction torque) KT (motor constant) Amature Moment of Inertia RM of the Motor LM of the Motor
Value
18 V 4.5 mV/min- 1 3800 rpm 190 mA 0.7 N cm 4.3 N cm/A 65 g. cm. 2 5.4 Q 5.5 mH
MAXIMUM SPEED
The maximum speed can be found from:
Vs min = 2 VCEsat + Rs 1m + Ke Q + Rm 1m
where: E =
Ke Q is the internally generated voltage
(EMF)
Ke
is the motor voltage constant
Q
is the rotation speed of the motor.
For example, if Vs min = 20V
2 VCEsat + Rs 1m = 5V (from L292 datasheet)
Rm 1m = 10.BV (Rm = 5.4 Q)
we obtain:
Ke Q (E) = 4.2V
and
4.2V
Q = 4.5 rnV/min-1 = 933.3rpm =
= 97.74rad/s
14/23 294
APPLICATION NOTE
The STRE1601 encoder has 200 tracks so this speed corresponds to :
200
= 3111.1 tracks/so
60
The time taken to reach maximum speed from a standing start can be found from
a Q
97.74 rad/s
~ t =
= 6597.S rad/s2 = 14.Sms
We can also express the acceleration in terms of tracks/s2 :
V
3111.1 tracks/s2
~ t
14.S ms
= 21 0209.S tracks/s2
Therefore the number of tracks necessary to reach the maximum system speed for our example is :
V2
p=
2K
= 23 tracks
This information is particularly useful for the pro-
grammer who writes the control software.
SETTING THE MAXIMUM SPEED
The chosen maximum speed is obtained by setting the values of R6, R7, RS, R9, C4 and C6 (all shown on the application circuit, figure 12). This is how it's done:
The first step is to calculate R6 and R7, which define the DAC current reference. From the L291 datasheet we know thatlref, the DA converter current reference, must be in the range 0.3mA to 1.2mA.
Choosing an Iref of roughly O.SmA, and knowing that Vref (the L290s reference output) is typically SV, it follows that:
Vref
R6 + R7 =
= 10kQ
Ire!
Therefore we can choose R6 = R7 = 4.7kQ (S% tolerance).
Substituting the minimum and maximum values of Vref (from the L290 datasheet) and the resistance
variations we can now check that the variation of Iref in the worst case is acceptable.
Vrefmin
Irefmin = (R6 + R7) max = 0.46mA
Vref (typ)
Ireftyp = 4.7 k + 4.7 k = 0.S3mA
Vref max Iref max = -:C(R=-6c--+-=RC:7:C:-)m-:-in = 0.62mA
These values are within the 0.3mA to 1.2mA limits.
Now that the reference current is defined we can calculate values for RS and R9 which define the tacho current at the summing point.
The full scale output current of pin 12 of the L291 (the D/A converter output) is :
10 = 1.937 Iref
which is typically 1.02mA.
The worst case output current is when Iref is at a maximum (0.62mA) and the lout error is maximum (+2%) :
10 = 0.62 x 1.937 x 1.02 = 1.22mA
This less than the 1.4 mA maximum value for lout specified in the L291 datasheet.
Assuming that the maximum DC voltage at the. TACHO output of the L290 (pin 4) is 7V (this is the tacho voltage generated at the maximum system speed), we can find the sum of RS and R9 ;
Vtacho DC
7
RS + R9 =
= - - = 6.SSkQ
lotyp
1.02
Therefore we choose RS = 4.7kQ and a SkQ trim-
mer for R9. R9 is used to adjust the maximum speed.
We can now calculate the ripple voltage and maximum tacho voltage:
It
Vripple pp = -
4
= ({2- 1) Vtacho DC 2.3 Vpp
It
Vtacho max = 4
= {2Vtacho DC 7.S Vp
15/23 295
APPLICATION NOTE
This value is within the voltage swing of the tacho amplifier (± 9V) ; that means the choice of
Vtacho DC = 7V is correct.
At this point we know the values of R6, R7, R8 and R9. The maximum speed can now be set by choosing values for C4 and C6 which form the differentiation networks on the L290. These values depend on the number of tracks of the optical encoder. For the STRE1601 encoder the capacitor values can be found from figure 18. These curves show how the capacitor values is related to frequency (encoder rotation speed) for different tacho voltages and maximum speed. The example values are Vtacho DC = 7V
and maximum speed = 3111 tracks/sec therefore
the value for C4 and C6 is 15nF.
The values of R4 and R5 must be 820£1 to minimize the offsets.
Figure 18 : C4 and C6 value versus rotation speed for various maximum tacho voltage values.
c.
(nF)
G J., 937
35
Illl
30
1\'1\
H\
25
, .,II
\ ~\\ \'
20
l\\.
15 10
\\,
" - l'..lr\-..:.
r-..
........
:--....['0
....... t'-- :---;t't--.
VtachoDC..=...5..V 6V I 7V
8[
I
iI III
1 111
I
2
3
4
5 6 f(KHz)-FTA
300 600 900 1200 1500 1800 rpm
Figure 19.
(.) See L292 datasheet for an accurate analysis of this block.
List of terms
s : Laplace variable
KT : Motor torque constant
Ta : Acceleration torque
Tf : Total system friction torque
J
: Total moment of inertia (J = Joe + Jm + JL).
: Speed : Angular position : Conversion factor that links the motor rotation speed and the TACHO signal. KT : Conversion factor that links the motor position and the
Vpos signal.
16/23
296
APPLICATION NOTE
LAPLACE ANALYSIS OF THE SYSTEM
itable values for the components R11, R12, R13, R14 and CS can be found from a Laplace analysis of the system. Figure 19 shows a simplified block diag ram of the system which will be useful for the analysis.
The analysis is based on the angular speed nand on the motor position 8. The motor is represented, to a first approximation, by the current 1m and by the acceleration torque, Ta, which drives an inertial
load J.
There are two conversion factors, Ksp and K8. They link the mechanical parameters (position and speed) with the equivalent feedback signals for the two loops. The values of Ksp and K8 are determined by the encoder characteristics and the gain parameters of the integrated circuits. The openloop and closed-loop gains are fixed by four external resistors: " Rref - fixes the reference current (R6 + R7) " Rspeed - fixes the speed loop gain (RS + R9) " Rpos - controls the position loop gain (R12) .. Rerr - controls the system loop gain (R13).
The stability both of the speed loop and of the speed-position loop are defined by external components.
The fundamental characteristics of the speed control system can thus be determined by the designer.
1:sp is the time constant that determines the dominant pole of the speed loop and is determined by CS, RS and R9
RS R9
RS + R9.
SETTING THE L292 COMPONENTS
The sensing resistor and feedback loop component values for the L292 can be calculated easily using the following formulae. A detailed Laplace analysis of this block is given on the L292 datasheet.
a) Sense resistors.
Rs = R1S = R19
1m
R2 R4
I
Vi
R1 R3 Rs
R2 R4 Vi
Rs = 1m R1 R3
(These resistors are all inside the L292).
where:
1m
is the motor current
Vi
is the input voltage corresponding to 1m.
For example, 1m = 2 A, Vi = 9.1 V, resistor values as in figure 7 (L292 internal block diagram) .
0.044
Rs=
Vi = 0.2 n
1m
b)R17,R15, R16,C12,C13
Gmo =
Vs = L292 supply voltage
Rm = motor resistance
VR = L292 reference voltage
and
,/
R4C13
~ =V 4R15 C12 Gmo Rs
R4 = L292 internal resistor (400n)
Rs = R1S = R19 A good choice for ~ is 11 .v2. Substituting this value, Gmo and the values of R4 and Rs :
~2= 1 2
400 C13 4R15 C12 x 0.2
1000 C13
=}
= 1
R15C12
0.9
Also
IT= 21tR15C12
Assuming that IT is 3kHz, another recommended value:
R15 C12",47 x 10·6s
Therefore we can find C13 : 1000 C13 =0 47 x 10.6 =} C13 = 47nF
Since
=R17C13
R17 = C13 Rm
Forthe example motor Lm = 5mH, Rm = 5.4n therefore:
R17 =
Lm C13 Rm
= 22kn
From R15C12=o47x 1O·6 s,choosing a value of R15 ; 510n, we have:
C12 = S2nF
Also, R16 = R15 = 510n.
17/23 297
APPLICATION NOTE
DEAD TIME
C17 sets the switching delay of the L292 which protects against simultaneous conduction. The delay is:
1: = R1: C17
and R, is an internal 1.5k resistor. The suggested 1.5nF value gives a switching delay of about 2.25/lS. This is more than adequate because the transistors have a switch off delay of only 0.5I1S.
SWITCHING FREQUENCY
The switching frequency is set by C17 and R20 :
I fose = 2 R20 C17
R20 must be at least 8.2kQ and is varied to set the frequency: the value of C17 is imposed by dead time requirements. Typically the frequency will be 15-20kHz.
It should be outside the audio band to reduce noise but not to high or efficiency will be impaired. The maximum recommended value is 30kHz.
CURRENT RIPPLE
To reduce dissipation in the motor and the peak output current the ripple, ~ Im,should be less than 10% of the maximum current.
Since
T
~Im=
2
(2T" = half period oscillator)
and ~ 1m = 0.1 1m max
Vs 0.1 1m max = 2 f LM min
LM min =
5 Vs f 1m max
Therefore there is a minimum inductance for the motor which may not always be satisfied. If this is the case, a series inductor should be added and the value is found from:
Lseries =
5 Vs f 1m max
EFFICIENCY AND POWER DISSIPATION
Neglecting the losses due to switching times and the dissipation due to the motor current, the efficiency of the L292's bridge can be found from:
~ t1 11- 1-
~ t1 - Llt2
Vsat
~ t1
Vover
----"
Vs Llt- ~ t2 Vs
where:
Vover == 2V (2VSE + Rs 1m) Vsat == 4V (2VCEsat + 3 VSE ) Ll t1 = transistor conduction period
Ll t2 = diode conduction period.
If Ll t1 ~ Ll t2 and Vs = 20V we obtain:
11=1-
4
20
=80%
In practice the efficiency will be slightly lower as a results of dissipation in the signal processing circuit (about 1W at 20V) and the finite switching times (about 1W).
If the power transferred to the motor is 40W, the 80% efficiency implies 1OW dissipated in the bridge and a total dissipation of 12W. This gives an actual efficiency of 77%. Since the L292's Multiwatt package can dissipate up to 20W it is possible to handle continuous powers in excess of 60W.
POSITION ACCURACY
The main feature of the system L290, L291, L292 is the accurate positioning of the motor. In this section we will analyse the influence of the offsets of the three ICs on the positioning precision.
When the system is working in position mode, the signal FTA coming from the optical encoder, after suitable amplification, is sent to the summing point of the error amplifier (L291). If there were no offset and no friction, the motor would stop in a position corresponding to the zero crossing of the signal FTA, and then at the exact position required. With a real system the motor stops in a position where FTA has such a value to compensate the offsets and the friction; as a consequence there is a certain imprecision in the positionning. The block diagram, fig. 20, shows the parts of the 3 ICs involved in the offsets. First we will calculate the amount of the offsets at the input of the IC L292 (point A of fig. 20).
18/23 298
Figure 20.
APPLICATION NOTE
TACHO
L292
R12
L..._ _ _ _ _ _ _..... 5-5965
L290
The offset of the TACHO signal, V2, is the main cause of the imprecision of the positioning. Another offset in L290 is Vi, the output offset voltage of Ai. The contribution at point A is :
R14 R13 V1A=V1' R11 . R12
R13 V2A = V2' R89
L291
In this IC there are the following offsets:
V3 = input offset voltage of the position amplifier
11 = input bias current of the postion amplifier
12 = output offset current of the D/A converter plus ER. AMP bias current
V4 = input offset voltage of the error amplifier.
Their contribution at point A is :
V3A = V3 · (1 +
R14
R13
) . -
R11
R12
R13 VllA= 11· R14--
R12
VI2A= 12. R13
V4A=V4(1+ R13 ) R1211R89
L292
Referring to this IC we must consider the input offset voltage V5. Moreover, we call V6 the input voltage that must be applied to the L292 to keep the motor in rotation, i.e. to compensate the dynamic friction. V6 is not an offset voltage, but has the same effects, and for this reason we have to put it together with the offsets.
V5A = V5
10 = Transconductance of L292 Vi
19/23
299
APPLICATION NOTE
Ie = Motor current necessary to compensate the dynamic friction
The total offset voltage referred to point A is given by the sum of all the precedent terms:
VA = V1A + V2A + V3A + Vi1A + VI2A V4A + VSA + VeA.
The amplitude of the signal FTA necessary to compensate the offset VA is :
R12 R11
VFTA= VA' - - , - -
R13 R14
A1
Calling VM the maximum value of the signal FTA, the phase error of the system is :
ex = sin-1
VFTA VM
If <Xc is the phase between two consecutive characters, (it may be equal 360' or multiple of it) the percentage error in the character positioning is :
ex
E= -a.-c ·100
In these calculations we have not considered how the precision of the signal FTA, coming from the optical encoder, influences the positioning error. The percentage value of the pitch accuracy must be added to Eto have the total percentage error in the character positioning. Any DC offset of the mean value of the signal FTA must be multiplied by A1 and added to V1 to obtain its effect on the error.
NUMERICAL EXAMPLE
In this numerical example we will calculated the precision of the positioning in the worst case, i.e. with all the offsets at the max value. The values of the external components are taken from the application circuit. (fig. 12).
R11 = 22K R12 = 100K R13 = 120K R14 = 15K RS9 = RS + R9 = 6K
From the data sheets of the three ICs we can find:
V1 = 55mV V2 = SOmV V3 = 4.5mV
V4 = 2mV
V5 = 350mV
11 = 0.3~
12 = 0.4f1A A1 min = 22dB = 12.6
V10i min = 205 --m-vA--
VMmin = 0.4 V For 16 we will consider the value 16 = 50mA
15 V1A = 55.10-3 ,
22
120 = 45mV
100
V2A = SO ' 10-3 , -1260= 1.6V
15 120 V3A = 4.5 ,10-3 (1 + 22) '100 = 9.1mV
120 VhA= 0.3' 10-e . 15 '103100 = 5.4mV VI2A = 0.4 . 10·e . 120 . 103 = 4SmV
120 V4A = 2 . 10-3 . ( 1 + 5.6 ) = 44.9mV
VSA = 350mV
50 V6A =205= 244mV
VA = 2.346V
100
VFTA = 2.329 '120'
--2-2:rs'
1 12.6 = 0.22SV
ex = sin-1
0.226 0.4
If we consider an optical encoder with 200 tracks/turn and a daisy wheel with 100 characters, the phase between two consecutive characters is ac = 720', and then the maximum percentage error we can have is.
E=
= 35 , 100 4.S%
720
From this numerical example we can see that the main contribution to the positioning error is given by the offset of the TACHO signal (V2A) , other big contributions are given by the input offset voltage of L292 (VSA) and by the voltage necessary to compensate the dynamic friction of the moto (VeA). This last term is only determined by the motor and can also have greater values.
The error we have calculated is the maximum possible and it happens when all the offsets have the max value with the same sign, i.e. with a probability given by the product of the single probabilities. Considering as an example every offset has a probability of 1% to assume the max value, the probability the error assumes the max value is :
p=( 10-2 )7= 10-14
20/23
300
APPLICATION NOTE
Figure 21.
spe-ed (rpm I
800
600
400
200
/
1/
, (, 'llB
f FTA
( KHz)
v:-
~
2 .66
1.("
w
l.I 17
,33
V
/
a.66
, 2
'8
24 spl'lc'd code
SPEED ACCURACY
If we consider the complete system with L290-L291L292 driving a DC MOTOR with optical encoder, we can note the speed of the motor is not a linear function of the speed digital code appied to L291. The diagram of fig. 21 shows this function and it is evident that the speed increases more than a linear function, i.e. if the speed code doubles, the speed of the motor becomes more than the double. The cause of this non linearity is the differentiator network R4 C4 and R5 C6 (see fig. 22) that has not an ideal behaviour at every frequency.
Figure 22.
I/MA =R5 1
r\ ~~bVMA f I
~l5 I wC6
,
:
~ ,
!, 'J9El.
IVAA
1) VMA = VAA sin cp
cp = tg·1
(J.I R5 C6
(J.I=2nf
2) VMA = VAA sin tg-1 (J.I R5 C6
f = frequency of the signal FTA
This last relation gives the amplitude of the signal VMA ; it is evident there is not a linear function between VMA and (J.I, like VMA = K(J.I and the difference is greater if the product (J.I R5 C6 doesn't respect the disequation (J.I R5 C6« 1., i.e. at high frequencies.
Figure 23.
~, . I " , '', -, /' ' ,
,.
I
,
,
~
,
\
,
_I
_,
,
,
,
VMBSignVAA~~OV -I/MAs1gnVAB= F
'> J96l
The phase angle between VMA and VAA should be 90' and then cp = 0, in our case cp increases with the frequency according to the equation cp = tg-1 w R5C6, and inflences the amplitude of the output signal TACHO. In fig. 23 are shown the waveforms that contribute to generate the TACHO signal. A and B are the signals VAA and VAS in phase with the input signals FTA and FTB. C and D are the signals VMA and VMS: the continue line indicate the ideal case, in fact the phase between VMA and VAA is 90' ; the dotted line is referred to the real case in which the phase is lower than 90'. By adding the two signals shown in E we obtain the TACHO signal, whose expression is :.
Figure 24.
5-5963
VTACHO = VMS. sign VAA - VMA. sign VAS. The signals in E are reffered to the ideal case, the ones in F to the real case. It is possible to demonstrate the mean value of the TACHO signal in the real case is lower than the one we could have with an ideal differentiator network and this explains why in fig. 21 the speed of the motor increases more than a linear funciton. The mean value of the waveforms F is (fig. 24).
21/23 301
APPLICATION NOTE
f It-cp
2K1
3) Vm = - -cp- K1 sin ad a= - It coscp
Since the waveforms E are half sinewaves, the mean value is
2 K1
4)V'm=~
We can conclude that two causes contribute to give a TACHO signal lower than the theoretical one, both due to differentiator network:
a) the amplitude of the signal VMA is lower than VMA = Kro and we can call £1 the relative percentage error.
£1 =
. sin tg·1 ro R5 C6 - ro R5 C6
~~~~-=---=-,---~- 100 ro R5 C6
b) the mean value of.the signals VMA . sign VAS and VMS. sign VAA is lower than the theoretical one because there is a shift in the phase of the signals VMA and VMS. The relative percentage error only due to the shift of the phase is
£2 = (cos cp-1). 100 cp = tg-1ro R5 C6
The total percentage decrease of the TACHO signal is given with a good approximation by the sum of £1 and £2.
Example:
Consider:
f = 3000Hz corresponding to
n=
3000
200
. 60 = 900rpm of the motor if 200 are the tracks/turn
of the encoder £1 = - 2.6% withR5 = 8200
C6 = 15nF
E2 =-2.6%
£3 = £1 + £2 = - 5.2%
From the diagram of fig. 21 we note that at a speed of 900 rpm corresponds· a theoretical speed of 855rpm with a percentage difference of about 5.2%.
SPEED ACCURACY DUE TO THE D/A CONVERTER
To analyse the influence of the DAC precision on the speed accuracy we will refer to the following (fig. 25).
Figure 25.
The value of the output current of the DAC 10 depends on Iref and on the digital code defined by the inputs SC1-SC5, while its direction depends on the value of the SIGN input, the max theoretical value of 10, obtained with SC1-SC510w is:
10M = ± 1316 Iref
The motor will run at a speed corresponding to the following value of the TACHO signal:
31 VTACHO = - 10M . R89 = ±~ Iref . R89
16 This last relation is true if we don't consider the motor friction and the offsets. Consider now the possible friction and the offsets. Consider now the possible spreads we can have in the motor speed due to the DAC. If we call1oM1 the value of the max output current 10 corresponding to the SIGN LOW and 10M2 the one corresponding to the SIGN HIGH, the percentage error we have in the max speed from the positive to the negative value is :
IOM1 + 10M2 . 100
10M Note that we have consider the sum of IOM1 and 10M2 because they have opposite signs. This kind of error is principally due to a different gain of the DAC between the two conditions of the SIGN LOW and HIGH. An equal difference of IOM1 and 10M2, from 10M ( IIoM1 I - 110M I = I 10M2 I - 110M I ) doesn't constitute a speed error because this shift from the theoretical value can be compensated by adjusting the resistor R89 that is formed by a fixed resistor in series with a potentiometer.
22/23
302
~~ ""I SINOGilD©SI'i·IT@~H~~ItO:'iMTIRIS@IlO!D©Nij;
APPLICATION NOTE
With the guaranteed values on the L291 data sheet we can calculate for £4 the max value:
21 !lA
~~. .
·100 = 1.5 %
1.4 mA
Another characteristic of a D/AC is the linearity, that in our case is better than ± 112 LSB. This value is sufficient to guarantee the monotonicity of 10, and then of the speed of the motor, as a function of the input digital code. The precision of ± 1/2 LSB implies a spread of the speed at every configuration of the input code of ± 1.61 % referred to the maximum speed. The max percentage error we can have is then greater at low level speed (±50% at min speed) and has its minimum value at the maximum speed (1.61%).
ACCURACY DUE TO THE ENCODER
The amplitude of the signals FTA and FTB determines the value of the TACHO signal. This amplitude must be constant on the whole range of the frequency, otherwise it is not possible to have a linear function between the TACHO signal and the frequency. The spread of the amplitudes of the two signals FTA and FTB between several encoder can be compensated by adjusting the potentiometer R9 (see fig. 12). The phase between the two signals should be 90' . If there is a constant difference from this value, a constant factor reduction of the TACHO signal results that can be compensated with the potentiometer R9. If the difference from 90' is random, also the reduction of the TACHO signal is random in the same way, and by means of R9 it is possible to compensate only the mean value of that reduction.
23/23
303
APPLICATION NOTE
AN ECONOMIC MOTOR DRIVE WITH VERY FEW COMPONENTS
INTRODUCTION
The main objectives of this design are the economy and circuit simplicity which enable costs to be reduced to a minimum. For this reason the design is particulary suitable for domestic appliances powered by the 220 V AC mains. In this area, characteristics such as low cost, simplicity (and consequently greater reliability) have priority.
With these objectives the choice of the power switch is very important because the complexity of the drive circuit, the number and the power of the auxiliary supplies and the protection networks, depend on its characteristics. These factors lead to the decision to use a HIMOS device (an IGBT) as a power switch. The main characteristics of a HIMOS device are that:
- It switches high current with very low ON resistance, similar to a BJT (bipolar junction transistor). It is very rugged and has very large safe operating areas similar to Power MOSFETs.
- It has high overload current capability.
- It is easy to drive (like Power MOSFETs) conse-
quenUy it is possible to drive it directly by means of popular linear IC.
These characteristics are very suitable for motor drive applications in general and make HIMOS the new way of power switching in this area. An additional factor is that a HIMOS device has a smaller chip area than Power MOSFETs, or bipolar transistors with the same ratings (V(SA) DSS and IDS max}·
CIRCUIT DESCRIPTION
This DC motor drive circuit has a single switch topology and works in current mode; an STHI10N50 HIMOS is used as the power switch. The complete circuit schematic is shown in figure 1. Its main features are as follows: - 300V, 4A DC permanent magnet step down motor drive - Current mode PWM control - Output current adjustable pulse by pulse from 0 to 4A - 220 AC ± 10% supply voltage - 6KHz switching frequency - From 6% to 95% operating duty cycle
Figure 1: Circuit diagram of the HIMOS motor drive
; ( C1
220V
cJ AC
"1SnF ,20V
JRS16K 220}JlFT
f--
TR2.) 2N2222 l.. RS
1Bk ~
R6
"',[9 101>. 01
DC MOTOR
BYTOBPI4QO
8
4
3.3 K RB
TR111/ ~--Jf
nur-f(3.. OZ~ [t C~ 1BV 1I'1onT
P1 22K
R9 100K
7
6
UC3842
-2 1 R10
. I22~0pF
3 5
47A
.£.7
STHI10NSO
1K
-10 nF ~ 02 BYT03400
.~6 .~p R11 18K
TsnF TnF
J :~[380nF
R2 O.22n
JR3390n
AN282/0589
1/4
305
APPLICATION NOTE
The PWM controller IC used is STUC3842. It is a popular, economic eight pin IC widely used for offline and DC to DC converters. STUC3842 provides the features necessary to implement fixed frequency current mode control scheme with a minimal external parts count.
Internally implemented circuits include under voltage lockout featuring start-up current less than 1mA, a precision reference, logic to insure latched operation, a PWM comparator which provides current limit control and a totem pole output stage. It can directly drive the gate of the 500V 10A HIMOS switch STH110N50. The choice of this IC and its current mode working matches the requirements of economy and simplicity of this application.
Fig. 2 - STHI10N50 output characteristics (I step = 6V)
Fig. 3 - STHI20N50 output characteristics
(I step = 6V)
- ·· . -~
· · :11
. '
,-'-
-. · '. .. !!!
liIj /
.-. + ,
-,
~/ ,
~II
f ..s:ii
Ill!!!
- !I"II.
~
I
~.
Ir3 ZIII!:OiI
, ''IIP!.:'!
-- .,.
5
A
500
lIIV
_. I
I I
~l!Ii
·:,C"- '~'"'
· ·
-- 2.5
The motor speed is controlled by the error voltage which is variable from OV to + 5V, and is appliedto pin 2 of the IC by means of R9. This voltage sets a constant current level at which the IC interrupts, pulse by pulse, the current in the power switch: the PWM control is therefore a "current mode" type. The HIMOS switch used is STH110N50, for higher power motors STHI20N50 can be used simply by changing resistors R2 and R6 and free-wheeling diode 01. Figures 2 and 3 show respectively the output characteristics of STHI10N50 and STHI20N50 devices.
An important part of the circuit is the snubber consisting of R3, C9, 02. This accomplishes two functions:
a) it provides power for the UC3842 using the charge current of C9 during the STHI1 ON50 turn-off; infact the IC requires about 20 mA DC as supply current and cannot be biased simply through resistor R1 which should be 10Kohm 10W. Instead, using this active snubber, R1 can be set to a value of 56Kohm 2W in order to apply the start up power to the UC3842.
b) it reduces the energy dissipated in the power switch during turn-off; consequently a smaller heatsink can be used for STHI10N50 giving additional cost reduction.
To insure a continuous power supply to the IC, using the active snubber C9, R3, 02, it is necessary that the capacitor C9 must be completely discharged before turn-off. Because C9 is discharged by means otR3 during the ON phase of the power switch, there is a limit to the minimum ON time which cannot be less than 8 flos, consequently the minimum duty-cycle is 6%.
Considering a peak current.lp = 4A, a fall time tf =
1.5 flos and the minimum ON time of 8 flos, the values of the snubber components are calculated as follows:
C9 = (lp·tf)/2Vcc = 10 nF
R3 = Ton (min/2. C9 =4000hm
The power dissipated across R3 is:
P = 1/2·C9·V2·f=3W
The adoption of this snubber does not affect the efficiency of the circuit during normal operation because its power dissipation is very low and it has the additional benefit of using this energy to supply the IC so reducing the dissipation in the power switch. The extra cost is negligible with respect to the cost of a transformer for supplying the low voltage powerto the IC.
The network of Tr2 and R6 adds a fraction of the ramp oscillator voltage to the "current sense" si-
_2/_4___________________________ ~~~~~~~~:~~~----------------------------
306
APPLICATION NOTE
gnal at pin 3 of the IC (via transistor Tr2 2N2222) to allow slope compensation. Consequently dutycycles as high as 50% can be obtained. Diodes D1 (BYT08PI400) and D2 (BYT03400) are fast recovery types and have been used in order to minimize stresses on the power switch.
MEASUREMENTS ON THE CIRCUIT The DC motor drive was tested in several operating conditions. These were maximum and rated output current and in blocked rotor conditions. The waveforms of the drain voltage, Vos, drain current, 10 , and gate voltage, VG, both with and without the snubber can be seen in figures 5 and 6 respectively.
Fig. 4 - STHI10NSO turn-off with snubber Id= 1A1div, Vds= VSOldiv, Vg=SVldiv
Here you can see the typical behaviour of a HIMOS device at the turn-off when typical features of both Power MOSFET and BJT are involved. The storage phase of the turn-off is dependent on the MOS behaviour as the base collector junction of the PNP transistor is reversed biased: the gate voltage decreases to a point where the Miller effect begins to control the current in the drain and Vos start to rise. The fall time phase can be divided into two parts: the first part is the MOS turn-off and is very fast, the second is slow and starts when the MOS channel is closed and the PNP transistor has an open base turn-off and is dominated by recombination of excess carriers. Therefore the first part of the time is controlled by the gate drive circuit, the second part is dependent on the PNP transistor life-time and gain.
Since the PNPgain increases as Vos increase, the fall time consequently varies with Vos. Therefore, when the snubber is used and the Vos slope is dominated by the capacitance, the fall time region due to the MOS is more evident (figure 6).
Figure 6 shows the turn-on behaviour of the HIMOS: it very fast (t-rise 30ns) and, as with Power MOS devices, is a function of the impedance of the driver circuit and the applied gate Voltage.
Fig. 6 - STHI10NSO turn-on Id= 1Aldiv, Vds=SOVldiv
Fig. 5 - STHI10NSO turn-off without snubber Id= 1A1div, Vds= SOVldiv, Vg= SVldiv
Figure 7 shows the behaviour in the case of a blocked rotor and with the current control set at the maximum 4A. This condition was simulated, as worst case, with and inductance of 300uH and a resistan-
ce of 1 n: the current does not exceed 6A. The over-
current of 2A, with respect the control current of 4A, is due to the delay introduced by the network
_____________________________ ~~~~~~?¥~~~©~ ___________________________3_/4
307
APPLICATION NOTE
of R7, C7 of about 2 fls. This filter network is necessary to suppress the leading edge spikes on the IC current sense comparator input.
Fig. 7 - Blocked rotor' beheaviour Id= Vds= 50Vldiv, Vg = 5Vldiv
;;;;;
3 10.1 U
1A/div,
~'I' IDa·· · .. .... 'P'"!: ~'"
.... .... ' .. , ....
n
,!'!I.J
...'II"I!. !'!iIi
~
1.1
I Il~
:' III:~ ..... I I
~t;f~ .... .... .... ..~., .... .... I'~" .... ....
· Omlt! Ei~u ~ l~ 50 ns
The losses in the circuit, for the maximum rating of each component are approximately as follows: P(R1)=2W, P(R3)=3W, P(R2)=3W, P(D1)=4W, P(Tr1)=7W.
CONCLUSION
A 300V 4A DC permanent magnet single quadrant motor drive was developed with objectives of maximum circuit simplicity and economy, Consequently a current mode PWM control with a popular IC was adopted and an STHI1 ONSO HIMOS (an IGBT) was used.
The low drive energy requirement due to the high input impedance of the HIMOS allows substantial cost reduction in the control circuit. Conductivity modulation of the drain produces a low ON resistance, an essential feature to work with high peak currents in the switching element. The ruggedness, due to the excellent safe operating areas, is especially relevant for motor control applications.
The easy drive, high current handling and excellent ruggedness make HIMOS the new way of power switching in the motor control field.
r u _4/4_ _ _ _ _ _ _ _ _ _ _
SGS-THOMSON _ _ _ _ _ _ _ _ _ _ __
·/ . " Ii:llJ©Iiil@~'L~©lIliil@,;;]O©§
308
APPLICATION NOTE
VERSATILE AND COST EFFECTIVE INDUCTION MOTOR DRIVE WITH DIGITAL THREE PHASE GENERATION
B. Maurice/JM. Bourgeois/B. Saby
INTRODUCTION
The three phase induction motor is a simple design, rugged, maintenance-free which appears in home appliances requiring cost effective solutions. For speed control of these motors, a frequency variation of the Inverter output voltage is required. The voltage/frequency ratio must be maintained constant, so control of these motors normally require complex control circuitry for the generation of the balanced three phase sine wave outputs.
l!sually the generation of the three phase PWM signals may be controlled by a dedicated circuit, such as the SGS-THOMSON L6234 which is driven by a separate microcontroller. This solution is optimum while performance prevails over cost.
The solution demonstrated in this application note is a simplified solution using a standard ST9 microcontroller which includes large on-chip ROM memory and an internal Direct Memory Access (DMA) controller. This combination reduces the need of dedicated ICs (hardware being replaced by software), and allows over 50% of the CPU time to perform control, environmental and supervision tasks.
A practical solution to quantize three phase sine-
waves, and to create the corresponding DMA table is shown allowing motor voltage and motor frequency to be chosen independently. A dead time avoiding cross conduction through the bridge is also created by software. Very low acoustic noise operation can be achieved despite a switching frequency below 10kHz, due to a shifting of the switching instants leading to a virtual doubling of switching frequency.
Each of .the six digital outputs of the ST9 sets directly the state of the six power MOSFETs (or IGBTs) of the bridge via an insulated interface. This interface is described in the second part of this note. The fully isolated pulse controlled gate driver requires no floating auxiliary supply, meets safety standards and achieves a large dV/dt immunity.
Figure 1 shows how to generate a three phase sine wave by modulation of pulse width. This modulation is often obtained with a special dedicated IC controlled by a MCU (above).
Using a MCU having large memory integrated on the chip combined with DMA, spares the use of dedicated IC (below). Hardware is replaced by software. The sine waves are directly synthesized by the MCU.
AN424/0292
1/14
309
APPLICATION NOTE Figure 1. Three Phase PWM Generation Techniques
Vee
MCU
+ DC line
dedicated IC
Vee
ST9 MCU with DMA
VR001508
+ Deline
'-------,.v,----"/
Pulse con trolled driver
VR001509
_ _ _ _ _ _ _ _ _ __ _~1_4_ _ _ _ _ _ _ _ _ _ ~~~tn&~~~91
310
APPLICATION NOTE
DIGITAL CONTROL OF POWER SWITCHES
In this proposed solution, the ST9 microcontroller controls simultaneously the ON- and OFF- states of the six power switches of the inverter bridge. All these instantaneous ON-OFF states are stored in internal memory (ROM) and are sequentially transferred (every 5s for example) to six bits of a parallel output port by DMA(see Figure 2). The voltage level 0-5V of each output bit drives directly the gate interfaces of the six power switches.
All data corresponding to the switching duty cycle values is permanently stored in ROM and generates the quantized three phase sine waves. A dead time between adjacent Power switches is also stored, avoiding cross-conduction through the power bridge. The motor frequency and motor voltage are also stored independently.
The major part of the ROM is occupied by this permanent data, used 'to generate, step by step, the three phase sine-waves. This data is grouped in several tables (patterns), constituting series of bytes that have to be sequentially output on the parallel output port. A full scrolling of each pattern corresponds to a complete switching basic cycle of the six power switches. This is repeated the necessary number of times to complete the step duration of sine wave. The following pattern will then be scrolled to realize the fo'!owing step.
This direct sequentiai"tran$fer from memory to output port is performed by DMA [2), and is self operating. The central unit only works when the last byte of one pattern appears, the program then deter-
mines whether the same pattern must be scrolled again, or if another new pattern has to be scrolled.
All patterns needed for an application, as well as the program managing their scrolling order and their number of repetitions, are to be created and stored in ROM.
MOTOR DRIVE CONFIGURATION
Microcontrolier
The ST9036 microcontroller from the ST9 family with 16k-byte of ROM or EPROM memory [1), of which only one output port and one multifunction timer are used for PWM generation. Six bits of its output port are gathered in pairs, one pair for every bridge leg (phases: u,v,w). The two bits remaining free can be used, for example, either to control two other power switches (i.e for heat control in a washer), or to generate a synchronized signal to perform measurement of V/I phase.
The ST9 microcontroller is able to manage two further functions:
a) Slow operations for motor and environment controls, such as timing of sequential operations, speed control, safety supervision tasks, etc. (These are not detailed in this application note).
b) Faster operations for real time management of the states of the power switches for PWM generation.
All others functionalities of the ST9036 remain available, such as other I/O ports, Timers, Analog/Digital converters and all interrupt functions.
Figure 2. DMA Transfer to control power switches
__ ._ ST--_9. M......_I.C.__R.__ OC.·..O·_-N---T-_R._O......L,---LER
Microcontroller MEMORY
~ Patterns --~'-
#4
#3
#2
#l
""" 1j7DMA 010101
010001 001111000011
gHg~g
tI· me
101010
101010
101010
1010LO
101010
101010
001010
OllOOO
011001
0D1l1l0o0n1
~
010001 011001 011001 011001 011000 001010 101010 101010 101010 l01010 101010 101010 001010 011000 011001
5U~g~
010001 010101
Voltages on output port
5
0
5 .'ug"
2 0 c
0
5
X not used
X
+ Deline VR001519
- - - - - - - - - - - - - - - ~~~~;~~~~~~~
3/14
311
APPLICATION NOTE Figure 3. Driver for one Bridge Leg
Vee
bit Nbr 0
From Microcon troll er Output Port
bit Nbr 1
Tl
Phose U
SECONDARY
with
T2
Short circuit I sense Protection
VR001510
In the practical example described in the following sections, ST9 is not heavily occupied by these real time operations:
Using DMA is similar to slowing down the ST9 and engages only 35-40% of the CPU time.
- Speed control (frequency variation) needs only few instruction lines but no memory space. The memory space is mainly used to store necessary data to generate six various three phase voltages supplying the motor (1 k-byte for each voltage).
Drivers For Power Switches
The driver interfaces the ST9 output port to the gate of the power switches.
it converts the output level (5V) to the required gate-source voltage level (15V) of IGBT or Power-MOSFET.
- it provides a galvanic isolation.
- it protects against current surges and short circuits.
It is constituted by six independent circuits for the six power switches. Each is a pulse controlled driver [4] including: (see Figure 3)
- a primary circuit to create a calibrated Pulse with short duration.
- a small pulse transformer. (DIL molded package)
- a floating secondary circuit operating without any auxiliary supply and including the autonomous short circuit protection.
The primary circuit differentiates the logic level input signal. The positive and negative calibrated output pulses (±15V/0.5Ils) correspond to the switch-
on/switch-off command. The primary circuit output stage is a full bridge having a low output impedance in order to obtain short rise times and high amplitude current pulses. The pulse transformer can be small. A ferrite core of 6.3mm diameter with 10 turns is sufficient as it has to sustain 15V for O.5lls. In this application, three core transformers are' housed in the same standard or SMD package [3]. The secondary circuit needs no supply and uses the input gate capacitor of the Power-MOSFET or IGBT like an R/S memory. latch. The required energy is limited to charge and discharge the input gate capacitor. During the OFF-state, a low impedance is maintained across the gate-source of the Power switch, avoiding any reconduction due to externally applied dV/dt.
Figure 4. Transformer Core Size vs 16 pin OIL
VROO1511
-4/1-4 - - - - - - - - - - - - "~ "'11 SliIGilo©Soo@-r1n~rHn(iO;"[lMOO@S;i!OJO©iN!i5 - - - - - - - - - - - - - -
312
APPLICATION NOTE
In several applications, when isolation between the power and control sections is not mandatory, the low side driver can be a simple non-insulated driver. Nevertheless, the fully isolated solution performs high dV/dt immunity and meets insulation standards.
DC/AC Inverter
For this function, a three-phase bridge with six switches (Power-M08FETs or IGBTs) is used. (Figure 1). The two switches of each bridge leg are opposite phase controlled. A dead time, avoiding simultaneous conduction, is generated directly by the 8T9036 microcontroller.
Sine wave generation: (Figure 5)
The voltage on middle point of "u-phase" bridge leg is given by: Vu = Voc.ou ou = u-phase duty cycle
ton hi = "ON state" duration of high side switch
0= ton hilTs Ts = switching period Vuw= Vu - Vw Vuw = phase to phase motor
voltage
If ou is sinusoidal modulated, the average voltage on half bridge middle point describes sinusoidal wave form centered to Voc/2. To avoid DC components in the motor, each phase voltage has to be symmetrical compared to Voc/2.
Motor voltage value
Motor voltage is maximal when the duty cycle modulation varies from 0% to 100% (modulation depth: K=1 00%) Motor voltage is minimal (nil) when modulation depth K=O; 0 does not vary and is equal to 50% (Figure 5b)
Sine wave frequency variation
This is obtained by varying the frequency of the duty' cycle modulation.
CREATING TABLES OF DATA
The variable speed drive of induction motors requires generating three voltage sine waves and control of their amplitude, phase and frequency. The first step is to digitize the three phase system in order to create all the necessary data to be stored into the ROM of the 8T9 microcontroller.
Figure 5. Sine Wave Generation at the output of one bridge leg
a. Modulation depth 60%, duty cycle 20 to 80%
b. Constant duty cycle
Ts
r-----J
Vu
0=80%
ton hi
0=20%
P"",:D:1 g\floooBib[U---8:;;: ~::
p""",:D:1 8---il---ildl:ft:EJ 0 EJ8-il
P"",:D:11f1ftEHbil ~ JkR-f1nt
pb"",:D:1 8\n-n-Tfo-n--BnnnBSD% VDC VR001518
--~-----------
b~ .."'!§ SiiICI,©SWi-l1J~~HllOi©1fMlB@SjlOJD(Ni;§
5/14 --------------
313
APPLICATION NOTE
Fundamental period quantification
The fundamental period of motor voltage is divided into 24 "segments"; (each segment equals 15· of arc). This gives a good sine wave accuracy in ma~y applications. During each "segment" the voltage IS a percentage of the DC line voltage, given by duty cycle (0). For example, the duty cycle must be 55% during the segment from 165· to 180· for phase U (Figure 6).
Creating the duty cycle table
The second step is to establish a table giving, for each segment, the duty cycle value (0) for each of the three phases. In fact 01, 03, 05 are duty cycle values for each high-side switch (T1, T3, T5). The low side switches are in the opposite states and
their duty cycie value is complementary to 100%. This entire table defines exactly the three-phase sine wave system during one period (To) and for one motor voltage. (Figure 7) These table values respect phase balance and avoid neutral currents. To achieve these conditions it must be ensured that:
a) on each line, the sum of the three duty cycle values is constant (equal to 150%).
b) The duty cycle has a symmetrical value either side of 50%. In practice the quantized values have to be chosen close to the mathematical value of sinus for only a quarter of the period, then symmetrically repeated respecting the condition (a).
This duty cycle table is not stored in ROM. It, only defines the necessary data to .create the patterns. One line of this table defines one pattern (see following section).
Figure 6. The fundamental period divided into "segments"
Deline Voltage
50
150
250
segment _ !-- TO/24
of period I
fundamental period TO
VR001513
6/14
~ ~itltl~~911 - - - - - - - - - - - - - -
314
APPLICATION NOTE
Figure 7 . Duty cycle table defining data to create patterns VPHASE = O.6XVLINE
Pattern
U
V
W
#
01%
03%
05%
80
40
30
2
80
45
25
3
75
55
20
4
70
60
20
5
60
70
20
6
55
75
20
7
45
80
25
8
40
80
30
9
30
80
40
10
25
80
45
11
20
75
55
12
20
70
60
13
20
60
70
14
20
55
75
15
25
45
80
16
30
40
80
17
40
30
80
18
45
25
80
19
55
20
75
20
60
20
70
21
70
20
60
22
75
20
55
23
80
25
45
24
80
30
40
One Pattern
010101 010101 1J10001 011001 011001 011001 011000 001010 101010 101010 101010 101010 101010 101010 001010 011000 011001 011001 011001 010001 010101 010101 010101 010001 011001 011001 OU001 011000 001010
101010 101010 101010 101010 101010 101010 001010 011000 011001 OU001 011001 010001 010101
Pattern definition
A pattern is a succession of bytes stored in memory. Each bit (1 ;O) of these bytes gives the instantaneous state (ON;OFF) of each of the 6 six power switches (Figures 7&9). Pattern contains number of bytes necessary to define one entire basic switching cycle.
A particular pattern has to be created for each segment of the sine wave period. All these patterns are stored in the ST9036 ROM.
For example (Figure 8), a pattern contains sequence of 42 bytes defining one basic switching
cycle. The switching period Ts, shared into 42 units of times, gives a good sensibility of duty cycle adjustment of about 2.5% (1/42th). This time unit corresponds to the rhythm of the DMA timer and its duration is chosen as a multiple of the ST9 microcontroller clock period (O.25fLS).
In this example, one unit of time equals 4.75fLS in order to have a pattern scrolling time or switching
period Ts = 200fLS. This corresponds to 5kHz of
switching frequency.
Two dead times (one time unit each) at every state change of adjacent switches avoid cross conduction of the bridge leg.
315
APPLICATION NOTE Figure 8. Example of switching cycle for transistor Tl
Vu (% of DC line)
100%.-______________________________________- .
+ DC line
I/V
I/V/
//V
/ /1/
//V/
/ /1/ /
/ /V//7
/ /
/7
30 ,L ,/.. /.. I' / /
// / /
/ // / /
/// / /
// ////
o /// ////
1 3 5 7 9).: 11 13 15 17 19 21 23
= Segment #9 : 6 30%
-
Vu
Repetition of 5 basic switching cycles
.......- - o u
Vu
saSiC switching cycle (;
T1 Gate
I
+
ON
I
OFF
1 1 1 1 1 1 11 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 /
I
I
T
unit of time
ton
Sequence of 42 logic states
· t
Ts : Basic switching period including 42 units of time
VR001520
_8/_1_4 _______________________ l:1,f~~~~~~~9©~ __________________________
316
Figure 9. Pattern table
to output buffer
APPLICATION NOTE
dead time
time
one pattern
Phose W {
a
Phase V {
00
o~
aa 00
Phose U {
00
o~
a
00
nb. timer
I<-N<")'<tlf) I
a
underflow I
I I
T6 I
T5 I
T4 I
T3 I
.,T2 I I
If)
a
N
If)
a
N
<")
42 time units
If)
O~NI
<")
'<t'<t'<tl
I
I I
I
I I I
VR001521
Figure 9: One pattern is an elementary table grouping all necessary bits to define the basic switching cycle of every six inverter switches. Bytes are sequentially read by DMA, and transferred to the output buffer. The resulting switching cycles shown on the bottom of the figure gives the following duty cycles:
-phase U: 01 (T1) = 100%; 02 (T2) = 100% - 01
-phase V: 03 (T3) = 20%; 04 (T4) = 100% - 03 -phase W: 05 (T5) = 30%; 06 (T6) = 100% - 05
MOTOR VOLTAGE CONTROL
One table of duty cycle defines the 24 stored patterns (set of patterns) containing information to one AC motor voltage. As an example, the peak value of phase voltage generated by the table given on Figure 7 is equal to 60% of VDC line. It is necessary to create a set of patterns for each of the needed motor voltage.
The motor voltage can be controlled independently of the frequency. This voltage depends on the set
of pallern which the DMA is reading. By storing within ROM and reading different set of patterns, the voltage across the motor can be changed and shaped. In this example, a set of patterns includes 24 patterns of 42 bytes each = 1008 bytes.
Figure 10 shows 01 duty cycle of the T1 switch for various values of motor Voltage. On the right side the chart gives the corresponding values of 03 and 05. Each line of these charts defines a pattern. These values respect the phase balance and avoid current in neutral line. The useful RMS voltage
r%; across motor phases is given by: VRMS= 21·K.-"\j .VDCline
The K factor corresponds to modulation depth of the duty cycle (0) as shown on examples (a,b,c).
a: K= 1.0 when duty cycle varies from 0% to 100%
b: K= 0.6 when duty cycle varies from 20% to 80%
c: K= 0.2 when duty cycle varies from 40% to 60%
- - - - - - - - - - - - - - "...,1 r.:::-=
Sl:C\cS©o-oTm~Hm©OlIMOOS@~OO©N:0
9/14 --------------
317
APPLICATION NOTE
Figure 10.01 Duty Cycle of T1 Switch
61 100%
90 80 70 60 a 50 40 30 20 10
61 100%
90 80 70 60 b 50 40 30 20 10
Pattern
81
83
85
= Vumax VLINE
/1
100
30
20
2
95
45
10
3
90
55
5
4
80
70
0
5
70
80
0
6
55
90
5
7
45
95
10
8
30
100
20
9
20
100
30
---------------- ----- ---
Set of
10 11
10 5
95 90
45 55
Patterns 12
0
80
70
13
0
70
80
14
5
55
90
15
10
45
95
16
20
30
100
17
30
20
100
1~~rA n~~
18
45
10
95
19
55
5
90
20
70
0
80
21
80
0
70
22
90
5
55
11 13 15 17 19 21 23
23
95
10
45
VR001522
24
100
20
30
= Vumax O.6VUNE
1
80
40
30
2
80
45
25
3
75
55
20
4
70
60
20
5
60
70
20
6
55
75
20
7
45
80
25
One Pattern
8 9
40
80
30
30
80
40
10
25
80
45
------------------------
11
20
75
55
12
20
70
60
13
20
60
70
14
20
55
75
15
25
45
80
16
3D
40.
80
17
40.
30
80
18
45
25
80
19
55
20
75
20
60
20
70.
21
70
20
60
22
75
20
55
11 13 15 17 19 21 23
23
80
25
45
VR001523
24
80.
30.
40.
61 100%
90 80 70 60 c 50 40 30 20 10
= Vumax O.2VUNE
1
60
45
45
2
60
48
42
3
58
52
40.
4
55
55
40.
5
55
55
40
6
52
58
40
7
48
60
42
8
45
60
45
Set of
9 10.
45 42
60 60
45 48
Patter
11
40.
58
52
-------------------- ----
ns
12 13
40. 40
55 55
55 55
14
40
52
58
15
42
48
60.
16
45
45
60.
17
45
45
60
18
48
42
60
19
52
40
58
20.
55
40
55
21
55
40
55
22
58
40
52
23
60.
42
48
11 13 15 17 19 21 23
24
60.
45
45
VRQ01524
10/14 318
APPLICATION NOTE
MOTOR FREQUENCY CONTROL
Motor frequency is controlled via duration of the fundamental period To.
The shortest duration of the period (the highest frequency) is reached when each segment of this period corresponds to only one reading of the corresponding pattern. In our example (Figure 11) the pattern reading duration equals 2001!s, and with 24 segments.
When each segment corresponds to two readings of pattern, the fundamental period is twice as long. Thus the frequency (motor speed) can be controlled step by step whether the pattern is read once or several times. Consequently when starting from the highest frequency, it is possible to have discrete submultiples of frequency.
F = FolN N = number of times of patterns being read
The speed resolution is low for high motor speed, but high for low motor speed. So, to perform the
speed control by software, it is sufficient to give the number of times the pattern is to be read. For example, when repeating 20 times the same pattern the following results are obtained:
4.751!s = time unit
42 = number of time units per pattern
20 = number of patterns (or switching cycle) reading per segment
24 = number of segments per fundamental period
This gives a fundamental frequency of 10.4Hz
Another way to adjust motor speed by software is to change the DMA timer period. That is equivalent to modifying the "time unit" duration. The reduction of time unit duration is limited by the highest consumption of CPU time to be accepted and the shortest permissible dead time is according to power switches used.
By combining these two methods, pattern repetition and timer variation, it is possible to perform quasicontinuous variation of motor speed.
Figure 11. Fundamental Frequency variation a. To = 200x24=4800 ms Fo=208Hz b. To = 200x2x24=9600ms Fo=104Hz
100% , -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---,
90
n. patterns per segment of period
80 70
I
60
50
40
30
20
10
100%.,-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---,
90
2n. patterns per segment of period
80 70
1
60
50
40
30
20
10
19 21 23
VROO1525
__________________________ ~~i~@~~~~~4 ________________________1_1_/1_4
319
APPLICATION NOTE
DEPHASING SWITCHING INSTANTS
When creating the pattern, the instant of switching can be chosen specifically for each bridge leg. For example it is possible to simultaneously turn-on all the high side switches (Tl, T3, T5) and stop them when respectively each duty cycle is reached (Figure 12a).
Through other ways for the same duty cycle the ON-state is centered atthe middle of pattern (Figure 12b).
Various other possibilities can be chosen to create the pattern. The acoustic noise of the motor will depend on this choice. For example the pattern shown in Figure 12c gives a large current ripple and very noisy motor,while, on the contrary, Figure 12b gives a noiseless motor according to small current ripple (shown at 20ms/div; 2A1div).
When the three high side switches or the three low side switches are simultaneously ON or simultaneously OFF, no energy is transmitted into the motor, which is freewheeling. Another possibility is to choose simultaneously the OFF-state rather than the ON state simultaneously as shown Figure 12e to compare with Figure 12b. In this case two swit-
ches of one bridge-leg are not switched and switching losses are reduced.
Figure 12 shows how various possibilities can be chosen for pattern creation. Current ripple and acoustic noise of motor will depend on this choice.
On the right side, motor current with:
noiseless motor according to small current ripple.
noisy motor according to large current ripple.
As the energy is transmitted when switches are not in the same state, the rule to create a pattern is to maximize the instants where the switches are in the same state and simultaneously shift the switching instants.
All these methods can be used to obtain very low acoustic noise operation in spite of a switching frequency below 10kHz.
Without reducing the time unit, it is possible to increase the acoustic frequency by sharing in two equal parts each duty cycle time (0=60% => 0=30%+30%) . The switching frequency is doubled and acoustic noise is close to the inaudible region and becomes very low (Figure 12d)
Figure 12. Pattern options affecting ripple and acoustic noise
T5 _ _ _ _ _ _ _ _ _ _ __
T3 _ _ _ _ _ _ _ _ _ __ a
Tl _ _ _ _ _ _ _ _ _ __
Switching instants T5 _ _ _ _ _ _ _ _'--_ __
T3 _ _ _--'_ _ _ _ _ _ _ _ _ __ b
Tl _ _ _ _ _ _ _ _ _ _"--_
II " Switching instantsT5 _ _ _ _ _ _ _ _ _ _ __
T3 _ _ _ _ _ _ _ _ __ _
Tl _ _ _ _ _ _ _ _ _ _ _ __
T5 _ _ _ _ _ _ _ _---'_ _ _ __
T3_~_ _ _ _ _ _ _ _ _BL_ _
d Tl---'_ _ _ _---'_ _ _ _L-
T5 _ _ _ _ _ _ _ _ _ _ __ T3 ______ ______ _______
~- ~-
T1 _____. .______~_ _ _L__
VROA1526
12/14 320
APPLICATION NOTE
EXPERIMENTAL EXAMPLES
Figure 13 shows an example of generated three phase PWM signals on microcontroller outputs. It represents three control signals for T1, T3, T5. The set of pattern corresponds to a modulation depth of 100% as shown on table Figure 10a. The phase angle between each phase is 120%.
Figure 14 shows current measured in motor phase (20ms/div, 2A1div). a) obtained with set of pattern shown on Figure 10b, and repeated twenty time, f= 10Hz b) patterns are repeated twice, f=1 OOHz.
The used set of pattern (at 60%) of Figure 10b, combined with doubly of switching instants (Figure 12d), gives a well defined sine wave.
Very little ripple of current and doubling switching frequency give a noiseless motor operation.
The motor is speeded up by repeating patterns only twice (Figure 14b). Simultaneously the motor voltage is increased by using set of pattern (Figure 10a) having modulation depth of 100%.
Figure 13. Three microcontroller outputs: 5ms/div,5V/div
T5
controll[I[III~.1111 ,.
1111_111[1111111' ,
T3 control
I
5ms/sqr
J
5V/sqr
Figure 14. Current measured in motor phase
--------------
A"'I! ~ S~D:C<;SOO-@~mc~O©UOMOQ;S@:OD©\N\)
13/14 --------------
321
APPLICATION NOTE
SUMMARY
For large volume applications such as washing machines, air conditioning or cooling pump motor drives, cost optimization is a key issue. The solution to drive induction motor presented in this paper simplifies conventional digital solution. Using a ST9 microcontroller with Direct Memory Access and fast data transfer, replaces dedicated ICs by software or more precisely by data stored in microcontroller memory. The proposed solution is very versatile because a standard microcontroller, the ST9036, can be programmed for various applications, only the software will has to be adapted.
This note presents methods to generate data in order to shift the switching instants of inverter switches. This allows to reduce motor acoustic noise in spite of· switching frequency being below 10kHz, and to minimize motor and converter losses.
The described pulse controlled gate driver uses standard components and small enough core transformers that can be fitted into a Surface Mounting Package. This way offers a cheap fully galvanic insulation when required.
REFERENCES
[1].SH family high performance 8/16 bit MCU SGS-THOMSON Microelectronics - Info pack
[2].3-phase motor drive I,Ising the ST9 multi-function timer and DMA B. SABY - SGS-THOMSON Microelectronics - Application Note.
APPENDIX MICROCONTROLLER WITH DMA
The feature of microcontroller with DMA (direct Memory Access) consists in having a possibility of direct access between microcontroller memory and its on-chip peripherals. Moreover, one of the parallel 1/0 ports can be coupled with the timer's DMA channel, allowing fast data transfers between memory and this 1/0 port with minimum CPU overhead. Data transfers are scheduled by the timer.
The only task of the Microcontroller software is to specify which pattern is to be read by the DMA channel at a given time in order to reproduce the three-phase sinewaves, as described in the previous sections. After a complete pattern transfer, the Micro-controller CPU is interrupted (DMA End of block interrupt) and the DMA should start to read the next pattern.
In order to achieve high speed continuous transfers without stringent response time requirements for this End of block interrupt, a "swap mode" is used: while a pattern is read by the DMA channel, the subsequent pattern can be prepared in advance; so, once the last byte ofthe pattern is read, the DMA automatically switches to the new pattern while the old one can be updated during the DMA End of block interrupt routine.
First tests show that the DMA operation in swap mode, as described hereabove, accounts for 3540% of the total available CPU time of the Microcontroller. Therefore, thanks to its processing power, the Microcontroller can easily perform any control and supervision task in addition to this DMA-driven PWM generation.
[3]. Data-book of F.E.E 39270 Orgelet France
[4].New Isolated Gate Drive for Power MOSFET and IGBT
JM. BOURGEOIS - E.P.E' Firenzell Sept 1991
.[5].External DMA mode: 1/0 data transfer synchronized by tirner
P. GUILLEMIN - SGS-THOMSON Microelectronics ~Application Note AN418
[6].Environment design rules of MOSFET in medium Power application
B. MAURICE - P.C.I.M. Munich/G 1989 - Proceedings book
___________________________ _14_1_14________________________ ~~~~~~~:9~
322
APPLICATION NOTE
MOTOR CONTROL DESIGN USING VERTICAL SMART POWER ICs
by R. Lelor, M. Melilo, A. Galluzzo
ABSTRACT
Readily available smart power devices can greatly simplify a power designer's design task by releasing him from the problems of designing high current control circuits. Whilst making this aspect of the design transparent to the user, smart power ICs only require a standard logic compatible input signal. These features are illustrated by practical examples of motor control using two different circuit configurations, a single switch and a full bridge circuit, working in continuous and in switched current modes. The paper demonstrates that the problems of motor control (stalled motor, overload, etc..) are simply and successfully resolved by using smart power devices.
The devices contain an integrated vertical current flow power MOSFET, high side gate drive, maximum current control, protection circuits and a diagnostic status output. The input and output control functions directly interface to a microprocessor allowing comprehensive control and fault diagnosis of the condition of the load, i.e. short circuit, open load and overload. Designs safe-guarding the circuit against extreme working conditions are considered, such as a power supply disconnection with an inductive load. Finally, future developments in smart power
Ie design for motor control are reviewed.
AN481/0492
1/10
323
APPLICATION NOTE
1.0 INTRODUCTION
In many application areas such as robotics, process control, automotive actuators, etc, the DC motor control board is, in effect, a power peripheral device of a micro-processor or micro-controller system.
Attaining high current, low power dissipation and effective diagnostic feedback with these peripheral boards can be a problem.
Using smart power ICs helps to overcome these difficulties and, additionally, provides a bonl)s: compact designs due to the reduced circuit size as a result of the integration.
The technology, one of three Vertical Intelligent Power (VIPowerTM) technologies, that includes, on a single silicon chip, a vertical current flow power MOSFET and analog and logic circuits, has allowed different families of devices to be produced that satisfy a wide range of applications.
Integrating a sense-FET on to the smart power ICs allows very high current, equal to that of discrete power MOSFET devices, to be controlled, resolving the problems of high current sensing even at high switching frequencies.
This leads to the possibility of making a wide range of interesting devices in a variety of packages with high power dissipation, some of which can be surface mounted.
The integration of analog and logic circuits that perform the various protection, diagnostic and current control functions, permit the deSign of a system where the peripheral circuit protects itself and the motor.
The micro-processor is able to handle the motor being aware of its working conditions.
2.0 MAXIMUM CURRENT LIMITATION AND CONTROL.
Current sense together with current limiting circuits are necessary in motor driving circuits, both for protection problems in overload conditions and in motor torque control. The delay, the accuracy and the working mode of these circuits can be varied according to the application requirements and with the working mode (switching or continuous).
2.1 CURRENT SENSING.
The following disadvantages of the standard current sense circuits using a sense resistor or a current transformer highlight the advantages of using an integrated current sense circuit with a sense-FET: - there is power dissipation (Pd=RsensI2) - a high peak voltage is generated across
the stray inductance due to the high switching speed (V peak = Lstray di/dt). - the noise tolerance of the control circuit is adversely affected due to capacitive coupling. Figure 1 shows that the sense-FET works as a current mirror so only a part of the current flows through the sense resistor, hence the power dissipation in the sense resistor is very low. In addition to this the integrated device requires less wiring. As a result there is less stray inductance. This, in turn, means it is possible to design a current sense circuit for very high switching speeds. If linear and accurate current control is not necessary, other methods of current sensing, such as detecting the saturation voltage or monitoring the junction temperature of the power sensing element, can be successfully employed.
- - 2110 - - - - - - - - - - - ' " ~~~~1tl~~:oo~!:~ - - - - - - - - - - - -
324
APPLICATION NOTE
Figure 2 shows the generic block diagram of the SGS-THOMSON Microelectronics high side intelligent switch. Figure 3 shows that when a smart power IC temperature sense circuitry protects the device to prevent its destruction in overcurrent conditions, the over-temperature circuit turns the integrated power switch off at a safe operating temperature (140°C). This type of protection depends on the ability of the device to dissipate heat.
2.2 CURRENT LIMITING WITH VIPower
o
Vsens.
_IL_ 01000 Isens.
o
0
Lp VERY LOW
/
THANKS TO INTEGRATION
Vsens 0 Rsens.·ILll000 + Lp.sens'd(lL/l000)/dl
Figure 1 - Integrated current sense using a sense-FET and ON state equivalent circuit.
The current limiting can be achieved using linear or chopper techniques. Both solutions allow the current control to be relative to an external command and/or to internal parameters (internal references, junction temperature, voltage drop across the power transistor during the on state, etc.) as shown in figure 4 and 5.
3.0 DRIVING HIGH SIDE N-CHANNEL POWER MOSFETs
A Power MOSFET used in high side configuration requires a voltage greater than the power rail, high enough to turn on the device in full saturation. This supply can have different configurations depending on the working conditions. There are different methods of generating this gate drive voltage. The charge pump technique can be used which is suitable for the continuous working mode or there is the bootstrap circuit which is suitable for switching applications. These techniques or a combination of them can be integrated into the control circuit of the VIPower ICs, but some integration problems must be considered.
Vee
~ ~~""U i () '"'"' ".:·.
I: =~[.---~~~R"E~O"N,,,L;T;~-J-
5 LOAD
[I; STATUS
TEMP.
[i]
GROUND
Figure 2 - Block diagram of a VIPower Ie showing
the main sense circuits.
Inn r, 1 lload
Tj~~~;~:g
n n status 11-----.
[
Figure 3 - Overload working mode of the VIPower intelligent switch, VN05
---------------------------~~~~~~~::~
3/10
---------------------------
325
APPLICATION NOTE
They are: the silicon area is proportional to capacitance value.
number of pins must be limited to reduce the cost of the package.This means that the design of the drive circuit must be the best compromise between silicon area, number of pins and in the application under consideration that can have the following requirements:
continuous working mode, switching working mode, or both.
low switching losses (fast turn-on).
low voltage applications typically 6 to 36V.
complete turn-on of the power transistor in all working conditions.
Figure 6 shows the schematic of an integrated charge pump circuit that ensures sufficient gate-source voltage even if power supply is 5V or less. This circuit multiplies the power supply voltage by three. The integrated charge pump can only supply a few milliamperes and is therefore limited to use in continuous mode applications (i.e. solid state relays) because it needs a few hundred microseconds to generate enough charge to turn-on a Power MOSFET. For switching applications, an external bootstrap capacitor can be connected to an internal control circuit, and, to ensure 100% duty cycle, both the charge pump and the bootstrap methods can be used (figure 7). Figure 8 shows the turn-on switching
behaviour of a VIPower Ie with cr: Power
MOSFET output using a bootstrap circuit to generate the gate drive voltage. The switching time can be optimized in order to match low switching dissipation and electromagnetic compatibility.
Vee
r---------------
II i..............
I
0I1...i....... ....1
I
¢r.... ·!
I L........1
L-------------IG-N-D --~
Figure 4 - Continuous current control in a VIPower IC
Vee
1----------------
I
.-------------r-----,I G NO
Figure 5 - Switched current control in a VIPower IC
Vee
Ichrage = C*V~F
Figure 6 - Integrated charge pump that multiplies Vee by 3.
- - - - - - - - - - - - - 4/10
--
-
-
-
-
-
-
-
-
-
-
-
l
i
f
i
~~~~m~::~~~
326
APPLICATION NOTE
Vee ----~~---r-----
,(!]
,(!]
y-----'
:.. . Y-\...../ ......-:-. r·... .......... .... ·~-r
,.,..~-(~.~ ..--l,r~-.·,"" .r-J._y-t-..~"....~"l'-l'i._~
I
I
j
Figure 7 - Bootstrap and charge pump in a VIPower IC, allowing switching and continuous mode.
Figure 8 - Switching waveforms of output voltage
and current in a VIPower IC V =5V/div, I =5Ndiv,
t = 1 us/div
4.0 FAULT DIAGNOSTIC.
The ability to process the diagnostic information is very important in the design of fault tolerant systems. In a motor drive circuit, this process can be complicated due to the changing working conditions of the motor and to the large variety of fault conditions, stalled motor, overload, open circuit due to the brush deterioration, etc. The control circuit of a VIPower Ie must be able to recognize these fault conditions and others, such as power supply failure, and differentiate between various fault conditions using a minimum of output pins and to be able to filter out false alarm signals. This feature is achieved by the integration of a digital delay network and logic circuit that can, for example, operate as follows: If a short circuit exists, when the device is turned on the VIPower IC internally limits the current and, after 33ms, it turns-off and the diagnostic output goes low.
If an open load exists (lout < 50ma), when the device is turned on, then the diagnostic output goes low after 2ms.
If a fault condition appears during normal operation, the diagnostic output goes low immediately and the device turns-off.
If the device turns-off due to a fault condition, the control circuit must be reset by taking the input low.
These functions make it possible to discriminate between a false alarm signal given when the motor starts up and there is an in rush current or due to the inductive behaviour of the motor which can cause a low current for few Ils.
By exploiting these features, it is possible to create a program able to interact with the VIPower IC and to identify the nature of the fault condition; this is illustrated in figure 9. A tri-state output can be used if only two fault conditions are to be identified.
------------- ~ ~~~~~~~r::oo~©~ -------------5/10 327
APPLICATION NOTE
RESET
==-1 ~ INPUT _ I ' " " " 'r " " ' -- - - -- - _I
,/
, ,,
SHORTC.
:
OUTPUTU
CURREN
:
, ,
"
, , 'OPB:N C.
DIAG. OUTPUT
, 33ms
'2ms'
Figure 9 - Timing diagram of the diagnostic system in the VM201 intelligent switch and flow chart of a
subroutine able to differentiate fault conditions.
5.0 MOTOR DRIVE USING TWO VERTICAL SMART POWER ICs IN A FULL BRIDGE CIRCUIT.
5.1 CIRCUIT DESCRIPTION.
The circuit in figure 10 shows how a very simple motor drive for an automotive electric window lift can be made using two high side smart power solid state relays and two discrete power MOSFETs in a full bridge configuration. The SGS-THOMSON VIPower ICs used, VN05, have a very low RDS(on) (150 mQ), maximum current limiting at 15A, undervoltage detection at 6.5V, thermal shut down (150°C), over-temperature and open circuit diagnostic output and a digital filter that makes the device able to distinguish between real and false fault conditions. The VM201, a power MOSFET plus the control circuitry integrated on to one silicon chip, provides all these features in a 5 pin HEPTAWATT
package. Each half of the bridge is comprised of one VM201 and one standard power MOSFET. The motor control board is CMOS and TIL compatible. This is possible because of the CMOSniL compatibility of the VIPower IC input and output and to the use of a low side CMOS buffer driver. The free-wheel diodes are the intrinsic diodes of the discrete and integrated power MOSFETs. No power sense components are needed as the VIPower IC has an internal sense-FET. In this application, the purpose of the diagnostic output (open COllector), is to detect the stalled motor condition to protect the window at its extremes of travel and any accidental obstruction, eg an arm or dog!
6/10
-------------------------- ~~~~~~~::~~--------------------------
328
APPLICATION NOTE
This condition is characterised by an overload current caused by the stalled motor. The ability of self decision of the VIPower IC and of interfacing software as shown in the previous section , 4, enables the circuit to filter a false stalled motor condition and to safeguard the power devices from over temperature stress. Open load fault diagnOSis can be used to recognize deterioration of the motor brushes.
5.2 BEHAVIOUR OF THE VIPower DEVICES.
The low ROS(on) (1 OOmn), allows the devices to work at a high ambient temperature. The worst case blockage of the window creates a current in the motor of up to 7A 8A causing on-state power dissipation in the VIPower IC of 10W - 13W at a junction
temperature, Tj = 100°C. This condition
allows the devices to operate under the worst case conditions with a Rth junction-ambient < 8°C/W, and with Tambient = 50°C. This avoids over-temperature detection during normal operation. The figure 11 shows the behaviour of the current in the motor and of the diagnostic output during turn-on and turn-off. This behaviour is due to the overload current in the motor when the window reaches its limits of movement or is physically obstructed.
6.1 POWER SUPPLY DISCONNECTION DURING OPERATION.
In some applications, such as process controls, the main power supply protection system can, under certain conditions, disconnect the power supply during operation. If the loads are motors or inductive loads, the collapsing magnetic field of the
inductance can drive the output pin negative. The control circuit of the IC is isolated from the power MOSFET output section by an isolating junction which forms a well in the silicon surface; the control circuitry is constructed in this well. If the MOSFET cannot provide the current flow and the junction of the control circuit insulation is forward biased, this condition can prove critical due to the activation of parasitic components, and cause a current to flow though the control pins of the VIPower IC that can damage or disturb the microprocessor circuits. The simple solution shown in figure 12, shows a clamping diode that enables the output power-MOSFET to conduct the energy stored in the inductance. Figure 13 shows the VIPower IC behaviour during a power supply disconnection; however the negative voltage spike on the diagnostic output can cause an incorrect feedback signal which can be avoided by using an RIC filter.
7.0 FUTURE DEVELOPMENT OF MOTOR DRIVE ICs.
The future trends of the VIPower technology, using a vertical current flow power MOSFET, are influenced by the needs in specific applications to drastically reduce the dimension of the high current motor control boards. Surface mounting packages are being developed to satisfy this requirement. They will allow mounting in hybrid circuits without the need for sophisticated die attach technology. These packages will have outlines that conform to those of existing packages, together with thermal resistance characteristics suitable for power devices.
7/10
- - - - - - - - - - - - D~ :.". '!IJ
Sii:1IJirSr!:·ITl@~H~~!:O1i'lMiI@iSi!lOrr!:Nil\
-----------329
APPLICATION NOTE
Figure 10 - Motor drive for a window lift with two VM201 intelligent switches
Figure 11 - The VM201 during the in rush current at turn-on of the left window and at turn-off due to a stalled condition. INPUT=5V/div, DIAG=5V/div, OUTPUT CURRENT=5A1div, t=100ms/div
~VCC 5V
Figure 12 - Protection from accidental power supply disconnection
Figure 13 - Waveforms during power supply
disconnection.
IN=5V/div,
DIAG=5V/div, OUT=1 OV/div,
lout=2A1div
7.1 CONFIGURATIONS OF NEW LOW VOLTAGE MOTOR DRIVE ICs.
To give some concrete example of future ICs, typically power tool applications with a single switch are considered. For full bridge applications, where bidirectional rotation is required, a double high side driver with two external low side discrete
power MOSFETs can be employed, figure 14. A full bridge cannot be integrated in one chip using only VIPower technology because the substrate of the IC forms a common drain to all the integrated power MOSFETs. However this can be resolved by using both
8/10
--------------------------~~~~;~~~:~~ --------------------------
330
APPLICATION NOTE Vee
Figure 14 - Chip of a double side driver
Duty cycle (%) 100+---------------~~~·I
oL---~----~----L---~----~~
-40 . 0
40
80
120
160
Tj(JC)
Figure 16 - Duty cycle reduction vs Tj in the circuit of Fig. 15.
the VIPower and the BCD (Bipolar CMOS DMOS) technologies. Figures 15 and 17 show examples of possible single switch mode motor control configurations integrated in VIPower technology: Figure 15: The micro-processor sets the maximum duty cycle and the VIPower IC internally limits the operating junction temperature; when the temperature reaches the maximum value, the temperature sense circuit operates in a feed-back loop and
Figure 15 - Limitation of the maximum CHIP temperature using a temperature feedback.
reduces the duty cycle (figure 16) in order to maintain the junction temperature at a safe value; This feature allows the motor to work in overload conditions safeguarding the power ICs from the stress of overtemperature. Figure 17: Speed and maximum torque control of the motor can be achieved using a feed-back control circuit for the current and the motor speed, the latter employing a frequency to voltage converter; this gives the possibility of precise control including motor acceleration control. All these applications see the VIPower IC as a peripheral device of a micro-processor with the ability to make decisions; The VIPower IC, however, is self protected from overcurrent, over-temperature, etc, and is able to exercise rapid control over the process.
8.0 CONCLUSION.
Several problems are solved by the integration of a power MOSFET with appropriate control circuitry on one silicon chip. It achieves:
high current capability in a compact package
l:ii ~~~~m&~:O!~~ ------------------9/10 331
APPLICATION NOTE
---~
I
1 ~BOOTSHIAP
OVERLOAD 1'1-----<..u-
I
DIAG. - - - - - - - - - ----------~~D-J
Figure 17 -Torque and/or speed motor control implementation
no power dissipation in the sensing element using a sense-FET.
no interference of the control circuit by stray induction in the external wiring.
the ability to drive a power device from a logic circuit.
diagnostic control and information. The internal protection, the ruggedness and the wide range of working frequency make the VIPower IC able to drive motors and inductive loads under all working conditions without external protection. The CMOSmL compatibility of the input and the output signals directly interface with a micro-processor and allow it to be used in many applications such as autol'notive actuators, process control, and robotics.
REFERENCES
1 Understanding Sensfet. Warren Schultz Motorola application note.
2 Lossless Current SenSing with Sensfet Enhances Motor Drive Design.
Warren Schultz. PCIM, April 1986.
3 Current Sensing Mosfet Simplify Current Mode Control
Warren Schultz - Jade Alberkrack
Power Technics Magazine, May 1986.
4 Drive Techniques for High Side
N-Channel MosFet
Warren Schultz. PCIM, June 1987
5 A New Monolithic Double High Side
Driver.
Michele Zisa, Microelectronics
SGS-THOMSON
PCIM EUROPE, November 1989.
6 PC Based Development System Cuts DeSign of Smart Power Ie Application. Thomas L. Hopkins, SGS-THOMSON
Microelectronics PCIM EUROPE, November 1990.
10/10
r== SCS.11tOMSON _ _ _ _ _ _ _ _ _ __
- - - - - - - - - - - - - ..., / l>Jo!:lfJ@rn~rn!:vll@IIlO!:$
332
DRIVERS AND IPS
333
APPLICATION NOTE
HOW THE TDE1897/8 BEHAVE IN EXTREME OVERLOAD CONDITIONS
by U. Moriconi
The circuit designer may be interested and get some insight on how the TDE189718 behave, if extreme overload conditions are forced on to them. Although the conditions may range outside the limits of the datasheet guarantieed performances, erroneous connections during an installation phase may occur and momentarily create such conditions. The performed tests confirm the extreme ruggedness of these devices and their ability to survive the accidental overload.
The TDE1897/8 is a monolithic Intelligent Power Switch (IPS) in High Side Configuration and BCD tecnology (see fig.1 ),dedicated to drive resistive and inductive load such as lamps, Relays, electro-valves, etc. An internal voltage clamping diode to +Vs creates, in inductive load, a fast demagnetization path without external components.
Suitable for industrial application, it operates in the 18 to 35V supply range delivering output current up to 500mA . In typical application it can
Figure 1 : Block Diagram
drive up to 1 - 1.5H load coil (48 to 60Q typical associated resistance).
OVERLOAD CONDITIONS
To investigate the behaviour of TDE1897/8 in extreme inductive overload conditions, that may occur when too big a load is connected to the device output, tests were performed, in bias conditions that lead the device to function out of the datasheet operatives and rated limits.
tIN RIN lSSK
-IN
\N453/0392
SWITCHING
INTERFACE
01
tUS
RSC.
'---i>I-t---o OUTPUT
1 - - - 0 GNO
02 OUT STATUS
1/5
335
APPLICATION NOTE
Test Conditions (referred to the circuit of fig. 2)
Vs = +24V; 10 = Internal Limited; Tamb = 25°C; L = 1.4H (non saturating); RI = 12Q; Vi = 2V
(Vih)(#); Tj = from 0Lim-Hy to 0Lim and above (*) (#) The input signal asks lor a permanent "on" state.
n "Lim & Hy = thresholds of intervention and histeresis of the
internal thermal protection circuit.
Figure 2: Inductive Load Equivalent Circuit and Demagnetization Cycle Waveforms
OVERLOAD OPERATION
Due to. the internal limitation (Isc), the output cur-
rent (10) is .not limited by the load (VslRI = 2A; Isc
:,; 1.5A) but by the device itself. As soon as the current reaches Isc, the I.P.S. goes out of the minimum resistance state and increases its volt-
age drop so that 10 = Ics. The silicon temperature
of the D.U.T. increases rapidly up to the thermal protection threshold value (0Lim) and such protection tries to cut-off the output DMOS. The turnoff of the output forces the demagnetization cycle, that discharges the energy of the inductive load (to Vs) through the device.
The higher clamped current value (Isc) will produce, during the demagnetization, more stress conditions because of both:
l' I s
..::. V s
45V
10
R
lOAD L-----......:::"I--_t
Uout I----~-tUS-UCl
UOS
UCl
us L -_ _1 - - L_ _~~-+t
1192rOct89?-84
- The higher energy in the magnetic load -The higher peak power (1)
During the "on" state the power (Pdon) on the D.U.T (see the 225msec. interval in fig.3) is defined by the 10 (Isc) and RI values. The chip temperature rapidly increases and reaches the upper thermal protection threshold value (0Lim); at that moment the protection is triggered on, inducing the attempt of switch-off, the associated demagnetization phase (some 50msec. after the 225m sec. interval), and finally the switch-off.
The D.U.T. starts then to cool down staying in the off-state, until the chip temperature goes down to lower thermal threshold value (0Lim-Hy). When lower limit (0Lim-Hy) value is underpassed, the thermal protection circuit withdraws itself, the chip resumes its normal functions and restarts another cycle. In facts its input has been connected permanently to a voltage level of more than 2V, meaning a continuos request for conduction. A new overload cycle is so started, and a periodic repetition of: · load charging
· current limitation
· overtemperature and demagnetization
· cooling down in the off state.
It can be noted that, for given thermal parameters (Zth, Thermal protection levels and hysteresis), differences in Pdon affect only the "TON" and "TOFF" duration and ratio of such periodic repetition.
The Minidip device (TDE1897BDP) suffers heavier stress conditions than the SI P9 option (TDE1898ASP) because of the package differences (Minidip vs. SIP9 involves higher thermal gradients).
Note(1) During the demagnetization phase , the power dissipated inside the I.P.S. Chip is: lo(t) · VCl -Io(t) decays to zero from Isc. -VCl is set by the I.P.S. itself to about 50V
2-/-5--------------------------- ~·~~~~~~~:oo?~ -----------------------------
336
APPLICATION NOTE
SOME MEASUREMENTS AND CALCULATIONS
For a typical TDE1897BDP sample, thats is in Minidip package, (see Fig. 3) in "thermal" periodic repetition, the current (self-limited region) is limited to 1.1 A and the voltage across the D.U.T. is = 10.8V for 225msec. "on" time. The energy dissipated on the D.U.T. in the demagnetization cycle is = 1.28 J . (**) The repetition cycle rate is = 0.27Hz(t = 3.7sec.).
Pdon (average) = 1.1A ·10.8V· 0.225sed3.7s = 0.72W
Pdem. (average) = 1.28J . 0.27cycles/s = 0.346W
Adding the small power dissipated for operating quiescent current and for lo(t)A2*RoN in loadcharging region, the total power p(tot)= 1.1 W is a realistic value.
Minidip (on the test-socket) Rthj-amb is about 85 °C/W that leads the average temperature in the hot region of the chip) to 115-120°C (the chip isn't homogeneous in temperature. Higher temperatures are reached, during dissipation, in the area of the output DMOS).
Figure 3: TDE1897BDP Output Voltage (CH2) and Output Current (CH1) vs. Time in Thermal Periodic Repetition.
CH1 = 200mAIdiv
CH2 = 10Vldiv
t = 50msldiv
CHI9"
Figure 4: TDE1897BDP Output Current and Temperature in the Test Point, vs. Time.
CH1 = 200mNdiv
CH2gncL
CH2 = 50°Cldiv
t = 50msldiv
--------------
.~ ...,/li!lSllG©OSO@-~T~~H©~OOOM@CIS'lOllN©$
3/5
--------------
337
APPLICATION NOTE
For a typical TDE1898ASP sample, that is in SIP9 package, ( see Fig. 5 ) in "thermal" periodic repetition, the current (self limited region) is limited to 1.15A and the voltage across the D.U.T. is = 10.2V for 300m sec. "on" time. The energy dissipated on the D.U.T. in the demagnetization
cycle is = 1.38J r*). The repetition cycle rate =
0.52Hz (t = 1.92sec.).
Pdon (average) = 1.15A· 10.2V . 0.3s/1.92s = 1.83W
Pdem (average) = 1.38J ·0.522 cycles/s = 0.72W
The total power = 2.BW
The Rth j·amb for SIP9 "on socket" is about 50 °CIW that leads the average temperature on the hot region of the chip to 150°C.
Note(**) The formula to use is : W = VCL-URi'{lo-[(VcL-Vs)/R,]-log[1 +(lo-R,)/(VcL-Vs)]}
-It is also interesting to see ( Fig. 4 and B ) the temperature versus time ( mesaured monitoring the forward voltage drop of an internal diode placed 1.5mm from. the center of the power DMOS ) in a region of the chip at lower average temperature.
On the "hot" region, the estimated temperature is quite higher (up to + BO°C. on the peak temperature, during the demagnetization phase)
However no failure could be observed on the cheked devices also reducing the R, value down to 8Q, on some Minidip samples.
Minidip
TDE1898DP TDE1897BDP
SIP9 ORDERING NUMBERS:
TDE1898ASP
S020 TDE1898FP
Figure 5: TDE1898ASP Output Voltage (CH2) and Output Current (CHI) vs Time in Thermal Periodic Repetition
CH1 = 200mAidiv
CH2 =10Vidiv
~ri·~··· ,
t = 100msidiv
,
l
I I
CH2gn
/ 300ms
\
1-1
CHlgn
, , , ,
4-/5----------------------------~~~~;~~~:~~n -----------------------------
338
APPLICATION NOTE
Figure 6: TDE1898ASP Output Current and Test Point Temperature vs. Time
CH1 = 200mNdiv
CH2 = 50"C/div
t = 100ms/div
/
Tmin" 120"C
_ _ _- - , CHIgnq.+--~
Tmax" 165"C
/
CONCLUSION
The complex protection sistem of TDE1897/8 proves effective also in extreme overloadconditions. Althougth the behaviour of such devices in those conditions cannot be guaranteed due to the high temperatures that accelerate the intrinsic
ageing mechanism, the test performed show that there is a lot of margin beyond the guaranteed limits of the device datasheet. These test also show that it is very likely that such devices will
survive to non permanent overloads like the ones possible in practice during the installation or modification of an industrial control system.
----------------------------- ~~~~~~~~:oo~~ ------------------------5-/5 339
APPLICATION NOTE
SWITCH-MODE DRIVERS FOR SOLENOID DRIVING
This design guide describes the operation and applications of the L294 and L295 switch-mode solenoid drivers. Integrating control circuitry and power stage on the same chip, these devices replace complex discrete circuits, bringing space and cost savings.
Many applications, particularly in computer peripherals, require a high power, fast solenoid driver circuit. In the past these circuits have been realised with discrete components because the high powers required precluded the use of monolithic technology.
SGS-THOMSON Microelectronics has overcome this problem with a new high power bipolar technology that uses an innovative implanted isolation technique. This technology is used to fabricate two switch mode solenoid driver chips, the L294 and L295, which both incorporate high power output stages and control circuitry. Both circuits are designed for efficient switmode operation and are mounted in Multiwatt ® plastic package.
THE L294 SOLENOID DRIVER
The L294 is designed for solenoid driving applications where both very high speed and high current are essential; needle and hammer driving in printer mechanisms, for example. It delivers 4 A with supply voltages up to 46 V, handling effective powers up to 180 W.
Shown in figure 1, the L294 is controlled by a TTL level logic input and the peak load current is programmed by a reference voltage applied to the pin labelled Vi.
Internal switchmode control circuitry regulates the solenoid current by turning the output stage on and off repeatedly to keep the load current between the
Figure 1 : Internal Block Diagram of the L294 Switch mode Solenoid Driver.
02
AN243/1288
1/11
341
APPLICATION NOTE
programmed peak value, Ip, and a lower limit of 0.9 Ip.
Other features of the L294 include thermal shutdown, output short circuit protection, overdriving protection and a latched diagnostic output. This output indicates fault conditions such as a short circuit solenoid. CIRCUIT OPERATION
In most applications the L294 is used with a fixed reference voltage (Vi) and the solenoid is controlled by negative-going pulses on the ENABLE input. When the ENABLE input is active (low level), the output stage is enabled and the load current rises as shown in figure 2.
The load current is sensed by an external resistor (Rs) in the emitter of the sink stage. Through the op amp and transconductance amplifier (OTA), the sensed voltage charges an external RC network (R1 C1) which determines the switching characteris~ tics of the device.
Figure 2 : Output Current Waveforms of the L294.
The Output Current in regulated by
Switching between a Peak Value, Ip, and
a lower Limit of 0.9 Ip.
.
OUTPUT CURRENT
-+_____ _ Vi~ _~________
ENABLE
5-588811
Figure 3 : Two Level Current Control can be implemented by switching Vi .between two Values.
OUTPUT CURRENT
-+l------'------~
LEVEL
5 - 5890
2/11 342
APPLICATION NOTE
The voltage across this RC network is compared with the voltage Vi, which fixes the output peak current. When the current has reached the programmed peak value this comparator switches, turning off the output source stage and closing a switch which reduces the voltage on the non-inverting input to 0.9 Vi. The load current now recirculates in 01. The voltage on pin 8 falls with a time constant determined by R1 C1 or the load characteristics, whichever is the longest. In other word. R1 C1 sets the minimum recirculation time constant.
When the voltage across R1 C1 has fallen to the 0.9 Vi threshold the comparator switches on, turning the output stage back on and restoring the Vi comparison threshold.
The output source stage is switched in this way, regulating the load current, until the ENABLE input goes high again. At this point the output stage is disabled - both source and sink - and the load current recirculates through 01 and 02 to ensure a fast decay. By varying the voltage Vi the peak load current can be programmed to any value in the range 0.6 A to 4 A. This feature can be exploited to implement two-level current control if the fixed reference is replaced by a switched reference as shown in figure 3.
PROTECTION
To protect the load and the L294 from overdriving an on-time limiter inhibits the output stage independently of the ENABLE input if the duration of the input pulse exceeds a period set by the external capacitor C2 (figure 4). This circuit is reset by taking the ENABLE input high. Theon-time limiter can be disabled by grounding pin 3.
Protection against overheating is incorporated in the form of a thermal shutdown circuit which disables the output stage when the junction temperature exceeds 150"C. The circuit restarts when the temperature has fallen about 20"C.
The L294 is also protected against short circuits to ground, to supply and across the load. Triggered when the source stage current exceed 5 A or the sink stage current exceed 1 V/Rs, the short circuit protection block inhibits the output stage and sets a flip flop which is supplied by a separate supply volt-
age Vss. This flip flop is connected to the diagnos-
tic output and signals that all is not well - a shorted solenoid, for example. The diagnostic flip flop is reset by removing the supply Vs. A LED can be connected to the diagnostic output as shown in figure 5. If the diagnostic function is not re-
quired the Vss supply can be omitted. The short circuit protection, however, still functions, even without VSS. Figure 4 : On-time Limiter Waveforms. After a Peri-
od defined by C2 the Output is disabled regardless of the State of ENABLE, protecting against overdriving.
PIN 3 VOLTAGE
USING THE L294 The basic application circuit for the L294 is shown in figure 5 ; a suggested layout is given in figure 6. The circuit is complete except for the source of Vi. In most cases this will be provided by a simple resistive divider dimensioned to set the desired peak current. With a 0.20 sense resistor as shown, the L294 has a transconductance of 1AN for Vi above 600 mV. The device will not work with Vi less than 450 mV and operation is not guaranteed for Vi between 450 mV and 600 mV. The on-time limiter delay - set by C2- is approximately 120000 x C2. Pin 3 must be grounded if the on-time limiter isn't used. Switching frequency depends partly on the timing network R1 C1 and partly on the load characteristics. R1 C1 determines the minimum value of t1 (see figure 2), which is given by t1 ;:: 0.1 x R1 C1. C1 must be in the range 2.7 - 10 nF to ensure stability of the amplifierOTA. R1 must be at least 10 kO to give sufficient gain for OTA. The standard application circuit of figure 5 has a switching frequency of about 10 kHz. The recirculation diodes should be fast types and rated at 3A (01) and 1A (02). If the full4A capability of the L294 is not used these can be reduced.
3/11 343
APPLICATION NOTE
Figure 5 : Standard Solenoid driving Application of the L294. Pin 7 must be connected to a Suitable Reference Voltage to set the Peak Current.
'5V
.V s
Vj
ENABLE
"1...r
The peak current, IOEx, (see figure 7a) is found
from:
Vz
R2
IOEX =
5
Rs
R1 + R2
Vz is the zener voltage. The zener and R5 can be omitted if a regulated 5 V supply is available for point A.
The holding current, Ihold, is found from:
Ihold =
Vz
(R2 II R4)
1
. . --~-~
5
Rs
R1 + (R2 II R4)
The duration of the peak is determined by R3C1 and is increased by raising R3 or C1.
Typical component values are listed in the table below:
5-531114
IOEX=4A IHOLO=1A
R1
D1 : 3A Fast Diode D2: 1A Fast Diode
trr:<;200ns
R2 R3
R4
RS
A high initial peak and low holding current can be
D1
obtained with the circuit shown in figure 7a. This
D2
example supplies a current peak for about 10 ms.
C1
10 kQ 47 kQ 150 kQ 2.7 kQ 0.2 Q (1 W)
3A O.S A 0.2 fIF
IOEX = 2.5 A IHo LO = 0.5 A
10 kQ 27 kQ 150 kQ 1.5 kQ 0.27 Q (O.S W) 1.S A O.S A 0.2 fIF
Figure 6 : Suggested printed Circuit Board layout for the Application Circuit of figure 5.
4/11 344
APPLICATION NOTE
Figure 7a : Application Circuit for two Level Current Control. This Circuit generates a high Peak Current for a Period determined by R3C1 then a lower holding Current.
5-5891/2
Figure 7b : Output Current Waveform obtained with the Circuit of fig. 7a.
5/11
345
APPLICATION NOTE
Figure 8 : Pin Functions\of the L294.
N°
Function
1 Solenoid Supply Voltage Vs (12-46 V)
2 Output, Source Stage
3
On-time Limiter Time Constant. A capacitor to ground sets delay period (120 000 x C2 seconds).
On-time limiter is disabled by grounding this pin.
4
Supply Input (5 V) for Diagnostic Flip Flop.
5
Diagnostic Output, Open Collector. Signals intervention of latched short circuit protection. Reset by
removing pin 1 supply.
6 Ground.
7
Vi Reference Input. Peak output current is proportional to Vi. Transconductance is 1 AN for Rs = 0.2 Q
and Vi ;:, 600 mV.
8
Timing. A parallel RC network from this pin to ground sets the minimum recirculation time constant.
The capacitor must be 2.7-10 nF to ensure stability.
The resistor must be greater than 10 kQ.
9
ENABLE. TTL-compatible logic input that controls the solenoid current. The solenoid is driven when this
input is at a low level. The on-time limiter overrides enable.
10 Connection for Load Current Sense Resistor.
11 Output, Sink Stage
THE L295 DUAL SWITCHMODE DRIVER
The L295 is a dual switch mode solenoid driver which .handles up to 2.5 A per channel at voltages up to 46 V - a total effective power handling of 220 W. Compared to the L294 it offers a more economical solation when 2.5 A is sufficient because there are two drivers per chip. Like the L294 it features switch mode regulation of the output current and thermal shutdown. Additionally it has a separate logic supply input so that the logic can be run at a lower voltage, reducing dissipation.
Intended for inductive load driving, the L295 is particularly suitable for solenoids and stepper motors. One L295 drives two solenoids and two L295s can drive the four phases at a unipolar steppermotor or the two phases of a bipolar stepper motor in bridge configuration.
Each channel of the L295 is controlled by a TTLlevel digital input and the peak load current is programmed, independently for ea9h channel, by a voltage reference input. A chip enable input is also provided to disable both channels together.
INSIDE THE L295
Internally the L295 (figure 9) bears little resemblance to the L294. Looking at channel one, when the VIN1 input goes high the output transistors 01 and 02 are switched on (the enable input EN is assumed to be active, i.e. low). The current in the load then rises exporientially, as shown in figure 10, until
the voltage across the external sense resistor RS1 reaches the current program reference voltage Vref1.
The comparator COMP1 switches and sets the flip flop FF1 which turns off the source transistor 01. The load current now recirculates through 02-02RS1 and decays.
What happens next is determined by the oscillator components Rand C on pin 9. If these components are present the flip flop is reset by the next clock pulse before the current decays very far. The output stage is therefore turned on again and the load current rises.
When it reaches the peak value COMP1 switches again, setting the flip flop and disabling the output stage. This process is repeated, regulating the load current until Vin1 goes low. The output stage is then disabled and the current falls off rapidly, recirculating through 01 and 02 (figure 10).
If the oscillator components are omitted and pin 9 grounded the current simply decays slowly until Vin1 goes low. The output stage is then disabled and the load current recirculates through 01 and 02. This case is illustrated by the waveforms of figure 11. Note that in this case the peak current. level is controlled.
Unlike the L294, the switching frequency of the current regulation loop is determined by the oscillator components Rand C (the L294 is also affected by the load). Typically, the switching frequency will be
6/11 346
APPLICATION NOTE
10-30 kHz. Another difference between the two devices is that the L294 gives a constant ripple, the L295 does not.
TWO LEVEL CONTROL Since the peak load current is programmed by the reference voltage (for each channel), two level cur-
rent control can be obtained by switching between two reference Voltages. A high V,ef is selected initially to give a high initial current peak. Then, after a suitable interval, V,ef is reduced to give the lower holding current (figure 12). Two level current control is very useful for solenoids which require a high initial current peak for fast actuation.
Figure 9 : Internal Block Diagram of the L295 Dual Switch mode Driver.
G i~I S~D©GUIS@I·l1I!H.rnO©1MrWJS@IOllDN©$
7/11
347
APPLICATION NOTE
Figure 10 : Waveforms illustrating Normal Operation of the L295.
Figure 11 : When the Oscillator Components are omitted and Pin 9 grounded the L295 delivers a simple Current Peak to the Load.
II I I r 1I r
II I
II II I
'0
1 1 1 ' 2 '31 '415 Iltnl
Ii : :; : I ;
. ,
. ,
. ,
5 - S8 62
Figure 12 : Two Level Current Control is obtained by switching V,ef between two Values.
10
Vi .~_N_I~~~____-,__________~____--. I
t- -
Vref
I
--I~'---.------~----------~----~I
I
:J -01 t -1I 1------1
I
·
, I 'i-SSG1
I I
:I I'
I
I:
II I I I I
: : : : I I I
"
II I I
n n I I
8/11
348
APPLICATION NOTE
L295 APPLICATION HINTS
The basic application circuit of the L295 is shown in figure 14. A suitable layout is given in figure 15.
Suitable values for the oscillator components, Rand C, can be found from the nomogram, figure 16. The value for the reference voltages depends on the desired peak current and is equal to IpRs ; it must be in the range 0.2 V to 2 V.
If the V,ef inputs are left open circuit the L295 assumes an internal default value of 2.5 V giving a peak current of 2.5/Rs amperes.
The L295 can also be used to drive unipolar stepper motors. For a four phase motor two devices are used, connected as shown in figure 17. This circuit
provides switch mode regulation of the load current with a chopper rate of about 25 kHz. The enable inputs (EN, connected together) enable/disable the whole circuit and the channel inputs Vinl ... Vin4 are driven by a suitable translator circuit. Phases 1 and 2 must not be energised together because they share the same sense resistor. The same applies to channels 3 and 4. However, ' two phase on' drive is stili possible for bifilar motors where phases one and two represent one winding and 3 & 4 the other, and also for variable reluctance motors with phase 1 adjacent to phase 3 etc.
Two L295s could also be used to drive a bipolar stepper motor in systems where a translator already exists.
Figure 13 : Pin Functions of the L295.
N°
Function
1
Solenoid Supply Voltage, Vs (12-46 V).
2
Channel one Output, Source Stage.
3
Channel one Output, Sink Stage.
4
RSI. Sense Resistor Connection, Channel one.
5
Vref1 . A voltage on this pin sets peak current of channel one. If this pin is left open or connected to Vss
a default Vref of 2.5 V is assumed. An externally applied Vref must be in the range 0.2 to 2 V.
6
Vin1. Logic Input for Channel one. Driver is active when Vin1 is high and EN low.
7
EN. Chip Enable (active low). When high both channels are disabled.
8
Ground.
9
Oscillator Timing Network. This pin is grounded to produce a single peak.
10 Vss. Logic supply voltage, internally regulated. (4.75-10 V).
11 Vin2. Logic Input for Channel two. Driver is active when Vin2 is high and EN low.
12 Vref2 . Voltage input, controls peak current of channel two. If left open or connected Vs an internal 2.5 V reference is assumed. An externally applied Vref must be in the range 0.2 to 2 V.
13 Rs 2. Sense Resistor Connection, Channel two.
14 Channel two Output, Sink Stage.
15 Channel two Output, Source Stage.
9/11 349
APPLICATION NOTE Figure 14: Typical pplication Circuit of the L295. R1 L1 and R2 L2 are solenoids.
+Vss
+Vs
01
5-58601, 01 : 3A Fast Diode trr 5 200ns 02: 1A Fast Diode
Figure 15: Suggested printed Circuit Board layout for the Circuit of figure 14.
C5_0171
10/11
350
APPLICATION NOTE Figure 16: Nomogram for the Selection of Values for the Oscillator components. Re.
Figure 17: Two L295s, connected as shown, can be used to drive a four Phase Unipolar Stepper Motor.
10 Vi'o-----l
V; 20-----l11
EN U""""t----,
L295 (, )
14
Vi 3
11
Vi 4
L295 ( 2)
01.03.05,07 :lAFAST DIODES 02 ,04,D6,Og: 2AFAST DIODES
5-5&92
11/11 351
APPLICATION NOTE
FULLY PROTECTED HIGH VOLTAGE INTERFACE FOR ELECTRONIC IGNITION
INTRODUCTION
It is well known that an electronic car ignition system must be able to generate and supply the high energy discharge to the spark plugs, firing the petrol/air mixture at a precise point in each piston cycle. This job is performed by means of an high energy coil, its driver stage and the most suitable controller; an example is shown in fig. 1.
In the most recent car ignition systems the coil current loading signal is controlled by a microproces-
Figure 1 : Car Ignition System.
By S. PALARA ; M. PAPARO ; R. PELLICANO
sor that can also optimize the ignition timing. This ensures the correct spark at every speed for all environmental conditions.
The engine efficiency is so optimized ensuring the minimum toxic exhaust gas emission.
The high voltage necessary to generate the spark is obtained by charging the primary winding of the ignition coil with a controlled energy, i.e. a controlled current.
-
[BATTERY [ ______ +
SUPPLY
IHTERfACE AIIIl COHTROl
POWER ACTUATOR
RDC ( 0. 1Q I
1
1
1. UBm·
HI&H UIIlTA&E AItJ SUPPLY
AN292/0189
1/6
353
APPLICATION NOTE
At the firing point this current is suddenly interrupted transferring the stored energy to the secondary winding and produces output voltage in excess of 20KV and therefore the spark.
The fig. 1 power actuator must also limitthe current to a max of 10A and the voltage on the primary to a maximum of about 400V.
The voltage clamp avoids any damage to the power actuator: if the spark plug, for example, is disconnected, the energy stored in the coil is transferred back to the power actuator.
The device described in this paper realizes these power actuator functions with a very innovative integrated single chip solution.
THE VIPOWER M1 TECHNOLOGY
The VIPower M1 structure shown in fig. 2 combines a vertical current flow NPN power transistor and a
Figure 2 : VIPower Technology Vertical Structure.
low voltage junction isolated I.C. on the same sili-
con substrate.
.
This is realized inside a diffused p-type well that takes the place of a reverse-biased p-substrate of conventionallCs and must be connected to the most negative supply.
As in a standard discrete BJT, the first epitaxial layer thickness and resistivity set the Vceo and the ruggedness of the high voltage device, the second epi growth fixes the features of the low voltage components (up to 100V VCBO).
The maximum voltage the power device can withstand is neverthless also dependent on the maximum field strentgh at the silicon surface and on the n+/p--well parasitic diode breakdown Voltage.
N- EPI
Nt SUBSTRATE
2/6 354
APPLICATION NOTE
The high voltage termination ofthe integrated circuit is achieved by a p-diffused resistor in spiral from .connected between the substrate (power darlington collector) and ground.
DEVICE CHARACTERISTICS The device realizes the ignition, power actuator subsystem of fig. 1.
Figure 3 : Device Block Diagram.
In the block diagram of fig. 3 the power Darlington with its driver and input stage, the current limit, voltage clamp circuitry and the overvoltage protection are shown.
VBAH .--------p-------~---()
HVC
DRIVER RB
Rs
GND
S(-0261/1
A TTUCMOS compatible input signal coming from a logic interface, like a microprocessor, determines the turn on of the power darlington integrated in the chip.
The darlington collector current charges the coil Iinearly as long as a set level is reached, typically
6A ± 3%, sensed by an internal aluminium emitter
resistance.
The voltage drop on this resistor is compared with an internally generated threshold (- 200mV) and limits the current, thus controlling the Darlington base current until the input signal causes the output Darlington to switch off.
JII·. ., SGS·ntDMSDN
3/6
·1< IiliOC~iIl@XmDi:S
355
APPLICATION NOTE
Photo 1 shows the coil current behaviour together with the corresponding input signal. Photo 1 : Collector Current and Corresponding Input Signal.
Input signal (5V/div) Coil. current (2Ndiv)
The current loop is made by compensated operational amplifier ensuring enough precision of the set value and hence of the stored energy without requiring external components. The regulation stability is infact mandatory in the car ignition system to avoid spurious sparks on the secondary coil winding. During the current limiting phase, the Darlington collector voltage reaches the battery voltage minus the voltage drop on the coil (due to the primary resistance). It causes high powerdissipation in the power actuator which the microprocessor minimizes by delaying the output Darlington switch on.
Photo 2 : Collector Voltage During Coil Charging.
The overvoltage on the power Darlington collector during the transition from the coil charging to the current limiting phase is low enough to avoid undesiderable sparks.
At the input signal switch-off the power Darlington is immediately turned off and the energy stored iri the coil is transferred from the primary to the secondary winding causing the spark.
The collector voltage of the power Darlington then rises very rapidly and is detected by the spiral resistor used as the high voltage termination for the chip.
Coil. volt. (5V/div) Coil. current (2Ndiv)
4/6
356
APPLICATION NOTE
This resistor, used as a divider, is connected to a low voltage zener circuit that turns on the power Darlington, holding the collector voltage at a value determined in the chip (- 400V± 10%) which is less than the Darlington VCEO.
Photo 3 : Voltage Clamp.
Photo 3 shows the collector voltage during the clamp in absence of the spark plug i.e. the worst case for stress on the integrated circuit.
Input signal (5V/div) Call. volt. (100V/div)
Fig. 4 shows the application circuit for this device. Figure 4 : Application Circuit.
~p
board
I
RsJ 300Il' J
) Ro
SOn.
4
2
5 VB020 ]
1
.-
Iijili~t H.v.
Two separate pins for the supply: pin 4 and pin 2, are connected to the battery by means of two different resistors. Pin 2 represents the supply of the driver with a cur. rent of up to 200mA.
Pin 4 is the supply for the rest of the circuit
S(-OllO
(k1 - 3mA). A picture of the die is shown in photograph 4. The device is assembled in a new fully insulated five-lead plastic power package, ISOWATT 5 and shown in figure 5.
5/6 357
APPLICATION NOTE Photo 4 : The Die.
Figure 5.
ISOWATT5
CONCLUSION
The ignition controller described in this paper completely substitutes the existing hybrid solution which requires additional components and manufacturing processes (i.e. insulating substrates, ink layers, active and special passive devices, laser trimming, en-
capsulation etc..). This single chip solution leads to an intrinsic increased compactness. The subsequent higher reliability is further enhanced by the known advantages of integration.
Additionally to that a cost reduction benefit through this approach is also achievable.
6/6
358
APPLICATION NOTE
TRANSISTORIZED POWER SWITCHES WITH IMPROVED EFFICENCY
ABSTRACT. An important objective for power electronic design is the reduction of power losses. This paper analyses the output characteristics of bipolar and MOS power stages and indicates limits for further on state loss reduction. A fast high voltage driver/switch combination with very low on state and switching losses is described. The switch is designed with cellular bipolar junction transistors driven by a smart power switch mode regulator. The driver handles duty cycles from 0... 100 % and requires only one unregulated auxiliary supply. The static and dynamic behaviour of the switch and its new driver stage are shown and discussed. The switch exhibits low losses and is able to operate at inaudible switching frequencies on the rectified mains.
Keywords. Mains supplied operation, on state loss reduction, simplified base drive, smart power, high switching frequencies, Darlington, POWER MOSFET, cellular bipolar transistor.
INTRODUCTION Loss reduction is a major objective in all power electronic equipment. The switching losses of all kinds of switching power semiconductors have been significantly reduced by means of structures , with increased interdigitation, cellular structures and improved carrier lifetime control. Today performances are often close to those that physical laws allow. The switching losses have been reduced to such an extent, that lowering on state losses has become the key for further loss reduction. Further loss reduction can only be achieved through the reduction of on state losses which is the major topic discussed in this paper.
HOW TO REDUCE LOSSES? Lowering on-state losses is of particular importance in inverter circuits operating with switching frequencies below 20kHz and in resonant converters where switching losses are already negligible.
For evaluation of on state losses, power semiconductor devices can be classified as:
By M. Bildgen ., K. Rischmuller'
a) devices with dominating resistive output behaviour b) devices with dominating p-n junction behaviour of output characteristics (Fig.1).
The Power MOSFET (MOS), the Bipolar Modulated FET (BMFET)5 and the Bipolar Junction Transistor (BJT) exhibit a resistive output behaviour (Fig.1 a). Their on state voltage drop can be reduced through increasing die size, a question of technology and cost.
The Bipolar Darlington (DLT), the MOS Gated Bipolar Transistor (MOSBIP), the Insulated Gate Bipolar Transistor (lGBT) and Thyristors (GTO, FCTh.,.) exhibit a dominating p-n junction output behaviour (Fig 1b), The on state voltage drop of these devices is the sum of the threshold voltage of the p-n junction and the voltage drop across a resistance. The threshold voltage is determined by physical laws, only the resistive part of the on state voltage depends on the die size. The influence of die size on on-state losses is relatively limited and is not a feature that can be used to give significant loss reduction.
MOSFET AND BIPOLAR TRANSISTOR The MOSFET, the BMFET and the BJT can have an on state voltage drop of less than 600mV and fast switching: A high power MOSFET e,g. a TSD4M450 (ROS(on) = 0,112, Vos =500V, 10 MAX = 45A) handles a current of 5 Amps with an on state voltage drop of only 500mV. The die area of such a device is about 170 mm2. The MOSFET requires only short gate current pulses for its drive.
A very fast cellular BJT e. g. a BUF410 (450V/1000V, 15A) switches 5 Amps with about 500mV on state voltage drop. The die area of this device is about 36mm2 and has therefore a very low silicon cost. The BJT requires base current:
- in excess of a fifth of the collector current - and negative bias for fast turn oft switching,
immunity against reverse current and dv/dt. Nevertheless, the power gain is very high, e.g. when switching 400V x 5A = 2kW, a drive power
AN813/0990
· SGS-THOMSON, Central Application Laboratory, Roussel, France
1/6
359
APPLICATION NOTE
Fig.1: Symbols, equivalent circuits and output characteristics of power semiconductor devices; a) devices with resistive output behaviOur; b) devices with p-n junction behaviour
a) IB~ VGS~i9
BJT
MOSFET
-~jl
i VGS iVaN
BM-FET
-g b)
~~j
I Vth"
OLT
MaS-SIP
I~ 1 - V/t'~
VGS
~ TvGS
\SIG~h
IGBT
GTO
SC-1320
i ~ I
VGS or IB
~
....... 1 I+-
Vth
VON
= VON Vth + r . I
TABLE 1: On-state and driver losses of different device/driver configurations
Device + Driver BJT + (1) DLT + (1) BJT + (2) DLT + (2)
On-losses VCE + Ic 0.5V x 20A = 10W 1.5V x 20A = 30W 0.5V x 20A = 10W 1.4V x 20A = 28W
Driver Consuptios Vs + 18 Total Conductive Losses
4A x 12V = 48W
58 W
0.6A x 12V = 7W
37W
10W
20 W
4W
32W
of only 1A x 1V =1 W (base current multiplied by base emitter .voltage) is needed. The gap in die size between the POWER MOSFET and the cellular BJT, increasing with voltage and current, is so important, that it is worth thinking about low loss base drive for bipolar transistors.1, 2, 3
TRANSISTORS AND DARLINGTONS The Darlington is the most popular switch in mains supplied, medium power applications. The major reason for this choice is its .moderate base current consumption.
A typical fast switching 20A,450V Darlington re-
quires a 0.6A base current. With a conventional driver circuit operating from an 8V to 12V auxilary supply, the worst case driver consumption would be 12V x 0.6A = 7W (Table 1).
The collector-emitter on state losses of the Darlington can be typically calculated to be about 30W. The total conduction losses amount to about 37W.
The bipolar junction transistor exhibits collector emitter on state losses of only 10W but requires a positive base current of 4A.
The total driver loss in the transistors is 4A x 1V = 4W (base current multiplied by base emitter voltage). With a conventional driver circuit operating
-2/-6-------------------------L" ~~~~~~:~~ ---------------------------
360
APPLICATION NOTE Fig. 2: Example of a switch-mode driver circuit for fast switching applications
SC-1322
*--
]
470
47il
n 15V
O~
o -1 LOcfF- - - - - '
Fig.3: Self generation of negative bias from a positive supply voltage
Rl
]
3300
2 x 1N4001
n OFF
ON --I L 0---'-1 fAr
R3 1000
SC-1323
---------------------------- ~~~~~~gu~:~~~ ---------------------------3/-6
361
APPLICATION NOTE
from an 8V to 12V auxilary supply, the worst case driver consumption would be 48W - total conduction loss would be 58W. The poor efficiency of conventional driver stages is the reason that the transistor power switch exhibits higher conduction losses than the Darlington. Using driver stages with high efficiency allows BJT power stages to be used instead of Darlingtons which results in significant loss reduction.
DESCRIPTION OF THE SWITCH MODE BASE DRIVER An L4974 smart.power IC with a MOSFET output stage operates as a buck regulator in current mode. The IC is contained in a DIL package but is able to supply a 4 Amp base current. (Fig.2). The efficiency is so high that thermal conduction to the PCB provides sufficient cooling. During the off state of the power transistor, TP, a MOSFET T1 applies a short circuit to the output of the buck regulator. The IC operates with low duty cycle and maintains constant current in the choke L. For turn on of the power transistor TP, the MOSFET, T1, is turned off and the constant choke current flows into the power transistor's base. The rate of rise of base current is limited only by the MOSFET turn off speed. In order to obtain very . fast switching, a high density MOSFET
Fig. 4: Test circuits for switching losses
(STVHD90) which has a very reduced input and output capacitance, has been used.
If the power transistor base current is 4 Amps and the auxilary supply voltage 20V, the driver input current will be about 0.47 Amps. Increasing the auxilary supply voltage further reduces the input current.
NEGATIVE BIAS FOR FAST TURN OFF SWITCHING The first version of the circuit generates negative bias with a Zener diode between auxilary supply and driver stage (Fig.2). The current return path to the auxiliary supply is through this diode. Losses in the Zener diode are small, due to the fact that input current of the driver circuit is small. For turn off, T1 and T2 are turned on, T2 applies the negative bias to the power transistor base, thus obtaining fast switching and immunity against reverse current and dv/dt.4
The second version of the circuit generates its negative bias directly from a positive auxilary supply:
a capacitor C1 (Fig.3) is permanently charged via a resistor R1 and a diode D1. At turn off switching, T2 is turned on·for a time t1, slightly longer than the power transistor's storage
+ vaux
DRIVER STAGE
5C-1321
OF D.U.T.......-I,.-rrl'TT1'-c:::r-..
C
BUF40S
BUF420
-4/6------------ LV ~~~;m~r::9lf -------------
362
APPLICATION NOTE
Fig. 5: Turn-on and off switching waveforms with transistors and Darlingtons
"= 7', IT\
r\
1 II
" 1-0.....
v.
r<:'.CE
SC-13e4
....Ie
SC-1326
- "'--
,.i\'\
/ f'.. -.::::. Ie
7J \ ........ /vCE
Darlington:
BUF405 + 8UF420/BYBO-600
Turn-on: VCE= 50V/div
Ie = 10A/div
l = 1DOns/div dic/dt = 450A/J,ts
-I\,,- 18 V '\. ..J Ie
SC-1325
I,.J
~
Bipolar Junction Transistor: BUF420/BYT30-600
Turn-on: VCE= 50V/div
Ie = 10A/div
l = 1OOns/div dic/dt = 450A/p.s
SC-13e7
\
\
V
I
18
II
~ i-"
Ie
VeE r-.. '--1/
Ve~E".D
Darlington:
8UF405 + BUF420/8YT30-600
Turn-off: VeE = 50V/div
IC = 5A/div I B = 2A/div
t = 500ns/div
Bipolar Junction TrlJn5i5tor:
BUF420/BYT30-600
Turn-off: VCE = 50V/div
I C = 5A/div I B= 2A/div t = 500ns/div
- - - - - - - - - - - - - - - - - - - - l . f i ~~tm~r::a!?~
5/6
363
APPLICATION NOTE
TABLE2: Switching energy losses of transistor and Darlington with BUF420 and BYT30-600
DEVICE UNDER TEST (DUT)
CELL. - BJT
CELL. - DLT
TURN-ON ENERGY
1 mJ 0.9 mJ
TURN-OFF ENERGY
0.5 mJ 0.8 mJ
TOTAL SWITCHING ENERGY
1.5 mJ
1.7 mJ
time, ts. T2 connects the positive electrode of C1 to ground, thus a negative voltage appears at the base of TP. T2 turns off after the turn off switching of TP and C1 continues charging. The state of charge of C1 is independant of duty cycle - sufficient negative bias is available with any duty cycle.
TEST RESULTS Fast transistors and Darlingtons made using cellular technology (e.g.BUF420) have been tested in a buck converter with 280V supply voltage and 20A output cu rrent (Fig.4) Both types of switches have been driven from the same switch mode driver circuit. The turn on and turn off waveforms are shown in Fig. 5a and 5b. The devices were operated at Tj =85°C.
As expected, the turn on speed dic/dt of the Darlington is twice as fast as that of the transistor switch. The reverse recovery current of the free wheel diode increases with di/dt. This makes the difference in turn-on loss between the fast switching transistor stage and the faster switching Darlington stage insignificant (Table 2). The storage time of a transistor stage is less than that of a Darlington stage. The test results confirm this well known fact.
With a given driver stage, the negative base current of a Darlington is reduced, due to the voltage drop of the speed up diodes. (Fig. 4) This explains the observed increased turn off losses with the Darlington.
CONDUCTION LOSSES The conduction losses, including driver losses have been calculated and confirmed by measurement. With a duty cycle of 100% the total conduction losses of a 20A Darlington with conventional driver are O.6A x 12V + 1.5V x 20A = 37W. The
same Darlington driven from the switch mode driver exhibits conduction losses of 32W. The conduction losses of the transistor with switch mode driver are 0.5A x 20V + 0,5V x 20A =20W. This is about 60% of the switch mode driven Darlington.
CONCLUSION Low loss driver circuits suffered from duty cycle limitations, or from excessive circuit complexity. New smart power devices reduce this complexity to an acceptable level, allowing the introduction of switch mode driver techniques in to transistorized power electronic equipment. The new configuration can be used to simplify and improve existing converter/inverter circuits (fewer auxiliary supplies, smaller heatsinks, higher efficiency).
The use of switch mode driver stages is not limited to BJTs, but offers improved efficiency in circuits with Darlingtons, BMFETs and GTOs.
REFERENCES 1) R.B.Prest, J.D.Van Wyk : Base drive for highcurrent low loss bipolar power transistors, PESC'86 Record.
2) C:K.Patni : An efficient "Switch mode" base drive for bipolar transistors, Internal note, SGSTHOMSON Microelectronics.
3) L.Perier,J.M.Charreton :25kHz Leistungsschalter mit 1000V Sperrspannung in dreiTechnologien,Elektronik Informationen H.9,1988
4) K.Rischmller: How to improve transistorized bridge converters, Proceedings of PCI'81
5) S.Musumeci, J.Eadie, p.wilson, A.Galluzzo: Bipolar mode JFET the BMFET, Technical Note 179, SGS-THOMSON Microelectronics.
6/6 ----------------------------
~~~~~~~~:~~
----------------------------
364
APPLICATION NOTE
ELECTRONIC IGNITION WITH VB020 AND L497
by M. Melito
INTRODUCTION
The VB020 is a monolithic high voltage integrated circuit which combines a vertical power darlington with built-in protection circuits for coil current limiting and collector voltage clamping, The device interfaces directly with a microprocessor which controls the dwell angle. This application note shows how it is possible to use the VB020 in an electronic ignition system not employing a microprocessor. The IC used, the L497, is a more conventional electronic ignition controller for breakerless ignition systems using a Hall effect sensor.
OPERATING PRINCIPLE
The schematic of fig.1 shows how the two ICs are connected to control both the coil current, providing the required stored energy and the dwell angle, for low power dissipation. The L497 was designed to drive an external Darlington and in a standard application circuit the current control is performed monitoring the coil current through a sensing resistor on the emitter of the Darlington. When the voltage drop across the sensing resistor reaches the internal comparator threshold value the dwell angle control circuit is enabled. Meanwhile the coil current is kept constant forcing the
AN482J0492
1/4
365
APPLICATION NOTE
" 8200~;~----
300 47 ~II~
lLl ~-.-----o!-----------"-----;
6 7 3 15
2
4
0- 5
14
3
12 L497
560 5 VB020
'" i'r-L i ~,;,,:t-~
2-2.-K n
01 lN4007
---t-----~
1.5K
\ :C .[1"'1_ O.l~F
100
------
Fig. 1 - Schematic of electronic ignition with VB020 and L497.
v~ = 2 V/div
r
lC011
lcoll = 1 A/div
t = 10 _/div
V13 =. 100 _/dlv V14 = 1 V/div Icon = 1 IVdtv
= t Z _/div
V, ,.------ '---
r--- f-'--, '--
Fig. 2 - V13' V14 and Icoil waveforms.
Darlington into the active region until the highlow transition of the input signal causes the spark to occur. The collector voltage is clamped to a value that is externally fixed by a resistive network. The internal dwell angle control circuit calculates the conduction time for the output Darlington in relation to the speed of rotation, to the supply voltage and to the characteristics of the coil, thus avoiding excessive power dissipation in the Darlington itself.
Fig. 3 - Duty-cycle = 30%; frequency = 20 Hz.
By linking together the L497 and the VB020 it is possible to avoid both the coil current sensing and the collector voltage clamping networks because the VB020 has internal built-in protection circuits which perform these functions. The dwell angle control is performed by supplying the L497 with the feedback signal shown in fig.2. The diode, 01, keeps the voltage at pin 13 of the L497 under the internal comparator threshold voltage until the VB020 begins to regulate the coil current. At this point
214
~------------------------~~~~~~~::~ -------------------------
366
leoll (
v, = 2 V/dtv
r
Icoll = 1 Aldtv
t = 10 -tdtv
APPLICATION NOTE
Icon
V5 = 2 V/dtv
ICCll = 1 A/dtv t = 2 -tdtv
V,
v,
I '--
Fig. 4 - Duty-cycle = 70%; frequency = 20 Hz.
V5 = 2 V/dtv
leo!!
Iron = 1 AldIV;1
"'-""1
Fig. 5 . Duty-cycle =70%; frequency = 100 Hz.
v,
Fig. 6 - Duty-cycle = 70%; frequency = 140 Hz.
Fig. 7 - Turn-off in normal operating mode.
Xco11
Vee = 50 V/dtv Icon = 1 Aldtv t = 50 us/dty
Fig. 8 - Turn-off with open gap.
D1 is turned-off and the voltage on pin 13 can reach the threshold voltage of the internal comparator enabling the dwell control circuit. Figures 3 to 8 show the system performance (Vin , Icoil) under various conditions and fig. 9 shows the conduction angle versus r.p.m. for a four cylinder engine.
-------------- --------------lifj ~~~~m~r::O!~~
3/4
367
APPLICATION NOTE
t_c_~/T~(~%~I_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- ,
80'",-
70'" 60'"
.......)><-(-4)(?---¥-)(- - - I/i"f-_c_~__-III_-_8I1___,_=__.m
/'
/~./+
................/....~ .... ,.,c.:: ...
17/ T
......
y,;-j/7/ '/
.
/ .
I
,-/ /'
~
40'" ................/ ..... ..... / . / ......................... ~.F'... ~~~"'""4
/ )/f//r*' ~------
- Vbat-20V
. . . . . . - . . . ::::vV 30'" ···········¢77~ ········································+Viia~iiV
20,"~==·
10'"
........................................... ···························*·yjjiii;ij"V"
0"L-~ __ ~ __ ~ __ ~ __ ~~~~~~~
o
2
3
4
«;
6
7
8
r.p.m. X 1000
Fig. 9 - Conduction angle versus r.p.m.
CONCLUSION
The VB020 can be used in electronic ignition systems without using a microprocessor. The overall cost of the system can be competitive with th.e solution using a Darlington because the current limiting and voltage clamping function performed by the VB020 are trimmed on silicon avoiding the need for additional adjustment.
REFERENCES
[1] F. Pellegrini, "L482 Development Report", SGS-THOMSON internal report, August 1982.
[2] M. Paparo, "L497 Development Report", SGS-THOMSON internal report, July 1985.
[3] "Automotive Products" Data-book, SGS-THOMSON microelectronics
-4/4------------~~~~~~&~:~~ -----------------
368
APPLICATION NOTE
INTELLIGENT AUTOPROTECTED DRIVERS
INTRODUCTION
In industrial applications, where digital control signals are provided by automation equipment, suitable Drivers are required to control various loads such as Relays, Lamps, Electrovalves, etc.
What are the essential main characteristics of these Drivers? · Primarily, they must be autoprotected, that is,
they must be self-resistant to industry-originated disturbances, short-circuits, over-currents, accidental load and ground disconnection, and so on. " Then, in case of fault occurrence, they must be capable of providing interactive dialogue with the central processor unit. · And finally, they must meet the requirements of the standards currently in force and those of the forthcoming projects, imposing that one terminal of the load should be directly connected to ground (see figure 1).
The objective of this note is to discuss and illustrate how a family of autoprotected control has been developed from basic concepts and also to outline the likely future trends.
by 10M. PETER and LRATES
FUNDAMENTALS
The control signal is applied to a comparator, the output of which drives a current source. This current source in tum drives the power transistor T1. A transistor T2 driven by the voltage drop across shunt Rse is configured to provide feed-back to power transistor T1. As soon as the voltage drop across this shunt exceeds O. 7V, T1 T2 configuration will act as a current limiting-unit so that llimit = O.8/Rsc. This is how the device is protected against short-circuits.
Another internal unit monitors the junction temperature which varies as a function of dissipated power (Le. Vee x lee) and cooling conditions. As soon as this temperature exceeds + 175'C (upper threshold), the protection until is activated and will sink the generator current Is thereby turning the device off. In the off condition, the device will cool down, and when the junction temperature falls below + 140'C (lower threshold), the thermal protection unit is deactivated and the device is restored to its normal operating mode. However, if the overload conditions persist, the system will operate in low frequency relaxation mode with a frequency ranging from 1Hz to a few Hz according to the nature of the overload. Whatever the operating conditions: " The current is limited at a programmable level. " The junction temperature limit is never exceeded.
AN268/0188
1/9
369
APPLICATION NOTE Figure 1 : There are two possible configurations of load/controller combination. Some standards and
forthcoming projects will require one end of the load to be directly connected to ground.
+
Figure 2 : Basic Functional Diagram of TDE 1647.
Thermal Protection
2/9
370
APPLICATION NOTE
These features make the TOE 1647 which is the basic circuit of the family, a switch well-suited to applications implementing drives for lamps, inductive loads, blinkers and relays, etc. It is worth mentioning that the current limit feature when used to limit the starting current, will in the case of incandescent bulbs, result in a considerable extension of their life duration.
INTERACTIVITY - A SECOND FAMILY OF CIRCUITS
In many applications, the control system must receive the acknowledgement of the execution of an issued command, or receive information reflecting possible failures and disturbances. The TDE1798
Figure 3 : TOE 1798 Autoprotected Control.
has been designed to meetthese requirements (see figure '3).
This autoprotected driver contains memory logic circuitry required to latch the device status and returl! the stored information to the processor.
This device is protected against thermal overloads exactly in exactly the same way as TOE1647 and in addition, if Reset input is held low, the driver output remains blocked after a thermal overload and this condition is indicated by a signal sent through the Alarm output pin. The Reset input is used to return the circuit to its normal mode of operation. In fact, if this input is maintained high, the device will operate in exactly the same way as TOE1647 that is, in case of continuous overloads, it will function in a low-frequency relaxation mode.
Alarm output (Source)
Inverting input 2
Non-inverting input 3
Alarm outpul (Sink)
3/9 371
APPLICATION NOTE
SHORT-CIRCUIT PROTECTION.
This device is protected against short-circuits by a current-limit feature operating exactly the same as the preceding device. Under overload conditions, the current is limited but the memory logic function is inactive.
POWER SUPPLY VOLTAGE LIMITS.
All of the devices of the entire family operate in a wide range of supply voltages: from + 6V to maximum voltage (between + 3V and + 6V, the protection logic is operational but the temperature detection circuit becomes inactive).
INDUCTIVE LOADS.
If a free wheel diode is connected across an inductive load, the voltage drop remains null while current decays slowly (figure 4,l. Two distinct solutions are possible to provide a rapid fall of this current:
Figure 4: Current Decay in an Inductive Load.
a)- Do not connect any additional device across the load. The output transistor of TDE1767/TDE1798 has been particularly designed to,operate. in avalanche mode and to clamp at voltage VZA. This outstanding feature eliminates the need of additional components in the case of inductive loads and automatically provides a rapid fall of load current.
As far as the users are concerned, this is an interesting feature. However, care must be taken not to exceed the operating limit of this transistor; that is, energy dissipated in the transistor
~ Ll2) should be less than 100mJ.
b)- In the case where energy stored in the load is very large, a Zener diode may be used to absorb this energy.
In case (b), the device and its internal logic circuits are protected against negative voltage peaks appearing between output and ground (figure 4).
v e
(a)
(b)
(el
a) - With free wheel diode. b) ~ Without free wheel diode - the internal transistor operates in avalanche (@ voltage VzA).This condition of-
fers the most rapid current fall.
c) - Addition of an auxiliary avalanche diode, Vz ~ V max.peak voltage accepted by the circuit. Note that these
devices have been designed to withstand peak negative voltages of as high as Vee - VZA between output and ground teminal.
4/9 372
APPLICATION NOTE
GROUND DISCONNECTION.
Besides the protection against disconnection of the power circuitry, these devices are also protected against accidental disconnection of ground return path. This is an outstanding security feature and the
TDE1798 was particularly developed to meet VDE422, the European standard which requires an instantaneous disabling of the output circuitry in case of accidental disconnection of ground (figure 5).
Figure 5 : The autoprotected control meet European security standard requirements. Output is automatically disabled in case of accidental disconnection of ground path.
~"\ ~\II
1
ANOTHER PROGRAMMABLE CIRCUIT.
TDE1767 is another version of this circuit which in combination with an external resistor, implements a programmable short-circuit detection feature.
HIGHER POWER - OPTIMUM SECURITY The control discussed so far are specified for output currents of O.3A to O.SA. TDF1778 & TDF1779 are dual auto protected control capable of handling up to 2 x 2A. These monolithic devices contain 2 individual drivers which share a common monitoring logic circuitry (figure 6).
Protection features offered by these circuits are:
A thermal protection feature similar to circuits mentioned earlier.
Signalling Logic, Fault Memory and the availability of a Reset input (similar to preceding circuit).
Short-circuit protection. If the device is operated with current of the order of 2A, safe operating
area of the transistor must be taken into account. Figure 7 illustrates the characteristics of the integrated protection unit. The fault memory feature is inactive when device is in current limit mode.
The output transistor of these circuits is not protected in avalanche. However, in the case of TDF1778, a 42V Zener diode inserted between the positive supply and the base of the output transistor, will transform it to an avalanche protected transistor.
An additional feature, detection of load disconnection, is also offered by these circuits. A high-value resistor (not shown in the figure 6) is connected between the power supply terminal and the outputs. As long as the load remains connected to the output and the input is blocked, the output potential is practically nUll. If the load is disconnected, this potential will rise and correspondingly, a signal is sent to the central unit through the Sense Output terminal.
5/9 373
APPLICATION NOTE
Figure 6 : TDF1778 Autoprotected Control.
r - - - - - - - -Strobe
I r-_.----~--------~--------~--_.--_t~Vcc
I
I
I
I
I
I
I OulpUI I D-t--t=-J-...J
'--c=J-....-o Oulput 2
Input 1 D-t-------...J
'----------4'"'" Input 2
Figure 7.
Alarm outpul
I
CI _________ _
Sense oulput
Resel Ground input
Dual output: 2 x 2A. Fault memory. Thermal and short-circuit protection. Detection of and protection against ground and load disconnection.
I
(AI
Vee
TDF 177. TDF 1779
6/9
374
10
20
30
40
Vee 0- Va tV)
Current protection limit. For TDFl778 and TDFl779 devices, this varies as a function of Vee -Va voltage appearing across the controller. This limit corresponds to the safe operating area.
APPLICATION NOTE
APPLICATIONS
Main characteristics of this family of AUTOPROTECTED CONTROL are: · Particularly suited to 24V to 48V - 0.3A to 4A sys-
tems. _ Operation from + 6V to maximum voltage. _ Can be used in parallel configuration. " Protection against: _ Over-currents. _ Excessive heating. _ Accidental ground disconnection. _ Interactive dialogue with central processor
unit (ALARM & RESET) terminals available on certain series. Detection of load disconnection (TDF1778 & TDF1779). _ Protection of output transistor by avalanche (some families). _ IlP and TIL compatible inputs.
Figure 8 illustrates some conventional industrial automation applications built around these devices.
Power handling capability of these devices can be readily enhanced by the addition of an external power transistor as shown in figure 9. Further to these conventional applications, autoprotected control are also well suited for the implementation of choppers (figure 10) and more complex circuits (Bridge, Half bridge...).
FUTURE EVOLUTION
Two trends for these circuits: _ Enhancement of power handling capability. _ Reduction of losses - A new circuit offering considerable reduction of voltage drop .and thus the losses, is forcast to be availaole in 1986. One of the consequences will be improving the circuit density in the equipment, thus achieving size reduction.
CONCLUSION
This new family of devices opens a new era of controllers which are:
_ On one hand stand-alone, i.e. self-protected against external disturbances. If operated in this mode, in case of fault occurence, the device itself will make the appropriate decision without the intervention of the central processor unit. On the other hand, capable of interactive dialogue, which means they are readily associated to processors and monitored by digital systems.
7/9 375
APPLICATION NOTE
Figure 8 : Some Typical Applications of Autoprotected Controllers.
+ 24V
.. 24V
TOE 1647
+OJA
Lamp driver
TOE 1647
TOE 1747
JL JL
Small motor controller (constant torque breaking)
Electrovalve driver
8/9
376
Relay driver
Figure 9 : TDE1767 Power Boosting.
Input
APPLICATION NOTE
Safe operating area in linear mode.
p
z,
RSC resistor determines the short-circuit current.
Voltage VZ1 determines the abscissa of point M. Resistor P determines the abscissa of point N.
VI (V) + 12 + 18
R1 (KQ) 62 91
Figure 10 : Voltage Step-Down Chopper.
V, __ ____ __________- - ,
~
~
A 1
R2 (KQ) 1.5 3.5
VO (V) +5 + 12
0.50 100 kO
'--------.-l.- Vo
15 k{l
A2
9/9 377
APPLICATION NOTE
INTERFACES DEDICATED TO PROCESSES CONTROL
Controlling tasks are very common in many areas, for example the control functions associated with buildings, the factory automation control, the production and control of energy, the chemical industries ... These tasks are genrally managed by process controlers or industrial micro computers linked to a supervisor and sometimes a dedicated computer. At the control level, sensors and actuators are the means of controlling the physical processes, and are monitored and driven by the process controller interfaces. _ 90% of system failures are due to the wiring or
the sensors/actuors. Wiring may be reduced by the use of a field BUS and the distributed interfaces. _ Considering the remaining 10% of failures, 90% of them are due to the input/output interfaces.
'Thus, if the reliability of the interfaces and the diagnostic functions are improved, the availability of the system increases (working time/wirking time + stopping time). Agood means to achieve that is to use integrated self protected interfaces allowing a telediagnostic from the controller. The devices have integrated on the same silicon chip the safety and diagnostic functions and the power switch. A better availability is achieved by mixing integrated interface with field BUS, decreasing the first 80% of errors, and the instanatiOn cost of the system.
By J.M. BOURGEOIS & L. PERIER
A FAMILY OF INTEGRATED INTERFACES
The family of new circuits are dedicated to drive any type of inductive and resistiv.e loads.
Their main characteristics are:
* No indeterminate states up on power on. * Short circuit protection with the positive supply and
ground by current limitation. * Over heating protection. * Protected against overloads. * Alarm output with delay. * Open ground protection. * Output voltage can be lower than ground for fast inductive load demagnetisation. * Differential input for universal logic compatibility. * Output paralleling capability. Generally, hybrid or discrete circuits are used for these interface functions in process controller. Using integrated devices is cost effective and provides a better thermal protection because of the integration of the temperature sensor. As consequence, overload protection is totally reliable. Integrated interfaces are available in high side and low side configuration, for a range of current from 0.5A to 2A. They operate with a supply voltage range of + 8V to + 32V, a typical block diagram of one of these devices, the UAB/UAF 1780, is shown in Figure 1.
APPLICATION CIRCUIT OF THE UAB/UAF 1780
+5U~~~--~~------~--~----~----.
3x 18K
AL 1
AN27010289
1/5
379
APPLICATION NOTE
Figure 1 : UAF 1780 Structure.
Rdl:f1lOCll
Alarm 1
InpUt 1 STROBE
~
Input 2
AIonn'
UnlylnGH--/1:J~-.on
M89UAF1780·01
APPLICATIONS A local peripheral was designed for use by a micro computer or process controllers. The circuit uses four UAB/UAF 1780 which are dual integrated interfaces delivering up to 1A without heatsink and more than 2A with. The interfaces are driven and monitored by a Z86E11 micro controller whose UART allows the communication link with a serial field BUS.
Figure 2 shows the block diagram of the system.
The configuration of the output of the integrated interface allows. each output to be used as on input (via Po) if desired. Only one of the four UAF 1780 is showed on the figure. - In output configuration, the interface controls and
minotors the load. The feedback signal to the port Po means that the state of the output can be monitored increasing the diagnostic capability - In input configuration, the interface is off and the signals are read via the Po port.
List of items:
* UAB/UAF 1780 : Intelligent full protected power switch * Z86E 11 : 8 bits microcontroler * TRANSIL TH6P04T6V5CL : Octal protection zener in OIL package * L296 : High current switching regulator with reset output * AM26LS31 : High speed differential line driver * AM26LS33 : Oifferentialline receiver * TRANSIL BZW5033 : Transcient voltage suppressors 5Kw/1 msec * BYW1 00/1 00 : High efficiency ultra fast diodes VRRM = 1OOV trr = 25/60nsec Vf = 0.85V
2/5 380
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33nFI947K
AL 1 AL 2
1=4u7F 19BuH VREF Vee UDUT
.B'rU188
UAF1780 DC/DC -..J
P36
P2
INP 1
OUT 1
I ZB6El1 P34
GHD
P35
P32 Uee
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INP 2 STROBE RESET GND
OUT 2 DELAV1 DELAV2
3 14 12 1 18 21
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5
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13 fi-B
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uF uF uF
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7
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INPUT OUTPUT f rorn/ to SENSOR ACTUATOR
nB9lJRFt?S9-B2
"10'
c..:.
(D I\)
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iil 3
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-mI
APPLICATION NOTE
MAIN CHARACTERISTICS OF THIS PERIPHERAL
a) Inductive load demagnetisation :
The ability of the integrated interfaces output to sustain negative voltage up to 30V, provide a very fast demagnetization of inductive loads. The size of the Zener diode depends on its voltage, the load current and the commutation frequency.
b) Noise and spike immunity.
The interfaces are supplied directly from the local 24V line. Because they withstand voltage spikes of up to 60V for 1Oms, a transil is an effective protection for supply disturbances.
The outputs are protected by diodes connected to the ground and to supply to ensure the interface outputs are not subjected to parasitic voltage spikes.
c) Interrupt priority register.
-The first priority is given to the switching regulator L296 which warns the· micro controller when there is an interruption in the supply volt-
age. This regulator provides simultaneously two auxiliary supplies one of which is isolated and used for the field BUS interface AM26LS31.
-The second priority is used for the communication with the host computer via the UART.
-The third priority is used to monitor the deiault signal of the UAF1780 interfaces.
d) Field BUS interface:
The galvanic isolation of this peripheral requires only three opto couplers because of the mUltiplexing of the INPUT/OUTPUT and alarm signal.
e) Efficiency:
The high efficiency of these integrated interfaces is due to an integrated DC/DC converter which reduces the on state voltage of the output Darlington stage.
DIAGNOSTIC CONTROL
When alarm output is enabled, the following processus is started.
Memorise when the alarm occur and send alarm register to host computer
YES
>---·NO
Diagnostic test using feedback
control
4/5 382
APPLICATION NOTE
INTERFACE BEHAVIOUR
a) Inductive load.
Figure 3 shows the turn-off commutation with an inductive load, the demagnetisation zener diode used was 10V. This diode provides a current path for the load demagnetisation and a protection against negative spikes induced from in the wiring.
Figure 3 : I load: 0.4 A/div V out: 10 V/div.
,
...,'
· _:,B_
-I
·· I
· ... B
D · ~
B
·· .. -4 I
·· I
!. · · I III B
I
III
B !. -.
-_.- --. ~--
' .. ,
-I ~
t : 20 msec/div.
b) Short circuit behavior:
Figure 4 shows the output current and the alarm signal in case of short circuit. The current is internally limited for a preset delay, after which a low level is applied on the alarm output and the current switched off. This device can be reactived by the reset input.
Figure 4 : V alarm: 2 V/div I load : 2 A/div.
c) Over heating detection:
Figure 5 shows the output current and alarm signal in case of over heating detection. When the silicon chip reaches 150°C, the current is switched off and the alarm output actived. If the reset input·is low, the switch restarts after the thermal hysteresis cycle and a preset delay. If the reset is high, the switch will remain off and the alarm low.
CONCLUSIONS
This family of integrated full protected interfaces provides more reliability in process control. Due to the alarm output, the real time diagnostic function can easily be multiplexed with a low cost micro controller.
The set of devices used for this application is optimized and provides a high immunity against all disturbances from the line voltage, the wiring and the loads.
BIBLIOGRAPHY
(1) AUTO PROTECTED CONTROLS Selection guide SGS - THOMSON
(2) NEW INTELLIGENT POWER COMPONENTS By K.RISCHMULLER, ELECTRONICA MUNCHEN 1986
(3) THE FIELD BUS by J.THOMESSE ENSEM/CRIN NANCY/FRANCE
(4) LA COMMUTATION A FAIBLES PERTES D'INSERTION by M.REFFAY, (Electronique Industrielle - 1 Mars 1987)
(5) RESEAUX ET TELEMATIQUES by G.PUJOLLE, D.SERET, D.DROMARD, E. HORLAIT, (EYROLLES EDITIONS)
t : 1 msec/div.
W:rtf/ SC<iGlO©SIii·IT@~H~I?O©TIMIiiIS@IOi!INQ©$
5/5
383
APPLICATION NOTE
HIGH SIDE MONOLITHIC SWITCH. IN MULTIPOWER-BCD TECHNOLOGY
Recent advances in integrated circuit technology have allowed the realization of a new mixed process integrating isolated DMOS power transistors in combination with bipolar and CMOS signal structures on the same chip. Called Multipower-BCD, this technology has been used to realize a monolithic self-protected high-side switch mainly intended for automotive applications. Driven by TTL, CMOS input logic it can supply resistive or inductive loads up to 6A DC allowing a current peak of 25A with an ROS(on) = 0.1 Q . Fault conditions are signaled on a diagnostic output pin.
by C.Cini, C. Diazzi, D. Rossi, S. Storti
ELECTRONIC POWER SWITCHES IN THE CAR
The increase of the number of the electrical components in the car (today more than 50) and the increase in assembly costs shall soon make economical multiplexed power supply and control systems. These systems consist of a single line for power supply and a multiplexed signal network for control; in this way it is not necessary to have a wire for every load, but only a common power line and a common signal line for all the loads (fig. 1).
Figure 1 : Example of a Multiplexed System.
AN271/0189
s - 9897
1/8
385
APPLICATION NOTE
The control system is made, for example, with a central unit near the dashboard, for the user interface, a serial data transmission line and some peripheral units near the loads (fig. 2).
The multiplexed system not only makes it possible to reduce weight and overall dimensions of the cable harness, now critical in some places (e.g. the junction between the vehicle body and the doors), but, also makes it possible to have a bidirectional signal between peripheral units and the central unit without any extra line, this is useful for fault detection and, in a future, for data transmission to make a more complex informatic system.
Today the key problem, from the system engineering point of view, is data transmission whereas for
Figure 2: Block Diagram of a Peripheral Unit.
semiconductor technology the key problem is the electronic power switches.
The electronic switch, in addition to its main function, must be able:
1) to withstand a very high peak current (20A) with total battery voltage (==14V) applied.
2) to protect itself, the power network and the load against overvoltages (load .dump == 60V) and overload (protection with fuses is impractical),
3) to make some fault detections e.g. detect short circuit or open load condition.
For this reasons a simple electromechanic or electronic switch standing alone is not sufficient, a more complex circuit is necessary and for this the monolithic solution is the most effective.
I Q~ r
IN
FAULT
L- OUT DRIVER PW
J.
J
0 1 IN ' - - OUT
I
FAULT
PW f--
FROM BATTERY
CODER RECEIVER
DECODE R TRANSMI HER.
1
FROM MULTIPLEXED DATA LINE
5 -9 B9B
2/8
386
APPLICATION NOTE
HIGH SIDE DRIVER
The problem of electrochemical corrosion is of primary importance in automotive systems because the electrical components are in an adverse environment (temperature, humidity, salt), for this reason the series switch is connected between the load and the positive power source. Therefore when the electrical component is not powered (that is for the greatest part of the lifetime of the car) it is at the lowest potential and electrochemical corrosion does not take place.
For this connection, components such as power PNP bipolar transistor or Power P-channel MaS would be integrated with low level signal circuitry
Figure 3 : Possible High Side Drivers.
(fig. 3a), but this kind of element is less efficient and more difficult to realize than their complementary one. NPN bipolar transistors or N-channel MaS, if directly driven by the supply voltage, are not a good solution because the minimum voltage drop on the switch is VBE or VT (threshold voltage) ; the best solution is to have a driving voltage for the power transistor, higher than the positive supply. Nevertheless a power junction NPN transistor (fig. 3b) needs a certain amount of base current ( ~ = 10-60 to have deep saturation) that could be obtained with a DCDC converter; if centralized it complicates the power supply distribution network, if decentralized it complicates the peripheral unit always critical for size, reliability and cost.
A) with PNP pass transistor
BATTERY
DECODER
r--------,
r - - - - . . ( ' ) . - LOAD I I
I I I I
I I
____ ...J
s - 9B99
8) with NPN pass transistor (needs external DC-DC converter)
DC/DC CONVERTER BATTERY
r--------,
I
I I I
LOAD
DECODER
5-9900
C) with N CHANNEL DMOS
BATTERY DECODER
r--------,
I
I
I
I
I
I
I
I
LOAD
5-9901
3/8
387
APPLICATION NOTE
On the other side a POWER MaS N-channel (fig. 3c), being a voltage driven device, requires for the driving only a capacitive charge pump which can be fully integrated on the switch chip.
Bipolar transistors moreover need driving power and principally, are limited in maximum peak power by second breakdown.
THE PROCESS TECHNOLOGY
For the realization of the device a mixed BipolarCMOS-DMOS process has been utilized. This process integrates the following components (tab. 1) (Fig. 4) :
Table 1 : Devices in Multipower-BCD Technology.
VERTICAL D-MOS P-CHANNEL DRAIN EXTENSION C-MOS N-CHANNEL C-MOS P-CHANNEL BIPOLAR PNP BIPOLAR NPN1 BIPOLAR NPN2 BIPOLAR NPN3
BVDss> SOV BVDss > 75V BVDss > 15V BVDss> 15V VCEO > 20V VCEO > 20V VCEO > 20V VCEO > 20V
VTH = 3V
VTH = 1.9V VTH = 0.9V VTH = 1.9V
j3 = 30 j3 = 30 j3 = 250 j3 = 250
Figure 4 : A Schematic Cross Section of Bipolar, CMOS and DMOS Structures.
IT = 1GHz h = 200MHz
IT = 10MHz fr = 300MHz IT = 1GHz IT = 140MHz
L. _ _ _ _ J 1 L-_ _ _ ---.l
L _____ ~ LI_ _ _
L I_ _ _- . J
POWER OMOS CMOS NPN PNP H.V. P-CH
s- 9351
MOS
4/8
388
APPLICATION NOTE
_ N-CHANNEL POWER DMOS able to withstand VDS = 60V for the series element.
_ BIPOLAR NPN AND PNP TRANSISTORS mainly employed in analog circuitry where low offset and high gain are needed e.g. voltage comparators and references, operational amplifiers.
_ CMOS TRANSISTORS to realize a dense logic network with stand by currents practically negligable.
_ PASSIVE COMPONENTS as resistors with a great variety of sheet resistivity (30+8500QlD)
to optimize both very high and very low resistive circuitry and gate oxide capacitors (e.g. to realize charge pump capacitors).
THE CIRCUIT
The circuit (fig. 5) is made by a power DMOS series element, a driving circuit with a charge pump, an input logic interface and some protection and fault detection circuits.
Figure 5: Block Diagram of High Side Switch L9801.
r---------------------- -- +Ve 1 ------------------,
1 1 31 1
GND~
1
CURRENT
I
IIIII
OPEN LOAD
~
5 OUT
1
1
1
1
1
U006: : DIS
1
___________________________________________ J
~
1
Q9
5-9895
5/8 389
APPLICATION NOTE
THE POWER DMOS
The power DMOS transistor is an array to 10,000 elementary DMOS cells that occupies an area of about 19,000 mils2 and has a ROS(on) = 80mQ with VGS = 1OV. The low value of ROS(on) is required both to increase the power transferred to the load and to minimize the power dissipated in the device. In fact the switch must be operative also at very high ambienttemperature (125'C) as required in automotive applications. For example to drive a 5A (60W) load, the drop on the switch is 400 mV and the dissipated power is 2W (Rth j·case 1.25'CIW).
THE CHARGE PUMP
The charge pump is a capacitive voltage doubler (fig. 6) starting from power supply (car. battery), driven by a 500 KHz oscillator.
The pump capacitor is an integrated 80 pF capacitor, the storage capacitor is the gate capacitance of the power itself (- 500 pF).
Figure 6 : Charge Pump.
Nevertheless a solution with a voltage reference and comparator is not suitable because it needs a bias current flowing also when the device is in the OFF state.
This point is of great importance because the switches are directly connected to the car battery without the interposition of the ignition switch, thus also a little current (> 50j.lA) multiplied for the number of the switches (e.g. 50), causes an appreciable discharge current always flowing.
For this reason a threshold circuit has been designed derived from a well known voltage reference (fig. 7).
Figure 7 : Input I;,terface.
+Vs
IN n-....,-~---«:
OUT
5 - 9903
500 KHz OSCILLATOR
DISABLE
5-9902
OUTPUT·
INPUT INTERFACE
Considering the very wide operating temperature
range (Tj = 40 to + 150'C) it is not possible to
obtain the logic threshold from the conduction threshold of any elementary device, because of its temperature coefficient, respecting TTL input levels.
Fixed a threshold value VIN = VIN*forthis value must
be, by design h = 12 = 10*.
= A01
if IX area ratio I X = - -
A02
must be
/).VBE
h - R1
(h + 12) R2 + VBE (02) = VIN
R2 KT
that is VIN* = 2 -R 1 q
1n IX + VBE 02
Reasoning around the threshold point it can b~ noted that the transconductance of 02 is greater than the transconductance in 01 branch (01 series R1).
For this
if VIN > VIN*
03 ON
if VIN < VIN*
03 OFF
6/8 390
APPLICATION NOTE
The choice of the values is made imposing:
1) VIN* '" VSG '" 1.2S0V band-gap voltage of silicon.
In this case VIN* is practically stable in tempera-
ture and centered respect TIL input levels
(VLMN< = O.SV. VHMIN = 2V).
The idle current lASS in the worst case, that is
when VIN = VLMAX = O.SV. Tj = 1S0°C, it must be lASS = h + 12 < SOl! A.
The proposed circuit has also a third working region:
when VIN < VSE
lASS = 0
03 OFF
Observed that the TIL OUTPUT low level is VL MAX O.4V with practical driving circuits the idle current of
this interface is zero: only at very high junction tem-
perature (VSE < 400mV) or with noise margin = VSE
O.4V) this performance cannot be warranted.
The output of this circuit is useful to switch off not only the power DMOS, but also all the other circuits so that the idle current only the one of the input interface.
PROTECTION AGAINST OVERVOLTAGES
When the supply reaches the maximum operative voltage (1SV) the device is turned OFF, protecting itself and the load; moreover local zener clamps are provided in some critical points to avoid that VGS of any MOS transistor could reach dangerous values even during 60V load-dump transistor.
PROTECTION AGAINST OVERLOAD
If the design of this device the peculiar inrush current of incandescent lamps must be considered, in fact.
1) When the tungsten wire is cold its resistence is about one tenth of the nominal steady state value (e.g. about 300mQ for a 12V/SOV lamp).
2) The decay time constant for the turn on extracurrent of an incandescent lamp supplied with an ideal voltage source is on the order of some milliseconds.
3) A lamp powered with a constant current slightly higher than its steady state value has a turn on time on the order of 1OOmsec. This time comparable with human reaction time is too much long for all flash-signalling devices.
The design choice has been to put a 20A current li-
mit (th~t is Imax = S Inom for a SOW/12V rated lamp).
This is a compromise between lamp turn on time
(40msec) and electric and thermal dimensioning of the device (fig. S).
If the high current condition persists (e.g. load short circuit) and the junction temperature rises above 1SS'C a thermal protection circuit turns off the device preventing any damage.
It must be noted that the power DMOS has no second breakdown, for this reason current limiting and thermal shutdown are sufficient to protect the device against any overload.
Some thermal hysteresis is provided to avoid a potentially critical condition (both current and voltage present during thermal shut down) for the POWER MOS.
Figure 8 : Lamp Current (IL) and Voltage (VL) vs. Time with 20A Current Limitation and 12V/SOW Lamp.
. -__, -__, - - ,__-,~G~-~"=55--'VL
(V)
20 r-r------j------:1:::::::;:====j14
16 1----I"'1\-----i--
-- 12
12 f-+----'---"'::--
10
6
4 _ L-~ _~_ _~_ _~_ _~_ _~
o
10 20 30 40 50 t(ms)
FAULT DETECTION
When the device is driven and one of the protections (over temperature, overvoltage, overload) is present a fault detection open drain output tums-on. This output is active also when the drop on the POWER MOS is less than SOmV (that is Iload < 1A) detecting the open load (disconnected or burned-out).
When the device is off the fault detection circuits are not active and output transistor is turned off to allow a minimum quiescent current.
MOTOR AND INDUCTIVE DRIVING
This device can drive unipolar DC motors and solenoids as well, in fact is can recirculate an inductive current when the output voltage goes more than a threshold lower than ground. The possibility to have a high start-up current is useful also for DC motors.
7/8 391
APPLICATION NOTE
CONCLUSION - FUTURE DEVELOPMENTS
A process allowing the integration of power DMOS, CMOS and BIPOLAR transistor makes possible the construction of a monolithic switch comprehending also protection and fault detection functions.
The power DMOS approach allows also the possibility to make a large range of power switches with different ON resistance and current capability only scaling proportionally the power area.
Moreover the CMOS structures can be utilized to make also the coder/decoder circuit to interface directly the transmission line.
Those features and the possibility to integrate more than one power element on the same chip makes possible, in a near future, the integration of the wholeperipheral unit.
8/8
392
POWER SUPPLY
393
APPLICATION NOTE
DESIGNING WITH THE L4963 MONOLITHIC DISCONTINUOUS MODE POWER SWITCHING REGULATOR
by M Roncoroni
The L4963 is a new switching regulator designed to operate in discontinuous mode, reducing the number of the external components, giving a very cost effective solution. This application note
explains how the device operates and how it can be used. Typical application circuits are also
described.
The L4963 is a new monolithic step down switching regulator IC operating in discontinuous mode. This device, able to deliver 1.5A to the load at a voltage of 5.1 V and up to 36V with derated current, is designed to satisfy very low cost applications due to the fact that the number of the external components are dramatically reduced. Moreover the inductor value is reduced by a factor of three or four in comparison with a corresponding continuous mode solution. Also the plastic package (Powerdip 12+3+3), that needs no heatsink, contributes to decreasing the cost of the overall application.
Although the L4963 is intended for very low cost applications, it integrates features like remote in-
Figure 1: L4963 Block Diagram
hibit, reset and power-fail outputs for microprocessor.
In the following we will explain in detail its principle of operation and the criteria that regulate the choice of the external components.
CIRCUIT OPERATION
The L4963 operates in discontinuous mode. In principle in this kind of operation the energy stored in the inductor is fully discharged to the load before to start a new cycle. To operate in this way, the device contains, in its regulation loop, additional blocks compared to the usual Error/Amplifier, Oscillator and Pulse Width Modulator used in the continuous mode devices.
-- .......... .
. ucc
: uss 3
1
.:!:. CI
:!
UOUT
L4963
P.F. 8 OUT
UCC R1
4-5-6 13-14-15
7 P. F. IN
AN458/0190
19
C
:C0ELAY
n!1IL4!163-8t
1/17
395
APPLICATION NOTE Figure 2: Waveforms
T
IL
ton toff' toff"
f152f1N458-82f1
(A) FIXED FREQUENCY OPERATION
ton
toff
i4-:4---T
~:
·4
T1
(8) UARIA8LE FREQUENCY OPERATION
The L4963 control loop is shown in the block diagram of fig.1 and the blocks that take part to the regulation loop, are determined by the system operating conditions.
For a given value of the inductor L (that will be further calculated), if we examine the current across the inductor ( IL ), we can have two different situations that modify the device operation. This two different conditions depend on the load current value that device has to deliver: changing the load current ( 10 ), the current through the inductor can have one of the shapes shown in fig. 2.
In both the waveforms, the current in the coil goes to zero during the Toft period of the power stage, but in the case shown in fig. 2A there is a "Dead Time" during which, both the Power stage and the Free-Wheeling diode are not conducting. The dead-time period ("Toft") increases lowering the load current. The system will start with a new cycle at the next set pulse coming from the clock. In this way the system operates in fixed frequency mode, set by the External resistor RT connected between pin. 17 and ground.
In fixed frequency mode, the current in the inductor reaches the peak value, determined by the load current, following the law:
Vin - Vcesat - Vout
L
. ton (1)
When the output voltage reaches its nominal value, the E/A output resets the power stage and the discharge period starts.
When the power transistor turns off, the inductor will try to mantain the forward current constant, and the voltage at pin.2 will fly negative until the diode D is brought into conduction. The current in the inductor L will now continue to circulate in the same direction as before, decreasing linearly from the peak value to zero following the law:
IL- = Ipeak -
Vout + VF
L
. toff
(2)
It follows, then, a third period toft" (dead time) during which there is no current neither across the power transistor, nor in the diode D, nor in the inductor L (the inductor runs 'DRY'). This period ceases when the next set pulse from the clock circuit enables again the power stage repeating the cycle.
The operation frequency is equal to the clock frequency, that is determined by the resistor Rt, connected between pin. 17 and ground:
0.033 fosc (KHz) = Rt (KQ)
In fig.3 are shown the voltage and current waveforms associated to this mode of operation.
2/17
------------------------
~~~~~~~~:~~~
-----------------------------
396
Figure 3: Fixed Frequency Operation
APPLICATION NOTE
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::
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.
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. .
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OSCILL'~
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RESET PULSEk
COMP "8" OUT
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. . ' '
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.'
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L
11!J2f1N458-83
- - - - - - - - - - - - - ....,1 ~ Si!lCrrli!S:ll·lT@rnH~rnOI!:MVIllS@OlOlIIN!:®
3/17
-------------
397
APPLICATION NOTE
Referring again to the block diagram in fig. 1, and with a given inductor L, we suppose to have a load current that reduces the Dead Time toff" to zero. At this point we suppose that the clock send a set pulse to the latch and the power stage turns on. The current in the inductor grows from zero up to its peak value (lpeak=2Iout) following the law stated in Eq. 1. If the peak current is below the Current Limitation threshold, it is again the Error Amplifier that turns off the power stage and the inductor will discharge following the eq. 2. If the system is not able to discharge completely the inductor during the maximum toff time. allowed by the fixed frequency operating mode an internal comparator, (which compares the voltage on the free-wheeling diode cathode with a precise internal reference Vr = -100mV) will mantain the power stage off until the inductor will be completely discharged. This comparator prevents the discharge of the internal timing capacitor Ct, until the Energy in the
Figure 4: Self-oscillating Operation
inductor is completely discharged and the diode D ceases to conduct (see fig.4).
The system is working in a variable frequency mode, with a switching frequency that is depending on the current delivered to the load. Bigger is the load current higher is the stored energy and longer is the time during which the comparator will block the discharge of the. timing capacitor Ct, decreasing the system operating frequency. In fig.4 are shown the waveforms associated with this mode of operation.
CALCULATION OF THE INDUCTANCE VALUE, L
To calculate the inductance, that is a critical element in the circuit, we have to consider that: · The switching frequency increases reducing
the load current lout and increasing Vin. · The switching frequency decreases increasing
the load Current lout and decreasing Vin.
So to calculate the inductor value we have to
ILI~
"UJ · .
'" t · ·
·· ..
. ,
OSC··'·· I ...,·~. L- L'...:,, ~....~I :
· ·
.
,
SET PULSE tt;~_-------lnL......;-::_-
RESET PULSE
: ·
h
______
_ _ _ _ _ __
~
~~L-
· .
COMP "8" _....;...---; OUT
fI!l2I1N458- 84
4/17
--------------
IiA::='!'='
SiI\GIUS©Il.i1Il@In0~©M~IiSI@OOOUN©~
--------------
398
specify the minimum operation frequency (higher than 20KHz to avoid audible noise), for the minimum input voltage Vin at full load. The equation to calculate the maximum inductor value is:
L~ (Vin(min)) - Veesat - Va) . D 2· lout(max)' fmin
where: D = ,-:-----'V-a:-:+---V'-F---:-:-"' Vin(min) - Veesat + VF
In overload or in short circuit conditions, the switching frequency decreases below the minimum limit fixed in standard operative conditions (fmin). For this reason is important to select a fmin with margin to avoid values inside the audible range in worst case. Too low inductance values are not suitable because the increased ripple current in the core may generate too high ~ipple voltage in the output.
Example:
We want to use the L4963 in an application in the following conditions: Vi = 15V to 35V Va =5V 10 = 1.5A (max) fmin > 25KHz Veesat= 1.5V VF = 1V
The right inductance for this application is calculated as follows:
5 + 1 Dmax = 15 _ 1.5 + 1 = 0.41
APPLICATION NOTE
Where: Ve = -8-. -ILC-p'oe=aukt=-. -' (7)
21 0ut 8 . Cout . f
lout 4· Cout . f
VESR = ILpeak . ESR = 2· lout . ESR (8)
Once fixed the amount of ripple voltage desired for the application, with the first term we determine the minimum suitable capacitor value and with the second one we determine the maximum ESR acceptable. Normally, for frequencies above 20KHz, the maximum ESR defines the choice of the filter capacitor value. In general, lower capacitor values have higher ESR ratings, so higher output capacitors than is calculated in eq. (7) should be used.
To guarantee a proper operation of the internal Error Amplifier, the minimum ripple voltage in the output must exceeds 15mV, to ensure a minimum voltage difference across its input terminals.
POWER DISSIPATION
It can be considered as the addition of three values:
Ptot = Psat + Pq + Psw
where:
Psat: Saturation losses of the power transistor plus the sensing resistor power dissipation.
Psat = V32 . 10 . ton = V32 . 10 . Va
T
Vi
L ~ (15 - 1.5 - 5) ( 0.41 ) = 46 H
2 . 1.5 . 25 . 103
. 11
Suggested value for L is in this case 40llH that corresponds to about a 15% less the max. allowed inductance.
V32 = dropout voltage between input (pin 3) and output (pin 2).
For worst case (for 12 = 3A switch current) the V32 = 2V
Pq: Losses due to the stand-by current and to the power driving current.
OUTPUT CAPACITOR SELECTION
All the considerations for the choice of the filter capacitor in a system working in continuous mode are still valid in a discontinuous mode operation (Ref. L296 Appl,note). Let summarize the results with some useful suggestion for this specific system.
The Ripple Voltage imposed on the D.C. output voltage is given by the sum of two terms. The first term (Ve), depends from ILpeak, Switch. Frequency and Cout values and the second (VESR) is due to Equivalent Series Resistance (ESR) of the capacitor multiplied by the ILpeak current.
Va = Ve + VESR (6)
Pq = Vi . 1'3q + Vi . 1"3q = t~ = Vi . 1'3q +Vo . I" 3q
In fig. 6 and fig. 7 are showed these two typical values of quiescent current. For the we worst case we can considered:
1'3q (0% d.c.) =13mA 1"3q (100% d.c.) = 17mA Psw: Power transistor switching losses:
Psw=Vi·IO· 2tr +TIf
-----------------------------
~~~~~~~~:~~~
5/17
-----------------------------
399
APPLICATION NOTE
Figure 5: V32 Voltage vs. Output Current
V32 I V)
1192AN45B·85
1.2
-25'~
1.1
~ Axe
1.0
- - ::-- - 13.9
I--
V /',,;125'C
f.--
V
--- 0.B
V
-- 0.7 r-
0.6
0.5
0.9
1 . 3
1.7 121AI
Figure 6: Quiescent Drain Current vs. Supply Voltage (0% Duty Cycle)
Iq
ImA )
14
119 tL 4963· Be
13
The fig. 8 shows the total power dissipation of the device.
For Vout >5V the output current can be less then 1.5A. In fact we have to consider that the maximum power dissipation for this device is 2W at Tamb of 70° and is this value that limits the output current value.
Figure 8: Power Dissipation vs. Input Voltage.
Pd IlJ)
1.8
1.6 '\.
1.4
119tL 4963·28
Vo.Vref
/
/ Io,,1.5A
/
/
/
/'
/
V, 10 ·lA
V
./
- 1.2
~,/
10
20
30
40
50 ViIV)
12
- 11
------ 1(3
-- f.--
--- 9
8
10
20
313
413 V i I V)
Figure 7: Quiescent Drain Current vs. Supply Voltage (100% Duty Cycle)
1191L4963-B9
Iq
ImA) 14
13
12
--- f...-
- --- f...-
EFFICIENCY The system efficiency is expressed by the following formula.
'11%P=o- 100 Pi
where Po = Vo 10 (with 10 = Iload) is the output power to the load and Pi is the input power absorbed by the system. Pi is given by Po plus all the other system losses. The expression of the efficiency becomes threfore the following.
'1P1o= +~ Ps~ at +~P~qP~ +o~ Ps- w +-P= D - + P~L
The three terms concerning the device power losses have already been discussed in the previous paragraph. We examine now the last two terms concerning the external components losses.
11
PO - Losses due to the recirculation diode
These losses increase as Vi increase, as in this
113
case the ON time of the diode is greater.
9
PD = VF . 10 . Vi - Vo = VF· 10 . ( 1 - -Vo )
8
Vi
Vi
10
213
30
413 V i I V)
where VF is the forward voltage of the recirculation diode at current 10.
- - - - - - - - - - - - - - l i i i 6-/17--------~----
~~~~mg,r::U!~::
400
APPLICATION NOTE
Figure 9: Efficiency vs. Output Voltage
f1!31L436J-24
"C
(% )
913
---b
/~ V
Lo lS8uH Lo 108uH
80
~ ~
LoB8uH
W Lo4GuH
78
1001. SA
OoBY~98
Uio45U
-
Au to Oscillating
18
28
38
lJout
Figure 10: Efficiency vs. Output Current
t1!3JL4963-23
"C (% )
DIODE BY~9B
lJo=l)ref
98
88
UIN-1SU
78
UIN 30U
58
0.5 8.7 0.9 1.1
PL - Losses d~e to the coil
1.3 10 (AI
Wecan divide these losses in two parts: core losses and copper losses.
The core losses for molypermalloy powder cores are given by the following formula.
Figure 11: Powerdip 12+3+3 Pin Connection
W = 0.568 , f1.23 . 82.56
where W = wattllb f= KHz
(Vi - Vo)·Vo·10B
8 = KGauss =
N
.
Ae·
f
.
V' I
N = number of turns Ae = core cross section (cm2)
copper losses: P - pl20 MLT.N
N = number of turns
MLT = lenghtlturn for 20% of winding factor p = copper resistivity (1.721 OE-6Wcm)
Refer to table 1 for some p/Aw suggest values.
Table 1
AWG
18 19 20 21 22
Diameter Copper
(em)
.102
.091 .081 .072
.064
OHMS/CM OHMS/CM
20C
100C
.000209 .000264 .000333 .000420 .000530
.000280 .000353 .000445 .000561 .000708
Typical efficiencies obtained with the test and application circuit of fig. 20 are shown below.
DEVICE DESCRIPTION
Fig.11 shows the pin connection of the Powerdip 12+3+3 plastic package. The internal block diagram of the device is shown in fig.1. Each block will now be examined in detail.
SIGNAL SUPPLY VOLTAGE OUTPUT
SUPPLY VOLTAGE GNO GNO GNO
P.FAIL INPUT P.FAIL OUTPUT
RESET DELAY
R OSCILLATOR FREQ. C OSCILLATOR INHIBIT INPUT GND GND GND FEEDBACK INPUT REFERENCE VOLTAGE RESET OUTPUT
ff9tL4963-82
-------------- LW ~~~~m~~:U!~l: --------------7/17
401
APPLICATION NOTE
POWER SUPPLY The device has two separate pins dedicated for the supply source. Pin.1 is for the Signal (Vcc) and Pin.3 for the Power (Vss) source; normally these two pins are connected together (see the typical application circuit Fig. 18). The L4963 is provided with an internal stabilized power supply that feeds the precise internal voltage reference 5.1 V (±2%) and the internal analog blocks.
UNDER VOLTAGE LOCK OUT (UVLO) The UVLO circuit ensures that Vcc is adequate to make the L4963 fully operational before enabling the output power stage. The UVLO turn-on and turn-off thresholds are internally fixed at 8.4V and 7.9V respectively. This function acts also on the Power Fail and Reset Circuits; their output voltages pin.8 and pin.10 respectively, remain low state until the turn-on threshold is reached.
OSCILLATOR The oscillator circuit behaves in a completely different way compared to the usual Step-Down regulator operating at fixed frequency and variable duty cycle. In fact, usually, the oscillator generates a fixed frequency sawtooth waveform that .is compared with the Error Amplifier output voltage/ generating the PWM signal to be sent to the power output stage. In the L4963, the oscillator function is quite differ-
Figure 12: Oscillator Circwit
ent. In the following we will describe briefly its
operatio.n referring to the simplified interrial sche-
matic shown in fig.12.
It is composed of a comparator (with inputs com-
patible to ground) with an hysteresis whose thre-
sholds are 1V and 4.1 V respectively.
The oscillator uses an external resistor RT on
pin.18 to establish the charging and discharging
current of the internal timing capacitor CT = 50pF,
fixing in this way the maximum switching fre-
quency;
0.033
fosc(KHz)= Rt (KQ)
It is also possible to increase the internal timing capacitor value, connecting an external capacitor
between pin.17 and ground. The oscillator circuit, as we have seen in the "CIRCUIT OPERATION" paragraph, sends a set pulse to the latch that enables the power stage. This set pulses train is at fixed frequency imposed
by the external resistor when the device operates for low output currents (Dead time present in the inductor current IL). When we are operating in self-oscillating mode, the comparator that senses the free-wheeling status disables the oscillator pulses output until the inductor is fully discharged, varying in this way the switching frequency. It is also possible to
disable the osci!lator forcing the system to operate always in, self-oscillating mode, connectingtogether the internal oscillator capacitor (pin.17) with the voltage reference pin.11.
Ui
3
1. 25U
INH 18 IT
RT
1192RN45B-8?
8-/1-7-------------------------~~~~~~~:9n ---------------------------
402
APPLICATION NOTE
CURRENT LIMITATION Output overload protection is provided by a current limiter circuit. The load current is sensed by an internal metal resistor (Rs) in series to the power transistor. When the voltage drop on the sense resistor, reaches the current comparator offset voltage, the current comparator generates a reset pulse for the latch, disabling the power stage. Typical current limiting threshold is around 4.5A. The power stage will be enabled again only when the energy stored in the inductor will be completely discharged, this due to the free-wheeling sense comparator (see Circuit operation paragraph for details). The current limiting circuit operates also as softstart during the device turn-on preventing overcurrents on the load. In fig.13 is shown the simplified internal schematic circuit of the current limiter.
Figure 13: Current Limiter
"92RH"5B-BB
Figure 14
RESET
The reset circuit accomplishes a very important function when the L4963 is used in applications where it feeds microprocessors and logic devices. The function block diagram is shown in Fig.14. The Reset circuit monitors the output voltage and generates a logic signal when the output voltage is within the limits required to supply correctly the microprocessor. This function is realized through three pins: · Feedback input (pin.12)
· Reset delay (pin.9)
· Reset output (pin.1 0)
When the monitored voltage on pin.12 is lower than 5V, the comparator (A) output is high and the reset delay capacitor is not charged because the transistor 01 is saturated, also the transistor 02 is saturated, mantaining the voltage on pin.1 0 at low level. When the voltage on pin 12 exceeds 5V, the transistor 01 switches off and the delay capacitor (Cd) starts to charge through an internal current generator of about 11 OIlA. When the voltage on pin 9 reaches 4.5V, the output of the comparator (B) switches low and pin 10 goes high. As the output is an open collector transistor (02), a pull-up external resistor is required.
On the contrary, when the Reset input voltage goes below 5V, with an hysteresiS of 100mV, the comparator (A) triggers again and sets istantaneously the voltage" on pin 10 low, therefore forcing to saturation the 01 transistor, that starts the fast discharge of the delay capacitor. As shown in the block diagram, the Reset output is low when the UVLO or The INHIBIT signals are present. Inside the chip there is a digital filter that prevents the Reset circuit activation if Vout drops below the reset threshold for less than 2s. In this way the Reset circuit neglects very fast drops in the output voltage. In fig.15 and Fig.16 are shown respectively the Reset circuit Waveforms and a typical application.
9
Cd::c
12
"92RH45B-B9R
----------------------------- ~~~~~~~~:oo~~ ---------------------------9-/1-7 403
APPLICATION NOTE Figure 15
Ui
RISING P.FAIL r-------------~ THRESHOLD
TURN-ON THRESHOLD__ _ L-~ ___________________~___TURN-OFF THRESHOLD
P.FAIL OU~
Uo-5.1U
RISING RESET THRESHOLD
· ~ ·· ·· 5U
.'. 199mU
, : FALLING', ~HISTERESIS
, RESET : .
: THRESHOLD: :
OUTPUT RESET
.;;-----.;!-
~
tdr
tdr
DELAY RESET
If91LoI96S-33
Figure 16
Ui C1
GND
POWER FAIL
R4
TP2
R3
138 11
2 t -. . . .. . . . r v v ' - - + - - - + - + - - -U- , ,oo- U r e f
L4953
R5
13.14.15
9 18 4.5,6
INHI8IT
C2
R2
I1!HL4963-3B
10/17
-----------------------------
~.~~~~~~~~~~
-----------------------------
404
APPLICATION NOTE
POWER FAIL
The Power-Fail circuit monitors the supply voltage (Vss) via an internal voltage divider (Rl =115Kn, R2=35Kn) as shown in Fig.l? When the supply voltage reaches the typical rising threshold voltage of 22V, set by the internal voltage divider, the Power Fail comparator output voltage goes low, turning off the output transistor Ql. This gives an high level on pin.S. As the power Fail output is an open collector transistor (Ql), an external pull-up resistor is required.
The Power Fail output goes low, giving an alarm signal, when the input voltage decreases reaching the internal typical Falling threshold voltage level of ISV. It is possible to change the rising and the falling threshold voltages, connecting a proper external voltage divider on pin.? In fig. 15 are shown the power fail waveforms.
INHIBIT
The INHIBIT function, available on pin.16, disables the regulator with a TTL logic signal. An high level at this pin (above 2.2V) switches off the power stage and forces low the output reset. This useful feature, is normally used for supply sequencing and remote control ON-OFF.
Figure 17
THERMAL PROTECTION
The thermal protection function, operates when the junction temperature reaches 150aC; it acts directly on the power stage, turning it immediately off. The thermal protection is provided with hysteresis and therefore, after an intervention has occurred, it is necessary to wait for the junction temperature to decrease of about 30a C below the intervention threshold.
APPLICATIONS
The L4963, thanks to the reduced external component count represents a very low cost effective solution in many applications.
In Fig.1S the complete typical application circuit is shown, where all the functions available on the device are being used. In fig.19 is shown the same application circuit for reduced filter capacitor count and its PCB. As evident the PCB dimensions are reduced. Below we will describe the design procedure to follow and some suggestion regarding the external components to use.
Uss
115K 7
35K
P.FAIL
tf92f1N458-tB
-----------------------------
~~~~~~~~:~~
11/17
-----------------------------
405
APPLICATION NOTE Figure 18: Test and Application Circuit
Ui 11313uF
GND
POWER FAIL 1K
1
11 1K
16
INHIBIT 2.2uF
3 8
12
2
L4963
13.14.15
18 4.5.6
51K
Uo: 12U Uo: 15U Uo: 18U Uo: 24U
Rx · 6.2K Rx · 9.1K Rx · 12K Rx · 18K
1K
1f91L4963-34
Uo RX 4.7K
PART LIST
C1 C2 C3, C4, C5 C4
R1 R2 R3 R4 R5,R6
CAPACITOR 1000flF 50V EKR (*) 2.2flF 16V 4700flF 40V EKR 1flF 50V film
RESISTOR 1KQ 51KQ 1KQ 1KQ
see table
Resistor Values for Standard Output Voltages
Vo
R6
RS
12
4.7Kn
6.2KQ
15
4.7Kn
9.1KW
18
4.7Kn
12KW
24
4.7Kn
18KW
Diode: BYW98
Core: L = 40flH Magnetics 58121-A2MPP
34 Turns O.9mm (20AWG)
n Minimum IOOflF if V; is a preregulated offline SMPS output or 1000flF if a 50Hz transformer plus rectifiers is used.
12/17
-----------------------------
~~~~~~~:~~~
-----------------------------
406
Figure 29: Typical Application Circuit
APPLICATION NOTE
Ui C1
GND
POWER FAIL
R4
TP2
R3
1 3 8 HI 12 11
2
L4963
16
9
13.14.15 18 4.5.6
INHIBIT
C2
R2
LI (*1
f19tL4963-3B
PART LIST
C1 C2 C3 C4
R1 R2 R3 R4 R5,R6
CAPACITOR 1000~F 50V EKR (*) 2.2~F 16V 4700~F 40V EKR 1~F 50Vfilm
RESISTOR 1Kn 51Kn 1Kn 1Kn
see table
Resistor Values for Standard Output Voltages
Vo
R6
RS
12
4.7Kn
6.2Kn
15
4.7Kn
9.1KW
18
4.7Kn
12KW
24
4.7Kn
18KW
Diode: BYW98 Core: L = 40lJ,H Magnetics 58121-A2MPP
34 Turns 0.9mm (20AWG)
(.) Minimum 100llF if V; is a preregulated offline SMPS output or 1OOOIlF if a 50Hz transformer plus rectifiers is used.
---------------------------
~~~~~~~~~~
13/17
---------------------------
407
APPLICATION NOTE Figure 20: P.C. Board and Component Layout of the Circuit of fig. 21 (1:1 scale).
L4963 Step-Down Regulator Design Example
Referring to the complete typical application circuit shown in fig.19, and defined the following conditions: · Vout = Regulated output voltage
· Vin(min)= Minimum input voltage
· Vin(max) = Maximum input volt'!-ge
· lout(max) = Maximum load current
· fmin = Minimum switch freq. in self-oscillating
mode.
.
We calculate the value of the external components. .
1. OUTPUT VOLTAGE SETTING:
The output voltage is established by the voltage divider constituted by R5 and R6. To select the right R5 value use the following formula:
R5 = (Vout-Vrel) . (R6) Vrel
where: Vrel= 5.1V R6 = Is normally set at 4K7Q
For a Quick calculation of some standard output voltages, the following table is useful;
Resistor Values for Standard Output Voltages
Vo
R6
R5
12
4.7Kn
6.2KW
15
4.7Kn
9.1KQ
18
4.7Kn
12KQ
24
4.7Kn
18KQ
To obtain Vout = Vre!, the pin.12 is directly connected to the output, therefore eliminating both R5 and R6.
2. INDUCTOR SELECTION:
The max. duty cycle is determined by the following formula:
Dmax
=
Vout + VF :V-;i-n-(-m--i'n-")"7- -;'V--e'-e'-(-s-a--t)--+--:V-cF:-
Where: Vee(sat) = 1.5 V VF = Catch diode forward drop
The maximum inductor value is then calculated:
L max = (Vin(min) - Vee(sat) -. Vout) . D max 2 . lout(max) . f(mln)
where: f(min) 20KHz to be out of the audible range.
In discontinuous mode operation, the inductor current may reach very high peaks (lPeak = 2Iout), so it is important to verify that the coil will not saturate in overload or short circuit conditions damaging the output power stage due to the high dl/dt ratio. Therefore, a correct dimensioning requires a saturation current above the maximum current limit threshold (12max - peak = 6A).
1-4-/1-7 -----------------------~~~~~~T:9~ --------------------------
408
APPLICATION NOTE
3. Output Capacitor Selection:
The output voltage ripple depends on the current ripple in the inductor and on the performance of the output capacitor at the switching frequency .The minimum value of the output filter capacitor is obtained from:
Cout(min) = -4:-.-:V-:ri-p"lpo"lu"e,t(("pm"-"-ap"x)')''.''f-m-:-in:-
where Vripple(p-p) is the amount of ripple voltage desired.
Clearly this formula doesn't take care of the capacitor Equivalent Series Resistance (ESR) value, that is the dominant factor to define the output ripple voltage at switching frequencies greater than 20KHz. So we suggest to use also the following formula:
ESR(max) = Vripple(p-p) 2 . lout(max)
Where the ESR(max) requirement is not satisfied by the capacitor value given by the first formula, use an higher value or, better, put in parallel several capacitors in order to reduce the total ESR. The capacitors' voltage rating should be at least 1.25 times greater than the given output voltage. The big advantage of this system is to greatly reduce number of external components compared to the continuous mode solution. The only drawback is a higher ripple voltage on the output that can be up three times larger than in continuous mode. A proper choice of low ESR filtering capacitors
can solve this problem greatly reducing the output ripple.
4. CATCH DIODE SELECTION:
The catch diode must comply with several requirements and its choice requires special care. The current rating must be at least 1.2 times greater respect the maximum load current, but this is not enough because in short circuit conditions, the maximum current limiter threshold is 6A to which correspond an average output current of lout = Ipeak/2 = 3A. This is the current requirement to useto choose the right diode. The reverse voltage rating of the diode should be at least 1.25 times the maximum input voltage. The diode recovery speed is not so important because the power stage is turned-on only when the inductor is fully discharged and the diode is definitely off. So there is not simultaneous conduction between them. This allows a reduction of the disturbances with respect to the continuous mode, because they are mainly radiated during the transistor switch on, for the steep slopes during the simultaneous conduction of transistor and reverse conductiondiode.
LOW COST APPLICATION
If the remote inhibit, the reset and the power fail functions are not used we can reduce further the external component count. It is possible in this case, to have a very efficientswitch mode power supply for very low cost applications. Two examples of minimal component count regulators are shown in fig.21 and fig.22.
Figure 21: A Minimal 5.1 Fixed Regulator - Very Few Components are Required
lJi
1000uF 501J
12
L4963
16 18 4.5.6 13.14.15
51K Rose
GND
(*1 COUT-1888uF WITH LOW ESR
f192f1N458-tt
1uF 5131J
GND
----------------------------- ~~~~~~~~:~~n --------------------------1-5-/1-7 409
APPLICATION NOTE Figure 22: A Minimal Components count for Vo = 12V
Ui
49uH
11 :1-
Uo
HH39u 50U
16 L4963
18 4.5.6 13.14.15
51K
Rose
GND
(*l COUT.1SBSuF WITH LOW ESR
ff91L4963-32
GND
DUAL OUTPUT POWER SUPPLY
The application shown in fig.23 is interesting b?cause it provides two output voltages. The main voltage, is directly controlled by the feedback loop, the second voltage is obtained throu~h an auxiliary winding. As the auxiliary voltag.e I~ o~ tained through a completely separated winding, It is possible to obtain either a positive or a negative voltage. Where isolation is not required between
Figure 23: Multioutput isolated.
the two outputs, we can reduce the number of the
auxiliary turns improving also the tolerance of the secondary output using the configuration illustrated in fig.24.
For both this configurations, the discontinuous mode is ideal because we have a good energy transfer between primary and secondary windinn-
gs, due to the high energy stored in the coil that is function of the ripple current in the inductor.
Ui 1BBBu
5BU
GND
1 3
11
2
16 L4963 12
13.14.15
0:
51K
~ +1~F 1N5822
o
1II1II
Uo2-12U/B.1A
0 n1
Uo1-SU/1.SA
n2 Uo2.Uol 0-
nl
Po2~2B%Pol
ff9211N458-12
GND
16/17
~ SGS·mOMSON _ _ _ _ _ _ _ _ _ _ _ __
- - - - - - - - - - - - - - ...." i'lAJU©rnl@~~~©1l~@II!U©il\
410
Figure 24: Multioutput not isolated.
APPLICATION NOTE
Ui
1888u 58U
1 3
11
16 L4963
r---~--~---oU02.12U/9.1A
Hl8uF
- - - o 2 I-.....-.,ry-v-..~.......
Uo 1 · 5U / 1. 5A
12
51K
GND
n1+n2 U02.Uo1
n1
P02~28"P01
119211N45B-13
GND
L4963 IN OFF-LINE POWER SUPPLV
The L4963 can be useful as post regulator in offline power supplies, where it can sobstitute the
usual linear post regulation increasing the efficiency and reducing the complexity of the transform8r, if the distributed power supply approach is used (see fig.2S).
Figure 25: Typical off-line solution using L4963 as post regulator.
L 4963
1K
49uH 2 121-+----J
BVI.J9B
Uo.SU/1.SA
1999uF 16U
N92RN45B-f4 GND
-------------- -------------- £;j ~~~gr::L!l~::
17/17
411
APPLICATION NOTE
INTRODUCTION TO A 10A MONOLITHIC SWITCHING REGULATOR IN MULTIPOWER-BCD TECHNOLOGY
byC.Diazzi
The L497X series of high current switching regulator ICs exploit Multipower-BCD technology to achieve very high output currents with low power dissipation - up to 10A in the Multiwatt power
package and 3.5A in a DIP package.
Switched mode techniques led to the development of high efficiency circuits offering space saving and a reduction in costs, mainly of the heatsink and output LC filter. For these applications a new technology, called MULTIPOWER-BCD, has been developed which allows the integration on the same chip of isolated power DMOS elements, Bipolar transistors and CMOS logic.
The technology is particularly suitable for the problems rising in the switch mode field, due to the characteristics of high efficiency, fast switching speed, no secondary breakdown of the power DMOS element.
The great flexibility that we have at our disposal for the choice of the signal and driving sections components allows optimization and compactness of the system. With MULTIPOWER-BCD it has been possible to implement the family L497X, a new series of fully integrated switching regulators suitable for DC-DC converters working in Buck configuration. The complete family consists of five devices which differ each other only by the output current value (2A, 3.5A, 5A, 7A, lOA) they
can deliver to the load. The devices rated at 2A and 3.5A are assembled in Power Dip (16+2+2), while the others are assembled in the Multiwatt15 package. Each device integrates a DMOS output power stage, a control section, limiting current and supervisor functions like Reset and Power Fail signal for microprocessors applications.
Output voltage can be adjusted starting from the internal reference voltage (5.1 V) up t~ 40V, allowing a maximum output power of BOW for the 2A version and of 400W for the lOA version. Maximum operating supply voltage is 55V.
THE TECHNOLOGY
The technology architecture is based on the vertical DMOS silicon gate process that allows a channel length of 1.5 micron ; using a junction isolation technique it has been possible to mix on the same chip Bipolar and CMOS transistors along with the DMOS power components (Fig. 2). Figure 1 shows how this process brings a rapid increase in power IC complexity compared to conventional bipolar technology.
Figure 1: BCD process and increase in power ICs complexity.
Complexity (Nr.of tr.)
1~~~-.~---.-----.-----r-----.--~~----,
..... ....
-;'CD IA-D-P) ...........
Pur. an log
AN487/0592
Power blp
1965
1970
1975
1980 1985
Years
1990
1995
2000
1/11
413
APPLICATION NOTE
Figure 2: Cross section of the BCD mixed technology.
S GO o S GO
SGD DGS BE C BeE
P-CH
' -_ _----'I LI_ _ _ _---'1 L--.J I
N-CH
I LI_ _---' L-.,--_ _ _- '
HV P-CH VDMOS HV CAP C-MOS
NPN
LPNP
In the 70's class B circuits and DC circuits allowed output power in the range of 70W. By 1980 ,with the introduction of switching techniques in power ICs, .output powers up to 200W were reached ; with BCD technology the output power increased up to 400W.
FUNCTIONS AND BLOCK DIAGRAM
The complete block diagram of the high power L4970A is shown in fig.3. Each block is analysed in the following.
POWER SUPPLY
The device is provided with an internal stabilized
power supply ( Vstart =12V ). that provides the
supply voltage to the analog and digital control blocks and also the supply voltage to the bootstrap section. The Vstart voltage .supplies als~ the internal Reference Voltage section that proVides accurate 5.1 V voltage to the control loop. Through trimming techniques the 5.1 V reference is within +- 2% limits.
OSCILLATOR and FEDFORWARD The oscillator block (fig.4) generates the sawtooth
Figure 3: Block diagram of the 10A monolithic regulator L4970A.
o - r SYNC
1:-:3:: - - - - - ,
VREF VSTART Vi 14 15 9
Rase
Vfa edb o-+::::rt.-
COMPo
~'-----+-t-'""VV'T"'" Va
L4970A
_________________ 2_1_1_1______________ ~~~~~~~~:~~n
414
Figure 4: Oscillator circuit.
ucco----...,--,
APPLICATION NOTE
Rose
..-I Case PWM COMPo
~
CLOCK
Figure 5: Voltage Feeforward waveform.
fl92L49?8-4?
U2
. . ----~----~----~----~--Ui-38U
--~~--~~--~~--~~--Ui=15U
Ue
LJ--H-+-H---l--++--I--H-+--+ t
U7
'+I---if-- Ui = 38U
...-~-t-- Ui .15U
'---'--+ t fl91L49?8-8?
waveform that sets the switching frequency of the system. The signal, compared with the output voltage of the error amplifier, generates the PWM signal to be sent to the power output stage. The oscillator features a voltage feed-forward technique which is completely integrated and doesn't require any external component. Feed-forward function works in the supply voltage range 1545V. The rate of increase of the sawtooth wavwform is directly proportional to the input volt~ge Vcc. As Vcc increases, the output pulse-width (transistor on-time) decreases in such a manner as to provide a constant "volt-second' product to the inductance(fig.5).
From fig.5 it is shown that the duty cycle changes due to the ramp increase when Vcc increases. The error amplifier output doesn't have to change to keep the loop in regulation. This feature in-
creases significantly the line regulation performance.
A resistor, between Rosc and GND , defines a current that is mirrored internally to charge the oscillator capacitor on the Cosc pin. The voltag~ at pin.Rosc is a function of Vcc value .for the .Implementation of the feed-forward function (oscllI~ tor slope proportional to Vcc). A comp~rator IS sensing the voltage across Cosc capacitor and discarge it when the ramp exceedes an upper threshold proportional to Vcc f.or the implemen~a tion of the feed-forward function. The Cosc dis-
charge current is internally controlled at a value of about 20 mA. The lower threshold of the comparator is about 1.3V (2VBE). Here are reported basic equations for the oscillator:
Vce - 9VSE
leHARGE =
for 15VsVees45V (1)
Rose.
~ SIiS·THOMSON _ _ _ _ _ _ _ _ _ _ _ _3/1_1
- - - - - - - - - - - - - - - - - - - - - - - - - - - .... , / 1iIl~l<:iR@~~~i:'ITIil@Ill~I<:~
415
APPLICATION NOTE
IDISCH == 20mA
(2)
VTH.HIGH -- Vcc -99VBE + 2VBE for 15V s;
~Vcc s; 45V
(3)
VTH. LOW = 2VBE
(4)
9
.FSWITCH == Rosc. Cosc.
(5)
Note that formula (5) does not take in account the discharge time of Case, that is not negletable working at high FSWITCH (200 KHz), and that is dependent on Case value.
( VTH.HIGH - VTH.LOW ) . Case.
T DISCH. =
20mA
(6)
By which:
FSWITCH =
(7)
Rose Case 9
+
T DISCH
During the discharge time of Cosc a clock pulse is generated that is available on pin.SYNC and that can be used to synchronize max 3 devices of the same family. See also fig. 6 and fig. 7 for the switching frequency versus value of R4 (Rose).
PWM
The· comparison between oscillator sawtooth and error amplifier output generates the PWM signal that feeds the driving stages. A PWM latch structure is implemented to avoid multiple pulses that could be dangerous for the power stage. A maximum duty cycle limitation is implemented in the PWM stage. Such limitation is obtained by the synchronization pulse 'generated in the oscillator section during the Cosc discharge time. When the pulse is present the driver is inhibited. In this way even if the error amplifier output completely overcomes the oscillator sawtooth, the power stage can not work in DC conditions, but is switched off
during the clock pulse allowing a maximum duty
cycle tipically in the range 90 - 95 %
SOFT START
Soft start (see fig.S) is an essential function for correct start-up and to obtain a monotonically increasing output voltage, without overstressing the output power stage. Soft start operates at the start-up of the system and after the intervention of thermal protection. The function is realized through a capacitor connected to soft start pin, which is charged at constant current(about 100uA) up to a value of about 7V.
During the charging time. , through PNP transistor 01 the voltage at the output of the transconductance amplifier is forced to increase with the same rising speed of Css capacitor. As the capacitor is charged, the PWM signal begins to be generated
as soon as the error amplifier output voltage crosses the ramp; the power stage starts to switch with steadily increasing duty cycle (fig.9).
The eharge of the soft-start capacitor is started every time the system begins to work after an anomalous condition occurred (undervoltage and thermal protection). The Css discharge current is in the range of about 20mA.
Figure 6: Switching frequency vs. Rose
(L4970A/77 Al75A).
fSlJ
!19JL 4978-42
1KHz)
C9·nF
588
2G8 18B 50
20
18 18 28 38 48 58 58 78
R4IK)
Figure 7: Switching frequency vs. Rose
(L4972A174A).
fSlJ 1KHz)
I C9.nF
t191L49?2 1?
5GG
28G 1GB 58
I'--.. 1.2nF
~;; :::: I'.... r-I
l ' ~
............... ~.5nF
...............
2.2nF
-- ~4.~
1-1
3.3nF
28
1B 18 28 30 48 58 68 70
R4IK)
416
Figure 8: Soft start circuit.
1 Iss
TRANSC. ERROR AMPL.
:1>-i UNOERUOLTAGE PROT.
~--~r-------~Q1
THERMAL PROT.
APPLICATION NOTE
PWM COMPo
Css ~ Figure 9: Soft start waveforms.
f/92L4!1?8-4811
CLAMPED ERROR AMPLIFIER
OUTPUT
- - - - - -.r!.~---7f-I---:.H-
OUTPUT CURRENT
SOFT START TIME
t
t
f151L45?B-BB
Figure 10: Error amplifier circuit.
18K
2.SK
1 ~---t:: 4
TO PWM COMPo
-----------------------------
~~~~~~~~:~~~
5/11
-----------------------------
417
APPLICATION NOTE
UNDERVOLTAGELOCKOUT The chip features a complete built-in under voltage lock out protection, keeps the power output stage off up to the moment Vcc reaches 11 v, with an hysteresis of 1V. After reaching the 11 V value the system starts with the soft start feature.
ERROR AMPLIFIER The error amplifier is a transconductance Operational Amplifier featuring a current output. The simplified schematic is represented in fig.1 O. The basic characteristics of the uncompensated operational amplifier are the following: - GM = 4mAJV, - Ro = 2.5Mohm, - Avo =80dB, - Isource/sink = 200f1A - Iinput Bias Current = O.3f1A The frequency behavior of the uncompensated amplifier is reported in fig.11.
Figure 11: Open loop gain (error amplifier only).
Av(dBl
88 -1----;..
48
by which
Ro Av(s) = GM . 1 + SRo Co
where Co = 3pF.
The error amplifier is inserted in the regulation loop and can be easily compensated, thanks to its high output impedance, with a network between its output and ground. The typical compensated network is shown in fig.13.
Figure 13: Compensation network of the error amplifier.
AMP.
n92L.f9?B-58
Rc
:::c Cc
The transfer function is:
A v
) (8
~
G M'
s2
RD
CD
Re
RD (1 + S Re Ce) Ce+ S (RD Ce+ RD
CD
+
Re
Ce)
+
1
In the hypoteSis that Rc<Ro and Cc>Co, the Bode diagram of the compensated amplifier is reported (see fig.14).
Figure 14: Bode plot showing gain and phase of compensated error amplifier.
Gv (dB)
UNCOMPENSATED
f
f192L49?B-5B
Neglecting the high frequency behav.ior (in the hypotesis that in the overall frequency compensation of the loop the second pole of the operational amplifier is far below the 0 dB axis), we can make a first order approx. by which the error amplifier can be schematized by the equivalent circuit of fig.12.
Figure 12: Error amplifier equivalent circuit.
v + ----0
v - --;;;L.
f192L49?fJ-5!
~~---k----~----~-------135
~------+----~~---+-~----- 98
2TTRoCc 2TTRcCc 2TTRoCo 2TTRcCo
1192L49?IJ-S9
The compensation network introduces a low frequency pole and a zero that usually is put at the frequency of the resonant pole of the output LC filter. The second high frequency pole is usually at a frequency of no interest. If needed , more sophisticated compensation circuits can be used by feedback with the opamp. An example is shown in fig.15.
6/11
-----------------------------
~~~~~~~~:~~
-----------------------------
418
APPLICATION NOTE
Figure 15: One pole, two zero compensation network.
C2
~UREF
I
N!J2L4!J?B-52
Such a configuration introduces a low frequency pole and two zeros Z1 = 1/2TIR1C1 and Z2 = 1/20R2C2. Note that due to the high output impedance it is present also a second pole p2 = gm/2TIC1. Usually it is better to use the highest possible value for R1, to have a low value for C1 in such a way to put p2 at the highest frequency. Limitations to R1 value are put by offset voltage due to opamp. input bias currents.
If a resistive divider is used at the output of the power supply, for voltages higher than 5.1 V, it is possible to introduce a second zero with the network of fig.16.
Figure 16: Compensation network for output voltages higherthan 51 V.
APPLICATION EXAMPLE
Consider the block diagram of fig.17, representing the internal control loop section, with the application values: Fswitch = 200KHz, L = 100~H, C =1 OOO~F, Po=50W, Vo =5.1V, 10 =10A and Fo = 500Hz.
Gloop = PWM . Filter
Figure 17: Block diagram used in stability calculation.
UREF ·
Uf
typ. 12
!
1192L.t97B~5.tn
Figure 18: Frequency behavior of the circuit of fig 17.
dB Io-1I3A
Uo C1
1192L49;'8-53
Rc
J: Cc
Such a configuration introduce 2 zeros at:
1
1
Z1 = 2TI Re Ce ; Z2 = 2TI R1 C1
and 2 poles at:
P
1
P2 = 1 . Rx = R1 R2
1 = 20 RaCe;
2TI Rx C1 '
R1 + R2
/f92L497B-S5
The system requires that DC gain is maximum to
achieve good accuracy and line rejection. Beyond
this a bandwidth of some KHz is usually required
for a good load transient response. The error am-
plifier transfer function must guarantee the above
constraints. A compensation network that could
be used is shown in fig.19.
A
( 1. + SR1 C1 ) (1 + SR2 C2 )
(s) =
C1
SR1 C1 ( 1 + s GM)
Figure 19: Compensation network.
--------------
A."'!I ~ SWluG!:ISff·il@l~t~rOn~Mmru@SlIO!luN~$
7/11
--------------
419
APPLICATION NOTE
Figure 20: Bode plot of the regulation loop with the compensation network of fig. 19.
. dB .
.... .. · ACSJ ~
Gloop
"
49
"j""........- ""... . PWMtFILTRO ". --',<:.~"~
,.......... .
58Hz
588Hz
58Kz 11!12U!l78-56
The criterium is to define Z1, Z2 close to the resonant pole of the output LC filter. The Gm/2DC1 pole must be placed at a frequency at which open loop gain is below 0 dB axis (Fig. 20).
CURRENT LIMITATION Current limitation is implemented intrnally to the chip and doesn't need any external component.
Figure 21: Current protection circuit.
The output current is sensed by an internal resistor in series with the drain of the power transistor. On chip trimming guarantees ±10% accuracy on the value of peak current limitation.
Current limit protection works pulse by pulse with lowering of tnhe switching frequency. Fig.21 shows circuital implementation of current protection.
--~-----+------~Ucc
Rs
MASTER CLOCK
S
POWER TRANSISTOR
Q
R
JlJl
TO SWITCH OFF POWER STAGE
1192L4978-57
8-/11- - - - - - - - - - - Gi'l SCiS-TlfOMSON · J, ~~©U1@rn~rnC1fUl@Il!U©@
420
APPLICATION NOTE
When the comparator senses an overcurrent, the flip-flop is set and an internal inhibit signal is generated. The flip-flop remains set until next reset clock pulse coming from the internal 40 KHz oscillator. After the reset pulse the regulation loop takes the control of the system and the output current begins to increase to the load value at the switching frequency of the master clock. If the overload condition is still present the protection cycle repeats. This mixed, pulse by pulse, lowering frequency current protection method, assures a constant current output when the system is in overload or short circuit and allows to implement a reliable current limitation even at high switching frequency (500 KHz) reducing the problems of signal delay through the protection stage. Fig.22 shows behavior of the inductance current when the system is in overload.
Figure 22: Overload inductance current.
Figure 23: Power fail and reset circuit.
The internal 40 KHz oscillator is synchronized with the master clock. When the system works with the master clock at a lower frequency of the internal clock, than the internal clock tracks the master frequency. This assures that the frequency does not increas during overload.
POWER FAIL-RESET CIRCUIT
The L4970A include a voltage sensing circuit that may be used to generate a power on power off reset signal for a microprocessor system. The circuit senses the input supply voltage and the output generated voltage and will generate the required reset signal only when both the sensed voltages have reached the required value for correct system operation. The Reset signal is generated after a delay time programmable by an external capacitor on the delay pin. Fig. 23 shows the circuit implementation of Reset circuit. The supply voltage is sensed on an external pin, for programmability of the threshold, by a first comparator. The second comparator has the reference threshold set at slightly less the ref. voltage for the regulation circuit and the other input connected internally at the feedback point on the error amplifier. This allows to sense the output regulated Voltage. When both the supply voltage and the regulated voltage are in the correct range, transistor Ql turns off and allows the current generator to charge the delay capacitor. When the capacitor voltage reaches 5V the output Reset signal is generated. A latch assures that if a spike js present on the sensed voltage the delay capacitor discharges completely before initialization of a new Reset cycle. The output gate assures immediate take of reset signal with-
o
R~Ji'~~ __________ ~
5V
------------------------------ ----------------~------------ ~~~~~~~~:oo~n
9/11
421
APPLICATION NOTE Figure 24: Reset and power fail waveforms.
RISINIiz P. FAIL THRESHOLD
TURN-ON
THRESH.
,t
5.1V lOOmV H1----HfSTERESIS
RESET OUT
to
DELAY RESET
out waiting for complete discharge of delay capacitor. Reset output is an open collector transistor capable of sinking 20mA at 200m V voltage.Flg. 24 shows reset waveforms.
THE POWER STAGE A simplified schematic of the output ,stage alo~g with the external filter components IS shown In fig.25. Figure 25: Power stage circuit.
POWER FAIL TIME
Power stage and associated driving circuits are among the most critical components to achieve good performances at 'high switching frequency. An external bootstrap capacitance, charged via diode 01 at 12V, is needed to provide the com~ct gate drive to the power OMOS N-channel transIstor. The driving circuit is able to deliver a current peak of O.5A, during turn on and turn off phases, to the gate of power OMOS transistor. The circuitdescribed shows commutation times of 50ns.
~--+-------------------------~----~ Vee
REF. 12U
VOLTAGE
D1 ~
C BOOTSTRAP
FROM PWM COMPo
J1JL
10/11
422
L49?B
l:W ~~~~!tl~::~y~~ ------------------
The five devices of L497X family differentiate each other only for the level of current protection, while the control part is the same and power device area is the same to guarantee low power dissipation also for low current versions in DIP package.
Table 1 and fig.26 shows electrical characteristics of the power DMOS implemented in the chip.
THERMAL PROTECTION
The thermal protection function operates when the junction temperature reaches 150°C; it acts directly on the power soft start capacitor, discharging it. The thermal protection is provided with hysteresis and therefore, after an intervention has occurred, it is necessary to wait for the junction temperature to decrease of about 30 degree C below the intervention threshold.
Table 1.
Bvoss > 60V ROSION) = 100mQ ROSION) = l50mQ VTH = 3V
at 10 = lmA at 10= lOA at 10 = lOA at 10 = lmA
APPLICATION NOTE
Figure 26: Gate-charge curve for the power
DMOS.
1189L49?8·36
Ugs
I U)
UDSo4GU
12
/
/
/
/
//~
113
//~
8
~ ~
6 4
V' lGA
SA
/ 1A
2 /
8
16
24 DglnC)
Tj = 25°C Tj = 150'C
VGS= OV VGs= tOV VGs= 10V
423
APPLICATION NOTE
SIMPLIFIED SWITCH-MODE BASE DRIVE CIRCUIT WITH THE L4974 SMARTPOWER-IC
INTRODUCTION
Conventional driver circuits for bipolar-junction-transistors and Darlingtons have a high power dissipation. In order to reduce this dissipation, switch-mode driver stages have been proposed1. A new, very simplified driver stage, taking advantage of the switch-mode principle is presented here. It has been designed around smartpower-IC L4974. The efficiency of the IC is so high, that even with a 4 Amp base-current, the smartpower device is housed in a DIL-package ... ! Bipolar-junction-transistors need negative bias in order to obtain fast turn-off switching and a good immunity against reverse conduction followed by dv/dt. This driver circuit generates the negative bias
Figure 1 : Dissipative Driver Circuit.
By Klaus RISCHMUllER
internally - it can be supplied from a single, unregulated source.
The new configuration can be used to simplify and improve existing converter/inverter circuits (less auxiliary supplies, less heatsinks and higher efficiency).
CONVENTIONAL BASE DRIVE VIS S\AfITCHMODE BASE DRIVE
Conventional base driver circuits draw base current from an auxiliary supply voltage between 6 to 12 Volts. The base-current amplitude is limited by means of resistors or dissipative current sources. (figure 1) Such a base driver has a very low efficiency. The power transistors base-emitter voltage is about 1V, but 5V to
Tr.
]
IVUlMJl Vaux
4A
---r 6... 12V
C J-
Tp
. l_~~_
SC-l024
During permanent conduction with a 4A-base-current, the transformer Trs has to supply a power of 56W. About 90% of this power is dissipated in the driver circuit.
\N36410689
114
425
APPLICATION NOTE
11 V are dropped inside the driver circuit. Applying the switch-mode·principle to base driver circuits, substantial energy savings can be made. Auxiliary power supply and heatsinking costs can be greatly reduced.
HOW IT WORKS
Figure 2 shows the principle of such a switch mode driver circuit. A smartpower-IC with a MOSFET output-stage operates as a buck regulator in currentmode. During the off-state of the power transistor, TP - figures 1-4., a MOSFET, T1, applies a short-
Figure 2 : Simplified Switch Mode Driver Circuit.
circuit to the output of the buck regulator. Thus, the smartpower IC operates with reduced duty cycle and maintains a constant current in the choke L. In order to tum-on power transistor TP, the MOSFET T1 is turned off and the constant choke-current flows into the power transistors base. The rate of rise of base current is only limited by the MOSFET turn-off speed. In order to obtain very fast switching, high density MOSFETs (STVHD 90) with very low input capacitances have been used in the circuii.
Tr.
Vaux
leI
20. 40V r - ----,
:Il~ I
I
I
1
I
I
I
I
I
ff
1
I
I
L,_~ _ _, _ . J
DZ
3.GV
sc- '015
n OFF
ON _I L
()-,---4------------'
With an input voltage of 20V and a base current of 4A, the transformer supplies about 1OW to the driver circuit. No device in the driver circuit has to be cooled with a heatsink.
During the on-state, the driver circuit input current can be estimated using the term 2 · IB * VBElVaux, where IB is the base current, VBE the base-emitter voltage and Vaux the voltage of the auxiliary supply.
If the power transistor base·current is 0.5A. and the auxiliary supply voltage 20 Volts, the driver input current will be about 0.5 Amps. If the auxiliary supply voltage is increased, the input current will be further reduced.
NEGATIVE; BIAS OUT OF POSITIVE SUPPLY
The negative bias for fast turn-off switching can be generated by various means.
A zener diode can be connected in series between auxiliary supply and driver stage, Oz (figure 2). The potential at the zener diode anode is negative compared to the emitter potential of the power transistor. The losses in the zener diode are low, due to the re-
duced input current of the switch-mode base drive.
For turn-off switching, T1 and T2 are turned on. T1 applies a short circuit to the buck regulator output, T2 applies the negative bias to the power-transistor base.
It is also possible to generate a negative bias directly from positive auxiliary supply:
A capacitor C1 (figure 3) is permanently charged via a resistor R1 and a diode 01. At turn-off switching, T2 is turned on for a short time t1 . This time has to be chosen to have a value slightly higher than power transistor's storage-timets. T2 connects the positive electrode of C1 to ground during t1. Thus a negative voltage is applied .to ·the base during turn-off switching off TP. T2 remains' 'off' after turn-off and C1 continues to be charged. The advantage of this configuration is that the state of charge of C1 is independant of du1!' cycle - sufficient negative bias is always available .
2/4
426
APPLICATION NOTE Figure 3 : Modified Circuit with Dynamic Self-generation of the Negative Bias.
Tr.
]
3300
r------,
+ - - 1 f - TII- < ; > - , I
I I
1 1
I I
I
1
~"Ji;:21 1
1
I. I 1
'1'1
1-.
IN / ' 1 4148
Tp
1
1
100
+ - - - . - - - - - < > - - - 1 - - - - ----t---"---+--~
2 x
1N4001
sc- 1026
OFF ONJL
SL
I I
3ys
The capacitor C1 is charged during the conduction and the non-conduction time of TP. Its state of charge is independant of the duty-cycle!
Figure 4: Complete Circuit Diagram for 4 Amp Base Current Supply.
Tr.
-~ j
~"~~V 2 :.""
.---1\1 L4974
.----..----- BYn3 - 1000
1 1
Tp
1000
sc -1027
The L4974 is housed in a Dual-in-Iine package - the PCB is sufficient for cooling. For higher base current, L4974 can be replaced by L4970.
3/4 427
APPLICATION NOTE
RESULTS
With a BUF 420 (a cellular ETD-transistor) in the power stage, storage-times less than 111S and falltimes lower than 25ns have been obtained when switching 20A, from a 400V supply.
The overshoot of the base-emitter voltage and the influence of parasitic inductances in series with the base are negligible due to the fact that the driver acts, at turn'on, as a nearly ideal current source. A turn-on speed dlddt for the power transistor as high as 200A/I1s has been obtained without any special design effort.
CONCLUSION
The application of the switch-mode principle to driver stages gives significant loss reduction and a very much reduced cost for auxiliary supply and heatsinking. In the past switch-mode driver circuits were considered as too complex. New smartpowerIC's allow a reduction in complexity and take advantage of the high efficiency achievable using a switch
mode circuit. The 4A-version of the driver uses a Dual-in-line IC and no heatsinks. The combination of switch-mode principle with self generation of negative bias further reduces cost of the driver and its auxiliary supply. The concept shown appears to be valid for base currents up to 20 Amps; its use for gate drive for SeR and GTO could also be investigated.
1. C.K. Patni : An efficient "Switch-mode" base drive for bipolar transistors, Internal report, SGS-THOMSON Microelectronics
2. Databook : POWER MOS DEVICES page 621 to 625 (STVHD 90), SGS-THOMSON Microelectronics
3. K. Rischmuller : Fast switching with power transistors and Dariingtons - state of the art, Application note, SGS-THOMSON Microelectronics
4. Databook : Industrial and computer peripheral IC's, page 401 to 416 (L4970), SGS-THOMSON Microelectron ics.
4/4 428
L ~
I i .. ,
S[j\GJj]SO©O-O1@~H!L~O©'jM]'OOS@!ORllNO©~
APPLICATION NOTE
ULTRA FAST NiCd BATTERY CHARGING USING ST621 0 MICROCONTROLLER
L. Wuidart, P. Richter
INTRODUCTION
Today many cordless and portable equipments are supplied by a Nickel-Cadmium (NiCd) battery. The ultra fast charging of these batteries in less than half an hour is a very attractive service for users. Such a short charging time requires an "Ultra Fast" battery, a supply with a relatively high output power, and a charge control circuit more complex than for standard chargers. Moreover, automatic battery voltage identification is an appreciable feature.
The power converter proposed in this note is able to fully charge a common NiCd battery pack of 1.2Ah/7.2V within 15 minutes. The power converter has thus a corresponding output power capability of roughly 80W. The converter operates as a current source providing a constant 7A current to the battery while charging.
The battery charge is controlled by an economical microcontroller, the ST6210, a member of the ST6 microcontroller family. The programmed control provided by the ST621 0 allows the charging of NiCd battery packs from 2 to 6 cells (2.4V to 7.2V). The supply to the microcontroller is simply generated from an auxiljary winding of the power transformer.
THE POWER CONVERTER
The asymmetrical half-bridge is today considered as one of the most attractive topologies for the primary side of a 220Vac off-line Switch Mode
Power Supply (SMPS, see Figure 1). Adding the SGS-THOMSON AVS10 kit allows the automatic sensing and adaption to input voltages in the range of 90 to 240Vac.
Contrary to single switch structures, the leakage inductance of the power transformer is much less critical. The two demagnetization diodes (BYT01/400) provide a simple non-dissipative way to systematically clamp the voltage across the switches to the input DC voltage Yin. This allows the use of standard 500V power MOSFET devices, such as the IRF830FI (in isolated ISOWATT 220 package), simply driven by a small pulse transformer.
The power converter is totally controlled from the primary side with a standard Pulse Width Modulation (PWM) control IC, the UC3845 regulating in current mode. A single optocoupler makes this SMPS operate as a battery charger. The SMPS is turned on or off from the secondary by the ST621 0 microcontroller via this optocoupler.
The switching frequency is fixed at 100kHz in order to keep the magnetic part to a reasonable manufacturing cost level. The power transformer and the output inductor can be integrated on a single ferrite core [4]. This integrated magnetic technique can be optimised to allow a Significant shrinking of the power converter size.
For more information on the power converter, refer to reference [4] of the bibliography.
AN433/0292
1/6
429
APPLICATION NOTE Figure 1. Ultra Fast NiCd battery charger schematic
- - - - - - - - - - - - f;i _2/_6___________
~~@m~~'9~
430
APPLICATION NOTE
BATIERY CHARGE CONTROL
Ultra Fast Charge Control Method
For Ultra fast charge systems - under half an hour - the majority of battery manufacturers recommend the negative delta voltage method (-/,,v) otherwise called the negative slope cut-off circuit [2] [3].
When a NiCd battery reaches full charge, its voltage decreases slightly (Figure 2). The negative delta voltage method (-/,,v) consists of stopping the charge as soon as the voltage characteristic slope becomes negative. This technique allows the very rapid charge of a NiCd battery, near to its full capacity. Moreover, no compensation for the age of the battery is required because only relative voltages are measured.
In this application, the battery voltage is sensed by a ST621 0 microcontroller housed in 20 pin dual in line package. The integrated Analog to Digital converter (ADC) of this micro-controller is able to detect a typical voltage drop of -10mV/cell.
MONITORING FUNCTIONS
The battery charge is totally monitored by the HCMOS ST6210 in PDIP or PSO 20 pin package, the ST6210. By using this micro-controller, additional monitoring functions can be easily added to the Ultra fast charge control program.
Stand-by current charge: Burst mode
Once the negative voltage drop has been detected by the ST6210, the ultra-fast charging is stopped and the power converter supplies the battery with a stand-by current around 170mA. This stand-by charge is provided by burst mode current control. The converter is successively turned on and off at 25Hz with a small duty cycle of 0.025. The ST621 0
Figure 2. One NiCd Cell Charge Characteristic
t 1.6
manages this burst mode from the secondary side via an optocoupler to the auxiliary supply of the PWM control IC (UC3845).
A small 100f1F reservoir capacitor is sufficient to keep the ST621 0 correctly supplied during the off periods (39ms) of the burst mode. This is possible due to the low current consumption in run mode of the ST6210 HCMOS micro-controller (typically 3mA with an 8MHz oscillator, reducing to typically 1mA for a 2MHz oscillator).
Battery temperature protection
Temperature protection is simply realized by using an NTCresistor placed on the battery pack. This NTC resistor is directly connected to another input of the ADC of the ST6210. When the battery temperature reaches 40'C during an Ultra Fast charge phase, the converter is switched into burst mode to protect the battery.
BatterY presence
The ST621 0 program detects whether the battery pack is connected or not. When the battery is not connected, the converter is turned into burst mode. The resulting stand-by current (170mA) flows into the output Trarisil diode (BZW 50-12).
CHARGE CONTROL PROGRAM DESCRIPTION
Figure 3 shows the main flow chart of the program for the complete charge control. The overall system is reset after each new mains connection.
Battery voltage measurement:
The battery voltage is directly measured by the ST621 0 Analog to Digital Converter through a resistor divider chain. The technique used allows the ST621 0 to automatically adapt to the battery type and voltage (from 2 to 6 cells, 2.4V to 7.2V).
t------+-----b~::::::s~~t=t-t.v
Oi 1.4
u
o'0 Z
-10mV/cell
1.3
I
Charging time (I) __
VR00160B
____________________________ ~~~~~~~~~~ ___________________________3/_6 431
APPLICATION NOTE Figure 3. Main flow chart of the Ultra Fast Charge control program
. - - - - - - - 0 . , , ' BATTERY VOLTAGE MEASUREMENT YES
NO
NO
YES
1
1
1- ___________________________ I
.- - - - - - - - - - - - - -
- -- - -- - - - -- - -1
1
STAND-BY CHARGE
NO
YES
NO
YES
1- ___________________ , _______ I VR001609
_4/_6_____________ ~~~~@~~~9©~ _ - - - - - - - - - - - - -
432
APPLICATION NOTE
Monitoring principle
The 8T621 0 averages a series of 256 battery voltage measurements (L Mn). The 256 conversions are made in a time frame of around 19 ms, with an inter-frame delay time of 0.5s (in this example). An average AVr of the last 8 averaged values is made according to the formula:
""" LMn .. 'LMn-B
Avr=,L..,
8
This AVr value is compared to the previous average AVr-1 and the highest value is stored. This rolling average value follows the battery voltage curve. Once the AVr value begins to decrease, indicating the battery is fully charged, the 8T6210 stops the Ultra Fast charging.
The response time to detect the battery voltage drop ranges from 0.5 to 4 seconds, depending on the slope of the battery voltage curve at the charge completion. A longer delay time is able to increase the noise immunity, but at the cost of an extended response time.
PRACTICAL RESULTS
Tests made with different battery packs confirm that the battery charge is efficiently controlled by the
8T621 0 using its internal AID converter. Results on
the battery voltage and temperature pack versus charging time are shown in Fig. 5.
These recordings have been made with a common 1.2Ah/7.2V NiCd battery pack for cordless drills. The temperature of the battery pack does not exceed 33'C for an ambient temperature of 26'C.
Figure 4: Sequencing principle of the Battery Voltage measurement
256 V BAT MEASURES
,
,
" , T-7\.,
'" ,,, ,, ,""\,,,,,,,,,,,,,,,,,
""",, \,,
-----~
----~
Comparison
I ·
Time VR001610
____________________________ ~~i~@~~~~~~©~ ___________________________5/_6
433
APPLICATION NOTE Figure 5 . VBAT and Pack. Temp Vs time
Battery pack 35 30 25'
Battery Voltage (V) 9.5
8.5 8
1 2
Charging time (mn)
VR001611
SUMMARY
Charging a.NiCd battery in less than half an hour saves battery packs and time. It can enlarge the use of battery powered equipments, especially in professional applications; Suc~ ultra fast charging has to be carefully monitored to maximize the lifetime of the battery and the charge safety. Moreover, this improvement needs to be achieved with a compact equipment including a mil'1imum of components.
The proposed power. charger is realized with a conventional1?MPS topology. The size and number of the magnetic comporients are minimized by using an integrated magnetic technique.
This note shows that an ultra. fast charge can be totally monitored by a single 20 pin HCMOS microcontroller, the ST6210.
The program used in the, validation of this Battery Charger is available. from SGS-THOMSON. This software routine has the basic ultra fast charger and many additional features including stand-by
charge, temperature· protection, battery presence detection and automatic battery voltage sensing. Given the flexibility offered by the programmability of the ST6210, other specific requirements can be implemented. Consult your local SGS-THOMSON sales office or franchised distributor.
REFERENCES [1] G.E. BLOOM, "CORE SELECTION FOR IN-
TEGRATED-MAGNETIC POWER CONVERTERS", Powertec~lnics Magazine - June 1990.
[2] A. WATSON-SWAGER, "FAST-CHARGE BATTERIES", EON, Dec. 7, 1989.
[3] M. GROSSMAN, "FOCUS ON RECCHARGEABLE BATTERIES: ECONOMIC PORTABLE POWER", Electronic Design, March 3, 1988.
[4] L. WUIDART, "ULTRA FAST NiCd BATTERY CHARGER WITH INTEGRATED MAGNETIC", PCIM - June 1991 - Nurnberg/G
-6/-6------------------------- ~~~~~~'~~4 ---------------------------
434
APPLICATION NOTE
DESIGNING WITH THE L296 MONOLITHIC POWER SWITCHING REGULATOR
A cost-effective replacement for costly hybrids, the L296 Power Switching Regulator delivers 4A at an output voltage of 5.1 V to 40V and includes many popular supply features. This comprehensive application guide explains how the device operates and how it is used. Typical application circuits are also presented.
The SGS THOMSON L296 is the first monolithic switching regulator in plastic package which includes the power section. Moreover, the circuit includes all the functions which make it specially suited for microprocessor supply.
Before the introduction of L296, which realizes the step down configuration, this function was implemented with discrete power components driven be integrated PWM regulator circuits (giving a maximum output current of 300 to 400mA) or with hybrid circuits. Both of these solutions are characterized by a low efficiency of the power transistor. For this reason it is generally necessary to operate at frequen-
AN244/1288
cies in the 20kHz to 40kHz range. Of the two alternatives discrete solutions are usually less expensive because they do not include as many functions as the L296. With the new L296 regulator the driving problem of the power control stage has been eliminated. Besides a higher overall efficiency, it is therefore also possible to operate directly at frequencies as high as 100kHz. At 200kHz the device still operates (further reducing the cost of the Land C external components) when a reduction of a few percent in efficiency is acceptable.
1/42
435
APPLICATION NOTE
The device delivers a maximum current of 4 A to the load, at an output voltage adjustable from 5.1 to 40V ; the maximum operating input voltage is 46V. The high voltage and the high current capabilities of the device are a result of the special technology used and the special care taken in designing the power transistor. Essential requirements for a good power transistor are high gain and high current levels, low saturation voltage and good second breakdown robustness. To achieve high gain at high current levels, the power transistor has to be designed to maximize the emitter's perimeter/area ratio.
In the L296 power transistor, realized with a high voltage (50V) process, current densities in the magnitude order of 1OmNMil2 are achieved.
In its most complete configuration, in which all the available functions are being used, a significant reduction of the external component count is achieved compared with discrete component solution.
The L296 is mounted in a MULTIWATT® plastic package with 15 pins, minimizing the cost per watt and allowing a low thermal resistance of 3°C/W between junction and package and of 35°C/W be-'
tween junction and ambient. This thermal resistance (inclucing the contact resistance) is comparable to that of the more costly metal TO-3 packages.
THE STEP-DOWN CONFIGURATION
Fig. 1 shows the simplified block diagram of the circuit realizing the step-down configuration. This circuit operates as follows: 01 acts as a switch at the frequency f and the ON and OFF times are suitably . controlled by the pulse width modulator circuit. When 01 is saturated, energy is absorbed from the input which is transferred to the output through L. The emitter voltage of 01, VE, is Vi-Vsat when 0 is ON and -VF (with VF the forward voltage across the D diode as indicated) when 01 is OFF. During this second phase the current circulates again through Land D. Consequently a rectangular shaped voltage appears on the emitter of 01 and this is then filtered by the L-C-D network and converted into a continuous mean value across the capacitor C and therefore across the load. The current through L consists of a continuous component, ILOAD, and a triangular-shaped component super-imposed on it, ~IL, due to the voltage across L.
Figure 1 : The Basic Step-down Switching Regulator Configuration.
c
1 LOAD
Dl
Vo
Vi
ESR
in
j (LOAD
5-6776
2/42 436
.~ ...,I SiICil~iS©I-ilT@~H~~O©1fMIilS@IOllUN©@
APPLICATION NOTE
Figure 2 : Principal Circuit Waveforms of the figure 1 Circuit.
JJ o" Q,
OFF ON OFF
I
I
ON , OFF
'ON 'OFF
I
I
" ',-,CC..,
I.
.~Lf= ..,
a)
T
la
r1 "~r1 Ipeak
.. ,
b)
10
-~ Ipeak ~
-,
n1lr--
c)
.. ,
Vl
Jl
n_:"~:'OI d)
~-(VF"VO)
I'" "," --=- -
'.0," .1
..
f)
Ie
~ -t lJ.VE~
..
g)
nvc=nQ= nIL c Sf[
h)
5-6788
3/42
437
APPLICATION NOTE
Fig. 2 shows the behaviour of the most significant waveforms, in different points of the circuit, which help to understand beller the operation of the power section of the switching regulator. For the sake of simplicity, the series resistance of the coil has been neglected. Fig. 2a shows the behaviour of the emitter voltage (which is practically the voltage across the recirculation diode), where the power saturation and the forward VF drop across the diode era taken into account.
The ON and OFF times are established by the following expression :
TON Va = (Vi - Vsat) TON + TOFF
Fig. 2b shows the current across the switching transistor. The current shape is trapezoidal and the operation is in continuous mode. At this stage, the phenomena due to the catch diode, that we consider as dynamically ideal, are neglected: Fig. 2c shows' the current circulating in the recirculation diode. The sum of the currents circulating .in the power and in the diode is the current Circulating in the coil as shown in fig. 2e. In balanced conditions the ~IL+current increase occuring during TON has to be equal to the ~IL- decrease occurring during TOFF. The mean value of IL corresponds to the charge current.
The current ripple is given by the following formula:
= A
u
l
L + =
A
ul
-
L
(Vi - VLsat)-V TON--
Va + VF L
TOFF
It is a good rule to respect to 10MIN ~ hJ2 relationship, that implies good operation in continuous mode. When this is not done, the regulator starts operating in discontinuous mode. This operation is still safe but variations of the switching frequency may occur and the output regulation decreases.
Fig. 2d shows the behaviour of the voltage across coil L In balanced conditions, the mean value of the voltage across the coil is zero. Fig. 2f shows the current flowing through the capacitor, which is the difference between IL and ILOAD.
In balanced conditions, the mean current is equal to zero, and ~Ie = ~IL. The current Ie through the capacitor gives rise to the voltage ripple. This ripple consists of two components :a capacitive component, ~Ve, and a resistive component, ~VESR, due to the ESR equivalent series resistance of the capacitor. Fig. 2g shows the capacitive com-
ponent ~Vc of the voltage ripple, which is the integral of a triangular-shaped current as a function of time. Moreover, it should be observed that ve (t) is in quadrature with ie(t) and therefore with the voltage VESR. The quantity of charge ~O+ supplied to the capacitor is given by the area enclosed by the ABC triangle in fig. 2f :
~Q=~ . ~ . ~IL
2·22
which therefore gives:
~V. e=
Q -C
~IL
=8-fc
Fig. 2h shows the voltage ripple VESR dl,le to the resistive component of the capacitor. This component is VESR (t) = ie (t) . ESR. Fig. 2i shows the overall ripple Va, which is the sum of the two previous components. As the frequency increases (> 20kHz), which is required to reduce both the cost and the sizes of Land C, the VESR component becomes dominant. Often it is necessary to use capacitors with greater capacitance (or more capacitors connected in parallel to limit the value of ESR within the required level.
We will now examine the stepdown configuration in more detail, referring to fig. 1 and taking the behaviour shown in fig. 2 into. account.
Starting from the initial conditions, where Q = ON, ve = Va and iL = iD = 0, using Kirckoff second principle we may write the following expression:
Vi = VL + ve (Vsat is neglected against Vi).
Vi = L
CdiILt
+
ve
=
. L
idliLl
+ Va
(1 )
which gives:
diL (Vi-Va)
dt = -L-
(2)
The current through the inductance is given by :
IL -- (Vi -LVa) t
(3)
When Vi, Va, and L are constant, IL varies linearly
with t. Therefore, it follows that:
~IL+ _ (Vi - Va) TON
(4)
-L
When 0 is OFF the current through the coil has reached its maximum value, Ipeak and because it cannot very instantaneously, the voltage across the coil is inverted and the diode 0 becomes forward biased to allow the recirculation of the current through the load.
4/42
438
APPLICATION NOTE
When Q switches OFF, the following situation is present:
= = = vc(t) Va, iL (t) io (t) Ipeak
And the equation associated to the following loop may be written :
VF + L ddiLt + Vc = 0
(5)
where:
vc = Va
CdliLt = - (VF + Vo)/L
(6)
It follows therefore that:
iL (t) = _ VF + Va t
(7)
L
The negative sign may be interpretated with the fact
that the current is now decreasing. Assuming that
VF may be neglected against Va, during the OFF
time the following behaviour occurs:
Va
IL= -L-t
(8)
therefore:
i1IL - = ~ TOFF
(9)
L
But, because
i1IL+ = i1IL-
if follows that:
(Vi - Va) TON Va TOFF
L
=-L-
which allows us to calculate Va :
Vo = Vi TON = Vi TON
(10)
TON + TOFF
T
where T is the switching period.
Expression (10) links the output voltage Va to the input voltage Vi and to the duty cycle. The relationship between the currents is the following:
TON lioc= 10DC·-,=-
EFFICIENCY
The system efficiency is expressed by the following formula:
Po 100
Pi
where
Po = Vola
(with 10 = ILOAO)
is the output power to the load and Pi is the input power absorbed by the system. Pi is given by Po,
plus all the other system losses. The expression of
the efficiency becomes therefore the following:
Po
11=
(12)
Po + Psat + Po + PL + Pq + psw
DC LOSSES
Psat: saturation losses of the power transistor Q.
These losses increase as Vi decreases.
Psat =Vsat. 10 TTON = Vsat 10 IVioi
(13)
where
-TO-N
Vo =-
T Vi
and Vsat is the power
transistor saturation at current 10.
Po: losses due to the recirculation diode. These
losses increase as Vi increases, as in this
case the ON time of the diode is greater.
Vi-Va
Po = VF 10 -V-i- = VF 10 (1 -
\VIai
)
(14)
where VF is the forward voltage of the recirculation diode at current 10 .
PL : losses due to the series resistance Rs of the
coil
PL = Rs 102
(15)
Pq : losses due to the stand-by current and to the power driving current:
T Pq = Vi 1'3q + Vi 1"3q TON
(16)
where being: TON Vo
--=r=v;-
it follows that:
Pq = Vi 1'3q + Vo 1"3q
in which:
1'3q = 13q
at 0 % duty cycle
1"3q = i3q(100 % d.c.) - 13q (0 % d.c.)
SWITCHING LOSSES
Psw : switching losses of the power transistor:
---zr- tr + tf
Psw = Vi 10
The switching losses of the recirculation diode are neglected (which are anyway negligible) as it is assumed that diode is used with recovery time much smaller than the rise time of the power transistor.
We can neglect losses in the coil (it is assumed that i1IL is very small compared to 10) and in the output capacitor, which is assumed to show a low ESR.
5/42
439
APPLICATION NOTE
Calculation of the inductance value, L
Calculation TON and TOFF through (4) and (9) re-
spectively it follows that:
TON
~It. L =---
Vi-Va
Mi: . L TOFF
Va
But because :
TON + TOFF = T
and
it follows that :
- ~IL-' L+~- IL'-L =T Vi-Va Va
Calculating L, the previous relation becomes:
L= (Vi-Va) Va T
Vi~IL
(18)
Fixing the current ripple in the coil required by the design (for instance 30% of 10), and introducing the frequency instead of the period, it follows that:
L = (Vi - Va) Va where L is in Henry and f in Hz Vi . 0.3 .10 · f
Calculation of the output capacitor C
From the output node in fig. 3 it may be seen that the current through the output capacitor is given by : ie (t) = iL (t) - 10
FigiJre 3 : Equivalent Circuit Showing Recirculation when Q1 is Turned Off.
1LOAD
c
5- 6777
From the behaviour shown in fig. 2 it may be calcu-
lated that the charge current of the output capacitor,
within a period, is ~1L.l4, which is supplied for a time
T/2. It follows therefore that:
~V =~2=~ILT=~
(19)
c 4C 2 8C' 8fC
but, remembering expression (4) :
---v:- ~IL+ (Vi - Va) TON d T
Va T
L
an ON =
therefore equation (1.9) becomes:
~V '= (Vi - Va) Va, c 8 Vif2 L C
Finally, calculating C it follows that:
C = '(Vi - Va) Va
8Vi~Vcf2L
(20)
where:
L is in Henrys C is in Farads f is in Hz
Finally, the following expression should be true:
~VCmax
ESRmax =
~IL
(21 )
It may happen that to satisfy relation (21) a capacitance value much greater than the value calculated through (20) must be used.
TRANSIENT RESPONSE
Sudden variations of the load current give rise to overvoltages and undervoltages on the output voltage. Since ie = C (dvddt) (22), where dVe = ~Vo, the instantaneous variation of the load current ~Io is
supplied during the transient by the output capacitor, During the transient, also current through the
coil tends to change its value, Moreover, the following is true:
VL = L ~
(23)
dt
where diL = ~Io.
VL=Vi-Vo
for a load increase
VL = Va
for a load decrease
Calculating dt from (22) and (23) and equalizing, it follows that:
L diL = C dVe
VL
ie
Calculating dVe and equalizing it to ~Vo, it follows
that:
~Vo=
~102 C(Vi - Va)
(24) for + ~Io
~Vo =
~102 CVo
(25) for - ~Io
From these two expressions the dependence of overshoots and undershoots on the Land C values may be observed. To minimize ~Vo it is therefore necessary to reduce the inductance value L and to increase the capacitance value C, Should other auxiliary functions be required in the circuit like reset or crowbar protections and very variable loads may be present, it is worthwhile to take special care for minimizing these overshoots, which could cause spurious operation of the crowbar, and the undershoot, which could trigger the reset function.
6/42 440
APPLICATION NOTE
DEVICE DESCRIPTION Fig. 4 shows the package in which the device is mounted and the pin function assignments. The internal structure of the device is shown in fig. 5. Each block willl10W be examined.
Power supply The device is provided with an internal stabilized power supply that, besides supplying the reference
Figure 4 : Pin Assignments of the L296.
voltage of 5.1 V for the whole system, also supplied the internal analog blocks.
Special features of the voltage reference are its accuracy, temperature stability and high line rejection. Through zenze-zap trimming, the voltage is within ±2% limits.
~15
~ '4 13 I 11 10 9· 8 7 6 5
-+~
~1
I
Tab connl"ctl"d to pin 8
CROWBAR DRIVE
RESET OUTPUT RESET DELAY RESET INPUT OSClll"JOR FEEDBACK INPUT FREQUENCY COMPENSATION
GROUND SYNC. INPUT INHIBIT INPUT SOFT-START CUR RENT LIMIT SUPPLY VOLTAGE OUTPUT CROWBAR INPUT
Figure 5 : Block Diagram of the L296. In Addition to the Basic Regulation Loop the Device includes Functions such as Reset, Crowbar and Current Limiting.
INHIBIT INPUT
I RESET DELAV
7/42 441
APPLICATION NOTE
OSCILLATOR
The oscillator block generates the saw-tooth waveform that sets the switching frequency of the system. This signal, compared with the output voltage of the error amplifier, generates the PWM signal to be sent to the power output stage. The saw-tooth, whose amplitude is between 1.2V. and 3.2V; is generated by charging rapidly the Cose capacitor which then discharges across the Rose resistance. As shown in fig. 6, the oscillator is realized by a comparator (with grounded compatible iriput) with hysteresis whose thresholds are 1.2V and 3.2V respectively. The Cosecapacitor and the Rose resistance are connected to the non-inverting input of the comparator which set the oscillating frequency is fixed. When the voltage on pin 11 is less than 3.2V, the switch 81 is closed and the current generator charges the Cosecapacitor rapidly; in this phase 82 is also closed. As soon as 3.2V is reached the comparator output drives 82 open (therefore opening 81, too) ; the inverting input voltage is reduced to about
Figure 6 : Internal 8che:matic of the Oscillator.
1.2V and the capacitor starts to discharge itself across the Rose resistor (the Ibias effect is neglected). When the voltage reaches 1.2V, 82 and 81 close again and a new cycle starts. The generated waveform is shown in fig. 7.
To achieve a good accuracy of the switching frequency it is essential to have a charging time of the capacitor which is much smaller than the discharging time. In this way, the oscillation frequency only depends on the external components Coseand Rose. Forthis reason the capacitor charging current (when 81 is ON) is typically around 10mA. For example, with a 2.2nF capacitor to switch from 1.2V to 3.2V about 400ns is required, which is negligible compared to the 1O).lS period that occurs when the operation is performed at 100kHz. The diagrams shown in fig. 8 allow the calculation of the Rose value (R1 in fig. 8) with Cose as a parameter (C3 in fig. 8) when the oscillation frequency required for operation has been previously fixed.
L296
5-67.'
_ _ _ _ _ _ JI
8/42 442
Figure 7a : Oscillator Waveform at Pin 11 with
f = 100Khz (Rose = 4.3KQ,
Cose = 2.2nF).
Figure 7b : Oscillator Waveform at Pin 11 with
f = 50Khz (Rose = 9.1 KQ,
Cose = 2.2nF).
Figure 8 : Nomogram for the Choice of Oscillator Components.
(..r..)
G 4~11
.......
. ""~ '\
100
O=\5nF
CJ.Z.2nF"r'\..
IIII 1",
10
lUI "
10
RI (OA)
APPLICATION NOTE
Fig. 8 shows two suggested values for the Cose capacitance. Excessively low capacitance value may give rise to an inaccuracy of the upper threshold due to the switching delays of the comparator. This inaccuracy in caused by an excessively short rise time of the voltage. A capacitance value too high gives rise to a charging time which is too compared to the discharging time. An additional inaccuracy cause would be therefore present for the switching frequency, now due to spread of the charge current.
The oscillation frequency is given by the following formula:
fose =
(26)
Rose Cose
PWM (see fig. 9)
The PWM signal is generated on the comparator output ; the triangular-shaped waveform and the continudus signal coming from the output of the trarisconductance error amplifier are sent to its inputs. The PINM signal is then transferred to the driving stage of the output power transistor.
SOFT START (see fig. 9)
Soft start is an essential function for correct start-up, to prevent stresses and possible breakdown from occurring in the power transistor and to obtain a monotonically, ihcreasing output voltage. In particular, the L296, as it does not have any duty cycle limitation and due to the type of current limitation does not allow the output to be forced to a steady state without the aid of the soft-start facility. Soft-start. operates at the start-up of the system, after the inhibit has been activated, after an intervention of the current limitation and after the intervention of the thermal protection.
The soft-start function is realized through a capacitor connected to pin 5 which is charged at constant current (= 100IlA) up to a value of about VREF. During the charging time, through PNP transistor 058, the voltage on pin 9 is forced to increase with the same rising speed as on pin 5. Starting from the dis-
charged capacitor condition (pin 5 voltage =OV) the
power transistor is in the OFF condition, as the voltage on pin 9 is smaller than the minimum level of the ramp voltage. As the capacitor is charged, the PWM signal begins to be generated as soon as the error amplifier output voltage crosses the ramp; the power stage starts to switch with steadily increasing duty cycle. This behaviour is shown in fig. 10. As soon as the steady condition is reached the duty cycle sets itself to the right value due to the effect of the feedback network while the soft-start capacitor completes its charging to a value very close to VREF.
9/42 443
APPLICATION NOTE
The soft-start effect is determined, apart from the switch-on time, when the current limitation operates, due to either an overload or a short circuit, to keep the mean value of the current absorbed by the power supply low.
Moreover from fig. 1'1 it may be observed that since the voltage on pin 9 can decrease under the mini-
mum ramp level and increase over the maximum level no limitations have been provided on the duty cycle, .which therefore may vary between 0 and 100%.
Figure 9 : Partial Internal Schematic Showing PWM and Soft Start Blocks.
~
l296
VREF
5OI'A!
p~
I
VREF
10
a5S
S-6184
Figure 10: Soft Start Waveforms. When power is applied, or after an inhibit, the L296's output current rises slowly under control of the soft start circuit.
05CILLATOR OUTPUT
NOMINAL ERROR AMP.OUTPUT
OUTPUT CURRENT
10/42
444
5 _5835
APPLICATION NOTE
Figure 11 : Waveform for Calculation of Duty Cycle and Soft Start Time.
(V)
5 ----------
Vp in5
1.2
tss
II
" tstart-up
5-6798/1
CALCULATING THE DUTY CYCLE AND SOFT-START TIME
Assume, for simplicity, that the rising edge of the ramp is instantaneous; V, is the output voltage of the error amplifier and Ve the ramp voltage (see fig. 11). The PWM comparator block switches when V, = Ve ; therefore:
V,=Ve=Ee RoseCose
Consequently:
E
t = Rose Case In V,
The time obtained from this expression is the TOFF
time of the power transistor. The duty cycle d is given by:
TON T - Rose Cose In VEr d =T =----:T=-----
E Vo
(27)
=1-ln-=-
V, Vi
Consequently, starting with the capacitor dis-
charged, the output of the regulator will be at the
nominal level when the voltage at the terminal of the
capacitor (which is charged by a constant current)
hC!s reached V, - O.5V.
tstart.up =
Css (V, - O.5V) 15so
where Css is the soft-start capacitor and 15so is the charging current.
Considering as the soft-start time the time required for the soft-start capacitor to charge from (1.2 V - O.5V) to V, - O.5V, gives: tss = --C-s-s-'(.V,.,-----1-.2-')-
Isso
substituting V, from (27) gives:
- ( 1 - ~~ )
V,= Ee
substituting into (28) gives:
( Va -1 )
Css
Vi
tss = -1- (E e
- 1.2)
sso
SYNCHRONIZATION
The synchronization function is available on pin 7, this function allows the device to be switched at an externally generated frequency (leaving pin 11 open), or to mutually synchronize several devices, using one of them as master and the others as slave (fig. 12).
This allows several devices to be operated at the same frequency, avoiding undesirable intermodulation phenomena. The number if mutually synchronizable devices is obviously much greater than the three devices shown in the figure. It is anyway diffi-
11142
445
APPLICATION NOTE
cult to establish an exact maximum number of devices, as it depends on different conditions.
The first consideration concerns the accuracy which must be achieved and maintained on the oscillation frequency. Since the bias current on pin 7 is an out-
put current, the sum of all the bias currents must be
much smaller than the capacitor discharge current in close proximity to the lower discharge threshold.
Therefore, assuming Cose = 2.2nF and Rose = 4.3KQ, it follows that:
~ =280 A
4.3KO
/l
Assuming that a 10% variation may be accepted, it follows therefore that the number of synchronizable devices is given by :
N = 28/lA
jbias max
This means that if the overall Ibias is too high it may modify the discharging time of the capacitor.
The second consideration concerns the layout design. In the presence of a great number of devices to be synchronized, the lenght of the paths may become significant and therefore the distributed inductance introduced along the paths may begin to modify the triangular shaped waveform, particularly the rising edge which is very steep. This effect would affect the devices thafare physically located more distant from the master device.
The amplitude ofthe saw-tooth to be externally con-
nected must be with in 0.5V and 3.5V, values also
representing the maximum swing of the error ampli-
fier output.
'
CURRENT LIMITATION
The current limitation function has been realized in a rather innovative way to avoid overload condition during the short circuit operation. In fact, while for all the other devices a constant current limitation is implemented by acting on the duty cycle (therefore, in short circuit conditions an output current is equal to the maximum limitation current), the new control approach allows operation in short circuit conditions with a mean current much smaller than the allowed 4A value. Operation of the current limiter will now be described. Refer to the block diagram, fig. 13.
The current which is delivered from the output transistor to the load flows through the current sensing resistor Rs. When the voltage drop on Rs is equal to the offset voltage of the current comparator, the comparator generates a set pulse for the flip-flop, with a delay of about 1flSec. The purpose of this delay is to avoid triggering of the protection circuit on the current peak that occurs dUQ!lg the recirculation phase. Therefore, the output Q goes low and the power ..§.tage is immediately switched off, while the output Q goes high and acts directly on the softstart capacitor dischargng the soft-start capacitor at a constant current (about 50/lA). '
When the voltage on pin 5 reaches O.4V the comparator triggers, supplying a reset pulse to the flipflop; from now on, the power stage is enable and the soft-start phase starts again. When the limitation cause, either overload or short circuit, is still present the cycle repeats again. The waveform of the output current on pin 2 is shown in fig. 14.
Figure 12: In multiple supplies several 1296's can be synchronized as shown here.
L296
11
7
OSC
SYNC
1
sc ±co~
L296
11
7
OSC
SYNC
I
1
L296
11
7
OSC
SYNC
I
J
S-~97&/l
12/42
446
APPLICATION NOTE
From fig. 14 it may be observed how this current limitation technique allows the short circuit operation with a very low output current value.
It is possible to reduce the maximum current value by acting on pin 4. On this pin a voltage of about
3.3V is present; by connecting a resistance a constant current, given by 3.3/R, is sent to ground. This current reduces the offset voltage of the current comparator, therefore anticipating its triggering threshold.
Figure 13 : Partial Schematic Showing the Current Limiter Circuit.
l296
9
5
Q
FLIP
FLOP
R Q
2
4
5-6785
C55
I
R
Figure 14a : Current Limiter Waveforms.
12
CURRENT
LIMITER
:~~:::w" -r~n-;~ n-A~~~a~ ~.. LIMIT
TRIGGERS
-'-----'---'..-.L--J...LL- .L-L...-L---U..- ..L-LL- .J.-
a
u.
CUR RENT
-----,-------
(
.. t
S. &59611
13/42 447
APPLICATION NOTE
Figure 14b: Load Current in Short Circuit Conditions
(Vi =4OV, L =30011H, f =100KQ).
·II I
L Hi II
, I
· .. .,
~ .~ ~
1
+- · · . · · · -+-t-+-+-t
I,'; =-i
II
II
I
=
1
=
· II
t: 5ms/div
Figure 14c : Current at Pin 2 when the Output is Short Circuited.
t: 5ms/div
RESET The reset function is of great importance when the device is used to supply microprocessors, logic devices, and so on. This function differentiates the L296 device from all previous devices. The block diagram of the function is shown in fig. 15. A reset signal is generated when the output voltage is within
the limits required to supply the microprocessor correctly.
The reset function is realized through the use of 3 pins: the reset input pin 12, the reset delay pin 13 and the reset output pin 14. When the voltage on pin 12 is smaller than 5V the comparator output is high and the reset capacitor is not charged because the transistor 0 is saturated and the voltage on pin 14 is at low level, since 02 is saturated, too. When the voltage on pin 12 goes above 5V, the transistor
o switches OFF and the capacitor can start to
charge through a current generator of about 100!lA. When the voltage on pin 13 goes above 4.5V the output of the related comparator switches low and the pin 14 goes high. As the output consists of an open collector transistor, a pull-up external resistance is required. In contrast, when the reset input voltage goes below 5V, less a hysteresis voltage of about 100mV, the comparator triggers again and instantaneously sets the voltage on pin 14 low, therefore forcing to saturation the 01 transistor, that starts the rapid discharge of the capacitor. Obviously, the reset delay is again present when the voltage on pin 13 is allowed to go under 4.5V.
To achieve switching operations without uncertainties the two comparators have been provided with an hysteresis of about 100mV. In every operating condition the reset switching is guaranteed with a minimum reset input of 4.75V, the value required for correct operation of the microprocessor even in the presence of the minimum VREF value.
Norl)1ally pin 12 is used connected to pin 10. When it is connected to the output, the function may be more properly called "reset" ; on the other hand, when it is connected through resistive divider, to the input voltage, the function is called "power fail". Fig. 16 and fig. 17 show the two possible usages.
The "power-fail" function is used to predict, with a given advance, the drop of the regulator output voltage, due to main failures, which is enough to save the data being processed into protected memory areas. Fig. 18 summarizes the reset function operation.
14142 448
Figure 15: Partial Schematic Showing Reset Circuit. L296
APPLICATION NOTE
RESET 14 OUTPUT
$-67f16
13
I CRESET
Figure 16: For Power - On reset the reset block is connected as shown here.
RESET OUT
~
14
L296
2
=
DVo
13
12
10
!~ CRESE
1
~ ..
--
I
5 - 677]
Figure 17 : To obtain a power fail signal, the reset block is connected like this.
RESET OUT
12
L296
I
15/42
449
APPLICATION NOTE
Figure 18 : Waveform of the Reset Circuit.
RESET THRESHOLD ----.
OUTPUT NOW
AN INTERRUPTION
STABLE,RESET
OF SUPPLY C"'U~S
GOES HIGH
RESET OF MICRO
IOOmV OF
-HY_SJTE_R_ES_IS
"'_-_-_+I-_-_-_-_-_-_-_""tI'
---
AT POWER DOWN
I MICRO IS INHIBITED IMMEDIATELY
-------
MONITORED VOLTAGE
RESET OUTPUT
DELAY
DELAY
CROWBAR
!his protection function is realized by a completely Independent block, using pin 1 as input and pin 15 as output. It is used to prevent dangerous overvoltages from occurring when the output exceeds 20% of rated value. Pin 15 is able to output a 1OOmA cur~ent to be sent to the gate of a SCR which, triggering, short circuits either output or the input. When connected to the input, as the SCR is triggered a fuse in series connected to power supply is blown and to bring the system back to operation manual intervention is requested. Figs. 19, 20 and 21 show the different configurations.
When the voltage on pin 1 exceeds by about 20% the VREF value the output stage is activated, which sends a current to the SCR gate, after a delay of about 51lsec to make the system insensitive to lowduration spikes. When activated, the output stage delivers about 1OOmA ; when not activated, it drains about 5mA and shows a low impedance to the SCR gate to avoid uncorrect triggering due to random noise. If the crowbar fu nction is not used connect pin 1 to ground.
Figure 19 : Connection of Crowbar Circuit at Output for 5.1 V Output Applications.
L296
15
I
5-6775
16/42
450
APPLICATION NOTE
Figure 20: Connection of Crowbar Circuit at Output for Output Voltages above 5.1 V.
Figure 21 : Connection of Crowbar Circuit to Protect Input. When triggered, the scr blows the fuse.
Vio-r=FU~~ ~~ ~ 3
L296
1 l I (.~ I 15 I
5 -67 69
...()INPUT
CROWBAR
INHIBIT
The inhibit input (pin 6) is TIL compatible and is activated when the voltage exceeds 2V and deactivated when the voltage goes under O.8V. As may be seen in the block diagram, the inhibit acts on the power transistor, instantaneously switching it off and also acts on the soft-start, discharging its capacitor. When the function is unused, pin 6 must be grounded.
THERMAL PROTECTION
The thermal protection function operates when the junction temperature reaches 150"C ; it acts directlyon the power stage, immediately switching it off, and on the soft-start capacitor, discharging it. The thermal protection is provided with hysteresis and, therefore, after an intervention has occurred, it is necessary to wait for the junction temperature to decrease of about 30"C below the intervention threshold.
APPLICATIONS
Though the L296 is designed for step-down regulator configurations it may be used in a variety of other
applications. We will now examine these possibilities and show how the capabilities of the device may be extended.
In fig. 22 the complete typical application is shown, where all the functions available on the device are being used. This circuit delivers to the load a maximum current of 4A and a voltage which is established by the voltage divider constituted by R7 and Rs resistances. The following table is helpful for a quick calculation of some standard output voltages:
Resistor Value for Standard Output Voltages
Vo
Ra
Ry
12 V 15V 18 V 24 V
4.7 kQ 4.7 kQ 4.7 kQ 4.7 kQ
6.2 kQ 9.1 kQ 12 kQ 18 kQ
To obtain Va = VREF the pin 10 is directly connected
to the output, therefore eliminating both R7 and Rs. The switching frequency is 100kHz.
17142 451
APPLICATION NOTE
Figure 22 : Schematic, PCB Layout and Suggested Component Values for the Evaluation Circuit used to characterize the L296. This is a typical stepdown application which exercises all the device's functions.
Vi
Rl
Cl 10pF
63V
RESET
3
14
12
13
L296
R6
10
II
~oo}' H
Ql
15
VO R7
R8
4.7
Kfi
__ GND~~---- ----------+---------------------------~--------~--~--~GND
INHIBIT
5-62801l
C7, C8 : EKR (ROE)
SUGGESTEDINDUCTOR(U)
Core Type
Magnetics 58930 A2MPP Thomson GUP .20 x 16 x 7
No Wire Turns Gauge
43 1.0 mm.
Air Gap
65 0.8 mm. 1 mm.
SUGGESTED INDUCTOR (L1) (continued)
Core Type
No Wire
Air
Turns Gauge Gap
Siemens EC 35/17/10 (86633 & - G0500 - x 127) 40 2 x 0.8 mm.
VOGT 250 IlH Toroidal Coil, Part Number 5730501800
18/42
452
APPLICATION NOTE
Figure 23 : Oscilloscope Photographs Showing Main Waveform of the Figure 22 Circuit.
fiI --. -
--
-~- ~
~ - -;;=,.1
-. --
iii:! i'::!! iii:!!
...-.:
, IIiii
ro. ';;"'?
=
II~ I. !;;J
~
~
--1IiI..".:I1I---
,
t: 2/-Ls/div
The oscilloscope photographs of the main waveforms are shown in fig. 23. The output voltage ripple !Y.Vo depends on the current ripple in the coil and on the performance of the output capacitor at the switching frequency (100kHz). A capacitor suitable for this kind of application must have a low ESR and be able to accept a high current ripple, at the working frequency. For this application the Roederstein EKR series capacitors have been selected, designed for hig h frequency applications (>200kHz) and manufactured to show low ESR value and to accept high current ripples. To minimize the effects of ESR,
two 100llF/40V capacitors have been connected in parallel. The behaviour of the impedance as a function of frequency is shown in fig. 24.
Also the selection of the catch diode requires special care. The best choice is a Schottky diode which minimizes the losses because of its smaller forward voltage drop and greater switching frequency rate. A possible limitation comes from the backward voltage, that generally reaches 40V max.
When the full input voltage range of the device is required in this application it is possible to use superfast siodes with 35 to 50ns rated recovery time, where no more problems on the backward voltage occur (on the other hand, they show a greater forward voltage). The use of slower diodes, with trr = 1OOns or more is not recommended; The photographs in fig. 25 show the effects on the power current and on the voltage on pin 2, due to the diodes showing different speeds. Diodes showing trr greater than 35-50ns will reduce the overall efficiency olthe system, increasing the power dissipated by the device.
The third component requiring care is the inductor.
Fig. 22a shows the part numbers of some types used fortesting. Besides having the required induct-
ance value, the coil has to show a very high satura-
tion current.
Therefore, a correct dimensioning requires a saturation current above the maximum value of 12L, the current limit threshold.
T.o achieve high saturation with ferrite cores an air
gap between the two core halves must be provided;
the air gap causes a leakage flux which is radiated in the surrounding space. To better limit this phe-
nomenon "pot cores" may be used, whose geometry is such to better limit the flux radiated to the outside.
Using toroidal cores, for instance of Magnetic 58930-
A2 moly-permalloy kind, both the requirements of high saturation and low leakage flux are satisfied. The satu-
ration is softer that the saturation shown by the ferrite
materials. The air gap is not concentrated in one area,
but is finely distributed along the whole core ;this gives
the low leakage flux value.
-
Careful selection of the extemal components there-
fore allows the realization of a power supply system
whose benefits are significant when compared to a
system with the same performance but realized with
the linear technique.
19/42
453
APPLICATION NOTE
Figure 24 : Typical Impedance/Frequency curves for EKR Capacitors.
..
.... ~
"' ~
r--.r-,
[0) ·
~
.......
1"- ..........
~ ~ 'I. I'\."'" I"'.r--
"0
~,
~ ,~
'~.
f-r---
1-----1-
..0.01
5
221'J
r--~
~'o
I--
------~20f21
'-..
I
7 lOll
t- · ,.
T
l I Il Ii
'..,H: ~ ___
Figure 25 : Oscilloscope Photographs Showing the Waveform obtained with Diodes having Different trr Values.
t : 211S/div
t: 2J.ls/div
LOW COST APPLICATION AND PRERE· GULATOR
Fig. 26 shows the low cost application of a 4A and
Vo = 5.1 V power supply. A minimum amount of es-
sential external components is required, which are necessary for correct operation. It is impossible to save other components, specially the soft-start capacitor. Without soft-start, the system cannot reach the steady state and there is also a serious risk of damaging the device.
This application is very well suited not only as a lowcost power supply, but also as pre-regulator for postregulators distributed in different circuit points, or even on different boards (fig. 27). The -post-regulators may be selected among the low-drop types, like L4805 and L387 for example, still obtaining a high efficiency, combined with an excellent regulation. The use of L387 device allows us to use also the reset function, useful to power a microprocessor.
20142 454
APPLICATION NOTE
SWITCHING vs LINEAR
Switching regulators are more efficient than linear types so the transformer and heatsink can be smaller and cheaper. But how much can you gain?
We can estimate the savings by comparing equivalent linear and switching regulators. For example,
suppose that we want a 4 N5 V supply.
Linear
For a good linear regulator the minimum dropout w1ll be at least 5V at 4A. The minimum input voltage is given by:
Vi min = Va + Vdrop + 2 1 Vripple
where:
10 t1 4 x S x 10 - 3
VriPPle:=C = 10x 10 3 =3.2V
V
Vf i(min) - ---
I
I
I
I
,
I
.I_ t) I,J
- -~ -=--=-_IV- ripp'e
I
. ,
5-59%
(a good approximation is Sms for t1 at mains frequency of 50Hz and 1O.OOOIlF for C, the filter capacitor after the bridge). Therefore Vimin:= 1.6V. Since operation must be guaranteed even when the mains voltage falls 20%, the nominal voltage on load at the terminals of the regulator must be :
Vnom = V,m,n = 10.6 =13.25V 0.8 0.8
To allow even a small margin we have to choose:
Vnom = 14V The power that the series element must dissipate is therefore:
Pd = (Vnom Va) 10 = 36W and a heatsink will be necessary with a thermal resistance of :
Rth heats. = O.S"CIW and the transformer must supply a power of :
Pdiss = 14 x 4 = 56W
It must therefore be dimensioned for:
PD= ~ =62VA 0.9
Switching (L296) Assuming the same nominal voltage (14V), the L296 data sheet indicates that the power dissipated in this case is only 7W. And this power is dissipated in two elements; the L296 itself and the recirculation diode.
It follows that the transformer must be roughly 30VA and the heatsink thermal resistance about 11 "CIW.
Linear
Switching
Transformer Heatsink
62 VA 0.8°C/W
30 VA 11 °C/W
This comparison shows that the L296 switching regulator allows a saving of roughly 50% on the cost of the transformer and an impressive SO-90% on the cost of the heatsink. Considering also the extra functions integrated by the L296 the total cost of active and passive components is roughly the same for both types.
Finally, it is important to note that a lower power dissipation means that the ambient temperature in the regulator enclosure can be lower - particularly When the circuit is enclosed in a box - with all the advantages cooler operation brings.
If for some reason it is necessary to use higher supply voltages the switching technique, and hence the L296, becomes even more advantageous.
1It..,~ I SU<G\JlSl©·~T@~H~~O©1lM~@SlllOllN©$
21142 455
APPLICATION NOTE
Figure 26 : A Minimal Component Count 5.1 V / 4A Supply.
r1000jJFISOV
.. IOVlo.46V INPUT
11
300pH
10 12 14 13
Figure 27 : The L296 may also be used as a preregulator in distributed supply systems. SV'",OOmA
L296
Ll
6V
~-6lallZ
(') L2 and C2 are necessary to reduce the switching frequency spikes.
LI.805
5V'",OOmA
r-t-~--....-05V
LlB7A
I
RE5ET OUTPUT
22/42
456
APPLICATION NOTE
POWER SUPPLY COMPLETE WITH TRANSFORMER
Fig. 28 shows a power supply complete of transformer, bridge and filter, with regulation on the output voltage from 5.1 V to 15V.
As already stated above, the output capacitors have to show some speciale features, like low ESR and high current ripple, to obtain low voltage ripple values and high reliability. The input filter capacitors must not be neglected because they have to show excellent features, too, having to supply a pulsed current, required by the device at the switching frequency. The current ripple is rather high, greater than the load current. For this application, two parallel connected 3300IlF/50V EYF (ROE) capacitors have been used.
mains preregulator can be added to reduce the input voltage to a level acceptable for the L296.
In this case the pre-regulator circuit is connected to the primary of the transformer which now operates at the switching frequency and is therefore smaller and lighter.
Using a UC3840 which includes the feed-forward function it is possible to compensate mains variation within wide limits. The secondary voltage is therefore only affected by load variations. Using one or more L296s as postregulators, feedback to the primary is no longer necessary, reduces the complexity and cost of the transformer which needs only a single secondary winding.
Fig. 28A shows a mUlti-output supply with a mains preregu lator.
POWER SUPPLY WITH MAINS SWITCHING PREREGULATOR
When it is desirable to eliminate the 50/60Hz transformer - in portable or volume-limited equipment-a
Figure 28 : A Typical Variable Supply showing the Mains Transformer.
BY251
20V~
10
5-5Bl2/5
v, = 5.1 to 15V
I, = 4A max. (min. load current = 100mA)
ripple,; 20mV
load regulation (1 A to 4A) = 10mV (V, = 5.1 V) line regulation (200V ± 15% and to I, = 3A) = 15mV (V, = 5.1V)
*SGS6R20 OR BYW80
23142 457
APPLICATION NOTE Figure 28A : A Multiple Output Supply using a Switching Preregulator rather than a Mains Transformer.
RESET
oOUT
L296
+5V(4A)
I
I~C~- 1-12~(200mA)
~-.- I'12v(JA)
I
POWER SUPPLY WITH 0 - 30V ADJUSTABLE VOLTAGE
When output voltages lower than 5V are required, the circuit shown in fig. 29 may be used.
Calibration is performed by grounding the P1 slider. Acting on P2, the current which flows through the 1OkQ resistor is fixed at approximately 2.5mA to Qbtain an output voltage of 30V. The equivalent circuit is shown in fig. 30.
Acting now on the slider of P1, the current flowing
through the divider may be varied. The new equival~
ent circuit is shown in fig. 31.
.
Reducing the current flowing, also the voltage drop across the 10kQ resistance is reduced, together with Vo. When the current reaches zero, it follows that Vo = VREF. When the voltage on the slider of P1 exceeds VREF, the current star! to flow in opposite direction and Vo begins to decrease below 5V.
When 11 x 10kQ = VREF it follows that Vo = O.
DUAL OUTPUT REGULATOR
The application shown in fig. 32 is specially interes~ ting because it provides two output voltages. The first voltage, the main one, is directly controlled by the feedback circuit. The second voltage is obtained through an auxiliary winding.
It often happens, when microprocessors, logic devices etc., have to be power supplied, that a main 5V output and an auxiliary + 12V or - 12V output are required, the latter with lower current requirements (100 + 200mA) and a stabilization level not excessively high. As the auxiliary power supply is obtained through a completely separated winding, it is possible to obtain either a positive or negative voltage (compared to the main voltage or also a completely isolated voltage. With Vi variable be-
tween 20V and 40V, Vo = 5.1 V and 10 = 2.5A, the auxiliary- 12V/0.2A voltage is within a ± 2% toler-
ance.
24/42
458
APPLICATION NOTE
Figure 29 : Variable 0-30V supply illustrating how output voltages below 5.1 V are obtained.
11O~F
10KA
ZI
150~H Vo
I SGStlR20 O~ 8ywOO
1~0F00
10Kll
2kll PI
lOOK a
Figure 30 : When setting up the figure 29 circuit the slider of P1 is grounded, giving the equivalent circuit shown here, and P2 adjusted to give an output voltage of 30V.
Figure 31 : Partial Schematic showing Output Voltage Adjustment of Figure 29.
l296 IO~--"
L296 10~------' 6V
s- 6771
25142 459
APPLICATION NOTE Figure 32 :Dual output regulator showing how an additional winding can be added to the inductor to generate
a secondary output.
0-
W <fl
aW :
H
'~"
...J
!
~---~+-~-------+--~----------~~
c:
C
:<:
:<:
0)
'"u:)
PERSONAL COMPUTER POWER SUPPLY
Using two mutually synchronized devices it is posible to obtain a four output power supply suitable for power a microprocessor system. V01 =5.1V/4A
26/42
460
V02 = 12V/2.5A (up 0 4A) V03 = - 5V/0.2A V04 = - 12V10.2A
The schematic diagram is shown in fig. 33. The 5V output is also provided with the reset function, that is available also for the 12V Qutput.
APPLICATION NOTE
Figure 33 : Microcomputer Supply with 5V, - 5V, 12V and - 12V Outputs.
47D1JF
I
L 296
"L~I~2 (I"
.1N5822
-5.1V
...
O.2A
I lOO I'F EKR
.S.lV L-----~~t_----~------~r_~'A
1Kll
RESET
---------------0
INHIBIT
* SGS6RZO OR BywBo
1~5822
~O.2-A 12V.
6.21<.n
L-______+'--+____~
T' 100pF
-'- EKR ~d.;~
r 1000}JF 25V EKR
27/42
461
APPLICATION NOTE
The feedback is direct, no other external component is used and no calibration is therefore required. An output is obtained with the accuracy of the reference voltage (± 2%). For the 12 V output, by using a resistive divider with 1 % resistance an output is obtained whose spread is within ± 4%.
The two devices are mutually synchronized not to give rise to intermodulation which could generate unpleasant noise and, at the same time, a further component saving is achieved.
The crowbar function is implemented on both 5V and 12V outputs, using a single SeR connected to the input. The latter, by discharging to ground the electrolytic filter capacitors, blows the fuse connected in series with the devices power supply. In this way, should a faulty be present on either of the mEli n outputs, the supply is switched off for whole system.
To inhibit both the devices with a single input signal,' it is possible to connect the two inhibit inputs (pin 6) together; the 5KQ resistance is used when the inhibit input is left open. If this input is not used it must be grounded.
As may be noted .in the diagram, to obtain the two auxiliary voltages is very simple and cost-effective.
It is suggested that the diodes are fast types (trr < 50nsec) ; should slower diodes be required some more turns have to be added to the auxiliary winding.
BATTERY CHARGER
When the device has to be used as current generator it is necessary to avoid the internal current limiter is operated fig. 34 shows the circuit realizing constant current limitation. In this way it is possible to obtain a 6V, 12V and 24V battery charger. For each of these voltages a max. current of 4A is available, which is large enough for batteries up to 40-45Ah (for 12V type). With reference to the electric diagram through tne 2KQ potentiometer the max output current is set, while through the Rl - R2 output divider the voltage is set. (Rl may be replaced by either a potentiometer or a 3 position switch, to directly obtain the three 6V, 12V and 24V voltages).
Figure 34 : Battery charger circuit illustrating how the device is used to regulate the output current.
~.7Kn
L296
11Mn
L=300j.JH
l00mn
2.2Kll.
ZI 5.6V
VO
SCHOTTKY
DIODE 7A
10Kll.
5
l;F lOKn
2.100
R2
HIGHER INPUT VOLTAGE
Since a maximum input voltage of 46V (operating value) may be applied to the device the diagram shown in fig. 35 may be used when it is necessary to exceed this limit.
This system is particularly useful when operating at low output voltages. In this case a mean current hoc which has a low value when compared to 10 is obtained. In fact, since Vo = Vi (ToNfT) and Vo 10 = Vi hoc (assuming the device has an ideal efficiency), it follows that hoc = 10 (ToNfT).
28/42 462
APPLICATION NOTE
Assuming to be :
Vo = 5V 10 = 4A and V3 ~ 37V
it follows that :
TON IT =Vo I Vi =3"57 =0.135
hoc =4 x 0.135 = 0.54A.
With input voltage 50V and 10 = 4A, the external transistor dissipates about 7W. High good efficiency is still achieved, around 74% ; in the real case, considering also the device losses, an efficiency around 62% is achieved.
During output short circuits the external transistor is not overloaded because in this condition liOC re-
duces to values lower than 100mA. It is not possible to realize this application with series post-regulator because the efficiency would be unacceptably low.
MOTOR CONTROL
The L296 is also suitable for use in motor controls applications. Fig. 36 shows how to use the device to drive a motor with a maximum power of about 1OOW and provided with a tachometer generator for a good speed control.
Figure 35 : The maximum input voltage can be raised above 46V by adding a transistor as shown here.
IC3 3300l'F SOV
I
5 - 6783
Figure 36: With a tacho dynamo supplying feedback the L296 can be used as a motor speed controller.
+Vj 2xnOOfJF
I
5 - 6167
3
Z
L296
7-11
5
9
1..7/-lF
I
Cl ]30 PF
R2
y' f"" 10KIl
. 10K!l
29142 463
APPLICATION NOTE
HIGHER CURRENT REGULATORS
It is possible to increase the output current to the load above 4A through the use of an external power transistor. Fig. 37 shows a suitable circu it. The frequency is around 40kHz to prevent the device from loosing excessive power due to switching on the external power.
The circuits shown in fig. 38 and fig. 39 show how current limitation may be realized in two different ways : through a sensing resistor connected in series with the collector of the external power transistor or through a current transformer.
In the first case, the sensing resistor is a low value resistor able to withstand the maximum load current required. The VCE of the power transistor is higher than its VCEsat ; when the resistor is connected in series to the collector VCE is reduced; consequently s.ince the overall dissipated power is constant, the power dissipated by the sensing resistor is subtracted from that dissipated by the power transistor. The values indicated in figs. 38 and 39 realize adjustable current limitation for load currents around 10A.
Figure 37 : The output current may be increased by adding a power transistor as shown in this circuit.
10.000,..F SOY
.12V
6.2 KO
YHEZOO1 22001':[
O.7KO
30/42
464
APPLICATION NOTE
Figure 38: This circuit shows how current limiting for the external transistor is obtained with a sensing resistor.
I 10000 ",F
3
L296
2
2N2906A
5-676511
Figure 39 : A small transformer is used in this example for current limiting.
Vi ~--~-------.-----------------------,
3
L296
4
150 nF lN4001
02 01 lN4001
5- 6766
Tl = MAGNETICS TOROID TYPE 55121 - A2
lK n
31/42
465
APPLICATION NOTE
STEP-UP CONVERTER
DESCRIPTION OF OPERATION
With the L296 it is also easy to realize a step-up converter, by using a MOS power transistor. Fig. 40 shows the electric diagram of the step-up converter. The frequency is 100kHz, operation is in discontinuous mode and the device internal current limiter is used. Therefore no other external protection is required.
The input voltage could be a 12V car battery, from which an output voltage of 35V may be obtained. Lower output voltage of 35V may be obtained. Lower output voltage values may be obtained byreducing the value of R7.
Fig. 41 shows the diagram of the circuit realizing the step-up configuration.
When the transistor 01 is ON, the inductance L charges itself with a current given by :
.
IL=
TVi"
t
The peak current in the coil is : Vi
Ipeak = -L- TON
Figure 40: A Step-up Converter using a Power MaS Transistor.
02
= Yo 3SV
~_ _ _¥ - - - . . _......../V",-~........_ .....-D0.5A
r2x100pF
C7 40V
R7 33K.ft
5-67110
HH 4.7Kll
Figure 41 : Basic Schematic for Step-up Configurations.
5-6779
In this configuration, unlike the step-down configuration, the peak currentis not strictly related to the load current. The energy stored in the coil is suc32/42 466
cessively discharged across the load when the transistor switches OFF. To calculate the 10 load current,
the following procedure may be used:
""12
L
2 I peak
=
Vo
10
T
I L 12 peak 0= 2 Vo T
For a greater output power to be available, the internallimitation must be replaced by an external circuit to protect the external power devices and to limit the current peak to a convenient value. A dual comparator (LM393) with hysteresis is used to avoid uncertainties when the current limitation operates. The electric diagram is shown in fig. 42.
~
11< en i"@ \"len.n ~:i!
~o
"@":eIn:
f~'1zio
w
.j:>. (J)
~
--J
I\)
s- 6781
~1l.
=- L = 50)J H
SGS8R20 OR
BYW80
R9
33K n
!l
to C (;
""I\)
(-xI)<I-0"
(I)::::r
'3~:<~"~
*"9
<::
"oC)
~
(I)
~
(f)
o::::r ~"
::J <0
o:::;:::r S-
(I) C)
<::
iil
;a.
3"
5-
<0
C
::J
C)
g"
::J
iii"
Cil e!.. N" ~
o Z
-I
m
APPLICATION NOTE
LAYOUT CONSIDERATIONS
Both for linear and switching power supplies when the current exceeds 1A a careful layout becomes important to achieve a good regulation. The problem becomes more evident when designing switching regulators in which pulsed currents are over imposed on dc currents. In drawing the layout, therefore, special care has to be taken to separate ground paths for signal currents and ground paths for load currents, which generally show a much higher value.
When operating at high frequencies the path length becomes extremely important. The paths introduce
distributed inductances, producing ringing phenomena and radiating noise into the surrounding space.
The recirculation diode must be connected close to pin 2, to avoid giving rise to dangerous extra negative voltages, due to the distributed inductance.
Fig. 43 and fig. 44 respectively show the electric diagram and the associated layout which has been realized taking these problems into account. Greater care must be taken to follow these rules when two or more mutually synchronized devices are used.
Figure 43 : Typical application circuit showing how the signal and power grounds are connected.
Vi _ ~~ _~__________- , Rl
RESET 14
R6
10
l I
R7
Cl
R2
10Jo'F
100
63V
KA
RS
4.7
C2
Kfi
2.2"
GNOo-~----------------~------------------
C7. C8 : EKR (ROE)
INHIBIT
__--->I<--______~"__---'L---<J GNO
SUGGESTED INDUCTOR (L1)
Core Type
No
Wire
Air
Turns Gauge Gap
Magnetics 58930 A2MPP
43 1.0 mm.
Thomson GUP 20 x 16 x 7
65 0.8 mm. 1 mm.
Siemens EC 35/17/10 (86633 & - G0500 x 127)
40 2 x 0.8 mm.
VOGT 250 J.lH Toroidal Coil, Part Number 5730501800
34142
468
Resistor Value for Standard Output Voltages
Vo
12 V 15 V 18 V 24 V
Rs
4.7 kQ 4.7 kQ 4.7 kQ 4.7 kQ
R7
6.2 kQ 9.1 kQ 12 kQ 18 kQ
APPLICATION NOTE
Figure 44 : A Suitable PCB Layout for the Figure 43 Circuit realized in Accordance with the Suggestions in the Text (1 : 1 scale).
HEATSINK DIMENSIONING
The heats ink dissipates the heat produced by the device to prevent the internal temperature from reacing values which could be dangerous for device operation and reliability.
Integrated circuits in plastic package must never exceed 150'C even in the worst conditions. This limit has been set because the encapsulating resin has problems of vitrification if subjected to temperatures of more than 150'C for long periods or of more than 170'C for short periods. In any case the temperature accelerates the ageing process and therefore influences the device life; an increase of 10'C can halve the device life. A well designed heatsink should keep the junction temperature between 90'C and 110'C. Fig. 45 shows the structure of a power device. As demonstrated in thermo-dynamics, a thermal circuit can be considered to be an electrical circuit where R1, R2 represent the thermal resistance of the elements (expressed in 'C/W) (see fig. 46).
C1, C2
I V
are the thermal capacitance (expressed in 'C/W) is the dissipated power is the temperature difference with respect to the reference (ground)
This circuit can be simplified as shown in fig. 47, where:
Cc is the thermal capacitance of the die plus that of the tab.
Ch is the thermal capacitance of the heatsink Rjc is the junction case thermal resistance Rh is the heatsink thermal resistance Figure 45.
PLASTIC PACKAGE
5 - 5 511
Figure 46.
35/42 469
APPLICATION NOTE
Figure 47.
5-5536
But since the aim of this section is not that of studing the transistors, the circuit can be further reduced as shown in figure 48. Figure 48.
ficult. This concept is better explained by the graph in fig. 51 which shows the case (and therefore junction) temperature variation as a function of the distance between two dissipating elements with the same type of heatsink and the same dissipated power. The graph in fig. 51 refers to the specific case of two elements dissipating the same power, fixed on a rectangular aluminium plate with a ratio of 3 between the two sides. The temperature jump will depend on the total dissipated power and on the devices geometrical positions. We want to show that there exists an optimal position between the two devices:
d = --}. sid e of the plate
Figure 49.
If we now consider the ground potential as ambient
temperature, we have:
Tj=Ta+(Rjc+Rh)Pd
a)
Tj - Ta - Rjc Pd
b)
Rh =
Pd
c)
Thermal contact resistance depends on various factors such as the mounting, contact area and planarity of the heatsink. With no material between the device and heatsink the thermal resistance is around OSC/W ; with silicone grease roughly 0.3"C/W and with silicone grease plus a mica insulator about OA"C/W. See fig. 49. In application where one external transistor is used together, the dissipated power must be calculated for each component. The various junction temperature can be calculated by solving the circuit shown in fig. 50. This applies if the dissipating elements are fairly close with respect to the dissipator dimensions, otherwise the dissipator can no longer be considered as a concentrated constant and the calculation becomes dif-
Figure 50.
Fig. 52 shows the trend of the temperature as a function of the distance between two dissipating elements whose dissipated power is fairly different (ratio 1 to 4). This graph may be useful in application with two L296 synchronized.
36/42
470
Figure 51.
APPLICATION NOTE
Te ('C)
70 65
· -10 Figure 52.
50
t -7 - 5 ,, -3 -2 -1
' ..
d (em)
,
.'3 :4 5
6
7 6 9
5-5516
I
I
10
..
150 140
-
-
T - T·~
130
120
A
,
---_.-...6. - --- I--.
I
1 '
___ "6-0
70
I
I
I
60
-10
-5:
B
'" "'-_,
.-J
---- I
,
,5
10
I....
d (em)
5 - 55'7
37/42
471
APPLICATION NOTE
APPENDIX A
CALCULATING SYSTEM STABILITY
This section is intended to help the designer in the calculation of the stability of the whole system.
Figure A1 shows the entire control system of the switching regulator.
The problem which arises immediately is the transfer function of the PWM block and output stage, which is non-linear. If this function can be considered linear the analysis is greatly simplified.
Since the circuit operates at a constant frequency and the internal logic is fairly fast, the error introduced by assuming that this function is linearis minimized. Factors which could contribute to the non-linearity are an excessive delay in the output power transistor, ringing and parasitic oscillations generated in the power stage and non-linearity introduced by magnetic part.
In the case of the L296, in which the power transistor is internal and driven by well-controlled and efficient logic, the contribution to non-linearity is further reduced.
For the assumption of linearity to be valid the cut-off frequency of the LC filter must be much lower than the switching frequency. In fact, switching operation introduces singularities (poles) at roughly half the switching frequency. Consequently, as long as the LC filter is still dominant, its cut-off frequency must be at least an order of magnitude lower than the switching frequency. This condition is not, however, difficult to respect. The characteristics of LC filter affect the output voltage waveforms ; is generally much less than an order of magnitude below the switching frequency.
Figure A1 : The Control Loop of the Switching Regulator.
5-6659
GAIN OF THE PWM BLOCK AND OUTPUT STAGE
The equation which links Vo to Vi is:
TON V o = VTi -
A variation L'>TON in the conduction time of the switching transistor causes a corresponding variation in the output voltage, L'>Vo, giving:
L'>Vo _ Y.J..
L'>TON - T
Indicating with Vr the output voltage of the error amplifier, and with Vet the amplitude of the ramp (the difference between the maximum and minimum values), TON is zero when Vr is atthe minimum value and equal to T when Vr is at a maximum. Consequently:
L'>TON
T
L'>Vr = Vct
The gain-is given by :
I':No
Vi
L'>Vr = 'Jct
38142
472
Since Vet is absolutely constant the gain of the PWM block is directly proportional to the supply voltage Vi.
Figure A2 : Open Loop Frequency and Phase Response of Error Amplifier.
G,
(dB)
60
50
"" G,
1'\.\
-40
'f \.\
30
"~
-80
,6
\ \
-120
10
\
\
-10
10 100 IK
10K lOOK 1M
f (Hz)
APPLICATION NOTE
The error amplifier is a transconductance amplifier (it transforms a voltage variation at the input into a current variation at the output). It is used in open loop configuration inside the main control loop and its gain and frequency response are determined by a compensation network connected between its output and ground.
Inthe application aseries RC network is recommended which gives high system gain at low frequency - to ensure good precision and mains ripple rejection and a lower gain at high frequencies to ensure stability of the system. Figure A2 shows the gain and phase curves of the uncompensated error amplifier.
The amplifier has one pole at about 7kHz and a phase shift which reaches about - 90' at frequencies around 1MHz.
The introduction of a series network Rc Cc between the output and ground modifies the circuit as shown in figure A3.
Figure A4 shows the gain and phase curves of the compensated error amplifier.
Figure A3 : Compensation Network of the Error Amplifier.
CALCULATING THE STABILITY
For the stability calculation refer to the block diagram shown in figure A5.
The transfer functions of the various blocks are rewritten as follows.
The simplified transfer function of the compensated
error amplifier is :
GEA = gm Zc = 1 + s Rc Cc
S Cc
1
(gm = 2500 )
The DC gain must be considered equal to :
Ao = gm Ro PWM block and output stage:
Vi GpWM=
LC FILTER: 1 + S C· ESR
S2 LC + S C ESR + 1 where ESR is the equivalent series resistance of the output capacitor which introduces a zero at high frequencies, indispensable for system stability. Such a filter introduces two poles at the angular frequency.
1
000 = VIC
Refer to the literature for a more detailed analysis.
Feedback: consists of the block labelled ex ex = 1 when Vo = VREF (and therefore Vo = 5.1V)
and
when Vo > VREF
Figure A4 : Bode Plot Showing Gain and Phase of Compensated Error Amplifier.
II"K:: - - - - - - -- - - - UNCOMPENSATED - - C O M P E N S ATEO
""I
I "-
I
1
1 1
~ /'
~~
, I
""-
I ,
:""-
I "
I
'I "\!
,,', !'\
Vl
"' ISO "a:' 135 "'0"'
90 '":l'
J
1
:
r "-
1
1
1
1
2TTR oCc 2TIRcCc 2TrRoCo 2nRcCo
$-6957
Figure AS : Block Diagram Used in Stability Calculation.
39/42 473
APPLICATION NOTE
To analyse the stability we will use a Bode diagram. The values of Land C necessary to obtain the required regulator output performancen, once the frequency is fixed, are calculated with the following formulae:
(Vi- Va) Vo
Vi f L'>IL
C=
(Vi- Va) Vo
8L f2 L'>Vo
Since this filter introduces two poles at the angular frequency
1 (00 = .j LC
we place the zero of the Re Ce network in the same place:
1 COz = Rc Cc
Taking into account also the gain of the PWM block, the Bode plot of figure A6 is obtained.
The slope where the curve crosses the axis at OdB is about 40dB/decade therefore the circuit is unstable.
Taking into account now the zero introduced by the
equivalent series resistance (ESR) of the output ca-
pacitor, we have further condition for dimensioning
the Re Ce network. Knowing the ESR (which is sup-
plied by the manufacturer for the quality compo-
nents) we can determine the value of Re so that the
axis is crossed at OdB with a single slope. The zero
introduced by the ESR is at the angular frequency:
WzESR =
1 ESR· C
The overall Bode diagram is therefore as shown in figure A7.
Figure A6 : Bode Plot of System Taking Filter and Compensation Network into Account.
dB
Figure A7 : Bode Plot of Complete System Taking into Consideration the Equivalent Series Resistance of the Output Capacitor.
dB
S· 6855
DC GAIN AND LINE REGULATION
Indicating the open-loop gain of the error amplifier with Ao, the overall open-loop gain of the system is :
Vi
R2
Vet
When Va = VREF, the gain becomes: Vi
At=Ao -Vet
Considering the block diagram of figure A8 and calculating the output variation L'>Va caused by a variation of Vi, from the literature we obtain:
L'>Vi
Va
AD Vi · ~
Vet
Rl + R2
This espression is of general validity. In our case the percentage variation of the reference must be added by vector addition.
Figure AS : Block Diagram for Calculation of Line Regulation.
r--
+
Vi
-
AO t-- ""Vct
"-'0 5-6856
I R2 I
I I Rl+R2
5- 6853
40/42 474
APPLICATION NOTE
APPENDIX B
REDUCING INTERFERENCE
The main disadvantage of the switching technique is the generation of interference which can reach levels which cause malfunctions and interfere with other equipment.
For each application it is therefore necessary to study specific means to reduce this interference within the limits allowed by the appropriate standards.
Among the main sources of noise are the parasitic inductances and capacitances within the system which are charged and discharged fastly. Parasitic capacitances originate mainly between the device case and the heatsink, the windings of the inductor and the connection wires. Parasitic inductances are generally found distributed along the strips of the printed circuit board.
Fast switching of the power transistors tends to cause ringing and oscillations as a result ofthe parasitic elements. The use of a diode with a fast reverse recovery time (trr) contributes to a reduction in the noise flowing by the current peak generated when the diode is reverse biased.
Radiated interference is usually reduced by enclosing the regulator in a metal box.
To reduce conducted electromagnetic interference (or radio frequency interferences - RFI) to the levels
permitted a suitably dimensioned filter is added on the supply line. The best method, generally, to reduce conducted noise is to filter each output terminal of the regulator. The use of a fixed switching frequency allows the use of a filter with a relatively narrow bandwidth. For off-line switching regulators this filter is usually costly and bulky. In contrast, if the device is supplied from a 50/60 Hz transformer the RFI filter problem is greatly reduced.
Tests have been carried out at the laboratories of Roederstein to determine the dimensions of a mains supply filter which satisfies the VDE 0871/6.78, class B standard. The measurements (see figs. B1 and B2) refer to the application with the L296 supplied with a filtered secondary voltage of about 30V,
with Va =5.1 V and 10 =4A. The switching frequency
is 100kHz.
Figure B1 shows the results obtained by introducing on the transformer primary a 0.01 f.lF/250V class X capacitor (type ERO F1772-31 0-2030). To reduce interference further below the limit set by the standards an additional inductive filter must be added on the primary of the transformer.
Figure B2 shows the curves obtained by introducing this inductive filter (type ERO F1753-21 0-124). Measurements have also been performed beyond 30MHz ; the maximum value measured is still well below the limit curve.
Figure 81 : EMI Measurements with a Capacitor Connected across the Primary Transformer with Screen Grounded (A)
~ t--"--,
JO
j
20
, : w !
i
I~I' 1I\~'j:~
I! i i i
J II
~
10
10KHz JO
100
300
1MIt.
10
30
41/42
475
APPLICATION NOTE Figure 82 : EMI results with the addition of an inductive filter on the mains input.
dB 90 80 70 60 50
~
30 20 10
10KHz 30
42142
476
APPLICATION NOTE
DESIGNING MULTIPLE-OUTPUT POWER SUPPLIES WITH THE L296 AND L4960
Multiple output supplies can be realized simply and economically using the SGS THOMSON Microelectronics L296 and L4960 high power switching regulators. This note describes several practical circuits of this type.
/
Most of the switching regulators produced today have multiple outputs. The output voltages most frequently used - at least for powers up to 50W - are + 5V - 5V, + 12V and - 12V. In these supplies the 5 V output is normally the output which delivers the highest current and requires the highest precision. For the other voltages - particularly the negative outputs - less precision (± 5 % ± 7 %) is usually sufficient. Often, however, for high current 12V outputs better stabilization and greater precision (typically
AN245/1288
± 4 % - the output tolerance of an L7800 series li-
near regulator) are required. Multiple output supplies which satisfy these requirements can be realized using the SGS THOMSON L296 and L4960 high power switching regulator ICs, Several practical supply designs are described below to illustrate how these components are used to build compact and inexpensive mUlti-output supplies.
1/10
477
APPLICATION NOTE
DUAL OUTPUT 15W SUPPLY
Vo1 = 5V/3A, Vo2 = 12V/150mA A single L296 is used in this application to produce two outputs. The application circuit, figure 1, illustrates how the second output (12V) is obtained by adding a second winding to the output inductor. Energy is transferred to the secondary during the recirculation period when the intemal power device of the L296 is OFF.
Since the 12V output is not separated from the 5V output fewer turns are necessary for the second
winding, therefore less copper is needed and load regulation is improved.
In applications of this type it is a good rule to ensure that the power drain on the auxiliary output is no more than 20-25% of the power delivered by the main output.
Table 1 shows the performance obtained with this dual output supply. This circuit operates at a switching frequency of 50KHz.
Figure 1 : Dual Output DC-DC Converter (5V/3A, 12V/150mA).
20V to 40V
11
rr2.2nF
9
L296
D2 N2 2
SGSBR20
D1
OR
BVW80
+12V
I-. 22~0,o..v.F EKR
10
I 33nF
Transformer: magnetics 58930, N1 =30 turns, N2 = 40 turns.
Table 1.
Output Voltage 101 =3A Output Ripple Line Regulation 101 =3A Line Regulation 101 = 700mA Load Regulation 101 = 700mA-' 3A Load Regulation 101 = 700mA Load Regulation 101 =3A Efficiency
Parameter
Vi = 30V
102 = 150mA
20V" Vi" 40V 102 = 150mA
20V" Vi" 40V 102 = 100mA
Vi = 30V 102 = 150mA Vi = 30V 102 = 100 .. , 150mA Vi = 30V 102 =100 -, 150mA Vi = 30V V01 = 5.120V 101 =3A V02 = 12.089V 102 = 150mA
2/10
478
S -8056 11
V0 1 5.120 70
15 15 10 0 0
V02
Unit
12.089
V
40
mV
30
mV
10
mV
130
mV
40
mV
40
mV
75
%
APPLICATION NOTE
DUAL OUTPUT 7.SW SUPPLY
VOl = 5VI1.SA, Vo2 = 12Vf100mA The same technique - adding a secondary winding - can also be used to produce an economical and simple dual output supply with the L4960, a device
containing the same control loop blocks as the L296 and a 2A output stage (fig. 2). Though this circuit costs very little the performance obtained (see table 2) is more than satisfactory. The switching frequency is 50kHz.
Figure 2 : Dual Output DC-DC Converter (5Vf1.SA, 12Vf1 OOmA).
+15V 10 35 V
1000 ,oF
~
L4960
, K.n. 1nF
~~ BVV 28-50
+12V
02 40V 20, 220f'F
· N2 Et<RI
L1--
Nl·
SGS8R20
01
OR
BYWBO
.5V
II- 220~F i.OV EKR
I J3nF
Transformer: magnetics 58206. Nl =30 lurns. N2 = 40 lurns.
Table 2.
Output Voltage 101=1.5A Output Ripple line Regulation
101 = 1.5A
line Regulation
101 =500mA
Load Regulation
101 =0.5A -4 l.5A
Load Regulation
101 = 500mA
Load Regulation
101 = 1.5A
Efficiency
Parameter
Vi = 25V 102 = 100mA
15VSViS 35V 102';' 100mA
15VSViS 35V
102 = 50mA VI = 25V 102 = 100mA Vi =25V 102 = 50mA -4 100mA
Vi = 25V
102 = 50mA -, 100mA
Vi = 25V VOl = 1.5V V02 = 100mA
S-8057/1
Val 5.050
50 7
7
3
a a
V02 12.010
30 75 60 100 55 50
Unit V mV mV mV mV mV mV
78
%
3/10 479
APPLICATION NOTE
TRIPLE OUTPUT15W SUPPLY
VOl =5V/3A, Vo2 = 12V/1 OOmA, Vo3 =-12V/1 OOmA
Figure 3 shows how to obtain two auxiliary outputs (± 12V) which are isolated from the5V output. For this output power range an L296 is used.
To ensure good tracking of the 12V and -12V outputs the secondary outputs in this application should be bifilar wound.
This circuit operates at 50KHz and gives the performance indicated in table 3.
Figure 3 : Triple Output DC-DC Converter (5V/3A, 12V/1 OOmA).
BYV 28-50 03
20V 10 40Y 11
l296
9
Kt5l1ll~.
I 33nF
Transformer: magnetics 58206, Nl = 30 turns, N2 = 40 turns.
Table 3.
Output Voltage 101 ;3A Output Ripple Line Regulation 101 ; 700 mA Line Regulation 101 ;3A Load Regulation 101 ; 0.7A --> 3A Load Regulation 101 ;3A
Load Regulation 101 ;3A 102; 50 --> 100mA Efficiency
Parameter
Vi = 30V 102 = 103 = 100mA
20V $. Vi $ 40V 102 ; 103 = 100mA 20V $ Vi $ 40V 102; 103; 100mA Vi; 30V 102 ; 103 ;100mA Vi; 30V 102 ; 100mA 103; 50 --> 100mA
Vi = 30V 103; 100mA
v jo-!"'-...AA~----*...,..t=4---o-12
~-....-~:--:,_-~::...:..:"'--".:....o"'S.lV
10
S-80!l'Hl
VOl 5.057
80 15 18 4
0
0
V02 12.300
30 60 100 150
125
V03
Unit
- 12.300
V
30
mV
60
mV
100
mV
150
mV
52
mV
50
120
mV
76
%
4/10
480
APPLICATION NOTE
TRIPLE OUTPUT 7.5W SUPPLY
Vol = 5V/1.5A, Vo2 = 12V/50mA, Vo3 =- 12/50mA
For lower output powers, the L296 in the previous
application may be replaced by an L4960 as shown in figure 4. The performance of this circuit is indicated in table 4.
Figure 4: Triple Output DC-DC Converter (5V/1.5A, 12V/50mA, -12V/50mA).
+15V to 35V
BYV 26-50
02
...-____1>---____>l--_-{)+12V
E~KORVh220,uF
40V EKR
22Oj.JF
v 03
'---____I--~-{) 12
BVV 26-50
L4960
Table 4.
Output Voltage 101 = 1.SA Output Ripple Line Regulation 101 = SOOmA Line Regulation 101 = 1.5A Load Regulation 101 = O.SA --> 1.SA Load Regulation
101 = 1.SA 103 = 20 --> 50mA
Load Regulation 101 = 1.SA 102 = 20 --, SOmA
Efficiency
Parameter Vi =2SV 102 = 103 = SOmA
1SV" Vi" 3SV 102 = 103 =SOmA 1SV"Vi ,,3SV 102 = 103 = 50mA Vi = 25V
102 = 103 = SOmA Vi = 25V 102 = SOmA
Vi = 2SV
103 = 100mA
~--------~----------~+5V
220}JF
I ~OV EKR
5-805912
VOl
5.040 60 5 4 5
0
0
V0 2
12.020 30 80 60 120
15
V03
- 12_020 30 80
60 120
Unit V mV mV mV mV
50
mV
50
15
mV
70
%
5/10 481
APPLICATION NOTE
THE L296 AND L4960 HIGH POWER SWITCHING REGULATORS
The SGS THOMSON L296 is a monolithic stepdown switching regulator assembled in the 15-pin Multiwatt package. Operating with supply input voltages up to 46V it provides a regulated 4A output variable from 5.W to 40V.
Internally the device is equipped with current limiter, soft start and reset (or power fail) functions, making it particularly suitable for supplying microprocessors and logic.
'The preCision of the L296's internal reference (± 2%) eliminates the need for external dividers or trinning to obtain a 5V output.
The synchronization pin allows synchronous operation of several devices at the same frequency to avoid generating undesirable beat frequencies.
The L4960 is a similar device assembled in the 7lead Heptawatt package. Like the L296 it has a maximum input voltage of 46V and it provides a regulated output voltage variable from 5V to 40V with a maximum load current of 2.5A. Current limiting, soft start and thermal protection functions are included.
The thermal protection circuit in both the L296 and L4960 has a hysteresis of 30°C to allow soft restartingafter a .fault condition.
THE STEP DOWN CONFIGURATION
Figure 5 shows the basic structure of a step down switching regulator. The transistor Q is used as a switch and the ON and OFF times are determined by the control circuit.
When Q is saturated current flows· from the supply, Vi, to the load through the inductor L. Neglecting the saturation voltage of Q, Ve =: Vi.
When Q is OFF, current continues to flow in the inductor L, in the same direction, forcing the diode into conduction immediately therefore Ve is negative. In these conditions the load current flows through L and D.
The·average value of the current in the inductor is equal to the load current. In the inductor a triangular current ripple equal to . ~IL is added to this average current.
During the tirne when Q is ON this ripple is : ~lL= (Vi-Vo)ToN
L
and when Q is off it is : Vo' TOFF
L
Equating these expression and assuming that the
transistor and diode are ideal we obtain:
TON Vo=Vi' -T-
TON is the conduction time of the transistor
T is the oscillator period
The absolute average current in the supply is there' fore:
lioc = 10 , T~N
Once the working frequency and desired ripple current have been fixed the value of the inductor L is given by :
L= (Vi-Vo)Vo Vi f ~ IL
and the value of the capacitor C required to give the desired output voltage ripple (~ V) is :
C- (Vi-Vo)Vo - 8 L f2 ~ fo
This capacitor must have a maximum ESR given
by:
.
~Vo
ESRMAX~=IL--
And, finally, the minimum load current, IOMIN, must
be:
IOMIN= 2~IL =
(Vi - Vol Vo 2 Vi fL
Figure 5 : Basic STEP-DOWN Configuration.
VE
l
'l
;c
RI
01
ESR
Rl
;0
1
v, LOAD
I ILOAO
VRF
6/10 482
APPLICATION NOTE
30W DC-DC CONVERTER
Designing power supplies in the 30-40W range is becoming increasingly difficult because it is here that there is the greatest need to maintain performance levels and reduce costs. The application proposed here is very competitive because it exploits new ICs to reduce size, number of components and assembly costs.
This solution, the DC-DC converter, compares very favourable with off-line switching supplies in terms of cost. DC-DC converters can, in fact, be realized
even by designers with little experience and allows the convenience of working with low voltages, Offline switching supplies are only preferable when the weight and size of the mains transformer in a DCDC converter would be excessive.
In this circuit, figure 6 two devices are used, an L296 and an L4960. The L296 is used, to supply a 5V output with a current of 3A and the auxiliary - 5V/1 OOmA output and the L4960 is used to provide the 12V/1.5A output and the auxiliary - 12V/1 OOmA output.
Figure 6 : Multioutput DC-DC Converter with L296 and L4960 (5V I 3A, 12V / 1.5A, -12V/1 OOmA, -5V/100mA).
20V!!-:;Vi~40V
0--- .. -..--.-T""---,
:r JOO"":r
SOV
470
~f
EYf
9
: I 3Jn,
L296
SGS~.:-ll r--l
OR
BYWBO II
.l2
-5.2V
lNS822
0.1 A
~-~--~-.----O
lKll 10
12
1000/0J'
T 2SV
lKll
·
EKR
14
RESET
13 2A
IseR
I
9K.1n
L4960
S-&07311
7/10 483
APPLICATION NOTE
Table 5 shows the performance obtained with this power supply.
TableS.
Output Voltage 101 =3A 102 = 100mA Output Ripple
Line Regulation 101 .. 1A 103 = 0.5A
Load Regulation 101 = lA to 3A
103 = 0.5 to 1.5A Load Regulation 101 =3A
103 = 1.5A Load Regulation 101 = 1A
103 = 0.5A Line Regulation 101 =3A
103 = 1.5A
Parameter Vi = 30V 103 = 1.5A 104 = 100mA
20V:;; Vi:;; 40V 102 = 100mA 104 = 100mA Vi = 30V 102 = 100mA 104 = 100mA Vi = 30V 102 = 50 -> 100mA 104 = 50 -> 100mA Vi = 30V 102 = 50 -> 100mA 104 = 50 -> 100mA 20:;; Vi:;; 40V 102 = 100mA 104 = 100mA
This application illustrates how two devices may be synchronized. Note also that the reset Circuit is used in this case to monitor the output voltage (see figure 7):
V01
V02
5.080 - 5010
V03 11.96
50
30
50
13 .
15
10
V04 12.00
40 20
Unit V mV mV
8
90
mV
3
80
mV
0
100
mV
0
100
mV
0
35
mV
0
90
mV
15
45
mV
15
40
mV
If a power fail function is required in place ofthe reset function the figure 6 circuit should be modified as shown in figure 8.
Figure 7 : Reset Output Waveforms.
OUTPUT NOW
AN INTERRUPTioN
STABLE,RESET OF SUPl'LY CAUSES
GOES ttlGtl RESEI OF MICRO
IOOmV OF HYSTERESIS
+ I
- j -- - -.:-...-----
AT POWER OOWN
------- /
. MICRO IS INHIBITED IMMEDIATELY
MONITORED VOLTAGE
I
I
RESET OUTPUT
8/10
484
Figure 8.
RESET
OUT
APPLICATION NOTE
12
l296
I
5-677.
CALCULATING THE POWER FAIL TIME
The 'power fail time' is defined as the time from when the power fail output (-pin 14) goes low to the time when the input voltage falls to the minimum level re-
Figure 9.
quired to maintain the regulated output (see figure 9). From this definition we can evaluate the energy balance.
Vi
P.F. WAVE fORM (PIN 14)
-+t-0ELAY RESET
I I I
L t PF
1
I
I I I I I I I
5-8074
9/10
485
APPLICATION NOTE
The energy which the filter capacitor C supplies to
the operating device while it discharges is :
E = 1/2 C (Vj2_ Vl)
(1)
The load drains a power of Po = Vo 10 . Taking into
consideration the average efficiency T\ (derived with
the input between Vj and V2), the power to be sup-
plied at the input of the device is :
Po
P0 2= -
(2)
T\
Equating the expressions (1) and (2) gives:
1/2 C (Vj 2 - V22) = - Po . tPF T\
where Vi is the input voltage at which the voltage on pin 12 reaches 5V (through the divider Rj/R2) ; V2 is the maximum input voltage below which the device no longer regulates.
Rearranging this expression to obtain C :
2 Po tPF C = T\ (Vj 2 _ V22)
EXAMPLE - Suppose that Vo = 5V, 10 = 3A,
Tpf = 10ms and Vi = 35V. Fixing Vj = 25V and
V2 = 10V we obtain:
_ 2 Po tPF _ 2 x 15 x 10 . 10-3 _
F
C - T\ (Vj 2 _ Vl) - 0.75 (252 -102) - 760!-l
We obtain choose a capacitor of 1000!-lF.
CROWBAR
The L296 includes an internal crowbar function; the only external component needed is an SCR. The intervention threshold of this block is fixed intemally at 20% of the nominal value of the internal reference.
In the figure 6 circuit the SCR is triggered by an overvoltage on the 5V output (usually the most important output to monitor) and shortcircuits to ground the 5V output and, through the diode which connects the two outputs, the 12V output.
Since the intemal current limiter in the device is designed to function as shown in figure 10 (that is, with pulsed output current) the SCR turns off in the gap between pulses and is re-activated gain if, when the device restarts softly, the fault condition has not been eliminated. But if the fault no longef"exists the SCR remains OFF and the output voltage returns to the normal value.
If the designer prefers the supply to remain off after the SCR has been activated the circuit can be modified as shown in figure 11. In this modification, when the SCR is triggered a very high current flows in the fuse, blowing it.
Since the filter capacitor can have a high value and be charged to high voltages the choice of SCR is important. The type used in this circuit - the TYP512 - is a plastic packaged SCR able to handle 12 Arms and 300A for 1Oms. The maximum forward and reverse voltages are about 50V.
If the crowbar circuit is not used it is advisable to connect pin 1 to ground or pin 10.
Figure 10 : Load Current in Short Circuit Conditions
(Vi = 40V, L = 300!-lH, f = 100KHz).
t: 5ms/div
Current at Pin 2 when the Output is Short Circuited.
Figure 11.
t: 5ms/div
FUSE
V; a-r=')--<t--~---l
I
~--i--'
5-6769
INPUT CROWBAR
10/10 486
APPLICATION NOTE
UC3842 PROVIDES LOW-COST CURRENT-MODE CONTROL
The fundamental challenge of power supply design is to simultaneously realize two conflicting objectives : good electrical performance and low cost. The UC3842 is an integrated pulse width modulator (PWM) designed with both these objectives in mind. This IC provides designers an inexpensive controller with which they can obtain all the performance advantages of current-mode operation. In addition, the UC3842 is optimized for efficient power sequencing of off-line converters and for driving increasingly popular POWERMOS.
This application note gives a functional description of the UC3842 and suggests how to incorporate the IC into practical power supplies. A review of currentmode control and its benefits is included and meth-
Figure 1 : Two-loop Current-mode Control System.
ods of avoiding common pitfalls discussed. The final section presents designs of two power supplies utilizing UC3842 control.
CURRENT-MODE CONTROL
Figure 1 shows the two-loop current-mode control system in a typical buck regulator application. A clock signal initiates power pulses at a fixed frequency. The termination of each pulse occurs when an analog of the inductor current reaches a threshold established by the error signal. In this way the error signal actually controls peak inductor current. This contrasts with conventional schemes in which the error signal directly controls pulse width without regard to inductor current.
AN246/1188
CLOCK
VERROR -~--=--=--=--
-.J VSENSE U U L ~ LATCH
OUTPUT
S-1819
1/15
487
APPLICATION NOTE
Several performance advantages result from the use of current-mode control. First, an input voltage feed-forward characteristic is achieved; i.e., the control circuit instantaneously corrects for input voltage variations without using up any of the error amplifier's dynamic range. Therefore, line regulation is excellent and the error amplifier can be dedicated to correcting for load variations exclusively.
For converters in which inductor current is continuous, controlling peak current is nearly equivalent to controlling average current. Therefore, when such converters employ current-mode control, the induc~ tor can be treated as an error-voltage-controlledcurrent-source for the purposes of small-signal analysis. This is illustrated by figure 2. The two-pole control-to-output frequency response of these converters is reduced to a single pole (filter capacitor in parallel with load) response.
One result is that the error amplifier compensation can be designed to yield a stable closed-loop converter response with greater gain-bandwidth than would be possible with pUlse-width control, giving the supply improved small-signal dynamic response to changing loads. A second result is that the error amplifier compensation circuit becomes simpler and better behaved, as illustrated in figure 3. Capacitor Ci and resistor Riz in figure 3a add a low frequency zero which cancels one of the two control-to-output poles of non-current-mode converters. For large-
signal load changes, in which converter response is limited by inductor slew rate, the error amplifier will saturate while the inductor is catching up with the load. During this time, Ci will charge to an abnormal level. When the inductor current reaches its required level, the voltage on Ci causes a corresponding error in supply output vol-tage. The recovery time is Riz Ci, which may be milleseconds. However, the compensation network of figure 3b can be used where current-mode control has eliminated the inductor pole. Large-signal dynamic response is then greatly improved due to the absence of Ci.
Figure 2 : Inductor Looks Like a Current Source to Small Signals.
VREF
Vi
VOLTAGE CONTROLLED CURRENT SOURCE
VO
I
':._1818
Figure 3 : Required Error Amplifier Compensation for Continuous Inductor Current Designs using (a) Dutycycle Control and (b) Current-mode Control.
(a)
(b)
2/15
488
S_7810
Figure 4 : UC3842 Block Diagram.
Y, GROUND
APPLICATION NOTE
VREF Sv SOmA
COMP 0 - - - - - - '
CURRENT SENSE
2R
R
'Y
6 --0
OUTPUT
Current limiting is simplified with current-mode control. Pulse-by-pulse limiting is, of course, inherent in the control scheme. Furthermore, an upper limit on the peak current can be established by simply clamping the error Voltage. Accurate current limiting allows optimization of magnetic and power semiconductor elements while ensuring reliable supply operation.
Finally, current-mode controlled power stages can be operated in parallel with equal current sharing. This opens the possibility of a modular approach to power supply design.
FUNCTIONAL DESCRIPTION
A block diagram of the UC3842 appears in figure 4. This IC will operate from a low impedance DC source of 10 V to 30 V. Operation between 10 Vand 16 V requires a start-up bootstrap to a voltage greater than 16 V in order to overcome the undervoltage lockout. Vcc is internally clamped to 34 V for operation from higher voltage current-limited sources (Icc S; 30 mAl.
UNDER-VOLTAGE LOCKOUT (UVLO)
This circuit insures that Vee is adequate to make the UC3842 fully operational before enabling the output
stage. Figure 5a shows that the UVLO turn-on and turn-off thresholds are fixed internally at 16 V and 10 V respectively. The 6 V hysteresis prevents Vee oscillations during power sequencing. Figure 5b shows supply current requirements. Start-up current is less than 1 mA for efficient bootstrapping from the rectified input of an off-line converter, as illustrated by figure 6. During normal circuit operation, Vee is developed from auxiliary winding WAUX with 01 and CIN. At start-up, however, CIN must be charged to 16 V through RIN. With a start-up current of 1 mA, RiN can be as large as 100 kQ and still charge CIN when VAe = 90 V RMS (low line). Power dissipation in RiN would then be less than 350 mW
even under high line (VAe = 130 V RMS) conditions.
During UVLO, the UC3842 output driver is biased to a high impedance state. However, leakage currents (up to 10 ~A), if not shunted to ground, could pull high the gate of a POWERMOS. A 100 kQ shunt, as showing in figure 6, will hold the gate voltage below 1 V
3/15 489
APPLICATION NOTE
Figure 5 : (a) Under-voltage Lockout and (b) Supply Current Requirements.
ICC Vi
(a)
Figure 6 : Providing Power to the UC3842.
<15m A
5_7107
_ _ <lmA+-:::::==!:~~
It:
Vi
lOY !6Y
(b)
Vi
5 _1811
OSCILLATOR
The UC3842 oscillator is programmed as shown in
figure 7a. Oscillator timing capacitor CT is charged
from VREF(5 V) through RTi and discharged by an internal current source. Charge and discharge times are given by :
te ~ 0.55 RT CT
td ~ RT CT In (
0.0063 RT- 2.7 0.0063 RT _ 4.0
)
frequency, then, is: f =-t-1--e + Id
For RT > 5 kn, td is small compared to Ie, and:
f~
1
~~
0.55 RT CT RT CT
4/15 490
APPLICATION NOTE
During the discharge time, the internal clock signal
blanks the output to the low state. Therefore, td limits
maximum duty cycle (DMAx) to :
te
td
DMAx = - - - = 1 - - -
te + td
1:
where 1: = 1/f = switching period.
The timing capacitor discharge current is not tightly controlled, so td rnay vary somewhat over tempera-
ture and from unit to unit. Therefore, when very precise. duty cycle limiting is required, the circuit of figure 7b is recommended.
One or more UC3842 oscillators can be synchronized to an extemal clock as shown in figure 8. Noise immunity is enhanced if the free-running os-
cillator frequency (f = 1/(tc + ld)) is programmed to be _ 20 % less than the clock frequency.
Figure 7 : (a) Oscillator Timing Connections and (b) Circuit for Limiting Duty Cycle.
GROUND 5
NE555 OI~CH 1
TRIG 2
(a)
Figure 8 : Synchronization to an External Clock.
EXTERNAL CLOCK
JlJU
I
, - - - vREF v;
..O.~:/JF
Rr
l
UC3842
f - - - Ryley
~ ~
..
cr
GND
l 47ft
_i-
~-1'1l
ERROR AMPLIFIER
The error amplifier (ElA) configuration is shown in figure 9. The non-inverting input is not brought out
(b)
O
tc
MAX = (IH + IL)
IH = 0.693 (RA + Rs) C
IL = 0.693 Rs C
to a pin, .but is internally biased to 2.5 V ± 2 %. The EIA output is available at pin 1 for external compensation, allowing the user to control the converter's closed-loop frequency response.
Figure 1Oa shows an EIA compensation circuit suit-
able for stabilizing any current-mode controlled topology except for flyback and boost converters operating with continuous inductor. current. The feedback components add a pole to the loop trans-
fer function at fp = 112 nRt Ct. Rt and Ct are chosen
so that this pole cancels the zero of the output filter capacitor ESR in the power circuit. Ri and Rt fix the low-frequency gain. They are chosen to provide as much gain as possible while still allowing the pole formed by the output filter capacitor and load to roll off the ioop gain to unity (OdS) at f ~ fswitehing/4. This technique insures converter stability while providing good dynamic response.
Continuous-inductor-current boost and flyback converters each have a right-half-plane zero in their transfer function. An additionai compensation pole is needed to roll off loop gain at a frequency less than that of the RHP zero. Rp and Cp in the circuit of figure 1Ob provide this pole.
5/15 491
APPLICATION NOTE
The E/A output will source 0.5 mA and sink 2 mAo A lower limit for Rt is given by :
Rt (MIN) VElA OUT(max) - 2.5 V =6 V - 2.5 V 7 kQ
0.5mA
0.5mA
E/A input bias current (211A max) flows through Ri, resulting in a DC error in output voltage (Va) given by:
~ Va(max) = (21!A) Ri
Figure 9 : UC3842 Error Amplifier.
It is therefore desirable to keep the value of Ai as
low as possible.
Figure 11 shows the open-loop frequency response of the UC3842 E/A. The gain represent an upper
limit on the gain of the compensated EIA. Phase lag
increases rapidly as frequency exceeds 1 MHz due to second-order poles at - 10 MHz and above.
s_ 7108
Figure 10 : (a) Error Amplifier Compensation Addition Pole and (b) Needed for Continu ous Inductor-current Boost ad Flyback.
Figure 11 : Error Amplifier Open-loop Frequency Response.
(a)
2.50V
G"
(dB )
PHASE
C·)
~ ~
60
"-~
·45
40
K ";:
"0
0
"\II '"
~. 180
10
100
He.
10K
lOOK 1M f{Hz)
(b)
6/15 492
2.S0V
APPLICATION NOTE
CURRENT SENSING AND LIMITING
The UC3842 current sense input is configured as shown in figure 12. Current-to-voltage conversion is done externally with ground-referenced resistor Rs. Under normal operation the peak voltage across Rs is controlled by the ElA according to the following relation:
VRS (pk) = Vc - 1.4 V 3
where: Vc = control voltage = E/A output Voltage.
Rs can be connected to the power circuit directly or through a current transformer, as figure 13 illus-
trates. While a direct connection is simpler, a trans-
former can reduce power dissipation in Rs, reduce errors caused by the base current, and provide level shifting to eliminate the restraint of ground-ref-
erence sensing. The relation between Vc and peak
current in the power stage is given by :
.
VRs(pk)
N
l(pk)=N( Rs )= 3Rs(Vc- 1.4)
where: N = current sense transformer turns ratio. = 1 when transformer not used.
Figure 12 : Current Sensing.
For purposes of small-signal analysis, the controlto-sensed-cu rrent gain is : i(pk) _ _N_
Vc - 3 Rs
When sensing current in series with the power transistor, as shown in figure 13, current waveform will often have a large spike at its leading edge. This is due to rectifier recovery and/or interwinding capacitance in the power transformer. If unattenuated this transient can prematurely terminate the output pulse. As shown, a simple RC filter is usually adequate to suppress this spike. The RC time constant should be approximately equal to the current spike duration (usually a few hundred nanoseconds).
The inverting input to the UC3842 current-sense
comparator is internally clamped to 1 V (figure 12).
Current limiting occurs if the voltage at pin 3 reaches
this threshold value, i.e. the current limit is defined
by:
iMAX =
N·1 V Rs
2R IV
R
S _7109
7/15 493
APPLICATION NOTE
Figure 13: Transformer-coupled Current Sensing. Figure 14 : Output Cross-conduction.
uc
3842
I)_781S
200ns/div.
TOTEM-POLE OUTPUT
The UC3842 has a single totem-pole output. The
outputtransistors can be operated to ± 1 A peak current and ± 200 rnA average current. The peak cur-
rent is self-limiting, so no series current-limiting resistor is needed when driving a power MOS gate.
Cross-conduction between the output transistors is minimal, as figure 14 shows. The average added power due to cross-conduction with Vi = 30 V is only 80 mW at 200 kHz.
Figures 15-17 show suggested circuits for driving POWERMOS and bipolar transistors with the UC3842 output. The simple circuit of figure 15 can be used when the control IC is not electrically isolated from the power MOS. Series resistor R1 provides damping for a parasitic tank circuit formed by the power MOS input capacitance and any series wiring inductance. Resistor R2 shunts output leakage currents (1 0 ~ maximum) to ground when the under-voltage lockout is active. Figure 16 shows an isolated power MOS drive circuit which is appropriate when the drive signal must be levelshifted or transmitted across an isolation boundary. Bipolar transistors can be driven effectively with the circuit of figure 17. Resistors R1 and R2 fix the on-state base current. Capacitor C1 provides a negative base current pulse to remove stored charge at turn-off.
PWMLATCH
This flip-flop, shown in figure 4, ensures that only a single pulse appears at the UC3842 output in any one oscillator period. Excessive power transistor dissipation and potential saturation of magnetic elements are thereby averted.
SHUTDOWN TECHNIQUES Shutdown of the UC3842 can be accomplished by two methods ; either raise pin 3 above 1 V or pull pin 1 below 1 V. Either method causes the output of the PWM comparator to be high (refer to block diagram, figure 4). The PWM latch is reset dominant so that the output will remain low until the first clock pulse following removal of the shutdown signal at pin 1 or pin 3. As shown in figure 18, an externally latched shutdown can be accomplished by adding an SCR which will be reset by cycling Vcc below the lower under-voltage lockout threshold (10 V). At this point all internal bias is removed, allowing the SCR to reset. Figure 15: Direct POWERMOS Drive.
12 t020V
UPS42 OUT~6~1 ~t05~11--~---4(~~
R1
GND
5
~-181f1
8/15
494
Figure 16: Isolated POWERMOS Drive.
18 to 30Y
FERROXCUBE
1811
LOO-3ca
APPLICATION NOTE
.1.
Figure 17 : Bipolar Drive with Negative Turn-off Bias.
12to30V
S_7817
UC3842 OUT~6~-I~--~---I-'--~--~
GND
,::»-78]8
AVOIDING COMMON PITFALLS
Current-mode controlled converters can exhibit performance peculiarities under certain operating conditions. This section explains these situations and how to correct them when using the UC3842.
SLOPE COMPENSATION PREVENTS INSTABILITIES
It is well documented that current-mode controlled converters can exhibit subharmonic oscillations when operated at duty cycles greater than 50 %.
Fortunately, a simple technique (usually requiring only a single resistor to implement) exists which corrects ihis problem and at the same time improves converter performance in other respects. This "slope compensation" technique is described in detail in Reference 6. It should be noted that "duty cycle" here refers to output pulse width divided by oscillator period, even in push-pull designs where the transformer period is twice that of the oscillator. Therefore, push-pull circuits will almost always require slope compensation to prevent subharmonic oscillation.
9/15
495
APPLICATION NOTE
Figure 18: Shutdown Achieved by (a) Pulling Pin 3 High (b) Pulling Pin 1 Low.
(a)
UC381,2
SHUTDOWN
(b)
TO CURRENT SENSE RESISTOR
SHUTDOWN
UC3842
Figure 19 illustrates the slope compensation tech-
nique. In figure 19a the uncompensated control volt-
age and current sense waveforms are shown as a
reference. Current is often ·sensed in series with the
switching transistor for buck-derived topologies. In this case, the current sense signal does not track
the decaying inductor current when the transistor is
off, so dashed lines indicate this inductor current.
The negative inductor current slope is fixed by the
values of output voltage (Va) and inductance (L) :
diL VL -VF-Vo -(VF+Vo)
dt =-L-= L
L
where : VF = forward voltage drop across the freew-
heeling diode. The actual slope (m2) of the dashed
lines in figure 19a is given by:
. Rs diL - Rs (VF + Va)
m2=~· Cit =
NL
where: Rs and N are aefined as the "Current Sensing" section of this paper.
In figure 19b, a sawtooth voltage with slope m has been added to the control signal. The sawtooth is synchronized with the PWM clock, and practice is
most easily derived from the control chip oscillator as shown in figure 20a. The sawtooth slope in figure 19b is m = m2l2. This particular slope value is significant in that it yields "perfect" current-mode control; i.e. with m2/2 the average inductor current follows the control signal so that, in the small-signal analysis, the inductor acts as a controlled current source. All current-mode controlled converters having continuous inductor current therefore benefit from this amount of slope compensation, whether or not they operate above 50 % duty.
More slope is needed to prevent subharmonic os-
cillations at high duty cycles. With slope m = m2,
such oscillations will not occur if the error amplifier
gain (AV(E/A)) at half the switching frequency (fsl2) is
kept below a threshold value (reference 6) :
Av (EtA)
it 2 Co < - - - c4- , , - m=m2
f = fsl2
where: Co = sum of filter and load capacitance
" = llfs
Slope compensation can also improve the noise immunity of a current-mode controlled supply. When the inductor ripple current is small compared to the average current (as in figure 19a), a small amount of noise on the current sense or control signals can cause a large pUlse-width jitter. The magnitude of this jitter varies inversely with the difference in slope of the two signals. By adding slope as in figure 19b, the jitter is reduced. In noisy environments it is sometimes necessary to add slope m > m2 in order to correct this problem. However, as m increases beyond m = m2l2, the circuit becomes less perfectly current controlled. A complex trade-off is then required ; for very noisy circuits the optimum amount of slope compensation is best found empirically.
Once the required slope is determined, the value of
RSLOPE in figure 20a can be calculated:
_ "VRAMP ·
_ 0.7 V ( RSLOPE) = ~ ( RSLOPE )
3 m - "tRAMP AVIE/A) - 'tI2
Z, I f,
t
Z, I fs
RSLOPE = -31-m.4-" .(ZF I fs) = 2.1 . m . " . ZF I fs
where: ZFI fs is the E/A feedback impedance at the switching frequency. For m·= mL : il'tRAMP RSLOPE = 1.7 " ( Rs (VNFL+ Vol ) ZF I fs
10/15
496
Figure 19 : Slope Compensation Waveforms: (a) No Compo (b) Compo Added to Control Voltage. (c) Compo Added to Current Sense.
APPLICATION NOTE
L_ INDUCTOR CURRENT CURRENT SENSE (TRANSISTOR CURRENT)
(a)
~ INDUCTOR C.uRRE.NT
(b)
CURRENT SENSE
i.--::-- I
TRANSI STOR
CURRENT
~_1829
Note that in order for the error amplifier to accurately replicate the ramp, ZF must be constant over the frequency range fs to at least 3 fs.
In order to eliminate this last constraint, an alterna-
tive method of slope compensation is shown in
figures 19c and 20b. Here the artificial slope is
added to the current sense waveform rather than
subtracted from the control signal. The magnitude
of the added slope still relates to the downslope of
inductor current as described above. The require-
ment for RSLOPE is now:
m = LlVRAMP (
Rf
) = 0.7 (
Rf
LltRAMP Rf + RSLOPE
,12 Rf + RSLOPE
R. SLOPE = -1.- m4 t- Rf - Rf = Rf (-1m-.4t - 1)
For m = m2:
1.4 NL RSLOPE = Rf ( Rs (VF + Vo) 't -1)
RSLOPE loads the UC3842 RT/CT terminal so as to cause a decrease in oscillator frequency. If RSLOPE » RT then the frequency can be corrected by decreasing RT slightly. However, with RSLOPE $ 5 RT the linearity of the ramp degrades noticeably, causing over-compensation of the supply at low duty cycles. This can be avoided by driving RSLOPE with an emitter-follower as shown in figure 21.
11115
497
APPLICATION NOTE
Figure 20 : Slope Compensation Added (a) to Control Signal or (b) to Current Sense Waveform. (a)
8 "REF
ZF
1 2.50V
UC3842
5 -7830
(b)
I --l:
I C,
"SENSE
FRO~ (/A
Figure 21 : Emitter-follower Minimizes Load at RT/CT Terminal.
8 VRH
",
~ 2N2222
RSlOPE.
iC '
4 Ryley
2or3
UC3842
12/15
498
UC3842
5-78]1
NOISE
As mentioned earlier, noise on the current sense or control signals can cause significant pulse-width jitter, particularly with continuous-inductor-current designs. While slope compensation helps alleviate this problem, a better solution is to minimize the amount of noise. In general, noise immunity improves as impedance decrease at critical points in a circuit.
One such point for a switching supply is the ground line. Small wiring inductances between various ground points on a PC board can support commonmode noise with sufficient amplitude to interfere with correct operation of the modulating IC. A copper ground plane and separate return lines for high-current paths greatly reduce common-mode noise.
APPLICATION NOTE
Note that the UC3842 has a single ground pin. High sink currents in the output therefore cannot be returned separately.
Ceramic bypass capacitors (0.1 flF) from VI and VREF to ground will provide low-impedance paths for high frequency transients at those points. The input to the error amplifier, however, is a high-impedance point which cannot be bypassed without affecting the dynamic response of the power supply. Therefore, care should be taken to layout the board in such a way that the feedback path is far removed from noise generating components such as the power transistor(s).
Figure 22a illustrates another common noise-induced problem. When the power transistor tu rns off, a noise spike is coupled to the oscillator RT/CT terminal. At high duty cycles the voltage at RT/CT is approaching its threshold level (- 2.7 V, established by
the internal oscillator circui\i when this spike occurs. A spike of sufficient amplitude will prematurely trip the oscillator as shown by the' dashed lines. In order to minimize the noise spike, choose CT as large as possible, remembering that deadtime increases with CT. It is recommended that CT never be less than - 1000 pF. Often the noise which causes this problem is caused by the output (pin 6) being pulled below ground at turn-off by external parasitics. This is particularly true when driving POWERMOS. A diode clamp from ground to pin 6 will prevent such output noise from feeding to the oscillator. If these measures fail to correct the problem, the oscillator frequency can always be stabilized with an external clock. Using the circuit of figure 8 results in an RT/CT waveform like that of figure 22b. Here the oscillator is much more immune to noise because the ramp voltage never closely approaches the internal threshold.
Figure 22 : (a) Noise on Pin 4 Can Cause Oscillator to Pre-trigger. (b) With External Sync. Noise Does not Approach threshold Level.
INTERNAL
--'--V-----A----=.-tl-
THRESHOLD
'"" ..
~
NOISE INDUCED OSCILLATOR PRE- FI RING
J \rF--'"""' ~
(a)
MAXIMUM OPERATING FREQUENCY
Since output deadtime varies directly with CT, the restraint on minimum CT (1000 pF) mentioned above results in a minimum deadtime varies for the UC3842. This minimum deadtime varies with RT and therefore with frequency, as shown in figure 23. Above 100 kHz, the deadtime significantly reduces the maximum duty cycle obtainable at the UC3842 output (also show in figure 23). Circuits not requiring large duty cycles, such as the forward converter and flyback topologies, could operate as high as 500 kHz. Operation at higher frequencies is not recom-
<; -7flll
(b)
mended because the deadtime become less predictable.
The speed 'of the UC3842 current sense section poses an additional constraint on maximum operating frequency. A maximum current sense delay of 400 ns represents 10 % of the switching period at 250 kHz and 20 % at 500 kHz. Magnetic components must not saturate as the current continues to rise during this delay period, and power semiconductors must be chosen to handle the resulting peak currents. In short, above - 250 kHz, may of the advantages of higher-frequency operation are lost.
13/15
499
APPLICATION NOTE
Figure 23 : Deadtime and Maximum Obtainable Duty-cycle vs. Frequency with Minimum Recommended
CT.
'd
(ns)
\---+--+--+-----t-----i(.,.)
100 \ - - - + - - -+--+--~---1
650 ~-+-----l r:::.c:'==---
100
200
300
400 1(KHz)
CIRCUIT EXAMPLES
1. OFF-LINE FLYBACK
Figure 24 shows a 25 W mUltiple-output off-line flyback regulator controlled with the UC3842. This regulator is low in cost because it uses only two magnetic elements, a primary-side voltage sensing technique, and an inexpensive control circuit. Specifications are listed below.
SPECIFICATIONS:
Une Isolation:
3750 V
Switching Frequency: 40 kHz
Efficiency @ full load : 70 %
Input Voltage
95 VACto 130 VAC (50Hz/60Hz)
Output Voltage:
A. + 5 V, 5 % : 1 A to 4 A load Ripple voltage: 50 mV P-P Max.
B. +12V,3%:0.1 AtoO.3A load Ripple voltage: 100 mV P-PMax
. C. -12V,3%0.1 AtoO.3A load Ripple voltage : 100mV P-PMax
14/15 500
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APPLICATION NOTE
A 25W OFF-LINE FLYBACK SWITCHING REGULATOR
INTRODUCTION
This note describes a low cost switching power supply for applications requiring multiple output voltages, e.g. personal computers, instruments, etc ... The discontinuous mode flyback regulator used in this application provides good voltage tracking between outputs, which allows the use of primary side voltage sensing. This sensing technique reduces costs by eliminating the need for an isolated.secondary feedback loop.
The low cost, (8 pin) UC1842 current mode control chip employed in this power supply provides performance advantages such as :
1) Fast transient response 2) Pulse by pulse current limiting 3) Stable operation
To simplify drive circuit requirements, a TO-220 power MOS SGSP369 is utilized for the power switch. This switch is driven directly from the output of the control chip. .
POWER SUPPLY SPECIFICATIONS
1. Input voltage: 95VAC to 130VAC (50 Hz/60 Hz)
2. Output voltage:
A. + 5 V, ± 5 % :1 A to 4 A load
Ripple voltage: 50 mV P-P Max B. + 12 V, ± 3 % : 0.1 A to 0.3 A load Ripple voltage: 100 mV P-P Max C. - 12 V, ± 3 % : 0.1 A to 0.3 A load Ripple voltage: 100 mV P-P Max
3. Line Isolation: 3750 V
4. Switching Frequency: 40 KHz
5. Efficiency @ Full Load: 70 %
BASIC CIRCUIT OPERATION
The 117VAC input line voltage is rectified and smoothed to provide DC operating voltage for the circuit. When power is initially applied to the circuit, capacitor C2 charges through R2. When the voltage
across C2 reaches a level of 16 V the output of IC1 is enabled, turning on power MOS 01.
During the on time of 01 , energy is stored in the air gap of transformer (inductor) T1. At this time the polarity of the output windings is such that all output rectifiers are reverse biased and no energy is transferred. Primary current is sensed by a resistor, R1 0, and compared to a fixed 1 V reference inside IC1. When this level is reached, 01 .is turned off and the polarity of all transformer windings reverses, forward biasing the output rectifiers. All the energy stored is now transferred to the output capacitors. Many cycles of this store/release action are needed to charge the outputs to their respective Voltages. Note that C2 must have enough energy stored initially to keep the control circuitry operating until C4 is charged to a level of approximately 13 V. The voltage across C4 is fed through a voltage divider to the error amplifier (pin 2) and compared to an internal 2.5 V reference.
Energy stored in the leakage inductance of T1 . causes a voltage spike which be added to the nor-
mal reset voltage across T1 when 01 turns off. The clamp consisting of 04, C9 and R12 limits this voltage excursion from exceeding the BVDSS rating of 01. In addition, a turn-off snubber made up of 05, C8 and R11 keeps power dissipation in 01 low by delaying the voltage rise until drain current has decreased from its peak value. This snubber also damps out any ringing which may occur dueto parasitics.
Less than 3.5 % line and load regulation is achieved by loading the output of the control winding Nc, with R9. This resistor dissipates the leakage energy associated with this winding. Note that R9 must be isolated from R2 with diode 02, otherwise C2 could not charge to the 16 V necessary for initial start-up.
A small filter inductor in the 5 V secondary is added to reduce output ripple voltage to less than 50 mV. This inductor also attenuates any high frequency noise.-
AN247/1188
1/5
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Figure 2 : Block Diagram: UC1842 Current Mode Controller.
APPLICATION NOTE
Vi GROUND
2 SOV
- - - - - I-.,...---+---~--~- ~~
VREf ,>v 50mA
2R
R
COMP 0---------'
0 3 - - - - - - - - - - - - - -
CURRENT SENSE
TYPICAL SWITCHING WAVEFORMS
6
--D
OUTPU T
Upper trace: 01 - Gate to source voltage Lower trace: 01 - Gate Current
3/5 505
APPLICATION NOTE TYPICAL SWITCHING WAVEFORMS
Upper trace: 01 - Drai'n.tq source voltage Lower trace: Primary current- ID
PERFORMANCE DATA
Conditions
Low Line (95 VAG) ± 12@ 10.0. rnA
± 12@30.0. rnA
+ 5 V@ 1.0. A 4.0. A
+ 5 V@ 1.0. A 4.0. A
Nominal Line (120. VAG) ± 12@ 10.0. rnA
+ 5 V@ 1.O..A 4.Q A
± ,12@30.0. rnA
High Line (130. VAG) ± 12@ 10.0. rnA
+5V@1.O.A 4.0. A
+ 5 V@ 1.0. A 4.0. A
± 12 V@30.0. rnA
+ 5 V@ 1.0. A 4.0. A
Overall Line and Load Regulation
, .
;.
Upper, tr!lce:~5V charging current
+ Lower trace.: 5V output ripple voltage
5 V out
5.21.1 4.854
5.199 4.950.
5.220. 4.875
'5.20.8 4.90.6
5.20.7 4.855
5.20.0. 4.90.2 ± 3:5 %
12 V out - 12 V out
12.0.5 12.19
11.73 11.68
-12.0.1 -12.14
-11.69 -11.63
12.0.7 12.23
11.73 11.67
-12.0.3 -12.18
-11.68 - i1.62
12.0.6' 12.21
11.71 11.66 ± 2.3·.%
-12.0.2 -12.15
- 11.67 11.61
f:2.4°ic,
4/5
506
APPENDIX POWER TRANSFORMER - T1
Core: Ferroxcube EC-35/3C8 Gap: 0.25mm. in each outer leg
Note: For reduced EMI put gap in center leg only. UseO.5mm.
TRANSFORMER CONSTRUCTION
CONTROL WINDING N:10.AWG JO(O.25mm) 2 IN PARALLEL
~ 2 LAYERS 3M MYLAR TAPE
BOBBIN-lSPCBl
APPLICATION NOTE
5 - 1931
2 LAYERS. 3M MYLAR TAPE ",,2v WINDINGS N:9. AWG30(O.25mm) 2WIRES IN PARALLEL. BIFILAR WOUND ~RIMARY ":£5. AWG 26Co.£mm)
5/5 507
APPLICATION NOTE
FLEXIBLE LOW COST HIGH EFFICIENCY 130W SMPS USING SGSD00055 AND TEA2018A
ABSTRACT
A low cost, high efficiency, flexible and reliable 130W flyback power supply has been designed using the new Fastswitch high voltage Darlington SGSD00055 and the TEA2018A PWM controller.
The advantages of the new Darlington are low cost together with low switching and driving losses, a large safe operating area and simple drive requirements.
The TEA2018A provides the SMPS with comprehensive protection whilst using very few components.
The low cost of this design makes it a viable option for use in personal computers, telecommunication equipment, battery chargers and TVs.
The example evaluated in this paper is intended for CTVapplications.
By R. LETOR · S. FLERES
at turn-off, a voltage that standard Darlingtons are unlikely to be able to handle.
An added advantage of this high voltage capability is that smaller snubber networks can be used giving reduced dissipation in these networks.
The switch mode power supply characteristics are summarised in the following table:
Operating mode: A.C. input voltage: Maximum frequency: Maximum output power: Outputs:
Line regulation: Load regulation: 110W efficiency:
non continuous flyback
110/220V ± 15%
25kHz
130W
+ 200V
50mA
+ 150V
500mA
+ 25V
1.5mA
+16V
500mA
.016%/V
.035%/W
82%
INTRODUCTION
The SGSD00055 is a new 1000V Darlington designed in high voltage planar technology.
The main features of this device are fast switching capability, large reverse safe operating area and very low cost.
This high efficiency 130W flyback SMPS capitalises on the features of this transistor to produce a highly reliable power supply.
By adding to this' the facilities offered by the TEA2018A, significant component reduction can be made whilst retaining all the desirable features.
The high voltage that the Darlington can withstand plus the large safe operating area allows the use of a low cost transformer with high leakage inductance.
The leakage inductance of a low cost transformer is likely to produce voltage spikes in excess of 850V
CIRCUIT DESCRIPTION
Figure 1 shows the complete circuit and component list.
The rectified mains voltage applied to the primary of the flyback transformer is switched at 20KHz by the Darlington 01 with a duty cycle of about 30%.
During the on-state the base current value depends upon the collector current, the TEA2018A performing the proportional base drive.
The negative voltage necessary for the turn-off is provided by the 06, R8, R9, C9 network, which charges the C6 capacitor during the on-state.
At turn-off, the inductor L1 limits the reverse base current and prevents the turn-off from being too fast hence reducing any "tail turn-off" problem.
The snubber network R12, C10, 08 ensures safe switch off inside the safe operating area and very low switching losses at turn-off.
AN36210689
1/5
509
APPLICATION NOTE
Figure 1 : 130W SMPS Using SGSD00055.
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COMPONENT LIST
R1 R2trimmer R3 R4 R5 R6 R7 RS R9 R10 R11 R12 R13 R14 R15 R16
1K 22K 1K 56K 100K 220K 10K 10 470 2.7 0.33 2.2K 1 0.75 4 100K
L1
4.71lH
C1 -C4 C5 C6 C7
1QF 6S0pF 4.71lF 100ilF
1/4W
1/4W 1/4W 1W 2W 1/4W 1W 2W 1/2W 2W 7W 2W 4W 4W 1/2W
1kV 1kV 6.3V 16V
CS C9 C10 C11 -C12 C13-C14 C15 C16
OZ1 OZ2 01 - 04 05 06 07 OS 09 - 010 011.- 012 Q1 IC1 T1 F1 F2
100J,lF 4.71l F 1.SnF 220llF 220llF 10llF 10llF
25V 6.3V 1kV 250V 63V EKA 250V 300V
10V 4.7V 2A250V 1 N4001 BA157 1N4148 BYT13-800 BYW9S BY299 SGSOOO055 TEA201SA SAREA 29.6024 0.5 A FUSE 0.5 A FUSE
1W 1/2W Rectifier Bridge
2/5 510
APPLICATION NOTE
Figure 2 shows the power losses in the Darlington and in R12 as C10 is varied.
The minimum power losses occur when C10 has a value of 1.0nF.
In fact a value of 1.8nF was used in order to give a sufficient safety margin at turn-off.
In this way a 1W reduction of the power losses in the Darlington was obtained (see figure 3).
This in turn reduced the working temperature with a consequent improvement in reliability. To obtain the same safety marg in with a 850V Darlington a 2.2nF capacitor would have to be used for C1 O.
Figure 2 : Power Losses vs CSnubber.
This would result in higher losses. Using the 1000V Darlington permits the use of a cheaper "Iossy" transformer as the Darlington itself will withstand the higher voltage peaks caused by a leakage inductance 4 times greater than the peak that a 850V Darlington can withstand.
The TEA2018A demagnetisation circuit allows the following features to be designed into the circuit:
_ non-continuous flyback mode for all load conditions
_ soft start _ short circuit protection
Figure 3 : Load Line Shape at Turn-off.
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7 6 5 4
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2
2 ClnFI
Figure 4 shows the short circuit conditions both with and without the demagnetisation control. During normal operation the maximum current is limited by the current mode control.
When a short circuit occurs without the demagnetisation circuit, the collector current increases until the transformer core is saturated.
This happens because collector current continues increasing even after the current limiter intervenes due to the storage current, at a rate O.25A!~S.
Hence the energy stored in the transformer core during tstorage eaches a value of about 50~J, while during the discharge cycle the energy reduces to about 3~J.
200
100
600
BOO
1000
In this application the demagnetisation circuit inhibits the base drive until all the stored energy in the core of the transformer has been discharged through the diode, the secondary winding and the short circuit resistances.
The demagnetisation current behaves in the same way during start-up avoiding extra currents.
It also ensures non-coniinuous mode operation under every load condition.
The following figures and photographs illustrate the performance of this power supply.
3/5 511
APPLICATION NOTE
Figure 4 : Short Circuit Operation.
DRIVING PULSES
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D
50 liS
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without demagnetisation circuit with demagnetisation circuit
Figure 5a : Efficiency versus Output Power.
HEATSINKTEl\fP F\h=S CIW
Figure 5b : Heatsink Temperature versus Output Power for Rth (heatsink) a"CIW.
1m we SfofPS
70
80
to
'00
110
1tO
4/5 512
'0
go
100
110
'20 ""
Photograph 1 : Collector Voltage and Current Waveforms.
APPLICATION NOTE
Photograph 2 : Turn-off Waveforms.
Ie = 1Afdiv VeE = 100Vfdiv Vee = 250V
Photograph 3 : Collector and Base Current at Tum-off.
Ic = O.5Afdiv VeE = 100Vfdiv Photograph 4 : Transient Response to a step Load
Ie = 1Afdiv IB = O.2A/div Photograph 5 : Output Ripple on the 25V Output.
V = 2Vfdiv
CONCLUSIONS
The new 1000V Darlington allows the construction of a flexible, reliable and low cost switching power supply. It has a high efficiency even at low loads due to the very low driving energy required, the low switching losses and the reduced snubber losses.
V= 200mVfdiv I = 1.5A
5/5 513
APPLICATION NOTE
A SECOND-GENERATION IC SWITCH MODE CONTROLLER OPTIMIZED FOR HIGH FREQUENCY POWER MOS DRIVE
INTRODUCTION
Since the introduction of the SG1524 in 1976, integrated circuit controllers have played an important role in the rapid development and exploitation of high-efficiency switching power supply technology. The 1524 soon became an industry standard and was widely second-sourced.
Although this device contained all the basic control elements required for switching regulator design, practical power supplies still required other functions which had to be implemented with additional external discrete circuitry. An additional development within the semiconductor industry was the introduction of practical Power
Mos which offered the potential of higher efficiencies at higher ,speeds with resultant lower overall system costs.
In order to be able to take full advantage of the speed capabilities of power MOS, it was necessary to provide high peak currents to the gate during turnon and turn-off to quickly charge and discharge the gate capacitances of 800 to 2000 pF present in higher current units.
a The development of second-generation regulating
. PWM IC, the SG1525A, and its complimentary output version, the SG1527A, was a direct result of the desire to add more power supply elements to the controllC,
Figure 1 : The SG1524 relating PWM block diagram. This design was the first complete I.C. control chip for switch mode power supplies.
jVi
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AN250/1188
1/12
515
APPLICATION NOTE
as well as to optimize the interfacing of high current power devices.
INTEGRATING MORE POWER SUPPLY FUNCTIONS
Having achieved the greatest level of acceptance among users of first generation control chips, the 1524 became the starting point for expanding IC controller capabilities. This early device, shown in figure 1, contains a fixed-voltage reference source, an oscillator which generates both a clock signal and a linear ramp waveform, a PWM comparator, and a toggle flip-flop with output gating to switch the PWM signal alternately between the two outputs.
With this circuitry already defined, a two pronged development effort was initiated : 1) to add additional features required by most power supply designs and 2) to improve the utility of features already included within the 1524. The resultant block diagram for the SG1525A is shown in figure 2. Two general comments should be made relative to the overall block
diagram. First, in optimizing the output stage for bidirectional, low impedance switching, commitments had to be made as to whether the output should be high or low during the active, or ON state. Since this is application defined there are needs for both output states, so both were developed with the SG1525A device defined by an output configuration which is high during the ON pulse, and the SG1527A configured to remain high during the OFF state. This difference is implemented by a mask option which eliminates inverterQ4 (see figure 3) forthe SG1527A. In all other respects, the 1525A and 1527A are identical and any description of the 1525A characteristics apply equally to the 1527A. Second, a major difference between this new controller and the earlier 1524 is the deletion of the current limit amplifier. There are so many system considerations in providing current control that it is preferable to leave this as a user-defined extemal option and allocate the package pins to other, more universally requested functions. Current limiting possibilities are discussed further under shutdown options.
Figure 2 : The SG1525A family represents a "second generation" of IC controllers.
V, 150---
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RT
, 0---- ... - - - - - I
r-~----------------------------
Vc
-013
,--I
I I
DlS7CH_AR_Gf_ _-
(O~P
, o---------~
IN:'~:".'_~
N j. INf-'UT 2 (r---
RHOR AMP.
C,G1525A OUTPUT STAGE
Vc
OUTPUT A
t--+----u' 11
5KJl
2/12 516
OUTPUT B ~---O".
SGIS17A OUTPUT STAGE
L
_ ~ _ _ _ _ ~ - - - ---
- - _.- -
APPLICATION NOTE
"TOTEM-POLE" OUTPUT STAGE
One of the most significant benefits in using the SG1525A is its output configuration. For the first time it has been recognized in an IC controller that it is more difficult to tum a power switch off than turn it on. With the SG1525A, a high-current, fast transition, low impedance drive is provided for both turnon and turn-off of an external power transistor or Power MOS. The circuit schematic of one of the two output stages contained within the device is shown in figure 3. This is a two-state output, either Os is on, forming a low saturation voltage pull-down, or 07 is on, pulling the output up to Vc. Note that Vc is a separate terminal from the Vi supply to the rest of the device.
This offers the benefits of potentially operating the output drive from a lower supply than the rest of the circuit for power efficiencies, decoupling of drive transients from more sensitive circuits, and a third terminal for extracting a drive signal. Note that even though Vc can be set either higher or lower than Vi, the output cannot rise higher than approximately 1 1/2 volts below Vi.
Figure 3: One of Two Power Output Stages Contained within the SG1525A which Conduct Altemately due to the Internal Flip-flop.
Vc is shown in figure 4. This transient will normally be decoupled from the rest of the control power by a 0.1 j.lF capacitor from Vc to ground but it shou Id not, otherwise, cause a problem unless very high frequency operation is contemplated where it will contribute to overall device power dissipation, by becoming a significant portion of the total duty cycle.
The output saturation characteristics of this stage are shown in figure 5. The source transistor, 07 is a straight forward Darlington and its saturation voltage remains between 1 and 2 V out to 400 mA under the assumption that Vi ~ Vcc. The sink transistor, Os, however, has a non-uniform characteristic which needs explanation. At low sink currents, the
1 mA current source through 05 insures a very low
saturation voltage at the output. As load current in-
creases past 50 mA, 08 begins to come out of satu-
ration for lack of base drive but only up to about 2 V. Here diode 02 becomes forward biased shunting a
portion of the load current through 05 to boost the base current into 08. With this circuit, the sink tran-
sistorcan both support high peak discharge currents from a capacitive load, as well as insure the low static hold-off voltage required for bipolar transistors.
Figure 4: Current "spiking" on the Vc terminal caused by conduction overlap between source and sink is minimized by highspeed design techniques.
Q7
~_~+--{) OUTPUT A orB
PWM DSC
F/ F
During the transition between states, there is a slight conduction overlap between source and sink which results in a pulse of current flowing from Vc to ground. However, due to the high-speed design configuration of this stage, this current spike lasts for only about 1Dans. A typical current waveform at
HORIZONTAL = 500nsIDIV
A typical output configuration for a push-pull bipolar transistor power stage is shown in fig. 6. With a steady state base drive current from the SG1525A of 100 mA, this stage should be able to switch 1 to 5 A of transformer primary current, depending upon the choice of transistors. The sum of R1 and R2
3/12
517
APPLICATION NOTE
Figure 5 : The output saturation characteristics of the SG1525A provide both high drive current an low hold-off voltage.
Ve E (V )
-
II
Vi ",20V lamb'" 15-C
G-$ll.ltI
Figure 7 : Base current waveforms (figure 6 circuit) show the enhanced turn-on and turn-off current possible with the SG1525A.
- I--~
0.01
-~ V
- SOURCE SAT.Ve-VOH
IIII
5rNt< SAT, VOL
Illi
01
10 (A)
determine the maximum steady state output current of the SG 1525Awhile their ratio defines the voltage across C2which, at turn off, becomes the reverse VBE for Q1. With the values given, the output current and voltage waveforms are shown in figure 7 for a one microsecond pulse. If power MOS are used for the output switches as shown in figure 8, the interfacing circuitry can become even simpler with only a small series gate resistor potentially required to damp spurious oscillations within the power device.
Figure 6 : A Typical Push-pull Converter Power Stage Using External Bipolar Power Transistor Switches
R1 fJOn
n 5G1525A
HORIZONTAL = SOOns/DIV
Push-pull direct transformer drive is also particularly advantageous with SG1525A as shown in figure 9. A version of this configuration is required for isolation when the control circuit is referenced to the secondary side of an off-line power system, and to provide level shifting of drive signals for bridge and full bridge switching. The configuration of figure 9 has a couple of important advantages. First, by connecting the drive transformer primary direct-. Iy between the outputs of the SG1525A, no centertap is needed and the full primary is driven with opposite polarities. Secondly, between each output pulse, both outputs are pulled to ground which effectively shorts the two ends of the primary winding together coupling a low-impedance turn-off signal to the switching transistors.
A useful single-ended configuration, typical of buck regulators, is shown in figure 10. Here the SG1525A outputs are grounded and the PWM signal is taken. from the Vc terminal which switches close to ground during each clock period as the internal source transistors are alternately sequenced.
GNO 12
4/12 518
APPLICATION NOTE
Figure 8 : Replacing bipolar transistors with power MOS provides even greater simplicity due to the low driving impedances of the SG1525A in each transition.
.vs
o~----~-------------.
Rl
Figure 10 : A single-ended Ground-referenced Power Stage for a Flyback or Boost Regulator.
TO OUTPUT FILTER
T,
SG 157~A
11 A
5G1525A
B 14
GNO
12
s - 6 JJ.B Figure 9 : The SG 1525A is ideally suited for driving
a low-power base drive transformer and eliminates the need fora primary centerc tap.
.v, o-----..---------------~----___,
13 CI
T2 5GIS2SA
GNO
5-6.1.1711
CONTROLLING POWER SUPPLY START-UP
Although the advantages of the SG1525A's output stage will often be reason enough for its selection, there are several other important and useful features incorporated within this product. One problem pre~iously overlooked in PWM circuits is keeping the output under control as the supply voltage is turned on and off. Undefined states, particularly the possibility of turning on an output before the oscillator is running, can be quite awkward, if not catastrophic. To prevent this, the SG1525A has incorporated an under-voltage lockout circuit which effectively clamps the outputs to the off state with as little as 2 112 V of supply voltage which is less than the vol-tage required to turn the outputs on. This clamp is maintained until the supply reaches approximately 8 V insuring that all the remaining SG1525A circuitry is fully operational prior to enabling the outputs. The clamp reactivates when the supply is lowered to approximately 7.5 V. There is about 500 mV of hysteresis built in to eliminate clamp oscillation at threshold.
5/12 519
APPLICATION NOTE
Another important aspect of power sequencing is restraining the outputs from immediately commanding a 100 % duty cycle when they are activated. This is accomplished by a slow turn on (soft-start) which is defined by an internal 50 JlA current source in conjunction with an externally applied capacitor. The details of this power sequencing system are shown in figure 11. 03 and 04 are the output gates normally driven by the oscillator through 02 to provide output blanking between pulses. (One of these transistors is shown as 02 in figure 3). At low supply voltages, 02 conducts with base drive from the 20 JlAcurrent source. 02 provides three functions. First, current through R4 acti-
vates the output gates with minimum voltage drop~ Second, current through Rs activates the shutdown transistor 05 holding the soft-start capacitor, Css, discharged. Third, R2 provides a small bucking voltage across R3 for hysteresis at the switch point.
When the input voltage becomes high enough to provide a little more than one volt at the base of 01, that transistor turns on. This tums off 02, activating the outputs and allowing Css to begin to charge from the internal 50 JlA current source. The time to reach approximately 50 % duty cycle will be
t = (2 volts ) C
50 JlA
ss
Figure 11 : The Internal Power Turn-on, Soft-start, and Shutdown Circuitry of the SG1525A.
Vi
CLOCK
VREF
BL"NKING
02 R4
R5
D2 DI
~ 03
OUTPUT GATE5
R2
R8
R3"
10
R6
5HUTOOWN
as
Q6
TO PWM COMPARATOR
.LI (55
TO PWM LATCH
s _6~"'1t
POWER SUPPLY SHUTDOWN
An important part of any PWM controller is t~e ability to shut it down at any time for a variety of reasons, including system sequencing requirements or fault protection. Several options are available to the user of the SG1525A, which require an understanding of the capability of the shutdown terminal, pin 10. Referring to figure 11, the base of 05 is turned on by a signal which is clamped to approximately 1.4 V by the action of D1 and the VSE of gates 03 and 04.
6112
520
This holds the outputs off and keeps Css discharged by 05 which, with Rg, becomes a 100 JlA net current sink.
If, during normal operation, pin 10 is pulled high, three things happen. First, the outputs are turned off within 200 ns through 01. Second, the PWM latch is set by 06 so that eve n if th e sig nal at pi n 10 were to disappear, the outputs would stay off for the duration of that period, being reset by the next clock pulse. Third, 05 is activated commencing a 100 JlA
APPLICATION NOTE
discharge of Css. However, if the activation pulse on pin 10 has a duration shorter than 1/3 of the clock period, the voltage on Css will remain high and softstart will not be reactivated. Naturally, a fixed signal on pin 10 will eventually discharge Css, recycling soft -start.
Thus, the shutdown pin provides both sequencing capability as well as a convenient port for protective functions, including pulse-by-pulse current limiting.
REGULATING PWM PERFORMANCE IMPROVEMENTS
The SG 1525A also offers significant performance and application improvements in almost all of the additional basic functions of a PWM over those obtainable with earlier devices. A general description of these features is outlined below:
REFERENCE REGULATOR The output voltage of this regulator is intemally
trimmed to 5.1 V ± 1 % during manufacture, eliminat-
ing the need for adjusting potentiometers in most applications.
ERROR AMPLIFIER SG1525A uses the same basic transconductance amplifier as the SG1524 with an important difference : it is powered by Vi rather than VREF. Now the input common-mode range includes VREF eliminating the need for a voltage divider with its attendant tolerances. An additional feature relative to the error amplifier is that the shutdown circuitry feeds into a separate input to the PWM comparator allowing pulse termination without affecting the output of the error amplifier which might have a slow recovery, depending upon the external compensation network selected. An important benefit of a transconductance amplifier is the ease with which its current mode output can be over-ridden by other external controlling signals.
PWM COMPARATOR The significant benefit of the SG1525A's PWM comparator is in its following latch. A common problem with earlier devices was that any noise or ringing on the output of the error amplifier would affect multiple crossings of the oscillator ramp signal resulting in multiple pulsing at the comparator's output. The SG1525A's latch terminates the output pulse with the first signal from the comparator, insuring that there can be only a single pulse per period, removing all jitter or threshold oscillation from the system. Another important advantage of this latch is the ability to easily implement digital or pulse-by-pulse
current limiting by merely momenetarily activating the shutdown circuitry within the SG1525A. This could be as simple as connecting pin 10 to a groundreferenced current sensing resistor. For greater accuracy, some added gain may be advantageous. Once a current signal causes shutdown, the output will remain terminated for ihe duration of the period, even though the current signal is now gone. An oscillator clock signal resets the latch to start each period anew.
OSCILLATOR
The functions of the oscillator within the SG1525A have been broadened in two important aspects. One is the addition of a synchronization terminal, pin 3, allowing much easier interfacing to an external clock signal or to synchronize multiple SG1525A's together. The other is the separation of the oscillator's discharge network from its charging current source for deadtime control. Reference should be made to the schematic of figure 12 for an understanding of the operation of this circuit. The heart of this oscillator is a double-threshold comparator, Q7 and Qs, which allows the timing capacitor to charge to an upper threshold by means of the current source defined by RT and mirrored by Q1 and Q2. The comparator then switches to a lower threshold by turning on QlO and discharges CT through Q3 and Q4 with a rate defined by RD. As long as CT is discharging, the clock output is high, blanking the outputs.
Since the overall oscillator frequency is defined by the sum of the charge and discharge times, there are three elements now in the frequency equation which is approximately:
f= CT (.07 RT + 3 Ro)
External synchronization can easily be accomplished with a 2.8 V positive pulse at pin 3. This will turn on Qg, lowering the comparator threshold below wherever the voltage on CT may happen to be. Two factors should be considered: First, the voltage on CT determines the amplitude of the PWM ramp, and if the sync occurs too early, the loop gain will be higher and the resolution may be worse. Second, the sync circuit is regenerative within 200 ns ; and, while a wider pulse can be used, CT will not begin to recharge as long as the sync pin is high. For synchronizing multiple SG1525A devices together, one need only to define a master with the correct RTCr time constant, connect its output pin to the slave sync pins, and set each slave RrCT for a time constant 10-20 % longer than the master.
7/12 521
APPLICATION NOTE Figure 12 : A Simplified Schematic of the SG1525A's Oscillator Circuitry,
~EF~_ _ _ _ _ _ _ _~_ _ _ _ _ _ _ _~_ _ _ _~~_ _ _ _ _ _~~_ _ _ _ _ _ _ _ _ __ 7.4Kn
S RA~P
a7
a8
14KD
------4-------~------------+--------+---4----~~~:M
Q9 alo
~-----_{2=K=n~_+--~~
2SKfl
013
DISCHARGE
25KQ
Cy
OJ
IKQ
Figure 13: 200 W, Off-line Forward Converter.
CLOCK ~T
"'-ll'
1000
"
" f---------------i
un
'"'
so
lS2SA
].91(0
r- ,-'-----'
0-1.u F
Nln
2On'
8/12 522
APPLICATION NOTE
A 200 WATT, OFF-LINE, FORWARD CONVERTER
The ease of interfacing the SG 1525A into a practical power supply system can be illustrated by the off-line, power converter shown in figure 13. This 200 W supply places the control circuitry on the primary side of the power transformer where direct coupling can be used to drive the power switch. While simplifying the drive electronics, this configuration usually requires an isolated voltage feedback signal which is most easily accomplished by an optocoupler driven by some type of voltage regulator IC such as a L123 or LM723. One other undefined block in figure 13 is the auxiliary power supply which supplies the low voltage, low current bias supply for
the SG 1525A and the drive for 01 the power switch.
The choice of the SGSP479 power MaS for this switch keeps the total power requirements from the auxiliary supply at less than 1 W ; readily implemented with a small, line-driven transformer. This converter is designed to operate at 150 kHz which is accomplished by running the SG1525A at 300 kHz and using only one of the outputs. This also automatically insures that the duty cycle can never be greater than 50 %, a requirement of the power transformer in this configuration. The high operating frequency allows the output filter's roll-off to be set at 12 kHz, greatly simplifying the overall loop stability considerations as adequate response can be achieved with only the single-pole compensation of the error amplifier provided by the 0.05 IlF capacitor on pin 9. The totem-pole output of the SG 1525A is used to ad-
vantage to drive 01 by providing a 400 mA peak cur-
rent to charge and discharge the power MaS gate capacitance while keeping overall power dissipation low. Waveform photographs of this operation are shown in figure 14.
Figure 14 : Current and Voltage Waveforms for the 200 W Off-line Forward Converter with a SG1525A Direct Driven Power MaS Switch (operating frequency is 150 KHz with output current equal to 40 A).
00-
01 Ils/div
a) Waveforms of 10. IG. VG
b) Risetime ~ 90 ns
0-
0-
0"":' c) Falltime ~ 30 ns
9/12 523
APPLICATION NOTE
When operating at full load, the efficiency of this converter is 73 % with by far the greatest power losses occurring in the output rectifiers-even though Schottky devices have been selected.
Switching losses have been minimized by the fast current transitions, primarily defined by the leakage inductance of the transformer. Although this switching time could probably be even further reduced, there could be problems with current spikes during
Figure 15: 500 W, 100 kHz Half-bridge Schematic.
rise time due to Schottky rectifier capacitance.
Current limiting for this converter is provided by· measuring the current in SGSP479 with the 0.1 Q resistor in series with the source and using this voltage to activate the shutdown circuitry within the SG1525A. While this will provide a fast-acting short circuit protection on a pulse-by-pulse basis, a comparator may need to be added for a more accurate current limit threshold.
-,-, ~
Yl now..c
,
......,,,
I
115""'",(
1
::==JJII" l~
--
'-----
-.w.
-.w.
1
~ - Il ~~--~-' ~'"
Il : .. .. .'" -- ---'J
~ ':-U ,G".
1.J1:a IIJDnt'
" I
: 'pO
_ ...,.., 1
t
::'F ji~
, :'.i:"
POL'PRQP
\
'1041.11
-
Ull ",ZOnf"
f I ...","
. -
r-<
: 1;;:'"
'F .'"
u
-Iii
...
... '"
..... Jj.-
( p
.~ =. ,.J I
... . 1 ~:
... ,
~
u.
... .....
::
-1
. _-
" 50
l!5zsa d"-'
.~.,..-
~,
"
... 1-1-
-_ ...
f; .- .f-of--
~
......
...'"
....
~G .... ....1~
f--
'10;-"'"
10/12 524
APPLICATION NOTE
Transformer winding data
500 W, 100 kHz, Off-Line, Half-Bridge Converter:
T1
Core: Ferrox 4S6T250-3CS
Pri : 14 T #22AWG
Sec (2) : 7 T#22AWG
T2 Core: Ferrox EC52-3CS (EE) Pri : 14 T, 2 layers, 2 #16AWG in parallel Sec (2) : each 2 T, C.T., copper strap 0.01" x O.S"
T3 Core: Ferrox 4S6T250-3CS Pri: 1 T Sec: 20 T, C.T. #22AWG
T4
117 V/220 V, 25 V, 0.15 A, 50-60 Hz
L1 Core: Ferrox IF30-3CS 4 turns, 5 #12AWG in parallel
500 WATT, OFF-LINE, HALF-BRIDGE CONVERTER
The circuit shown in figure 15 uses a pair of SGSP479 power MOS in a half-bridge configuration with the SG1525A chip referenced to the secondary side of the power transformer.
The power MOS gates are driven directly from the control chip output through step down and isolation transformer T1. The SG1525A output terminals (pins 11 and 14) provide active pull-up and pulldown (dual source/sink for the primary of T1. This provides the fast, high current turn-on and turn-off pulses needed for the power MOS gates. In addition, the two ends of the primary windings are shorted to ground during deadtime, which prevents accidental turn-on by transients. Note that the current supplied by the SG1525A outputs drops to a small value when the gate capacitance has been charged or discharged to the desired gate voltage. Damping resistors with series blocking capacitors across the two secondaries of T1 minimize ringing due to the power MOS gate capacitance and the inductance of T1 and lead inductance, particularly during deadtime.
Deadtime for the SG1525A is set very simply by a single resistor between pins 5 and 7. Only a small amount of deadtime is needed since the power MOS have no storage time and a very short delay time.
Slow turn-on is accomplished by a single capacitor at pin S.
Current limiting is provided by current transformer T3 in series with the primary of the power transformer T2. The Signal is rectified, threshold adjusted and sent to the shutdown terminal, pin 10, of the SG1525A.
Waveforms of the converter are shown in the scope 'photos of figure 16. Current rise and fall times are 20 ns and 10 ns. Figure 16 : Performance Waveforms for the Half-
bridge, 500 W, 100 kHz Converter with Output Current of SO A.
oAoA,v-
2 !'s/div a) Waveforms of ID. IG, VG
100 ns/div b) Risetime
00-
0100 ns/div c) Faittime
11/12 525
APPLICATION NOTE
IMPROVED PERFORMANCE; LESS COMPLEXITY
Although power supply designers for some time now
have had an ever widening inventory of Ie compo-
nents available to ease their design tasks, the final measure of improvement has to be in terms of system performance versus cost. With fewer interface components to the power stages, freedom from potentiometer adjustments, protected start-up and shut-down, a built in soft-start network and several additional system-level features, the SG1525A pro-
vides a significant contribution to both performance and costs while simultaneously making the designer's task easier. With these accomplishments, it is clear that this device truly does represent a stepfunction improvement, introducing a second-generation of power control components.
© 1984 by Unitrode Corporation. All rights reserved. This bulletin, or any part or parts thereof, must not be reproduced in any form without permission of the copyright owner.
12/12
526
APPLICATION NOTE
200kHz 15W PUSH PULL DC-DC CONVERTER
INTRODUCTION
The 15 W DC-DC converter, shown in fig. 1 has a push-pull topology and works in continuous mode with two outputs (+ 6 V, - 6 V) and features primary side control with full protection against fault conditions. There is no insulation between the primary
BY M. SUTERA
and secondary side.
Due to the high working frequency, the power switches used are the new SGS-THOMSON advanced POWER MOS type: IRFZ20 with high density and bonding on the active area.
+llV
R'
0--.
:r e·
R.O
r"R4""'ru,
I
9 "
"G
".
G -R7
"Z
GND
D.
-+6 OUT
I
~ ~-9~8,
GUO ...()
-6 CUT
\N35210689
1/6
527
APPLICATION NOTE
The PWM controller is the linear integrated circuit SGS3S2SA, with dual source/sink output drivers, internal soft-start, pulse by pulse shut-down and ad-
justable dead-time control. Table 1 shows the power supply specifications.
Table 1.
Operating mode
Push Pull
DC Input Voltage
10V DC to 18V DC
Switching Frequency
200kHz ± 10%
Total Power Output
15W
Outputs
+ 6V ± 5% 0.1 to 1.3A
- 6V ± 5 % O. 1 to 1.3A
Line Regulation (+ 6V output)
0.05%/V
Load Regulation (+ 6V output)
O.2%/A
Efficiency (@ 1/2 load)
:
76%
Output Ripple @ Max Load + 6V. - 6V Outputs 50mV Peak to Peak
Figure 1.
+lZV
- r r n.
RIO--
:fe.
01
l TRI
~
~ ~ ___
F"'·w',....-l_l.., 8-1 ....J.15---.J13-.....J.,O-----.1I
I
SGS 3525A
9 12
R.
G AI eL
=R7 ---
R2
tT . TR2
GNO
CIRCUIT DESCRIPTION
The OC input is chopped at a high frequency
(200kHz). This high switching frequency allows the
use of a very small transformer.
Oue to the push-pull configuration of the converter
the POWER MOS devices, the transformer and the
diodes work at the frequency of 100kHz
(photo 1, 2) ; the output filters and the oscillator of
PWM controller work at a frequency of 200kHz
(photo 3).
When Tr2 is on and Tr3 is off, diodes 02, 03 con-
duct and diodes 01, 04 are off. When Tr3 is on and
Tr2 is off diodes 01 , 04 conduct and diodes 02 03
are oft
'
The snubber formed by CS, R17 is used to clamp the voltage spikes on Tr2 and Tr3 drains. With a leakage inductance Ld = O.S).1H, a primary current Ip= 2.8 AatVINMIN and maximum load and an allowable voltage spike Vp = 30V we can calculate CS as follows:
CS =
= 1.8 nF
Eq.1
The PWM controller SGS3S2A has the two drive outputs in totem-pole configuration in order to drive the POWER MOS. The feedback signal for the PWM is directly connected to the inverted input of
2/6 528
APPLICATION NOTE
the error amplifier from the + 6 V output by the resistive divider R4-R1. The maximum current protection is sensed by Tr1, R9, RS and is connected to pin 10 (shut-down). The magnetic coupling of the series inductance in the output filter is very important for good regulation of the voltages. In this way when the load is very different in the two outputs (+ 6V max load; - 6V min load or viceversa) the indirectly regulated output (- 6V) has a very stable output voltage (see fig. 2).
Figure 2.
The efficiency is excellent: 70 % over a wide range (fig. 3).
The transient response is very fast : about 50ms. Photo 4 shows the transient response of load regulation due to a load variation from 1OOmA to 1.3A and from 1.3A to 100mA (+ 6Voutput).
Fig. 4 shows the P.C. board (track layout) and the component positions.
Vo(-6) · o
Figure 3.
EFFICIEIJCY 1%1
___ ---11~~-~-~
./-"'---
101+61
p IWI
3/6 529
APPLICATION NOTE
Figure 4 : P.C. Board and Components Layout (1: 1 scale).
TRANSFORMER
For this design a Tomita E core of 2E 6 ferrite material was chosen. To calculate the core size we used the following equations:
105 . POUT Ae' An >
1.16·L'1B·f·d
= O.143cm4 Eq.2
where: POUT = output 1,5 (W) L'1B = flux density swing (T) we chose
L'1B = 200mT d = current density we chose = 450A/cm2
= working frequency of transformer Ae = effective area of magnetic path [cm2] An = useful winding cross section [cm2]
The core size is then EE 25 x 6.5 with Ae = 0.42cm2, An = 0.45cm2 and Ae . An = 0.189cm4 > 0.143cm4.
The maximum value of primary current at VMIN is :
POUT Ip=
T)' OMAX' (VMIN-L'1V)
15 0.75· 0.8·9
=2.8A Eq.3
where L'1V is the voltage drop on the R9 resistor and on the POWER MOS, OMAX = maximum duty cycle, T) = efficiency.
The turns ratio is given by the following equations:
Vprim.
n= - - - 'OMAX Vsec
VMIN-L'1V n=
VOUT + VI
. OMAX = 1.03
Eq.4
The nurnber of turns Np is calculated as follows:
NpMIN = _ _V_M_IN_[V_]_._OM_A_X_ _ _ .104 = 9.5turn
L'1B [T ] . Ae [cm2] . f [Hz]
Eq.5
The number of turns used was Np = 10 and Ns = 10.
The prirnary inductance is tHen the same as the secondary inductance.
Lp = Ls '" Np2 . AL = 100 . 2400nH = 240/lH
The value of Ld (leakage inductance) was measured on the transformer:
Ld = 0.5/lH
4/6 530
APPLICATION NOTE
OUTPUT FILTER The most interesting part of the output filter is the transformer T2 which, coupling the output series inductance of the two outputs, gives good regulation of the - 6V output (magnetic regulator). T2 construction is very simple because the two inductance are directly wound on the same cylindrical ferrite core. Each winding is made up of 200 turns
and is: L (+ 6V) = L (- 6V) = 17J.!H.
The lou r last recovery diodes used are BYW29 -1 00 type. Capacitors C1 0, C11 are 220/lF Roederstein EKR low ESR type lor application in switching power supplies. The ripple value obtained is very low = 50mV peak to peak (photo 3). Photo 1 : Tr2, Tr3, Vds (Vds = 20V/div.).
c
o
Photo 2 : Tr3 Waveforms (VG = 10V/div,
Vds = 20V/div, Id = 1A/div.).
a
COMPONENT LIST
Resistors R1 R2 R3 R4 R5 R6 R7 RB R9 R10 R11 R12 R13 R14 R15 R16 R17
B.2K 5.6K 1.2K 1.5K 1.2K 470K 3.3K 390Q 0.22Q 10Q 22Q 22Q 5.6K 5.6K 1BQ 47Q 33Q
1/4W 1/4W 1/4W 1/4W 1/4W 1/4W 1/4W 1/4W 1W 1/4W 1/4W 1/4W 1/4W 1/4W 1/4W 1/4W 1/2W
Capacitors
C1
100/lF
C2
1nF
C3
1/lF
C4
10nF
C5
1.BnF
C6
2.2/lF
C7
10nF
C8
2.7nF
C9
10nF
C10
220/lF
C11
220/lF
C12
330nF
C13
330nF
Transistors
TR1
2N2907
TR2, TR3 = IRFZ20
Diodes D1, D2, D3, D4
BYW2929-100
ICs
11
= SGS3525A
Transformers
T1 core
TOMITA EE 25 x 6.5 2E6 Material
T2 core = cylindrical 30 x 20mm
5/6 531
APPLICATION NOTE
Photo 2a : Turn On.
Photo 2b : Turn Off.
Photo 3 : Ripple on + 6V and - 6V Outputs (20mV/div.).
Photo 4 : Transient Response (20mV/div.).
6/6
532
APPLICATION NOTE
HIGH VOLTAGE TRANSISTORS WITH POWER MOS EMITTER SWITCHING
INTRODUCTION
This paper summarizes the results of an investigation carried out on power devices with both MOS and BIPOLAR parts working together in the same circuit. The "emitter drive" configuration was considered, with switching power supply applications in mind.
The devices used are : PowerMOS Bipolar transistors Ultrafast bipolar transistors (Hollow Emitter) Fast darlingtons
: SGSP321, IRFZ20 : BUV48, BU508A : SGS463 : SGS443 : SGSD00055, BU810
In the case of flyback switching power supplies a practical example is also described.
BY M. SUTERA Figure 1 : The Basic Circuit used forthe Evaluation
of the Emitter Switching System. The Base Drive Circuit used is shown for Comparison.
FAST DIODE
CIRCUIT DESCRIPTION
The term "emitter switching" describes a circuit configuration where a low voltage transistor (MOS or Bipolar) switches off the emitter current of a high voltage transistor, and consequently the transistor itself.
This configuration combines the fast switching of a low voltage device with the high power switching of a high voltage device, since: high current x high voltage = high power switching.
The combination of a high voltage bipolar and a low voltage Power MOS is preferable due to the high switching speed and the low driving energy of the combined power switch.
The base of the high voltage bipolar device is driven by a constant voltage source. The energy dissipated to drive the high voltage bipolar device depends on the losses that the forward bias current IB1 generates in the resistance in series with RB, IB12. RB. t. Thi·s power dissipation can only be reduced by using high gain transistors or Darlingtons.
(see fig. 1).
The diode in series with the base serves to clamp the base over voltage at turn-off. The two transistor stage is driven by the gate of the low voltage Power MOS. Very low driving energies, about 180nJ per cycle, are involved in the charging of the input capacitances.
Consequently the stage can be directly driven by the output of suitable linear integrated circuits.
The possibily of direct driving by an IC output together with the excellent switching speed make this configuration extremely suitable for switching power supplies at frequencies of 50kHz or higher.
CIRCUIT OPERATION As we have seen, the forward base current IB1 is fixed by the external circuitry:
VBB - VBEsat - VOSon
IB1 =
RB
The collector current instead depends on the load, and in general, varies with the time. The turn-on and turn-off phases can be analysed separately.
TURN-OFF When the driving signal to the Power MOS is low the drain current is interrupted and the emitter current of the high voltage bipolar falls to zero. The emitter reaches the base voltage and will not carry any more current. As a result the collector current can only flow through the base, becoming a reverse base current that depletes the base to collector junc-
AN357/0689
1/6
533
APPLICATION NOTE
tion. This reverse base current 182, from the moment when the emitter current disappears, coincides with the collector current. See photo 1. The stored charge is removed in a typically very violent, and consequently rapid manner.
Photo 1 : Base and Collector Current at Turn-off.
Photo 2 : Base and Collector Current at Turn-on.
As a result the storage time is substantially reduced.
The fall time, which is related to the recombination under the emitter, is also generally reduced.
Typical values for the fall and storage time of the SGS-Thomson devices used in the test are shown in table 1, for both emitter and the base drive circuits.
Table 1 : Typical If and ts on Inductive Load.
Device
BUX48 BU508A SGSDOO055 BU810 SGSDOO035 SGSDOO039
IC(A)
Emitter switching
tstarage tfall
Base Switching
tstorage tfall
10 500ns 100ns 2,IS 200ns 5 800ns 300ns 6,IS 400ns 10 400ns 100ns 1.2>Ls 100ns 5 300ns 150ns 800ns 150ns 10 300ns 50ns 800ns 50ns 5 300ns 40ns 700ns 50ns
TURN-ON
When the Power MOS is the on state, the bipolar device also starts conducting. The dynamic behaviour (see photo 2) does not differ in any substantial way from the usual case of the base drive.
The dynamic saturation transient VCEsat dyn is also practically the same with a base drive as with an emitter drive. The.collector current, when the collector load is the primary winding of a switching transformer, can vary according to two possibilities, (see fig. 2).
a) After the initial peak due to the recovery of the diode present on the secondary winding, the collector current increases linearly starting from zero
b) After the same initial peak, the collector current increases linearly starting from the value memorized in the magnetic circuit at the end of the previous cycle.
Figure 2 : Collector Current Waveforms with Varying Load.
5-&112
"1 v1 v1
I I .1 1
I
5-8111
REVERSE BIAS SAFE OPERATING AREA
A problem that occurs in bipolar transistors is damage caused by "current crowding".
Fig. 3a illustrates current flowing in a typical bipolar device. Fig. 3b shows how, when the device is
2/6 534
APPLICATION NOTE
turned off and the current begings to die away, the current focuses with a high concentration under the emitter. This high current density can damage or destroy the transistor.
Figure 3a.
Figure 4b : Fast Turn-off. Crowding with Low Average Heating but Possible High Peak Power.
Figure 3b.
5-8116
Figure 4c : Fast Turn-off (with VCE delayed by snubber network).
Ie COLLECTOR
The energy dissipated within a bipolar power transistor at turn-off can be found graphically from a plot of Ic versus VCE at turn-off. Three cases are shown in fig. 4a, band c. The shaded area is proportional to the energy that is dissipated in the device during turn-off. Consequently turn-off times affect the SOA of the device, (fig. 5b). These problems can be overcome using emitter switching. Figure 4a : Slow Turn-off. No Crowding but High
Average Heating.
5-8115
5-8117
The way the stored charge is swept away in the high voltage bipolar device when it is driven by the emitter, produces some interesting consequences. The stored charges are evacuated through the base contact when the emitter current is zeroed and not later than a few tens of nanoseconds after the beginning of the storage interval. Consequently, during the turn-off, no charge is injected from the emitter irito the base. Although the reverse base current is quite relevant, no focusing of the current in the centre of the emitter fingers takes place.
3/6
535.
APPLICATION NOTE
The bipolar device therefore exhibits an ~nergy absorbing ability at the turn-off RBSOA that IS substantially higher than if a normal base drive were used. With a base drive the emitter would inject charges and the voltage drop across the distributed base resistance would induce the "emitter crowding" phenomenon.
The practical evidence for all the transistors investigated (BUV48, BU508A, SGSF463) shows that.the reverse bias operating area (RBSOA) extends nght up to the BVCES ! (see fig. 5).
This extreme effect is unfortunately much less pronunced when using fast Darlingtons. The higher complexity of the charge extractio~ m~chanism and the charge injection from the emitter Into the base in the driver transistor imply that the RBSOA extension is almost irrelevant.
Figure Sa : Reverse Bias Safe Operating Area.
Ie r:::l=q:::I=l=1r::q::p::p::p:G::5q',:1~~
(A)
15
12
BASE
rSWITCHING
200
800 vee'''
Figure Sb : How Reverse Bias Safe Operating Area Changes for : i) slow turn-off. ii) fast turn-off.
Ie
(A
i 15 'III! 111,111111 I111111
12 I
TYPICAL LOAD LINE WITH
~ SNUBBING
~~~~E_ROF~
..
J>,. ON OFF~
SLOWER TURN-OFF
200
A POSSIBLE APPLICATION
A possible application of the "emitter switchin~" c?nfiguration is shown in figure 6, where a SWitching power supply operating in a "flyback" mode has been implemented.
The basic criteria used in choosing the value of the circuit elements are given below. The purpose of the study was to demonstrate the feasibility and to evaluate the advantages. Exact circuit element values can be further optimized, especially in the case of the transformer.
The power source in the mains singlephase, 220V a.c., and the switching frequency can be set to 50kHz or more.
The devices used were:
01 :
fast Darlingtons with BVCES 1000V for 110V line - SGSBU810 for current up to 5A - SGSD0055 for current above 5A Fast transistor with BVCES 2 800V for 220V line - SGSF443 for currents up to 5A - SGSF463 for current up to 10A
02 :
Low voltage POWER MOS (BVoss = 50V) - SGSP321/1RFZ20 for currents up
to 10A
03: Control
High voltage, low current POWER MOS V(BR) oss ~ 450V)
IC:
UC3842
DZ2:
Zener diode 2W/20V
D.1 :
25V diode, with Ie peak rating as high
as 1OA for 500ns
C6:
Electrolytic capacitor, 100IlF, 25V.
It absorbs possible variations of VBB.
R3:
Resistor setting the forward bias
. base current of the Darlington:
VCE - VBEsat - VOSon - R7 10 R3=-------------------
IBt
Its power rating must exceed R3 . IB2
. t (in practice 3W)
R7:
Shunt resistor to sense the switch
current. The over current Is max pro-
tection is set according to
1V
R7=----
Ismax
4/6 536
APPLICATION NOTE
C4,R6: C3, R5:
RB, R9:
C2, R4: R1 : R2: 04:
RC network, filtering the disturbances induced by the switching transients on the Ismax protection input.
RC network, setting the switching frequency and the maximum duty cycle, according to the UC3B42 data sheet. !charge = 0.55 Rs C3
Idischarge = Rs x C31n [(6.3 Rs - 2.7)/(6.3 Rs - 4)] f = 1/(!c + td)
Resistive divider of the feedback voltage from a secondary sense winding, rectified by 05 and C5. The divided voltage is compared by the control IC to an internal reference of 2.5V.
Compensating network in the error amplifier of the feed-back voltage.
Resistor biasing the 03 gate (1.2M, 1/4W)
Resistor that limits the inrush current
through the POWER MOS, 03, at
the turn-off (1.2, 2W)
.J
Fast recovery diode Its voltage/current ratings depend on
Figure 6 : "Emitter Switching" Circuit.
the particular secondary winding it rectifies.
05 :
Low current/low voltage diode
03, R10, CB : Snubber network (fig. 6 shows just one of the possible configurations).
Ld Il
CB=-Vos2
R10 = 1/4fCB P (R1O) = 1/2 Ld 102 . f where:
f = switching frequency ld = stray inductance of the transformer Vas = maximum voltage overshoot allowed
03 :
A 400V fast recovery diode
C7 :
The use of a capacitor reduces the crossover of the Darlington {3 to 6nF)
It is important to note that, the power transistor 03 acts only at the turn-on of the power supply and when the capacitor C6 supplies more energy to the base of the Darlington and to the supply input of the IC than is returned to C6 during the turn-off of the Darlington, 01.
04
CE
QJ R9
D2 R3
7 C2
UC
II 3842 6
,
3
5008118
5/6 537
APPLICATION NOTE
CONCLUSION
The "emitter drive" configuration exhibts some clear differences with respect to the usual "base drive" configuration, and they can be particularly useful in switching power supply applications:
- Substantial reduction of the storage time and improvement of the fall time.
Switching frequencies of 50kHz and higher are possible
- The dynamic drive circuitry is simplified. The negative voltage supply is not required to remove the stored charge from the base. The energy needed to drive the gate of the POWER MOS is very low (180nJ per cycle).
Extremely high ruggedness at the turn-off of the inductive load (i.e. very large RBSOA) if the high voltage bipolar part is a transistor.
Higher power dissipation in the on-stage, due to the additional losses in the POWER MOS (102 . Ros (on) . ton).
This last point is the only disadvantage, but it is more than compensated for if switching at high frequencies. The lower switching losses (a saving each cycle) can justify the higher on-state losses (a fixed expenditure) as soon as the switching frequency is high enough, which is often the case in switching power supplies.
6/6 538
APPLICATION NOTE
A TRANSISTOR FOR 100 kHz CONVERTERS: ETD
INTRODUCTION
Power converter designers aim to reduce the size and the weight of their equipment. Hence, there is a trend towards higher operating frequencies. Consequently for the semiconductor manufacturers, there is a growing demand for fast switches. The POWER MOSFET transistor is now well known as a fast device.
However, the development of ultra fast "ETD" bipolar transistors is now challenging this way of think-
BY Luc WUIDART
ing in certain applications. As an illustration, we have selected an example of a "300W - 1OOkHz forward" switch mode power supply (SMPS).
VOLTAGE CONSTRAINTS
This "forward" converter contains a single power switch and operates directly from the 220V AC mains. The principle wave forms are illustrated in figure 1.
Figure 1 : Basic Theoretical Wave Forms of the Forward SMPS.
TOaD 018 L
AN361 10689
1/7
539
APPLICATION NOTE
The switch must be capable of withstanding a static collector-emitter voltage which, to afirst approximation, is given by :
(1 + np/no) x Vin, where,
np = number of turns in the primary winding
- no = number of tums in the demagnetization winding - Vin = rectified mains voltage
When operating on the 220V AC mains and when np equals no,· the voltage across the switch termi-
nals should only reach 750V in the worst case (corresponding to a maximum rectified mains value of 375V AC).
In reality, the voltage across the switch terminals reaches a peak value (Vpeak) which is much higher. The peak value depends upon the switching time, the circuit capacitance and the leakage inductance Lf between primary winding np and the demagnetization winding no (see figure 2).
Figure 2 : Leakage Inductance Lf between Primary Winding npand Demagrietization Winding no.
TOOO-020
L
Tr. D1
+
+ ~.--------------~-------.
np
·
1 Is
1 Vs
s
-@~_L.-
DESIGN OF SNUBBER CIRCUIT
At turn-off, energy stored in the transformer leakage inductance generates a voltage spike (figure 3). In order to limit this voltage spike, the energy must be transferred to the capacitor Cmin in the snubber circuit. The energy depends on the switching current. In a 300W SMPS, the peak value of the current Imax
is 5A. It is this value of current which is used to calculate the value of the capacitance Cmin required.
With a maximum voltage Vpeak, the value of Cmin can be calculated using the following formula:
Cmin = -----·-2·---L-f--X-"I2m--a-l·-····---·-·-2-
Vpeak - Vin max (1 + Np/No)
Figure 3a : Wave Forms of Switching Current and Voltage Across the Switch Terminals at Turn-off.
TOCO 021
Irtfi~I 2/7 540
APPLICATION NOTE
Figure 3b : Definition of the Voltage VCEoff. VCEoff is measured when the Collector Current Reaches 2 % of the Collector ICend.
7000 011 I, V
We call VCE,If the voltage which appears during the turn·off at the moment when the collector current
Ie reaches 2% of its value Iceno. If the value VCEoff measured in the circuit is low compared to the rating
VCEW of the transistor. the safety margin between the SOAR and the stress on the transistor is large.
VCEW is the maximum VeE voltage at turn-off with current.
In practice, Vpeak can be set between 800 and 900V. To provide a safety margin, a switch with a blocking
voltage capability of 1ooav must be used. This voltage
corresponds to parameter VCEV for bipolar transistors and to VDSS for POWER MOSFET components.
For bipolar transistors, an additional parameter must be considered : the Reverse Biased Safe Operating Area: (RBSOA). The turn-off cycle must remain within the RBSOA, otherwise, the value of capacitance must be increased from Cmin to a higher value Cr.
Thermal dissipation in the snubber resistor, Rs (figure 6), will be increased in the same ratio:
Cr = .-.-t-f-i--X.--Im--a~.x--2 X VCEoff
For the selected transistor, VCEoff must be less than the specified VCEW (see figures 3a and 3b).
SWITCH TYPE In this application, three different types of switch using different technologies are considered. These are:
conventional bipolar transistor, - POWER MOSFET, - ultrafast bipolar "ETD" transistor (see appendix). Table 1 summarizes the performances of these types of switches under operating conditions, i.e., for a junction temperature of 1OODC and with a well adapted gate/base drive (optimized totem-pole drive for POWER MOSFETs and negative bias drive for bipolar transistors).
Table 1 : Transistor Characteristics.
oaoe Characteristics at Tj = 1 "Totempole" gate drive. Base drive with negative bias. Same silicon
area for each switch.
STHV 102 VDMOS
BUV 48 Conventional Transistor
BUF 410A ETD Transistor
Blocking Voltage Capability
1000V 1000V 1000V
Switching Time
(Tj = 100°C)
t,
tfi
100ns
100ns
85ns (60A/ps)
50ns (100A/ps)
250ns 100ns
Conduction
(Tj = 100°C)
"v RDsan, CEs_t
5An
2.8V (5A)
2.8V (5A)
3/7 541
APPLICATION NOTE
The first point to notice isthat at turn-off, an ETD transistor is as fast as a POWER MOSFET. More surprisingly, the ETD transistor is twice as fast as a POWER MOSFET at turn-on.
Let us now consider the effects of the characteristics
upon the size of the snubber. With a leakage inductance of 6.51lH and a current of 5A, a capacitor Cmin of value 680pF is sufficient to limit the voltage Vpeak to 900V (fig. 4) :
Figure 4 : Comparison of Turn-off Cycle Within the Safe Operating Areas for the Three Different Switches.
~~-.-
I c I A)
RBSOA of conventional bipolar transistor
15
Load-nne with
10
Cmln· I80PF
~l
. "-. '(
Loali-line with C, .1.8nF
VCEon
1000 Vpeol<
VCE IV)
10(.0.) 15
SOA ofal'owerMOSFET
10 Load-llne with Cmln ·~80pF
'''/.f 50D VCEon
I 1000
VpeBk
VOS (V)
IcI A)
1~
RBSOA of the ETD tran3 i:stor
Load-linDwith
10
,/Cmln· 680pF
'-..
500 VCEon
Vpeol<
VCE (V)
4/7
l!fi~I S1>llG~I:ISiiI·@rmn~rnO«:1iM'IiiSI@IlOl~I:Ni!l
542
APPLICATION NOTE
However, a capacitor Cr of 1.8nF is required to limit the VCEoH voltage to a value that is within the RBSOA of the bipolar conventional transistor. In comparison, the POWER MOSFET and ETD transistors can be kept within their safe operating areas with a capacitor of only 680pF.
LOSS EVALUATION
For the 300W forward SMPS operating at 100kHz,
the following assumptions have been made.
The losses have been evaluated assuming a current Inom of 4A, corresponding to the nominal output power. A current of 2.8A rms is obtained with a duty cycle of 48.5%. For a realistic comparison, conduction losses were reduced by paralleling two POWER MOSFETs (the conduction losses of a single POWER MOSFETs would be approximately 43W).
The results of this evaluation are as shown in Table 2.
Table 2 : Results of Loss Evaluation for the Conventional Bipolar Transistor, the two paralleled Power MOSFET and the ETD BUF 410A Transistor.
BUV48A
Silicon Area
30mm 2
Snubber
C,
(RCO)
PR'
1.8nF 51W
Losses in the Switch
30W
Conduction
5AW
Switching
20.7W
Drive
3.9W
TOTAL LOSSES (RCO + COM)
81W
PR is the power dissipated in the resistor of the snubber circuit.
2 x STHV102
40mm 2 680pF
19W 34W 21.3W 12.3W OAW
53W
BUF410A 30mm2 680pF
19W 17.5W 5AW 9.2W 2.9W
36.5W
for this application, the ETD transistor requires no more silicon area than a conventional bipolar transistor. the ETD transistor uses the same value of snubber capacitance as a POWER MOSFET. conduction losses in the ETD and the conventional bipolar transistor are the same. the ETD transistor has the lowest switching losses of the three devices considered.
In our example, at 100kHz, the superior performance of an ETD transistor results in about a 50% reduction in losses as compared to the BUV48A and 30% compared with POWER MOSFETs.
vices considered, the ETD transistor is the optimum cost/performance solution.
In addition, as a result of its fast switching capability (tr < 50ns ; tli < 1OOns) and its extended RBSOA, the ETD transistor can be successfully used in other applications such as resonant converters, motor drives or uninterruptible power supplies.
ETD transistors with blocking voltage capability higher than 1000V are under development. These transistors will enable higher switching frequencies to be used in equipment supplied directly from the 380/440V mains supply.
CONCLUSION
The example described in this paper (300W 100kHz SMPS), figure 6 shows that of the three de-
5/7 543
APPLICATION NOTE
APPENDIX I
WHAT MAKES ETD TRANSISTORS SO ATTRACTIVE?
The new generation of ETD transistors adapted for high voltage applications is designed with an inovative technology utilizing a high degree of interdigitation.
The most innovative feature of this technology consists of the replacement of the traditional bipolar structure with emitter fingers (size: 250/lm) by a cellular structure with much smaller dimensions (80/lm cells). This cell design considerably eases the extraction of charge stored in the transistor during each switching cycle, since access to the intrinsic base is easier. This makes it possible to reduce switching times to values as low as 100ns.
The "Planar" technology has been selected for two reasons:
It permits extension of safe operating area at turnoff. Moreover, it requires a reduced number of
masking levels with respect to conventional high voltage "mesa" power technologies.
REGULATION DYNAMICS
InSMPS or motor drive applications, the minimum conduction time is a fundamental parameter when considering the dynamic regulation. The delay time at turn-off of the POWER MOSFETs specified in the data sheet is sufficiently low. In the case of bipolar transistors, storage time depends on conduction time. In our application at 100kHz, conduction time must vary from less than one microsecond to five microseconds. In the BUF410A data sheet, the cu rve showing the variation of storage time, ts, versus conduction time, tp, shows that storage time varies from zero to 750ns maximum (see Figure 5). Consequently, the regulation dynamics are not limited.
Figure 5 : Curve Illustrating the Variation of Storage
Time tsi versus Conduction Time tp. (ETD trC).nsistor BUF41 ~Al.
If-- lsi (~s
-- ----.~-"
S[-1106 -f--
1\
1.2
li
1.0 -I I - l-'"
O.B
1/
._- ._-
- - --~
-I-- I( =5A
IB=0.5A ~I- -
06 1/
-- vBB = -5V
_._.,-~ -I--
04
Tj = 100 O(
- ~I~
--lj-H~H- O.2~ f---f--- -f---
~I- -
~I- f--- ..._, --
I
f--- c--
10 15 20 25 30 35 Ip (~sl
6/7 544
APPLICATION NOTE
Figure 6 : Schematic Diagram of an ETD BUF41 OA Transistor Implemented in a 300W - 100kHz Forward SMPS Application.
2:~ov---m-a-i-ns--------'_~
TOOO-026 DI
@--------+-----~
+ 12V
jl _.:kl';;j"'"' ] C:J~:LII< _1- 11:1.,-.1-1" · ~_1O_0_0-t-BY;T~OO
~
I ""eo 6S0pF
-
10
~10A
From galvanic insu\ulion
--':~ J 3300
To control Ie Q I p-channel-45V. Dohms
Q2
p-channel-6DV, 1 ~6ohms
7/7 545
APPLICATION NOTE
AN INNOVATIVE HIGH FREQUENCY HIGH CURRENT TRANSISTOR CHOPPER
INTRODUCTION
Recent developments in power semiconductors and associated technologies have made possible the realization of medium power converters (5-50kVA) operating at switching frequencies higher than 20kHz.
This paper presents the design of a high current (500A), high frequency (20kHz) chopper using fast Darlington switches operating from a low voltage supply (60V). New optimised design techniques for paralleling power semiconductor devices are described. The association of these methods allows the switching of 500A in less than 200ns.
These new techniques are also suitable for high volt-
By L. PERIER & J. BARRET
age medium power converters operating at high switching frequency, such as UPS, welding converters, motor drives and battery chargers.
A 500A - 20kHz CHOPPER WITH DARLINGTON IN PARALLEL
High frequency bandwidth and regulation is achieved for the 500A output current by switching at an ultrasonic frequency of 20kHz with a turn-off time of less than 200ns. Consequently, high rates of change of current (in excess of 2000N~IS) are experienced. Six Darlington transistors (ESM2012 D) in parallel and four ultra fast rectifiers (BYV54-200) in parallel are used to achieve the current rating.
Figure 1 : Switches used in the Chopper.
TOOO 092
~ I ~ -- r -.- - - - - -
1
~ I :
! I : H © '
I 1
1
:1 I
-I
~A:1
@
1
.
1
L ________ · ___ .J
AN366/0689
ESM 2012 D
VCEW = 125V VCEV = 150V
VCEsat (100°C) < 1,5V
for Ie = 70A Is = O,25A
tl;( 100°C) < O,4ms Rth = O,7K/W
BYV 54-200
VRRM = 200V VF(100°C) < O,85V for IF = 50A Rth = 1,2K/W
1/8 547
APPLICATION NOTE
Figure 2 : New Base Drive Concept which Automatically Generates the Negative Bias. The negative bias generated is independent of the duty cycle.
11 Power stage
QC-----J9 r ---,
L.
___
:
~
r ---~
2
x
IlYV
54 - 200·
L
___
:
~
TODD 093
- -- -"-
c @.--~--------------------~
G x
ESp,( 2012 fl
-,
- 1- ---T--t-+£
11 27U~1 11 --~----4-+-l
1
1
aD-lOa £ ·
=--- -- - - _____ I --1
1 [
100
n L
- -. - - _.-1
L - - -_ _
21 Base Drive
Bzxes
C3VO
n:!.xlIJ
C2V~
TODD 094
+ 7-13V
66 B
ON
Jl
@-~__~~__________~__~~~____~~~__~. F./GNO The 500A/60V/20kHz chopper
2/8 548
APPLICATION NOTE
A power Darlington and diodes are shown in figure 1 together with their important characteristics. Figure 2 shows the power stage and the base drive circuit.
A base current of 5A is sufficient to control a collector current of 500A. The static and dynamic sharing of the collector and base current between the paralleled devices is better than 90% provided:
a) The devices are mounted in a circular layout on a common heatsink as shown in figure 3.
Good utilization of the heatsink is achieved using this physical layout.
b) The bases of the output stages of the Darlingtons must be linked together. The access to the bases of the output stage of the ESM2012 D Darlingtons enables this.
Due to excellent current sharing, the Darlingtons can be used close to their nominal collector current rating.
Figure 3 : Circular Geometry for the Physical Layout of Power Devices.
TODD 095
Top view
The BYV54-200 ultra fast rectifiers in parallel are not derated as these fast recovery epitaxial diodes have
Figure 4 : Power Stage.
Side view negligible voltage drop (VF) spread.
3/8 549
APPLICATION NOTE
Low wiring inductances are required for high performance switching as parasitic inductances cause
overvoltage spikes at turn-off,
Figure 5 : A Low Wiring Inductance is Necessary in Order to Avoid High Over Voltages at Switch off,
+
I :.
/~ ~,
L
~
~')~I
'\
VeE
Off]
@--
-
~v Ie : - - :
.crI £:Ii-·I-
The 500A chopper has been designed with a low inductance plate wiring method, The plate wiring con-
Figure 6 : Low Inductance Wiring,
TOaD 097
L
i00nH
If
200ns
Ie
i0A I 50011
!'.v
J 5V
250V
sists of 2 parallel copper plates separated by a thin adhesive insulator (see figure 6),
TODD 098
+ +
Load
~--
Load
Technology
High· wiring inductance
Low .winng inductance
~-"
I
AdheSIve LnsuLator (Kapton)
4/8 550
APPLICATION NOTE
Wiring inductances as low as 5nH/m can be achieved in a 500ARMs circuit using plate wiring.
The parasitic inductance of the power stage of the 500A chopper (capacitor + Darlington + free-wheeling diode) has been estimated at 20nH. Such a reduction of wiring inductance in the power stage and
the base drive allows:
* Very high switching speed of the Darlingtons at turn-on and turn-off: 2000NIlS.
* At turn-off an overvoltage of only 50V is experienced by the Darlingtons for a dlldt of 2000A/IlS.
Figure 7 : Turn-off Switching of the Fast Darlington Switch.
TOOO 099
1 1IC0,0VAC/dEiv
20V/div
... V o
!,-r-... VCE
'-I. / i\
V "v
1\ Ie
'\
/\ r-.. '-
The ISOTOP package is used forall the powersemiconductor components in order to optimize cooling and wiring. The package has screw terminals on the top of the
Figure 8 : A High Current Package: ISOTOP.
----7
t ~ 1 OOns/div
case suitable for plate wiring, low parasitic inductance due to its low profile and internal insulation with low thermal resistance.
Current
Copper
......
Screws
PCB
U
Heat
Heat sink
TOOO 100
CONCLUSION
The design of a 500A - 20kHz chopper using fast switching Darlingtons and diodes has been presented.
The power semiconductor components have been packaged in the ISOTOP package, allowing screw connections and plate wiring techniques to be used. The techniques developed also can be applied in the design of medium and high voltage converters.
5/8
551
APPLICATION NOTE BIBLIOGRAPHY
111 G.A. FISHER High Power Transistor Inverters 16th Power Engineering Conference/Sheffield (UK)
121 K. RISCHMOLLER La commutation rapide des transistors et Darlingtons de puissance Electronique de Puissance n 15. Schnell schalten mit Transistoren und Darlingtons Elektronik 20/9/85
131 L. PERIER High Current Switches for Bridge Leg EPE 85/Bruxelles (B)
141 J.D. VAN WYK - R.B. PREST Base Drive for High Current Low Loss Bipolar Power Transistor Switches PESC 86 (June 86)
151 J.J. SCHOEMAN - J.D. VAN WYK - H.w. VAN DER BROECK On the Steady-state and Dynamic Characteristics of Bipolar Transistor Power Switches in Low Loss technology lEE Proceedings 132 - Sept. 85.
6/8 552
APPLICATION NOTE
APPENDIX I
LOW INDUCTANCE WIRING
1. Modelling and inductance The inductance of wiring made circular cross section wire, can be modelled as the sum of two terms:
a) Self inductance of one wire:
LI = 1-10 (Him)
8][
Eqn.1
b) Mutual inductance of the loop:
L2 = -1]1[0
b- a
Ln -a- (Him)
Eqn.2
The total inductance of the wiring as thus:
LT = -110
( -1
b- a + In - -
) (Him)
][ 4
a
Eqn.3
TOOO 101
- ,,,
---:,,
b
- ,,
..
= :
LT depends strongly on the geometry of the circuit. The best way to decrease LT is to decrease the area of the loop:
TODD 102
:>
2. TECHNOLOGY FOR LOW INDUCTANCE WIRING
TOOO 103
adhesive ~ copper
d
L = 110. W EqnA
I = 500A, 0 = 20A/mm2, W = 50mm, d = 1mm =} L = 20nH/m
7/8 553
APPLICATION NOTE
APPENDIX II The cooling ability of a heatsink is not linearily dependent on its length
TOOO 104
~e -- -- -- -- -- -- -- -c:.--- - - -
~e
2,8~
2
~--------__ Losses
Separation of heat sources is thus necessary to optimize the cooling
SOOw
SOOw
@J
tfu
=
Weight + 0,7
TOOO 105
= Weight = 1
J2 Length, volume and weight can be reduced in some case by a factor of if heating sources are spread
over the heatsink
8/8
554
APPLICATION NOTE
A POWER STAGE FOR A 20kHz 1OkW SWITCHED MODE POWER SUPPLY FOR THE INDUSTRIAL 380/440V MAINS
INTRODUCTION
The theory of transistor converters operating from the single phase 220V mains is not the same as that for switched mode power supplies operating directly from the 380V and 440V mains and delivering an output power of more than 10kW. For the latter the increased technological constraints must be taken into account when designing such a converter. This paper explains the design of a 10kW - SMPS operating on the three-phase 380V - 440V mains and the solutions which have been found to resolve the technological problems.
CHOICE OF THE CONVERTER STRUCTURE
The converter has been designed for a supply from the 380V and 440V mains. It must provide an output voltage of 80V and an output power of 10kW. The operating frequency has been chosen to be 20kHz. There are several possible solutions for the topology of the converter. The choice of topology
Figure 1 : Full Bridge Converter.
By Jean BARRET
has been strongly influenced by technological considerations.
CONVERTER TOPOLOGIES FOR THE 10kW - POWER RANGE
Considering the high supply voltage and the switching frequency of 20kHz, converter topologies applying a voltage in excess of the supply voltage to the transistors, or necessitating a power transformer with a low leakage inductance have been eliminated. Transformers with a low leakage inductance that respect the insulation standards are difficult to manufacture. The one transistor "forward" converter and "push pull" converter are thus eliminated.
The choice of the converter topology is reduced to two converter types:
- The full-bridge (figure 1) which is a symmetrical structure with alternating magnetic polarisation.
- The asymmetrical half-bridge (figure 2) in which the magnetic polarisation is uni-directional.
AN367/0689
1/9
555
APPLICATION NOTE
Figure 2 : Asymmetrical Half Bridge FORWARD Converter.
CHOICE CRITERIA
Theoretically the complete bridge is the solution for high output power: at equal output power the transformer is half as big as that of an asymmetrical half bridge.
In practice, there exist a certain number of secondary parasitic phenomena which reduce the advantages of a symmetric structure in comparison to the half bridge. One of these phenomena is that a full bridge is never perfectly balanced. A circuit to correct the symmetry must therefore be designed in and the transformer must be slightly larger to avoid saturation due to dissymmetry.
The full bridge necessitates the use of 4 bidirectional switches and therefore of 4 galvanically isolated drive circuits, whilst the half bridge only requires 2. Simple switching aid networks cannot be directly applied to a full bridge, due to the direct coupling bet'Neen the upper nnd !0\-:8:- s'vvitches. Supplementary chokes therefore have to be added which would complicate the circuit considerably.
The asymmetrical half bridge does not have these problems. The input current of the asymmetrical half bridge has a bad form factor. Consequently and contrary to a full-bridge, the input filter capacitors of a half-bridge are subject to a high RMS-current.
These different considerations led us to choose an asymmetrical half bridge. The experiment has shown that our choice was reasonable and we think today that,for an output power in the 1OkW area, the asymmetrical half bridge presents the best technical and economical compromise.
For a substantially higher output power the full bridge seems to be preferable. AltemativelY,2 asymmetric half-bridge circuits can be used, operating in antiphase.
THE ASYMMETRICAL HALF BRIDGE
GENERAL CIRCUIT DIAGRAM
The figure 3 shows the basic circuit and the principal voltage and current waveforms of an asymmetrical half bridge.
!n this converter, the transistors T1 and T2 are driven simultaneously. They conduct for a time "C and are off for the rest of the period, T - "C.
The diode D1 on the secondary conducts while the transistors are conducting (time "C). The secondary current (during time "C) goes through the inductance L. The diode D2 operates as a free-wheel diode (time T -"C).
2/9
556
Figure 3 : Forward Asymmetrical Half Bridge Converter.
APPLICATION NOTE
.. I IT, CIT2
i
.
I D3 CIn.,
r1...l,
...4---------.-~
T
r ,--.--
~
....
..
IL~
I ::::::::::;:'" ----=::::::;::: ./
-~-------. ----
THE MAIN FEATURES OF AN ASYMMETRICAL HALF BRIDGE
The main features of an asymmetrical half bridge are:
The power transformer and ferrite core. Litz wire is used for the primary because of its reduced skin effect. The low leakage inductance is obtained by winding a half-primary and a half-secondary onto each leg of the transformer. A reduction ofthe duty cycle with increasing input voltage limits the magnetisation of the core. This reduces the transformer's volume to a minimum.
The Power Switches. The simultaneously driven power switches must be fast.Their drive must not be disturbed by parasitic signals. To obtain agood voltage safety margin, turn-off snubbing networks are necessary.
Rectifiers and filter components. The choke inductance is the prinCipal component of the output circuit. As far as possible, the inductance must be high, so that the maximum current in the power switches and the recifier diodes is as low as possible. Fast recovery diodes are used to reduce the switching oscillations. The use of an RC net-
work in parallel to each diode reduces 'the voltage ripple on the output.
- Safety. In power equipment, safety isa fundamental element which must be considered from the very first stages of design. The principal active safety elements we introduced are:
a, current limitation for the power switches, b, a soft start,
c. protection against overload on the output,
d. control of auxiliary voltages,
e, control of the transformer core magnetisation, I. minimum conduction time for complete dis-
charging of the snubbers.
- Control. The control circuit was developed with an integrated circuit, the UAA4006. Amongst other things, this circuit contains several protection functions. The output voltage is detected by means of an extra winding on the filter choke. The free wheel diode is conducting during the demagnetisation phase of the filter choke. During that time interval the voltage across the filter choke is equal to the output Voltage. This voltage is fed to the control IC, The control IC also provides the features a-f listed above for safe operation,
3/9
557
APPLICATION NOTE
THE POWER SWITCHES
For the 1OkW switched mode power supply operating from the 380V - 440V mains two fast power switches able to switch 1OOA with a maximum supply voltage of 700V are required. There are two possible solutions when choosing the power transistors.
1. To choose transistors with VCEW higher than the m.aximum voltage the switch has to sustain. Theoretically, this would allow a design without turn-off switching aid networks.
2. To choose transistors with VCEW higher than half the maximum supply voltage and with a VCEV rating higher than the maximum voltage the switch has to support.
The second solution has the advantage of better switching performance than the first one.
Figure 4 : Power Switch.
+ 5 A m-ax - 20 A max
The switching times must be as .short as possible since the minimum conduction time is of the order of 7~s and during a short circuit at the output about 2 to 3~s.
Our choice is a Darlington combination using ESM6045A (fig. 4).
PRINCIPAL CHARACTERISTICS OF THE TRANSISTORS USED
ESM6045A
VCEW > 450V
VCEV> 1OOOV (VSE = - 5V)
VCEsat> 2.0V
tfi < O.6~s }
tsi < 6.0~s
Ic = 60A and 18 = 2.4A
te < 2.0~s
Ti = 100c C
lIe < 100 A
--, I I
I----------~,
I
I
1 I
I'
I
I
I I
I
I
I
I
I
-.l
Note that this type of transistor is mounted in an ISOTOP package. The insulation voltage between the die and the bottom of the case is 2.5kV r.m.s. This avoids not only external insulation but also considerably reduces the capacitance between the transistor and the heat sink, hence gives a reduction in RFI. A l':p.rtrlin numher of preC8.utions are required when using transistors with VCEW lower than the maximum voltage, to which the switch is subjected:
A base-emitter resistance must be connected to each transistor (value stated on the data sheet), which insures a static blocking voltage of 700V and therefore protects .the switch against any problem arising from the negative bias. Nevertheless the auxiliary voltage should be monitored.
A turn-off switching aid network must be connected to each switch to insure that the load line stays in the RBSOA at switch off. In our case, the
network has to be calculated so that the collectorcurrent reaches zero before the collector-emitter voltage reaches 450V.
- The driver circuit must be capable of providing sufficient base current with an optimized waveform.
The conduction time of each transistor will always have to remain higher or equal to the time necessary to discharge the snubber capacitor even in the case of an overload.
If these precautions are respected, the voltage safety margin is the same as if very high voltage transistors were being used.
BASE DRIVE CIRCUIT
The base drive turns the transistor switches on and off as determined by the electronic control and safety circuit.
4/9 558
APPLICATION NOTE
The positive base drive is regulated in order to maintain the power transistors in quasi-saturation. This reduces the effect of parameter spread of the power transistors and simplifies the paralleling. The storage and fall times are also reduced by this means.
Figure 5 : Base Drive Circuit.
The base drive must have a high immunity to electrical disturbances (dV/dt for example). The input interface uses a driver transformer with a bobbin with two segments. The base drive circuit for one switch is shown in figure 5.
r------------l
v .Y
I I I I
I
I I
I L __ ..
x x
"E 'E"
«
000 N
+ I
\
5/9 559
APPLICATION NOTE
Figure 6 : Wiring for High Power Switching. a) Base Drive with Poor Wiring.
b) Base Drive with Recommended Wiring.
6/9
560
APPLICATION NOTE
WIRING PRECAUTIONS
Special care must be taken concerning the wiring of the fast high power switches. The switching speeds being in the order of 200Allls (much more if they are not limited), current/voltage oscillations are induced in the leads.
It is therefore necessary to pay particular attention to the wiring to reduce the parasitic inductance:
The connections between transistors, and to the drive must be as short as possible (figure 6) and form very small wiring loop areas.
- Try to obtain the highest symmetry possible between the paralleled transistors. The spread of the transistor -characteristics is only of second order, (for components of the same type and from the same manufacturer) the spread in switching times is essentially a result of the wiring dissymmetry.
- The reference point for the driver must be the emitter connection of the power transistor. Figure 6a shows an example where the zero point of the driver circuit is disturbed by voltages created by the fast rise and fall (d Iidt = 50AlIlS) of the output current of the driver stage.
- The decoupling capacitors must be connected as close as possible to the switches.
- The decoupling capacitors must have low equivalent series inductances and resistances. To further reduce the impedance of the decoupling capacitor, multilayer film capacitors with low parasitic impedance have been connected in parallel to the electrolytic capacitors.
THE SNUBBERS
A turn-off switching aid network is needed due to the VCEW rating of the switching transistors which is lower than the supply voltage. To obtain high efficiency from the power supply, switching aid networks with energy recovery have been choosen 121.
Due to the reverse recovery behaviour of the diodes
these snubbers do not operate in an ideal way. The reverse recovery current of the diode DAc3 (fig. 7) causes some problems.
The reverse recovery time, trr, is dependant on the diode technology and the switching conditions.
The reverse recovery current of this diode has sev. eral consequences.
- With a low load on the output of the power supply it produces a reverse collector-emitter current in the transistor. The transistor can be protected against this current by means of an antiparallel diode between collector and emitter.
- The reverse recovery current of DAc3 partially recharges the capacitor C1 (and discharges C2), figure 7.
- It also flows through the choke L. If the stored energy is not discharged it will generate overvoltages. The diode DAc4 clamps and limits this overvoltage to the supply-voltage. Unfortunately, the current through this "clamp" recharges C1 still more (fig. 8).
Diode DAC3 must be chosen with care. To reduce the parasitic phenomena it must have a very fast recovery characteristic. The type BYT30-1 000 was used.
The resistor (R) parallel to the diode DAc1 allows the complete discharge of the capacitor C1 during the conduction time of the transistor (figure 8). This increases the snubber losses, but they are still significantly reduced (- 30%) when compared to those of a conventional RCD-snubber.
These modifications to the snubber with energy recovery are justified with high switching frequencies (e.g. : 20kHz) and when the minimum conduction time is short. In this case the snubber must reset very rapidly and the parasitic phenomena of the components can no longer be neglected.
The other components of the snubber are chosen in the same way as those for the conventional RCDsnubber.
7/9 561
APPLICATION NOTE
Figure 7 : Non Dissipative Snubber.
+ VA
I wcJ__ ""
I WAf) Ie ---....-~.-.- -~II
Figure 8 : Complete Diagram of a Power Converter Output Stage.
II
IJ'OO"' ___
o
Diodes: BIT 30 - 1000 ( D AC ..... .l
Transistors: 2 x i';SM n045A
8/9
562
APPLICATION NOTE
CONCLUSION
The technological constraints are very important in the design of converters supplied from the 380V 440V mains.
The use of high voltage transistors with a VCEW rating lower than the supply voltage requires certain precautions, but enables a fast switching speed to be achieved.
The magnetic components (transformer, filterchoke), technological choices are also important since they affect the overall performance. of the equipment as well as their influence on the size of the active components.
Adding the snubber with energy recovery increases the efficiency of the power supply and the overall reliability.
This circuit constitutes a basis for the development of switched mode power supplies in the power range of 1 to 10kW for power supply, welding induction heating, battery charger and other high power applications.
REFERENCES
111 "La securite de fonctionnement des equipe-
a ments transistor".
Le transistor de puissance dans la conversion d'energie - p. 123 - 136.
Joel REDOUTEY - SGS-THOMSON Microelectronics -1983.
121 "Transistor chalter im bereich hoher Leistungen und Frequenzen" RTZ Bd 100 (1979).
Andreas BOEHRINGER und Helmut KNOLL University of Stuttgart.
131 "Retard, bruit, remise en cond~ction"
Le transistor de puissance dans la conversion
d'energie.·
.
Jean BARRET - SGS-THOMSON,Microelectronics 1983.
141 "Improved Transistorized High Power Choppers" PCI 83 - Geneve.
Klaus RISCHMULLER - SGS-THOMSON
Microelectronics.
.
161 "3KW switch mode power supply providing sinusoIdal mains current and large range of DC-output" PCI 80 - Munich.
Helmut KNOLL - University of Stuttgart.
9/9 563
APPLICATION NOTE
POWER SEMICONDUCTORS FOR HIGH FREQUENCY AC/DC CONVERTERS SUPPLIED ON THE 380/440V MAINS
INTRODUCTION
This pape~ is the result of the development in our laboratory of different switches and converters able to operate at ultrasonic frequency, supplied directly from the rectified 380/440V mains.
This paper presents, in the first part, a typical specification for the converter and power switches.
The second part describes several switches and driving circuits optimized for those requirements.
1. SPECIFICATION:
Our objective was to develop switches and drivers optimized for AC/DC converters supplied on the industrial380/440V mains, switching at ultrasonic frequency as used in Switch Mode Power Supply, battery charger or weldin\:!. converter applications.
We based our development on the design of a 5KW asymetrical half bridge (2 transistor forward) converter. An equipment of 1OkW could be design with the same switches mounted in full bridge or in the assembly of two asymetrical half bridge operating in antiphase.
Because of the high voltage supply, the blocking voltage capability of the switches is 1000V. In order
to minimize the transformer and filters size and the
acoustic noises a switching frequency over 20kHz
is required.
.
In a 5kW asymetrical half bridge supplied on the 380V mains, the maximum duty cycle of conduction
.By L. PERIER & J.M. CHARRETON
of the power switches is 50% of the total period. The current in the switch is 15A. Consequently the RMS current in the switch is 11 A.
In order to use a very small heatsink the conduction losses in each switch are minimized (30W).
Auxiliary supplies for the power switches are also excluded in order to minimize the volume and the cost of the auxiliary circuitry.
2. A 1000V MOSFET SWITCH:
Power MOSFET technology is well adapted for the design of switches able to operate at high frequency. 1000V MOSFETs exist and they present the classical advantages of the MOSFET technology : low drive consumption, good turn-off safe operating area, high over current capability, ...
Butthe resistance olthe epitaxial layer required to widthstand the blocking voltage Vos (if 250V) is approximately proportionnal to Vol,5. Consequently, the on resistance R(on) of the Power MOSFET increases rapidly with the blocking voltage capability Voss.
The only way to ·reduce the conduction losses with a 1000V MQSFET is to operate at very low current density and to use very large die areas.
In our design, one switch requires a Ron of 0.15 ohm (Tj = 25°C). That means the paralleling of 25xSTHV102 (3.5 ohms in SOT93 package) or more reasonably 5xST5MG40 (0.7 ohm in ISOTOP package).
Figure 1 : ON Resistance R(on) versus Blocking Voltage Volt.
. (die area = 1mm2 - junction temperature = 100°C). .K... on.ln.,
1 5 0 t - - - - -_ _ _;
3Ot--------f
5
2t=:~~:::::U~~
10
100
500 1000 Blocking (V)
Voltage
AN368/0689
1/5
565
APPLICATION NOTE
The gate drive presented in figure 2 provides the galvanic isolation of the drive signal and avoids auxiliary supplies.
When the signal MOSFET T1 is on, the power MOS-
FET T is on. When the signal MOSFET T2 is on, the driving transformer is short circuited and discharges the gate source capacitance of T, turning Power MOSFET T 'off'.
Figure 2 : Schematic of the Power Switch and Driver.
BYVlO-40
TOOO 060
input.
+v
rl@-t::~J:33~.7 (T2)
STHV102 (T)
Core: 76A FT 25 (LCC)
3. A CASCODE/EMITTER SWITCHING SWITCH:
50V high density Power MOSFET can operate at a current density 100 times the current density of 1000V MOSFET for the same conduction losses (typically 2A/mm2 instead of 0,02A1mm2).
The current density of a 1000V bipolar transistor is in the region of 0.4A/mm 2. For applications requiring the same current capability and the same dissipation, the 1OOOV MOSFET requires about 30 times more silicon than the equivalent bipolar solution resulting in a substantially higher power .switch cost. Bipolar transistors developed with highly interdigitated technologies such as the Easy-To-Drive tech-
nology (ETD) have a very fast fall time compatible with operation at high frequency.
Consequently a solution using a high density 50V Power MOSFET (STVHD90) and a 1000V bipolar in ETD technology (BUF420A) in cascode configuration has been developed.
The driving circuit presented in figure 3 requires only one transformer to provide the voltage control of the MOSFETand the base current of the bipolar.
When the signal MOSFET T1 is on, the power switch T is on. The turn-on of.the signal MOSFET T2 turns-off T.
2/5
566
Figure 3 : Schematic of the Cascade Switch and Driver.
BYVLO-40
APPLICATION NOTE
TOOO 061
15n
BYT13~1000
I DYW90-IOO DY.90-IO~I------+
~..
~-~~-~-Y
InF
2xD2x 15C13V
Core: 76A IT 25 (LCC)
As presented in figure 4, the cascade switch is very fast at turn-off. A Storage time less than 500ns and fall time less than 20ns have been obtained. The rate of fall of the collector current is very high (2000A/l-ls). The use of low inductance wiring methods and packages is a condition for the design of this circuit. A turn-off snubber (R, C) limits ascii la-
Figure 4 : Cascade Switching Waveforms.
tu rn-on
TOOO 062
f'\
/ \
II \
)
""-I---I-'
II 1\
/
~ h
tions and maintains the bipolar switch inside its specified Reverse Bias Safe Operating Area. The rate of rise of the collector current (dl/dt)on at turn-on is limited in the converter by the leakage inductance of the power transformer. Therefore turnon speed of the switch is not very critical. A (dl/dt)on of 50A/s has been obtained.
turn-off
TOOO 063
f' ----
r~
V
-... 1\/
I)
V t-------
Ic, Ib : 5A/div.
Vcs : 200V/div.
t : O,2I-ls/div.
3/5
567
APPLICATION NOTE
4. BIPOLAR SWITCH: The elimination of the 50V high density MOSFET is the last step to reduce the conduction losses and the number of power packages. But the remaining bipolartransistor must be driven with a negative bias on the base/emitter junction in orderto obtain fast tum-off and a blocking voltage capability extended up to VCEV. Figure 5 : Bipolar Switch and Driver.
'OV
In the circuit presented in figure 5, when T1 is on the power switch T is on. T is turned-off when T2 and T3 are on. T2 drives the negative base current of T and is turned-off after 3J.lS. T3 resets the magnetic flux in the driver transformer before the next turn-on
ofT.
TODD 064
ON
or£" (T)
~.
BUF420A
ci=:: (T3) 4700
(l~)
Core 1'6,\ IT 2~ (Lee)
BCl27
-{>- o.g
-{>- 0"
With this circuit, a BUF420A switches 20A with a storage time of 21ls and a fall time of 50ns at
Tj = 100°C, see figure 6.
Figure 6 : The Bipolar Switching Waveforms.
-I r-- h
J \
~
,
j
Ib ' 2 A Idiv Ie: 10A/div.
4/5
568
APPLICATION NOTE
5. CONCLUSION: This paper proposes different switches and drivers able to operate in AC/DC converters switching at ultrasonic frequency and directly supplied from the rectified 380/440V mains. The availability of 1OOOV MOSFET makes possible the design of switches with high frequency capability, large turn-off safe operating area, large overcurrent capability and easily controlled gate drive. A limitation of this solution is in the trade-off between the conduction losses and the current density. A medium current 1OOOV MOSFET switch needs several packages in parallel or a big heatsink. A switch developed with 1000V bipolar transistor has low conduction losses and few parallel packages. Thanks to the use of highly interdigitated very
BIBLIOGRAPHY:
(1) Transformer coupled direct base drive technology for high power high voltage bipolar transistor PWM inverter by Swanepoel, Van Wyck and Schoemen (IEEE 1987 Atlanta)
(2) Designing switched mode converters with a proportional base drive technique by J. Gregorisch
(3) Self-supplying proportionnal base drive by M. Brkovic and Z. Veljokovic (PCI 1987)
fast technology (ETD) the switching speed is comparable to the MOSFET solution. But the turn-off delay time is longer and the driving circuitry is more complex than a MOSFET circuit.
A Cascode circuit has the advantages of both bipolar and MOSFET technologies. It allows low dissipation with short turn-off delay time and simple driving circuitry. High density low voltage MOSFETs minimises the increase of the forward drop. Because of the very fast turn-off speed, special care must be taken with the wiring.
Driving circuits using only one transformer to provide the galvanic isolation power/logic and the energy to drive the power switches are also presented and adapted to each configuration of power switch.
(4) New design considerations for increasing switching frequencies in transistorized high voltage converters by P. Maugest and L. Perier (lEE Birmingham 1986)
(5) Optimized power stages for high frequency 380/440V AC medium power switch mode supplies by C.K. Patni and L. Perier (lEE London 1988).
5/5 569
APPLICATION NOTE
OPTIMISED POWER STAGES FOR HIGH FREQUENCY 380/440VAC MEDIUM POWER SWITCH MODE SUPPLIES
ABSTRACT
This paper presents the elements necessary to make the optimum choice of power semiconductors (for the transistors and secondary diodes) and the power stage configurations for medium power SMPS (from 1kVA to 15kVA).
The power stage practically realized comprises of an asymmetrical bridge forward converter. An optimised power switch combining bipolar and MOSFET technologies is developed. It is capable of switching in excess of 50A at 25kHz on the 380/440VAC rectified three phase mains.
Secondary diode choice depends largely on the transformer ratio and the desired output D.C. voltage. Conduction losses at 25kHz govern the choice of secondary diodes.
By C.K. PATNI & L. PERIER
INTRODUCTION
System designers of switch-mode solutions forelectric welders, battery chargers and computer power supplies need to choose the power-stage configuration, power semiconductors and regulation best suited for their application. This paper provides data necessary to make this choice.
Figure 1 illustrates a system block diagram of a typical medium power SMPS with the primary operating directly on the 380/440VAC rectified mains. The paper limits the discussion to the power-stage of the SMPS. Power stage configurations such as asymmetrical bridge, full-bridge and half-bridge converters are compared. Bipolar and MOSFET technologies are compared. Schottky and fast recovery epitaxial diodes are considered for the secondary rectification.
Figure 1 : Block Diagram of a Medium Power SMPS.
TOOO 002
360 VAC
>--- 440 VAC
3-Pho3e
Sufl St.art
r--------------- l
I
Tru,nstormer
Reclification
I
RccliCication
I
,----- I
· I --1I r-t-
Primary
Switch Converter
( >2SkHz)
~Ii '---
-
·
I
I I p
~ulp ul
I
II
'-----
I
Nol always neceSS6 ry
I I IL -
I
J - - - - - - - - ~-----
r---- J
'--- ~,",~"~ x",~
Switching signl1ls
-
r-----
Relullllion &
protedion
Current feedback
. - <" Low vollft'~ power sup,..hes
Voltage reedbllck
AN369/0689
1/7
571
APPLICATION NOTE
POWER STAGE CONFIGURATIONS
For medium power applications (1kVA to 15kVA), the choice of the converter on the 3-phase industrial mains is between the asymmetrical bridge, capacitor-split half-bridge and full-bridge converters [1]. The half-bridge and full-bridge converters aresymmetrical converters and thus require smaller input filtering than asymmetrical bridge converters. However, it is possible to combine two asymmetrical bridge converters operating in antiphase in order to obtain a power stage, which viewed from its input and output current waveforms, appears to be a symmetrical full-bridge converter.
The asymmetrical bridge converter (figure 2) comprises of two power switches in series with the load connected between the two switches. Simultaneous conduction of these power switches when a fault condition exists on the secondary of the transformer is not catastrophic as there is at least the leakage inductance ofthe transformer limiting the rate of rise of primary switch currents. The controlled rate of rise of primary current enables low-cost feedback protection circuits to react to the fault condition and turnoff the primary switches.
Figure 2 : Asymmetrical Bridge Converter - The Developed Power Stage.
TOOO 083
HVDC (540V DC nominal) BYTl2P[ lOOO BYV255-200
) lBV DC
~--,+----~~~
42 ~ maximum pnmary SWllch dutY-CYCle 25kHz SwilChLng frequency
HVGND
The use of turn-off switching-aid-networks (snub-
bers) does not pose a problem in asymmetrical
bridges. In half-bridge and full-bridge converters,
the use of turn-off snubbers generally necessitates
the use of turn-on snubbers required to limit the rate
,....f. VI
... ;,....,..... live:;
,...1
UI
......i.-n ........ ,
t-'IIIIIUIY
..... 'ui+,....h
~VYIL""II
""'11r-rant"" V ...... '''-'I'L....
Lr.l.J..Jl .
The developed power stage utilizes the asymmetrical bridge converter because of these reasons.
For very high output power capability (in excess of 1OkVA), the full-bridge converter can be ihe optimum choice provided the circuitry necessary to maintain volts-seconds symmetry can be easily implemented. The full-bridge operates the transformer in two magnetic quadrants. Consequently the size of the transformer can be reduced. Figure 3 illustrates a full-bridge converter which incorporates the advantages of the asymmetrical bridge structure (no
2/7 572
catastrophic simultaneous conduction of transistors and easy snubber networks) with the advantages of the symmetrical converter of reduced transformer size.
TECHNOLOGY CHO!CE
Bipolar and MOSFET technologies are best adapted for high frequency (greater than 20kHz) medium power SMPS. Fjpure 4 illustrates the on-state resistance for 1mm of silicon surface versus blocking voltage for high voltage power MOSFETs. The resistance of the epitaxial layer required to withstand blocking voltage Vas (in excess of 250V) is approximately proportional to VOS2.5. Consequently, even if this theoretical limit is approached, the on-state resistance increases rapidly as blocking voltage Vos increases for high voltage power MOSFETs.
APPLICATION NOTE
Figure 3 : A Quasi-asymmetrical Full-bridge Converter. - Transformer provides inductance between two switches in series.
TODD 084
HYDe
r- - ---------- ----,
: .1 turn
~~~~~~~
.1 turn:
~~Lo~~--r. 1
.1
1 turn
\ turn:
1
1
1
HVGIffi
n s
Trar.sfar.ne!"
LOAD
Figure 4 : MOSFET Blocking Voltage versus on-state Resistance/mm2. TOOO 085
Rd~OIl mm 2 (Ti 100'C) 150 (tog scale)
lOY
10QV
soov looav
3/7
573
APPLICATION NOTE
The current density for a 1000V bipolar transistor2 such as a BUF410A is in the region of O.4A/mm when conducting a nominal current of 1OA with an on-state collector-emitter voltage of 2V maximum at 100°C junction temperature. The equivalent onstate resistance for a 1OOOV bipolar is thus approximately S Ohm/mm 2 whereas for a 1000V Power MOSFET is 100 Ohm/mm2. For an application specifying only nominal switching current capability, the Power MOSFET solution requires 30 times more silicon than the equivalent bipolar solution (not considering the drive requirements) resulting in substantially higher power transistor cost.
Even though higher current density is achieved with bipolar transistors, the Power MOSFET has the clear advantage of a larger safe operating area at turn-off, larger peak current capability and easy voltage controlled gate drive. The 1OOOV bipolartransistor has the disadvantage of longer turn-off delay time (due to its storage time) and high drive current requirements. A cost comparison of a Power MOSFET based solution with a bipolar based solution should thus be based on cost of the switch together with its drive, protection and auxiliary power supply circuits.
Quantitative comparison is complicated by the very different operational characteristics of Power MOSFETs and bipolar transistors. However, qualitative comparison leads the authors to conclude the following:
1) In medium power SMPS, where bipolar and Power MOSFET technologies can be used, the technology comparison must be based on cost evaluation of solutions meeting the specification both for PEAK transistor switching current as well as AVERAGE/RMS transistor switching current.
2) Generally the Power MOSFET is sized for the RMS transistor switching current, whilst verifying that the peak current capability of the device meets the specification.
3) The bipolar solution is sized on the peak transistor switching current specified in the application.
THE DEVELOPED POWER STAGE
The developed power-stage has the characteristic iisteu ill table 1. Ti-,8 asynliTietrical bridge fOi"vvard converter was used with the maximum duty cycle limited to approximately 40%. The continuous rated primary current was 20A (for 40% duty cycle). The peak primary switch current capability was SOA. The transformer design (provided in appendix I) had a primary to secondary turns 'ffi/.io of 10 to 1. Consequently the continuous rated secondary output current was 200A at a secondary output voltage of approximately 18V. The secondary output peak current was SOOA when primary switch current was SOA.
Table 1 : Developed Power Stage Characteristic.
Comments
Input Supply Voltage Continuous Primary Current Peak Primary Current Maximum Duty Cycle Switching Frequency Continuous Secondary Current Peak Secondary Current Secondary Voltage (nominal)
Value
380/415/440V AC 20A 50A 40%
25kHz 200A SODA 18V
THE ASYMMETRICAL BRIDGE CONVERTER
A solution for the converter, based on bipolar and Power MOSFET technologies, encompassing the advantages of high switching current density and voltage controlled drive, was developed: this converter for the power stage was based on the CASCODE switch [3]. Due to the relatively large nominal primary switch current (20A), a bipolar based solution was necessary. The CASCO DE switch required a simple voltage controlled drive signal. No floating auxiliary supplies were required as the base current for the bipolar transistor was provided by a proportional current transformer. Figu re S illustrates the primary CASCODE switch (based on bipolar and MOSFET technologies) which is used in the asymmetrical bridge converter.
The switch comprises of a BUV298A bipolar transistor (B1 lin ISOTOP package and a high density SOV (23 mOhm at 2S°C) Power MOSFET STHVD90 (F1) connected in CASCODE. A 1000V Power MOSFET STHV102 (F2) provides the initial base current. A SOV Power MOSFET BUZ11 (F3) turnson when the STHVD90 CASCODE MOSFET (F1) is turned-off. Consequently the collector current is extracted via the base through Power MOSFET F3. A turn-off snubber (comprising of R1, 01 and C1) maintains the turn-off within the reverse bias safe operating area (RBSOA) of the bipolar BUV298A.
The primary switch conduction losses (at nominal 20A current for 40% duty cycle) are approximately 30W at a 100°C junction temperature tor the CASCODE switch. The primary switch could be based purely on 1000 volts Power. MOSFETs (STHV102, 3.S ohm at 2S0C) in parallel. However, for 1.0 of these Power MOSFETs in parallel, under the same operating condition, the conduction losses would be approximately 90W.
Figure 6 illustrates a pulse transformer gate drive used with the primary switches. This gate drive provides positive and negative bias of the Power MOSFETs in the CASCODE switch. The pulse
4/7 S74
APPLICATION NOTE
transformer also provides the isolation between the drive, the asymmetrical bridge converter requires no primary switches and the control logic. With this gate . auxiliary power supplies. Figure 5: The Developed CASCODE Asymmetrical Bridge Converter.
TODD 087
"602F
g:~ polY]lrtlpylene
Figure 6 : Isolated Pulse Transformer based Gate Drives for Power Stage. TODD 086
-t 12V
10 tUrns
HJ4148
:.wu
10 turns
5/7
575
APPLICATION NOTE
ASYMMETRICAL BRIDGE OPERATION
Figure 7 illustrates the extremely fast switching and shart (less than 500ns) starage time at turn-aff abtained using this CASCODE switch. The primary switch was tested with a bridge high valtage DC rail af 600Vac, primary current af 50A at 25kHz switching frequency.
Figure 7: CASCODE Primary Switch Cammutatian - (I PEAK = 50A).
Figure 8 : Secandary Diade Switching Waveforms.
Vo I :::; 20V /div
10 = 50A!div Ves
t::: lps/div
lB:: lOA/div
Ves:: ZO(]V!div
'e :: 20A/div
SECONDARY RECTIFYING DIODES
The transformer had a primary to. secandary turns ratio. af 10 to. 1. Cansequently the valtage experienced by the secandary diades at 600Voc HVDC was . 60V in additian to. any avervaltage due to. parasitic inductances.
Schattky diades which have extremely law canductian valtage (appraximately O.4V) can nat be used far this applicatian as they are limited in blacking vo.ltage to. appro.ximately 50V. If the seco.ndary o.utput valtage was 5V (far example, camputer applicatians), the transfarmer ratio. wauld have. been higher thus permitting the use af Schattky diades.
The diades best suited far the specified secandary
autput are fast recavery epitaxial diades ('FRED').
FRED diades BYV255V200 were used in the circuit
havinQ canductian valtages af approximately 0.85V
at rated current and at 125°C junctian temperature.
Figure 8 illustrates the blacking valtage experienced
by the secandary diades with resistor/capacitar
snubber netwarks.
.
At cantinuaus rated autput pawer, each secandary di.ode canducts far approximately 50% af the time an average current af 100A. Assuming a junctian temperature af 125°C, the instantaneaus farward valtage drop is 0.85V at approximately 100A. Hence di.ode co.nductian lasses are approximately 85W ; (0.85Vx100A= 85W).
6/7 576
VOl::: 20V/div 10'::- 50A/div
APPLICATION NOTE
The leakage inductance between primary and secondary of the transformer is generally large such that the rate of decay of current in these diodes is controlled. Hence the reverse recovery is not critical. Thus at 25kHz switching frequency conduction losses are the prime criteria forthe choice of the secondary diodes.
CONCLUSION
Bridge converters for medium power SMPS(1 kVA to 15kVA) have been discussed. Turn-off snubbers and low-cost protection circuitry can be used with asymmetrical converters. A quasi-asymmetrical fullbridge converter has been proposed for high power SMPS which operate the transformer in two magnetic quadrants.
The 1000V Power MOSFET is a well adapted choice for low continuous power SMPS especially when high pulse current capability is specified for the primary switch. Bipolartransistors have high current density and are better adapted for medium powerSMPS.
The choice of secondary diodes at 25kHz switching frequency is based primarily on conduction losses.
The developed power stage utilized the CASCODE configuration for the primary switch. This solution had the advantages of both the bipolar and Power MOSFET technologies. Fast epitaxial rectifying diodes (FRED) have been used in this power stage.
REFERENCES
1. SGS-THOMSON Microelectronics, 1984, "Transistor and Diodes in Power Processing", 187198.
2. SGS-THOMSON Microelectronics, 1978, "The Power Transistor in its Environment", Chapter 8, 181-206.
3. Robinson F. and Williams B.w., 1987, "Emitter Switching High-Power Transistors", EPE Conference, 55-59.
ANNEX I
TRANSFORMER DESIGN
The transformer design parameters for the developed asymmetrical bridge forward converter are:
VMIN = 500Voc
VMAX = 600Voc
VOUTPUT = 18V
IOUTPUT =200A
Duty cycle = 0.4 (MAX)
Freq. (f) = 25kHz
For forward converter operation equation [1] pro-
vides an approximate practical method of calculating the ferrite cross-sectional area.
S = K VVOUTPUT.loUTPUT = 900mm2
[1]
S = cross-sectional area in mm2
VOUTPUT = Output secondary voltage
IOUTPUT = Output secondary current
K = 15 (for B50 ferrite material).
Two GER65/33/27 (LCC) E shape B50 ferrites were sandwiched together to form a ferrite core crosssectional area (S) of 1064mm2.
Minimum number of primary turns (Np) can be calculated using equation [2].
VMAx.Duty cycle
Np>
> 36
[2]
BMAx.S.f
Np was made equal to 40.
The number of secondary tums can be calculated using equation [3].
VOUTPUT.Np
Ns = -----~> 3.6
[3]
VMIN.Duty cycle
Ns was made equal to 4. Hence the primary to secondary tums ratio was 10 to 1. Consequently peak primary current (20A) was one tenth of 200A secondary current.
The primary RMS current can be calculated using equation [4].
V IRMS = IPEAK. \/Duty cycle = 20 0.4 = 12.5A [4]
Using a current density of 5Nmm2, the primary was
wound using two wires in parallel of 1.25mm diameter.
The secondary wire cross-sectional area was 20mm2 calculated in a similar manner as for the pri-
mary wire.
MEASURED PARAMETERS
Leakage inductance = 90llH (secondary short-circuited)
Primary inductance = 17.5mH
Insulation material used between primary and secondary was capable of supporting 1500VAC at 50Hz. Three pieces of 0.65mm plastic film were used for this isolation.
7/7 577
APPLICATION NOTE
TEA2260 ! TEA2261 HIGH PERFORMANCE DRIVER CIRCUITS FOR S.M.P.S.
SUMMARY
Page
INTRODUCTION . ..................................................... . 2
1.1
MASTER SLAVE MODE ................................................ . 2
1.2
BURST MODE ....................................................... . 3
1.3
OPERATION OF MASTER SLAVE POWER SUPPLY IN TV APPLICATION ........ . 3
1.4
SECONDARY REGULATION ............................................. . 6
1.5
PRIMARY REGULATION ............................................... . 8
II
CIRCUIT DESCRIPTION ............................................... . 9
11.1
VOLTAGE REFERENCE AND INTERNAL Vcc GENERATION .................. . 10
11.2
OSCILLATOR ........................................................ . 10
11.3
ERROR AMPLIFIER ................................................... . 12
11.4
PULSE WIDTH MODULATOR ........................................... . 12
11.5
SOFT START OPERATION ............................................. . 13
11.6
BURST GENERATION IN STAND BY ..................................... . 13
11.7
IS LOGiC ............................................................ . 13
11.8
SAFETY FUNCTIONS: DIFFERENCES BETWEEN TEA2260 AND TEA2261 ...... . 15
11.8.1 I max ............................................................... . 16 11.8.1.1. First threshold VIM1 ................................................. . 17 11.8.1.2. Second threshold VIM2 for TEA2260 .................................... . 18 11.8.1.3. Second threshold VIM2 for TEA2261 .................................... . 18 11.8.2 Logical block ......................................................... . 18 11.8.2.1. Logical block for TEA2260 ............................................ . 18 11.8.2.2. Logical block for TEA2261 .............. , ............................. . 19
11.9
OUTPUT STAGE ...................................................... . 19
III
TV APPLICATION 120W 220 VAC 16KHz SYNCHRONIZED .................. . 20
111.1
CHARACTERISTICS OF APPLICATION ................................... . 20
111.2
CALCULATION OF EXTERNAL COMPONENTS ............................. _ 20
111.2.1 Transformer calculation ................................................. . 21 111.2.1.1 Transformer specification ............................................. . 22 111.2.2 Switching transistor and its base drive ..................................... . 23 111.2.2.1 Current limit calculation ............................................... . 23 111.2.2.2 Snubber network .................................................... . 23 111.2.2.3 Base drive ......................................................... . 24 111.2.3 Oscillator frequency ................................................... . 25 111.2.4 . Regulation loop ....................................................... . 26 111.2.5 Overload capacitor .................................................... . 27 111.2.6 Soft start capacitor .................................................... . 27 111.2.7 Feedback voltage transformer ........................................... . 28 111.2.8 Start up resistor ....................................................... . 28 111.2.9 High voltage filtering capacitor ........................................... . 29
111.3
ELECTRICAL DIAGRAM ............................................... . 30
AN376/0691
1/34
579
APPLICATION NOTE
SUMMARY (continued)
Page
IV
TV APPLICATION 140W 220 VAC 32kHz SYNCHRONIZED " " " " " " " " " " 31
IV.1
APPLICATION CHARACTERISTICS ...................................... . 31
IV.2 TRANSFORMER CHARACTERISTICS ..................................... 31
IV.3
ELECTRICAL DIAGRAM ....................................... , ....... . 32
V
TV APPLICATION 11 OW 220 VAC 40kHz REGULATED BY OPTOCOUPLER . . . . . . 33
V.1
FREQUENCY SOFT START. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
V.2
APPLICATION CHARACTERISTICS ....................................... 33
V.3
TRANSFORMER SPECIFICATION ........................................ 33
VA
ELECTRICAL DIAGRAM
34
I. INTRODUCTION
The TEA2260/61 is an integrated circuit able to drive a bipolar transistor directly with an output base current up to 1.2A. So .the TEA 2260/61 covers a wide range of application from 80W to more than 200W with all safety requirements respected. The high performances of the regulation loop provide a very low output power due to an automatic burst mode. The TEA 2260/61 can be used in a MASTER SLAVE STRUCTURE, in a PRIMARY REGULATION or a SECONDARY REGULATION. The TEA 2260/61 is very flexible and high performance device with a very large applications field. The only difference between TEA2260 and TEA2261 concerns security functions (see paragraph 11.8)
1.1. MASTER SLAVE MODE (fig.1)
In this configuration the master circuit located on the secondary side, generates PWM pulses used for output voltage regulation. These pulses are sent via a feedback transformer to the slave circuit (Fig.1 ). In this mode of operation, the falling edge of the PWM Signal may be synchronized with an external signal. By this way the switching off time of the power transistor, which generates lot of parasites, can be synchronized on the line fly back signal in TV applications. An other advantage of the MASTER SLAVE STRUCTURE is to have a very good regulation not depending of the coupling between transformer primary and secondary windings, which allows the use of low cost switch mode transformers.
Figure 1.
ISync.
Pulses
n
h PWM
Signal
I
I
n ~
II
I
I
..
Pulse Inpul
b
h
Base Current _ _ _
V
D ..
b ~
V90TEA2260/61·01
--------------------------- 2~/~34----------------------- ~~~~~~~,,?~
580
APPLICATION NOTE
1.2 BURST MODE (fig.2) During start-up and stand-by phases, no regulation pulses are provided by the master circuit to the slave circuit. The slave circuit operates in primary regulation mode. When the output power is very low the burst mode is automatically used.
Figure 2 : Burst Mode Operation.
This operating mode of the SMPS effectively provides a very low output power with a high efficiency. The TEA2260/61 generates bursts with a period varying as a function of the output power. Thus the output power in burst mode can varied in a wide range from 1W to more than 30W.
I"
Burst Period typ:::30ms
"'1
1
1
1
1
1
1
1
1
-,
~ Switching
1
Period
1
1
1
COLLECTOR CURRENT ENVELOP
DETAIL OF ONE BURST V90TEA2260/61·02
1.3. OPERATION OF MASTER SLAVE POWER SUPPLY IN TV APPLICATION The system architecture generally employed is depicted in Fig.3. On the secondary side a micro controller is connected to the remote control receiver which generates control signal for the standby and normal modes of operation (FigA).
· In stand-by mode, the device power consumption is very low (few watts). The master circuit does not send pulses and hence the slave circuit works in primary regulation and burst mode.
o In the normal mode, the master circuit provides the PWM signal required for regulation purposes. This is called MASTER SLAVE MODE. The master circuit can be simultaneously synchronized with the line flyback signal.
· Power supply start-up. As soon as the Vcc(start) threshold is reached, the slave circuit starts in cor1tinuous mode and primary regulation as long as the nominal output voltages are not reached . After this start-up phase the microcontroller holds the TV Set in stand-by mode or either in normal mode.
-------------- ~ ~~~~~~]m~~:R~ --------------3/34
581
W ((1X1l 1-1>
I\)
-I>
~
~cn
"©,'U"'I
!i1:liio!
"iii:
;!U:!~I
<
(0
o
-m-l ~
~''""
6
'"
AUDIO OUTPUT STAGE
Muting Control
Remote Stand-by
Remote Stand-by
."11
cO" c
CD
l> 1:1
"rt-I
Col
5
--;
» <
l> -I
0
--0
Z
~
6-
Z
~.
0 ::J
0
-mI
(J)
"r<a-
ro 3
0 0;-
(0
ill 3
~P
~PWM
INFRA-RED RECEIVER
'iJ Small signal primary ground ~ Power primary ground CJ Secondary ground (isolated from mains)
I:!!
IC I:
iil
",.
r-------~/r---------~
(J)
'<
TEA2260/61
(IJ
CD
Vee voltage
I"
:3
o
VCC(STOP) :
Collector current envelop
1
n::
I
n
n
n
i
n rI ~------~/"I ~------~
~
n
n
· t
(\J (IJ
-Qs:
6'
:::J
.t I a(\J
3
~
~CII
©n
Output voltage
1
",CII
i:
~
_,
~~
I:B::C
I
I
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~~
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t
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@
;~;p~s:u:-p:pyly
: :
: i
I I
I
I
:
· t
:
~I i @ l i i 1,...1- - - - - - - - - r - - - - - - - - - - - - - - - i - - - - - - G) j
control _ voltage
~.
. ·t t
l>
"C "C
I
I t 1
Normal operation
I 2
at<-o;
I
Start-up
Stand-by
i--
"I"
"I'"
I I 17
,Stand-by
"I·
If-
/
o r
~
I~ (]I
(Xl
w
» m
''m""
· t 1 and t 2 : commands issued by ~p
~
I~
5 z z ~ m
APPLICATION NOTE
1.4. SECONDARY REGULATION (fig.5, 6) In this configuration the TEA2260/61 provides the regulation through an optocoupler to ensure good accuracy. The advantage of this configuration is the avaibility of a large range of output power variation (e.g 1W to 110W).
Figure 5: TV Application System Diagram.
This feature is due to the automatic burst mode (see paragraph 11.6). The structure in a TV Set is simpler than the MASTER SLAVE STRUCTURE because the power supply switches from normal mode to burst mode automatically as a function of the output power.
0W0w: 0:> <i:Ui 0:0
~w
<::0:
V90TEA2260/61·05
- - 6/34 - - - - - - - - - - - - ~ ~~~(~)mg~~2c~ - - - - - - - - - - - - - -
584
"T1
<C' c
iil
Cl
(f)
- TEA2260/61 b6LVc;c;(~~I
Vcc vollage
I I
'Ui
CD 3
-
I VCC(STOPI
:
I
~ I
o
CD Ul
Colleclor current envelop
1
:: i
~ I
n n n (I~'
n n n 1'//-'-------1
Q
~ 0'
OJ
~
~I
~
CD
0'
~
",en
l!t;:
Output voltage
1
'~:i!
~o
§Ja::
!i~
~z
Stand-by voltage
1
:v::
I
I I
I
: I
I
7//I
h~'----------~
3
~ · I
envelop
r CD ~p supply
Ii/~1:I : -------r-----------r-----
~ I
vollage
I I
»
"C
<
I.
Start-up
· 1·
<0
0
-m-i
~
''0"">
· I 1 and I 2 : commar:ds issued by ~p
Sland-by
II t 1
~ 1
Normal operalion //
II t 2
~ 1·
Sland-by
,If-
o"rC-
~
(5
Z
Q
~
I~ (11
00 (11
Ig
o Z
m-I
APPLICATION NOTE
1.5. PRIMARY REGULATION (fig.7) In this configuration the TEA2260/61 provides the regulation through an auxilliary winding. This structure is very simple but the accuracy de-
Figure 7: TV Application System Diagram.
pends on the coupling between the transformer primary and secondary winding. Due to the automatic burst mode the output power can vary in a large range.
a:
8 >
t---C::::J----4---li!----t~
t----jl---,--------------··~-
V90TEA2260/61·07
8-/3-4 --------------~~~~~~~~~~?~~ - - - - - - - - - - - - - - - -
586
S
ERROR AMPLlFLIER
l
VREF
2.49V
WffiEMt
~
i'iSUI
~n
~'f
;'J:i!
~O
~3::: ""©",OU2I
<
(0
m»0--<
''e""n
m 0
I~ 01
(Xl
-.&
I~
Ro Co
Vcr.
V+
i~----------------------------~
Vee MONITORING
LJ
l.4V 10,3V
OVERVOLTAGE PROTECTION
PRIMARY PULSES
I I REGULATION
IS
PULSES
'LOGIC
'
LOGIC PROCESSOR
O_15VT
iR'
SECONDARY PULSE
IS IN
C2
I MAX
GND
1:::!1 -n= to 0'· c: c: (") CD CD Jj
(Xl (Xl (")
· en C
15"=t :eEnmC -~(e"n)
_. JJ
g-::J"::t:- !I
010 co- Z
Cl.
C
n-::J
6-
::J
V'
l>
"C
"rCc=;
~
(5
Z Z
S m
APPLICATION NOTE
The circuit contains 8 blocks: · Voltage reference and internal Vcc generation. · RC oscillator · Error amplifier · Pulse width modulator (PWM) · "Is logic" for transformer demagnetization
checking. · Current limitation sub-unit (IMAX) · Logical block. · Output stage.
11.1. VOLTAGE REFERENCE AND INTERNAL Vcc GENERATION (fig.9) This block generates a 2.5 V typo voltage reference
Figure 9 :Voltage Reference Block Principle.
valid as soon as Vcc exceeds 4V. IHs not directly accessible externally but is transmitted to other blocks of the circuit. This block also generates an internal regulated Vcc, VCC(int), the nominal value of which is 5V. VCC(int) supplies the circuit when Vcc is higher than VCC(start) (1 O.3V typ;). This allows the circuit to achieve a good external Vcc rejection, and to provide high performance even with large Vcc supply voltage variations. This block also generates initialization and control sig nals for the logical block. It also contains the VCC(Max.) comparator (typ threshold 15.7V).
r-----------~~------~16r_------~----_.
Vee
lS.7V
Vee MAX
V2re.S! V
<J --
-----..._-----4-------,
RESET SIGNAL .-----./ RESET f - - - - - l GENERATOR
11.2. OSCILLATOR (fig 10,11) The osciilator determines the switching frequency in primary regulation mode. Two external compo-
Figure 10 Operating Principle.
V90TEA2260161·09
nents are required: a resistor Ro and a capacitor Co. The oscillator generates a sawtooth signal, which is available on pin 10.
- - - - - - - - - - - - - - - - Vee int (5V)
Vref+Vd
Vd diode threshold voltage Ro
leh ~
'"Idiseh 2KO
cor
Q
2/3 Vee int 1/3 Vee int
V90TEA2260161-10
-10-/3-4------------------------~~~~@~~~~~~ ---------------------------
588
APPLICATION NOTE
Co capacitor is charged with a constant currerit. The current is fixed by Ro which is supplied by voltage Vref.
Ich = 2.5 Ro
When the voltage across Co reaches
"32
.
X VeCint (typ 3.33V), Q TranSistor conducts and
Co is quickly discharged into an 2kQ (typ) internal resistor. When the voltage reaches 1/3 x Vec· int (typ 1.66V), the discharge is stopped, and the linear charge starts again.
Figure 11 : Sawtooth available accross Co.
J.JJV ------------------------
I
I
I
I
I
I
I
I
I
I
. i 1 6~ - - ---------------------~---- - - - - - - - - - -
T 1
I T2 I
~-----------T--------t--~
~------------------------~
V90TEA2260/61·11
Theoretical values of T,T1 and T2 as function of Ro and Co: T = Co (0.69 x Ro + 1380) T1 = Ro x Co x 0.69
T2 = Co x 2000 x 0.69 = Co x 1380
Due to the time response of comparators and normal spread on thresholds values, the real values ofT1 and T2 may be slightly different, compared with these theoretical values. (see following curves).
Figure 12: Frequency as a Function of Ro and Co.
Fa
9 8 7 6
5
3 2
10KHz IOkO
5 6 7 8 9 lOOK
150K
2
Ra
V90TEA2260/61·12
---------------------------- ~~~~~~g~~~~~ -------------------------1-1-/3-4
589
APPLICATIOfli NOTE
11.3. ERROR AMPLIFIER (fig.13)
It is made of an operational amplifier. The open loop gain 'is typically 75dB. The unity gain frequency is 550kHz (typ). An internal protection limits the out-
put current (pin 7) at 2mA in case 01 shorted to
ground.
Output and inverting input are accessible thus
giving high flexibility in use. The non-inverting input
is not accessible and is internally connected to
VREF (or 0.9 VREF in burst mode - see paragraph
11.6)
,
Before drJving the pulse width modulator (PWM) and in order to get ttie appropriate phase. the error amplifier is followed by an inverter.
Figure 13.
v,ef~ -1
E: ERROR SIGNAL
-~------ ------ 6
7 -----
E
S
V90TEA22M/61-13
11.4. PULSE WIDTH MODULATOR(PWM)(fig.14) The pulse width modulator consists of a comparator fed by the output signal of the error amplifier and the oscillator output. Its output is used to generate conduction signal.
Figure 14.
error ~a _ n..rL sawtooth~
NVI
V90TEA2260/61-14A
TON MAX .vOL TAGE SAWTOOTH (p;n 10)
The TEA2260/61 actually integrates two PWM.:
· A main PWM generates a regulation signal (oc) by comparing the error signal (inverted) and the sawtooth.
· An auxiliary PWty1 generates a maximum duty cycle conduction signal (~), by comparing the sawtooth with an internal fixed voltage. Furthermore, during the starting phase of the SMPS, in association with an external capacitor, thispWM generates increasing duty cycie. thus allowing a "soft" start-up.
· A logic "AND" between signals (oc) and (~) provides the primary regulator output signal TA.
Figure 15.
L V90TEA2260/61-14B
"TON MAX"
<~" error
(inverted) I\N
V90TEA2260/61-15
1-2-/3-4------------------------~~il@~~~~1 ---------------------------
590
"
APPLICATION NOTE
11.5. SOFT START OPERATION (fig.16) From t1 to t2, there is no output pulse (pin 14) and C1 is charged by a 180flA current (typically). When C1 voltage reaches 1.5V (typically), output pulses appear and the charge current of C1 is divided by 20 (9flA typically), then the duty cycle increases
Figure 16 : C1 Voltage (Pin 9).
2.7v-
progressively. When C1 voltage reaches 2.7V (typically), the soft-starting device ceases to limit the duty cycle, which may reach 60% Under established conditions C1 voltage is charged to 3.1 V (typically)
~..,.-------- 3.1V
1.5v - - - - -
MIN
V90TEA2260/61-16
11.6. BURST GENERATION IN STAND BY (primary regulation mode)
When the SMPS output power becomes very low, the duty cycle of the switching transistor conduction becomes also very low. In order to transmit a low average power, while ensuring correct switching conditions to the power transistor, a "burst" system is used for energy transmission in stand by mode.
Principle: For a medium output power (e.g. more than 10W), the voltage reference is applied to the non- inverting input of the error amplifier. When output power decreases as the minimum conducting time of the power transistor is reached, the output voltage tends to increase. Consequently the error signal applied to the PWM becomes higher than the sawtooth. This is detected by a special logic and the voltage applied to the non inverting input becomes
Vref = 0.9 x 2.5 = 2.25V typically.
Consequently the regulation loop is in an overvoltage equivalent state and the output pulses disappear. The output 'voltage decreases and when it reaches a value near 0.9 times the normal regulation value, the voltage applied to the non inverting input is switched again to the normal value
VREF = 2.5V. Pulses applied to the power transistor
reappear, the output voltage increases again, and
so on ... A relaxation operation is obtained, generating the burst. Futhermore, to avoid a current peak at the beginning of each burst, the soft-start is used at this instant.
Advantages of this method: .. improved power supply efficiency compared with
traditional systems, for low power transmission. .. automatic burst-mode continuous mode transi-
tion, as a function of the output power. D high stand-by power range. D burst frequency and duty cycle adjustable with
external components to the circuit.
11.7. IS LOGIC (fig.17) During the transition from the "stand-by" mode to the "normal operating" mode, conduction pulses generated by the secondary regulator occur concurrently with those from the primary regulator. These pulses are non-synchronous and this may be dangerous for the switching transistor. For example if the transistor is switched-on again during the overvoltage phase, just after switching-off, the FBSOA may not be respected and the transistor damaged. To solve this problem a special arrangement checking the magnetization state of the power transformer is used.
- - - - - - - - - - - - - - - ~~~~~~~~~~~~~ -------------~ 13/~ 34 591
APPLICATION NOTE Figure 17 : IS Logic Principle Schematic.
Vee in! (5V) IN
IS
TA PRIMARY REGULATION SIGNAL
IS
TB
LOGIC
Is
The aim of the IS Logic is therefore to monitor the primary regulation pulses (TA) and the secondary regulation pulses (pin 2), and to deliver a signal TB compatible with the power transistor safety requirements. The IS Logic block comprises mainly two D flipflops. Figure 18.
V90TEA2260f61-17
When a conduction signal arrives, the corresponding flip-flop is set in order to inhibit a conduction signal coming from the other regulation loop. Both flip-flops are reset by the negative edge of the signal applied to the demagnetization sensing input (Is Pin 1).
PRIMARY PULSES (TEA226D)
SECONDARY PULSES (TEA517D)
VCE VOLTAGE
IS INPUT (PIN 1)
D 1 , I I
0,
,I "
I I"I
0
I
I
I
I
I
I
I
I
I I
I
H[Y CY[L I I I I II I II
I
I II
I
"
I II I ,I
I I I I I I I I I I I
I I I I I I I I I
I
J I I 1I I I II I I I
I I
0 ~
,I"I I
II I II I II I II I II I II I
II I
I I
I I
I
OD[jN ~ II I
I I
I I
I
I I
I
I I
I
I I
I
I I
I
I
I I
[Lt,
IC PRIMARY CURRENT
PRIMARY REGULATION
Note :The demagnetization checking device just described is only active when there are concurrently primary and secondary pulses, which in practice only occurs during the transient phase from
SECONDARY REGULATION
V90TEA2260f61-18
Stand-by mode to normal mode. When the power supply is in primary regulation mode or in secondary regulation mode, the demagnetization checking function is not activated.
-14-/3-4----------------------------~ ~~~~~~~~~~~~ -------------------------------
592
APPLICATION NOTE
11.8. SAFETY FUNCTIONS: Differences between TEA2260 and TEA2261
TEA2260 : Concerning the safety functions, Vcc(max) (overvoltage detection) VIM1, VIM2 (overcurrent detection) the TEA2260 uses an internal counter which is incremented each time Vccstop is reached (after
Figure 19: TEA2260 Safety Functions Flowchart.
fault detection) and try to restart. After 3 restarts with fault detection the power supply stops. But in certain cases where the TV set is supplied for a long time, without swich off, the power supply could stop (cases of tube flashes). In this case it is necessary to switch off the TV set and swich on again to reset the internal counter.
--------------
~First
y
.:: threshold reached _'_ , __
··············l·········
-------=-~
y ~hre~sehcoonldd__r_e_~c_h_e.d."'--> VI~ N
Vccmax reached
y VC2 < 2.6V
Restart number = 3
N >'-'-------"
Reset C2
N
discharged
y
TEA2261 :
The safety detections are similar to TEA2260 for Vcc(max) (overvoltage detection) VIM1, VIM2 (overcurrent detection), but each time a fault detection is operating the C2 capacitor is loaded step by
V90TEA2260/61-19
step up to 2.6V, (case of long duration fault detection) and the power supply stpos. To discharge C2 capacitor it is necessary to switch off the TV set and to switch on again and the power supply starts up.
593
APPLICATION NOTE Figure 20 : TEA2261 Safety Functions Flowchart.
First
y
threshold reached
VIMt
N
Vccmax
y
reached
.Second threshold reached
N
VIM2
VC2 < 2.6V
y
VC2 < 2.6V
y
N
Reset C2 discharged
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~y
11.8.1. I MAX (power transistor current limitation) The current is measured by means of a resistor inserted in the emitter of the power transistor. The voltage obtained is applied on pin 3 of the TEA2260/61 . The current limitation device of the TEA2260/61 is a double threshold device. For the first threshold, there is no difference between the two devices, only for the second threshold.
Figure 21. , - - - - "1
TEA2260 ----~-----~
V90TEA2260/61-20
POWER TRANSISTOR RS
V90TEA2260/61-21
-16-/-3-4--------------------------- ~ ~~~~~g~~J?~~
594
APPLICATION NOTE
11.8.1.1. First threshold: VIM1 (typical value)
$ Figure 22 : Current Limitation Schematic Principle. First Threshold Part.
I VCCint(5V)
Logic part pulse by pulse
CHARGE CURRENT
limitation 11
I CH
I MAX
2.6V
TO LOGICAL BLOCK
V90TEA2260/61-22
Two actions are carried out when the first threshold is reached · The power transistor is switched-oil (pulse by
pulse limitation). A new conduction pulse is necessary to switch-on again.
· The C2 capacitor, which is continuously discharged by Idisch current (1 GilA typically), is charged by the current Ich - I disch (451lA - 1GilA = 351lA typically), until the next conduction pulse.
Figure 23 : Example of First Current Limitation Threshold Triggering.
Conduction pulse
I
I
VIM1
IMAX Voltage (pin 3)
Output current (pin 14)
C2 Capacitor current (pin 8)
The capacitor C2 is charged as long as an output overload is triggering the first current limitation threshold. When the voltage across C2 reaches the threshold VC2 (typically 2.55V), output pulses (pin 14) are inhibited and the SMPS is stopped. Arestart may be obtained by decreasing Vcc under the VCC(stop) threshold to reset the IC.
V90TEA2260/61-23
If the output overload disappears before the voltage across C2 reaches VC2, the capacitor is discharged and the power supply is not turned off. Due to this feature, a transient output overload is tolerated, depending on the value of C2 (see 111.2.5).
----------------------------
~~~~~~~~~~~~~
17/34
----------------------------
595
APPLICATION NOTE
11.8.1.2. Second current limitation threshold (VIM2) for TEA2260 In case of hard overload or short circuit, despite the pulse by pulse current limitation operation, the current in the power transistor continues to increase. If the second threshold VIM2 is reached, the power supply is immediately turned off and the internal counter is incremented. After 3 restarts, the power supply is definitively stopped. Restart is obtained by decreasing Vcc below VCC(stop), as in the case of stopping due to the repetitive overload protection triggering.
11.8.1.3. Second current limitation threshold (VIM2) for TEA2261 For this device, if the second threshold is reached, the power supply is turned off, C2 is charged and a new start-up is authorized only if VC2 < 2.6V.
11.8.2. LOGICAL BLOCK: This block receives the safety signals coming from different blocks and inhibits the conduction signals when necessary.
11.8.2.1. Logical block for TEA2260
Figure 24 : TEA2260 Simplified Logical Block Diagram.
TC
Vee (reset) - - - - + - - - - - - - - '
V90TEA2260/6t -24
TB
is the conduction signal (primary or sec- These three signals VC2, 12, VCC(Max.) are memo-
ondary)coming'from the Is logical
rized by 82.
block.
In case of B2 flip-flop setting (12 or VC2 or VCC(Max.)
defect) the current consumption on Vcc increases.
TC
is the conduction signal transmitted to
This function allows to decrease the Vcc voltage
the output stage.
until VCC(stop). After this the current consumption on
Vcc decreases to ICC(start) and a new start up is
is the output signal of the first current lim- enabled.
itation threshold comparator. It is
memorized by the flip-flop-Bt.
12
is the output signal of the second current
limitation threshold comparator
VC2
is the output signal of the comparator
checking the voltage across C2.
VCC(Max.) is the signal coming from Vcc checking comparator.
The VCC(Off) signal comes from the comparator checking Vcc. A counter counts the number of VCC(off) establishment. After four attempted starts of the power supply the output of the circuit is inhibited. To reset the circuit it' is necessary to decrease Vce below 5.5V typically. .In practice this means that the power supply has to· be disconnected from the mains.
- - - - - - - - - - - - - - -18/-34------------~~~~©~g~:~©'
596
1I.8.2.2.Logical block for TEA2261
Figure 25.
----"'-'-EOR }-~S
VCC(Max)--
5L
~ --+-<"--1 ~ --+---IR
APPLICATION NOTE
--R RESET
Vcc(off) is a signal coming from a comparator checking Vcc. When Vcc > Vcc(stop),VcE(off) is high. Vcc(max) is a signal coming from a comparator checking Vcc. When Vcc > Vcc(max),Vcc(max) is high.
h is a signal coming from the first current limitation
threshold comparator: When Imax x RSHUNT > VIM1, 11 is high. 12 is a signal coming from the second current limitation threshold comparator.
Figure 26.
V90TEA2260/61-25
When Imax x RSHUNT > VIM2,12 is high.
TB is the conduction signal coming from the error
ampliflier system. TC is the output signal transmitted to the output stage.
11.9. OUTPUT STAGE
The output stage is made of a push-pull configuration : the upper transistor is used for power transistor conduction and the lower transistor for power transistor switch-off.
TC
V90TEA2260/61-26
A capacitive coupling is recommanded in order to provide a sufficient negative base current through the power transistor .
-------------------------
~~~@~~~~~~
19/34
----------------------------
597
APPLICATION NOTE
Figure 27 : Typical Voltage Drops of Output Transistor versus Current.
(v) volt~ge dr"op
----T1 -T2
1 - - - - - - - -----=~~
---
-
I
: I
I
I
I
I
I
:
power transistor
~~~~~~~I~~~~~~c~ol~lec~to~,~c~u,_,e~n~t (A)
V90TEA2260/61-27
Important remark : Due to the internal output stage structure, the output voltage (Pin 14) must never exceed 5V. This condition is respected when a bipolar transistor is driven_ Note that Power-MOS transistor drive is not possible with the TEA2260/61.
III. TV APPLICATION 120W - 220 VAC -16 kHZ SYNCHRONIZED ON HORIZONTAL DEFLECTION FREQUENCY
General structure and operational features of this power supply were outlined in section I. The details covered below apply to a power supply application using the master circuit TEA5170. (refer to TEA5170 data sheet and TEA5170 application note "AN088" for further details)_
III.1_ CHARACTERISTICS OF APPLICATION · Discontinuous mode Flyback SMPS · Standby function using the burst mode of
TEA2260/61 · Switching Frequency
- Normal mode: 15.625 kHz (synchronized on - horizontal deflection frequency) - Standby mode: about 16 kHz · Nominal mains voltage: 220 VAC · Mains voltage range: 170 VAC to 270 VAC · Nominal output power: 120W · Output power range in normal mode 14W < Po < 120W · Output power range in standby mode 1W<Po<25W · Efficiency - Normal mode: 85% (under nominal conditions) - Stand by mode: 45% · Regulation performance on high voltage output : 140 VDC
- ± 0.3% versus mains variations of 170 VAC to
270 VAC (POUT: 120W)
- ± 0.5% versus load variations of 14W to 120W (Vin = 220 VAC)
· Overload protection and complete shut down after a predetermined time interval.
· Short circuit protection. · Open load protection by output overvoltage de-
tection · Complete power supply shut-down after 3 re-
starts resulting in the detection of a fault condition for TEA2260. · Complete power supply shut-down when VC2 reaches 2.6V for TEA2261.
111.2_ CALCULATION OF EXTERNAL COMPONENTS Also refer to TEA5170 application note "AN408/0591" for calculation methods applicable to other power supply components.
The external components to TEA2260/61 determine the following parameters: · Operating Frequency in primary regulation · Minimum conduction time in primary regulation · Soft start duration · overload duration · Error amplifier gain and stand-by output voltage · Base drive of the switching transistor · Primary current limitation
Ideal values: · Free running Frequency in stand-by mode:
16kHz · TOn(min) duration: 11ls · Soft start duration: 30ms · Maximum overload duration: 40ms · Error amplifier Gain: 15 · Maximum primary current depends on the trans-
former specifications
=20~/~3_4 ________________________ ~~~~~~~~~~~ ____________________________
598
APPLICATION NOTE
111.2.1. Transformer calculation The following important features must be considered to calculate the specifications of the transformer: · Maximum output power: 120W · Minimum input voltage: · 220 VAC - 20% ~ Vin(min) = 210 VDC with 40V
ripple on the high voltage filtering capacitor
Figure 28.
· Switching Frequency: 15.625kHz · Maximum duty cycle: 0.45 · Output voltages:
+ 140V - 0.6A + 14V - 0.5A +25V -1A + 7.5V - 0.6A + 13V - 0.3A
Vo
NflFoo, I
Lp Ip
I Pout.
V,N
IVCE
V90TEA2260/61-28A
Is
1
VCE
I I I I I I I
~
I I I
'i
t
I. ,
Maximum primary current
IP(max) = 2 x
POUT T
11
x
V'N(min)
x
ON(max) --T--
11 : efficiency of the power supply 0.80 < 11 < 0.85
Primary inductance of the transformer
L P =V-'N1(m-in-) x T ON(max) P(max)
Tr~nsformer ratio ns (VOUT + VDl X TDM
np V'N(min) x T ON(max)
__ t -r----L----~----~~
Reflected voltage
1 VR = T
x V'N(min)
----1
TON(max)
V90TEA2260/61-28B
Overvoltage due to the leakage inductance
C V
IP(max)
PEAK=-2-
x
~
with: Lf = leakage inductance of the transformer 0.04 x Lp < Lf < 0.10 x Lp C = capacitor of the snubber network (see 111.2.2.2)
----------------
~
~~~~~~~~~~s~
21/34
-----------------
599
APPLICATION NOTE
Numerical application To determine the spec;ifications of the transformer, it is necessary to make a compromise between a maximum primary current and a maximum voltage on the transistor :
· To minimize the maximum primary current
WI'th 0 .4 < T ONT(max) <0. 5
· To minimize the maximum voltage on the transistor during the demagnetization phase.
O.3
<
TONT(max)
04 <.
When the output power of the power supply is greater than 100W it is better to minimize the maximum primary current because the current gain
Bf = Ic / 18 of bipolar transistor is 1.5 < Bf < 6
eho'lce .. -T-ONT(m-ax-) < 0 .45
Figure 29.
2XPOUT
2x120
Ip(MAX) = . .
TON(MAX) 0.85 x 210 x 0.45 3A
11 x VIN(MI~) x - - T -
Lp=V-IIN-(-MxINT) ON(MAX)=21-30 x0.45x6410-6 =1.95mH P(MAX)
VR = T
1 x VIN(MIN) = - 1 - - x 210 = 172V
----1 T ON(MAX)
--1 0.45
VPEAK will be calculated with the snubber network determination (see 11.2.2.2.1)
111.2.1.1 Transformer specification · Reference: OREGA - SMT5 - G4467-03 · Mechanical Data:
- Ferrite: B50 - 2 cores: 53 x 18 x 18 (mm) THOMSON-Lee - Airgap : 1.7 mm · Electrical Data:
V90TEA2260/!51-29
Winding np nAUX n2 n3 n4 n5
Pin 3-6 7-9 19-13 19-20 14-17 22-21
Inductance 1.95flH 8.1flH 770flH 8.2flH 4.2flH 31.7flH
- - 22/34 - - - - - - - - - - - - - ~ ~~~,;m~~~9©~ - - - - - - - - - - - - - - -
600
APPLICATION NOTE
111.2.2. Switching transistor and its base drive
111.2.2.1. First current limitation Note: in current limitation TISon < TON
Figure 30 : Current Limitation.
2
wI - l Vpin
~,- 10' "-----------'-
I
~l----k-.--T_18
'B
O_N---------'
V90TEA2260/61-30A
Ie
V90TEA2260/61-30C
V90TEA2260/61-30B
The current measurement is IE = IB + Ic The maximum collector current calculated in 111.2.1 is IC(Max.) = 3A (a switching transistor SGSF344 may be chosen)
The current gain is: Sf = -Ilc = 3.5 B+
The current limitation is :
IE(max) =IP(max) - (Ts xVI~ N(m) in) + IB+
with: Ts = storage time of the switching transistor (typ 3J..ls) and VIMI = first threshold of current measurement (typ 0.6 v)
VIM1 RSHUNT=--
IE(max)
Numerical application IE(max) = IP(max) - (Ts xVI~ N(m) in) + Is+
IE(max) = 3 - (3 10~6 x 210 ) + 0.85 = 3.52A
1.95 10~3
VIM1
06
RSHUNT = - IE(m- ax) = 3.5·2 = 0.169£1
111.2.2.2 Snubber network A R.D.C network is used to limit the overvoltage on the transistor during the switching off time. When the transistor is switched off, the capacitor is charged directly through the diode. When the transistor is switched on, the capacitor is discharged through a resistor.
C _ IP(max) X tf o - VCEo
2 X -3-
· 3 x R x C = T on(min) (to discharge the the capacitor C by the correct amou nt)
o Maximum power dissipated in R :
p = ~ x C x (VIN(max) + VR) 2 x F
- - - - - - - - - - - - - - - - --------~------- ~ ~~~;~g~~~~~
23/34
601
APPLICATION NOTE Figure 31.
Ip max
1
c
V90TEA2260/61·31 A
Numerical application (with SGSF 344 transistor) with: IP(Max.) = 3A - VIN(Max.) = 370 VDC tf = 0.311S - VR = 172V VCEO = 600V - F = 16kHz
TON(Min.) = 411S
C = IP(max) x tf
2 x VCEo
3
3 x 0.3 10-<> 2.25nF 2 x 600
3
R = TON(min) = 4 10-6 = 5600 3 x C 3 x 2.25 10-9
P = '12 x C x VIN(max) + VR) 2 x F
P = ~ x 2.25.109 x (370 + 172)2 x 16.103= 5.29W
In the final application a value of 2.7nF is chosen to decrease the overvoltage on the transistor in short circuit condition.
Figure 32.
Ie
V90TEA2260/61·318
111.2.2.2.1 Overvoltage due to the leakage in-
ductance
(See. 111.2.1)
The capacitor C of the snubber network influences
the overvoltage due to the leakage inductance.
~ Vpeak= IC(max)
2
C
Numerical application
with: Lf = 0.08 x Lp = 0.08 x 1.9 10 -3 = 15211H
Vpeak~X ~= 390V
2
2.25 109
so VCE(Max.) = VIN(Max.) + VR + Vpeak =
VCE(Max.) = 370 + 172 + 390:= 930V
111.2.2.3. Base drive The output stage of the TEA2260/61 works in saturation mode and hence the internal power dissipation is very low.
Is
vz V90TEE2260/61-32A
IB+= VCC+-Vp-VZ-VBE
Rl V90TEE2260/61-328
2-4-/3~4------------------------~~~~©~2~~~~~~ ----------------------------
602
Rl= ~ Ve~e-+- - ~ Vp---V~z- - - VS~ E Is+
Numerical application
on R = 13 - 0.9 - 3 - 0.6", 1
1
0.85
-
Figure 33.
]:r-----,
I
I
:
I
I
I
I
I
I
I
I
I
I
I
I
: '-+:-------'
Ie
APPLICATION NOTE
in this case the current gain,
BF =
Ie -=
3 --- =
3.5
but
it
is
recommanded
to
Is 0.85
verify the VCE sat dynamic behaviour on the tran-
sistor as follows:
Vm
OSCILLOSCOPE
V90TEA2260/61-33A
Vm 4V f----..
Ideal value: 1V :0; VCEsat + VD :0; 2V
Remark :The mains of the TEA2260/61 must be provided through an isolation transformer for this measurement
111.2.3. Oscillator frequency The free running frequency is given on 11.2.
V90TEA2260/61-33S
The typical value of minimum conduction time TONIMin.) on the output of the TEA2260/61 is given
by: TON(Min.) = 1040 x Co
Note: the minimum conduction time TON(Min.) on the transistor is longer due to the storage time.
----------------------------- ~ ~~~C~n&g:f~ii?r~ -------------------------2-5-/3-4
603
APPLICATION NOTE
Figure 34.
"'""F-;1/3;z=\
:~
t
I I
I I
18
----I I-- TON MIN
I I
I I ON TEA2260 I I
I I
I I
I
Ie
~TON MIN :
I ~~AJ~'~TORI
I
I
I
I
V90TEA2260/61-34
Numerical application Fa = 16kHz Co is chosen at 1nF so TON min on the TEA2260/61 = 11ls
Ro =
1
1.57 . 10s
Fox Co x 0.66
Ro =
1
_ 1.57 . 10s
16 lOs x 1 10-9 x 0.66
Ro = 93kQ
Ro = 1OOkQ is chosen.
Note: Fa is chosen relatively low to avoid magnetization of the transformer during the start-up phase.
111.2.4. Regulation loop In stand by mode the error amplifier of the TEA2260/61 carries out the regulation.
Figure 35.
R4
r------------------- 7 -------
R
'------- Vref V90TEA2260/61-S5
· The R.C. filter is necessary to avoid the peak
voltage due to the leakage inductance. The time
constant't = RC is about 30llS < R.C. < 150llS as
a function of the transformer technology.
· To achieve a stable behaviour of the regulation
loop and to decrease the ripple on the output
voltage in stand by mode the time constant
should be approximately:
= ROUT x COUT
(R1 + R2 + Rs) xC
15
with : COUT (filtering output capacitor) and ROUT (load resistor on the output in stand by mode) ., To ensure a stable behaviour in stand-by mode
the amplifier gain is choosen to :
G= ~= 15 R2+Rs-
Calculation of R, Rl, R2, R3, R4
a) The resistor R is given by
R= ..!.
C C choosen between 11lF < C < IOIlF 't = 80llS is chosen C = 2.21lF is chosen
Numerical application
So R = ..!. = 80 10-6 = 36Q C 2.2 10-6
2-6-/3-4------------------------~~~~~~g~~~9~~ -----------------------
604
APPLICATION NOTE
b) The resistors R1, R2, R3 are given by COUT x ROUT
R1 + R2 + R3 =: 15 x C
with: VREF : reference voltage of the error amplifier VREF = 2.5V Vcc(stand-by) : Vcc voltage in stand by mode. Vcc(stand-by) = 0.9 x Vcc (in normal mode)
Numerical application
with:
Vcc =13V
VREF = 2.5V
ROUT = 2kQ on output 135V
COUT = 100jJ.F on output 135V
C = 2.2jJ.F
COUT x ROUT R1 + R2 + R3 =: 15 xC
100
-6 10
x
2
10 3
=
6kQ
15 x 2.210-6
VREF
R2 + R3 = (R1 + R2 + R3) x Vcc(stand py)
R2 + R3 = 6.103 x 0.:~513 = 1.28kQ
values choosen : R2 potentiometer resistor of 1kQ R3 fixed resistor 1kQ R1 = (R1+ R2 + R3) - (R2+ R3) R1 = 6k - 1.28k = 4.7kQ c) The resistor R4 is given by R4 =: 15 X (R2 + R3)
Numerical application R4=: 15 x (R2 + R3) =: 15 x (1.28103) =: 18kQ
111.2.5. Overload capacitor When an overload is detected with the first threshold VIM1 the capacitor C2 (pin 8) is charged until the end of the period as shown in figure 36. So the average load current is given by :
T- TON IC2 = - - T - X ICH - IDISCH
the threshold to cut off the TEA2260/61 power supply is 2.5V typically and hence the delay time before overload detection is given by : Toverload = -=----2o.5;x;-C2---~-
T- TON (--T- x ICH) - IDISCH
Figure 36 : Load of Overload Capacitor.
'::k1 2T nnuu ---TON---"'"'1 ----------T---------~
~ !, I 1u-w,' I"'"'
V90TEA2260/6.1-36
Numerical application
with: maximum overload time = 40ms
the longer delay time is obtained when
TON = T ON(Max.)
« C2 '"
T -
TON(Max.) I )
T
x CH -
I ) DISCH
X ~ Toverload
C2 = (0.55 x 45 x1 0-6_ 10 x10·6 40~~0-3 =: 220riF
Note : in practice, the overload capacitor value must be greater than the soft start capacitor (C2 ~ C1) to ensure a correct start up phase of the power supply.
111.2.6 Soft start capacitor Refer to paragraph 11.5 for the soft start function explanation. The soft start duration is given by :
(2.7- 1.5) X C1 TSOFTSTART = 9 . 10-6
C1'" 7.5.10-6 x TSOFTSTART
Numerical application
with: Tsoft start =30ms
C1 = 7.5 10-6 x 30 10-3 = 220nF
111.2.7. Feed back voltage transformer A feedback voltage transformer is used to send information from the secondary circuit (master circuit) to the primary circuit (slave circuit). This transformer is needed to provide an electric insulation between primary and secondary. side.
- - - - - - - - - - - - - - liii ~itlH~";1:~~~ - - - - - - - - - - - - - - 27/34
605
APPLICATION NOTE
ViRf:} f,fR12 Figure37. . np
C1 .
ns
v,
restarts. and to cut off the TEA2260/61 on fault detection when the power supply is switched off. Hence it is recommended to connect the start-up resistor as follows:
Figure 38.
V90TEA2260/61-37
The feedback input of TEA2260/61 is fed with logic level (threshold 0.9V) It is necessary to have the same waveform on the primary side as on the secondary side. For this reason the time constant must be higher than the maximum conduction time in normal mode. Hence the primary inductance Lp must be calcuc lated as follows: Lp > 3.R.ToN(Max.)
Numerical application with: T ON(Max.) = 28~s R = 2700 Lp > 3 x 270 x 28 10-6 = 22mH
a) When the TEA5170 is used VIN = 7V
ns
VS(min)
np VIN x (1 _ TON(maX»
T
~~ 7 x (11~5 0.45) = 0.389
b) When the TEA 2028 is used VIN = 12V
~~ 12 x (11: 0.45) = 0.227
Note: The R1.C1 filter is used to damp oscillation on the secondary side of the feedback transformer. The time constant R1 x C1 == 0.1 ~s.
111.2.8. Start up resister After switching on the power supply the filtering capacitor on Vcc of TEA2260/61 is charged through a resistor connected to the mains input voltage. Do not connect this resistor to the high voltage filtering capacitor because there is enough energy in this capacitor to cause three attempted
Imoy
!1l--1-1_L
Rst
START UP RESISTOR
Icc start
V90TEA2260/61-38
Start-up delay time
-r-2 x VIN AC(min)
IMOY=
.
7t
X
R ST
.
VCC START
Start-up delay time = Tst = I
I
x C
MOY - CC START
-r-2 x VIN AC(min)
l ( RST = --(O------:V-,-C-C-S-T--'A'-'-RT-'-==c..-'-----'J 7t X C x TST ) + Icc START
Power dissipated in start-up resistor
P = VIN AC(max)2 2 . RST
Numerical application
with:
start-up delay time = 1s
VIN(max) = 370V DC (VIN AC(max) = 265V)
VINAC(min) = 175V
VCCstart= 10.3V
ICCstart = 0.7mA
C = 220~F
~=
7t x (220
2 x 175
10-6 x 10.3 +
0.7
3=~ill
10- )
Value choosen = 22ill
Power dissipated
P = (265)2
1.6W
2 x 22 103
- - - - - - - - - - - - - - =-28::./=-34~____________ ~ ~~~~m~~~~~J;~
606
1I1.~:9. Determination of high voltage filtering capacitor Figure 39.
c
APPLICATION NOTE
V90TEA2260/61-39A
Vin
'\
!:N
\
\
\
I
\ (I
\ /
\ 1
\ /
\1
I-- T/4+t -----,
I
1-------- T --------1·1
Hypothesis:
/c,.V : ripple on the filtering voltage VIN.AC(min) : minimal value of A.C. input voltage T : period of the mains voltage POUT: output power of the power supply 11 : efficiency of the power supply
C =l
-n + ArcS·1n(1 -
/c,.V . In)
x 2
VIN AC(min) x'l2 x POUT
2n
/c,.V x VIN AC(min) x {2
11
Numerical application
/c,.V = 40V VINAC(min) = 170 VAC T = 20ms
POUT = 120W
11 = 0.85
V90TEA2260/61-39A
value choosen : C = 120J.lF
--------------------------- ~~~~~~g:~p~ ------------------------2-9-/3-4
607
Oo l
(Xl
.'i."s..
~
~en
"",1,e1:n'1 '~9i·!
!]!O
~~
~O
@:iiJZ
... Small signal secondary ground ~ Power primary ground CJ Secondary ground (isolated from mains)
POUT; 120W f : 16kHz
"T1
»
cO' W
"\J
s..:.:.:
CD
a·mr-
:c
»(r"-5
> o
":»sc:
"\J
o » I o-f
Z
o z
m-f
APPLICATION NOTE
IV. TV APPLICATION 140W - 220 VAC - 32kHZ SYNCHRONIZABLE All details concerning the determination of external components are described in section III.
IV.1. APPLICATION CHARACTERISTICS. · Discontinuous mode flyback SMPS · Stand-by function using the burst mode of
TEA2260. · Switching frequency in burst mode: 16kHz · Switching frequency in normal mode: 32kHz · Nominal mains voltage: 220 VAC · Mains voltage range: 170 VAC to 270 VAC · Output power range in normal mode
2SW < Po< 140W · Output power range in stand-by mode
2W < Po <4SW · Efficiency at full load> SO% · Efficiency in stand-by mode (Po = 7W) > SO% · Short circuit protection · Long duration overload protection · Complete shut down after 3 restarts with fault
detection for TEA2260 · Complete shut down when VC2 reaches 2.6V for
TEA2261
Load regulation (VDC = 310V)
Output 13SV (± 0.1S%) --7 (1135 : 0.01 A to O.SA; 125=1A) Output2SV(±2%) --7(1135: O.SA; 125 = O.SA to 1A)
Line regulation (h35 : O.SA; 125 : 1A) Output 13SV (± 0.13%)--7 (21 OV < VDC < 370V) Output 2SV (± 0.17%)
IV.2. TRANSFORMER CHARACTERISTICS · Reference: OREGA.SMTS. G4S76-03 · Electrical Data:
Figure 41.
Winding np naux n2 n3 n4 n5
Pin 3-6 7-9 19-13 19-20 14-17 22-21
V90TEA2260/61·41
Inductance
790~H 5.4~H 338~H 4.8~H 3.4~H 13~H
---------------------------~~~~~~g:~~~~~ ------------------------3-1-/3-4 609
'~."..
~
~~
">lUI
Wo~i! 'D~ I
~i: @UI ~o
!l\z
" Small signal secondary ground
%% Power primary ground
c:::::J Secondary ground (isolated from mains)
POUT : 140W f : 32k.Hz
100pF
BY218-600
tPLR811
12V
"~O.5A
4;~0F
:< »
!-l m m r
~
:II (')
r ~
:C ;
G>
"tJ
o"rtJ
»
o-I
Z
o Z
m-I
:II
s~ :
T47nF
lN4148
150pF
~ I:I'~'~
APPLICATION NOTE
V. TV APPLICATION 11 OW ·220 VAC· 40kHz REGULATED WITH OPTOCOUPLER
This application works in asynchronous mode. The regulation characteristics are very attractive (output power variation range from 1W to 11 OW due to automatic burst mode (see 11.6). In this configuration higher is the regulation loop gain, lower is the output voltage ripple in burst mode (e.g. ouput voltage ripple 0.8% with a loop gain of 15).
V.1. FREQUENCY SOFT START The nominal switching frequency is 40kHz but during the start-up phase the switching frequency is shifted to 10kHz in order to avoid the magnetization of the transformer. Otherwise the second current limitation will be reached at high input voltage and hence the power supply will not start.
Line regulation (1135: O.6A; 125. 1A) Output 135V (± 0.30%) -> (21 OV < VDC <, 370V) Output 25V (± 0.30%)
Influence of the audio output on the video out· put
Output 135V (± 0.1 %) ->(1135 = 0.6A; 125 : 0 -> 1A) Output 135V (± 0.05%) ->(1,35 = 0.3A; 125 : 0 ->1 A)
V.3. TRANSFORMER SPECIFICATION II Reference: OREGA.SMT5. G4576-02 o Mechanical Data:
- Ferrite: 850
- 2 cores: 53 x 18 x 18 (mm) THOMSON LCC
· Electrical Data:
Figure 43.
V.2. APPLICATION CHARACTERISTICS · Discontinous mode Flyback SMPS
· Switching frequency: 40kHz
· Nominal mains voltage: 220 VAC
· Mains voltage range: 170 VAC to 220 VAC
· Output power in normal mode 30W < Po < 110 W
· Output power in burst mode: 1W < Po < 30W. The transient phase between normal mode and burst mode is determinated automatically as a function of the output power. Hence the regulation of the output voltage is effective for an output power variation of 1W < Po < 110W
· Efficiency as full load > 80%
· Efficiency in burst mode (Po = 8W) > 50%
· Short circuit protection · Open load protection
· Long duration overload protection
· Complete shutdown after 3 restarts with fault detection for TEA2260
· Complete shut down when VC2 reaches 2.6V for TEA2261
Load regulation (VDC = 310V) Output 135V (± 0.15%) -> (1,35 : 0.05A to 0.6A;
125 = 1A) Output 25V (± 2.5%) ->(1135 = 0.6A; 125: 0.25 to 1A)
Winding np naux n2 n3 n4 n5
V90TEA2260/61·43
Pin 3-6 7-9 19-13 19-?-0 14-17 22-21
Inductance 790llH 5.4Il H 3381l H 4.81l H 3.4IlH 131lH
- - - - - - - - - - - - - - ~ ~~c~~:mg~~CJ~~ - - - - - - - - - - - - - - 33/34
611
Cl w
~
I\)
.t.1,.
~
"'len .":,fte':n-'
~i!
l"Io @~:eIn
~O
:l,lz
'f SmaU signal secondary ground ~ Power primary ground ~ Secondary ground (isolated from mains)
POUT: 110W f : 40kHz
BY2l8-600
7.5V lA
220 Q l6W
!! :<
Cc.Q.:.
CD
.r"m'"
"'"
!'>
~ m
l>
~
.~-
c=;
l> -I
:II (')
7!
(5
Z
Z
c
~
S m
~
:!::
APPLICATION NOTE
TEA2018A-TEA2019
FLYBACK SWITCH MODE POWER SUPPLY IMPLEMENTATfON
By : J-Y.COUET & T.PIERRE
SUMMARY
Page
INTRODUCTION
3
II
TABLE OF UNITS AND SYMBOLS
3
III
CURRENT MODE REGULATION .
3
111.1
DESCRIPTION . . . . . . . . . . .
3
IV
FUNCTIONAL DESCRIPTION OF TEA2018A .
5
IV.1
BLOCK DIAGRAM . . . . . . . . . . . . . . .
5
IV.2
OSCILLATOR AND MAXIMUM DUTY CYCLE .
5
IV.2.1 Simplified diagram ..
5
IV.2.2 Waveforms . . . . . . . . . . . . . . . .
6
IV.3
ERROR AMPLIFIER . . . . . . . . . . .
6
IV.3.1 Functional behaviour on low-load . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
IV.4
CURRENT MEASUREMENT & LIMITATION . . . . . . . . . . . . . . . . . . . . . .
7
IV.4.1 Disabling the current monitoring function . . . . . . . . . . . . . . . . . . . . . . .
8
IV.5
DEMAGNETIZATION MONITORING. . . . . . . .
. ....... .
8
IV.6
THERMAL PROTECTION . . . . . . . . . . . . . . . .
. ........ .
9
IV.7
TEA2018A BEHAVIOUR AS A FUNCTION OF Vcc . . .
. ........ .
9
IV.8
OUTPUT STAGE (POWER TRANSISTOR BASE DRIVE)
......... .
11
IV.8.1 Transistor turn-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
IV.8.2 Proportional base drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
IV.8.3 Transistor turn-off . . . . . . .
12
IV.8.4 Minimum conduction time . . . . . . . . .
12
V
APPLICATION EXAMPLE . . . . . . . .
12
V.1
CUSTOMIZED APPLICATION DESIGN .
12
V.1.1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
V.1.2 Calculation of power elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
V.1.3 Transistor switching aid network . . . . . . . . . . . . . . . .
. .... .
13
V.1.4 Demagnetization sensing . . . . . . . . . . . . . . . . . . . .
13
V.1.4.a
Risk of flux runaway without demagnetization sensing . . . . . . .. . . . . . .
13
V.1.4.b
Implementing the demagnetization sensing function . . . . . . . . .
14
V.1.4.c
Damping network . . . . . . . . .
14
V.1.4.d
Transformation ratio considerations .
15
V.1.5 OSCILLATOR . . . . . . . . . . . . . .
16
V.1.6 Power transistor base drive . . . . . . .
17
V.1.7 SELF-SUPPLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
V.1.7.a
Positive self-supply: Vcc. . . . . . . . . . . . . . . . . . . . . . . . .
18
V.1.7.b
Negative self-supply: V· . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
AN406/0591
1/37
613
APPLICATION NOTE
SUMMARY (CONTINUED)
V.1.8 V.1.9 V.1.10 V.1.11
Regulation . . . . . . . . . . . . . . . . . . . . . . Operation under overload & short-circuit conditions Operation on low-loads . . . . . . . . . . . . Complete Application diagram . . . . . . . .
VI
FUNCTIONAL DESCRIPTION OFTEA2019 .
VI.1
INTRODUCTION . . . . . . . . . . . . . . .
VI.2
BLOCK DIAGRAM . . . . . . . . . . . . ..
VI.3
DIFFERENCES BETWEEN TEA2018A & TEA2019
V1.3.1 Oscillator . . .
V1.3.2 VeE monitoring . . . .
V1.3.3 Output stage. . .. . .
V1.3.4 PLL . . . . . . . . . .
VI.3A.a Operating principles
VI.3A.b Internal structure ..
VI.3A.c
PLL input signal ..
V1.3A.c1 Transistor turn-off Signal: Tswo .
V1.3A.c2 Synchronization Signal. .
VI.3A.d Characteristics of the PLL
V1.3A.d1 Synchronization . . . .
V1.3A.d2 Capture Range. . . . .
VI.3A.e Output filter calculation.
VI.3A.f
Numerical application .
VI.3A.g Holding range . . . . .
V1.3.5 Synchronization signal and the input filter.
VI.4 VIA.1 VIA.2 VIA.3
APPLICATIONS . . . . . . . . . . . . . . Typical application with synchronization . TEA2019 configuration for power boosting Monitor application . . . . . . . . . . . .
VI.5
SYNCHRONIZATION SIGNAL TRANSMISSION.
VI.6
APPLICATION VARIANTS
V1.6.1 V1.6.2 V1.6.3 VI.6A V1.6.5 V1.6.6
Regulation by optocoupler .. . . . . . . . V· generator . . . . . . . . . . . . . . . . . Overvoltage protection . . . . . . . . . . . Application without demagnetization sensing Full shut-down at overload . . . . . . . . . Oscillator (TEA2018A only) . . . . . . . . .
VII VI1.1 VI1.2 VI1.3
FIXED FREQUENCY DISCONTINUOUS MODE FLYBACK . FUNDAMENTALS . . . . . . . . . . . . . . . . . . . . . . . TRANSFORMER CALCULATION AND POWER SEMICONDUCTORS SELECTION MULTI-OUTPUT FLYBACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page
19 19 20 21
22
22
22
23 23 23 24 24 24 25 26 26 26
27 27 27 27 27 27
28
29 30 30 31
32
33 34 33 33 34 34 34
35
36
37
37
-2/-37-------------------------~~~i@~~:~~©~ ---------------------------
614
APPLICATION NOTE
I - INTRODUCTION
The aim of this application note is to provide the designer with information on how to design and implement a simple and low-cost switching power supply around the TEA2018A SMPS Controller. This publication has been sub-divided into 3 distinct sections, namely: - An overview of the current mode regulation - Detailed description of TEA20 18A characteristics - Application example of a 30W discontinuous
mode flyback converter operating directly on 220VRMS mains voltage. This document also covers a description of TEA2019 which replaces the TEA2018A in appli-
cations requiring power transistor turn off synchronization with an external signal. This function is particularly useful in video applications where the switching transistor turn off is synchronized with the line flyback signal.
SPECIFICATION OF A TYPICAL APPLICATION - Discontinuous Mode Flyback - Switching Frequency: up to 40kHz - Power: the power handling capability is deter-
mined by the amount of available base current. Assuming a forced gain of 6 for the power transistor: · PMAX ~ 60W (TEA2018A)
· PMAX ~ 90W (TEA2019)
II - TABLE OF UNITS AND SYMBOLS
Symbol f
fosc fREF lOUT
Ip Is Lp POUT T TREF tON tON(L) ts VAC VSE VIN Vcc VeE VOUT "'ICHARGE
11
Function Switching Frequency Oscillator free-running Frequency Reference Frequency (TEA 2019) Output Current Primary Current Secondary Current Primary Inductance Output Power Switching Period Reference Period (TEA2019) Transistor ON time Conduction time fixed by current regulation Power transistor storage time Mains RMS Voltage Power Transistor base-emitter voltage Input DC voltage Positive supply voltage Power transistor collector-emitter voltage Output Voltage Average current delivered by the PLL of TEA2019 Power supply efficiency
Unit
Hz Hz Hz
A A A
H
W s s s s s VRMS V V V V V A %
III - CURRENT MODE REGULATION
111.1 - Description In current mode operation, the regulation is performed by monitoring the peak current through the power switch (switching transistor). - At every period, the conduction of the power
transistor is initialized by a clock signal issued from the oscillator.
- The power transistor is turned-off when its collector current reaches the threshold level fixed by error amplifier.
------------------------------ ~ ~~~©~9j~~~?©' ----------------------------3/-3-7
615
APPLICATION NOTE
Figure 1 : Current Mode Control
'-----is Q
R
UTPU FILTER
IC
r .... OSCII,LATOR' ./1 A './1 .-
SAWTOOTH
V V V,
'-------~
ISENSE
ISENSE
The main advantage of Current Mode Regulation in Discontinuous Mode Flyback Configuration is that it offers an efficient rejection of all input voltage variations. The peak current value through the power switch, at constant output power, is independent of the input voltage value.
Figure 2
t " " ~ OUTPUT
n-
FLIP·FLOP
_
91AN2018/9·01
Variations of the input voltage have no effect on the error amplifier output voltage.
PRIMARY CURRENT
Constant Error Amplifier Output Voltage
__:~/: ____ L_~ __ --l~::-------
di=L; --
di VIN>
di=Li
Full Input Voltage Rejection
91 AN2018/9-02
-4/3-7-----------------~~~~~;~~~e~9~~ ----------~--------
616
IV· FUNCTIONAL DESCRIPTION OF TEA 2018A
IV.1 . Block diagram (all values given in the following block diagram are typical values ). Figure 3
Vee
APPLICATION NOTE
I L
:~
_______________ ~
I--------::G-ro-un-:id 2f----------,,-iv. 91 AN2018/9-03
IV.2 - Oscillator and maximum duty cycle IV.2.1 - Simplified diagram Figure 4
,----------------[
I
I
:
Vlh(1):
RI
I I
I I
I
I
I
I
I
I
I
I
I~
r---------~
I ~
I
I·~
1
I'"
I
I
I
I
I
I
I
I
I
I
L
_ _ _ _ _ _II_y~~~~~~c~_
~ I
· During Ct charge: Vth(t) = 0.66 Vcc · During Ct discharge: Vth(1) = 0.33 Vee
· Vth(2) = 0.56 Vee
91 AN2018/9-04
~ ~~~©~~~i~2~ ----------------------------5/-3-7
617
APPLICATION NOTE
IV.2.2 - Waveforms Figure 5
OSCILLATOR SAWTOOTH
INTERNAL CLOCK SIGNAL
COMPARATOR MAXIMUM
DUTY CYCLE OUTPUT
BASE CURRENT
91 AN2018/9-05
PERIOD:
T ~ tCHARGE + tDISCHARGE · tCHARGE ~ 0.66 Rt . Ct · tDISCHARGE ~ 0.66 RDISCHARGE . Ct
IV.3 - Error am plifier
- The error amplifier gain is internally fixed at 30dB typical value. Internally implemented compensation networks
set the frequency response characteristics. - Voltage Reference : The value of the reference
voltage applied to the inverting terminal is 2.4 V.
Figure 6 : Error Amplifier Frequency Response Characteristics
40
20
..iii
''""
'"
-20 -40
1
c
w
~
6: -100
-200 1
........ ,
,
,
, I , I
10
I
I
,
I , I
I
10
,
I
II
II
i
1 , ,
, I
100
1000
FREQUENCY (kH:)
I
, ,
,
, I
II I
I
, ,
,, I
I I
II I I II
, I
,
,II
I
,
11'-
! Phase Margin =56"
,
I
I
I
I
100
1000
FREQUENCY (kHz)
ain Margin .. 17 dB
,
1 I
,
,
,,'10000
,, I , ,,, ,
, I
I,, ,
I I
,
10000
91AN2018/9-06
- - 6/37 - - - - - - - - - - - - - - ~ ~~~l;mr~:!~~~
618
APPLICATION NOTE
IV.3.1 - Functional behaviour on low-load
When the feed-back voltage exceeds the regulation range, the comparator output remains in high
state thereby avoiding the initiation of any new conduction cycle.
Figure 7
ll-----jrt+-
FEED-BACK
: tN I
:
:
· t
Q =~~'h ~ H ~ .,
I
I
r
I
I
r
I r I I
! !
BASE CURREtIT
L-_ _ _ _--I 3 1 - - ISENSE
91 AN2018/9-07
Consequence: On low loads, the conduction' frequency becomes lower than the oscillator frequency_
IV.4 - Current measurement & limitation
Peak current through the power switch is set by the error amplifier output voltage.
Clamping the amplifier output voltage at O.63V will result in limiting the ISENSE pin voltage at 1V level.
Figure 8
.oa:<s
Jl
"0
Q)
R2
Q)
u..
llkO
Rl 10.5 kO
L--------~-I-S-E~N3SE
,,"''CK 6 __
m
_ _ _ _ _ _ _ _ _, . .
b~ .. t
EORURTOPRUTAVMOPLLTIFAIGEER ______________ 0.63 V
L-_________________._.. t
,~~k, o~~ 11 I,:'
91 AN2018/9-08
In cu rrent Ii mitation :
V+ = 1.23 V - VBE = O.63V
)
_ _
___R_1__ =:> V(PIN3) = -1 V
V - V(PIN3) + ( VREF - V(PIN3) ) R1 + R2
------------------------------ ~~~~@~~~~~~~ ----------------------------7/-3-7
619
APPLICATION NOTE
IV.4.1 - Disabling the current monitoring function During oscillator saw-tooth flyback, the output of the PWM comparator is disabled and consequently: - The minimum conduction time tON(min) required to
discharge the snubber network is fulfilled whatever the status of ISENSE input at the beginning of Figure 9
Q
conduction cycle (T1 period on waveforms of Figure 9). - All parasitics such as those generated by the recovery of secondary-connected diodes (without RC filter) are eliminated (period T2 on Figure 9).
"'''~W'~~
UJ INCTLEORCNKAL SIGNAL
n
.. t
I I PIN 3VOLTAGE
, ,
· I
IV.S - Demagnetization monitoring
No new conduction cycle is allowed as long as the pin? voltage remains higher than 0.1 V . When used in Discontinuous Mode F/yback configuration, this function will inhibit any new conduction
Figure 10: Demagnetization Sensing
91 AN2018/9-09
as long as the transformer is not fully demagnetized. It is obvious that this function offers efficient security in case of overload and short-circuits.
Q
Comments:
- Demagnetization monitoring feature can be used to implement an on-off function.
91 AN2018/9-1 0
- This function is disabled by grounding the pin?
620
APPLICATION NOTE
Figure 11 : Waveforms
~:hJ:.=l=~==-=---~=-FLJ~t=F-'b=. : : t=-D-=t- '- [j-t- I:.~.-. t
-0.60
U
~ ... t
I
I
I
I
"«W'wtirz
~
Ill§;
I :
nI ;, ~I
U
.... t
u
u u
91 AN2018/9-11
IV.6 - Thermal protection When the junction temperature exceeds +150°C, an on-chip protection device will inhibit any new conduction.
IV.7 - TEA2018A behaviour as a function of Vee Figure 12: Vee Monitoring Circuit
r--
I
I I
INTERNAL
Vee MONITORING
I
BIAS Vee ~
I
'--_--'''GOOd'' 4.9 V 6 V
I
Undervaltage
I
L ____-,
S Q I
I
FLlp·FlOP
I
I
R Q
I
IL ____________________ ~
91AN2018/9-12
------------------------------ ~~~~©~~~:~~~ ----------------------------9-/3-7 621
APPLICATION NOTE Figure 13: Waveforms
VCC RISING SUPPLY VOLTAGE (V)
-VC-C-(ST-AR-1) -(SV-) - -
---1- --VCC(STOP) (4.9V)
I I
SUPPLY CURRENT (A)
I ~t
REFERENCE 24v-,...I----:l....:----
VOLTAGE (V)
~t
NEGATIVE OUTPUT
OSCILLATOR VOLTAGE (V)
Vee FALLING
Vose =Vee
~t
- --- -- - --- VeC(START) ---O.SSVee ---0.33 Vee
91AN2018/9·13A
SUPPLY VOLTAGE (V)
- - - - - - - 1 - - - - - - VCC(STOP) (4.9V)
1
I
SUPPLY CURRENT (A)
REFERENCE VOLTAGE (V)
OSCILLATOR
VOLTAGE (V)
1
1.6 mA (max)
F
1
1- 2.4V
rvwwvvJ- 0,66 Vee
-0.33 Vee
NEGATIVE OUTPUT
t
... t
.. t
.. t
... t
91AN2018/9·13B
5 1 6- 120/23- 7 --~------ 'II. Sii)GJua:S:oo@-r1n~lHia:O:"D'ML'llS0U<!OJUa:N:", - - - - - - - - - - - - -
APPLICATION NOTE
IV.S· Output stage (Power transistor base drive) The TEA2018A has been designed to provide direct drive to bipolar power transistors. Figure 14 : Simplified Diagram of the Output Stage
IB(ON) IC(COpy)
Jl
Rc
Pulse Width Modulator
OV~
Figure 15 : Waveforms
t~ --r ~ -.. I I tIB(ON) td ~ I I
91 AN201819-14
tIB(ON) ~ 0.66 x 2000 x CT
td ~ 500 ns (typ)
As IB(oN)~ 1 Y
18 ~ IY-I - YNS
RB
(YNS : negative stage dropout 0.8 Y to 1 Y)
91AN201819-15
------------------------------ ~ ~~~;~~~~~~~ ---------------------------1-1/-3-7
623
APPLICATION NOTE
IV.8.1 - Transistor turn-on A pulse current "IB(ONj" provides for rapid transistor turn-on. The duration of this pulse is equal to the oscillator saw-tooth fall time. The value of this current is : IB(ON) ~ 1V/RB
IV.8.2 - Proportional base drive Once the turn-on current pulse IB(oN) has been issued, the internal current recopy device of TEA2018A will output a voltage VOUT such that:
You! ~ V(PIN3) + V SE VOUT ~ VSE + Rs. Is VtpIN3) ~ RE. Ic
=> Forced gai.n ~ -Ic ~ -Rs Is RE
1V.8.3 - Transistor turn-off The power transistor is· turned-off by the application of a negative base current. A 500ns typical interval duration between the positive stage turn-off and the negative stage turn-on, will prevent simultaneous conduction of complementary output stages and also abrupt transistor turn-off.
v - APPLICATION EXAMPLE
V.1 - Customized application design V.1.1 - Specifications
Output Power Effective Input Voltage Input Voltage for Start-up and Regulation Regulation Input Voltage after Start-up Transistor Reflected Voltage Switching Frequency Expected Efficiency Output Short-circuit Protection Open-load Protection 2 Outputs
IV.8.4 - Minimum conduction time In order to allow the discharge of snubber network, each conduction cycle has a minimum duration equal to tON(min). Figure 16
BASE CURRENT
COLLECTOR CURRENT
· tON(min) = tIB(ON) + ts
· ts : Power Transistor storage time
91AN2018/9-16
3.3W S; POUT S; 30W 176 VRMS S; VAC S; 245 VRMS 200 Voc S; VIN S; 350 Voc 130 Voc S; VIN S; 350 Voc
VR~.210V
f ~ 27kHz 11 ~70% Yes Yes (5V, 2A), (12V, 1.5A)
--12/37------------- ~ ~~~~m~:lP~~
624
APPLICATION NOTE
V.1.2 - Calculation of power elements (see also section 7.1)
· VIN(MIN) = 200V
iii tOTN(l} = 0.426
· Ip(AV) = 0.214 · Lp = 3mH
(where tON(l) = conduction time fixed in current limitation mode) iii Ip(PEAK) =; 1A e POUT(MIN) = 2.65W
· 5V Output:
ns S 0.029 np
IS(PEAK) = 9.4A => Diode: BYW98 - 50
· 12V Output:
ns S 0.061 np
IS(PEAK) = 7.05A => Diode: BYW98 - 50
· Transistor selection
{·
" "
IC(MAX} = 1A
}
VC(MAX} = VIN(MAX} + VR + VSPIKES ~ 800V
=> BUV 46A
V.1.3 - Transistor switching aid network Figure 17
"C = I(PEAK}. tF = 1nF 2.V
" 3RC = tON (MIN)
R ~ 1kQ [ for tON(MIN) = 3/ls]
" Diode: BA159 " Maximum Power dissipated in R :
2" P = 1 C [VIN(MAX}]2. f = 1.8W
V.1.4 - Demagnetization sensing
a. Risk of flux runaway without demagnetization sensing
In the absence of demagnetization sensing, the converter will operate in continuous mode flyback at power supply start-up and also in the case of
91 AN2018/9·17
overloads. Due to the minimum conduction time imposed by TEA2018A, there will be risk.of flux runaway within the transformer and the current through the transistor.
- - - - - - - - - - - - - - ---------~~--- ~ ~~~~m~~~R~
13/37
625
APPLICATION NOTE
Figure 18
m== x _
.......,oNlm;nl
,
_ ______________;. CPMAX
i::tI
, I
I I
I I
I
I
I
I
I
I
,
I
I
t
T
2T
3T
,
91AN2018/9-18
~ Flux runaway at start-up or in case of short-circuit: VIN _tON(MIN) > VLOSS . ( ). [T - tON(MIN)l
(Where VLOSS Z 1.5 V is the voltage drop accross the rectifier diode and the resistive component of secondary winding).
Combining tON(min) and demagnetization sensing functions, will yield highly secure operation ensuring the following functions:
· magnetic flux monitoring
· efficient discharge of snubber networks
b. Implementing the demagnetization sensing
The winding used for circuit power supply will also reflect an image of the induced flux. The value of the resistor "Ros" used for this function is not critical and can fall within: 10kQ < Ros < 47kQ range .
Figure 19 : Configuration Arrangement and Short-circuit Waveforms
",~1 Voelw!:1ak
~
T
2T
8 V
1VC E I
,"I 0t..,
p__ v,,"
m_l"~~,~
vu- .-O.6V
t
91AN2018/9-19
No new conduction cycle may be initiated as long as the transformer is not fully demagnetized. On start-up, and in the case of overloads, the demagnetization sensing function will modify the frequency of the conduction cycles accordingly.
c - Damping network
Once the transformer has been demagnetized,
positive voltage oscillations produced by the discharge of resonant "Lp.C" network may result in unwanted activation of the demagnetization monitoring function. To prevent this problem, all that required is to damp the voltage oscillations, as shown in Figure 21, through "Ro - Do" network where diode Do "shunts" the resistor "Ro".
626
Figure 20
0: W
l::
:;:W WCJ
ci:< o!:;
tWi °>
...l
o...l
U
W
.... ~
;?;!:;
0. 0
>
APPLICATION NOTE
End of
I I
I X : : I New Conducllon noral/owed
Figure 21
UNDERDAMPING
V"~
CORRECT DAMPING
91 AN201 819-21
BOVERDAMPING
elay
i
I
I
2~ Ro+R«
Ro+R~ 2~
2~ Ro+R»
91 AN201 819-21
· Resistor:
Ro ~ 2~- R ~ 2.2kn
o
91 AN201819-20
d - Transformation ratio considerations On initial start-up, due to demagnetization monitoring function, the value of conduction frequency will
· Power:
· Diode: (BA 159)
IRMS
~ Ip(RMS)
VO(MAX) ~ VR + VSPIKES
rise in multiples of the normal operating frequency "f" as illustrated below:
BEGINNING OF
START-UP
fin -----.. f/n-1 _
... _
f/2 -----..
END OF START-UP
627
APPLICATION NOTE
Employing a conventionally calculated transformer, the converter will stop operating at "f/2" frequency. Figure 22
.IS -
np
nS Vo
Lp
<PM
·
At freq ue ncy "ii2" :
TRANSFORMER FLUX Combining (1), (2) and (3) :
91 AN2018/9-22
The converter operating frequency will switch from "f/2" to "f" if the following condition is satisfied:
(1 ) (@ f/2 frequency)
(2)
(where tON(L) = conduction time fixed in current
limitation mode)
V.l.5 - Osci lIator
The value of capacitor "Ct" is calculated as a function of :
· tON(min): = 311S
· tON(min) = tIB(ON) + tSTORAGE ) Ct = 1.2nF
· tSTORAGE = 1 .511S · tIB(ON) = 0.66 Ct . 2000
Ct ~ 470pF
The value of resistor Rt is calculated as a function of period T as follows:
T = 0.66 Ct (Rt + 2000) = 3711S ~ Rt = 47kQ
628
APPLICATION NOTE
V.1.6 - Power transistor base drive
The "Re" resistor is calculated as a function of "current limitation" and the resistor "RB" as a function of "forced gain". Resistor "Rp" can be con-
Figure 23
nected to pin 3 "I SENSE" to protect the device against mains-generated transitional overvoltages.
Current limitation
I I
I I I
IL_
A - Transient
Ie
BUV 46A
Re Ie IB
91 AN2018/9·24
V(pIN3) ~ O.88V (current limitation threshold value)
Gain calculation
f IC(MAX) = 1A =} Transistor: BUV46A =} Forced Gain ~ I = 9
B
- - - - - - - - - - - - - - - ~ ~~~;1t'IT19m(~I!~~ - - - - - - - - - - - - - - - 17/37
629
APPLICATION NOTE
V.1.7 - Self-supply Power supply start-up A high value resistor inserted between the "high voltage source" and "Vcc" capacitor will charge up this capacitor upon the initial supply start-up.
Figure 24
The TEA2018A starts operating at Vcc ~ 6V (typ). On-chip implemented hysteresis of 1.1 V (typ) will trigger the self-supply function.
V1N(DC)
R
Vcc
...----16
~ c:r:CHARGE
VCC(START) VCC
l-tSTART-I
The value of R is calculated to yield maximum start-up time.
o C = 220~F ° VCC(START)MAX = 6.6V ° ICC(MAx) = 1.6mA ° tSTART = 3s
°
I CHARGE
=
VCC(START)MAX. tSTART
C
° R = VAC(MIN) . -v2
ICC(MAX) + ICHARGE
°R=120kQ
· t
c
91 AN2018/9-24
a - Positive self-supply: Vee
The Vcc supply is provided by a flyback-type winding. The number of turns "n" is selected to yield a voltage "V" of approximately 1OV.
Within the self-supply arrangement, the resistor "RF = 15Q" in combination with the capacitor of
Figure 25
1N4148
VIN
I
vI RF
·
'AVERAGE
6 -.,
I I I
1
n
9 + Vo
ns Vou't+ Vo
VCC, form a filter network which attenuates mainsgenerated voltage spikes. Note that in the absence of this filter, the energy generated by voltage spikes can often satisfy the power supply requirements of the TEA2018A in case of any short-circuit on low-voltage windings.
91 AN2018/9-25
is sufficiently high to meet the power supply requirements without RF
-18-/-37------------------------- ~~~~@~~M~g~ ----------------------------
630
APPLICATION NOTE
b. Negative Self-supply: V A negative supply voltage ''V"'' is required for efficient transistor turn-off.
This voltage is generated by an auxiliary winding connected in forward arrangement.
The "zener diode" will clamp this negative voltage and make it independent from the input voltage (VIN > 200V).
The "Cs" capacitor will accelerate V- settling process upon the initial power supply start-up. Resistor "Rs" is used to limit the current upon the negative power supply setup.
Figure 26
V.1.8 - Regulation As illustrated in Figure 28, the self-supply winding is also used for voltage regulation.
To avoid the power drawn by TEA2018A to influence the regulation, the supply for regulation is generated by a source independent from "Vcc".
Figure 27
R
1N414B
1N4146
n
Cs 10llF
3.9V
91 AN201 B/9·26
·
IAV
=
Is
x
~
T
=
15
mA
(VIN. n:)-<1V-IV-ll · RS(MAX) = - ' . - - - " - - - - - - - -
I(Av)
= 230Q (@ VIN = 200V)
Prefered value: Rs = 150Q
91AN2018/9·27
The RC filter attenuates the parasitics due to voltage spikes generated by switching. However, the cut-off frequency of this filter must be sufficiently high so as to avoid excessive slow-down of the regulation loop response.
V.1.9 - Operation under overload & short-circuit conditions
In case of any overload, the secondary voltage will fall, circuit power supply will drop below VCC(STOP), consequently TEA2018A stops operating and its power consumption will fall under the current supplied by the start-up resistor.
The capacitor of "Vcc" begins charging up and a new conduction cycle will be initiated as soon as "Vcc" reaches "VCC(START)" level.
The system will function in relaxation mode as long as the overload persists.
- - - - - - - - - - - - - - ~ ~~;~@mgm~~L~ - - - - - - - - - - - - - - 19/37
631
APPLICATION NOTE Figure 28
POSITIVE SUPPLY VOLTAGE
cg~~~~~~R n n 11---..1 ENVELOPE L_______~---..I[]~----L~-----L~--~I--LII--I-----..-. t I · 1 Short-circuit
91 AN2018/9-28
V.1.10 - Operation on Low-loads When the output power lalls below:
p
= (V,N · t(ON(MIN/ . I .
OUT(MIN)
2 L . p
11
the regulation becomes incompatible with the operating Irequency "I", conduction cycles occur in a random lashion and at a frequency lower than "I".
Figure 29
~ OSCILLATOR
SAW·tOOTH
h_ COLLECTOR CURRENT
I I I :
llON(min)
H
r1
Note: This event has no impact on the power supply reliability.
.. t
... t
91 AN2018/9·29
--- 20/37 ------------------ J:fi ~~~;mgJ'~l~,,~lj ---~----------
632
t"oT1· :<
e :.....
@
Ul 0
0
0
~
~jcn ~n
~cr
~i!
~o
T I ~.Il
47~F
3B5V
Q C::i 12~W
1N4148 680
I.~ . 1111 !
Ii
-H.-~;J-:'~: TI~::~;N4148! :i ~., "F
J RF Filter I
2x12mH 1
~Ljg
I I ' 4.7~F I~=F==~f=====~====~============~--~ I!I
n T.l.
I ;""·L.l4.7k!l ....
I I ill I
I
1SV
i
....
I
:
~ 1BSA9:·:f 11 2.32W}ill
L:j~_~__FI:I ~1k!l I 1 0 UB~BO~ ~ ~....J
nO y" 05A . . I
~ J, ..!.J 47 [
~ 5;
4.70 -
;!.;
L:....JllN41484
TEA 2018 A
'= I
fL?~y "rJB-Ari JIO':":
46A 1159
, 220V AC
k!l
.
r1 :t ~2r1 :"1
r-="1
I 0"""
...., -
1500
;: 1 nF 1 kV
BYW98·50
~I 1
'OOO~F"'"
~
~ .+ 12 V
BYW 98·50
!1 · + sV 4700~F
1
3
"c0o
CD
»
"0
"oQ·. ~o·
~
0
iii'
<0
til 3
",3:::
.~
81)2
(J)
~
w w
W
--J
»
"tJ
II 3.5W ::; POUT::; 30W
III Output short-circuit protection
n"rtJ
II Outputs: · 5V . 2A · 12V . 1.5A
II Open-load protection
oz~
o z
-mI
APPLICATION NOTE
VI - FUNCTIONAL DESCRIPTION OF TEA2019
VI.1 -Introduction The TEA2019 has an internal architecture similar to TEA2018A and offers the following additional features: - a true positive current source providing linear
charge-up of the timing capacitor "Ct"
VI.2 - Block Diagram
Figure 31
- an internal PLL which allows syncl\ronization of the power transistor turn-off with an external clock signal
- power transistor desaturation monitoring - possibility to dissipate externally the power re-
quired for transistor base drive
IS
Vee
. - - - - - - - - - - - . . , 5 ~--------__I31---------~
n. PHASE
LOCKED LOOP
Sampling Pulse
Vee "gooCr Bias
Demagnetlzatlon Sensing
&
___ ..1
L -_ _ _ _ _ _ _ _ _ _~12~---~11~----~
ISENSE
Ground
VeE Monitoring
V91AN2018/9-30
- - 22/37- - - - - - - - - - - - - ~ ~~~@lt&~If[0l~~
634
APPLICATION NOTE
V1.3· Differences between TEA2018A & TEA2019
V1.3.1 - Oscillator The oscillator saw-tooth waveform is linear. The
capacitor "Ct" charging current is constant and is determined by the value of resistor "Rt".
Figure 32
TEA2019 ooovccP=u:::
0.33VCC
o
.. I
I I T
I I-----...J
· T = tCHARGE + tDISCHARGE · T = 0.69 Ct (Rt + 2000) · Maximum Duty Cycle = 80 %
91 AN2018/9-32
V1.3.2 - VCE Monitoring If during the power transistor conduction period the pin 4 voltage exceeds 3.2V, the transistor would be
Figure 33
turned-off until the next conduction cycle. To disable this function, pin 4 must be grounded.
vee
10 kQ
· T1 = Transistor turn-off by desaturation monitoring
·T2 = Transistor tu rn-off by regulation
SIMPUFIEO OIAGRAM
91 AN2018/9-33
------------------------------ ~ ~i~~~2~~~~~~ ---------------------------2-3/-3-7
635
APPLICATION NOTE
V1.3.3 - Output stage An external resistor connected between Vcc and VAUX will dissipate a portion of the power required by the base drive. The value of this resistor is calculated to be as large as possible but appropriately dimentioned to. avoid the saturation of the
output stage 01. Figure 34
R
91 AN2018/9·34
R = Vee - VSE - VeE(MIN) Rs (where VeEIMIN) ~ 1.5 V)
IS(MAX)
Figure 35
- Power dissipated in OJ (Flyback) :
=-=r P tON [ (Vee- VSE)1'8-(M2AX~) - (Rs+ R) . 1!lI3MAX)]
- Power improvement compared to TEA2018A:
~p
2 . R. ISIMAX)
2 (Vee - 3.5 V)
Y = 3 (Vee - VSE) - 2 . Rs . IS(MAX)
Vee - 5V
~: {at: Vee =+ 9 V =>
= 0.5 i.e. 50%}
VI.3.4 - PLL In a discontinuous mode flyback configuration, the power transistor turn-off produces significant amount of noise. It is therefore interesting to synchronize this event with an external signal. Since the transistor turn-off instant in current mode operation is generally unknown, consequently, only phase and frequency locking of the oscillator will enable to synchronize the transistor turn-off time without disturbing the voltage regulation loop.
a. - Operating principles
Oscillator phase and frequency can be accurately controlled by adjusting the charge current of "Ct" capacitor. The PLL behaves as a current generator, the direction and the magnitude of which are function of the phase difference between transistor turn-off and the synchronization signal.
~ICHARGE< 0
~ICHARGE> 0
Tosc
=Vcc
ICHARGE 2RT -tJ.lcHARGE
91 AN2018/9-35
-24-/3-7---------------------------~ ~~~@~g~~~~~ ------------------------------
636
APPLICATION NOTE
b - Internal structure The major building block of the PLL is an analog multiplier whose two inputs are the synchronization signal and power transistor turn-off monitoring sig-
Figure 36
nal. Multiplier output signal has a complex spectrum; a low-pass filter is employed to extract the DC and low-frequency components.
/ ! Sync. Pulse
(fREF ,TREF)J I 7
91 AN2018/9·36
Figure 37 : Synchronization configuration waveforms
Tswo
SYNCHRONIZATION PULSES
PLL
f'-
're"on
OUTPUT CURRENT
(;
N
« Z
Oi
0I · I I· Ts
o~
~A
In phase
D-
--+-i-Tsl2
I I
~I I I
I
I
I I I
0
Maximum Delay
O
-W-Tsl2
l L I
I
[ [ I
~ d
Maximum advance
The PLL will source or sink the maximal current when the shift interval between synchronization signal and the transistor turn-off equals tsl2 .
637
APPLICATION NOTE
c - PLL input signal
c1 - Transistor turn-off Signal: Tswo Due to transistor storage time, the PWM compara-
tor will generate a pulse which will be used as Tswo signal.
Figure 38
IS:lf___ o
(SENSE
~ I
VEA
,------~
t CO~~~~OR
n ~
t . BASE
......-&
I CURRENT I~
U o
~t
· t
91 AN2018/9-38
c2 - Synchronization Signal The characteristics of synchronization signal are outlined in section 6_3.5. d. - Characteristics of the PLL
d1 - Synchronization When synchronization occurs, the average current delivered by PLL is equal to dlcHARGE required for frequency compensation.
Figure 39
TEA 2019 Tswo
~ , SYNC.
(TREF)
.
I
tl~LL_j_
Fr
If f I I d ICHARGE I = ~ rPLL(dt) + IPLL(dt)
91AN2018/9-39
- - 26/37 - - - - - - - - - - - - ~ ~tmt"~~~
638
APPLICATION NOTE
d2. - Capture Range: I fa - fREF I MAX
The signal delivered by PLL prior to synchroniza-
tion has I fa - fREF I component. GdB is the overall
gain of multiplier and filter stages. Phase locking is
Figure 40
possible if the frequency difference I fa - fREF I sat-
isfies the following relationship: GdB I fo-fREF I ~ 0 db
I
I
I I c
Rt
I I L
.,.el ____!_ti_l _
I
--1
f =
1
1 2 It (R + R1) Cl
f3
I I Log. fose - fREF
91AN2018/9·40
R + R1
f3 = 2 It . C . R . R1
e - Output filter calculation
For stability reasons, the output filter is calculated at gain Gl ~ 0 dB.
- "f2" frequency determines the capture range. - "f3" frequency is equal to the free-running fre-
quency"fo". - The "Go" gain is rather complex to evaluate. By
approximation, it is proportional to the switching transistor storage time "ts".
At ts = 21ls , the gain Go = 24dB
f - Numerical application
The following calculations yield the optimum value of capture range:
· fa = 15.6kHz (switching frequency)
· f2 = 2.2kHz (this is the selected
capture range ± 81ls with
respect to 641ls period)
Gl = OdB, Vee = 8V, ts = 21ls, Ct = 1.5nF , Rt = 56kW , Go = 24dB R = Rt yields excellent noise immunity.
R1 Go - G, = -20 log R + R1
=> R1 ~ 3.9kQ
2 rr R1C1 R + R1
2rr. C. R. R1
=> C, ~ 22nF => C ~ 3.3nF
g - Holding range Once the capture occurs, the free-running frequency "fose" can rise within the holding range without causing loss of synchronization. When synchronization is achieved, the filter no longer introduces any attenuation and thus the holding range becomes larger than the capture range.The holding range is given by :
Ll.T = TREF . _ _ _-'-1- - -
I + 0.33 . Vee. CT
IpLL . ts
Where: - TREF: the period of synchronization signal - IpLL : the maximum current the PLL can source or
sink (0.7mA typ)
---~-------------~~ii;~~~~~~~~~ -~--------------2-7/-37
639
APPLICATION NOTE
V1.3.5 - Synchronization signal and the input filter The synchronization signal applied to PLL input (pin7) must respect the following conditions:
Figure 41
PIN7"VIO!LTA~ r:r: dv/dt> 0 I"' (V)
TREF
· I
O.55V(typ)
~_I 2.5V (max)
I--l
Synchronization Range
91AN2018/9-41
The TEA2019 has been particularly designed for video applications where the synchronization signal is obtained from the flyback signal generated
Figure 42
during the line flyback. Figure below illustrates the configuration arrangement used in such applications.
'" 20kn
VSYNC
I e I
I~ -r~~f '
· In typical application: C3 = 47nF, C2 = 33nF
· R2 is calculated as a function of :
R2 '"
e
C2 log ( VSYNC ) VSYNC- VIN
91 AN2018/9-42
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· Input voltage range: 90 VAC to 260 VAC · Scanning Frequency: 32kHz · 20W:o; POUT:O; 40W
iii Output: · 60V + 1.5%, 0.5A
· 24V ± 2%, O.4A
I!Il Synchronization signals is transmitted via an optocoupler inserted within the regulation loop.
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APPLICATION NOTE
VI.5 - Synchronization signal transmission
This signal is often generated from the secondary of the power supply, and therefore requires gal·
vanic isolation. Two solutions outlined below are both appropriate:
Figure 46 : Transmission through EHT transformer winding
Well-insulated wire
I
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I
~ 'tEA 2019.
I . 4TI--~
Secondary
PrImary
Figure 47 : Transmission via the Optocoupler of Regulation Loop
91 AN2018/9-46
~_----j=-- Vee
2.21<0
TEA 2019
Primary
Secondary
"tfov
Sync Pulse
91 AN2018/9-47
In this configuration, the optocoupler is used for the transmission of both, feed-back voltage and the synchronization signal.
~32~/37----------------~IF~~~wf~~4 ---------------------------
644
VI.6 - APPLICATION VARIANTS V1.6.1 - Regulation by optocoupler Figure 48
I I
V1.6.2 - V' Generator Figure 49
APPLICATION NOTE
91 AN2018/9·48
3.3V 1W
Up to ICIAVI = O.2SA
V1.6.3 - Overvoltage protection Figure 50
Up to IC(AVI = O.SA
Vz
Vee
TEA2018A OR
TEA 2019
91AN2018/9·50
--------------- ~ ~~~o~~~~~~ --------------- 33/37
645
APPL.ICATION NOTE
VL6.4 - Application without demagnetization sensing If the condition given below is satisfied, the demag- any risk of flux runaway in case of short-circuits or netization sensing function can be omitted without at start-up.
V
+ (VOUT V LOSS) ::; V LOSS IN(MIN)
V1N(MAX)
T-t
ON(MIN)
·
~ T - t
tON(MIN)
tON(MAX)
Consequently, the damping network is no longer required and the "demagnetization sensing input" can be grounded.
VL6.5 - Full shut-down at overload In case of overload, the arrangement depicted below will completely shut-down the power supply. To re-start the system, capacitor "C1" must be discharged.
Figure 51
>--..---.-__ H.V.
C1 470 kn
R
C2
Vee
12V
a~t:I:~ > ~~--------------------.-
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re-start inhibited
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+
Overload
C2 ~·10 C1
R ~ 220 n
91 AN2018/9·51
VL6.6 - Oscillator (TEA2018A only) Figure 52
Rt
Rt
OR
Both configurations are functionally equivalent
91 AN2018/9·52
-34-/3-7------------------------~~i~~~~~~~ ---------------------------
646
APPLICATION NOTE
VII- FIXED FREQUENCY DISCONTINUOUS MODE FLYBACK
VI1.1 - Fundamentals
An operating phase includes 3 phases:
· 0 s t s tON : energy is stored within the primary
inductance
· tON S t s tdm : energy transfer toward the secondary
winding
· tdm S t s T : dead time, the transformer is fully
demagnetized.
Figure 53
K : closed
K: open D : conducts
Vo = Vour +nn-ps VIN
dis dt -
Energy stored during tON (V t )2
W LP =2~ L
P
tdm < t < T
K : open
D: blocked
Transformer Flux
d 4> --L dIs
VIN
dt- Sdt
91AN2018/9·53d
--------------------------- ~~~~@~2:~2~ ------------------------3-5-/3-7
647
APPLICATION NOTE
VII.2 " Transformer calculation and power semiconductors selection Figure 54
Ip(AVERAGE)
VOUT=VItNTO- N-2~LpT
tON
1
o
tON
T
tdm
91AN2018/9-53d
· Maximum operation duty cycle:
(1)
tON(L) = VR T VR + VIN[MIN)
· Maximum average primary current:
· Maximum peak primary current:
· Primary inductance:
· Maximum transformation ratio:
(1) ( ns ) = [VOUT + Vo 1[T - tON(Lll
np [MAX)
VIN[MIN) . tON(L)
· Peak rectifier current:
(2)
tON[L) _
VR
T - VR + -Y2 . VIN(MIN)
Ip(AV)MAX = POUT(MAX) . - -1 -
11
VIN[MIN)
T Ip[PEAK) = 2 Ip(AV)MAX . -t-
ON[L)
tON(L) Lp = VIN(MIN) . I
P[PEAK)
(2)
( ns ) _ [VOUT + Vo 1[T - tON(Lll np [MAX)- VIN(MIN) . tON(L) . -Y2
IS(PEAK)
=
2
IO~T
(ldm
T _
tON)
· Minimum power transfer at frequency "f" :
f [ VIN(MAX) . tON(MIN)
POUT(MIN) = 11 .
2. Lp
.f
Where: (1) : without demagnetization monitoring (2) : with demagnetization monitoring
· tON(L) : Conduction time before current limitation
-36-/3-7 -----------------------~~~~~~J?I --------------------------
648
APPLICATION NOTE
VI1.3 - Multi-output flyback All transformer windings undergo the same flux change of dljJ/dt. Regulation of any output causes regulation of all other windings. Figure 55
91 AN2018/9-55
----------------------------~~~~~~g~~~?G~ -------------------------3-7-/3-7
649
APPLICATION NOTE
AN AUTOMATIC LINE VOLTAGE SWITCHING CIRCUIT
VAJAPEYAM SUKUMAR THIERRY CASTAGNET
ABSTRACT
90V - 132V range.
The voltages found in line sockets around the world vary widely. Power supply designers have, most often, overcome this problem by the use of a doubler/bridge switch that can double the 120V nominal line and simply rectify the 240V nominal voltage.
b) 240V nominal, 50Hz systems. Equipment has to be designed to run in the 187V-264V range.
A good reference for the various line voltages around the world is found- in [1).
A two device solution (comprising an integrated circuit and a customized triac) that will adapt the power supply to various line voltages around the world is described in the following paper. This circuit replaces a manual switch and could also open special markets. Other advantages of this integrated circuit solution are ease of circuit design, lower power dissipation, a smaller component count and additional safety features.
INTRODUCTION - THE DOUBLER/BRIDGE CIRCUIT.
AC line voltages the world over can be divided into two main categories:
a)120V nominal, 60Hz systems. Electronic equipment is usually designed to run in the
Power supplies built to run off these voltages have to be either wide range input or must use a doubler/bridge circuit. The disadvantage of the wide range input scheme - that all components have to meet worst case current and voltage requirements - makes such a solution popular only at less than 75W power levels. The popular doubler/bridge circuit is shown in Fig. 1. When the AC input voltage is 120V nom. (doubler mode) the switch S1 is closed. During the positive half cycle of the input voltage capacitor C1 is charged. During the negative half cycle of the' input voltage, capacitor C2 is charged to the peak line voltage. When the line voltage is 240V nom. (bridge mode), the switch S1 is open and the circuit works like a conventional bridge rectifier.
Figure 1. Schematic Diagram of a Doubler/Bridge Circuit.
!12:, 6~Hz 24~V.5~Hz
AN389/0191
Cl 24<lV Sl 0
12~V
C
S"w' [ TCH I NG
REGUUlTOR
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t.o
5<l~11
116
651
APPLICATION NOTE
At power levels of over SOOW, power factor correction circuits and three phase line input voltage circuits dominate. So, the automatic line voltage switching (AVS) circuit is used mostly in the 7SW-SOOW power range.
rhe recent push to replace the mechanical switch S1 in Fig.1 with an automatic line voltage switching (AVS) circuit came from computer
Figure 2. Discrete AVS Circuit Block Diagram
manufacturers. They found that the small additional. cost of the AVS circuit is less than the costs of power supply failures incurred by inadvertently positioning the switch in the wrong position.
While many of the early AVS designs used relays, the triacs, with their superior reliability, small size and low cost are now more popular.
HIGH VOLTAGE DC BUS
COMPARATOR POWER
VOLTAGE SENSE
A1
SIGNAL AMPLIFIER
AND
LEVEL
A2
SHIFT
PRIMARY RETURN
DISCRETE AUTOMATIC VOLTAGE SWITCHING CIRCUIT
Figure 2 shows a diagram of the various blocks comprising a discrete implementation of the AVS circuit. The line voltage selection circuit can be divided into three main functions:
1. Detection of peak line input voltage. Various schemes use resistive or capacitive di-· viders to measure the voltage across C1 and C2.
2. Comparison with a reference voltage that is generated 'with tl:1e help of a zener diode. A simple comparator can be implemented with two small Signal transistors.
3. Drive for the triac. If the circuit is to be in the doubler mode, then the output Signal of the comparator is boosted to provide the
drive to turn the triac on. This interface circuitry can consist of a high voltage transistor and bias resistors.
DISCRETE VS INTEGRATED CIRCUIT AVS.
An IC based AVS circuit should be designed to overcome the disadvantages of the discrete solution that are listed below.
1. Power Dissipation.
Thi's is critical because the entire supply current necessary for the operation .of the AVS circuit comes from the high voltage bus. Every milliampere of current saved in the sensing, comparison and drive circuitry increases the efficiency of the entire system.
PD(AVS)=k*(VAd. (1)
About 80% of the power lost in the AVS scheme
6S2
APPLICATION NOTE
is in the gate drive to the triac. This means that a sensitive gate triac is the best candidate for the switch S1 in Figure 1.
Discrete AVS solutions usually use between 5W and 12W.
2. Immunity to Input Line Voltage Transients.
Most power supplies today are designed to meet IEEE 587 or similar line. transient specifications. We must choose a triac that withstands these transient voltages without any triggering. So we have to make a compromise between low gate drive requirements (IGT) and good static dv/dt immunity. The gate drive circuit of the triac must also be designed to reduce any parasitic voltages at the gate. The gate non- trigger voltage (VGo) of most triacs is about 0.2V.
3. Effect of Line Sags and Surges.
Line voltages are generally considered to vary about +/- 10% from their nominal values. The 120V. nominal can be as high as 132V and the 208V nom. can fall to 187V. Between 132Vac and 187Vac, there exists a window, in which we have to design the threshold voltage of the comparator in Fig. 2. Additional ('strife', etc.) test requirements can reduce this window to a smaller 140V to 170V. An analysis of worst case component tolerances is critical in AVS design.
Ultimately, however, there will always be line voltage waveforms that will fool an automatic voltage selection scheme. One can think of situations where, say, a large motor will pull the line voltage down below the threshold voltage during startup. A good AVS system will monitor the line voltage and protect the power supply . In some applications, the bridge mode (240V mode) is considered the fail safe mode and if the unit starts off in the bridge mode, it should not be able to change modes till the power is recycled.
SGS-THOMSON AVS10 SOLUTION.
We at SGS-THOMSON studied the possibility of an integrated circuit solution for this application. The cost constraints ruled out any exotic single chip solutions and forced us to opt for an 8 pin DIP IC for sensing and a TO-220 triac as the power switch. This IC+triac solution, called AVS10, also offers optimal protection against noise.
In order to maximize the design flexibility and re-
duce turn around time, we chose a semi-custom
solution called ANACA. A 12V CMOS ANACA process used offers mixed analog/digital standard cell capability.
OPERATION OF THE AVS10 CIRCUIT
A typical application diagram for the AVS10 in a power supply is shown in Fig. 3.
Figure 3. AVS10 Application Schematic Diagram
I120V. 6121Hz OR 240V .. 5121Hz
NTC R2
R 1
01
R6
R7
___________ -------------J>..."l ~~i@m~ml~~©~
-'--3_/6
653
APPLICATION NOTE Figure 4. AVS10 Block Diagram
r
,
-
-
-
-
-
-
-
-
-
-
-MODE 7 -
-
-
-
-
-
-
"
"""'--- M2. --11
I
I I
OSC/IN
'----;1
I I I I
__ ~
OSCfO~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ / /
The series circuit of D1, R6, R7 and C2 provide power for the chip. Pin 1, Vss, is a shunt regulator that provides a -9V (nom.) output. R1 and R2 are resistive divider precision resistors that are a measure of the input line. The voltage at Pin 8 varies with the input line. Thus the voltage at Pin 8 is not only a measure of the peak input voltage, but it can also sense line voltage zero crossing. Pins 2 and 3 are inputs to an oscillator. The resistor R3 and C1 set the oscillator frequency. Pin 5 drives the gate of the triac thf;,ough a 3900 resistor. Pin 7 offers the user a choice of two different modes of operation. The block diagram of the IC is given in Fig. 4.
1. Decreased Power Dissipation.
Decreased power dissipation is an important advantage of the AVS10. While most discrete AVS schemes need 5W to 12W of power, the AVS10 uses about 2W. This performance is thanks to an innovative gate triggering scheme (Patent Pending). The gate current is made up of a pulse train that has a typical duration of around 23~s (45kHz+/-5%). The duty cycle of the pulses is typically 10%. The values of R2 and C3 in Fig. 3 are chosen to give us the pulse frequency.
2. Immunity To Voltage Transients.
The triac of the AVS1 0 is a sensitive gate triac
that is specified to remain off when subjected to dv/dt of 50V/~s. Circuit layout is critical in preventing false dv/dt turn on of the triac [2]. The IC of the AVS10 circuit has a built in digital filter that suppresses the effect of all spikes of less than 200~s duration.
3. Operating In The Failsafe Mode.
Vrnode = Vss.
The mode pin on the AVS10 IC, Pin 7 deter' mines the behavior of the circuit if it is turned on into a line surge/sag situation. If Pin 7 is tied to Vss (Pin 1), the AVS10 circuit is in a failsafe mode.. This means that if .the device is turned into a bridge mode, it will remain in the bridge mode, even if the voltage were to suddenly dip into the 11 OV range.
4. Operation In Reactive Mode. Vrnode = VDD.
If Pin 7, the mode pin, is tied to VDD, then the device will switch between bridge and doubler modes if the input voltage changes. If the 11 OV input changes to 220V, then the AVS10 turns the triac off by the next mains cycle. If the 220V input falls to 110V, the AVS10 circuit has a validation period of 8 mains cycles ( when it verifies that the voltage is still at 110V) after which the triac turns on. Thus, safety features are built into the AVS10 circuit. Typical timing diagrams for the two modes are given in Figs. 5 and 6.
-~_6-----------------------~~l ~i~@~~~~~~~~-------------------------
654
Figure 6. Timing diagram· Vmode = Vss Yac(RMS) .
240V 120V
I
TRIAC FIRING ORDER
o
Tdelay
I t
<1 cycle
APPLICATION NOTE
1-TRIAC ON : O-TRIAC OFF
Figure 5. Timing Diagram - Vmode = Vdd
240V 120V
Yac(RMS)
TRIAC ~IRING ORDER I
o
Tdelay
II
<1 cycle
6FF 1=TRIAC ON \ O=TRIAC
I
I
8 cycles <1 cycle
------------J..-yl
~~~@mY:l~~~~
-
-
-
-
-
-
-
-
-
-
-
-
=
-
-
:
5/6
:.
655
APPLICATION NOTE
A detailed account of how to set the input voltage threshold is found in [2].
5. Additional Safety Features.
Additional steps are taken to enhance the safety of design include starting up always into the bridge mode. There is a delay of around 250 ms at start up before the AVS10 goes into the doubler mode.
Hysteresis is also built into the comparator to prevent small line voltage variations from causing toggling between bridge and doubler modes. Only a voltage variation of over 10% of the line voltage can cause the AVS1 0 to change modes.
CONCLUSION
This paper describes an efficient way of implementing an automatic doubler/bridge circuit. The primary use of this circuit is in 75W to 500W SMPS. Other innovative uses are possible. One example would be industrial motor drives which can be designed to accept either 120V line-toneutral or 208V line-to-line input.
The main advantages of the AVS1 0 solution are:
1. High Efficiency. Losses are just 2W vs. 5W-10W for discrete schemes.
2. Safety. Uses digital spike suppression, hysteresis, validation of range, a failsafe mode and good control over. the triac trigger· ing.
3. Space Optimization., small supply resistor. Good reliability.
4. Ease of Use. Eliminates manual line selection errors.
5. Suitable solution for various power range: AVS10 up to 300W AVS12 up to 500W.
REFERENCES.
[1] PSMA Handbook of Standardized Terminology for the Power Sources Industry. Appendix C.
[2] SGS-THOMSON technical note 'How To Use The AVS Kit'.
6/6
656
APPLICATION NOTE
HOW TO USE THE AVS KIT
PRELIMINARY NOTE
I DESCRIPTION OF THE AVS KIT:
The AVS10, or AVS12, is an automatic mains selector to be used in on line SMP supply with Power up to 500W. It is made of two devices.
This switch modifies automatically the structure of the input diodes bridge in order to keep a .same DC voltage range.
!110V OR
C2
nov
------------------ Cl
vss
16K/l %
I
1 MOil %
G AVSo1r0CB AVS12CB
The AVS is compatible with 50 and 60 Hz mains frequency and operates on two mains voltage ranges: - On range I (110 VRMS) the AC voltage varies
from 88 to 132 V and the triac is ON : the bridge operates as voltage doubling circuit.
- On range 1\ (220 VRMS) the AC voltage varies from 176 V to 276 V and the triac is OFF : the circuit operates as full wave bridge.
II PERFORMANCE OF THE AVS : The control of the switch is made by the comparison of the mains voltage (VM on pin 8) with internal threshold voltages (VTH and VH on pin 8).
When mains voltage increases from range I to range II the triac conduction is completly stopped before one mains period because VM > VTH.
When mains voltage drops from range II to range I VM becomes lower than VTH - VH. There are two options (V mode on pin 7) :
- V mode = VDD ; the triac triggering is valided 8 mains periods after power on reset.
V mode = VSS ; the triac control remains locked to range II until circuit reset.
III USE OF THE AVS : Calculation of the oscillator:
AN390/0191
114
657
APPLICATION NOTE
The oscillator frequency is determined by the mains frequency (50 and 60 Hz) and the gate
control : its required value must be 45 KHz ±
5%; so the value of components is : C = 100 pF/5%
R = 91 KOhms/1%
The frequency control is made on pin 3.
Adjustement of the mains mode change:
The measure of the mains voltage is made by a detection of the peak value. The change of mains range is made by adjustement of resistor bridge and we advice:
800 kOhms < R1 + R2 < 2 mOhms
Calculation of the change from range I to range II (on pin 8) :
[VTH . (R1 + R2)]/(R2 . ...J2) + Vreg I ...J2 = max.RMS voltage on Range I
Vreg typ = - 9 V and VTH typ = 4.25 V
Calculation of the change from Range II to range I :
[(VTH - VH) . (R1 + R2)/R2 . ...J2] + Vreg I ...J2 = min. RMS voltage on range II
Vreg typ = - 9 V and VH typ = 0.4 V
Performance of the power on reset:
The power on reset permits the charge of the bulk capacitors of the SMPsupply through soft start circuit. The triac triggering is valided (on range I) after the validation of power on reset (charge of supply capacitor C) and a temporization of 8 mains periods.
T delay = delay time between power on and
triac triggering
Td = 0,89 . Vreg . R . C/[(VRMS . ...J2/n)- R. Iss] + 8/f
f = mains frequency
R = supply resistor = 18 kOhms
C = supply capacitor = 33 flF
VRMS = mains voltage
Iss = quiescent supply current of AVS
Supply of the controller:
The structure of the supply regulator is a shunt regulator and its current must be lower than Iss max = 30 mAo
In order to have a good behavior of the circuit against mains voltage spikes the pin 4 (VDD) of the integrated circuit has to be connected straightly with the A1 of the triac. In same way the supply diode rectifier and R1 have to be connected to the diode bridge (see typical application piagram).
Triac control :
Between pin 5 and triac gate there is a resistor in order to limit the gate current; its value is given by the controller supply and triac ; the required value is 390 Ohms (5%).
Thermal rating of triac:
The knowlegde of the maximum triac current ITM and the current pulse width tp in worst case conditions allows to calculate the losses, PT dissipated by the triac:
ITAM = RMS triac current
= ITM x ...Jtp x ...Jf
PT = 4 . tp . f . hM . VTOln
+ rt . tp . f . (ITM2)
for AVS10CB :
VTO = threshold voltage of triac = 1.1 V rt = on state triac resistance = 49 mohms
for AVS12CB:
VTO = 1V rt = 45 mOhms
The figure 1 of DC general characteristics of triac gives these losses PT versus ITRMs for this application. The figure 2 allows to calculate the external heatsink RTH versus PT and Tamb when Tj = 110C
Tj - Tc = RTH j-c AC . PT
Tc - Tamb = RTH . PT
658
Example on AVS10 :
APPLICATION NOTE
so
IT IRI4S) IA)
o
!J 2 3 ·
6 7 e
Figure 1 and Figure 2 of AVS10 Datasheet
, 10 30 50
100
I'.: .\1\
110 110 130
if tp = 2ms and ITRMS = 5A
- PT = 3.SW
-Tc = 100°C if Tj = 110°C
- RTH = 7.5 °C/W if Tj = 110°C and Tamb< 70°C
Annex: AVS demo board
COMPONENT LIST FOR AVS10.
DESIGNATION
QTE
PRINTED CIRCUIT
1
RESISTANCE
1
RESISTANCE
1
"RESISTANCE
1
RESISTANCE
2
RESISTANCE
1
DIODE
1
CONDENSATOR
1
CONDENSATOR
1
TRIAC
1
INTEGRATED CIRCUIT
1
SUPPORT
1
INVERTER
1
SOCKET
1
PLUG
1
REFERENCE
4751 R1 R2 R3 R4 R6 D1 C1 C2 IC2 IC1
SW1 SL3W
BL3
OBSERVATIONS
MARQUE
1 MOhms 1% 1S KOhms 1% 91 KOhms 1% 9.1 KOhms 1W 390 Ohms 5%
1N4007 100 pF 5% 33J.lF 16V RADIAL AVS10CB / AVS12CB AVS1ACPOS CIS PINS
MINIDIP 3 PINS 3 PINS
SGS-THOMSON SGS-THOMSON
WEIDMULLER WEIDMULLER
_ _ _ _ _ _ _ _ _ _ _ t==' SGS.mOMSON _ _ _ _ _ _ _ _ _ _3_/4
..'Y1 Ii'j]D©OO@I'lu'I'l©1i'OO@[i:!]D©~ 659
APPLICATION NOTE
Products PIN out
VSS Osclin Osc/Out
VDD
TO 220 AB (Plastic)
DIP-8 (Plastic)
Components layout
C2
eCl eeC3
R
0
KO
---1 ---1
EJ --Qg-
~
.5 ~
At
~
~ u··0
V
leI
· s
D G ~
B
G 0
~
Printed circuit layout (Copper side) : 1/1 scale
VM Mode
Nc
VG
- 4 / 4 - - - - - _ - - - - i ....'L SCiS-THOMSON---------·J J , ~U©Ilil@[lllblli©'ITOO@lllU©ij)
660
APPLICATION NOTE
POWER SUPPLY DESIGN BASICS
by P. ANTONIAZZI
Aimed at system designers whose interest focusses on other fields, this note reviews the basic power supply design knowhow assumed in the rest of the book.
In mains-supplied electronic systems the AC input voltage must be converted into a DC voltage with the right value and degree of stabilization.
Figures 1 and 2 show the simplest rectifier circuits. In these basic configurations the peak voltage across the load is equal to the peak value of the AC voltage supplied by the transformer's secondary winding. For most applications the output ripple produced by these circuits is too high. However, for some applications - driving small motors or lamps, for example - they are satisfactory.
If a filter capacitor is added after the rectifier diodes the output voltage waveform is improved considerably. Figures 3 and 4 show two classic circuits commonly used to obtain continuous voltages starting from an altemating voltage. The Figure 3 circuit uses a center-tapped transformer with two rectifier diodes while the Figure 4 circuit uses a simple transformer and four rectifier diodes.
Figure 3 : Full Wave Rectified Output From the Transformer/rectifier Combination is filtered by C1.
D1
5-7644
Figure 4 : This Circuit Performs Identically to that Shown in Figure 3.
Figure 1 : Basic Half Wave Rectifier Cjrcuit.
f\{\
5-7639
Figure 2 : Full Wave Rectifier Wich uses a Center-tapped Transformer.
AN253/1088
Figure 5 shows the continuous voltage curve obtained by adding a filter capacitor to the Figure 1 circuit. The section b-c is a straight line. During this time it is the filter capacitor that supplies the load current. The slope of this line increases as the current increases, bringing point c lower. Consequently the diode conduction time (c-d) increases, increasing ripple. With zero load current the DC output voltage is equal to the peak value of the rectified AC voltage.
Figure 6 shows how to obtain positive and negative outputs referred to a common ground. Useful design data for this circuit is given in figures 7, 8 and 9. In particular, the curves shown in Figure 7 are helpful in determining the voltage ripple for a given load current and filter capacitor value. The value of the voltage ripple obtained is directly proportional to the load cu rrent and inversely proportional to the filter capacitor value.
1/5
661
APPLICATION NOTE
Figure 5 : Output Waveforms from the Half-wave Rectifier Filter.
Vo (V)
b
VAC d
.. a · \ \, '
,, ,
.\ ' I
5-1641
Figure 6 : Full-wave Split Supply Rectifier.
01
"JII
+Vo
GND
-VO 5-761,5
Figure 8 : DC to Peak Ratio for Half Wave rectifiers.
0.05 0.5
3
80
-~r
Rl 70
10
50
30
40
30 100
20
10
0.1
10
100
toDD
Note: C:farads.Rl:Ohms
Figure 9 : DC to Peak Ratio for Full-wave Rectifiers.
Jr5i3lID~ - ,Voe
VM (-,.)
v", RS FULL~WAVE
.0
g, V
80
~V.......- !
70
- --;:/ 60
~ ~ f--
.......-
~ 50 I--
,.-
G-S1S" R
o.
1 3
1
2 3
5
4~
30 0.1
100
100
1000
Figure 7 : Ripple Voltage vs. Filter Capacitor Value (full-wave Reciifier).
VR (Vpp)
I III
v
G 5185
I
l~o~IJ/
~
/
/
2000,uF
0.5
/
/
8000pF
0.2
V
0.1 0.05
0.03 0.05
/
t--
0.1
Q2
~~~~~::E
RECTIFIER
=-=
-t-
as
Figure 10 : DC Characteristics of a 50 VA Non-regulated Supply.
G .. 572/1
Yo
(v )
I
YR
(V pp )
36
:Jlj~ 220V
+
34 32 30 2.
\
"-i'. ...... 1'-. --........
-- " ..f-"'"
I "F300
Vo
-
RIP~ ~ I-"
VOUT(DC)
r--. t-....
O.li
0.8
1.2
1.6
215 662
APPLICATION NOTE
Table 1.
Mains Secondary DC Output Voltage (Vo)
= = = (220V) Voltage 10 0 10 0.1A 10 1A
+ 20% + 15% + 10%
-10% -15% -20%
28.8V 27.6V 26.4V 24V 21.6V 20.4V 19.2V
43.2V 41.4V 39.6V 36.2V 32.4V 30.6V 28.8V
42V 40.3V 38.5V 35V 31.5V 29.8V 28V
37.5V 35.8V 34.2V 31V 27.8V 26V 24.3V
The performance of a supply commonly used in consumer applications - in audio amplifiers, for example - is described in figure 10 and table 1.
When a low ripple voltage is required an LC filter network may be used. The effect on the output voltage of this addition is shown in figure 11. As figure 11 shows, the residual ripple can be reduced by 40 dB. But often the inductor is costly and bulky.
Often the degree of stability provided by the circuits described above is insufficient and a stabilizer circuit is needed. Figure 12 shows the simplest solution and is satisfactory for loads of up to about SOmA. This circuit is often used as a reference voltage to apply to the base of a transistor of to the input of an op amp to obtain higher output current.
The simplest example of a series regulator is shown in Figure 13. In this circuit the transistor is connected as a voltage follower and the output voltage is about 600 - 700mV lower than the zener voltage. The resistor R must be dimensioned so that the zener is correctly biased and that sufficient base current is supplied to the base of 01.
For high load currents the base current of 01 is no longer negligible. To avoid that the current in the zener drops to the point where effective regulation is not possible a darlington may be used in place of the transistor.
When better performance is required the op amp circuit shown in Figure 14 is recommended. In this circuit the output voltage is equal to the reference voltage applied to the input of the op amp. With a suitable output buffer higher currents can be obtained.
The output voltage of the Figure 14 circuit can be varied by adding a variable divider in parallel with the zener diode and with its wiper connected to the op amp's input.
The design of stabilized supplies has been simplified dramatically by the introduction of voltage regulator ICs such as the L78xx and L79xx three-terminal series reg ulators which provide a very stable output and include current limiter and
thermal protection functions. Figures 16, 17 and 18 show how these circuits are used. Refer to the datasheets for more information.
Figure 11: Ripple Reduction Produced by a Single Section Inductance-capacitance Filter.
(dB )
1\
\.
20
"\.
G_5782
L :1
.~r :::r:
\.
f =60Hz
I.
\.
\.
I
\.
I
30
I \
I\. f=120Hz
I
\.
40
\.
10
30
100
300
1000
L(H)· C()JF)
Figure 12 : Basic Zener Regulator Circuit.
Vi -Vo =R
(IL+S)mA
[
Vi
---+----'"'0 Vo=12V
~ r' IL
· Z12
oc-'--------+----o GND
_ _
5·'646
Figure 13 :The Series Pass Zener-based Regulator Circuit can Supply Load Currents up to about 100mA.
1.2Kfl U1
Vi =15V-22V
+----~--o Vo=11.4V
C1 10116V
o--~--+-~----oGND
3/5 663
APPLICATION NOTE Figure 14:The Op-amp-based Regulator can Supply 1OOmA with Excellent Regulation.
RZ
Fig ure 15 : Zener Regulator Circuit Modified for Low-noise Output.
r---------------~~--------~).18V
+ 11.4V
5 -7652
Figure 16 :A Three Terminal 1A Positive Regulator Circuit is very Simple and Performs very Well. 4)( lN4002
Cl 2200/Z5V
C2 10116V
4/5
664
Figure 17 :A Three Terminal1A Negative Voltage Regulator.
4xlN4002
APPLICATION NOTE
1----_--0 Vo
C2
Figure 18 : Complete ± 12V -1 A Split Supply Regulator Circuit.
T1 .=)',-T_+--+_0_4_4_X1_N.,.,1.OO2 01
C1
C2 2200ll'SV
5-7650
'12V
05 1N4001
GNO
10116V
06 1N4001
S _7651
-12V
5/5
665
APPLICATION NOTE
VERY LOW DROP REGULATORS
ENHANCE SUPPLY PERFORMANCE
e'
By Paolo ANTONIAZZI and Arturo WOLFSGRUBER
Standard three-terminal voltage regulator ICs use an NPN transistor as the series pass element, so the input-output voltage drop is 1.5V-2V. Low dropout regulators using lateral PNP pass transistors have been available for several years, but a lateral PNP transistor has low gain, so the base current is necessarily high, and a low fr, so the settling time is poor. Moreover, for stability a large output capacitor is needed.
Applying a new bipolar technology (see APPENDIX: Technology Is The Key) SGS-THOMSON has
developed two 5V low drop voltage regulators that use a new vertical PNP transistor structure to obtain low dropout and low quiescent current.
Type L4940 delivers up to 1.5A and offers an inputoutput voltage drop of 700mV at the fu111.5A output current. A 1A version, type L4941 , has an input-output drop of 450mV at 1A (100mV at O.1A). Both types have a quiescent current of 15mA at 1A (4mA with no load). Consequently these devices dissipates less power, improving the efficiency of any supply system (figure 1).
Figure 1 : A voltage regulator using vertical isolated PNR transistor is more efficient than regulators with NPN pass transistors because the drop out is lower. And it is more efficient than a regulator having a lateral PNP pass transistor because the quiescent current is lower.
(~)
100 90 BO 70 60 50
5
-15·'.
oil
6.4V
"'10·'.~
fYoinr Ltl~.41
t = ?; 25°( 10 = 500 mA
Vo = 5V Vripple =200V
G-6356
.. -15°'·
6.55V VintyP.
6
... -15·'.
B.2V
Yin typo for L7805
· + 10·'·
7
8
9 Vin(V)
AN290110188
1/9
667
APPLICATION NOTE
Compared to other "low drop" regulator the L4940 and L4941 have other advantages: regulation performance is guaranteed right down to the minimum input voltage and the device is stable even without an output capacitor. Additionally, a special circuit limits' the quiescent current for input voltages from 3V to 5V, typically high for low drop regulators because of the saturation of the series regulator.
The two application areas which benefit the most from second generation low drop regulators like the L4940 and L4941 are post regulation and battery supplies. However, the device brings cost savings in any three"terminal regulator application.
LOW DISSIPATION REDUCES SIZE, WEIGHT & COST
In simple series regulator applications the low dissipation of the L4940/1 reduces the size and weight of the mains transformer, heatsink and printed circuit board. A comparison between equivalent 5V/1 A circuits using the L4941 and a standard L7805 regulator (figure 2) shows that the L4941 solution is not only more compact and lighter, it also costs less since the difference in costs between an L4941 and an L7805 is less than the cost saving.
Figure 2: In simple series regulator applications theL4941 can replace standard three-terminal regulators like the L7805, reducing size, weight and cost. Heat dissipation is reduced, too.
jAC -LI NE
:t15%
1 N4001 ~__~"""'_---<II~--I SERI ES
ll
REG.
::_._---+-----41>------4
::
II L-_ _ _......- {
COMPARISON BETWEEN L7805 AND L4941
Component Transformer
Diodes Capacitors
Heatsink PC Area
L4941 Value
220V/7,5V 9.4VA
2x1N4001 4.7flF10V 10flF 20'C/W 20cITf
Cost' $4.8
$0.1 $0.5 $0.1 $0.2 $0.27
L7805
Value
Cost'
220V/8.6V
$5.4
11VA
2x1N4001
$0.1
4.7flF 16V 100n
$0.75 $0.08
10'C/W
$0,3
26cm"
$0.35
$5.97
$6.98
The L4941 solution, excluding the cost of the IC, is thus $1 cheaper. Moreover it is lighter, more compact and dissipates 1.6W less.
* guide price for 1000 pieces.
2/9 668
APPLICATION NOTE
These low drop regulators also bring important benefits in supplies using post regulation, the technique where one or more linear regulators follow another regulator (often switching), to improve precision, reduce ripple and improve transient response. Though lightweight and cheap, an offline switching regulator suffers from poor load and line regulation and needs additional chokes and capacitors to reduce ripple.
Using standard reg ulators the efficiency of post regulation systems is low because the intermediate voltage must be high enough to allow for the post regulator's voltage drop. Moreover, a lateral PNP
low drop regulator has a poor transient response so it cannot reject switching ripple effectively.
If L4940s or L4941 s are used for post regulation the intermediate voltage need only be 1V above the final output voltage and 40dB SVR can be obtained at 30kHz. Consequently less power is dissipated both in the post regulators and in the pre-regulator, making post regulation much more attractive -- designers can now have the precision, low ripple and fast response without sacrificing efficiency.
Figure 3 shows a typical post-regulation power supply using a switching regulator, based on the L4960, followed by L4941 low drop regulators.
Figure 3 : Low drop regulators like the L4941 improve the efficiency of post regulation supplies because less power is dissipated and because the intermediate voltage can be lower. In this typical supply design an L4960 offline switching regulator is followed by L4941 post regulators, giving an high overall efficiency.
1.2K.n.
1--..--o5V-1.5A
5-10325/1
3/9
669
APPLICATION NOTE
IMPROVING BATTERY SUPPLIES
The second application area where the L4940 and L4941 are particularly useful is in battery-powered equipment. Because of their lower dropout these devices need fewer battery cells -- five, compared to the six needed for an NPN regulator. In addition, with five NiCd cells the efficiency is 77-96% and the cells can be completely discharged.
The low quiescent current of the L4940 and L4941 reduces power consumption, prolonging battery life. Moreover, since they will continue to provide a stable 5V output with input voltages as low as 5.45V they also extend. the effective battery life by allowing continued operation when the battery would previously have been discarded (figure 4).
Figure 4: The vertical PNP pass transistor permits a minimum dropout without the penalty of higher quiescent current, giving a 30-50% longer battery life in equipment drawing a constant current two hours a day.
Vin r-______. -______- r______~--------_r------_.------~r_~G~-~63~5~7--
(V)
6 CARBON - ZINC CELLS
10
AT 21·C WITH DISCONTINUOS USE
9
8
7
6
REGULATING
LIMIT OF L4941 - -
5
20
40
60
so
100 (h)DISCARCE TIME
4/9 670
APPLICATION NOTE
Figure 5 shows how an L4941 solution compares with five alternative 5V battery supplies. Figure 5: The L4941 is also useful in battery-powered equipment, prolonging battery life by reducing cur-
rent drain and supplying a regulated 5V output until the battery voltage has fallen to 5.45V. Here the L4941 solution is compared with five alternatives.
R
.>. 5
CELLS..:z:..
1. ZENER REGULATOR -- High current consumption when battery fully charged and high losses in Rser.
2. NPN SERIES REGULATOR -- Needs at least 7Znn/C, 6NiCd or 4Pd cells ..
3. DC-DC CONVERTERS -- Complicated and costly. Generates EMi.and average efficiency <= 75%.
5 to 6 ..:c..
CELLS
4. DISCRETE LOW DROP REGULATOR -- Bulky and perforrns poorly in comparison with integrated solutions.
5/9 671
APPLICATION NOTE
Figure 5 (continued).
5 to 6 CELLS
LM29XX
>47uF
5. LATERAL PNP LOW DROP REGULATORS -High quiescent current, limited output current and stability problems.
5 to 6 CELLS
L4941....-.......-O 10uF
6. L494x VERTICAL PNP LOW DROP REGULATORS -- Need only 6Zn/C cells or 5NiCd celis (which are completely discharged). Quiescent current is low and average efficiency 80%.
HIGHER CURRENT
To obtain more than 1.5A output current a discrete PN P transistor can be added to the L4940 as shown in figure 6. In this circuit Q2 is a current limiter to pro-
tect the external pass transistor when the output is short circuited. An on-chip protection circuit prevents damage to the L4940.
When the load current does not vary greatly higher
Figure 6: An external PNP transistor can be added to the L4941 to obtain higher output current. Q2 is a current limiter to protect the external transistor.
0-100mohm
G1
tIN
MIN
G2 S.5V
1
OUT
5V 1A
100uF
6/9
672
APPLICATION NOTE
output current can also be obtained by using a shunt resistor as shown in figure 7. Figure 7: If the load current does not vary much a simple way to obtain higher current is to add a shunt
resistor.
i.50hlll - 2W
Vin 6.2V
ti5~
L4941
.L
5V - 1.3A tl01
Another way to obtain higher current is simply to connect several devices in parallel as shown in figure 8. This solution also increases the overall re-
liability of the system and is useful also when reliability is of prime importance.
Figure 8: Multiple L4941 s can be paralleled to increase both output current and reliability.
IN
OUT
7/9
673
APPLICATION NOTE
Finally, higher current can be obtained with two.devices in parallel connected to parallel sources (figure 9). This circuit provides an uninierruptable 1.2N5V
output by paralleling the normal line input with a backup battery, which is charged through Rlim when the AC input is present.
Figure 9: Connecting two L4941s in parallel with an AC input and a battery yields an efficient 1.2N5V uninterrutable supply.
AC LINE
7.2U
5U-l.2A
CELLS 5 Ah
NBBL 4941 - 82
USING THE L4941 AS A MODULATOR
Apart from .power supply applications, the L4941 can be used as a modulator (figure 10). The modulator part of this circuit is also useful in the lab as a supply for SVR measurements or generally as a
basic circuit for an amplifier or generator driving resistive loads. The average output voltage can be varied by adjusting the divider on the non-inverting input of the op amp.
Figure 10 :The L4941 can be used as a modulator as illustrated in this circuit.
RUDIO
INPUT 0---1
lUpp Max.~ ·
USUTA
MOO. RM
4.7K
18K
nBS
8/9
"~ '''11 SL'lGilDiS:li·In@~~t!OreiiM'iiiS1@[OlI)NU©~
674
APPLICATION NOTE
APPENDIX: TECHNOLOGY IS THE KEY
In parallel with the emergence of mixed bipolar/DMOS processes, pure bipolar technology has made significant advances, too. One of the most important of these advances? the development of a new power PNP transistor structure -- the isolated collector vertical PNP (ICV PNP) -- which is similar in performance to NPN power transistors.
SON MICROELECTRONICS Multipower-HDS2 p2
(HDS2 p2 = High Density Super Signal/Power Pro-
cess) used to design the l4940 & l4941 low drop regulators, a 20V "Multipower" process which offers NPN & ICV PNP power transistors, small signal NPN & PNP transistors, III logic, ECl logic and a new low leakage diode structure (see fig. 11).
The ICV PNP is a key element in the SGS-THOM-
Figure 11 : Multipower bipolar process with new ICV-PNP (isolated collector vertical PNP), similar in performance to NPN power transistors.
Bee
BEe
C E BC
R KR
ilL
NPN
lev PNP
LLD
s- 9427
This process is characterized by an exceptionally high current density -- 6A1mm2 for NPN transistors;
2A/mm2 for PNP transistors (at VSAT =1V, HFE =10)
-- and very high density in the signal processing section.
Thanks to the lev PNP power transistor structure, designers can choose any output configuration -low side, high side, half bridge, bridge. In addition, the low voltage drop of the ICV PNP is very useful in applications where the dropout voltage is critical in voltage regulators and automotive solenoid drivers, for example.
Another new structure offered by Multipower-HDS2 p2, the low leakage Diode (llD) is very useful in power ICs driving inductive loads. With a parasitic PNP gain about four orders of magnitude lower than
conventional diodes, the LLDs reduce dissipation in the chip -- always an important consideration in power IC design.
Multipower-HDS2 p2 can be applied in simple products where an ICV PNP output stage is needed such as the L4941. Moreover, because it allows the integration of very complex control circuits it is also used for power ICs which integrate a complete power subsystem such as the L6217, a single chip microstepping drive for stepper motors.
A similar process rated at 60V -- Multipower-S2 p2 -- has also been developed. While Multipower-HDS2 p2 is aimed at 10w'voltatJe, high complexity applications, Multipower-S2 P is intended for higher voltage applications with medium complexity control circuits.
9/9 675
APPLICATION NOTE
A DESIGNER'S GUIDE TO THE L200 VOLTAGE REGULATOR
Delivering 2 A at a voltage variable from 2.85 V to 36 V, the L200 voltage regulator is a versatile device that
simplifies the design of linear supplies. This design guide describes the operation of the device and its applications.
The introduction of integrated regulator circuits has greatly simplified the work involved in designing supplies. Regulation and protection circuits required for the supply, previously realized using discrete components, are now integrated in a single chip. This had led to significant cost and space saving as well as increased reliability. Today the designer has a wide range of fixed and adjustable, positive and negative series regulators to choose from as well as an increasing number of switching regulators.
The L200 is a positive variable voltage regulator which includes a current limiter and supplies up to 2 A at 2.85 to 36 V.
The output voltage is fixed with two resistors or, if a continuously variable output voltage is required, with one fixed and one variable resistor.
The maximum output current is fixed with a low value resistor. The device has all the characteristics common to normal fixed regulators and these are described in the datasheet. The L200 is particularly suitable for applications requiring output voltage variation or when a voltage not provided by the standard regulators is required or when a special limit must be placed on the output current.
The L200 is available in two packages:
Pentawatt - Offers easy assembly and good reliability. The guaranteed thermal resistance (Rthj-case) is 3 'C/W (typically 2 'C/W) while if the device is used without heatsink we can consider a guaranteed junction-ambient thermal resistance of 50 'C/W.
TO-3 - For professional and military use or where good hermeticity is required.
The guaranteed ju nction-case thermal resistance is 4 'CIW, while the junction-ambient thermal resistance is 35 'C/W.
The junction-case thermal resistance of this package, which is greater than that of the Pentawart, is
partly compensated by the lower contact resistance with the heatsink, especially when an electrical insulator is used.
CIRCUIT OPERATION
As can be seen from the block diagram (fig. 1) the voltage regulation loop is almost identical to that of fixed regulators. The only difference is that the negative feedback network is external, so it can be varied (fig. 3). The output is linked to the reference by :
Vout = Vret
R2 (1 + - - )
(1 )
R1
Considering Vout as the output of an operational amplifier with gain equal to Gv = 1 + R2/R1 and input signal equal to Vret, variability of the output voltage can be obtained by varying R1 or R2 (or both). It's best to vary R1 because in this way the current in resistors R1 and R2 remains constant (this current is in fact given by Vret/R1).
Equation (1) can also be found in another way which is more useful in order to understand the descriptions of the applications discussed.
Vout = R1 h + R2 i2
and since in practice h " i4 (i4 has a typical value of
10 !lA) we can say that
Vout + R1 i1 + R2 i1 with i, = Vrel R1
Therefore
Vout
R2 =-
R1
Vret + Vret = Vret
(1+
R2 -)
R1
In other words R1 fixes the value of the current circulating in R2 so R2 is determined.
AN255/1288
1/20
677
APPLICATION NOTE Figure 1 : Block Diagram.
INPUT
OUTPUT
L----~---------~~4REFEVROLETANGECE
'--------<~--------_-----------03 5·3928
GROUND
Figure 2 : Schematic Diagram.
2/20
~ . .. , /
Si!GiU©SI!·1ImHI!O.~MIi©SOOOIlN©$
678
Figure 3.
Vs o----------~
APPLICATION NOTE
RJ r-----L-j-------+---+------~V~I
4
OVERLOAD PROTECTION
The device has an overload protection circuit which limits the current available.
Referring to fig. 2, R24 operates as a current sensor. When at the terminals of R24 there is a voltage drop sufficient to make 020 conduct, 019 begins to draw current from the base of the power transistor (darlington formed by 022 and 023) and the output current is limited. The limit depends on the current which 021 injects into the base of 020. This current depends on the drop-out and the temperature which explains the trend of the curves in fig. 4.
Figure 4.
la(mall)
tAl
. . .. .-~.
~~'~.~. :~"l
· · . __ · __ .~. I- ~ _. · · ·
,-.
!
...-----'
'---'J,~
+--tT- _'
-t
t ~ 20,.us -'o.Voo: 2"'.
. ~
I
~--t-~lJ=25·C'....,-___:___' ·· ~- "duty-cyclp.::'-'o I
~
0- _.
·
·
·
·
··
I ·
THERMAL PROTECTION
The junction temperature of the device may reach destructive levels during a short circuit at the output or due to an abnormal increase in the ambient temperature. To avoid having to use heatsinks which are costly and bulky, a thermal protection circuit has been introduced to limit the output current so that the dissipated power does not bring the junction temperature above the values allowed. The operation of this circuit can be summarized as follows.
In 017 there is a constant current equal to :
Vref- VSE17 R17+R16
(Vref = 2.75 V typ)
The base of 018 is therefore biased at :
VSE18 =
Vref- VSE17 R16+R17
·R16=350mV
Therefore at TJ = 25 ·C 018 is off (since 600 mV is needed for it to start conducting). Since the VSE of a silicon transistor decreases by about 2 mVrC, 018 starts conducting at the junction temperature:
Tj= 600;350 +25 =150·C
o
10
20
CURRENT LIMITATION
The innovative feature of this device is the possibility of acting on the current regulation loop, i.e. of limiting the maximum current that can be supplied to the desired value by using a simple resistor (R3 in fig. 2). Obviously if R3 = 0 the maximum output cur-
3/20 679
APPLICATION NOTE
rent is also the maximum current that the device can supply because of its internal limitation.
The current loop consists of a comparator circuit with fixed threshold whose value is Vsc. This comparator intervenes when 10 . R3 = Vsc, hence
10 = ~ (Vsc is the voltage between pin 5
R3 and 2 with typical value of 0.45 V).
Special attention has been given to the comparator circuit in order to ensure that the device behaves as a current generator with high output impedance.
TYPICAL APPLICATIONS
PROGRAMMABLE CURRENT REGULATOR Fig. 5 shows the device used as current generator. In this case the error amplifier is disabled by shortcircuiting pin 4 to ground.
Figure 5.
R 5
V5·2 10=-
R
5-Z4ZS/1
The output current 10 is fixed by means of R : 10 = V5-2 R
The output voltage can reach a maximum value Vi - Vdrop =' Vi 2 V (Vdrop depends on 10)'
PROGRAMMABLE \/,OLTAGEHEGULATOR Fig.' 6 shows the device connected as a voltage regulator and the maximum output current is the maximum current that the device can supply. The output voltage Vo is fixed using potentiometer R2. The equation which gives the output voltage is as follows:
Vo= Vref (1 + R2) R1
By substituting the potentiometer with a fixed resistor and choosing suitable values for R1 and R2, it is
4/2b
680
possible to obtain a wide range of fixed output voltages. Figure 6.
5
The following formulas and tables can be used to calculate some of the most common output voltages.
Having fixed a certain Vo, using the previous formula, the maximum value is :
Vo max = Vref max
(1 +
R2 max ) and the
R1 min
minimum value is :
Vo min = Vref min
(1 +
R2 min R1 max
The table below indicates resistor values for typical output voltages:
Vo ± 4 % 5V 12 V 15 V 18 V 24 V
R1 ± 1 % 1.5 kQ 1 kQ 750 Q 330 Q 510 Q
R2 ± 1 % 1.2 kQ 3.3 kQ 3.3 kQ l.8 kQ 3.9 kQ
PROGRAMMABLE CURRENT AND VOLTAGE REGULATOR
The typical configuration used by the device as a voltage regulator with external current limitation is shown in fig. 7. The fixed voltage of 2.77 V at the terminals of R1 makes it pos?ible to force a constant current across variable resistor R2. If R2 is varied, the voltage at pin 2 is varied and so is the output voltage.
The output voltage is given by :
Vo = Vref · (1 + ~), with Vref = 2.77 V typ
R1
and the maximum output current is given by :
10 max = V~2 with VS-2 = 0.45 V typo
To maintain a sufficient current for good regulation
the value of R1 should be kept low. When there is no load, the output current is Vref/R1. Suitable values of R1 are between 500 Q and 1.5 kO. If the load is always present the maximum value for R1 is
limited by the current value (10 flA) at the input of
the error amplifier (pin 4).
Figure 7.
.I---] R3
'0 V5- 2 (max)= - R3
2 ) .------'-'---., '0 = Vref ( 1 + R
R1
I
L 200
0.23!
":;'"
3 R 1 4 R2 82011
Figure 8.
Figure 9.
R
APPLICATION NOTE
DIGITALLY SELECTED REGULATOR WITH INHIBIT
The output voltage of the device can be regulated digitally as shown in fig. B. The. output voltage depends on the divider formed by R5 and a combination of R1, R2, R3 and P2. The device can be switched off with a transistor.
When the inhibit transistor is saturated, pin 2 is brought to ground potential and the output voltage does not exceed 0.45 V.
REDUCING POWER DISSIPATION WITH DROPPING RESISTOR
If may sometimes be advisable to reduce the power dissipated by the device. A simple and economic method of doing this is to use a resistor connected in series to the input as shown in fig. 9. The inputoutput differential voltage on the device is thus reduced.
The formula for calculating R is as follows:
Vi min - (Vo + Vdrop)
10
5-5518/1
Where Vdrap is the minimum differential voltage between the input and the output of the device at current 10. Yin min is the minimum voltage. Va is the output voltage and 10 the output current.
With constant load, resistor R can be connected between pins 1 and 2 of the IC instead of in series with the input (fig. 10). In this way, part of the load current flows through the device and part through the resistor. This configuration can be used when the minimum current by the load is :
10min =
Vdrap -R-
(instant by instant)
5120 681
APPLICATION NOTE
Figure 10.
R
Vi C>--+------'-I
LIGHT CONTROLLER
Fig. 12 shows a circuit in which the output voltage is controlled by the brightness of the surrounding environment. Regulation is by means of a photo resistor in parallel with R1. In this case; the output vol-tage increases as the brightness increases. The opposite effect, i.e. dimming the light as the ambient light increases, can be obtained by connecting the photoresistor in parallel with R2.
Figure 12.
5 ':151911
SOFT START
When a slow rise time of the output voltage is required, the configuration in fig. 11 can be used. The rise time can be found using the following formula:
CVo R ton =
0.45
At switch on capacitor C is discharged and it keeps the voltage at pin 2 low; or rather, since a voltage of more than 0.45 V cannot be generated between pins 5 and 2, the Va follows the voltage at pin 2 at less than 0.45 V.
Figure 11.
t = C Va R on 0.45
1 Kll
I
Capacitor C is charged by the constant current ie.
.
Vse
le= -R-
Therefore the output reaches its nominal value after the time ton:
Ic · ton
Vo- Vse = - C -
Vo - 0.45 ·R := CVoR
0.45
0.45
LIGHT DIMMER FOR CAR DISPLAY
Although digital displays in cars are often more aesthetically pleasing and frequently more easily read they do have aproblem. Under varying ambient light conditions they are either lost in the background or alternatively appear so bright as to distract the driver. With the system proposed here, this problem is overcome by automatically adjusting the display brightness during daylight conditions and by giving the driver control over the brightness during dusk and darkness conditions.
The circuit is shown in fig. 13. The primary supply is shown taken straight from the car battery however it is worth noting that in a car there is always the risk of dump voltages up to 120 V and it is recommended that some form of protection is included against this.
Under daylight conditions i.e. with sidelights off and T1 not conducting the output of the device is determined by the values of R1 , R2 and the photoresistor (PTR). The output voltage is given by .
Vout = Vrel (1 +
R2 )
PTRl/R1
If the ambient light intensity is high, the resistance of the photo resistor will be low and therefore Vout will be high. As the light decreases, so Vout decreases dimming the display to a suitable level.
6/20 682
Figure 13. BATT.
SIDELIGHT - SWITCH
APPLICATION NOTE
In dusk conditions, when the sidelights are switched on, T1 starts to conduct with its conduction set by the potentiometer wiper at its uppermost positiolQ the sidelights are at their brightest and current through T1 would be a minimum. With the wiper at its lowest position obviously the opposite conditions apply.
The current through T1 is felt at the summing node A along with the currents through R2 and the parallel network R1, PTR. Since Vref is constant the current flowing through R1, PTR must also be constant. Therefore any change in the current through T1 causes an equal and opposite change iri the current
through R2. Therefore as 1r1 increases, Vau! de-
creases i.e. as the brightness of the side-lights is increased or decreased so is the brightness of the display.
The values of R2 and PTR should be selected to give the desired minimum and maximum brightness levels desired under both automatic and manual conditions although the minimum brightness under manual conditions can also be set by the maximum current flowing through T1 and, in any case, this should not exceed the maximum current through R2 under automatic operation.
The circuit shown with a small modification can also be used for dimmers other than in a car. Fig. 15 shows the modification needed. The zener diode should have a VF;:: 2.5 V at 1= 10j.lA.
HIGHER INPUT OR OUTPUT VOLTAGES
Certain applications may require higher lriput or output voltages than the device can produce. The problem can be solved by bringing the regulator back
Figure 14.
2
! R2
.---......-:-_ _~_ _ _ I TI
Figure 15.
!>-SSll
+
5-3997/1
7/20
683
APPLICATION NOTE
into the normal operating units with the help of external components.
When there are high input voltages, the excess voltage must be absorbed with a transistor. Figs. 16 and 17 show the two circuits:
Figure 16.
Figure 17.
SOY
BDX53
Vi
j
Figure 18.
The designer must take into account the dissipated power and the SOA of the preregulation transistor. For example, using the BDX53, the maximum input voltage can reach 56 V (fig. 16). In these conditions we have 20 Vof VCEon the transistor and with a load current of 2 A the operation point remains inside the SOA. The preregulation used in fig. 16 reduces the ripple at the input of the device, making it possible to obtain an output voltage with negligible ripple. If high output voltages are also required, a second zener, Vz, is used to refer the ground pin of an Ie to a potential other than zero; diode D1 provides output shortcircuit protection (fig. 18).
Rsc Vj(max) = 56V. Vz
L 200
1
4
01
r
Vi
j
_J ~YZ~Rl ~.~ vllo
- - 1 l IO,..F
S-l9n'l
POSITIVE AND NEGATIVE VOLTAGE REGULATORS
The circuit in fig. 19 provides positive and negative balanced, stabiliied voltages simultaneously. The L200 regulator supplies the positive voltage while the negative is obtained using an operational amplifier connected as follower with output current booster.
Tracking of the positive voltage is achieved by putting the non-inverting input to ground and using the inverting input to measure the feedback voltage coming from divider R1-R2.
The system is balanced when the inputs of the operational amplifier are at the same voltage, or, since one input is at fixed ground potential, when the voltage of the intermediate point of the divider foes to 0 Volts. This is only possible if the negative voltage, on command of the op-amp, goes to a value which will make a current equal to .that in R1 flows in R2. The ratio which expresses the negative output voltage is:
V-= V+' R2 (If R2 = R1,we'li get V- = V+) R1
8/20 684
Figure 19.
A : V;lm"i " ± 34 V
v 8 : Vi (max) :::; ± 22
Figure 20.
3 < Vo < 30 3 < Vo < 18
APPLICATION NOTE
SincE) the maximum supply voltage of the op amp
used is ± 22 V, when pin 7 is connected to point B
output voltages up to about 18 V can be obtained.
If on the other hand pin 7 is connected to point A,
muGJ;! higher output voltages, up to about 30 V, be obtli.lned since in this case the input voltage can rise to 34 V.
Fig. 20 shows a diagram is which the L165 power op amp is used to produce the negative voltage. In this case (as in fig. 19) the output voltage is limited by the absolute maximum rating of the supply volt-
age of the L165 which is ± 18 V. Therefore to get a
higher Vout we must use a zenerto keep the device supply within the safety limits.
If we have a transformer with two separate secondaries, the diagram of fig. 21 can be used to obtain independent positive and negative voltages. The two output diodes, D1 and D2, protect the devices from shortcircuits between the positive and negative outputs.
L200
lK.Il.
Vo .JIO(Vr 4 )V
A : for ± 18 V ~ Vi ~ 32 V Nole: Vz must be chosen in order
to verify 2 Vi - Vz = 36 V B : for Vi ~ ± 18 V
lKll
IOK.Q. O.1,AJF ..-_-j'=oK=.Q.:r-_ _- .
> = - - - - * - - - - - - - - u - Vo
-Vio-----~-----J
9/20 685
APPLICATION NOTE
Figure 21.
D
Figure 22.
~-lS(,()H
COMPENSATION OF VOLTAGE DROP ALONG THE WIRES
The diagram in fig. 22 is particularly suitable when a load situated far from the output of the regulator has to be supplied and when we want to avoid the use of two sensing wires. In fact, it is possible to compensate the voltage drop on the line caused by the load current (see the two curves in fig. 23 and 24). RKtransforms the load current IL into a proportional voltage in series to the reference of the L200. RK IL is then amplified by the factor
R2 + R1 R1
With the values of Rz, R2 and R1 known, we get:
R - R R1 K - z R1 + R2
Rz, R1 and R2 are assumed to be constant.
If RK is higher than 10 n , the output voltage should
be calculated as follows:
Va = Id RK+ V,et R2 + R1 R1
s
L200 2
t
1
Vi
3
4
Id
R2
Vo
!
I
RK RI
5-5524/1
10/20
686
Figure 23.
----
-
~-
Figure 24.
APPLICATION NOTE
-- ~-
MOTOR SPEED CONTROL
Fig. 25 shows how to use the device for the speed control of permanent magnet motors. The desired speed, proportional to the voltage at the terminal of the motor, is obtained by means of Rl and R2.
VM = Vref (1 + ART2 )
To obtain better compensation of the internal motor resistance, which is essential for good regulation, the following equation is used:
R3 ~ ~ · RM
R2
This equation works with infinite R4. If R4 is finite, the motor speed can be increased without altering the ratio R2/Rl and R3. Since R4 has a constant voltage (Vref) at its terminals, which does not vary as R4 varies, this voltage acts on R2 as a constant current source variable with R4. The voltage drop on R2 thus increases, and the increase is felt by the voltage at the terminals of the .motor. The voltage increase at the motor terminals is :
Vref
· R2
R4+ R3
A circuit for a 30 W motor with RM = 4 n, R1 = 1 kn, R2 = 4.3 kn, R4 = 22 kQ and R3 = 0.82 n has been realized.
POWER AMPLITUDE MODULATOR
In the configuration of fig. 26 the L200 is used to send a signal onto a supply line. Since the iriput signal Vi is DC decoupled, the Vo is defined by :
Vo = Vref (1 + R2) Rl
Figure 25.
RJ
5-1.124 11
The amplified signal Vi whose value is :
Gv=-~
R3
is added to this component. By ignoring the current
entering pin 4, we must impose i1 = i2 + i3 (1) and
since the voltage between pin 4 and ground remains
fixed (Vref) as long as the device is not in saturation,
i1 = 0 and equation (1) becomes:
.12 =- = .13 WI'th'13 -V-i
R3
(forXc «R3) Therefore
Vo=R2 i2=- ~ ·R2
R3
An application is.shown in fig. 27. If the DC level is to be varied but not the AC gain, Rl should be replaced by a potentiometer.
11/20 687
APPLICATION NOTE Figure 26.
Figure 27.
Is
I
L200
2
3
4
......RI[)!Ol IKn
RZ l liZ
R3
~ 13
Vo·vo
"V
:~
!L551SI1
39Kn
"-' v, _ _ O-~~--~----~~----
HIGH CURRENT REGULATORS
To get a higher current than can be supplied by a single device one or more external power transistors must be introduced. The problem is then to extend all the device's protection circuits (short-circuit protection, limitation of Tj of external power devices and overload protection) to the external transistors. Constant current or foldback current limitation therefore becomes necessary.
When the regulator is expected to withstand a permanent shortcircuit, constant current limitation becomes more and more difficult to guarantee as the nominal Vo increases. This is because of the increase in VCE at the terminals of the transistor, which leads to an increase in the dissipated power.. The heatsink has to be calculated in the heaviest working conditions, and therefore in shortcircuit. This increases weight, volume and cost of the heatsinkand increase of the ambient temperature (because of high power dissipation). Besides heatsink, power
transistors must be dimensioned for the short-circuit.
This type, of limitation is suited, for example, with highly capacitive loads. Efficiency is increased if preregulation is used on the input voltage to maintain a constant drop-out on the power element for all VOU!, even in shortcircuit. Foldback limitation, on the other hand, allows lighter shortcircuitoperating conditions than the previous case. The type of load is important.
If the load is highly capacitive, it is not possible to have a high ratio between Imax and Ise because at switch-on, with load inserted, the output may not reach its nominal value.
Other protection against input shortcircuit, mains failure, overvoltages and output reverse bias can be realized using two diodes, D1 and D2, inserted as indicated in fig. 28.
12120 688
Figure 28.
01
, - - - - - ~;(4-----
Figure 29.
APPLICATION NOTE
20V
.v,
Vi 0---.-4-=>+-4 2.50
IOpF
Dl
B20n
!J-'!IS17
S-15J9/l
USE OF A PNP TRANSISTOR
Fig. 29 shows the diagram of a high current supply using the current limitation of the L200. The output current is calculated using the following formula:
I = VSC '" 0.45 V =4.5 A
o
RSC - 0.1 n
Constant current limitation is used ; so, in output shortcircuit conditions, the transistor dissipates a power equal to :
Po = Vi · 10 = Vi · Vsc
Rsc
The operating point of the transistor should be kept
well within the SOA ; with Rsc = 0.1 n, Vi must not
exceed 20 V. Part of the 10 crosses the transistor
and part crosses the regulator.
Figure 30.
The latter is given by : IREG = Is +
VSE -R-
where Is is the base current of the transistor (-100 mA at Ic = 4 A) and VSE is the base-emitter
voltage (- 1 V at Ic = 4 A) ; with R = 2.5 n, IREG :=
500 mA.
USE OF AN NPN POWER TRANSISTOR
Fig. 30 shows the same application as described in figure 29, using an NPN power transistor instead of a PNP. In this case an external signal transistor must be used to limit the current. Therefore:
10 = VSEQ1 Rsc
As regards the output shortcircuit, see par. 1.5.
Rsc lOll.
L 200
5-290'11
13/20
689
APPLICATION NOTE
12 V 4 A POWER SUPPLY
The diagram in fig. 31 shows a supply using the L200 and t.he B0705. The 1 kQ potentiometer, PT1 , together with the 3.3 k resistor are used for fine regulation of the output voltage.
C~rrent limitation is of the type shown in fig. 32. Tnmmer PT2 acts on strech AB of characteristic.
With the values indicated (PT2 =1 kQ, PT3 =470 Q,
R = 3 kQ), currents from 3 to 4 A can be limited. The field of variation can be increased by increasing the value of Rsc or by connecting one terminal of PT to the base of the power transistor, which, however, provides less stable limitation. If section AB is moved, section BC will also be moved.
Figure 31.
The slope of BC can be varied using PT3. The voltage lev~1 at point B is fixed by the voltage of the zener diode. The capacitor in parallel to the zener ensures correct switch-on with full load. The B0705 should always be used well within its safe operating area. If this is not possible two or more B0705s should be used, connected in parallel (fig. 33).
Further protection for the' external power transistor can be provided as shown in fig. 34. The PTC resistor, whose temperature intervention point must prevent.the Tj of the power transistor from reaching its maximum value, should be fixed to the dissipator near the power transistor. Oimensioning of RA and Rs depends on the PTC used.
sw
17V~Yj ~25V
0.22 f.lF
VOUT
12V
IKll
3
0.33 J.JF
lKll
____________ __ L-__~__~~r-
~~
~-SENSE
\
\
I
I
I
+-__ ________ __ o-~~~ -4~__~________________
~
I
-J~L-~_O/P
IN 1,1 1,8 2.7Kll
S-SS28
14/20
690
Figure 32. Vo
(V)
s- 5460 Figure 34.
Figure 33.
APPLICATION NOTE
A
L200
5-5529
VOLTAGE REGULATOR FROM 0 V TO 16 V 4.5A
Fig. 35 shows an application for a high current supply with output voltage adjustable from 0 V to 16 V, realized with two L200 regulators and an external power transistor. With the values indicated, the current can be regulated from 2 A to 4.5 A by potentiometer PT2. PT1, on the other hand, is used for constant current or foldback current limitation. The integrated circuit IC2, which does not require a heatsink and has excellent temperature stability, is used to obtain the 0 V output. It is connected so as to lower pin 3 of IC1 until pin 4 reaches 0 V. 01 and 02 ensure correct operation of the supply at switchon and switch-off.
~-5!i1JO
15120 691
APPLICATION NOTE Figure 35.
2A
.VOU! ZA
!I-!l5J111
POWER SUPPLY WrfH Vo =2.8 TO 18 V, 10 = 0 T02.5A
The diagram in fig. 36 shows a supply with output voltage variable from 2.8 V to 18 V and constant current limitation from 0 A to 2.5 A. The output current can be regulated over a wide range by means of the op. amp. and signal transistor TR2. The op. amp. and the transistor are connected in the vOltage-current converter configuration. The voltage is taken at the terminals of R3 and converted into current by PT2.
10 is fixed as follows :
R410 = 11 (*) PT2
(**) Isc= RVs2c
When 11 = Isc, the regulator starts to operate as a
current generator. By making (*) equal to (**) we get:
R410 -- =
vsc
-
T~erefore
10 =
VSC ---
· PT2
PT2
R2
R2·R4
Diodes D1 and D2 keep transistor TR2 in linear condition in the case of small output currents. If it is not necessary to limit the current to zero, one of the diodes can be eliminated: the second diode could also be eliminated if TR1 were a darlington instead of a transistor.
The op. amp. must have inputs compatible with ground in order to guarantee current limitation even in shortcircuit. With a negative voltage available, even of only &a few volts, current limitation is simplified.
16120
692
APPLICATION NOTE
Figure 36.
...
Bmo5
TRI¥ ,!U..,
'0 R4
'·0
0.111
III
j DZ ZXINIoOOI
~DI
2~ ~
.!!!..
~n
S
.=25V
,I L200 12
lUI I il · nF
[q :ii~ : :Ql]jJF
~v.f!!I 114 LS404
TR2
II~I
RS
Tn
"'!3 jJF
"
~
up· 4-7Kll..L
;..
LAYOUT CONSIDERATIONS The performance of a regulator depends to a great extent on the case with which the printed circuit is produced. There must be no impulsive currents (like the one in the electrolytic filter capacitor at the input of the regulator) between the ground pin of the device (pin 3) and the negative output terminal because these would increase the output ripple. Care must also be taken when i_nserting the resistor connected betWeen pin 4 and pin 3 of the device. The track connecting pin 3 to a terminal of this resistor should be very short and must not be crossed
Figure 37.
5
+
by the load current (which, since it is generally variable, would give rise to a voltage drop on this stretch of track, altering the value of Vref and therefore of Va. When the load is not in the immediate proximity of the regulator output "+ sense" and" - sense" terminals should be used (see fig. 37). By connecting the "+ sense" and "- sense" terminals directly at the charge terminals the voltage drop on the connection cable between supply and load are compensated. Fig. 37 shows how to connect supply and load using the sensing clamps terminals.
A
B
1 3 Cl CZ Vi
2200
j t'F
5- 5 382
_I
o
L·· SGS-THOMSON 'I. IliIDlCli@lIII.IiC1J'llItmJlJIC1ll
17/20
693
APPLICATION NOTE Figure 38.
CAD B
HEATSINK DIMENSIONING
The heatsink dissipates the heat produced by the device to prevent the internal temperature from reaching value which could be dangerous for device operation and reliability: Integrated circuits in plastic package must never exceed 150 'C even in the worst conditions. This limit has been set because the encapsulating resin has problems of vitrification:if~lJbjected to temperatures of more than 150 'C for longperiods or of more,than 170 'C for short periods (24 h). In any case the temperature accelerates the ageing process and therefore influences the device life; an increase of 10 'C can halve the device life. A well designed heatsink should keep the junction temperature between 90 'C and 110 ·C. Fig. 39 shows the structure .of a power device. As demonstrated in thermodynamics, a thermal circuit can be considered to be an electrical circuit where R1, 2 represent the thermal resistance of the single elements (expressed in C/W) ;
Figure 39.
PLASTI C PACKAGE
DIE DIE ATTACH
/
5-5511
Figure 40.
R1
R2
R3
R4
DIE
~- 5;'j\2
DIE ATTACH
C1, 2 I V
the thermal capacitance (expressed in 'C/W) the dissipated power the temperature difference with respect to the reference (ground)
This circu,t can be simplified as follows:
Figure 41.
5-5536
Where Ce is the thermal capacitance of the die plus that of the tab. Ch is the thermal capacitance of the heatsink Rjc is the junction case thermal resistance Rh is the heatsink thermal resistance
But since the aim of this section is not that of studing the transistors, the circuit can be further reduced.
18120
694
Figure 42.
Figure 43.
APPLICATION NOTE
If we now consider the ground potential as ambient temperature, we have:
Ti = Ta + (Rjc + Rh) Po
(1)
Rth= Ti-Ta-RiCoPd
(1a)
Pd
Tc=Ta+RhoPd
(2)
For example, consider an application of the L200 with the following characteristics :
Vintyp = 20 V
] \yp''''' Vo = 14 V
10 typ = 1 A
ooooltioo.
Ta = 4 0 ' C
Vin Vo
=ma1x4=V22
V
-_
10 max = 1.2 A
overload conditions
Ta= 60'C
Pdtyp = (Vin - Vol 010 = (2014) 01 = 6 W
Pd max = (2214)01.2 = 9.6 W
Imposing Tj = 90 'c of (1 a) we get (from L200 char-
acteristics we get Rjc = 3 'C/W).
Rh = 90 - 4~ - 306 = 5.3 'CfW
Using the value thus obtained in (1), we get that the junction temperature during the overload goes to the following value:
Tj = 60 + (3 + 5.3).9.6 = 140°C
If the overload occurs only rarely and for short periops, dimensioning can be considered to be correct. Obviously during the shortcircuit, the dissipated power reaches must higher values (about 40 W for the case considered) but in this case the thermal protection intervenes to maintain the temperature below the maximum values allowed.
Note1: If insulating materials are used between device and heatsink, the thermal contact resistance must be taken into account (0.5 to 1 'C/W, depending on the type of insulant used) and the circuit in fig. 43 becomes :
Note 2 : In applications where one or more external transistors are used together with the L200, the dissipated power must be calculated for each component. The various junction temperatures can be calculated by solving the following circuit:
Figure 44.
This applies if the various diSSipating elements are fairly near to one another with respect to the heatsink dimensions, otherwise the heatsink can no longer be considered as a concentrated constant and the calculation becomes difficult.
This concept is better explained by the graph in
fig. 45 which shows the case (and therefore junc-
tion) temperature variation as a function of the dis-
tance between two dissipating elements with the
same type of dissipator and the same dissipated
power. The graph in fig. 45 refers to the specific case
of two elements dissipating the same power, fixed
on a rectangular q.luminium plate with a ratio of 3 be-
tween the two sides. The temperature jump will de-
pend on the dissipated power and one the device
geometry but we want to show that there exists an
+ optimal position between the two devices:
d =
0 side of the plate
Fig. 46 shows the trend of the temperature as a func-
tion ofthe distance between two dissipating elements whose dissipated power is fairly different (ratio 1 to 4).
G i~I S~DICCIliOSO!·Jnrn!llO.ImM'I!S@OOODI:NII
19120 695
APPLICATION NOTE
This graph may be useful in applications with the L:200 + extemal transistor (in which the transistor generally dissipates more than the L200) where the temperature of the L200 has to be kept as low as possible and especially where the thermal protection of the L200 is to be used to limit the transistor temperature in the
Figure 45.
case of an overload or abnormal increase in the ambient temperature. In other words the distance between the two elements can be selected so that the power transistor reaches the Tj max (200 "C for a TO3 transistor) when the L200 reaches the thermal protection intervention temperature.
Tc (Oe)
70 5
-10 Figure 46.
55 50
.. -7 -5 -3 -2 -1 ' d (em)
:4 5 6 7 8 9 10
." 5-55'6
;I -
-10
150 140 130 120
,A
-- ---TT~
-. B
60
- - ....... ,I . . . . . - - - .-JI
-5:
.,
,5
10
' ..
d (em)
.'
5 - 5517
A : Position of the device with high power dissipation (10 W) B : Position of the device with low power dissipation (2.5 W)
20/20
696
APPLICATION NOTE
DUAL REGULATORS SIMPLIFY MICRO SYSTEM SUPPLY DESIGN
Combining two 5 V regulators and a reset circuit on a single chip, special purpose regulator chips simplify
the design of power supplies for microprocessor systems incorporating battery backup RAMs or shadowtype NV RAMs,
Power supplies for microprocessor systems are often complicated by the need to take care of the special requirements of non-volatile read/write memory. Where battery backup CMOS RAMs are used, for example, it is important to ensure that the RAMs are disabled when the primary supply is removed. And when shadow-type NV memory is included the backup transfer must be initiated and completed when the supply is interrupted. Designed specificalIy for such applications, the SGS-THOMSON Microelectronics L4901 , and L4902 dual voltage regulators combine two 5 V regulators plus a reset circuit on a single chip, simplifying the designer's task.
Assembled in the SGS-THOMSON Heptawatt [TM] 7-lead package, the L4901 and L4902 contain separate voltage regulators rated at 5 V/300 mA (the "V1" output) and 5 V/400 mA (the "V2" output).
Both the V1 and V2 regulators have an output volt-
age precision of ± 2 % and include protection
against output short circuits and 60 V input tran-
sients. Also included on the chip is a reset circuit with externally programmable timing which depends on the input voltage and the output of the V1 regulator. Functionally, the two devices are identical except that the L4901 has separate inputs to the two regulators and the L4902 has a common input plus a disable input which controls the V2 output (fig. 1). Generally the V1 regulator is used to supply circuits which must be powered continuously - volatile memory, a time-of-day clock and so on - while the V2 output supplies other 5 V circuits which may be powe red down when the equipment is inactive.
The V1 output features a very low leakage current at the output - less than 1 !lA - to allow the use a backup battery. The V1 regulator also features a low quiescent current at the input (0.6 mA typical) to mi-
nimize battery drain in applications where the V1 regulator is permanently connected to a battery supply.
Figure 1a : TWO 5V OUTPUTS - The L4901 Dual Regulator Provides 300 mA and 400 mA 5 V Outputs and Includes a Microprocessor Reset Function. This Device is Ideal for Microprocessor Systems with Battery Backup or Shadow RAM.
± 111 !N
"OnF III IN
AN256/0189
1/7
697
APPLICATION NOTE
Figure 1b : DISABLE INPUT - The L4902 is Similar to the L4901 but also Features a Disable Input for the V2 Regulator.
IN
I
l4902
7 Vl0UT
DISABLE
5- '3)()7
Figure 2: WAVEFORMS - An Important Feature of the L4901 Series Regulators is that the Reset Circuit Monitors the Input Voltage.
I I I
v I I
I I 02 ~--+--I
SWITCH
ON
VOl OVERLOAD
V02
VIN
OVERLOAD OVERLOAD
IRD
THERMAL
SHUT
SWITCH
DOWN OFF
2/7
698
APPLICATION NOTE
VERSATILE DEVICES
The L4901 and L4902 are versatile devices which simplify the supply circuitry of many systems and can be used in a number of different ways.
One possibility, outlined in figure 3, is to connect the V1 regulator permanently to a battery to supply a CMOS time-of-day clock and a CMOS microcomputer chip with volatile memory. In this example the V2 output supplies non-essential 5 V circuits. A typical use of this scheme is in trip computers or car radios with programmable tuning.
An alternative, shown in figure 4, is to use the L4901 with a backup battery on the V1 output to maintain a CMOS clock and a standby-type NMOS microcomputer chip. In this case the main on/off switch disconnects both the V1 and V2 regulators from the battery.
Figure 5 illustrates how the L4902's disable input may be used in a CMOS microcomputer application. In this example the V2 output, supplying non-essential circuits, is turned off under control of the micro-
processor circuit. Configurations of this type are used in products where the "OFF" switch is part of a keypad scanned by a micro which operates continuously, even in the "OFF" state.
The L4901 is also ideal for microcomputer systems using battery backup CMOS static RAMs. As shows in figure 6 the V1 output supplies the CMOS RAMs and the V2 output supplies the microprocessor plus other 5 V circuits. The L4901 's reset output is used both to reset the Z80 and, through the M74HC138 address decoder, to ensure that the RAMs are disabled as soon as the main supply voltage starts to fall. Note that the M74HC138 is supplied from the backup battery.
It is important to make sure that the RAMs are disabled because the lithium cells used as backup batteries have a high internal resistance. If the RAMs were not forced into the low consumption standby state the battery voltage could drop so low that memory contents are corrupted. Moreover, to prevent latch up, no input of a CMOS RAM should ever be higher than the supply Voltage.
Figure 3: LOW QUIESCENT CURRENT at the V1 Input makes the L4901 Useful in Applications like this where the V1 Regulator is always connected to the Battery.
BATTERY
l.
INI O.22 ..... F I
FI l .....
ICT
10nF
REG. 1
REG. 2 4
5 RESET OUT
RESET
CMOS IJP WITH VOLATILE
RAM
Voo
RESET
OTHER LOGIC
@5V
5_7710
3/7
699
APPLICATION NOTE Figure 4 : LOW LEAKAGE at the VI Output makes the L4901 Ideal for Battery Backup Operation.
'''"'i ~Y
INI
I
REG.'
1.
,,",±IN 2
2
REG. 2
...~3
CT
T 10nF
.J..
1
J 7 OUTI I.LDI < 2IJA Voo
~.
CMOS CLOCK
~J.JF
~~
VSB
Y BACKUP BATTERY
IJP(3875-2875)
6
OUT2
~ ItoIOJ.JF
I
VIO RESET
WITH BATTERY BACKUP RAM
VDO 5 RESET OUT RESET
OTHER LOGIC
@ 5V
'=>_7771
Figure 5: STANDBY - The L4902 can be used in Applications where the Supply is connected Permanently and the Disable Function Used to Turn Off on-essential Circuits in the Standby State.
J:.
ICT
10nF
REG.1 REG. 2
4
7
OUT 1
VOO
I'J.JF 3 V02 DIS 6
5 RESET OUT
VDD OUT PORT IN PORT
CMOS IoJp WITH VOlATILE
RAM
__Voo
Rf.5£T
OTHER LOGIC
~5V
5-7843
IDEAL FOR SHADOW MEMORIES
Another interesting application forthe L4902 is supplying a shadow-ram microcomputer chip like the SGS-THOMSON M38SH72 where a fast non-volatile memory is backed up on-chip by a slow EEPROM (figure 7). For these chips it is important to
ensure that the backup command is generated when the supply is removed, a function which the L4902's reset output can perform. Since the L4902's reset function depends on the INPUT voltage the power fail condition is sensed early enough to guarantee that the backup transfer will be successful.
4/7 700
APPLICATION NOTE
In figure 7 the reset output is forced low when the input voltage falls below 6.3 V or when the V1 output goes below 4.S V. This allows 10 Ils for the backup transfer (with 10 IlF capacitors) which is more than sufficient.
Similarly, the L4902 can be used with shadow-type RAMs such as the Xicor X2201. In the figure S circuit a capacitor on the V1 input ensures that the X2201 is powered during the transfer operation. When the input voltage is removed or goes below 6.3 V the L4902's reset output, connected to the SOS5's TRAP input, forces the execution for a service routine which saves the state of the machine in the RAM then issues a backup command. The V2 output drops immediately while the 6S0 IlF capacitor on the V1 input provides enough energy to keep the X2201 running for the 10 ms needed to com-
plete the backup transfer. The low consumption of the V1 regulator allows the use of a relatively small capacitor for this function.
ADiNG A WATCHDOG
By adding a few components and two Schmitt trigger gates a watchdog function can be added tothe L4902 (figure 9). Normally an output port of the micro will supply a software-generated pulse at least every 10 ms. If something has gone wrong in the software or hardware and these pulses are missing the disable input will be activated after a period set by R1.C1, disabling all the circuitry connected to the V2 output of the L4902. The disable period could be usefur to prevent spurious operation of motors and so[enoids while the control processor is ma[funtioning.
Figure 6 : CMOS RAMs - The L4901 is Useful in Systems with Battery Backup CMOS RAMs Because the Reset Output can be used to Ensure that the RAM Chips are disabled to Reduce Battery Drain when the Main Supply is removed.
LI ,.,
/2,'2:r~: '
,
CUll
oon
L~,I.'~
"" l4901
J : ". '
I "'no
TO OTHER
5.V CHIPS
10nF.:t~: CT
R(Ser ~l -
(",ND
..l!
, - - en
. - R/W
J.
[
L ~ .ESE'
woU L-..., 01
'DD
YO
MR[Q
ZB4DO
."
L
rn
ii
" rn
-
M74HCl38
----_C
Yr-
. ." f------- ·
."
Yi-
;S I-
TO OTHER M(MORT CHIPS
l&f--
nI-
l.
l
~-1D1111
1"00
,@-..
.~
..040S
.., '5TATIC
LIKE
TC~516
00 T~565
J.
1 1.8tolV un..... BATT[AV
5/7 701
APPLICATION NOTE
Figure 7: NV MEMORY ~Cs - The L4902 is also Useful for Supplying Chips like the SGS-THOMSON M38SH72 Single-chip Micro with NV Memory. In this Application the Reset Circuit initiates the RAM-to-shadow Transfer.
Vi DISABLE
I
Vol 7
1> 6 Vo2
TO OTHER 5V CHIPS
~ F
L4902
:c 3
4.7 f'F
5
2 4
I 100nF
s· 3)62
VDD
M38SH72
RESET VSH
GND
Figure 8 : SHADOW RAMs - The L4901 's Reset Function also serves in Systems using Shadow Type NV RAMs like the X2201 to ensure that the Backup Transfer is executed Correctly.
Vi
INI
J: 680 ,..F
OUT I 7
v'"
J: 10}JF
X2201
L4901
IN2
OUT 2 6
10f'F
I
3 CT
lonFI
RESET 5 GND
4
'Ie;, ADDRESS
TRAP
DATA
8085
S-8a~~ "
6/7 702
APPLICATION NOTE
Figure 9 : With a CMOS Schmitt Trigger and a few Components a Watchdog Function can be added for Critical Application.
~------------------------------~__------~VDD
10K A
- - - - - - - - - - - - -I
OUTPUT PORT
I
: JlJ1Jl
7/7
703
APPLICATION NOTE
LOW DROP VOLTAGE REGULATORS FOR AUTOMOTIVE ELECTRON ICS
By S. CISCATO
Linear voltage regulators with an input-output voltage drop of less than 2Vare used to ensure continuity of
the stabilized output in applications where a battery supply is used. This note describes the characteristics
and operation of these devices.
Low drop linear voltage regulators are low voltage (5 to 12V) regulators which are able to provide effective stabilization of the output voltage even when the difference between input voltage and output voltage is less than 2V.
This situation can arise accidentally for a brief period when the main supply source is overloaded. It may also result from a deliberate design decision aimed at reducing the power dissipated in the supply - for example, when the device is used as a post regulator in portable instruments.
Low drop regulators are used widely in automotive applications, a field where integrated circuits have to be particularly rugged. For this reason most low drop devices include protection functions not found in standard regulators. Before describing the SGS THOMSON family of low drop regulators we will therefore begin with a brief description of the automotive electrical environment.
Figure 1 : Cold Starting Supply Voltage Drop.
14V - - - - - - _ _ _ _ 12V
CHARGING ALTERNATOR
-6V
~
COMPRESSION STROKE
I
I
KEY I KEY I OFF ON
STARTING TIME
, MOTOR RUNNING t
AUTOMOTIVE ENVIRONMENT
In addition to the battery voltage drop during starting, the automotive field presents a number of other serious problems concerning the regulator input voltage: positive and negative high energy I high voltage transients (load dump and field decay), positive and negative low energy/very-high-voltage spikes (switching spikes), battery reversal and battery voltage doubling.
All of these hazards must be withstood by the regulator without damage over an ambient temperature range very close to military standards (- 40 to + 125"C for underhood devices; - 40 to + 85"C for other devices). Moreover, an output voltage preci-
sion of ±4% to ±2% is required overthe whole tem-
perature range and in all conditions of input voltage and load current.
BATTERY VOLTAGE DROP
During motor starting the battery is overloaded by a peak current of up to 1OOA drawn by the starter motor. In this condition, which persists for 20~30ms, the battery voltage drops to about 6V in very.cold weather (figure 1).
Using standard regulators with a dropout of 1.7V to 2.1V the minimum 4.75V supply necessary for essential functions such as ignition, injection and electronic engine control cannot be guaranteed. Another unfortunate consequence is the loss of RAM memory contents in car radios and trip computers.
A voltage regulator with a voltage drop of less than 1.2V is therefore necessary.
BATTERY VOLTAGE DOUBLING
To aid cold weather starting with a partially flat battery, sometimes two batteries are used in series, doubling the Voltage. Regulators must therefore withstand input voltages of 24-26V without disturbing operation.
BATTERY REVERSAL
Voltage regulators must be protected internally against negative input voltages to guard against accidental.battery reversal.
LOAD DUMP TRANSIENTS
Load dump transients are high voltage, high energy positive transients.
AN254/1088
1/8
705
APPLICATION NOTE
The response time of the output voltage of an alternator to load variations is very long because of the long time constant of the excitation winding and mechanical inertia.
When the load is reduced instantaneously (by turning off lights, cooling fans and so on) the output voltage of the alternator tends to present a positive peak, the amplitude of which depends on the speed of rotation and the excitation current.
During normal operation this does not cause problems because of the high capacity of the battery which, connected in parallel with the alternator output, is able to absorb the transient energy without a sig nificant increase in Voltage.
However, motor manufactures impose the standard that electronic devices must be protected against load dump transients because it is possible for the connection between battery and alternator to break.
The worst case voltage peak occurs when the battery-altemator cable is disconnected with the battery discharged and the motor running at its fastest rotation speed. In this case, the load variation is at a maximum and the voltage peak reaches a value comparable with the no-load output of the alternator running at maximum speed with the maximum excitation current.
Figure 2 shows a typical load dump waveform.
Motor manufacturers require that voltage regulators are able to protect themselves and the load against peak voltages of 60 - 1OOV with an equivalent series resistance of 0.1 to 1Q, depending on the type of alternator and external protection device used.
Figure 2 : Load Drump Transient.
(V)
VM =60V to laOY
,I>< RISE TIME 3: 5ms
--- .......
(ms
100
200
300
400
S~8061
FIELD DECAY TRANSIENTS
Field decay transients are high energy, high voltage
negative transients.
'
If the ignition switch is turned off while current is flowing in inductive loads (electric motors, alternator field coil and so on) a negative voltage transient appears
on the supply rail. The peak value in modulo of this transient is of the same orderof magnitude as a load dump transient. In this case, too, the regulator must protect itself and the load.
SWITCHING SPIKES
Windscreen wiper motors, lamp flashers and ignition sparks behave as high frequency noise generators with an equivalent series resistance of 50 to 500 Q. The energy associated with these transients is much lower than load dump or field decay transients but the negative and positive peaks can reach 200V. Figure 3 shows the voltage waveform which the. regulators must withstand.
Figure 3 : Switching Spikes.
""1TI h:PAUSE 90ms
__ J~VJ__
100 \0200'01
--
GNO
RISE TIME,. 50 ns TlME CONSTANT = lOOns
100fS
10ms
PAUSE 90 inS
5-8062
REGULATOR DESIGN
DROPOUT
The dropout voltage of a linear voltage regulator can be defined for a given output current, 10, as the minimum difference between input and output voltage below which the output voltage is 1OOmV lower than the voltage measured at 10 with the nominal input Voltage. The current 10 must be specified since the dropout voltage increases as the load current increases .
To obtain a dropout voltage of 0.05 to 1V with an output current of 10 to 50mA, the regulator types L387A, L487, L47XX, L48XX, L4920, L4921 , LM2930A and LM2931A are configured with a PNP series-pass transistor as shown in figure 4. The PNP transistor is connected in the common emitter configuration and can therefore operate in saturation, yielding the low dropout voltage desired.
For higher dropout values an NPN series-pass element in emitterfollower.configuration may be used. This approach, shown in Figure 5, is used in the L2600 series regulators which have a' maximum dropout voltage of 1.9V at 500mA.
2/8
706
APPI-ICATION NOTE
Figure 4 : PNP Series Pass Transistor in Common Emitter Configuration for very Low Drop Out Voltage Regulators.
IN
OUT
GND
5-8064
Figure 5 : NPN Series Pass Transistor in Emitter Follower Configuration.
IN
OUT
o---------~-------L---O
GND
CURRENT CONSUMPTION/QUIESCENT CURRENT
The circuit configurations shown in figures 4 and 5 behave differently as far as concerns the current consumed by the device but not delivered to the load. In the case of figure 5, this current is that necessary forthe functioning of the auxiliary circuitry of the regulator (voltage reference, op amp and so on). The base current of the output transistor flows into the load.
In the Figure 4 circuit, in contrast, the base current of the output transistor does not flow through the load and, particularly in saturation, depends heavily on the load current.
Normally lateral PNP transistors are chosen for ICs because they can withstand high positive and negative overvoltages. When negative overvoltages at the input do not occur, or are eliminated by external protection devices, vertical PNP transistors can be used in place of lateral types.
Since vertical PNP transistors have higher gain the current consumed in the regulator is significantly reduced. Vertical PNP transistprs will be used in future designs.
VOLTAGE REFERENCE
The wide operating range of input voltage (6 to 26V) and ambient tef11perature ( 40 to 125 DC) over which high output voltage precision is required means that a well stabilized voltage reference musi pe used.
All low drop regulators use bandgap type voltage
references (see figure 6). In this structure the two
transistors Q2 andQ1 have an emitter area ratio of
10 and carry equal collector currents imposed by the
current mirror Q3, Q4, Q5. In'these conditions the
base-emitter voltages of 01 and 02 differ (at 25 DC)
~:
.
KT A(Q2) VBE = - - 1n - - = 60 mV
q A(01)
A(Q2)
.
.
where A(Q1) = 10 (emitter area ratio)
KT - =26mV
q
K = Boltzmann's constant
T = Temperature in Kelvin
q = Charge on an electron
Figure 6 : Bandgap Voltage Reference Circuit in Low Drop Voltage Regulators.
1K n
05
04
03
:1------"'01-'- - 0 vREF
, x
5- 80 65
3/8
707
APPLICATION NOTE
The rejection of Vrel to variations in the supply voltage is improved by supplying the reference circuit from a stabilized voltage. This is achieved in the L26XX, L48XX, L4920, L4921, LM2930A and LM2931A regulators by means of a preregulator. In the L487, analysing the Figure 6 circuit gives:
B!. Vrel = VBE (01) + 2 L1 VBE (02, 01) R2 " To maintain'Vrel constant as temperature varies it
i~ necessary that d dVTrel = 0 which implies choo-
sing
R2 so that 2R2 . ~ + dVBE(Ol) = 0
R1
R1 T(25')
dT
where T(25 ') = 298 K
d VBE ( 0 1 ) .
. .
dT = negative temperature coeffiCient of
the base-emitter voltage.
In L387A and L47XX regulators, in contrast, the supply to the bandgap is switched from the input to the output as soon as the nominal output voltage is reached (figures 7, 8, 9). The variation in output voltage with temperature is shown in figure 10.
Figure 7: Block Diagram of L2600 Series Regulators.
Figure 8 : Block Diagram of L387A and L487 Series Regulators.
IN
OUT
GND
s- 8067
Figure 9 : Block Diagram of LM2930A, LM2931A and L4800 Series Regulators.
OUT
OUT
Figure 10: Outputs Voltage vs.Temperature.
GND
4/8 708
·.9 I---.L.,.-.l--r+++-+-H-++-+-!-'-+t-H
~40 -20 0 20 40 60 eo 100
Tj C-C)
APPLICATION NOTE
PROTECTION AGAINST HIGH ENERGY TRANSIENTS
To protect the LM2930A, LM2931A, L4920, L4921 and L48XX regulators against high-voltage, highenergy positive transients the basic circuit shown in Figure 11 is used. The zeners in this circuit limit the supply voltage to the maximum operating value and turn off the output stage. The output transistor can thus withstand voltages up to the BVCES , breakdown voltage.
In the other regulators (L487, L387A, L47XX and L26XX) the supply to the internal circuits is also turned off.
The speed of intervention of these protection schemes is fast enough to ensure that the regulator can withstand high energy transients with a rising slope of 1OV/IlS without problems, interrupting normal operation only momentarily.
Protection against negative transients is provided by the high series impedance of the possible current paths and the reverse BVBEO breakdown voltage of the lateral PNP transistors (BVCBO).
The breakdown voltages BVCES and BVCBO depend on the technology therefore the transient capability is ± 60V, ± 80V or ± 1OOV for the various types.
Figure 11 : Overvoltage Protection Circuit.
PROTECTION AGAINST LOW ENERGY OVERVOLTAGES As shown in figure 3, the low energy overvoltages which the devices must resist have very brief rise time and can exceed the breakdown voltages. The protection schemes described above are therefore' insufficient. However, since the energy associated with these transients is very low, the regulators can withstand them without problems. Nevertheless it is advisable to place a capacitor of around 1OOn F at the input. All of .the low drop regulators except the L26XX types need a compensation capacitor at the output. This capacitor also provides extra filtering for low energy transients because it has a low impedance at high frequencies.
Figure 12 : Thermal Protection Circuit.
~>---------jl TRA~AS~~TOR ~
vREF
DRIVER
IN
FROM OP. AMP
DRIVER
GND
s - 8069
GND
5- 8070
THERMAL PROTECTION
When the junction temperature exceeds the safe maximum for the device a thermal protection circuit (figure 12) holds the output transistor off until the overtemperature condition has passed.
In the figure 12 circuit the resistors R1, R2 and R3 are calculated so that the base voltage of 01 is 600mV, thus preventing the conduction of 01 and
02.
As the junction temperature increases the minimum VBE for conduction of the two transistors fall until, at abo.ut 15 "C, 2 VSE =600mV, the two transistors con-
duct and 02 turns off the output transistor driver.
CURRENT PROTECTION
In the L487, L387A and L26XX regulators the output current is limited to its maximum value in the event of a short circuit. A special circuit acts on the base of the output transistor, preventing the output current from exceeding the limit set for the duration of the overload.
5/8 709
APPLICATION NOTE
In the L4920, L4921 , LM2930A, LM2931 A and L48XX regulators a foldback circuit (figure 13) is used.to limit the power dissipated in both the devices and the load in short circuit conditions. The current is limited to.a low value (Isc) of about 200 mAas soon as it exceeds the maximum value. The output voltage in this condition reaches a value corresponding to the current Isc flowing through the load. When the overload condition is removed the output voltage only returns to the nominal load value if the new static load line does not intersect the negative slope region of the curve in figure 13. If it does, the new operating point will be at the intersection. It is important to note that when power is applied, if the load line intersects the curve in the negative slope region, the regulator will operate with a lowerthan-nominal voltage. This can happen with a passive load greater than the normal load (even if it is less than the maximum load 1M) or with' active loads such as a current sinker which draw more than Isc even at low voltages (figure 13, curve 3).
Figure 13 :1} Acceptable Load Line for Turn-on 2} Unacceptable Load Line for Turnon.
v0 r-r-TT--.-r-.--r-r-TT--.-r-.--r-r-.-T'--T"51181
Iv 1 H-+++-t-+-+-t-+++-t-+-H-++-H--1
3 1
~~~~~~~~~~~j=
200
~OO
500
600 lo(mAl
EXTERNAL COMPENSATION
Since the purpose of a voltage regulator is to supply a fixed output voltage in.spite of supply and load variations, the open loop gain of the regulator must be very high at low frequencies. This may cause instability as a result of the various poles present in the loop. To avoid this instability dominant pole compensation is used to reduce phase shifts due to other poles at the unity gain frequency. The lower the frequency of these other poles, the greater must be the capacitor used to create the dominant pole for the same DC gain.
Where the output transistor is a lateral PNP type there is a pole in the regulation loop at a frequency
too low to be compensated by a capacitor which can be integrated. For the L487, L47XX, L48XX, L387A, LM2930A and LM2931 A external compensation is therefore necessary so a very high value capacitor must be connected from the output to ground.
The parassitic equivalent series resistance of the capacitor used adds a zero to the regulation loop. This zero may compromise the stability of the system since its effect tends to cancel the effect of the pole added. In regulators this ESR must be less than 3Q and the minimum capacitor value is 47 F (100 IlF for L4800 series).
In the L2600, which uses an NPN power transistor, the stabilization capacitor is small enough to be integrated so no output capacitor is needed. Indeed, if an output capacitor is used it may cause oscillation unless it is greater than 100 IlF, in which case it would itself be the dominant pole. If an electrolytic capacitor of more than 100 IlF is used, a small capacitor must not be added in parallel or with the ESR of the electrolytic it would from another pole, worsening the stability of the system.
TURN-ON WITH CAPACITIVE LOADS
A load which presents a significant capacity between the output and ground (including the external compensation capacitor) will be seen by the regulator as a short circuit when power is applied. The regulator therefore delivers the short circuit current until the load capacitor has been charged to the nominal value.
This factor is extremely important for the dimensioning of the power source. Even a very small DC load can in such cases behave like a maximum load and the power drained from the supply is the sum of the short circuit current delivered to the load and the maximum current consumed in the regulator.
Moreover, as explained above, in regulators with foldback protection the static load line must not cross the negative slope region of figure 13 or the output voltage will not reach the nominal value when power is applied.
SPECIAL FUNCTIONS
RESET The L387A and L487 include a power on/off reset function which inhibits the operation of circuits supplied by the regulator when the output voltage is too low (4.7SV) to guarantee correct operation of logic (figure 14). To avoid malfunctions a delay is also introduced so that the enable signal is only issued some time after the safe output voltage has been reached.
6/8 710
APPLICATION NOTE
Figure 14 : Reset Timing Waveforms.
OUTPUT
3.7
DELAV
CAPACIT.
t1I RESET
$-B072
The reset circuitry (figure 15) consists of : _ a comparator connected between the voltage reference and a tap of the output divider, the voltage of which is higher than the feedback voltage;
an SCR to memorize any brief glitches in the output voltage that can cause some trouble with the logic.
_ a delay circuit with an external capacitor charged by an internal current source
This function has been integrated into the voltage regulator to exploit the basic advantage of taking information at the source. The use of double calibrations can thus be avoided.
For the correct operation of the reset function, two basic relations must be satisfied in all cases
Vres max < VOU! min
(1 )
Vresmin > 4.75 V
(2)
where Vres maxIVres min are maximum/minimum va-
lue for the reset signal going high-low.
(1) means that the RESET signal must be high when the device is regulating
(2) means that the RESET signal must be low when the output voltage goes under 95 % of the nominal (5V). Expressions (1) and (2) can be rewritten as:
(Vres max Vres min) + (Vnom YOU! min)
(3)
< Vnom 4.75V
This means that the sum of all the errors in the worst case must be less than 5 % (250mV).
_ absolute spread of the reference _ error due to the load regulation (1 % max) _ error due to the offset of the reset compara-
tor and error amplifier (0.5 %) _ errors due to the output divider (0.5 %) _ hysteresis of the comparator to speed up the
transitions (50mV that is 1 % referred to 5V
output)
Figure 15 : Schematic Block Diagram of a Voltage Regulator with Reset Function.
...,
IN
I
I
I
I L __
I
5- 80 71
7/8 711
APPLICATION NOTE
VARIABLE OUTPUT VOLTAGE
The L4920 and L4921 are structurally identical to L48XX series regulators except that the voltage divider in the feedback loop is available externally (figure 16). The output voltage can therefore be varied from 1.25V (the reference voltage) to 20V. It should be noted, however, that the minimum input voltage is 5.1 V for operation with output voltages
below 4.5V (otherwise the internal circuits will not work). For output voltages above 4.5V the input voltage must be at least equal to the output voltage plus the dropout voltage. The L4920 and L4921 are therefore low dropout regulators only for voltages above 4.5V.
A value of 6 Kn is recommended for R2 to match the internal circuitry.
Figure 16 : The L4920 and L4921 are Structurally Identical to L48XX Series Regulators Except that the Voltage Divider in the Feedback Loop is Available Externally.
IN PUT
1
IPREREGI..lATOR
1
illI
BANDGAP
REFEPENCE AND
ERHOR
1
AMPLIFIER
I
1 I DUMP . PROTECTKlNJ
[
I, 1 THeRMAL PROTECTION
I I FOLDBACK C~~~i~; I
1
!._791&1"
OUTP UT Rl
A D J U 5T R2
GN o
8/8 712
POWER MOS & IGBTS
713
APPLICATION NOTE
SAFE BEHAVIOUR OF IGBTs SUBJECTED TO dV/dt
by R. Lelor, M. Melilo
ABSTRACT
When an IGBT in the off state is subjected to a high dV/dt, parasitic turn-on can occur leading to additional losses. This paper describes the phenomenon and indicates the main parameters influencing this behaviour. Several methods of suppressing this parasitic phenomenon are described. Using a suitable design of gate drive, it is possible to increase the circuit reliability in all conditions. Practical examples and measurements are ~iven ..
INTRODUCTION
The behaviour of IGBTs subjected to a dV/dt differs according to the working conditions. We can consider two distinct cases:
- static dV/dt
The static condition occurs when the dV/dt applied to an IGBT in the off state, acting through the reverse capacitance C9 "" Cres ' causes the gate voltage to rise turning the device on. This behaviour is typical of a circuit in bridge configuration, where thedVI dt is generated during complementary switch turn-on. This undesired effect generates
t\N476/0492
1/9
715
APPLICATION NOTE
additional losses, mostly in devices in the off-state, due to the presence of both high voltage and high current on the collector. Parasitic turn-on must be avoided and this can be prevented by modifying the design of the drive circuit. dynamic dV/dt
In this condition the dV/dt is applied to an IGBT during the recombination of minority carriers in the substrate and a peak current appears during the collector voltage rise time even if the gate and the emitter are in short circuit. The dynamic condition can occur when the IGBT works in thyristor mode, typically in aquasi resonant converter with a zero curent switch (QRC-ZCS).ln this case the power losses depend on the device structure and on the converter resonant frequency. Thus, this phenomenon sets a limit to the operating frequency.
1. SPURIOUS TURN-ON IN STATIC dV/dT CONDITION.
1.1 Description of the Phenomenon.
The equivalent diagram offig.1 shows current flow across the structure of an IGBT in the offstate when a rising collector-emitter voltage is applied. The current through the reverse capacitance Cgc ( Cgc « Cge ", Cres => i = Cres · dV/dt), charges the gate capacitance; in this way, the gate voltage can reach the IGBT threshold voltage and a conduction current appears. Photo 1 shows the waveforms du ring aspurious dV/dt turn-on giving prominence to the simultaneous presence of high voltage and high current. If the output impedance of the drive source is high this phenomenon occurs more easily because of the higher ratio between the reflected Vge and the applied dV/dt.
I = cog· dV/dt 1---
.~ ,... ccg
c
I
dV/dt
Rg
Fig.1 - Current flow through IGBT capacitances due to dV/dt
Photo 1 - Waveforms during a spurious turn-on due to static dV/dt condition. Gate voltage = 2V/div,
Drain Voltage = 200V/div, Drain current = 2A1div.
Thus the main parameters influencing an IGBT's behaviour in staticdV/dt condition are:
- device characteristics (C res ' Cge, Vth , gls) - temperature
- Rge, dV/dt value - gate bias
2-1-9 ------------------------~~~~;~~~:9~ --------------------------
716
APPLICATION NOTE
1.2 The influence of temperature.
When the temperature increases, IGBT parameters vary as follows: - transconductance at low current increases - threshold voltage decreases - turn-off time increases As a consequence, when the temperature increases the power losses due to dV/dt turnon increase and the phenomenon occurs at a lower dV/dt value. Photo 2 shows a comparison of the peak
current at Tj = 25°C and Tj = 1GGoC with the
same static dV/dt conditions.
1.3 The influence of dV/dt and Rge'
The effect of Rge and dV/dt can be evaluated with the simplified circuit in fig.2 but the mathematical resolution is not easy because of the influence of the voltage on Cge and Cge' The behaviour of SGS-THOMSON's IGBTs were characterized by the test circuit in fig.3, taking care to measure the energy dissipated
in the devices at Tc =1GGoC E =d v(t) · i(t)dt.
The curves in fig.4showthis measured energy versus both Rge and a typical dV/dt. Considering a single curve, dV/dt = ~onstant, it can be observed that it has a minimum constant value for Rge lower than the "knee" value. In this region IGBT parasitic turn-on does not occur and the absorbed energy only charges the IGBT output capacitance.
1.4 The influence of gate bias.
Gate bias voltage influence was analyzed for negative voltage (V EE) using the test circuit in fig. 3. Figs.5 and 6 show that, when VEE = -5V spurious turn-on does not occur even if the value of the resistance connected to the gate is high (18GQ). Looking at the waveforms in fig. 7 we can note two different effects on the gate voltage due to the negative bias.The first is obviously that the gate voltage is offset from VEE and the second is that there is a different gate voltage peak even if the applied dV/dt is the same. This happens because of the influence of gate voltage on C ge. Photo 3 shows the gate charge curve and clearly demonstrates the variation ofthe slope
.--------------e c
Ceg · f(Veg)
'hoto 2 - Comparison between the peak current
due to static dv/dt with Tc = 25°C and
Tc = 100°C, 10 = 2Ndiv, V0 = 100V/div,
Rg = 100 W, E@25°C = 226 mJ,
E@1QQoC = 1. 2m6 mJ
G
Rgi
dV/dt Cge · f(Vge)
Rge
E
Fig. 2 - Simplified input circuit.
- - - - - -_ _ _ _ _ W'I SGS·1HOMSON _ _ _ _ _ _ _ _ _ _ _3_/9
'J, Ii>lD([;L1Im~rnIi:'ii'L1I@[;JDIGi§l
717
APPLICATION NOTE
Vee
/--
~iI v" (100V/div)
;""'-
/i \Jh;~Ie \1\ '
'
(5A/div)
~V'
~
~
~ ~
l~ie~'G~) ~
1 Vetl " le\ (20 0 VA(diV:
Fig. 3 - Test circuit and related waveforms
EnergY(IlJ) @ Tj · 100'C
500
8kV IllS
STGH8N100
400
4kV/IlS 1kVIllS
300
.5kV/IlS
200
100
0
20
40
60
8
100
Rge(ohm)
Photo 3 - Gate charge. Curve Vge = 2V/div. Vee = 100V/div
Fig. 4 - Energy dissipated. versus Rge and dV/dt
of the voltage occuring at Vge=-2V. If Vge is
greater than this value then Cge =Cies (input
capacitance, output short circuited) if Vge is lower than this then Cge is about four times Cies and reduces the gate voltage peak.
2. HOW TO AVOID PARASITIC dV/dt TURN-ON.
The previous paragraph shows that it is possible to avoid undesired turn-on during dV/dt by:
a) connecting gate and emitter by a low turnoff resistance
b) reducing dV/dt c) biasing the gate, during the off state, with a
negative voltage
2.1 LOW Rge VALUE DURING THE OFF PHASE.
Depending on the required performance, this solution can be applied as follows:
4/9
--
-
-
-
-
-
-
-
-
-
-
-
l
i
;
j
~~~;m&r::oo~J:
-
-
-
-
-
-
-
-
-
-
-
-
-
718
APPLICATION NOTE
6rE~ne=r~g~y~(m~J~)____________________- - . 6 il.Rg~. 100 ohm
4
3
2
STGH8N100
dV Idt · 8kVIlJs
1 .
Tj· 100·C
oL---------~=---~~--------~
o
2
3
456
Negative gate bias(V)
200 Energy(uJ)
STGH20N50
160
Rge · 180 ohm dV Idt · 8kV IllS
Tj · 100·C
100
STHI10N50 60
oo~-----=2 ==3 ~==4 ====~6 --~6
Negative gate bias(V)
Fig. 5 - Dissipated energy versus negative gate bias and Rge
1/
I-
dV~dt I
!/
100 v/,,;V
f-- I-- --'
I.r"'-
2 V/"';v
(
v~ = 0/
"t--l"- I---t - f-.
-- = - Vet
5V
I "r-
2 V/d;v
I I
Fig. 7 -Comparison of gate voltage behaviour with and without negative bias
1) Rge is the gate turn-off resistance as shown in fig.8a.
2) Rge is connected just after turn-off as shown in fig.8b.
The disadvantage of the driving circuit shown in fig .8a is that this circuit does not guarantee the full safe operating area (RBSOA) when Rgs is less than 1OOQ, for the following reasons:
. the latching current depends on dV/dtduring turn-off
Fig. 6 - Dissipated energy versus negative gate bias
- Rge strongly influences dV/dt at turn-off
- the RBSOA is guaranteed for Rg = 100Q
Fig.9 shows this behaviour and the diagram in fig.10 shows thatthe maximum Rge necessary to avoid dV/dt problem is less than 100Q Thus, the driving circuit of fig.9 is suitable for applications where the full safe operating area @ Rg = 100Q is not required. The driving circuit of fig.8b turns-off the IGBT with Rg = 1OOQ obtaining the full RBSOA but the delay "d= tstorage + tfall" for each must be optimised for each application.
2.2 Reduction of dV/dt.
The spurious turn-on problem due to dV/dt is typical of the circuit shown in fig.11; in this circuit, the free-wheeling diode in the parallel with the lower IGBT, which is in the off state, is turned off during the upper IGBT turn-on and a high dV/dt is generated. Thus, dV/dt value depends on : - complementary IGBT turn-on speed (dl/dt) - free-wheeling diode "softness" - wiring inductances
-------------------------- ~~~~~~~:9~-------------------------5/-9 719
APPLICATION NOTE
Jl
Jl
Rg (on) Rg (off)
l !-.....
Age
(a)
(b)
Fig. 8 - IGBT driving circuits
STGP10N50
140 Ie (A)
120 ............................. Vce···400··V
100 ...
.. Tc ......100~C
eo ..........................V"JL~...15..V....
60
40 20 ................................................................................
o+---~---+----~--~~-+--~
o 20 40 eo so 100 120
Rg (ohm)
Rge (ohm)
250r=~------------------------------.
200
Tj = 100 'c
150
STGH20NSO
100
50
2
4
6
8
10
dVIdt (kV11-18)
Fig. 9 - Ilatch versus Rgoff
Fig. 10 -Max Rge values that avoid static dV/dt
turn-on versus dVIdt
Vee Vee IRM
b h h t. lG8T CURRENT
dV/dt DURING DIODE RECOVERY
Fig. 11 - Typical circuit where static dV/dt conduction can occur.
-6/-9------------------------ LV ~~~~m&~:oo~~ --------------------------
720
APPLICATION NOTE
Diode current recovery
during turn-off = 10Aldiv
Drain voltage and dv/dt due to the diode turn off 200V/div.
Current due to spurious turn-on with Rgs = 100 Q2A1div
Photo 4 - Waveforms in the circuit of fig. 11 when: Rgon = 100 Q
Diode recovery = 5A1div.
Dv/dt due to diode turn-off 200V/div. Current in the IGBT in off state 2A1div.
Photo 5 - Waveforms in the circuit of fig. 11 when Rgon = 200Q. In this condition turn-on due the dv/dtdoes not occur.
and it can be minimized:
- using fast soft recovery diodes. - reducing wiring length. - turning on IGBTs slowly, with a high value of
turn-on gate resistance. Photo 4 and 5 show that the dV/dt is reduced to a safe value in the circuit of fig.11. Photo 4 uses a low value of turn-on gate resistance whereas photo 5 uses a high value gate
resistance. In the case of photo 5 spurious turn-on due to the dV/dt does not occur.
2.3 driving the IGBTwith a negative voltage. Biasing the gate negatively, as shown in photo 6, causes a higherdV/dtduring turn off because of the availability of a large gate current. It is possible to avoid this drawback, which reduces the effective RBSOA, simply by increasing the value of Rg(off)'
- - - - - - - - - - - - - -------------lifi· ~~~~mgr:::>!?::
7/9
721
APPLICATION NOTE
3. DYNAMIC dV/dt.
This condition may occur in a zero current quasi resonant converter where the IGBT works as a thyristor. In this application, see fig. 12 and photo 6 the IGBT is turned-off when the collector current is zero and the collector voltage starts to rise after a delay time td '" (2 · fresonance)-l, corresponding to the end of the reverse recovery phase of the antiparallel diode. This increasing voltage causes a currentspike,
leading to power losses becauseofthe minority carriers in the IGBT substrate. The amplitude of the spike depends on several factors which involve both IGBT and circuit characteristics. One of the factors is the amount of the stored charge when the dV/dt is applied. The stored charge depends on the type of IGBT (slow or fast), junction temperature and resonant frequency. Increasing temperature and/orfrequency leads
Cr Lr
Fig. 12
3.5 iP-~ea=k~c=ur~r=en~t~(~A~)______________~~
3
2.5
peak current_
2
1.5
STGH8N100
:r
delay time
Te · 100'C
?5 dV/dt. 5000V/IlS
oL---~--~--~--~--~--~--~
o
2
3
4
5
6
7
Delay time (us)
Fig. 13 - Peak current versus tdelay
Gate voltage = 10V/div Drain current = 2Ndiv
Drain voltage = 200V/div
Photo, 6 - Waveforms in a resonant converter where dynamic dvldt occurs. Device = STGH8N100, Tc=100°C
8/9
-------------------------- 11.."
~~~mgr::9J: ------------------------
722
APPLICATION NOTE
to a higher current peak. The diagram in fig.13 shows how increasing resonant frequency affects the current peak. For frequencies lower than about 120 kHz the current peak is constant, because there is no more stored charge and due solely to capacitive effects that are similar to those in Power MOSFETs. The other factor is related to the rate of voltage rise which depends strongly on the softness of the diode. Using a slower IGBT emphasizes the effects discussed above. In low frequency working conditions the power losses are no longer negligible and must be considered during the circuit design in order to avoid thermal runaway and consequent device failure.
4. CONCLUSION.
The dV/dt phenomenon causes power dissipation in IGBT devices and this may lead to the failure due to thermal runaway. The
way to avoid this phenomenon depends on the operating conditions. When an IGBTworks in astatic dV/dt condition, as for example in a bridge circuit, it is possible to prevent the dV/dt phenomenon by modifying the design of the IGBT drive circuit:
- reducing dV/dt.
- connecting a low gate-emitter resistance.
- driving the IGBT with a negative voltage at turn-off.
If a high current is to be controlled with a switched mode technique, it is necessary to design the drive circuit to obtain the full guaranteed RBSOA.
When the IGBT works in dynamic dV/dt condition, as in a QRC-ZCS, it is not possible to avoid power dissipation in the device by optimization of the drive circuit. These kind of losses can only be limited by selecting a suitable converter resonant frequency and antiparallel diode.
-------------------------~~~~~~~~::~------------------------9/-9 723
APPLICATION NOTE
STATIC AND DYNAMIC BEHAVIOUR OF PARALLELED IGBTs
by R. Letor
ABSTRACT
Problems associated with power device characteristics when power devices are connected in parallel, such as thermal stability and balanced switching behaviour can be solved by using insulated gate bipolar transistors (IGBT). This note deals with parallel IGBT behaviour analyzing both static and dynamic characteristics. The influence of heatsink mounting, lay-out, and drive circuit are described in order to demonstrate the best way to parallel IGBTs for optimum performance,
In addition the major advantages of the ISOTOP package are shown.
I. INTRODUCTION
When switching devices are paralleled, the following points must be carefully considered: 1) On-state losses balance. 2) Switching losses balance. 3) Thermal stability. The loss unbalance, depending mainly on the spread of the device parameters (V CEsat' switching time), can cause excessive power dissipation in one or more devices.
AN47710492
1/13 725
APPLICATION NOTE
The thermal instability, correlated to the behaviour of the devices when the temperature increases, can cause thermal runaway and lead to the failure of the device. This note explains the theory, describes practical examples and suggests possible solutions. The behaviour of the IGBTs considered is not dependent on type, hence, the results can be extended to all SGS-Thomson IGBTs.
II. BEHAVIOUR OF PARALLELED IGBTS IN THE ON STATE.
The IGBT is a voltage driven device, hence when the devices are in parallel the drive conditions are the same for all devices (i.e. they all have the same VGE)' Thus the influence of output characteristics and of the transfer characteristics can be studied separately.
A. Current balance in the on state.
Current balance can be studied with the simplified circuit of fig.1 where the following conditions are respected:
VCEsat1 = VCEsat2 IC1 + IC2 = ILOAD
VCEsat1 = f(l c1 , Tj1' VGE1)
VCEsat2 = f(I C1 ' Tj2' VGE2)
(1)
This system of equations (1) has a graphical
solution which is shown in fig.2 for the
extrapolation of current balance in two
paralleled IGBTs with the same junction
temperature (Tj1 = Tj2)·
Figure 3 shows the influence of the spread of
VCEsat on the current balance.
B. The influence of the temperature on current balance.
The fig.4 shows the basic equivalent structure of the IGBT. The device functions as a bipolar transistor which is supplied base current by a PowerMOSFET. The IGBTs output characteristic combines both the bipolar and the Power-MOSFET characteristics.
IC1
IGBT1
~ I IGBT2
!'--...Ivc 1
IC2
t-,.....
VCE2
VG
I load
Fig. 1. Circuit where current balance depends only on IGBT characteristics.
Fig. 2. Graphical extrapolation of current balance
in the on state for two STGP10N50 @
ILOAD = 10A; Tj1 = Tj2 = 25°C; Ic = 1Ndiv.:
VCE = O.5V/div.
- - 2/13 - - - - - - - - - - - LV ~~~;mgr::oo~~ - - - - - - - - - - - - -
726
APPLICATION NOTE
The curves in fig.S show these effects and highlight the following points:
1 - The temperature coefficient of VCEsat is negative at low current density (I < I NOM) (bipolar effect).
2 - The temperature coefficient of VCEsat is positive at high current density (I > INOM) (Power-MOSFET effect).
3 - The temperature coefficient of the dynamic resistance (di/dv) is positive (Power-MOSFET effect).
The effect of this behaviour is that the influence of the temperature on current balance is small and that the current balance improves when the temperature increases, if Ti1 = Ti2 (~Tj = 0), (fig.6). Figure 7 shows the effect on current balance when the junction temperature of paralleled
devices are different (~Tj =0) and the medium
temperature is constant (Tj1 + Tj2)/2=K: - At low current, current balance is worst
when the temperature difference increases, but the temperature coefficient is low.
!50 Mell load (%)
I load · I NOM.
40 .............................
Tj1 · Tj2 · 100 C
30·VGE··.;.··15V····Z ................................
y 20 ............
... H
···································
10 .
"'. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18 0: I
e Ie · (It'B)IB
1
o 5 W ~ ~ ~ ~ $ ~ ~ 00
~VCE(satllVCE(sat} (%)
Fig. 3. Current balance versus the VCE(sat) difference in two paralleled IGBTs.
Fig. 4. Simplified equivalent circuit of an IGBT.
coefficient
80 (101 - 102)/1 load (%)
CQ9f,fic ent
VCESAT
Fig. 5. Output characteristics versus the temperature for STGP10N50. I = 2A1div.; V = O.5V/div.
2
4
6
8
10 12 14 16
I load (A)
Fig. 6. Current balance versus ILOAD and temperature in two paralleled IGBTs.
-------------- LV ~~~~m~r::O!~:= -------------3/13 727
APPLICATION NOTE
- At high current the behaviour is similar to the power- MOSFET behaviour; in fact, current balance improves when the temperature difference increases.
C.INFLUENCE OF THE TRANSFER CHARACTERISTICS.
When IGBTs are strongly saturated, the influence of the transfer characteristics on paralleled devices behaviour is small. The figure 8 shows that the gate voltage scarcely influencesthe VCEsat value; hence it is not possible to improve the current balance in the on-state by connecting an emitterground resistance.
III. PARAMETERS INFLUENCING SWITCHING BEHAVIOUR.
The IGBT's switching behaviour depends on:
- Device parameters (Vth, gis' Cj, CrSS'Co)' - Drive circuit.
- Lay-out (Parasitic inductances).
The switching behaviour is studied in the circuit of figure 9 where the stray inductance "Ls1+Ls2+Ls3" is small and the IGBTs are
turned on, while the free wheeling diode is still conducting; with this working conditiondildt is not limited by. the stray inductances and depends on the IGBTs switching speed
(dlldt » Vcc/(Ls1 + Ls2 + Ls3).
A. Turn-on.
During turn-on, the switching losses depend mainly on the di/dt that influences the peak current due to the diode recovery (Eco '" Ipeak · tcross · Vcc/2). In the circuit of figure 9, the voltage drop caused by the inductance of the emitterground connection (Ls1 ), reduce the drive current (IG = (Vd - VG - Ls1 · di/dt) I RG), and acts as a negative feedback during current rise time. Taking into account the effect of Ls1 ' the value of di/dt is:
dildt", (Vd-Vth) I (RGCj I gls + Ls1)
For 1000V devices and with RG = 100Q:
15 · 10-9 < RGCj I gls < 25 · 10-9
The inductance of 1cm of wiring is:
Ls1 '" 10 · 10-9 H/cm
1~IC~1(~~)-~I~c2~(~~)~~~)~_ _~ 8.5 ····················2··.· STGP 1ON50
5t~=::;~:~<~~:
4"4 . ::::::::::::::::::S;~::~:~:~:~~:::::::::
S.9 ......... II ............................
2.::L...-_~dI~=:::=::""":~=::~.::;;.c~:::c:;;;A.::c:.:-:=:t
- KT' - 0.03 Ale
-+- KT'O -+- KT' 0.001 Ale
1.~ L--'---'-_.._. . . . . . _....-.-.<--._.._....-.L...----.J 6VCE sat/VeE aat-25%
f 10 20 80 40 50 eo Voe' 15V
Tj · 90 C TI1-1J2 ( C)
Fig. 7. Influence of 11Tj on current balance during the ON-state. KT is a temperature coefficient.
6 VcEsat (V)
STGP10N50
4
··..···..·······..········· ..(c ..·1OA·· .... ..
3
.. ... ...........Ii..~..JQQ.G......... ..
11 .. ··....··......·..·····....·..·......·..··..··....·..····..··..·..···+ ............................j
O,L---'---~~~--~----'-'-;--~--~
m 6 7 9 f t ~ ffi V GATE-EMITTER VOLTAGE (V)
Fig. 8. Typical VCEsat versus gate bias.
-4/-1-3 ---------------------- L;i ~~~~~~:~~~ -------------------------
728
APPLICATION NOTE
From this it can be seen that the spread of device parameters has less influence on the di/dt value than the parasitic inductance of the emitter-ground connection.
B. Fall.
During current fall two distinct phases can be seen (figure 10). Phase 1 is similar to the current fall of powerMOSFET and the parameters influencing the di/dt are the same parameters that influence dildt during turn-on. The tail during phase 2 which is due to the minority carriers stored in the substrate mainly affects the switching losses. The tail amplitude depends on Tj and on the turn-off current; hence, the turn-off current and the working temperature mainly influence the losses during the fall time (Fig. 11,12).
C. Storage.
During the storage time "Ie = gls (VGE-Vth)", "dildt = 0" ,and the current waveform depends only on the IGBTs parameters (giS' Vth) and on the drive circuit.
IV. PARALLELED IGBT'S SWITCHING BEHAVIOUR.
The influence of the drive circuit, of the layout and of the device parameters was verified using the following conditions: - 1 Gate drive with separate gate resistances
(fig.13). - 2 Gate drive with one gate resistance
(fig.14). - 3 Unbalanced emitter-ground wiring
connection (fig.1S). - 4 Paralleling devices with the maximum
spread of the parameters. The voltage and collector current waveforms are stable in all conditions, even in the worst case condition where the gates are driven with a common resistance and the wiring inductances are strongly unbalanced
A. Turn-on. Photo 1,2 show that the drive circuit influence on peak current balance is small and photo 3 shows that the peak current unbalance is significant in condition 3, where
.1Ls1 = 0.1SIlH.
~ c ,,' - - -
"" PEAK DUE TO d1Idl
,," VQ
"/
'---<:I--~-oVcc
laS
FREE WHEELING
Fig. 9. Circuit showing the parasitic inductances influencing the switching behaviour.
P-MOS region
Bipolar region
b ~ ( ~,
Va
!
I
Ie
,I II
.~Iil
~
t
t
storage fall
Fig. 10. Gate voltage and current wavelorms during turn-off time.
5/13
-------------------------- ~~~~~~:::~ ----------~--------------
729
APPLICATION NOTE
Cross-over energy (mJ)
3
I
;
!
2.5 .. lSTGP\0~50 J....... 1 ....J .1.
2 ···~~~ii~;~, I!
.il . j ··1··
1.6·····!··j+·
1 .
0.6
oL-__l -__~__~__-L__-L__~__·~ o 5 10 16 20 26 30 35
Iswilch (A)
Fig. 11. Switching losses at turn-off Vsturn-Off current.
1.5 ;N=o=m=a;:l.i-m=d-::E..c.o..::(:Ec;c:o../:E:.c.:o.=·'--1-,0-0.:..C:.).:.-=..,...----'---,-----,
1.25 .. ············r· ............ ,...
········r-··
i
···i····
i
1 .
....l ...........i.
0.76····
j
!
0.6 ... ....i ·····j·iSTGP10N50
i
i~.ro~
0.25 . "'r ·······:I·r~:~;i~i~T~h;. oL-_ _- L____L -__~____~__~__~
o
25
50
75
100
125
150
Tj ( C)
Fig. 12. Influence of temperature on turn-off losses.
=3
I'
Fig. 13. Driving with separate gate resistance.
.----------~---~~
Fig. 14. Driving with one gate resistance.
Vao
RaIl Vd
WIRING UN:W...ANCE
Fig. 15. Emitter ground wiring unbalance.
Photo 1. Turn-on with separate gate drive (fig. 13) of an STGH8N100; I = 2Ndiv., t = 200ns/div.
6/13
--------------~------------- ~~~~~~~~::~----------------------------
730
APPLICATION NOTE
IGBTs with the maximum difference in parameter values were paralleled; the comparison of current waveforms in photo 1 and 2 demonstrates that the influence of parameter spread is low (L s1 = 30 nH).
B. Fall.
Photo 4 and 5 show that the wiring inductance unbalance affects only the power-MOSFET phase; but this behaviour creates negligible
switching loss unbalance in comparison to the total turn- off switching losses. The current unbalance just before current fall that affects the tail amplitude can create significant switching loss unbalance (see fig 17).
C. Storage.
During the storage time, the spread of the IGBTs parameters (gis' vth ) and the difference
Photo 2. Turn-on with one gate resistance
(fig. 14) of an STGH8N100;
I = 2A1div., t = 200ns/div.
Photo 3. Turn-on with unbalanced emitter-ground
wiring (fig. 15) ofa STGH8N100;
I =2A1div., t = 200ns/div.
Photo 4. Turn-off with balanced gate-emitter wiring (fig. 14) of a STGH8N100;
I = 2A1div., V = 200V/div., t = 500ns/div.
Photo 5. Turn-off with unbalanced emitter-ground wiring (fig. 15) of a STGH8N100;
1= 2A1div., V = 200V/div., t = 500ns/div.
------------- ------------- I:fi ~~~~~~::O!~~
7/13
731
APPLICATION NOTE
between storage times causes current unbalance thus creating switching loss unbalance. Photo 6 shows the effect of the storage time differences when the gates are driven with separate gate resistances. The collector current begins to fall in the device with the smaller storage time, consequently the current increases in the other IGBT so increasing storage current unbalance. Driving the gates with only one gate resistance minimize this effect (photo 7); the device with the higher storage time hold the gate voltage to "Vth+glslc" until the fall time phase, so equalizing the storage times. Current unbalance due to the IGBTs parameter spread can be calculated with the equations (2) and (3). The curves of fig.16, 17 show, respectively, storage current unbalance and the consequent switching loss unbalance between two devices where the Vth and gls values are the limits of the parameter spread.
Photo 6. Effect of separate gate drive on storage current waveform. I c=2A/div., VCE=200V/div., VGE=l OV/div., t=500ns/div.
Iload = 11st + 12st = VGE (gls1 + gls2)-
(glsl vth1 + gls2vth2)
(2)
Istorage = 11st - 12st = VGE (g'Sl - g'S2) -
(glSl vth1 - gls2vth2)
(3)
V. THERMAL STABILITY.
When IGBTs are connected in parallel the onstate current is greater in the device with the smaller V CEsat (fig.2); thus, the power dissipation and the junction temperature is higher in this device. This phenomenon can cause a thermal instability because of the following reasons:
Current unbalance increases when junction temperature difference increases (fig.7 ).
- Switching loss unbalance increases when junction temperature difference increases (fig.12).
The thermal stability can be achieved by mounting the paralleled IGBTs on the same heatsink; in this way the heatsink works as a negative feedback, because it transmits the heat from the device with the higher T j to the device with the lower T j so reducing the junction temperature difference. In the ideal case where the thermal resistances (Rthj h,Rth x) are null, the thermal stability is assured because the devices work at the same temperature and the current balance improves when the temperature increases as shown in fig.6. In real conditions the thermal resistances "Rth1h" are not negligible and the thermal stability can be studied with the equivalent thermal circuit of fig, 18 which can be simulated with the system shown in fig,19, The behaviour of the system near the final working point, is simulated using two paralleled IGBTs driving a constant inductive load; the devices are only active when the
- - - - - - - - - - - - - 8/13
- - - - - - - - - - - - - l i f j ~~~~~~r::oo~!:
732
APPLICATION NOTE
heatsink temperature is uniform and at the final temperature which is independent of the current balance as the equations (4),(5),(6), (7),(8) show.
(Theatsink=T amb+ Rth h-amb. (VCE(sat) (I C1+IC2 )+
Switching losses} ~ canst.
(4)
ICI + IC2 = ILOAD = canst.
(5)
VCEsat ~ canst.
(6)
Switching losses ~ canst.
(7)
T ambo = canst.
(8)
The stability was evaluated with the following conditions:
- heatsink temperature constant (load constant). Initial junction temperature equal to the heatsink temperature (100°C). Turn-off current unbalance constant and equal to the maximum value (worst case). Thermal capacitances disregarded.
Photo 7. Turn-off with one gate drive resistance;
Ic=2Ndiv., VcE =200V/div., VGE = 10VI div., t = 50Dns/div.
Photo 8. Comparison of current balance at Tj=25°C and 100°C; Ic=2Ndiv., t=1 0lls/div.
tOO{·'-I.~C1~-~lc~2~l/~[I~oa=d~(~~b~)________________
STGPION50 .......... . 80 ............ ································Tj~··l(jc:fC·············
(glol-gf82)/gfe · 26'10
20 ..................................................................................
oL-----~----~----~----~--~
o
6
10
16
20
26
LOAD CURRENT (Al
Fig. 16. Storage current unbalance versus load current.
+.. 0.26 ...............1I............ 0.2 .............
0.16 ...... i
.. STbp 1ON50 ........
···········1· i 0..1
-1 j , " j···(gTrJ 8.1~0g0;~C2j;gla~25%·
0.05 ···········i······(vti/::vt;:i2ijyji'~25ijj,
OL---~IL---~----~----~----~
o
6
10
15
20
25
LOAD CURRENT (Al
Fig. 17. Switching losses unbalance due to storage current unbalance.
--------------------------l.V ~~~;m~r::il~~ ----------------------9-/1-3
733
APPLICATION NOTE
The blocks in fig.19 signify the following computations: 1 - calculates initial current unbalance
(~Tj = 0) depending on the output characteristics of paralleled IGBTs. 2 - Calculates junction temperature difference depending on the on-state current unbalance (~Ion) and on switching current unbalance (~Is)'
~Tj = Rthjh * (~ Power dissipation).
FRAME
\
I
i-;::J I
_DIE
{d
Fig. 18. Equivalent thermal circuit.
EFFECT OFL\.VcE8St
EFFECT OF RthJh
EFFECT OF~TI
Fig. 19. Simulation of the temperature changes for two paralleled IGBTs.
3 - Calculates the growth of current unbalance (incr.~I) due to junction temperature difference (fig.16).
If Rth x is negligible (Rth x « Rth jh):
f(~lon) = Rth jh * ~Pdon = Rth jh * VCEsat * (ton/T) * ~Ion = KR * ~Ion (9)
f(~ls' ~Tj) = Rth jh * Pdswitching =
Rth jh * f * ~Eco(~ls ' ~Tj)
(10)
~Eco(~ls' ~Tj) = ~Eco(~ls' 100°C) *
* (1+~Tj * Ks) (see fig.12,17)
(11)
incr~lon=KT*~Tj (seefig.7) (12)
The equation (13) is the transfer function of the system.
~Tj = KR * ~Ion + Rth jh * f * ~Eco / (1-(KR * KT + Ks * Rth jh * ~Eco * f)) (13)
Thermal stability is guaranteed if the equation (14) is true.
(KRKT + Ks Rth jh * ~Eco * f) < 1. (14)
A. Example of two paralleled STGP1 ON50FI (Fully insulated package).
Conditions:
f = 15KHz
ILOAD = iDA
b.VCEsatlVCEsat=20% Rth jh = 3.5°C/W tonlT = 0.5
Parameters ~Eco = 0.2 mJ
Reference See fig.17
Ks = 0.005;oC See fig.12
KT = 0.007 ArC See fig.7
-10-/1-3-----------------------~~~~;~~:::~ --------------~----------
734
APPLICATION NOTE
KR = 3.5
KR = 2 Rth jh · tonlT
lil on (liTj=O) = 2A See fig.3
VCEsat = 2V
Solution of the equations (13) and (14): KRKT + Ks * Rthjh * liEco * f) = 0.08« 1 (15)
r----_----.--{)
BYTl6P400A 2 · STGP 1ONSO
I LOAD
.·· J
H j = 19°C
(16)
lilon (liTj = 19°C) = 2.13 A
(17)
The equations (15) (16) (17) show that the thermal stability is very high even when the devices are insulated and switching loss unbalance is high (worst case). The conditions studied in this paper were carried out by mounting the paralleled devices in the chopper circuit shown in fig.20. Photo 8 shows the current balance improvement when the heatsink temperature increases (25°C - 100°C) and the devices are working in the chopper circuit. The fig.21 shows the output characteristics of the paralleled devices and the estimated onstate cu rrent.
Fig. 20. Chopper circuit where paralleled IGBT behaviour was checked.
-r; I III :~I
100·C
~100·C I
/1 IGBT2
25 ·c-f
IGBTl
'--25 ·c
j. I
ILL
.11 rl
I I I
·nI c@100·C H-
--t, . I
1/ ..
1// Jd '/
V CEsat
Fig.21. Output characteristics of the devices in fig. 20 and estimation of current balance at Tj1 = Ti2 = 25°C and 100°C.
VI. IGBTS IN THE ISOTOP PACKAGE.
To reduce parameter spread, the IGBTs dice are mounted in the ISOTOP package with the "die sister" technique; the thermal resistance between the device junctions is reduced to a minimum and the gates are connected in parallel.
When the ISOTOP packages are paralleled, they give the following advantages:
The small and compact size of the package (fig.22) and the low Rthjc value (0.5°C/W) give a minimal thermal resistance between the paralleled devices.
- This package was designed in order to minimize emitter ground wiring effects; In fact Isotop packages provide an auxiliary emitter pin' which makes it simple to separate the driving circuit from the power circuit (fig.22,23).
Photo 9 & 10 show that unbalanced wiring connections have very little effect on the
--------------------------~~~~~~~:9~ -----------------------1-1-/1-3 735
APPLICAnON NOTE
15 Inrn f Z min
LOAD
Photo 9. Turn-on of two TSG50N50DV with unbalanced emitter ground wiring. le=25Ndiv. VGE=1 OV/div. t=200ns/div.
Fig. 22. Dimensions of the ISOTOP package and schematic diagram showing an auxiliary emitter pin.
Photo 10. Turn-off of two paralleled TSG50N50DV. Ie = 25Ndiv. VeE = 100V/div. VGE = 1Odiv. t = 1~s/div.
Fig. 23. Paralleling ISOTOP.
switching behaviour: the difference in length of emitter ground connections is 15 cm. It can be seen in photo 10 that there is no peak voltage due to di/dt (V = L di/dt) on the gate-emitter auxiliary pin during current rise.
12/13
---------------------------~~~~~~~~:~~ ---------------------------
736
APPLICATION NOTE
VII. CONCLUSIONS.
The performances in terms of current balance, thermal stability and switching behaviour when SGS-THOMSON IGBT devices are paralleled, are very satisfactory. The transfer characteristics has no real influence on current balance in the on-state. The on state current and the switching current balance are ensured respectively by the low spread of the VCEsat values and by the low spread of device parameters. High thermal stability is obtained by mounting the paralleled devices on the same heatsink even when the devices are insulated (mica, insulated package). For an optimum switching behaviour of paralleled devices, it is necessary:
- to drive the gates with only one gate resistance.
- to balance the emitter-ground wiring.
When IGBTs are in the ISOTOP package, the. wiring unbalance tolerance is high and the thermal resistance (R thjh ) is low; thus,the advantages of the ISOTOP package are:
- easy to design the lay-out when paralleling IGBTs in ISOTOP.
- small thermal resistance between the junctions of paralleled devices; thus, temperature difference between the junction of the devices in parallel is reduced to a minimal value.
REFERENCES.
[1] B. JAYANT BALlGA, "Temperature behaviour of insulated gate transistor characteristics"; Solid state electronics vol. 28 N° 3, pp 289-297,1985.
[2] M. MELITO - F. PORTUESE, "Gate charge leads to easy drive design for POWER MOSFET circuits", PCI June 1990.
[3] SEBOLD R. KORN, "Parallel operation of the insulated gate transistor in switching operations.", PCI June 1986.
[4] D-S KUO, MEMBER IEEE, J-Y CHOI, D. GIANDOMENICO, C HU, SENIOR MEMBER, S.P. SAPP, K.A. SASSAMAN and BREGAR., "Modelling the turn-off characteristics of the bipolar-mos transistor", IEEE ELECTRON DEVICE LETTERS, vol. EDL.6, N°5, MAY 1985.
[5] M. HIDESHIMA, T. KURAMOTO & A. NAKAGAWA, "1000V 300A bipolar-mode mosfet (IGBT) module", Proceedings of 1988 International Symposium on Power Semiconductor Devices, Tokyo, pp. 80·85.
- - - - - - - - - - - - - l . f i ~~~;m~~:~?!:~ - - - - - - - - - - - - - 13/13
737
APPLICATION NOTE
HOW SHORT CIRCUIT CAPABILITIES GOVERN THE DESIRED CHARACTERISTICS OF IGBTs
by C.G. Aniceto, R. Letor
ABSTRACT.
Short circuit tolerance of IGBTs can be obtained by the optimization of both the protection circuit and the intrinsic ruggedness of devices. This note discusses application design criteria and IGBT characteristics compared to the intrinsic short circuit ruggedness.
1.0 INTRODUCTION.
The continuous growth of IGBT applications requires more differentiation of device electrical characteristics. In fact, the structure of IGBTs makes them flexible to use and their
switching performance can be specifically matched to many different applications. For the best match between application requirements and IGBT characteristics, some compromise between the saturation voltage, switching speed and ruggedness is necessary. To define the suitable IGBT short circuit ruggedness specification, this note analyzes the parameters influencing their behaviour during short circuit operation, and verifies the performance of the more usual short circuit protection compared to IGBT short
AN478/0492
1/9
739
APPLICATION NOTE
circuit ruggedness. It is also shown that modification of the IGBT structure improves the short circuit performance without compromising the saturation voltage and switching speed.
2.0. SHORT CIRCUIT OPERATION OF IGBTs.
Static and dynamic characteristics are not sufficient to predict the short circuit behaviour of IGBTs. Also, dynamic phenomena correlated to stray parameters and to the short circuits circumstances must be. carefully considered.
2.1 SHORT CIRCUIT MODES AND WAVEFORMS. Real short circuit mode can be simulated using the test circuits "A" and "B" illustrated respectively in figure 1 and figure 5.
TEST CIRCUIT "A": The device is turned on when the collector is directly connected to
the supply voltage and the short circuit inductance can be changed.This circuit simulates either a short circuit in one leg of a bridge circuit, or a permanent short circuit of the load [4]. The waveforms of figure 2 show the behaviour in the test circuit "A" when all the stray parameters are reduced to a minimal value. The effect of a significant short circuit inductance is shown in figure 4. The inductance, the reverse capacitance "C RS.' the gate capacitance "C G", RG, together with the IGBT amplification, constitute a resonant R,L,C circuit as shown in figure 3. Hence dildt at turn-on generates a very high peak current due to a gate voltage overshoot.
TEST CIRCUIT "B": The short circuit is actived during the on-state. In this case a dVldt is applied to the collector when the gate voltage is high and the device is in full conduction. This condition simulates accidental short circuit of the load during normal operation [4].
I
I
. M .
'w
liL~ '100 Idlv
-100 Idlv
\
'10 IdIv
'10 Idly
Fig.1. Testcircuit"A"LsHORT~4I!H,LSTRAy~150nH.
Fig. 2. Short circuit test with short circuit inductance = LSTRAY' Time scale: 2jJsJdiv.
-2/-9 -----------------------~~~~~~~~:~~ -------------------------
740
APPLICATION NOTE
Fig. 3. Simplified equivalent circuit of the short circuit condition. Vec
Fig. 5. Test circuit "B". Short during saturation.
I -...j.r;"-+'-I 'r.:~i~'--'¥";~l~lJ./-A.I.'..+++.I~"=-_ --~-;-',~,,,-t:i:,l:..,
IIc·10DIA/dlv -l
, I ~ :GATE OVERSHOOT-r--
l/i
-
, I i
i~ I I
'\ - :
I i vG- 10V/dl"
:I - !II
Fig. 4. Short circuit test with short circuit inductance = LSHORT' Time scale = 2l1sJdiv.
dV/dtl .~~~
.
lY+ I I I . ' , I I ~ ' Ve, laav dlv ~ Ii .
..~
I' (l'VPEAK CURRENT
!, TI I I I
l i II 1- i I I
. . ') I ; IC· 100Aldiv
I T III
I ir- ~ :GAT~ OVERVOLTAC E
V' 'I I
I
I
1\
I
I
! .~I Va· I~V(dl~
I I I"-+-
Fig. 6. Effect of the dVldt when the short circuit occurs during IGBT full conduction.
t = 2lls/div.
The waveforms of figure 6 show the effect of the dV/dt in the test circuit "8". The dV/dt acting trough reverse capacitance causes the gate voltage to rise over the driving voltage [6]. A peak current much higher than short circuit current is generated.
2.2 SHORT CIRCUIT STRESSES.
The failure of IG8Ts during short circuit condition occurs either with static latch or with dynamic latch of the parasitic SCR of the structure (figure 14) [2]:
- Static latch isduetothe high current density. - Dynamic latching is due to the high dV/dt
at turn-off. The influence of the temperature is critical because the latching current decreases when temperature increases. Moreover, during short circuit there is a very fast temperature rise due to the very high energy increase dissipated in the device. For this, gate voltage overshoot must be avoided and the short circuit currentmust be reduced as much possible. In fact:
- - - - - - - - - - - - - L." ~~~r:~~:: -------------3/9
741
APPLICATION NOTE
During overshoot, the collector current
(ic = gFS latching
(vc~r-reVntT,H))
can reach the static especially if the
transconductance of the device is high.
At turn-off the junction temperature is higher
than at turn-on, so the dV/dt due to the stray
inductance "Lsc" can cause a dynamic latch-
up.
Moreover, the stray inductance "Lsc" creates
an overvoltage at turn-off (see figures 2,4,6)
due to the dildt. If the dildt at turn-off is not
controlled by a suitable gate resistance the
overvoltage can rea.ch breakdown causing
device failure.
2.3 PARAMETERS INFLUENCING SHORT CIRCUIT BEHAVIOUR (figure 7).
The main parameters influencing static and dynamic short circuit behaviour. are:
- Transconductance gFS' CG, CRS (Device
parameters) - Driving voltage VD' RG (Driving circuit)
- Lsc ' LSE (Stray inductance of lay-out and of capacitance)
- LSSHORT' dVCE/dt, VCE (Short circuit conditions)
The stray inductances LS E (emitter-ground) and LSG (gate-drive) mainly influence di/dt at turn-on, but they are not critical for usual circuit lay-out and must be carefully considered, only when devices are paralleled [8]. Transconductance gFS is the most critical parameter. In fact, a high value of gFS can generate very high continuous short circuit current and very high peak current during transient.
2.4 SHORT CIRCUIT CAPABILITY CHARACTERIZATION.
In order to make test conditions as reproducible as possible, the short circuit capability characterization was implemented
using test circuit "A"' with stray inductances
reduced to minimum value.
f L',"~+ UC[[~:C ::' MAXhJs)
lell NOM 12
10
)c~ Lsc [_~
8 6
l· ~RGLlJ SGI~ ~
1 "-~
(n') Vo
G
Va
l~:;. LSE
4
4
2 Te.·. 125C .
2
Vee· 2/3 BVe S
0
07 8 9 10 11 12 13 14 15 16
GATE VOLTAGE(V)
Fig. 7. Circuit parameters influencing short circuit current of the IGBTs.
Fig. 8. Short circuit performance versus gate bias of IGBTs having a high transconductance. Maximum current overshoot ~ 20%
ISHORT CIRCUIT'
4/9
-------------
r==
~"'fl
&CiS.THOMSON
i'>l~«::mJ@rn~rn©1rmJ@oo~«::$
_ _ _ _ _ _ _ _ _ __
742
APPLICATION NOTE
V REF 15V
Fig. 9. Short circuit protection with high false alarm immunity.
9 'i
1II1\ I !i
II II I
H I! .
Ff=r
~4i
~:
~
U Ii
±
I II
t I I it
.*~
± ±
I I
1/"··
I
- Ii
+ Ii
i T
I
~ ~I
I Vr."
I I Ie
I Vn
I delay 2
I V~.n.
,
I dolay 1
! VIN
Fig; 10. Timing diagram of the protection circuit at turn-on and during overcurrent condition.
Short circuit capability is expressed in terms of: - MAX SHORT CIRCUIT TIME (twas
defined in figure 2) - SHORT CIRCUIT CURRENT & PEAK
CURRENT (ISHORT' IpEAK) Versus: - VG' RG, TC' Vcc· Figure 8 shows a characterization example of a IGBT having a high value of the transconductance. For VG ~ 13V the device fails at turn-on due to static latch-up.
3.0 SHORT CIRCUIT PROTECTION.
To ensure short circuit tolerance of a power control system and of its output power switches, the following problems must be carefully considered:
1 - Limitation of the short circuit current.
2 - Limitation of short circuit protection delay.
3 - Nuisance tripping creating false alarm.
3.1 DESCRIPTION OF THE PROTECTION CIRCUIT.
The figure 9 shows the schematic diagram of a protection circuit using the IGBT
saturation voltage for sensing. Sensing resistors or current transformers can also be employed without significant changes. The zener diode limits the gate voltage during a short circuit condition so limiting short circuit current. Delay 1 and delay 2 realized with a R, C filter and Schmitt trigger avoid activation of the protection circuit in case of false short circuit conditions. Delay 1 must filter transitory phenomena at IGBT turn-on, delay 2 gives noise immunity to the circuit. The diode "02" clamps gate voltage overshoots due to dV/dt.When a short circuit is detected the IGBT is turned off by its gate resistor in order to limit dV/dt and collector overvoltages. The timing diagram in figure 10 shows the working mode of the circuit at turn-on and with an overcurrent condition during operation:
- At turn-on, the input 1 of the "AND" becomes
high (IN HIGH = 8V) after delay 1; If IGBT
saturation was not detected (INLOW = 2V) during delay 1 the driving circuit input taken low.
------------ ------------- LW ~~~m~r::oo~~
5/9
743
APPLICATION NOTE
It
....J
fl-
CEo IOGVI Iv
II 'I
·
l
IC" IOOAI Iv
V--r--t\
. V
\
Va 10V/ Iv
.- . ~-.----
It
,f ;-' VCE" OOYI Iv
1/.
,~ n,.
J~ IC" OOAI Iv
/' ---- _._\\
-
4 Va 10Vt v
Fig. 11. Short circuit protection waveforms in the test condition "B". IGBT isTSG50N50DV. Time scale: 211S/div.
Fig. 12. Short circuit waveforms without voltage reduction of a IGBT having low transconductance compared to waveforms of figure 11 in dotted lines. t = 211S/div.
- When, during normal operation, there is a overcurrent condition, the IGBT saturation voltage reaches reference voltage "V REF" and the comparator activate the zener and the delay 2. If the overcurrent condition continues after delay 2, then the driver input is pulled down and the IGBT is turned-off.
This circuit works as a monostable multivibrator with positive edge triggering, but the IGBT is "ON" only if VIN is high, so the noise immunity is assured. If a overcurrent or a short circuit condition were detected, it is necessary to take VIN to the low.
3.2 PERFORMANCE OF THE PROTECTION CIRCUIT.
When the short circuit exists at turn-on (test circuit "A"), test conditions of the characterization are respected. The performances of the circuit can be critical when the short circuit occurs during normal working conditions and the device is in full saturation. Figure 11 shows that a significant current overshoot stresses the IGBT (STGP50N50) under this short circuit
condition even if the protection works correctly. In fact the protection circuit needs a delay to pull the gate voltage to a safe value. This delay depends on the saturation voltage detection time and on the discharge time of the IGBT input capacitance. The discharge time can be significant due to the Miller effect during collector voltage rise. Moreover a high value of gFS can induce a very sharp rise of the current during delay. To avoid this phenomenon, IGBTs with a lower value of saturation current and transconductance should be employed. In fact, if the short circuit current is limited by the device itself, then it is not necessary to reduce the gate voltage during short circuit time. Figure 12 shows collector current and gate voltage waveforms of an IGBT having
low saturation current (ICsa! = 3 · INOM
@ VG = 15V) subjected to the same short circuit condition shown in figure 11 and without any gate voltage reduction, compared to the STGP50N50 with high transconductance and gate voltage reduction during short circuit (same waveforms of figure 11 in dotted lines).
-6/-9 ------------------------~~~~~~~:~~ --~----------------------
744
APPLICATION NOTE
~~-
r I I YYI uu Gl\ uL ~M"
.f'--, ITH GATE CLAMP_
~ IC" OOA dlv -
/
'I
I
VG" tOV div
. -- -
Fig. 13. Gate voltage and collector current with and
without gate voltage clamping. t = 2~s/div.
Fig. 14. Cross section of IGBT structure and simplified equivalent circuit.
If the gate voltage reduction is eliminated a fast clamping circuit is necessary. Figure 13 shows a comparison of the gate voltage and collector current waveforms with and without gate clamping voltage. This diode also limits gate voltage overshoots in the short circuit condition.
3.3 SHORT CIRCUIT SPECIFICATION OF IGBTs.
The criteria for providing short circuit
protection to match the reliability of the more
usual protection circuits are:
- tw> SIlS
(delay to avoid false allarm)
- lesal < 3 · INOM (to ensure safe turn-off) - Tc = 12SoC (working temperature)
SIlS is the time necessary to ensure full
saturation of IGBTs.
To give sufficient margin for safe operation
tw'" 1OilS.
4.0 DESIGN OF AN IGBT UNDER SHORT CIRCUIT CONDITIONS
The intrinsic short circuit ruggedness of IGBTs was improved by a optimization of the device structure aimed at obtaining a suitable value of the saturation current ("Iesal" @ VG=1SV, Tj=1S0°C).
Parameters influencing transconductance and
lesal (lesal = gFS' (VG-VTH) saturation current also affect saturation voltage "VeEsal" [2] as shown by (1) and (2).
lesat =
(1 )
1 VCE = KT In r (1-upNp)dlc
+
l q
2qWRZDaniF(d/La)
(1 - upNp)Lele +
(2)
IlnsCoxZ(V G-VTH)
Where "Le" is the channel lengh, "Z" is the channel perimeter, "Cox" is the oxide capacitance (Cox = £ S/tox )' lesal can be limited both by reducing the gain of the PNP transistor (uPNP) and by acting on the MOSFET characteristics (Lc' Z, Cox), "uPNP" influence both the PN junction threshold (first term of equation (2)) and the second term. For this reason only the MOSFET characteristics were optimized, so gaining advantages both in dynamic performances (C G reduction) and in thermal stability [8].
------------- -------------Ii;i ~~~~m~r::I!~~
7/9
745
APPLICATION NOTE
PNP gain effect
MOS structure effect
4.5;...V~CE:.....:::sa::.t..!.(v~)_ _ _ _ _ _ _---.:I.:::C/-.:..I.:.:N~O~M·18
4
16
3.5
14
3
12
2.5
10
2
8
1.5
6
4
M
2
o 1 2 3 4 5 6 7 8 9 10 11 12 13
t WMAX(lls)
Fig. 15. Trade"ofi between saturation voltage and the short circuit ruggedness expressed as MAX tw and saturation current@VG = 15V.
To reduce the saturation current by 70%, channel lengh (Lc) and oxide thickness "tox" were increased by 40%. This gives the best compromise between short circuit performances and saturation voltage as figure 15 and 16 show. The lefthand side of figure 15 shows the effect of the PNP gain reduction due. to life time reduction processes.
5.0 CONCLUSION.
The analysis of parameters influencing short circuit operation of IGBTs has led to the design of a suitable protection circuit, even for devices having modest short circuit performance. This solution allows the use of IGBTs with very low saturation voltage. However, an additional very fast circuit that reduces gate voltage .during short circuit is necessary. During the delay of this circuit the dV/dt due to the IGBT desaturation can cuase a dangerous peak current. IGBTs having low transconductance .can solve this problem. Deacreasing transconductance of a IGBT
100
80
60
40
20
o~~~~~~_~-i_i-~_L-~
o 2 4 6 8 m ~ u re ffi ~
VCE(V)
Fig. 16. Comparison of two IGBT output characteristics, with low lesat (ICsat= INOM) and HIGH leSa! (10 · INOM) @ VG = 15V.
causes saturation voltage to increase. The optimization of the IGBT structure allowed the realization of an IGBT with sufficient short
circuit capability (tw MAX = 10 J.ls), and with
a value of VCEsat that is 20% higher than the
VCEsat of a IGBT having tw MAX =1J.ls. This
IGBT requires a simplified short circuit protection network and it does not compromise the efficiency or the short circuit ruggedness of the system.
REFERENCES.
[1] CELL GEOM ETRY ON IGBT LATCH UP. H. Ylmaz, member IEEE IEEE electron device letters, vol EDL-6, N°8, August 1986
[2] 'MODERN POWER DEVICES B.J. Baliga A Wiley Inter.
[3] PROTECTING IGBTs AGAINST SHORT CIRCUIT
G. Castino; I.A. corporation Italy
EPE journal, vol.1 n02, october 1991.
8/9
----------------L~I ~~~~~~~~ -----------------------
746
APPLICATION NOTE
[4] THE APPLICATION OF AN IGBT IN POWER ELECTRONIC CIRCUIT. M. Felovob, H. Amann, H. Stut, L. Lorenz, SIEMENS AG. PCIM91. Proceedings.
[5] A MODULAR GATE DRIVE FOR INSULATED GATE BIPOLAR TRANSISTORS. Sujit K. Bismas, Biswarup Basak, Hanshik S. Rajashekara CJadavpour univ., Calcutta IEEE lAS conf. 1991 proceedings.
[6] SAFE BEHAVIOUR OF IGBTs SUBMITIED TO A dV/dt. R. Letor, M. Melito SGS-THOMSON PCIM, 1990 proceedings.
[7] OPTIMUM DRIVING CIRCUIT FOR IGBT DEVICES SUITABLE FOR INTEGRATION. C. Licitra, S. Musuneci, A. Raciti, A. Galluzzo, R. Letor and M. Melito. SGS-THOMSON & UNIVERSITA' DI CATANIA. ISPSD'92 proceedings:
[8] STATIC AND DYNAMIC BEHAVIOUR OF PARALLELED IGBTs. R. Letor IEEE 1990 proceedings.
------------ LV ~~~~:~:::= ----'----------9/9 747
IrI..=,-l= S[KIGA]DS©OO-@1rn[HbrnO©'[M]'OSO@[OK!]ND©~
APPLICATION NOTE
SWITCHING WITH IGBTS: HOW TO OBTAIN A BETTER PERFORMANCE
by A. Galluzzo, R. Letor, M. Melito
ABSTRACT
IGBTs are now being used in a variety of switching applications due to their attractive characteristics, particularly their current density, ruggedness and gate driving circuit. To exploit the best aspects of IGBTs it is necessary to understand how their switching performance can be controlled by the designer and how much the voltage and current waveforms can be shaped to obtain an acceptable compromise in terms of switching speed, ruggedness, power dissipation and EMI.
This paper, starting with voltage and current waveform analysis, highlights both the device and driving circuit characteristics which govern the switching. It suggests, by using a simple driving circuit, how to control both voltage and current slopes, independently. The influence of negative gate bias and driving impedance versus dV/dt ruggedness are analyzed. Finally the IGBTs switching behaviour, when connected in parallel, is examined.
AN479/0492
1/10
749
APPLICATION NOTE
1 - ANALYSIS OF PARAMETERS WHICH INFLUENCE SWITCHING WAVEFORMS
The switching behaviour of IGBTs is affected The gate voltage was set at 15 V to give a
by the unavoidable parasitic capacitance of low Vcesat and also because this value is
the structure. Moreover the turn-off losses are applied as a standard gate voltage ,when
strongly dependent on the characteristic of the various device characteristics are defined in
tailing effect on the collector current during data sheets.
turn-off. Nevertheless switching losses can be predicted and then limited to an acceptable value, that is compatible with the need for safe and noiseless switching. The main parameters governing switching behaviour: gate bias, driving impedance, stray inductances, gate charge must also be taken into account. Fig. 1 shows a schematic circuit wh~re the parasitic inductances which influence switching behaviour are highlighted. In the following discussion it has been assumed that the stray inductances are small
enough so that dl/dt » VcC/{Ls+Lc+Ld).
1.1 TURN-ON
1.2 TURN-OFF
The IGBTs turn-off (fig. 6) can be divided into three consecutive phases: a) the gate voltage begins to decrease until it
reaches the value when the Miller effect occurs;during this phase the collector voltage increases slightly changing the output characteristics with Ic=constant. b) this phase is the Miller effect and the gate voltage remains constant because of modulation of the collector-gate capacitance. This is due to collector voltage rapidly increasing to its maximum value.
When the freewheeling diode is conducting c)the collector current begins to fall quickly (it
during turn-on switching (fig. 2) , increased
is related to the turn-off of the MOS part of
losses occur in the diode if the dlldt in the IGBT
the IGBT structure) then it continues with
collector is increased. However the losses in
a "tail" which is due to recombination of
the IGBT decrease with increasing dl/dt in the
minority carriers in the substrate.
IGBT collector (fig. 3).
This tail, which causes the major losses, is
Reducing dl/dt leads to higher losses in the strongly related to technology and its effect
power switch but it makes the reverse recQvery can not be mitigated by driving circuit.
behaviour ofthe freewheeling diode softer, thus After the collector current, collector voltage
reducing EMI problems. Fig. 4 shows dlldt and junction temperature has been
versus ,Rg with Lsas'a parameter. Ls includes determined, turn-off losses can be controlled
both stray inductances due to package and only during phase b) varying dv/dt through Rg
external inductances due to source grounding while losses occurring. during phase c) are
layout. These inductances strongly influence slightly influenced by the driving circuit.
dlldt at turn-on because they act as negative Increasing dV/dt decrease~ losses but it is
feedback to the gate thus reducing the effective necessary to take care not to exceed the
voltage applied to the device. This effect is RBSOA boundaries which also depend on
emphasized in fig. 5 where the collector and junction temperature, collector current and
gate current are shown.
collector voltage.
----------,.--- -- 2110 ---------- LV ~~~~~:=
750
, - -......--OVcc Ld
Lc
APPLICATION NOTE
I
~.
II
\ \
Ls
Fig. 1: Parasitic inductances influencing the switching behaviour
Fig. 2: Turn-on switching during freewheeling diode conduction
2 Cross-Over Energy (mJ)
switch turn-on losses
1.5
/
total losses
0.5
o~~=========~
50
100
150
200
250
dl/dt (AI~s)
Fig. 3: Switching losses comparison
200 dl/dt (AlIIII) 1110
100 00
100
Rg (ohm)
1000
Fig. 4: Rg and Ls int.luence on dlJdt during turn-on
vir
I\IS
1\ /J, '-''" .......
J \U\
""'-..'-- .....
I \ '\ r.
I '" J Ie
-"'. ,... ~ ......
MOSFET TURN-OFF
Fig. 5: Ic and Ig during turn-on
Fig. 6: IGBTs turn-off
-------'---------- '''I' ~~~~mgr::~~:: --------------3/10 751
APPLICATION NOTE
2 - HOW TO MANAGE DI/DT AND DV/DT
Useful information about switching behaviour of IGBTs. can be obtained from the gate charge curve. Even if the measuring conditions are quite different from the operating ones the total charge supplied to gate during switching is the same. The switching speed of a voltage driven device is strictly related to the rate of supplying charge to the gate input. This is true for IGBTs too, except during the falling edge of the collector current. If we are able to control the rate of supplying this charge, i.e. if we can manage the amplitude of the gate current during switching we can independently vary both the voltage and the current slope.
2.2 TURN-ON
The driving circuit shown in fig. 7 allows dl/dt to be varied through R1 but at the same time this resistance fixes the collector voltage slope. Increasing R1 leads to a lower dl/dt and also to a lower dV/dt which increases turn-on losses.
It would be useful to have a di/dt low enough to reduce EMI problems and a dV/dt fast enough to keep power losses to a minimum. It is possible to achieve that using a driving circuit which operates according to the schematic shown in fig. 8. The current slope is fixed by R1 and voltage slope by R2 by turning 02 on after 01 with a suitable delay. The waveforms in figures 9a and 9b show the difference between the standard circuit and the improved version.
2.3 TURN-OFF
The driving circuit can only control the slope of the collector voltage (fig. 10) and only slightly influences the fall of the collector current which is responsible of the major losses due to the tailed turn-off. Figures 11, 12 and 13 show the effect of Vc, Ic and Tj on the amplitude of the tail of the collector current. To minimize turn-off losses it is best to choose a device whose characteristics matches better the required operating conditions in terms of Vc, Ic and Tj.
R1
)~I
~ ; - - - - 4 - - - - - '
1
l
Fig. 7: Standard driving circuit
Fig. 8: Improved driving circuit
----,----------- 4/10
-------------L"11
~~~m~r::oo~~
752
APPLICATION NOTE
Fig. 9 a: Switching waveforms with standard driving circuit
Fig.9 b: Switching waveforms with improved driving circuit
STGP1ON50
dV/dt (V/IJS)
3000
.
,
2500
2000 1500 .......,...... .
1000 .
500
OL---~--~--~--------~--~
o 20 40 50 80 100 120
Rg (ohm)
Fig. 10: Rg influence on dV/dt during turn·off
STGP10N50
120 Itall %
100
80
60
.........................., ................T...e.. = 100°C
Ie = 10 A
40·····················....···...... Rg·ii·100..ofirif
20
....................... ..... "Vge'=-15'V'
o~---+----~----~---+--~
o 100 200 300 400 500
Vee (V)
Fig. 11: Itail versus collector voltage
SO !tall/Ie %
STGP10N50
40· .... · .. ·~·· 30 20 10
5
10
16
20
26
Ie (A)
Fig. 12: Itail versus collector current
STGP10NSO
120~1~=a~II~~~.--------------------~
1:::..... ~...:..:.
60 .. 40
Vee = 400 V Ie = 10 A
..... Rif·....roo..O/1lif
= 20 ................................ Vge 15 V .
o
o
26
50
75
100 126
TeI"C)
Fig. 13: Itail versus Tj
---------------------------~~~~~~~~:~~
5/10
---------------------------
753
APPLICATION NOTE
3 - HOW TO AVOID DV/DT PROBLEMS
The spurious turn-on problem due to dV/dt is typical of the circuit shown in fig. 14. The free-wheeling diodes in parallel with each IGBT are turned off during the opposite IGBT turn-on generating a dV/dt whose value depends on :
- opposite IGBT turn-on speed (dl/dt)
- free-wheeling diode "softness"
- wiring inductances
- gate bias and driving impedance
This applied dv/dt, acting through the cOllector-gate capacitance (fig.15) causes the gate voltage to rise turning the device on and leading to additional losses. This undesired effect is emphasized when temperature increases because of temperature dependence of Vth arid gfs. It is possible to avoid this effect either minimizing the dv/dt value or making the device less sensitive to dV/dt by a driving circuit specifically designed for this purpose or combining the two techniques above mentioned. The first item requires using fast soft recovery diodes, reducing wiring length and turning the IGBTs on slowly. The second one requires the driving impedance to be fixed at such low value that the gate voltage can not exceed the threshold voltage during dV/dt. The value of this driving impedance depends on die-size of the device: fig. 16 shows the Rge needed to avoid spurious turn-on due to dv/dt. Another way of avoiding spurious turn-on is to bias the gate negatively. Fig. 17 shows the different behaviour of gate voltage with and without negative bias. The lower peak of the gate voltage is due to the different equivalent input capacitance when the gate is negatively biased.
4 - PARALLELED IGBTS SWITCHING BEHAVIOUR
The influence of the spread of parameters, of drive circuit and lay-out unbalance was investigated splitting the analysis as follows:
a) driving IGBTs with one gate resistance for each device (fig. 18);
b) driving IGBTs with a common gate resistance for all the devices (fig.19);
c) unbalancing emitter wire connection (fig. 20);
d) paralleling devices with the maximum spread of the parameters.
The performed analysis pointed out that voltage and collector current waveforms are stable even in the worst case conditions which occur when the gates are driven with a common resistance and the wiring inductances are strongly unbalanced. In detail: - IGBTs behaviour during turn-on is not very different in a) or b) conditions (fig. 21 and fig. 22). If the paralleled devices have different storage times, driving the gates with one resistance for each device has the drawback shown in fig. 23: the collector current of the device having the smaller storage time begins to fall before the other one do. Consequently, because of the inductive load, the 2nd IGBT has to switch-off a collector current greater than the other device thus increasing storage current unbalance. Driving the gates with only one gate resistance minimizes this effect (fig. 24): the device with the higher storage time holds the gate voltage to "Vth + Ic/gfs" until the fall time phase, so equalizing the storage times. - The effect of a poorly balanced emitter connection is highlighted during the rising and the falling edge of the collector current.
-6/10- - - - - - - - - - - - LV ~~~~m~r::~~~ - - - - - - - - - - - -
754
APPLICATION NOTE
Fig. 25 shows the peak current unbalance, during turn-on, when the condition c) occurs. In the case shown ~Ls = 0.15iJ.H. Fig. 26 and fig. 27 show the corresponding effect during turn-off: wiring inductance imbalance affects only the power-MOSFET phase. This behaviour creates negligible switching losses imbalance compared with the total turnoff ones. The current unbalance just before current fall affects the tail amplitude and it can create significant imbalance in the switching losses. - IGBTs with the maximum spread in parameter values were paralleled; the comparison of current waveforms in fig. 21 and fig. 22 demonstrates that, during turn-on, the influence of parameter spread is low (Ls = 30 nH). The spread of IGBTs parameters (gfs, Vth, gate-charge) leads to different storage times and causes current imbalance thus creating switching losses imbalance. Current imbalance due to the IGBTs parameter spread can be calculated with the equations (2) and (3). The curve of fig. 28 shows the imbalance in switching losses between two devices where the Vth and gfs values are the limits of the parameter spread.
Iload = 11st + 12st = VGE (gls1 + gls2) -
(gls1 Vth1 + gls2Vth2)
(2)
Istorage = 115t - 12st = VGE (gls1 - gls2) -
(glSl Vth1 - gls2Vth2)
(3)
gate bias, dVIdt influence and effects of device paralleling. The following statements were explained: - it is possible to manage separately both the current and the voltage slope except the collector current tail; - negative gate bias reduces spurious turn on caused by dV/dt in bridge configurations; - negative gate bias without Rg adjustment reduces the RBSOA because of increased dV/dt; - common resistor on the gate of paralleled devices improves switching losses balance; - stray inductance on emitter connection reduces switching speed and can causes losses unbalance in paralleled devices; Performance improvements obtained by optimization of gate driving circuit involve cost increases. It is task of the system deSigner to define a good trade off between cost and performances.
Vee
CONCLUSION A careful analysis of circuit and device
parameters, influencing switching waveforms, was carried out taking into account negative
Fig. 14: Typical circuit where dVfdt conduction can occur
------------- !.V ~~~~m~r::G!~i:~ -------------7/10
755
APPLICATION NOTE
I· Ceg · dV/dt
1--
...J..
C
T,Ceg
I
W~ ...J.. _Cee I
E
Rg
dV/dt
Fig. 15: Current flow through IGBT capacitance due to dV/dt
100 V/div
dV~ d lH/+--+--+_I---I---I--l
I II
I
I~
I I
V"f = oj
2 V/div
~R~ge~(o~h~m~)____, -___________
250,
200
Tj = 100 'c
150
STGH2bN50
100
~=-= 50
01
0
4
6
8
dV / dt (KV /1.15)
J 10
Fig. 16: Rge values that avoid dV/dt conduction versus dV/dt
,----------0 Vee
Rgl
SV
I Irt-
2 V/div
Fig. 17: Comparison of gate voltage behaviour with and without negative bias
Vee
Vd
Rg2
O)--------------~----*------o
Fig. 18: Driving with separate gate resistance
,-----_>-----0 Vee
Rg/2
Vd
o)--------------~----*------o
Fig. 19: Driving with one gate resistance
Rg/2
o-------c=
Vd
o
Fig. 20: Emitter grounding unbalance
-8/-10---------------------------~~~~~~~:~~~ ----------------------------
756
APPLICATION NOTE
Fig. 21: Turn-on with separate gate drive (fig. 18)
of an STGH8N1 00. Ie = 2A1div
Fig. 22: Turn-on with one gate resistance (fig. 19)
of an STGH8N1 00. Ie = 2A1div
+ ! 2··11
i I
Fig. 23: Effect of separate gate drive on storage
current waveforms. Ie = 2A1div, Vee = 200/div, Vge = 10/div
Fig. 24: Turn-off with one gate resistance.
Ie =2A1div, Vee = 200/div, V ge = 1O/div
Fig. 25: Turn-on with unbalanced emitter-ground
connection (fig. 20). Ie = 2A1div
Fig. 26: Turn-off with unbalanced emitter-ground
connection (fig. 20). Ie = 2A1div
- - - - - - - - - - - - - - ~ ~~~;mg::i!~J: - - - - - - - - - - - - -9/1-0
757
APPLICATION NOTE
. · .... .. -',--'- -,- ---.--
2'.l IOPllis UZRI8
r ~D&II 9 7
,
I
Col· .
. ...
....
. ... ....
S1, 8.& I
-(
I
L
.... ~
I
, I
I'
~
l.,.
.rJ
I
I i-lll I
~
r~ ~
0
,.J.. .. I '~' ... ... ....
~ . ~ ..
. ...
I · !
.",!!!!!! . -~ !!!!!!
I
!
.1
'. ·1
I
Fig. 27: Turn-off current waveforms with balanced
gate-emetter wiring (fig. 19). Ie = 2Ndiv
0.3
0.25
0.2 .
0.15 --
:--~~;O~lO .C-
0.1 -
j--.----,---------- ---------
0.05
~--:~:~i;~:~::~~ ~~--~~~
_ _ oL---~--
L __ _~_ _ _ _L -_ _~
a
5
10
15
20
25
load Current (Al
Fig. 28: Switching losses unbalance
REFERENCES.
B. JA YANT BALlGA, "Temperatu re behaviour of insulated gate transistor characteristics". Solid state electronics vol. 28 W 3, pp 289-297,1985.
2 M. MELITO - F. PORTUESE, "Gate charge leads to easy drive design for POWER MOSFET circuits", PCIM June 1990.
3 SEBOLD R. KORN, "Parallel operation of the insulated gate transistor in switching operations.", PCIM June 1986.
4 D-S KUO, MEMBER IEEE, J-Y CHOI, D. GIANDOMENICO, C HU, SENIOR MEMBER, S.P. SAPP, K.A. SASSAMAN and BREGAR, "Modelling the turn-off
characteristics of the bipolar-mos transistor", IEEE ELECTRON DEVICE LETIERS, vol. EDL.6, N° 5, May 1985.
5 M. HIDESHIMA, T. KURAMOTO & A. NAKAGAWA, "1 OOOV 300A bipolar-mode mosfet (IGBT) module", Proceedings of 1988 International Symposium on Power Semiconductor Devices, Tokyo, pp. 80-85.
6 R. LETOR - M. MELITO, "Safe behaviour of IGBTs subjected to dV/dt", PCIM June 1990.
7 R. LETOR, "Static and dynamic behaviour of paralleled IGBTs", IEEE-lAS Annual Meeting October 1990.
-10-/1-0--------------------- !fi ~~~~~~r::oo~~ ----------------------
758
APPLICATION NOTE
SERIES CONNECTION OF MOSFET, BIPOLAR AND IGBT DEVICES
by R. Letor
ABSTRACT.
Fast power switches with voltage ratings much higherthan those of single fast switching devices can be made byconnecting BipolarTransistors, Power MOSFET and IGBTs in series. Problems associated with device characteristics such as balanced switching, steady state and thermal behaviour must be carefully considered when designing with such switches. This note deals with the series connection behaviour analyzing both static and dynamic characteristics of the devices. Two philosopies for driving circuits are
described and design criteria are given for obtaining optimum performance.
1.0 INTRODUCTION.
Advantages of BIPOLAR TRANSISTORS, Power MOSFETs and IGBTs reside in the simplicity of the driving circuit and on their high switching speed. But, applications of these devices are limited to maximum reverse voltage, generally up to 1000V - 1500V. Higher voltage ratings would make these devices unattractive due to problems related to their structure.
AN480/0492
1/11
759
APPLICATION NOTE
For example, theoretical ROS(on) of a Power MOSFET increases with the square of the
voltage breakdown (ROS(on) = 5.93 E-9 *
(VDSMAX)2.5). Figure 1 showing the real behaviour of SGS-THOMSON Power MOSFETs versus breakdown voltage, demonstrates that the current rating of three BOOV Power MOSFETs in series will be higher than a single 2000V Power MOSFET. Moreover, the design of IGBTs and BIPOLAR transistors with higher voltage ratings can be difficult due to the rise time of the switching waveform shown in figure 2. Therefore, in some applications like battery chargers, inverters for medium voltage lines such as railway traction using frequencies up to 20kHz or high resolution TV deflection with operating frequencies of up to 64kHz, the series connection of fast switching power devices can be an interesting solution. When connecting switching devices in series, vQltage sharing during the off-state, and during transient must be carefully considered. In fact the spread of leakage current creates unequal reverse voltage sharing. Delay between commutation due to switching time
differences causes transient overvoltage. If the parameters are temperature dependent, junction temperature difference must also be considered.
2.0 STEADY STATE VOLTAGE SHARING.
2.1 HOW TO BALANCE STEADY STATE VOLTAGE SHARING.
Figure 4 illustrates how the difference in blocking voltage characteristics results in unequal state voltage and how a resistor connected in parallel to each device (figure 3) equalizes the voltage sharing. Equations 1 and 2 can be derived from the graphical information in figure 4 and to evaluate the value of R that reduces the difference of blocking voltage to a fixed value ~VR with a fixed VM.
~VR12 = VR1 - VR2 = R1 * ~IR12
(1)
VM = VR1 + VR2 + ... + VRn
(2)
Equation (1) assumes that the leakage current is constant, this approximation is errs on the side of caution and introduces a safety margin.
RDSon (ohm*cm2)
1~--~--~------~~--~' 0.1 b~-------T.---:r--------1
~L- R~VE=------1 1.000E -03 f---_ _ _ _
.-..-..-..'.I.D.E."-'A=-L.,..CU___
1.000E-Q4 L---~~-'--"~~~~.~~~_--'---'
10
100
1000
VDSmax (Volt)
Fig. 1. Ideal and real behaviour of ROS(on) vs breakdown Voltage.
STORAGE TIME (~s)
3.5
2.5 --
/
/
1.5
/
1 /*
0.5
/
i
~
I
--I
o
o
500
1000
1?OO
2000
BVCES (V)
Fig. 2. Storage time behaviour versus rated BV CES for bipolar transistors.
2/11
-----------------------.L~I
~~~;~g~:~~
-----------------------
760
APPLICATION NOTE
V~h ~ yRn
I
R2
R1
Fig. 3. Connection of sharing capacitors.
If we suppose that device 1 has the lower IRM' VR1 will be the maximum reverse voltage (V R1 = VRM) and developing the equation (2):
VM = VRM + VRM - ~VR12 + ... ... + VRM - ~VR1n = n · VRM -l:~ ~VR1n-(3) The worst case condition, when n devices are connected in series, occurs when (n-1) devices have maximum leakage current and one device has the lowest possible leackage current: ~IR1n = ~IRmax· In this case, setting R1 = R2= ... = Rn' the solution of the equations 1 and 2 gives:
R = (n · VRRM - VM) 1 (n-1) · ~IRmax' (4)
1000 ;--IJA""---_ _ _ _ _ _ _ _ _ _--:-~_ ___,
INVERSE CHAR ACT. .. R
BOO
~~
-V-RI
600
400
INVERSE - CHARACTERISTICS
V1·V2 ..V3
Vl V2 1
2
Thousands V
VM
Fig. 4. Graphical calculation of sharing resistors when VM and tN R are fixed.
The difference in junction temperature depends on both differences of power dissipation and on the thermal resistance between devices.
~Tj = ~ (Rth · POISSIPATION)
Experience shows that ~Tj = 10°C is the maximum value for insulated devices mounted on the same heatsink. Using the derating shown in figure 5, for ~Tj = 1Q°C:
~IRT = 0.2 IRM.
Taking a safety margin we can use:
2.2 EVALUATION OF ~IRmax.
~IRmax is the sum of ~IRo + ~IRT' where: - ~IRo is the maximum leakage current
dispersion at a fixed VRand Tj. - ~IRT is due to the difference between the
junction temperatures of each device (~Tj). For devices today available ~IRo = 0.61RM @ VR = VRRM and Tj = 1QO°C.
~IR = 0.85 IRM.
2.3 EXAMPLE 1: series connection of three STHV82 Power MOSFETs: Ratings: Voss = 800V loss max = 1000J.1A @ Tj=125°C ROS(on) max = 20 @ Tj=25°C
Rthj-case = 1°C/W
------------- LV ~~~~mgr::il~J: -------------3111 761
APPLICATION NOTE
Conditions: Maximum blocking voltage: V M = 2000V Maximum Current and duty cycle: 1M = 3A, tonlT = 0.5 Case temperature:
TCASE = BO°C
Switching frequency: 50KHz. Calculation of sharing resistor values. Tj can be estimated using: ROS(on) @ Tj = 100°C"" ROS(on)(25°C) * 1.7
Tj "" Tcase + Rthj-Case * ROS(on) * ID2 * ton/T "" 100°C. For Tj = 100°C using the derating of figure 5: IRM = (1 - 0.6)mA "" OAmA For safety operation and reliability VRM "" 0.9 Voss = 720V. Using equation (4): R = (3 * 720 - 2000)/(2 * 0.4 E-3) = 200 kn. Maximum power dissipation of each resistor when ton=O: V2/R = 2.6 W.
10 ;;.::LE:ccAKc:cA=GE=-C:..:Uc.cRRc.::Ec..:.NT:....:(:::cmA"'-)_-c-'-_ _ _ _-:;o+--,
BIPOLAR TRANSiSTORS ........
m w w _ w _ 0.001 _ _ ""-_~~
~_~_~_----L_~
~
~
JUNCTION TEMPERATURE (OC)
Fig.5. Leakage current versus junction temperature.
2.4 IS IT POSSIBLE TO ELIMINATE THE SHARING RESISTORS?
For high frequency operation, it is necessary to consider the impedance of the output capacitance of the device which is in parallel with the sharing resistors. In the previous example the impedance of the STHVB2 output capacitance (150pF) is much lower than the calculated value of the sharing resistors:
ZCoss = 1/21tfCoss "" 21 Kn « 200Kn
Therefore, if only high switching frequency conditions are expected, then .the sharing resistors can be omitted.
3.0 DRIVING CIRCUIT FOR FAST SWITCHING DEVICES IN SERIES.
Two philosophies for driving switching power devices in series and for optimizing transient voltage sharing can be developed:
1) Driving each device in series with syncronized pulses and masking the difference of switching time.
2) Equalizing switching times with an optimized driving circuit.
Syncronized driving pulses can be generated by a transformer and delay turn-off time difference can be masked by snubber capacitors. When continuous mode and wide range of duty cycle are required, it is difficult to design a method for driving the transformer. In this case auxiliary supplies and optocouplers can be used. Equalization of switching times and continuous mode can be achieved using capacitive coupling between outputcircuit and driving circuit and diode network can be used for continuous bias.
------------- -4/11------------ I.." ~~~~r::i!~::
762
APPLICATION NOTE
3.1 DRIVING CIRCUIT GENERATING
SYNCRONIZED
PULSES
AND
TRANSFORMER COUPLING.
It is possible to achieve excellent synchronization of the driving pulses together with good control of the driving voltage and current. Figure 6 shows a driving circuit for both voltage and current controlled devices. The coupling inductances between the primary winding and every secondary must be as balanced as possible in order to equalize all the transfer impedances. In both circuits the device driving current is limited on the primary side of the transformer; this feature reduces the difference in delay turn-off time of devices in series. In fact during delay turn-off time or storage:
(101 + 102) = 10 · n2"n 1 Input impedances of devices'" 0
(-I B1 '" -I B2 = 10/2),
At the end of storage for bipolar transistors or at the end of Miller effect for voltage controlled devices (Power MOSFET, IGBT) the input
impedance becomes very high and the driving current fall, when the faster device turns-off, the device with the higher turn-off delay time increases its switching speed because it is driven by all the available current
(-IB(G) '" 10 ' n2"n 1))·
3.2 EQUALIZATION OF TURN·OFF DELAY TIMES USING CAPACITANCES.
In the circuit of fig ure 7, the capacitors transm it driving voltage to the high side devices and the diodes supply continuous gate voltage during the on state. The circuit works as follows.
During transition: We suppose that initially all Power MOSFETs are in the off state and capacitor voltages are balanced. When the positive edge is applied to drive circuit, P 1 turns-on and pulls down the source of P2' The capacitor network charges the gate of P2' P2 starts turn-on phase and pulls down source of P3 etc ... The turn-off phase is similar to the turn-on phase. When P1 turns-off, the source of P2 is pulled up. A negative voltage discharges the gate of P2 into the capacitor network turning
Vee cr-r--1'i
=
L
I
,------r---() D P3
D P2
Rd
Fig. 6. Syncronized Drive of fast switching power devices in series using a transformer.
D P1
DRIVE
o s
Fig. 7. Capacitors and diode network driving Power MOSFETs connected in series.
------------------~~~~~~~::~n ------------------------5/-1-1 763
APPLICATION NOTE
P2 off, etc. For a better voltage balance during switching, the capacitor must be charged to the same voltage (VC1=VC2=",=VC3); imbalance is due to Power MOSFET gate charge and discharge of the capacitors network. For this
fNmax = (n-1) * Q GATE CHARGE / n * C During on state:
VGATE(n) = VORIVE - (n-1) * (VOS(on)+VFdiode) Therefore, for full saturation of every device connected in series a driving voltage greater than 15V is necessary. Possible configurations. This circuit configuration can be used for series connection of IGBTs and BIPOLAR TRANSISTORS. When connecting IGBTs, sharing capacitors are necessary because the tu rn-off current tail of IGBTs does not depend onthe driving circuit.
ADVANTAGES: Using POWER MOSFETs this circuit allows optimum dynamic voltage balance with low values of capacitors so minimizing energy dissipation.
DISADVANTAGES: The circuit is critical when driving bipolar transistors due to high drive energy. It is difficult to optimize switching waveforms. You can see in Photo 1 that current fall waveforms are not correct. The driving voltage necessary for full saturation can be greater than the rated gate voltage. For better on-state and switching performances, a regulator for each POWER MOSFET gate must be introduced (Figure 8) and optimization of the driving circuit will be necessary.
EXAMPLE 2.
Photo 2 shows POWER MOSFET drain voltage balance and drain current behaviour in the ci rcu it of fig ure 7, where STH V102 devices are connected in series and in parallel.
C = 1500pF.
Q GATE CHARGE of 2 * STHV102 @ (VG = 15V) = 2 * 85nc = 170nc
fN = 170 E-9 /2* 1500 E-12 = 56.5V
Photo 1. Voltage sharing and drain current of two Power MOSFETs in series as described in the example 1.
I = 2Ndiv, V '" .500V/div.
Photo 2. Load current and voltage sharing behaviour of two BUV46 in series as shown in figure 5. Cs = 4.7nF,
Is =O.5A/div,I LOAD =2A/div, V =500V/div.
6/11
-------------------------~~~~~~~~::~-------------------------
764
APPLICATION NOTE
4.0 TRANSIENT VOLTAGE SHARING WITH SYNCRONIZED DRIVING CIRCUIT.
The transition overvoltages due to the difference between turn-off times can be controlled using sharing capacitors as shown in figure 9. During switching operation, discharge of the sharing capacitors generates power losses so reducing efficiency of the converter. In this note we define the losses of efficiency due to the capacitors discharge as follows:
Balancing losses/handled power = n · 0.5 · C
· V2 · f/(V M · Ie · duty cycle}.
4.1 HOW TO CALCULATE SHARING CAPACITORS.
Worst case condition occurs at turn-off with a inductive load. When the faster device in series turns-off, all the current load charges the capacitance in parallel to the slower device output·, and generates a fast voltage rise. Using suitable capacitances it is possible to retard the voltage rise and to fix ~VRas shown in figure 9.
f C = ~Q/~VR = t'(1 1(t} - 12(t}} dt 1 ~VR (5) t,
For n devices connected in series and
setting C1 = C2 = .... = Cn' ~t and ~I are
fixed to the maximum value.
4.2 SERIES OF BIPOLAR TRANSISTORS.
At turn-off the difference in storage time must be considered. In fact, denaturation at the end of the storage will cause collector voltage rise. For bipolar transistors the spread of this parameter, about 50%, is much higher than the fall time. For this ~Q "" IOFF · ~tslorage and the equation (5) becomes:
CMIN = IOFF · ~tslorage 1 ~VR max'
(6)
EXAMPLE 3: Series connection of two BUV46AFI.
Ratings: VCES = 1000V 1.SIlS < tSlorage < 2.5 Ils @ Ie = 2.5A;
IS1 = -IS2 = 0.5A, Te = 2SoC.
IC nom. = SA
161.1021--------.--, .
o S
Fig. 8. Driving circuit of figure 7for optimized driving voltage and switch-off.
11 12
Fig. 9. Evaluation of sharing capacitors reducing the effect of delay turn-off time spread.
- - - - - - - - - - - - - -------------l.1j ~~~~m&~:U!~~
7/11
765
APPLICATION NOTE
Conditions: Maximum turn-off clamping voltage: VM = 1600V. IOFF max. = 3A. Switching frequency: 15 KHz, duty cycle = 0.5 'B1 = -I B2 = 0.5A
Solution: For safety margin:
VCEmax = 0.9 * VCES = 900V I5.VR max= 2 * VCEmax - VM = 200V Using equation (6):
C2M1N = (3 * 1E-6)/200 = 15nF. The power dissipation due to discharge of sharing capacitors is: Balancing losses = PD = C * V2 * F = 144 W. (Balancing losses/handled power %) = PD / I * Vmax * 0.5 * % = 6 % For better efficiency this energy must be reduced. For this, it is necessary to limit the maximum spread by a selection of devices. If L'ltstorage = 300ns, then a 4.7 nF sharing capacitor can be used as shown in photo 2.
4.3 SERIES OF POWER MOSFETs. The current fali in POWER MOSFETs is very fast; equation (5) becomes:
I5.VR = IOFF * I5.tOFF / C tOFFmax can be calculated using gate charge, as shown in figure 7:
- tOFF = (01 + 0d'GATE
If 'GATE is balanced for ali devices in series, then I5.tOFF max can be calculated using the distribution of figure 11; moreover, due to
temperature independance of gate charge, temperature difference between junction devices can be disregarded:
- I5.tOFF = 5/100 * (typical value of tOFF) If each POWER MOSFET has its own driving resistor, then tolierance of resistors must be considered and delay turn-off time can be calculated as follows:
- tOFF = ta + tb = RGCGS In3 + 02 RG / (VDrive - GmID)
EXAMPLE 4: Series of two STHV102. Ratings: VDS = 1000V Gate charge: 01 + 02 = 62 nc ± 5% Conditions:
'G = 100 mAo Maximum clamping voltage:
VM = 1600V
IOFF = 3A F = 15 KHz, duty cycle = 0.5 Solution: For safety margin:
VDSmax = 0.9 * VDS = 900V 15.VR max = 2 * VDSmax - Vmax = 200V
I5.tOFF = 15. (01 + 02)/IG = 6.2 E - 9/ 100 E - 3 = 62ns.
CM1N = (3 * 62 E-9) / 200 = 930pF.(1000pF) PD @ F=15 KHz = C V2 * f = 9.6 W (Balancing Losses/handled power) = 0.4 % Photo 3 shows devices behaviour with the conditions of the example and C = 1500pF.
8/11
-------------
L..,/
~~~;t!'~r::I!~l:
-------------
766
APPLICATION NOTE
4.4 SERIES OF IGBTs.
Photo 4 shows the behaviour of two 1000 V IGBTs in series at turn-off using an inductive load with sharing capacitors (1500pF). Due to the high fall time value (figure 9), the total voltage (V CE1 + VCE2) can reach the clamping voltage before the end of current fall. Therefore, the equation (6) can not be
simplified and eNR must be split as follows:
~VR = ~VR1 + ~VR2
where:
~VR1 = V1 - V2 @t=ta (photo 4) is due both, to the delay turn-off time difference, and to the difference of current tail during voltage rise.
~VR2 is due to the difference of sharing capacitor charge when V1 + V2 = VCLAMP = constant"due to the difference of current tail and ~tFALL: ~V2 = ~02/2C
The minimum value of sharing capacitor can not be calculated easily due to the influence )f dV/dt on the current tail behaviour. For easy evaluation, the charge time of the
,haring capacitor (ta - to) must be equal to the
llaximum tFALL. In this case:
C = 2 * (IOFF - ITAIL/2) * tFALLmax
W R = ~VR1 = (~tOFF * (JOFF - ITAIL/2))/C + ~ITAIL * tFALLma/2C
~tOFF depending on gate charge spread is temperature independent.
TAIL' ~ITAIL' tFALL are temperature dependent as shown in figure 13.
EXAMPLE 5: Series of two IGBTs STGHBN100.
Ratings:
VCESmax = 1000 V ICmax = BA @ Tc=125°C
tFALL = BOOns ± 20% @ Tc =125°C
(see figure 9) Gate charge = 60 nc ± 5% (similar to STHV102)
Conditions:
VCLAMP = 1600 V ~VRmax = 200V ICmax = B A Tjmax = 125°C IGATE = 100mA f = 15Khz, duty cycle = 0.5
Solution:
C = 2 * (JOFF - ITAIL/2) * tFALLmax 1 VCLAMP = 7.B nF
~tOFF = ~ (01 + 02)/I G = 6.2 E - 91 100 E - 3 = 62ns.
~VR = ~VR1 = (~tOFF * (JOFF - ITAIL/2))/C + ~ITAIL * tFALLma/2C = 113 V Resulting ~VR« 200 V, a 6.B nF capacitor can be used and ~VR=130V. Balancing losses =
PD (15KHz) = C * V2 * f = 65W (Balancing Losses/handled power) =
PD / Vmax * 1* 0.5 = 1 %.
- - - - - - - - - - - - - - - - - - - - - - - - - 1,1."11 ~~~m~r::Ll!~~~
9/11
767
APPLICATION NOTE
Photo 3. Load current and voltage sharing of two Power MOSFET STHV102 in series as shown in figure 5. C s = 1.5nf, L'.toff = 60ns, I = 2Ndiv, V = 500V/div.
Photo 4. Turn-off behaviour of two IGBTs STGH8N100 in series with syncronized driving pulses. C = 1.5nF, Tj = 100°C. I =2a1div, ICHARGE=0.5Ndiv, V=200V/div.
11 VDS
iD-""
TURN-OFF WITH SNUBBER
Fig. 10. Turn-off behaviour of Power MOSFET when connecting snubber capacitors.
59.60 *..
********* ************** '" ***** '" '" *** *** '" ** '" '" ** *** *** ***** *"''''>Ie'''",*",,,, '" >Ie ** *** '" **** '" ********* '" ********* '" '" 62.92 *** '" **** '""''*''' **** ****** **** '" >I<
**** '" '" ** *'" '" ** '" ******* *"'* ** **
**************** **********
*.***··*****
66.24 *
Fig. 11. Spread of the Power MOSFET gate charge.
t
Ie
delay turn-off t fall Fig. 12. Current fall behaviour of IGBT devices.
Tfall (nsec)
1000-·---
900~
f 800
Itaillioff (%)
700 1-
Tlall
70
1 600
500[
50
400,
Itaillioll %
300
. 30
200
STGH8N100i
100 - - --L_ _""._l.~--------.L_ _ _~_ _~_ _~J 10
25
50
75
100
125
150
Tc (C)
Vce' 800V , le'8A , Vg'15V , Rgo 1000hm
Fig. 13. tFALL and current tail of IGBTs vs junction temperature.
768
APPLICATION NOTE
5.0 CONCLUSIONS.
Every switching power device can be connected in series successfully in order to make a power switch for fast switching applications working at a voltage greater than 1500 V. For optimum voltage sharing during steady state and switching, it is necessary:
- to make a compromise with the additional power losses introduced by sharing capacitors and by sharing resistors.
- that the junction temperature difference between devices in series must be as low as possible; especially for bipolar transistors and IGBTs.
Bipolar transistors require a selection by storage time. Power MOSFETs are temperature independent and have very low parameter
spread, making them easy to connect in series. IGBTs need considerable sharing capacitors, but these devices are attractive thanks to their very low saturation voltage and low driving energy. The driving circuit can be made either by using a trahformer for syncronized driving pulses, or with a diode and capacitor network. When using a transformer, driving voltage or current can be controlled easily, but, continuous mode and a wide range of duty cycle can be a problem . The diode and capacitor network allows equalisation of devices turn-off time, so reducing sharing capacitors value when gate voltage controlled devices are used. This method requires hard optimization of the circuit for very fast switching applications.
------------- ------------- Jjfj ~~~;m~~~:~~~
11/11
769
APPLICATION NOTE
NOVEL PROTECTION AND GATE DRIVES FOR MOSFETs USED IN DRIDGE-LEG CONFIGURATIONS
INTRODUCTION
The bridge-leg is an important building block for many applications such as drives and switch-mode power supplies. Simple gate drives with protection for POWER MOSFETs need to be designed for the "low-side" and the "high-side" switches in the bridge-leg. The POWER MOSFET can conduct a peak drain current, ID, which is more than three times its continuous current rating. The POWER MOSFET peak current capability and its linear operating mode are used to good effect in designing device protection ci rcu itry.
Bridge-leg configurations have a direct bearing on the degree of protection that can be incorporated. Consequently, bridge-leg configurations, protection concepts and gate drives are created simultaneously to design optimised and reliable power electronic circuits.
Figure 1 : Bridge Configurations.
BY C. PATNI
H.Y.D.C.
P A~O----~~UT
Do=±-
H.Y. GND a) Bridge-leg using Internal Parasitic Diode.
H.V.D.L
H-BRIDGE USING POWER MOSFETs
Three POWER MOSFET based bridge configurations are illustrated in figure 1. Figure 1a illustrates a bridge-leg which uses the internal parasitic diode as a free-wheeling diode thus reducing cost. However, since the reverse recovery of this parasitic diode is in the order of a microsecond, the turn-on switching times of the POWER MOSFET have to be increased in order to reduce the reverse recovery current. The turn-on time of the POWER MOSFET is controlled such that the pulse current rating of the intemal diode is not exceeded. Hence a compromise is made between maintaining the safe operating area of the MOSFET and reducing turnon switching losses. For example, an SGSP477 MOSFET has a diode pulse current rating in excess of BOA and a typical diode reverse recovery time of 300ns. A rate of change of current at turn-on, limited to 50Als, is a realistic compromise between reverse recovery current magnitude and turn-on losses. Consequently switching speed is sacrificed for cost. For switching frequencies up to 10kHz, when operating on a 400V DC high voltage rail, this configuration can be chosen as switching losses are limited, thus enabling a realistic thermal design.
B o - - j -_ _ _ _ _..J>-j
OUTPUT
H.V. GND S(-0324
b) Asymetrical Bridge-leg providing dildt Protection.
H.V.D.C.
,.
Ao--l~
,. OUTPUT
Bo--l1
~
H.V. GND
$(-0]25
b) Bridge-leg with blocking Diodes.
AN351/0689
1/6
771
APPLICATION NOTE
The turn-off speed of the POWER MOSFET in this configuration has no restrictions. Thus a fast turnoff is desirable to reduce turn-off losses. As the rate of change of current is limited, radio frequency interference (RFI) and electromagnetic interference (EMI) are reduced.
An asymmetrical bridge-leg, illustrated in figure 1b ; can be used to limit dildt during a short-circuit condition thus providing sufficient time to switch-off the appropriate power devices. The inductors limit the rate of rise of output current. They also limit the freewheeling current through the internal parasitic diodes of the MOSFETs. Adding external freewheel diodes and inductors increases reliability at the cost of increased complexity. The inductors reduce RFI and EMI as the rate of change of current is limited.
The configuration illustrated in figure 1c has Schottky "blocking" diodes to prevent current going through the MOSFET internal parasitic diodes. Schottky diodes are often used since conduction losses are kept to a minimum.
Bridge configurations shown in figure 1band 1care considered for high frequency switching applications. The advantage of the asymmetrical bridge-leg configuration over the bridge configurations in figures 1a and 1c is that the bridge-leg is capable of withstanding simultaneous conduction of the two devices in the bridge-leg since there are series inductors which reduce the dlldt under this condition. Hence the short-circuit detection loop time is not so critical and the devices are not stressed with high dlldt and high pulse currents.
The choice of the bridge configuration depends on the technical specification of the application. For ·example, if the technical specification for a specific application can be met by using the configuration shown in figure 1a, then this configuration should be used as costs are lower than with the other two configurations shown in figures 1band 1c.
GATE DRIVE CIRCUITS
The POWER MOSFET is a voltage controlled device, unlike the bipolar transistor which requires a continuous base drive. An application of a positive voltage between the gate and the source results in the device conducting a drain current. The gate to source voltage sets up an electric field which modu-. lates the drain to source resistance. The following precautions should be considered when designing the gate drive;
1 - Limit VGS to 20V maximum. Use of a gate to source voltage in excess of 16V has a marked effect on the lifetime of the device.
2 - Gate drive parasitic inductance can cause oscillations with the MOSFET input capacitance. This problem becomes more pronounced when connecting devices in parallel.
3 - There should be sufficient gate to source voltage for the transistor to be fully conducting.
Figure 2 : Gate Drive Circuits. a) Isolated gate drive with controllable switching times.
5(-0328
b) Simple gate drive for N-Channel MOSFETs in pa~ rallel.
.12V
c) Gate drive with VDS (on) control for short-circuit protection.
+12V
2/6 772
APPLICATION NOTE
Bipolar, MOSFET, CMOS or open-collector TTL logic can be used in the design of simple high performance gate drives. Totem-pole buffers, (figure 2a), are often effectively used to control the turn-on and turn-off individually. Figure 2b illustrates a total MOSFET based gate drive with which the switching speeds at turn-off can be individually controlled. CMOS or open-collector TTL logic can be used to drive MOSFETs directly, provided an ultrafast switching speed ( 50ns) is not necessary. In motor drive applications switching speeds of 100 to 200 nanoseconds are sufficient as switching frequency is seldom in excess of 50kHz. Discrete buffers are used to provide high current source and sinking capability when improved switching speeds are required or when MOSFETs are connected in parallel.
Short-circuit protection techniques similar to bipolar transistors may be considered for MOSFETs. VDS(on) monitoring permits the detection of short-circuit conditions which lead to device failure. The device can be switched off before the drain current reaches a value in excess of the peak pulse current capability of the MOSFET. This form of protection is very effective with MOSFETs as they can sustain a pulse current in excess of three times the nominal continuous current. Figure 2c illustrates a gate drive which incorporates VDS(on) monitoring and linear operating mode detection for the MOSFET in the case of short-circuit conditions. When the MOSFET is tu med on the on-state voltage of the device (VDS(on)) is compared with a fixed reference Voltage. At turn-on, VDS(on) monitoring is inhibited for a period of approximately 400ns in order to allow the MOSFET to tum-on fully. After this period, if VDS(on) becomes greater than the reference value, the device is latched-off until the control signal is turnedoff and turned-on again.
"HIGH-SIDE" SWITCH GATE DRIVES
The top transistor in a bridge-leg requires a "highside" gate drive circuit with respect to the bridge ground. Three possible gate drive concepts are shown in figure 3 :
a) The "bootstrap" drive, requiring logic signal isolation, but no auxiliary floating supply.
b) The level shifting drive.
c) The floating gate drive with optically coupled isolators, pulse transformers or DC to DC chopper circuit with transformer isolation.
Figure 3 ; Gate Drives for Top Transistor of Inverter Leg.
a) "Bootstrap" supply floating gate drive.
H.v.D.C.
BSUOPPOLYT--STRA'PPr~:::~~==~-r-
lOGIC
SIGNAL
5(·0329
b) Level shifting gate drive.
H:V.D.C. .12V
H.V.D.C.
~E')_"'M'~-I,'T
) ~
lOGlWl
SIGNAL
SC-0330
c) Floating supply isolated gate drive.
H.V.D.C.
ISOlATE;-rGATE DRIVE
lOGIC SIGNAL
5(·0331
Bootstrap supplies are particularly well suited to POWER MOSFET gate drives which require low power consumption. Figure 4 illustrates two bootstrap supply techniques. Bootstrap supplies limit transistor duty cycle since they require a minimum transistor off time during which they are refreshed.
3/6 773
APPLICATION NOTE
Supply efficiency and maximum duty-cycle are parameters which govern the design of the bootstrap. Figure 4a illustrates a conventional bootstrap with an additional capacitor, C1, which improves the maximum duty cycle as the supply is refreshed even during transistor on time by this capacitor. Figure 4b illustrates a high efficiency bootstrap supply which uses a small MOSFET, 01 , for regulation. In this design a low power bootstrap drives the gate of 01 .
The level shifting gate drive, (figure 3b), requires a high voltage p-channel MOSFET which drives the n-channel power device. The p-channel MOSFET is switched using a resistor divider network. No floating supplies are required. A power supply of 12V, referenced to the high voltage d.c., is used to provide positive gate source voltage. for n-channel POWER MOSFET. This circuit eliminates the need for logic signal isolation and a floating supply. The disadvantage of this circuit is the high cost of the pchannel drive MOSFET.
Figure 3c illustrates a floating gate drive with a floating supply. This drive is the most expensive out of the three shown in figure 3. However, the floating supply need only have a low output power, since MOSFETs are voltage controlled devices. The advantages of this drive are its high efficiency and unrestricted transistor duty-cycle.
Figure 4 : Bootstrap Supply Techniques. a) Conventional bootstrap with additional capacitor C1.
H.Y. O.c.
BOOTSTRAP SUPPLY
b) High efficiency bootstrap. H.V.D.C.
S(-0331 11
Figure 5 : Isolated CMOS Drive with Vos Control for Short-circuit Protection . · 12V
S(-03l3/1
R1 = Dependent
R4 = 1kD
on application R5 = 120kD
R2 = 10kD
R6 = 56kD
R3 = 22kD
IC1 = HCF4093
4/6
774
S[-0331./1
IC2 = HCPL2200
C1 = 560pF Dt = 1N41448 02 = BYT11/600
01 = BSS100 02 = SGSP477
APPLICATION NOTE
Figure 6 : Short-circuit Conditions for an SGSP477 VDS & ID.
VDS: 50V/OIV ID: 10A/OIV t : 2f.ls/OIV a) Output to high voltage short-circuit.
·m,o
,...,.. l'---
t-- t--
I
t"-
Il
- - - -..... 1
b) Outpulto Output Short-circuit.
5 -G]I.1
I--
.
/ /
V o/"
r--.. r-....
~ t-
----_.t
PROTECTION
Power electronic circuits such as bridge-legs are often required to have protection against output to output short-circuit, over-temperature, simultaneous conduction of devices in series in a bridgeleg and output to high voltage supply or ground rail short-circuit. These power stages are generally part of an expensive system such as a machine-tool or a robot motor drive. Thus the additional cost of protection circuitry is commercially acceptable. A compromise is generally reached between equjpment costs and the degree of protection required.
Short-circuit protection of a power MOSFET can be achieved by either VDS(on) monitoring or a current sense. In the previous section gate drives using the VDS(on) monitoring technique were presented. Figure 6 illustrates the MOSFET drain to source voltage, VDS, and the drain current, ID, when short-circuits are experienced by the POWER MOSFET, SGSP477, driven by the gate drive illustrated in figure 5.
The MOSFET is turned-off when the drain current increases sufficiently and VDS(on) monitoring is inhibited for a period of 400ns to allow the device to turn-on fully.
An inductor is used in series with the device, as illustrated in figure 1b. This inductor saturates when a large short-circuit current flows. The rate of change of the short-circuit current due to the saturation of this inductor is illustrated in figure 6a and 6b. Figure 6a illustrates the POWER MOSFET drain to source voltage, VDS, and the drain current, ID, when a bridge-leg output to high voltage supply rail short-circuit occurs. Figure 6b illustrates an output to output short-circuit of two bridge-legs.
Another protection technique uses the "current mirror concept", (1). An image of drain current is obtained by having a small MOSFET, (integral or discrete), in parallel with the main power MOSFET as illustrated in figure 7.
Figure 7 : The Current Mirror.
b
I::; N1 ~E N» 1000
T
~o
Voltage proportional
IIR
f to drain current ViO
S(·0335
Figure 8 illustrates a floating gate drive which utilizes a pulse transformer for transmitting simultaneously the MOSFET on-signal together .and the gate to source capacitance charging current. The current mirror technique is used to provide short-circuit and over-load current protection. The pulse transformer operates at an oscillating frequency of 1MHz when a turn-on control signal is present.
5/6 775
APPLICATION NOTE
The secondary is rectified to provide the gate source capacitance charging. voltage. The current mirror provides a voltage "image" of the main MOSFET drain current. This voltage is compared with a fixed reference voltage in order that the gate drive be
latched-off when the drain current becomes in excess of a specificed value. Figure 9 illustrates how the MOSFET, SGSP477, is latched-off when the drain current exceeds 10A with this gate drive circuit.
Figure 8 : Pulse Transformer Gate Drive with Current Mirror Protection for an SGSP477.
. L.l
. ON
R1 = 470Q R2 = 1kQ R3 = 33Q R4 = 2kQ R5 = 100Q R6 = 100Q R7 = 100Q R8 = 100Q
R9 =100Q C1 = 330pF C2 = 10nF
C3 = 10nF
C4 = 220pF 01 = 1N4148 02 = 1N4148 03 = 1N4148
Figure 9: Overload Current Protection using Current Mirror Concept with the Gate Drive of Figure 8 for an SGSP477.
S( 0)42
-,
(
(ontro'l
sign;a\
o
-
V i.--"
· t
Timescale: 5/ls1D1V -ID : 5NOIV - VDS : 100V/0IV Control signal: 5V/0IV - VGS : 5V/01V.
6/6 776
04 = 1N4148 05 = 1N4148 06 = 1N4148 07 = BZX85C15 08 = BZX85C15V
01 = { 02 =
03 =
small signal
n-channel MOSFETs
04 =SGS477 05 = BC337 06 = BC327 Q7 = BC337 08 = BC327 09 = BC337 010 = BC327 011 =BC337
CONCLUSION
MOSFET based bridge-leg configurations requiring protection and floating gate drives have been presented. Novel self-protecting gate drives for the "high-side" and "low-side" switching have been discussed. These drives provide protection against output to high voltage d.c., output to ground and output short-circuit. For the high-side switch "bootstrap" supply gate drive, level shifting gate drive and floating supply isolated gate drives have been compared.
Protection against short-circuit condition has been demonstrated using VDS(on) monitoring and the current mirror concept. Both techniques are well suited for protection against short-circuit conditions. However, the current mirror concept also provides a sufficiently linear image of the current for regulation.
REFERENCES:
1. Fuy G. Current-mirror FETs cut costs and sensing losses EON September 4 th, 1986.
APPLICATION NOTE
USE OF INTERNAL MOSFET DIODE IN BRIDGE-LEGS FOR HIGH FREQUENCY APPLICATIONS
By C.K. PATANI - D. STEED - J.M. CHARRETON
ABSTRACT
Reverse recovery of the intrinsic MOSFET diodes is investigated for the classical MOSFET and the MOSFET with minority carrier lifetime control. Turnon losses in bridge-legs using intrinsic MOSFET diodes limit the switching frequency particularly in the case of the classical MOSFET. Adapted bridgeleg configurations are presented which enable the use of the intrinsic MOSFET diodes for the free wheeling function in inductive load switching without any appreciable reverse recovery current and MOSFET turn-on switching losses!
INTRODUCTION
The MOS field effect transistor (MOSFET) contains an intrinsic PN diode within the structure which can conduct a current from source to drain. The PN junction diode is in fact part of a parasitic NPN bipolar transistor as shown in figure 1. Free-wheeling
diodes in bridge-legs are necessary when switching inductive loads. The intrinsic diode can be used .to fulfil this free-wheeling function. However, the intrinsic diode of the classical MOSFET has a long reverse recovery time and "snap-off" characteristic which can cause large dV/dt. The snap-off can result in the device failing in one of two ways. Firstly, due to internal capacitances, Cdb and Cbe, a base current may be established which turns-on the intrinsic bipolar transistor (see figure 1)1. Secondly, the dV/dt may be such that the drain to source voltage of the MOSFET exceeds the blocking voltage thus causing avalanche breakdown. This paper investigates various means of limiting the maximum reverse recovery current of the intrinsic diode to ensure reliable operation. A comparison is made between the novel solutions presented permitting the use of internal diode, and conventional solutions for using MOSFETs in bridge-legs, such as lifetime controlled MOSFETs and series blocking diodes.
Figure 1 : Equivalent Circuit for a MOS Field Effect Transistor (MOSFET).
Drain
Intrinsic NPN transistor
AN356/0689
1/10 777
APPLICATION NOTE
METHODS OF LIMITING REVERSE RECOVERY CURRENT
Limiting the reverse recovery current of the intrinsic diode can be achieved by stopping current from passing through the blocked MOSFET by means of a series blocking diode or limiting the rate of change of current in the intrinsic diode. The snap-off characteristics of the internal diode can be limited by having small RC snubbers across the drain to source of MOSFETS in bridge-leg configuration. Solutions which limit the rate of change of current in the intrinsic diode are discussed below.
BRIDGE-LEG DESIGNS UTILIZING MOSFET INTRINSIC DIODES
a) SOLUTION WITH UNCOUPLED UNSATURABLE INDUCTORS
In the circuit shown in figure 2, if T1 is blocked and T2 is conducting, the load current flows through T2.
As T2 turns-off the current transfers to the freew-
heeling diode D2, as the rate of change of current
into the intrinsic MOSFET diode of T1 is limited by
inductors L1 and L2. The zener voltage across Z2
causes the current to transfer from the external
freewheeling diode D2 to the intrinsic MOSFET
diode in T1until D2 no longer conducts (as shown
in figure 3). When T2 is turned-on subsequently the
current transfers from the intrinsic diode of T1 to T2.
The reverse recovery of the intrinsic diode is, how-
ever, lirnited by inductances L1 and L2. This can be
seen clearly in figure 4. The bridge-leg can be de-
signed (by dimensioning L1, L2 and Vz) such that
the external freewheeling and zener or transil diodes
only conduct for a small fraction of the freewheeling
period. Consequently, they do not have to be
mounted on a heatsink. The disadvantage of using
the zener is that the MOSFETs must now be rated
for at least the high voltage DC rail HVDC, plus the
zener voltage.
'
Figure 2 : Bridge-leg with Uncoupled Unsaturable Inductors.
HVDC
SGSP477
RZW5018 Z2 Transi I
02 BYW98 200
L1
7ull
Transi I BYW5018
Z1
L2
BYW98 200 D1
7ull
~
SGSP477
Inductive load 1load
HVGNO
2/10
778
Figure 3 : Transfer of Current to Intrinsic Diode.
APPLICATION NOTE
[t'"
::
V
./
V V
Figure 4 : Turn-off of the Intrinsic Diode.
Time scale: 211S/DIV Vos : SOV/DIV 10: 10AlDIV
Intrinsic Diode: 10AIDIV Current (110)
MOSFET : SGSP477
h
/ "-
/
1/
\
\ I.
I-!
Time scale: 1llS/DIV Vos : SOV/DIV 10: 10A/DIV
Intrinsic Diode: 10A/DIV Current (110)
MOSFET : SGSP477
Another advantage of inductances L1 and L2 in the circuit is that they limit the build up of current during fault conditions such as simultaneous conduction of the two devices.
L1 and L2 must be chosen such that their inductances are big enough to prevent intrinsic diode reverse recovery problems hence reduce losses. They must be small enough to allow current to transfer from the freewheeling diodes D2 and D1 to the intrinsic MOSFET diodes in T1 and T2 such that the average current passing through the external diode and zener or transil is low.
b) SOLUTION WITH MUTUALLY COUPLED INDUCTORS
Inductors L1 and L2 can be mutually coupled as shown in figure 5. Coupling L1 and L2 doubles the
inductance between transistors T1 and T2 (SGSP477), thus reducing the reverse recovery problem of the intrinsic diode as the rate of change of current is reduced. Coupling, therefore, saves the cost of one core and less windings are necessary to provide the same degree of protection as in the case of uncoupled inductors. The voltage and current waveforms of the MOSFETs and their intrinsic diodes for this solution are similar to that obtained with solution (a).
3/10 779
APPLICATION NOTE
Figure 5 : Bridge-leg with Mutual Inductors.
HVDe
· D2
L1
Transil Z2 L2
~
Inductive
load
-
Load Z1 Transil
D1
HVGND
C) SOLUTION WITH SATURABLE INDUCTORS
Saturable inductors such as toroids with a few turns can be used in the bridge configuration shown in figure 6. Saturable inductors are better suited than non-saturable inductors in so much as they can be used to limit the reverse recovery of the intrinsic diode to an almost negligible level. The saturable inductor is designed to saturate after the intrinsic diode has reverse recovered. Before saturation the inductor presents a high impedance and only a low magnetising current flows.
In figure 6, it is assumed that T1 and T2 are blocked and the intrinsic diode of T1 is conducting. If T2 is now turned-on, the current in the intrinsic diode decreases rapidly since inductor L1 is saturated until this current reverses resulting in negative volts-seconds across the inductor which thus desaturates. The inductor thus presents a high impedance while the current through it is equal to or less than the magnetising current. The intrinsic MOSFET diode
begins to reverse recover as the current through it becomes negative. The inductor is designed not to saturate for a period of at least 1~s, thus enabling the reverse recovery of the intrinsic diode without excessive reverse recovery current. There is a certain degree of minority carrier recombination while the inductor is unsaturated which also reduces the maximum reverse recovery current, IRM. The reverse recovery of the intrinsic diode can be seen in figure 7.
While T2 is conducting the load current inductor L2 is saturated. When T2 turns-off the MOSFET current transfers to diode D2. The free-wheeling current path through the intrinsic diode of T1 has a high impedance due to L1 being unsaturated. Consequently the build-up of current through the intrinsic diode of T1 is slow until this current reaches a value equal to the magnetising current, Imag, of inductor L1 which then saturates. This effect can be clearly seen in figu re 8.
4/10
780
Figure 6 : Bridge-leg with Saturable Inductors.
HVOC
APPLICATION NOTE
02
Z2
L __ ......_ _ _ _~
HVGNO
The turn-on of the MOSFET in the solution with saturable inductors (shown in figure 6) is illustrated in figure 9. It can be seen that the MOSFET losses are negligible, since the saturable inductor in series with the MOSFET that turns-on, limits the rate of rise of current while it is unsaturated. Figure 9 also illustrates that the reverse recovery of the intrinsic diode of the free wheeling MOSFET is also limited ..
In the bridge-leg with saturable inductors (figure 6), if transils (Z1 and Z2) and resistors (R1 and R2) are removed, the external free-wheeling diodes have to be of high current rating as they conduct all the load current until the saturation of L1 and L2. Subsequently the external diode shares part of the freewheeling current with the intrinsic diode. It is advantageous to reduce the current through the external free-wheel diodes 01 and 02 as rapidly as possible for the following reasons:
1. If 01 and 02 conduct for a small fraction of the maximum free-wheeling duty cycle, then their power rating is substantially reduced.
2. If the free wheeling current through the external diode 01 orD2 is reduced rapidly, the inductor in series (L1 or L2) is no longer saturated. At the consecutive turn-on of T1, L1 presents a high impedance thus performing a turn-on snubber function. Transistor turn-on losses are thus minimised particularly for inductive loads.
3. Output short-circuit protection is also enhanced if the inductors are unsaturated prior to transistor turn-on.
The current through the external free-wheeling diodes can be reduced rapidly by increasing the rate of release of inductor stored energy by transils (Z1 and Z2) and/or resistors (R1 and R2) as shown in figure 6.
5/10 781
APPLICATION NOTE
Figure 7 : Reverse Recovery of Intrinsic Diode using Saturable Inductors in the Configuration of Figure 6.
, ~
Time scale: 500ns/DIV
"
~
Intrinsic Diode Current liD: 10AlDIV
-"/
j
Voltage across MOSFET intrinsic diode VID: 50V/DIV
Time scale: 500ns/DIV
Figure 8 : Transfer of Current to Intrinsic Diode using Saturable Inductors in the Configuration of Figure 6.
~ J
)
h
\
/
./
-H+
/'
VDS : 50V/DIV ID: 5A1DIV
Intrinsic Diode: 5A1DIV Current (liD)
MOSFET : SGSP477
Figure 9: Turn-on of the MOSFET in the Configuration with Saturable Inductors. (The turn-on snubber and the intrinsic diode reverse recovery actions are illustrated).
\.
:H++ /'" r- ~
V
" t-'
6/10
7.82
Time scale: 500ns/DIV VDS : 50V/DIV ID: 10AlDIV
Intrinsic Diode: 10A/DIV Current (liD) MOSFET : SGSP477 .
APPLICATION NOTE
Table 1 : Advantages and Disadvantages of Solutions for limiting Reverse Recovery Current in the Intrinsic MOSFET Diode.
Sol.
Type of Protection Used
Advantages
Disadvantages
a) Unsaturable Inductors
- Reduction of turn-on losses. - Controlled dlldt at turn-on. - Controlled reverse recovery of
intrinsic diode.
- In order to use low current rated freewheeling diodes, transi! diodes have to be used . increasing the voltage rating of the MOSFETs in the circuit.
b) Unsaturable Mutual Inductances - Smaller and less expensive than - As above. two inductors since only one coupled inductor.
- As above.
c) Saturable Inductors
- Negligible turn-on losses. - Negligible intrinsic MOSFET
diode reverse recovery losses. - Controlled dlldt turn-on.
- As above.
COMPARISON OF USE OF INTRINSIC MOSFET DIODE WITH ALTERNATIVE SOLUTION
Figure 10 illustrates three bridge-leg configurations that can be used with MOSFETs when switching inductive loads. Figure 10a) illustrates a bridge-leg which uses the intrinsic diode of a classical MOSFET having a reverse recovery in the order of a microsecond. The same configuration can be used with a lifetime controlled MOSFET which has an intrinsic diode having a reverse recovery time around 250ns. An asymmetrical bridge-leg illustrated in figure 10b), is similar to the above mentioned solutions permitting the use of the intrinsic diode. The configuration illustrated in figure 10c) has series
Figure 10: Bridge-leg Configurations.
"blocking" diodes which prevent conduction of the intrinsic MOSFET diodes and thus avoid reverse recovery problems associated with the slow intrinsic diodes. In this configuration fast recovery epitaxial diodes are used as external free wheeling diodes.
Tests were performed using 500V, 0.6 ohm at 25°C classical MOSFETs (BUZ353) and lifetime controlled MOSFETs in the bridge-leg illustrated in figure 1Oa). Experimentally obtained losses within the diode and the MOSFET at turn-on are presented in figure 11. The solution enabling the use of the intrinsic diode without reverse recovery problems (figure 1Ob) has practically no losses due to reverse recovery of the intrinsic diode.
a) Bridge-leg using intrinsic MOSFET diode
b) Asymmetrical bridge-leg providing dildt protection, turn-on snubber and limited reverse recovery problems
c) Bridge-leg with series blocking diodes and fast freewheeling diodes
7/10
783
APPLICATION NOTE
Figure 11 : Turn-on Losses in a Bridge-leg. Turn-on Losses in the MOSFET
WT
(pJ)
4000
Classical MOSFET
3000
2000
1000
Lifetime controlled MOSFET
BYT12P600
L_~5-0--1OT"0--1'50--2::-:0'-':D:--~2::-:5~D:----'d i Idt (AI ~s)
a) Turn-on losses in the MOSFET when switching 10A inductive load current on 400Voc rail as a function of the rate of change of MOSFET drain current (dlo/dt)
Reverse Recovery Losses in the Diode
lid (I'J)
1500
1000
with classical MOSFET
500
wi th l Het ime cant rolled MOSFET
BYT12P600
o ~-~----~-----~--.
50 100 150 200 250
di Idt
(AIl's)
b) Reverse recovery. losses in the freewheeling diode when switching 10A inductive load current on 400Voc rail as a function of the rate of change of freewheeling diode current (dIFD/dt) during diode turn-off.
8/10
784
APPLICATION NOTE
Figure 12 : Turn-on Ilustrations of the MOSFET Drain to Source Voltage (Vos) and Current (10) at Turn-on of the Transistor Limited to 1OOA/~s.
A
/
" - / It /
I /
a J
a) Classical MOSFET (500V, 0.6 ohm) BUZ353
Diode losses = 540~J
MOSFET losses = 3200~J
Vos MOSFET drain to source voltage 100V/DIV 10 Drain current 5NDIV Time 200ns/DIV
/~
11'"
/
\ I\,.
/
/
tw.
b) Lifetime controlled MOSFET (500V, 0.6 ohm)
Diode losses = 460~J
MOSFET losses = 1600~J
Vos 100V/DIV 105A/DIV Time 100ns/DIV
- r--..
1/
"1'\
/
"N /
!'(
J
c) External fast diode BYT12P-600
Diode losses = 130~J MOSFET losses = 560~J
Vos 100V/DIV 105A/DIV Time 50ns/DIV
It can be seen that due to the slow intrinsic diode of the classical MOSFET, turn-on losses are twice that with a lifetime controlled MOSFET. With external
fast freewheeling diodes losses are only 20% of the losses in the classical MOSFET.
9/10
785
APPLICATION NOTE
CONCLUSION
Reverse recovery of the intrinsic MOSFET diode has been investigated. Losses caused by slow intrinsic diode recovery for the classical MOSFET have been compared with losses using lifetime controlled MOSFETs in a bridge-leg and losses using fast external freewheeling diodes. It has been shown that turn-on losses in a bridge-leg using classical MOSFETs are five times greater than losses in bridge-legs with fast external freewheeling diodes and two times greater than losses in bridgelegs using lifetime controlled MOSFETs.
By using different types of inductors (such as saturable inductors) in bridge-legs it has been shown that negligible turn-on losses can be achieved as reverse recovery of the intrinsic MOSFET diode can
be limited. Practical results confirm that by using saturable inductors astutely in bridge-legs, it is possible to use the intrinsic diode of the classical MOSFET in high frequency inductive load switching applications with negligible turn-on losses.
REFERENCES
SGS
"Power MOS Devices", 1st Edition, October 1985.
2 J.T. DAVIES - P. WALKER - K.I. NUTTALL
"Optimisation of VDMOS power transistors for minimum on-state resistance", lEE Proceeding, vol. 134, PT.1, No.3, June 1987.
10/10
786
APPLICATION NOTE
ENVIRONMENT DESIGN RULES OF MOSFET IN MEDIUM POWER APPLICATION
ABSTRACT
The use of POWER MOSFET allows high switching speed in power applications above 10kW. Nevertheless the main limitations come from the characteristics of the circuit design. From a practical example, this paper analyses and proposes solutions to adapt the POWER MOSFET and the layout in order to minimize parasistic inductances. Special emphasis is given to the driver circuit, package, wiring rules and voltage spike protection at turn-off.
I - INTRODUCTION
POWER MOSFETs are now considered standard tools by circuit designers working at tens of Amps and hundreds of Volts. Their traditional advantages (easy drive and over current capability) remain true when switching over 10KWatts. Nevertheless, the main limitations encountered are not from the MOSFET itself as it can switch high cu rrent at high speed (over 1000Amps/sec), but from characteristics of the circuit design. After presentation of a specific example of Power MOS drive, the optimisation of the power devices and the layout will be analysed in the practical example of a chopper operating with ISOFET (1000V - O.7Q or 100V - O.014Q). Finally,
BY B. MAURICE
an over-voltage protection circuit is presented.
II - HIGH POWER MOS DRIVE
Even with high power switching (over 10KW), the driver circuit can be very simple (fig: 1), comparable to the ones used for low power circuits.
The major characteristics of a POWER MOSFET is its high input capacitance (ie : Ciss ~ 12nF for 100V - 14mQ MOSFET) which must be rapidly charged and discharged when switching without creating oscillations.
The following rules have been used for the design of the driver : · A low dynamic internal impedance which permits
peak current greater than 1Amp for 300nanosec to charge and discharge the ISOFET input capacitance. .· A low impedance circuit reduces the sensitivity to dVDs/dt at turn-off of the ISOFET. · The total resistance of the gate circuit must be greater than 5Q in order to sufficiently damp the circuit preventing oscillatiohs and possible parasitic turn-on of the ISOFET.
Figure 1 : Driving Circuit for ISOFET Over 1OkW Switching.
VOCo-------------------~--------~._--
1SV
3.3I.rf'
~t AN358/0689
SGSP322
BZX55C l8V
SGSP322
BZX55C l8V
Qi = 1OOV O.4Q P-channel MOSFET
lSOFET TS05MG40V
1/9 787
APPLICATION NOTE
· The links between drive and gate, short and noninductive, are made between the gate pin and the "Kelvin Source" pin. The use of the "Kelvin Source" pin is very important when driving Power MOS. It
avoids parasitic effects caused by dlldt in the source lead.
· The gate protection Zener diode has to be mounted close to the ISOFET package.
Figure 2 : Over Current Capability and Switching Speed with ISOFET TSD5MG40 (1000V -0.7Q-ID = 13A). a. Turn-on; the ISOFET controls 30A-650V and sustains 11 OA peak (8 x ID). The over current is due to the recovery of the free-wheeling diode (BYT230PIV 1000). b. Turn-off; with dlldt = 1600A/usec ; and dV/dt = 15000V/usec. The switched power = 25kW ; and the switching losses = 1.3mj
a. Turn-on VO = 200Vldiv 1D=20Ndiv
t = 50nsldiv.
Rg=5Q
III - LAYOUT DESIGN FOR HIGH SPEED SWITCHING
The reduction of the parasitic inductances is a major challenge for power switching especially with a power MOSFET switching over 1000Amps/usec (figure 2). With this switching leading edge, a 10cm diameter wiring loop causes a 100V voltage overshoot. To solve this potential problems two actions are necessary: choosing a well adapted device and optimise the layout design.
a. Adapting the device to the layout
ISOFET is a MOSFET housed in an ISOTOP package (figure 3) :
b. Turn-off
VO = 100Vldiv
10= 10Ndiv
· The ISOTOP package can be directly screwed on the printboard because all of its terminals are at the same level. Therefore, all inductances due to the length of external wiring connexions, are eliminated.
· As a result of a low profile package (12mm), the internal parasitic inductance is less than 10nH. Moreover, its Kelvin source (KS) enables the minimisation of disturbances induced by the power circuit in the driver circuit.
· Even though it has a thermal resistance value of only 0.25°CIW, the case is fully internally insulated at 2.5kVRMS. Therefore it can be mounted near to the diode package on a common heatsink in order to obtain a very compact circuit layout.
2/9
788
APPLICATION NOTE
Figure 3 : An ISOFET is a MOSFET housed in an ISOTOP package, which has a low profile. It is easily integrated in low inductive layouts. The "Kelvin Source" lead (KS) separates the gate circuit from the internal inductance of the source connection.
IS mm
12 mm
b. Design of the layout The chopper shown in figure 4 contains two active components: the Power MOS and the freewheel-
ing diode; both in ISOTOP package screwed side by side, on a common heatsink and directly connected on the printed circuit board (PCB).
Figure 4 : a. Chopper Schematic showing the Inductive Loop to be Reduced.
b. The Same Circuit with two ISOTOP Packages (diode and ISOFET). The packages and links adopt an "in line" configuration in order to reduce the inductive loop.
a
.
L»IXJCT:tVE LOOP TO BE REDUCED
3/9
789
APPLICATION NOTE
b LOAD
+
ee0V
..-.....-.........-..-...--... .~
o G9
~s s
By observation of the facts presented in appendix 1, the design rules used for the layout are summarized:
· Use of double sided PCB where each high current path is immediately above its returns path on the other side of the board.
The current densigy has been reduced by enlarging the copper tracks in order to decrease the local dlldt and consequently the resulting induced voltage.
Use of several links instead of one, between two large copper tracks, avoids high current concentrations and reduces the inductance (figure 5).
· Oecoupling capacitors have been configured in the same direction as the direction of current flow. This prevents the formation of an inductive loop. (compare figure 6a and figure 6b hatched surfaces).
The use of several smaller capacitors in parallel permits reduction of the equivalent internal parasitic inductance. (figure 6c).
· Choose components (e.g. capacitors) specified with a low intemal inductance. (electrolytical capacitor 700llF/400V can have a parasitic inductance of several tens of nH). Prefer the capacitor packages which minimize the inductive connection length.
Figure 5 : Junction between two wide copper tracks is less inductive when several spaced links are used rather then a single link.
-e
e = L x dI/dt
- e'
e'= 1/3 e
4/9 790
APPLICATION NOTE
Figure 6 : Configuration of Decoupling Capacitors: a. An inductive loop is formed, perpendicular to the current flow, because the current flow is not super imposed near the capacitor, b. Capacitor lying in the same direction as the direction cif current flow. inductive loop minimised. c. Several smaller capacitors in parallel reduce their equivalent internal parasitic inductance for the optimum solution.
5/9 791
APPLICATION NOTE
As a result the residual inductance of the finished layout (fig. 7) has been measured as 35nH. (fig. 8)
plus 15nH when a current sensing loop (15mm2) is added to the layout
Figure 7 : A Double Side Very Low Inductive Print Circuit Board. (scale: 0.5) Note the Multi Links (A) to connect One Side to the Other.
I entree · ·cde · · 00
...
..
o · o ·
· ·
~OC70
o
· -
drive. rnax1Bv
HT rnaxBOOv
POWER MOB .IBOFET
SIDEA
o 0
o
L
a
6/9 792
SIDE B
APPLICATION NOTE
IV - OVERVOLTAGE DURING TURN OFF
We have previously seen that by following these sound rules a parasitic inductance value of 3SnH can be achieved. It represents the sum of several small components : active components. passive components and PCB. It seems difficult to reduce it further in a circuit without paralleling several power switches. In view of the ISOFET fast switching speed at turnoff (1 OOOAmp/usec), the inductive voltage spike with 3SnH will be 3S Volts. This overvoltage is accept-
able for devices rated over SOOV. It is not negligeable in low voltage applications such as battery powered equipment.
Two solutions are possible:
a. Slowing down the ISOFET
The switching speed at turn-off can be slowed down by increasing the gate resistor value. This' method increases the commutating time and consequently the switching losses. These losses are increased by SO% when Rg increases fro S to 10n. (figure 8).
Figure 8 : Increased Gate Resistor reduces dlldt and Overvoltage at Tum-off. (driver circuit fig. 1). The
total parasitic inductive loop (SOnH) includes the inductance of the sense current loop.
ID = 10AIdiv VD = 100V/div t = SOns/div (ISOFET TSDSMG40V 1OOOV - o.m)
Switched power = 2SkW ; Switching losses = 1.3mJ in (a) and 2.0mJ in (b).
b. Protection against over-voltage at turn-off
Use of a MOSFETwith a low margin forthe rating voltage (VBR(DSS)) can be achieved by using active protection (i.e. Transil) in order to clamp the voltage spikes.
One solution is to connect a Transil acros the drainsource leads. In this case, the energy is dissipated in the Transil which has to be cooled in order to dissipate the average power.
(1/2 Ll2f = 20W with 40nH, 100A, 100kHz)
We have chosen another solution by connecting the Transil across the drain-gate leads (figure 9). When the over voltage transient reaches the clamping voltage, the clamping current goes through the gate resistance and biases gate above SV. (ex: 1A into 5£1).
This way, the clamping power is dissipated in the MOSFET and a smaller Transil is required (P ~ 1W at 100kHz in our case).
As the Transil does not heat up, the clamping voltage does not vary with temperature. The equivalent dynamic resistance is very low because the serial resistance of the Transil is divided by Rg and by the MOSFET transconductance.
The current though the Transil being low, the voltage to be considered for its choice is the breakdown voltage at test level (VBR at IR) instead of the surge clamping voltage (VcL). The Transil breakdown voltage should be chosen to be lower than the maximum desired clamping voltage less 5 Volts to take into account the MOSFET gate threshold voltage.
7/9
793
APPLICATION NOTE
Figure 9: Over Voltage clamping by a Transil across the Drain-gate Leads durring turn-off. (ISOFET TSD4M150V 1OOV - 14mQ). Upper Trace shows the Current in the Transil (IT).
ID = 20A/div, VD = 20V/div, IT = 1Aid iv, t = 100ns/div.
.-
I
- - - - .I .'
IT
~ t------<>--~1t IN4148 BZW06-78
·....
v,
v - CONCLUSION
MOSFETs switching power over 10kW have the same basic advantages as lower power Mosfe!. The driving circuit remains very simple and the over current capability is huge. A specific emphasis has been placed on the minimization of circuit layout inductance. Because of the very fast switching (easily over 1000A/s) it is advantageous to use:
packages like ISOFETwhich minimise their intemal inductance and allow easy connection to printed circuit board and to heatsink. Also Kelvin Source contact to minimise drive circuit interference.
double side printed circuit board with symmetrical
copper tracks, reduced current concentration, and components positioned in order to minimise parasitic inductance. overvoltage protection which avoids oversizing the voltage rating of MOSFETs in low voltage applications.
BIBLIOGRAPHY
[1] An Innovative High Frequency High Current Transistor Chopper. L. PERIER ; E.P.E. Bruxelles 1985.
[2] POWER MOS DEVICES Data Book 1st edition June 1988 SGS-THOMSON Microelectronics.
8/9 794
APPLICATION NOTE
APPENDIX 1
MEASUREMENT OF PARASITIC INDUCTANCES ON A DOUBLE SIDED PCB
_ In the figure below, the link between points C and
D simulates the connection of a capacitor with nap internal inductance, connected on double sided Printed Circuit Board.
Figure 10.
A
I, dI/dt"~_~,,_
n
~~~---------200rnm
_ The measurements are made with ad I/dt generator:
a _ I = to 40Amps with a dl/dt = 1000Als
MEASUREMENT RESULTS Figure 11.
The measurement of the induction voltage
VL between A to B, and C to D, permits cal-
culation of L = VL I (dl/dt)
L,,=35nll (5+30) r.",=30nl!
~
:J:
I,,,=110nll (90+30) Lco=30nll
L"9=10nll (3-1-7)
Lco=7nl!
LA,=5nl! (3+2)
Lco=2nll
AJ 8· L",=14nH (12+2) r.",=2nll
MEASUREMENT CONCLUSIONS
· Capacitors should be positioned in the same direction as direction of current flow. Compare : a. to b.
· Several links between two large copper tracks are less inductive than a single link. Compare: b. to c.
Every current path should be exactly above its return path on the other side of the board. Compare: d. to e.
· Decrease local dl/dt density by enlarging copper tracks. Compare: c. to e.
9/9
795
APPLICATION NOTE
COMPACT HIGH PERFORMANCE BRUSH D.C. MOTOR SERVO DRIVES USING MOSFETS
ABSTRACT
For medium power (200VA to 6kVA) brush D.C. motor SeNO drives, MOS field effect transistors (MOSFET) are ideally suited. A compact high performance (20 to 50kHz) 1.2kVA brush D.C. motor velocity servo drive, which has been developed and tested, is presented. SGSP477 and BYW8PI200 high efficiency fast recovery epitaxial diode (FRED) are used in the 1.2kVA power stage. A 6kVA motor drive design using ISOFETs is also presented.
TSD4M250 (ISOFET) and BYV54V200 FRED diodes are utilized in the 6kVA design in which FREDs are used as the MOSFET series blocking diode and the freewheel diode. Different power H-bridge configurations are chosen and justified for the 1.2 and 6kVA drives. Particular emphasis is placed on short-circuit protection techniques and simple gate drives.
INTRODUCTION
Brush D.C. permanent magnet motors are extensively used as velocity servo drives for high performance applications such as robotics and machine-tools. The high voltage D.C. (HVDC) supply of the flower stage for such motors rated up to 6kVA is generally limited to 200V D.C. because of sparking of the commutator and brush assembly.
The commutator has a maximum volts per segment rating at rated power above wh ich there is excessive brush wear. MOSFETs are well adapted for medium power applications at voltages up to 500V. Consequently the ease of paralleling, high peak current capability and the ease with which MOSFETs can be controlled and protected make them ideal power semiconductor switching devices for such motor drives. Medium power brush D.C. motor voltage limitation of 200V D. C. enables fast recovery epitaxial diodes (FRED) to be used which have high efficiency due to very low conduction losses and negligible switching losses:
BYW81 PI-200 : FRED: .
Vf < 0.85V (IF = 12A ; Tj = 100'C) trr < 35ns
Block diagram schemes for brush D.C. permanent magnet velocity servo drives are discussed. SeNo drive specifications shown in table 1 are considered and sol-
By C.K. PATNI
utions for the 1.2kVA and 6kVA motor drives are presented. The 1.2kVA motor drive is developed and tested. Protection, efficiency and switching frequency requirements have strongly influenced the designs.
Other than the power ratings, the parameters listed in the specification are common for many high performance servo drives. The main component in the design of the hardware is the power H-bridge switching ideally above the audio-frequency range. High frequency switching permits a compact power output filter to be used to filter the switching frequency if so desired.
SWITCH-MODE MOTOR DRIVE CONCEPTS
Figure 1 illustrates a conventional pulse width moldulated (PWM) D.C. motor seNO drive. The velocity demand and the tachogenerator feedback signals are compared and the resultant velocity error is amplified. This error is fed to the current seNO amplifier where it is compared with the actual current flowing in the motor armature. The amplified current error is fed into a linear PWM generator. The control of the mark to space ratio of the PWM generator is achieved by comparing the input error signal with a constant frequency triangular waveform. This results in a fixed frequency PWM signal which is fed to the power stage.
A switch-mode drive designed to the specification in table 1 com prises of :
11 Drive and protection for power devices 21 Power supplies 31 Regenerative energy clamp (4 quadrant control) 41 Cu rrent loop 51 Control and logic for PWM and velocity seNO.
The block diagram of the drive which has been developed is outlined in figure 2. (The complete circuit diagram is provided in figure 14). The differences between the two schemes outlined in figures 1 and 2 are that the current control loop and the PWM integrated circuit are eliminated in the second scheme. In the second scheme the velocity error is fed directly into a velocity compensation and modulation' circuit. The elimination of the current feedback loop limits this scheme in so much as it can not be used in torque control applications.
AN359/0689
1/10
797
APPLICATION NOTE
Table 1 : Typical Brush D.C. Servo Drive Specification. Specification
Modulation Frequency Continuous Power Maximum Continuous Current Bus Voltage Input Efficiency Short to Ground Short to Bus Voltage Armature Short Operating Temperature Velocity Demand Regenerative Energy Dissipation
Figure 1 : PWM D.C. Servo Drive.
'\.., A.C. MAINS
1.2kVA
I
6.0kVA
> 20kHz < 50kHz
1300VA 10A
I I
120Voc
6000VA 50A
> 90%
Shut down
Shut down
Shut down
o to 50"C
10V
10% of Continuous Rating
8. MAINS FILTER
REGENERATIVE
f - - - - 1 ENERGY
CLAMP
VELOCITY ERROR COMPENSA nON
BRIDGE
PVM
DECODE
V"-:_- ~-TACHO
CURRENT F~EDBACK VELOCITY FEEDBACK
Figure 2: Schematic Diagram of Brush D.C.P.M. Motor Drive.
"'v A.C. MAINS
1 1
I PO\lER SUPPLIES & HAINS rIL TER I
t
."" ~ Veto
VELOCITY
. L . ERROR
COMPENSA TlON
MODULATOR
..... -
ru
1
BRIDGE
VyIT
M~
REGENERA TIVE ENERGY CLAMP
'---
VELOCITY rEEDBACK _
2/10
798
APPLICATION NOTE
BRIDGE CONFIGURATIONS & MODULATION TECHNIQUES
The bridge design must be capable of supplying bidirectional current to the motor for optimal four quadrant control. This can be achieved by using a "T-bridge" or an "H-bridge", as shown in figure 3. The H-bridge is generally chosen since it requires a single power supply. The voltage rating of the power semiconductor devices matches the motor voltage rating for the H-bridge alternative.
The H-bridge has eight operating modes when connected to a D.C. motor load. These modes can be seen in figure 4. Two of the modes increase current supplied to the motor winding in either direction. The other six operating modes reduce current in the motor winding and are commonly known as freewheeling modes. Numerous switching modes are possible for PWM and current control. For example,
Figure 3 : Bridge Configurations.
.it is possible to PWM both the top and bottom devices in the bridge or simply either the top or bottom device. It is possible to use the PWM mark to space ratio such that the mark provides a positive rate of change of current in the motor winding and the space provides a negative rate of change of current. The control of the pulse width thus establishes a,n adjustable average voltage across the motor load.
A modulation technique used in the developed servo drive is illustrated in figure 5. This modulator is based on "delta modulation" (reference 1). The mark to space ratio of the modulator output (O(t)), determines the conduction period of the MOSFETs in the H-bridge. The modulator comprises of the standard delta modulator (part A), the proportional term (part B) and the integral term (part C) of the PID controller.
+v
D.C. MOTOR
... +---+-o-c=---mC\TIT~
D.C. MOTOR
-v'
Figure 4 : Operating Modes of the H-bridge Showing Current Flow Paths.
v
v
8 8
v
v
~ tl t~I
{M +
3/10
799
APPLICATION NOTE
Figure 5: A PID Controller with Binary Output.
r-~-------------~
I
~~~
I
e(_t)~-.----rl-i
H
om:
I HYSTERESIS
I I I
® I I
I I I I
1-----
-1
------1
I
I
I
L
_ _ _ _ _ _ _ _ _©..-IJ
SWITCHING DEVICES FOR A RANGE OF D.C. MOTOR SERVO DRIVES
At medium power levels the MOSFET is ideally
suited offering high switching speed, ease of paral-
leling and simple gate drive and protection. SGS-
Thomson has introduced a range of MOSFET
devices in plastic isolated packages. The 200V de-
vaicseers~osudmrivmearraisnegde
in table 2, can be used to design from 600VA to 6kVA without the
need to parallel MOSFETs in separate plastic pack-
ages.
The MOSFET internal parasitic diode is too slow for applications requiring ultrasonic switching frequen-
cies. Excessive switching losses in the MOSFET can result from the reverse recovery time of the internal parasitic diode (greater than 600ns). Noise is also induced on the supply rails when the conducting diodes reverse recover. Table 2 specifies high efficiency ultra fast recovery epitaxial diodes for freewheeling. These diodes, having a conduction voltage of less than O.85V at rated nominal current, are ideally suited as MOSFET series blocking diodes used to prevent the conduction of the internal parasitic diode.
Figure 6 illustrates possible techniques for utilizing fast external diodes for the 6kVA brush D.C. motor design.
4/10
800
APPLICATION NOTE
Figure 6: 6kVA MOSFET Switch Configurations Using ISOFETs and FREDs.
~-il ~I
I
--
I -1 ____
I BYV54V200
~= ~ I.r-t-I
I <FRED)
L
_
f
1
-.J
11 .J L:
~ :J
TSD4M250
Li p 1-.--1
~~ 1-
I ",v"veo"
TSD4M250
Manufacture: SGS - THOMSON MICROELECTRONICS
Basic Brush D. C. Motor Drive Spec. Switching Freq. > 20kHz
Part N°
ROS(ON)
10
RTH
Part N°
VF at
IF
MOSFET T) = 25°C Tc = 100°C
Diode FRED T) = 100°C
POWER Vnom
Inom
(Q)
(A)
(OC/W)
(V)
(A)
(VA)
(V)
(A)
SGSP367 '
0.45
10
1
BYW80PI200 0.85
7
600
120
5
SGSP477 '
0,17
20
0.83 BYW81PI200 0.85
12
1200
120
10
TSD4M2502 0.021
68
0.25 BYV54V200
0.85
50
6000
120
50
Table 2 A range of brush D. C. motor velocity servo drives.
1 - without insulation.
2· ISOFET : MOSFET chips in parallel in ISOTOP package.
1.2.KVA BRUSH D.C. SERVO DRIVE
Figure 7 illustrates the block diagram of the developed 1.2kVA brush D.C. selVa drive. The Hbridge operates at a nominal voltage of 120Voc. The D.C. motor in certain applications is driven by its load and hence is a generator of energy. This regenerative energy causes the HVDC rail voltage to increase as energy is stored in the smoothing capacitors.
At a maximum voltage of 160Voc, a resistive dump is turned-on to dissipate the regenerative energy and thus limit the HVDC to 160Voc. The drive utilizes the velocity PID controller illustrated previously in figure 5. A current sense resistor is incorporated in the H-bridge to provide load current feedback necessary to limit this load current to the maximum continuous current rating of the drive.
MOSFET based bridge-leg configurations have previously been discussed (reference 2). The bridgeleg utilized comprises of "low-side" and "high-side"
switches connected in series across the HVDC. In this asymetrical bridge-leg, (illustrated in figure 7), the rate of change of short-circuit current is limited by inductors (L1 and L2 : RM14 cores) which also limit freewheeling current from going through the parasitic diodes of the MOSFETs. At the 10A maximum continuous current rating of the drive, these inductors are still a managable size. This bridge-leg configuration is capable of withstanding simultaneous conduction of the two devices in the bridgeleg since there are series inductors which reduce the rate of change of drain current. This provides sufficient time for the short-circuit detection loop to operate. The power devices are thus turned-off without being stressed with high rates of change of pulse currents.
At a maximum continuous current rating of 10A, SGSP477 MOSFETs and BY81 PI200 fast freewheel diodes plastic packages are optimally rated for the 1.2kVA power stage.
5/10 801
APPLICATION NOTE
Figure 7 : 1.2 Brush D.C. Motor Velocity Servo Drive (120VDC ; lOA: nom.f.
H.V.D.C. MONITOR
)
RESIST3
BY\J81PI 150\1 200
ISOLATED
r - ~~~~ nRIVE
PROTECTION
lt SGSP477
+-
RMl4 CORE
TO 221)[ _ .JY\J8IP[ 200
DC MOTOR
ri~7GH-SIDE' FL---
~t ISOLATED
GATE DRIvE
SGSP477 IJITH
LI
PROTECTION
I CMOS GATE
1.-1
DRIVE \.lITH PROTECTION
f
-
-
-
-
'
'
'
~
1
CMOS GATE DRIVE \lITH
+-W· 1t SGSP477
PROTECTION f-----''''1
TACHO
n CURRENT
ti SENSE
aIL2
'---t-- SGSP477 CMOS GATE DRIVE \.lITH
HL_ _ _ PROTECTION
'LoV-SIDE' L-~~_
H.V.GND
TRANSISTOR :::::::
VELOCITY Ft:EDBACK
SIJITCHING
-
~ SIGNALS
TRANSISTOR
CURRENT
VELOCITY
S\JITCH!NG
r - - - - \
DECODE \.lITH
LIMIT CONTROL
CDMPEN$A nON I\. MODULATION'
~~~~~~_.J ~- CROSS-.rc._OU_P_LE_ _ _ _ _ _ _
t !.-
MODULATED OUTPUT
-- ,....... VnFHLAONCnlTY
GATE DRIVES AND PROTECTION
Similar gate drives and protection circuits, (illustrated in figure 8), have been used forthe "high-side" and "low-side" switches. This CMOS gate drive is well suited as switching speeds of 100 to 250 nanoseconds are sufficient in motor drive applications requiring a switching frequency of around 20 to 30kHz. Monitoring of the drain to source voltage while the device is conducting permits the detection of shortcircuit conditions which lead to device failure. The device is turned-off before the drain current reaches a value in excess of the peak pulse current capability of the MOSFET. When the MOSFET is turned-
on the on-state voltage of the device (VDS(on)) is compared with a fixed reference voltage of approximately 8V. At the turn-on instant, VDS(on) monitoring is inhibited for a period of approximately 400 nanoseconds in order to allow the MOSFET to turn-on fully. After this period, if VDS(on) is detected to be greater than the fixed reference voltage, the device is latched-off until the control signal is turned-off and turned-on again.
The "high-side" gate drives have isolated low voltage supplies and isolated command signals using high speed opto-couplers.
6/10 802
Figure 8 : An Isolated CMOS Gate Drive with Protection.
10K
22K 120 IK
+12v
lei (114)
APPLICATION NOTE
leI 4093 <1/4)
SGSP477
56K OV
BSSIOO
MOTOR DRIVE PERFORMANCE
Figure 9 illustrates the dynamic response of the motor drive to a step demand of 4000rpm. The response has been optimised for the no-load case (trace 1). Under heavy load inertia there is an over-
Figure 9 : Velocity Response of Motor Drive.
shoot in the velocity response (trace 2). The effects of changing the proportional gain and the integmtor time constant of the PID controller can be seell in figures 10 and 11 .
SPEED (RPM)
4000
DEMAND
1. tiD LOAD RESPONSE 2. LOADED RESPONSE
RESPONSE
4000
--
~2 LL I
Time scale: O.Ss/div
7/10
803
APPLICATION NOTE
Figure 10: The Effect Upon the Dynamic Response of the Analogue Velocity Servo System, When the Gain of the Proportional Term in the PID Controller is Varied.
!\
",,-/ -
Time scale: 0.05sldlv
4000 Deno.nd
ResponsE' 4000
Figure 11 : The Effect Upon the Dynamic Response of the Analogue Velocity Servo System, when the Time Constant of the Integrator in the PID Controller is Varied.
1\
~ V
Time scale: 0.05sldlv
Speed (R.P.M.l 4000 DeMo.nd
Response
6KVA BRUSH D.C. MOTOR SERVO DRIVE
Figu re 12 illustrates the block diagram of the proposed 6kVA (120Voc ; 50A) motor drive using ISOTOP packages for the MOSFETs in parallel (ISOFET) and the FRED diodes.
Blocking diodes in series with the MOSFETs are proposed to prevent the MOSFET internal parasitic diodes from conducting. The asymetrical bridge-leg configuration is not a cost-effective solution since inductors rated for 50A continuous operation are large and expensive. The series blocking diode has to be an ultra fast high voltage type. If the transistor F2 (shown in figure 12) is conducting, the drain to source capacitance of the transistor F1 is charged to the HVDC voltage. If F2 is turned-off, the load current transfers from F2 to the free-wheel diode, 01. Consequently the series blocking diode, 02, supports the drain to source capacitance voltage of F1 (equal to HVDC) provided this capacitance is not discharged by turning-on F1.
8110
804
An isolated D.C. current measurement device, (such as an Hall-effect current sensor, LT80-P, manufactured by LEM), is recommended for the measurement of load current necessary for current limit control.
Pulse transformer based floating gate drives illustrated in figure 13 can be used for the TS04M250 ISOFETs. The pulse transformer is used to transmit simultaneously the ISOFET logic command signal together with the gate to sou rce capacitance charging current. The current mirrortechnique (reference 2) is used to provide short-circuit and over-load current protection. The pulse transformer operates at an oscillating frequency of 1MHz when a turn-on control signal is present.. The secondary is rectified to provide gate source capacitance voltage. The current mirror provides a voltage "image" of the main drain current. This voltage is compared with a fixed reference voltage in order that the gate drive be latched-off whenever the drain current exceeds the specified overload current level.
APPLICATION NOTE Figure 12 : 6kVA Brush D.C. Motor Velocity Servo Drive (120Voc ; 50A : nom.) .
I H.v.D.C. HDNlTOR
.~L
RESIST]
BYIJ81Pl 200
500\01
ISOLATED GATE DRIVE IJITH PROTECTlON
D2 BYV54V200 ISOTOP
Dl X
aL "'L...r Fl TSD4H2S0 ISOTOP
- ISOLATED
GATE DRIVE \JrrH PROTECTION
D4
CMOS GATE
I.J
1-----''1[ DRIVE \JITH
PROTECTION
I::J SGSP477
rSOLATED
GATE VITH
DRIVE~lt Jt:.
r ~
PROTECTION
mr-
TSD4M250
ISOTOP '1
"
at
D3
"t....J
F2
TSD4."1250 ISOTOP
ISOLATED GATE DRIVE \.lITH PROTECTION
----~---+--+------H-V-G-N~D-~IS~D-L.~T~E-D-----t-~~----
TRANSISTOR:::::::::
CURRENT SENSE
VELOCITY FEEDBACK
S\lITCHING
--
SIGNAL'~\\ TSRVAITNCSHISINTOGR,I
I I CURRENT
I \
DECODE \JITH 1 - - - - - - - 1 L!MIT
CROSS-.CDUPLEj
CONTROL
I~D~~~~g~rcNI, ___V_E_L_D_CIOTY
8. MODULAT!ONr
J
~EH""ND
" -_ _ _ _ _ _ _ _--'M=ODULAED OuTPUT
Figure 13: Pulse Transformer Gate Drive with Current Mirror Protection for a TDS4M250.
9/10
805
APPLICATION NOTE
CONCLUSION
MOSFET based brush D.C. motor velocity servo drives have been described, with particular emphasis placed on the bridge-leg configuration, the PID compensation and modulation, the gate drive and protection techniques. The PID compensation and modulation circuits require few components to achieve good velocity servo performance.
Figure 14 : 1.2kVA Switched-mode MotorDrive.
"-
~3
'" ~M
0. ro
O M
M m
~ t~
~
l~~
~~
The development has led to a compact high performance 1.2kVA drive which is fully protected against output short-circuit conditions. A 6kVA motor drive is proposed using ISOFETs. MOSFET switching devices and their associated free-wheel and blocking diodes have been specified for a range of brush D.C. motor drives rated between 600VA to 6kVA without the need to parallel MOSFETs in separate plastic packages.
10/10 806
APPLICATION NOTE
SWITCHING WITH MOSFETs AND IGBTs: 50Hz TO 200kHz
by K.G. Rischmiiller
ABSTRACT
The basics of IGBT and Power MOSFET characteristics are discussed and their switching behaviour analysed. Circuits for loss evaluation of MOSFETs and IGBTs are described and evaluation methods for output charge and energy are shown. It is demonstrated that on-resistance and output capacitance are related and how loss minimization can be achieved in different PWM and resonant topologies. Gate drive methods enabling reduced switching loss, better overload behaviour and less driver energy consumption are also shown.
INTRODUCTION
The excellent switching behaviour of Power MOSFETs is an incentive to power supply designers to increase switching frequencies and thus reduce the cost and size of the magnetics. Nevertheless, low frequency switching with controlled current and voltage rise times can also lead to new concepts and cost reduction. When optimising low and high frequency power control circuits, the neglected parasitic effects of Power MOSFETs and their bipolar counterparts, IGBTs, become important and have to be taken into account for circuit - design.
AN463/0492
1/18 807
APPLICATION NOTE
A: UNDERSTANDING POWER MOSFET AND IGBT BEHAVIOUR
Over the last few years, Power MOSFET high voltage capability and on-resistance have been very much improved. The on-resistance per die area is a means by which these improvements can be measured (fig.A 1). On resistance per die area is close to the physical limits for Power MOSFETs having a 600 - 1000V breakdown voltage, thus major improvements in the on-resistance of these devices can be obtained only by increasing the die area. Bipolar operation is the only way to decrease on-resistance per unit area to below the physical limit dictated by the resistance of the n-body of the MOSFET. The Insulated Gate Bipolar Transistor (IGBT), the Bipolar Modulated FET (BM-FET) and the Field Controlled Thyristor (FCTh) have bipolar modes of operation.
THE DIFFERENCE BETWEEN POWER MOSFETS AND IGBTS
The IGBT can be understood as a Power MOSFET driving a PNP-transistor (fig.A2). During conduction, the p-Iayer injects minority carriers into the resistive n-Iayer, thus significantly reducing the on-resistance of the device (fig.A2). The higher the breakdown voltage of the device, the higher the difference in onresistance between a unipolar Power MOSFET and a bipolar IGBT. Fig.A3 shows the output characteristics of 1000V devices having similar die-size. The reduced on-resistance of IGBTs does not come for free: IGBTs exhibit more turn-off losses than Power MOSFETs (fig.A4) and their protection against overload is more difficult.
log RON. mm2
9
30 mm2
300 mn - 600 V
0.6
30 mm2 20 mel - 60 V
60 V
600 V
log Uw
Fig. A1: MOSFETs on-resistance per silicon area versus breakdown voltage. With high voltage devices it is close to bulk-resistance. Low voltage devices have much potential for improvement.
2/18
-------------------------L~I ~~~;~~~:~~-------------------------
808
APPLICATION NOTE
fLp
n-
n+ P
r ~G L-jIHOS $c±> IeIP
Ie
e
~ ~I'"
I
G
\,.
o--J "-.I ~--( I
E
Fig. A2: Cross section and simplified equivalent circuit of an Insulated Gate Bipolar Transistor (IGBT). This device combines Iowan-resistance with simple drive requirements.
MOSFET
IGBT
. . . . . . . . . . . . . . . . . . . . . . . 30
3.5 AYos
3.0 V
I
A -/11----
I
J
3.0 V
Fig.A3: Output characteristics of a 1000V-MOSFET and an IGBT having similar die-size.
c OPEN BASE
D,3A
E
I-- 0.6 Jl S
~I
Fig. A4: IGBTs exhibit a turn-off collector current tail and significant turn-off losses in PWM circuits.
-------------------------- ~~~~~~~:~~ ------------------------3/-1-8
809
APPLICATION NOTE
HOW TO CONTROL TURN-ON SWITCHING
Turn-on switching when the freewheeling diode is conducting leads to losses in a Power MOSFET and to similar losses in an IGBT (fig.A5). Increasing the di/dt of the drain current, or for an IGBT the collector current, leads to reduced turn-on losses. Reducing di/dt leads to higher losses, but makes the reverse recovery behaviour of the freewheeling diode "softer", thus reducing RFI problems. When switching a short circuit, drain-source or collector-emitter voltage is at a constant high level while the drain or collector current increases at a certain di/dt (fig.AS). It stabilises at a certain current value, Isc . The amplitude and duration of this current should be minimised in order to minimise energy stress on the semiconductor device. The output characteristics of the Power MOSFET IRFP450 helps us to understand how we can control di/dt and Isc (fig.A?). The time needed to move the gate - source voltage from approximately 2V to about SV determines the rate of rise (di/dt) of drain-current. The amplitude of.a short circuit current, Isc ' is controlled through applied gate-source
voltage. An IGBT behaves similary (fig.A?b). The dildt and Isc control can be implemented with a driver stage which monitors drainsource or collector-emitter voltage (fig.AS). The rate of rise of gate-voltage is controlled through R1. The Zener diode, D2, clamps the gate voltage to, for example, 6V and thus limits
Isc· Under normal operating conditions, the drainsource or collector-emitter voltage decreases after the reverse recovery of the freewheeling diode, T1 blocks and the gate voltage can increase to about 10V. Such a circuit greatly limits energy stress under short circuit conditions.
TURN-OFF SWITCHING
The switching device should not be damaged during turn-off switching. A power transistor datasheet usually contains the test circuit used for establishing the safe operating area (SOA) of the device (fig.A9). During operation the load line should not cross the limits of the SOA, but it is important to remember that the SOA itself is valid for given drive, junction temperature and dV/dt conditions.
Vs
R
DF
I,V
~ L IL
T
i -1
VDS
to
Fig, AS: Turn-on switching with a conducting freewheeling diode.
4/18
----------------~-------~~~~~~~:~--~---------------------
810
APPLICATION NOTE
Vs
DF
V"
I,V
T +ID
1 -l
VDS
t
Fig. A6: Switching-on to a short circuit.
Vr, :\OV
a
I/S(
6V
r
6
T ,15'( 1
6
SV
,
4.5V ~'- I.-
VG!; 4V
50 too t50 100
,)
lolAI
VGS ,15V
50
TCilS I!=2S 0 (
/ v 131
V
40
IV
l1V
30
111/ V/
v
10V
20
1M /
~
9V
IJj
7V
10
... ~
5V
~
5 VoslVI
POWER MOSFET IRFP450
IGBT STGH20N50
Fig. A7: Output characteristics of a POWER MOSFET and an IGBT
V,I
-- ,- ...
I
v
t
t
Fig. AS: Principle 01 driver stage controlling dildt and short circuit current amplitude,
-------------- LV ~~~;m~r;,:~~©~ --------------5/18
811
APPLICATION NOTE
Reverse biased SOA
·lolAI.
·10' ,
·10'
· · · , · · · 1
V _15V T:.l000 ( R,.100n.
L.1BO~H
II
G( 1Q64
.
(a)
(b)
Fig. A9: Test circuit for the safe operating area (a) and SOA of IGBT STGH20N50 (b).
The rate of rise of collector-emitter-voltage (dv/dt), junction operating temperature, Tj, and drive conditions strongly affect the turn-off behaviour of IGBTs. In particular, the latching current is modified by these parameters. The simplified equivalent circuit of an IGBT (fig.A10) can be used to understand modifications of latching current: transistor T1 conducts when the Power MOSFET structure is on; T2 will conduct when the voltage drop across Rs exceeds about 0.6V; the IGBT "latches" if this happens. Once the device latches removing the gate-emitter voltage will not turn off the device and the device may be destroyed. The value of Rs doubles between 25°C and 125°C. The base-emitter threshold voltage of T2 diminishes at about 2mV/oK - both contributing to a reduction of latching current from 100% at 25°C to 30% at 125°C. At turnoff switching, a dv/dt between collector and emitter will add a capacitive current flowing into Rs, thus reducing latching current further and making it dependent upon dv/dt (fig.A11).
The resistance Rg between gate and emitter, strongly affects turn-off behaviour of Power MOSFETs and IGBTs. When the collectoremitter (drain-source) voltage increases, capacitive current flows into the drive circuit and leads to a voltage drop across Rg, thus maintaining Vge(Vg5) at a dv/dt dependent level. The resistor Rg can be used to control dv/dt during turn-off. Thus turn-off losses, RFI and latching current can be set to desired values. The higher the Rg value, the lower the turn-off dvldt and the higher the latching current.
B - DRIVER CIRCUITS FOR POWER
MOSFETs AND IGBTs
Driver circuits have an influence on cost, performance and reliability of the whole power switching function. Driver circuits should transform the logic level control signal into a suitable voltage/current waveform, exhibit low power consumption and often offer galvanic isolation between input and output.
- - 6/18 - - - - - - - - - - - ~ ~~~;m~r::oo?l: - - - - - - - - - - - -
812
APPLICATION NOTE
c
cpJ dV/dt
~c
E
Fig. A10: Equivalent circuit of an IGBT for understanding the latching behaviour.
I,V
Ie
t Fig. A11: Turn-off dV/dt as a function of gate resistance.
AVOIDING SPURIOUS TURN-ON
In bridge legs, Power MOSFETs and IGBTs are subject to dv/dt, when the opposite transistor switches on (fig.B1). This dv/dt will charge the parasitic drain-source or collectorgate capacitance and lead to a current flow out of the gate. If the voltage drop across Lp, Rp and Rg exceeds about 1V to 2V, the Power MOSFET/IGBT will conduct, leading to extra switching losses. A driver stage having three different states
gives a good compromise (fig.B2): dv/dt during turn-off switching can be set by means of Rg, thus obtaining excellent safety agajnst latching and low RFI. After turn-off switching, a low driver output impedance gives good immunity against spurious conduction. Nevertheless the parasitic resistance, Rp and inductance, Lp, should not exceed certain limits depending on dv/dt, die-size and parasitic package inductances.
!V ~~~~n!~~:0l~l: - - - - - - - - - - - - -7/18 813
APPLICATION NOTE
Vs
T1
-M ---1~
L
Rp
1VB
)
1
Fig. B1: Bridge leg with inductive load, where transistor T2 is subject to "passive" dV/dt.
Fig. B2: Tri-state driver limiting turn-off dv/dt and having high immunity againstpassivedv/dt.
-VB
E
Fig. B3: IGBT with parasitic capacitances and inductances.
PACKAGE
MAXIMUM DRIVER IMPEDANCE
TO 220 TO 218 ISOlOP TO 240 MODULE
100/300 nH ao/160nH 20/60nH NEGATIVE BIAS NEGATIVE BIAS
dV/dt-10kV/ ).IS
TABLE I: Maximum driver impedance as a function of device package.
MAXIMUM DRIVER IMPEDANCEI NEGATIVE BIAS?
During dv/dt, the gate voltage should not exceed about 1 volt. The maximum driver impedance must be fixed at a value that is dependent on the die size, which is related to
eCG and the parasitic package inductance
LP(int) (fig.B3). If LP(int) is very high, negative bias may be required in order to avoid spurious conduction. Table I indicates the
maximum required driver impedance for a dv/dt of 10kV/j..ls.
PULSE CONTROLLED DRIVER SUITABLE FOR 0 - 1 MHz OPERATION
When applying a voltage pulse with, for example, a 1OVamplitude and 500nsduration, to the gate of a Power MOSFET (T) or an IGBT,
-------------------------- 8/18
--------------------------~~~~~~~::n
814
APPLICATION NOTE
01
ONJL
~ OFF fL C2
J
~l
Fig. 84: Pulse controlled driver circuit memorizing on-state and off-state.
Fig. 85: Pulse controlled drive with transformer isolation. Even though there is no auxiliary supply, any pulse width, at virtually any relevant frequency, can be controlled.
SOOns!DIV
:ig. 86: Transformer output signal at gate-emitter! gate-source voltage with pulse controlled driver.
:harge will be stored in the gate capacitance fig.B4). Thus the power device will remain :onducting, even after removal of the input )ulse. This is called the "memory-effect". f a similar pulse is applied to a second Power ~OSFET (T2), the latter will conduct, lischarge the gate of Power MOSFET (T) and emain conducting - the off-state is
memorised. Supposing R is low enough, dv/dt applied to Power MOSFET (T) does not lead to spurious conduction. It is possible to add a pulse transformer for galvanic isolation and a third Power MOSFET (or bipolar transistor) can be used to discharge the gate of T2, whenever an "on-signal" is generated (fig.BS). When using the "memory-effect", only pulses of about S!lVS have to be transmitted by the transformer; a very small toroid transformer is sufficient. Figure B6 shows the transformer output voltage and resulting gate-source/gateemitter voltage. The circuit can handle any duty cycle.
RESONANT DRIVER FOR POWER MOSFETs AND IGBTs
Power MOSFET and IGBT driver circuits for high frequency conversion should drive the power devices in such away that the resulting switching losses are low. Even at high
-------------l.V ~~~~m~~:O!~~ - - - - - - - - - - - - -9/18
815
APPLICATION NOTE
operating frequency, the driver circuit should have negligible power consumption. Power MOSFETs and IGBTs are charge controlled devices. For turn-on one has to supply a certain amount of charge into the gate. For turn-off, charge has to be removed. During switching, one can consider the drain source path of a Power MOSFET as a fast varying current source - moving in a drive determined time from conduction to zero current or vice versa. Driving the gate with a rectangular shape current (constant amplitude during a certain amount of time) would enable faster charge removal and faster switching but it is difficult to realise. Resonant gate drive with an inductance between driver and gate is easy to realise - one can even use an increased parasitic wiring inductance. With this approach, the time to charge or discharge the gate can be reduced by a factor of about two. Depending on the circuit, gate charge can be recovered and gate drive power consumption reduced. One of the possible resonant gate driver
circuits can be supplied from a single 5V source, and it generates a ten volt gate voltage for conduction and a negative bias for the offstate. Conventional gate driver circuits charge and discharge a Power MOSFET's input capacitance through resistors and a parasitic inductance Lp (fig.B?).
Fig. B7: Principle of conventional driver circuit with simplified equivalent circuit of MOSFET
D1 51
+5~
T
D2 52
z
Fig. B8: Resonant gate driver. Power consumtion of the driver is 1/4 of a conventional driver.
--10/18 ----------- ~ ~~~~m~r::O!~l: -------------
816
APPLICATION NOTE
At turn-on switching E = 1/2 CV2 is lost in Ron 1.
At turn-off switching, same amount of energy is lost in Ron2. When driving power Power M08FETs at high frequency these losses become significant and should be reduced. Resonance effects can be used for this purpose (fig.BB). When driver transistor 81 is turned on; a sinusoidal current flows into the gate capacitance of the power device. The gate voltage reaches about twice the driver supply voltage Vaux . Thus, a Power M08FET requiring a gate-source voltage of 1OV can be driven from a 5V-supply. The diode D1 avoids discharging the gate~ For turn-off switching, 82 is closed, a sinusoidal current removes the charge from the gate. The gate-source, or gate-emitter in the case of an IGBT, voltage of the power device is inverted (negative). Most of the stored energy is used to generate a negative bias voltage (fig.B9). Diode D2 avoids discharging the negative gate charge. Due to resonance overvoltage, gate voltage would reach the breakdown voltage of the gate oxide after a number of switching cycles.
A Zener diode, Z, has to be used to limit gate voltage. The energy consumption of a resonant gate driver is about a quarter of that of a conventional driver. The charging and discharging of a capacitor with a given peak current, is achieved more rapidly through an inductance of an appropriate value. Resonance driver circuits therefore have the ability for the fast switching of power devices (fig.B10).
C - LOSS REDUCTION IN PWM CONVERTERS
PARASITIC CAPACITANCES CONTRIBUTE TO LOSSES
The influence of the Power M08FET output capacitance is negligible in low voltage, low frequency applications. This changes greatly when increasing operating voltage and switching frequency. The effect of the output capacitance, Cout ' has to be taken into account in high voltage, high frequency applications. For switching loss evaluation, it is possible to
0,5 AI OIV
500 Ns/oIV a) POWER - MOSFET IRFP450
(3,3nF parallel to G-E) b) IGBT STGH20N50
Fig. 89: Gate-current and gate-source/gate-emitter voltage waveforms.
--------------------------~~~~~~~::~~
11/18
--------------------------
817
APPLICATION NOTE
. .I
........iH.H.1
... , VGS: 10V/0
..... , ..... J ········· ....·... 1
l:rf. ...;.'_::.-+--:--:-......;,._~=7 ! ...'..;j....,....._,.. ;..:,-r-';'--'---+--'---'- 'G: lA/Diy "..iJ-.._..
10: 20A/Div
250 ns/Div
this energy may either be recovered or dissipated . In PWM circuits (fig.C3) the Power MOSFET discharges its output capacitance at turn-on switching and (0.5 · Cout * VOS(01l)2) Joules are lost. (C out is the effective output capacitance of the Power MOSFET, V OS(oll) the drain source voltage just before turn-on switching). The discharge-current flows inside the Power MOSFET, it cannot be observed on an oscilloscope.
Fig.810: An ISOFET TSD5MG40V (1 OOOV, 0.7Q) driven by a resonant driver. Switching losses are greatly reduced.
use a simplified equivalent circuit of Power MOSFETs (fig.C1). The function of the output capacitance can be understood as a built-in capacitive snubber. At turn-off switching, this capacitance is charged from Von to the maximum voltage VOS(Off) applied to the Power MOSFET (fig.C2). Once charged, the capacitor contains energy. Depending on the converter structure,
HOW TO MEASURE STORED CHARGE?
A simple circuit can be used for evaluation and specification of the output capacitance (fig.C4): The device under test (OUT) is connected to a high voltage supply via a resistor. A second Power MOSFET is paralleled to the OUT. The Power MOSFET under test is permanantly blocked, the second Power MOSFET switches periodically. At turnon of the latter, you can observe the discharge current and time on an oscilloscope and determine the amount of charge, energy and the value of the capacitance.
SOURCE
SOURCE It BODY
p' DRAIN
DRAIN
Fig. C1: Power MOSFET cross section· a) parasitic capacitors b) equivalent circuit.
-- 12118 ----------- LV ~~~~m=:U!~:: -------------
818
APPLICATION NOTE
....
····
J':1
o.
650V
k · I ·
~
I·'
III
·
.... r.. . . .... ~
,. ~
..... ... ..0;; ;.;;:::: 1600A/ys
I:
--!>-
SONS
G -l
s
COUT
Fig. C2: Turn-off switching of a 1000V-O.7Q Power Fig. C3: Discharging output capacitance during
MOSFET.
turn-on switching.
400V
VDS
f SOV/DIV
10 fO,IA/DIV
SONS/DIY Fig. C4: Evaluation of Power MOSFET output capacitance,
a) test circuit, b) waveforms with IRF450, VDS(ofl) = 400V.
ON-RESISTANCE - CAPACITIVE LOSSES
A Power MOSFET's contribution to converter losses are conduction, switching and gate drive losses. Conduction losses can be reduced by increasing the die size, leading to smaller on-resistance. Increased die size introduces increased output capacitance and switching losses (fig.C5).
Minimum losses are obtained when losses due to discharge of the output capacitance and conduction losses are equal (fig.C6). Optimisation depends on the supply voltage, the converter structure and the switching frequency. The consequences are: from a certain
------------- LV ~~~~m~::9~ -------------13/18
819
APPLICATION NOTE
~~!~c
:
T Ron 1 ~ Cout 1
Ptoto\ = P capacitor + P conduction
'" DRAIN
~
area. 2
Cout = Cout 1 + C out 2 ···
4 5 Silicon oreo
Fig. C5: Power MOSFET cross section. Increase of silicon area or paralleling discrete devices reduces on-resistance but increases output capacitance.
Fig_ C6: Conduction and switching losses versus area. Total loss has a frequency dependent minimum.
11 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .
!
(Jl
III o(Jl
...J
f(kHz)
Fig. C7:Total losses versus frequency calculated asymmetrically with three 500V Power MOSFETs (same technology, different on-resistance).
switching frequency upwards, a size reduction of the Power MOSFET leads to improved efficiency, even when it is associated with an increased on-resistance. In SMPS applications with PWM and with a maximum drain-source voltage of 400V, switching losses due to the discharge of the output capacitance are dominant at switching frequencies exceeding 100kHz to 150kHz
(fig.Cl). For loss reduction in SMPS operating below 100kHz Power MOSFETs with low onresistance are preferable - above 100kHz Power MOSFETs with low output capacitance and higher on-resistance are better.
INFLUENCE OF TOPOLOGY
Comparing energy stored in the two Power MOSFETs of an asymmetrical half bridge
-14-/-18------------------------ 'fi ~~~~~~~:oo~J: --------------------------
820
APPLICATION NOTE
160 pF
26 pJ
max 800 V 370 pF
120 J-IJ
Fig. C8: Energy stored in the output capacitance of two OAQ 1000V Power MOSFETs and in one 0.8 Q - 1000V MOSFET.
t
t
Fig. 01: Typical waveforms with zero voltage switching (a) and zero current switching (b).
flyback converter with a single switch flyback shows that significantly more energy is stored in the high voltage device used in the single switch flyback (fig.C8). It is possible to estimate that between 30% to 60% of that energy is dissipated.
D - POWER MOSFETs AND IGBTs IN RESONANT CONVERTERS
A large number of different resonant and quasi-resonant topologies exist. For the purpose of choosing semiconductors, one can
distinguish two basic modes of operation: Zero voltage switching and zero current switching (fig.D1). The other modes are in between. IGBTs are as simple to drive as Power MOSFETs and offer, in the area of high .voltage switching, much better on-resistance per unit silicon area and may offer less conduction losses or lower costs. Depending on the converter topology, either Power MOSFETs or IGBTs may be more suitable.
-------------------------~~~~~~~~:9~----------------------1-5-/1-8
821
APPLICATION NOTE
ZERO VOLTAGE SWITCHING
A typical circuit with zero voltage switching consists in a switch, T, with paralleled capacitor and series choke (fig.D2). The whole is supplied from a voltage source. During conduction in the switch, the choke current increases with time. At turn-off, the voltage across C and the switch increases as a sinuoidal function and may reach s.everal times the supply voltage (fig.D3). Afterwards it swings back to below zero where it is clamped by the diode. The output capacitance of the semiconductor switch and the capaCitor are discharged via the inductance. Thus the energy is recovered. The only losses are due to the parasitic resistance Rs, which is a part of the Power MOSFET's on-resistance. Increasing silicon area reduces on-resistance, Ron, and parasiti~ damping resistance, Rs. An increase of silicon area is not paid for with an increase of capacitive loss. Power
MOSFET switching losses can be considered as negligible with this operation mode. High voltage IGBTs exhibit significantly lower conduction losses than high voltage Power MOSFETs with similar die size. The IGBT can be understood as a Power MOSFET driving a PNP-bipolar transistor (fig.D3). The onresistance of the Power MOSFET is virtually divided by the bipolar gain. It is possible to compare the switching to that of a high voltage PNP-transistor, switching with open base resulting in a collector current tail. This tail cannot be ignored as the resulting loss is a major limitation for the application of IGBTs in converters with zero voltage switching.
ZERO CURRENT SWITCHING
A typical circuit using zero current switching consists of a switch with a series choke, the whole paralleled with a capacitor and supplied
SA
---j
~I
(au t
o.
I-- 0.8 jl S
,I
Fig. 02: Typical circuit with zero voltage switching.
Fig. 03: Equivalent circuit of an IGBT and waveforms in a ZVS-circuit. Even a small tail current leads to significant turn-off energy loss.
- - - - - - - - - - - - - 16/18
---------~--- L"fl ~~~~~~¥r::oo~~
822
APPLICATION NOTE
(out
T
Fig. 04: Typical circuit with zero current switching.
c
90A I---'-- ,.....
II t\
\
I
1\
o I . . ... \
, " .. "., .... ... Ie
200V
....
/(
o ""'-- ...Jr....
I
Fig. 05: Collector current and collector emitter voltage of a 10 Amp-500Volt IGBT (STGP10N50) with zero current switching.
I
E +
Fig. 06: Equivalent circuit explaining the absence of a current tail. When the collector-emitter voltage of the IGBT is negative, a current flows thourgh the body diode into the base of the PNP. This current blocks the PNP structure efficiently.
from a current source (fig.04). At turn-on, the current through the switch increases with a sinuoidal function and then swings below zero (fig.01). The negative half wave flows through the diode.
At turn-on switching, output capacitance is discharged into the switch; capacitive losses similar to PWM-converters can be observed. IGBTs do not show current tail in this configuration! After the zero crossing of the collector current a short negative current pulse can be observed (fig.OS). It flows through the body diode into the base of the PNP, sweeping stored carriers away, thus avoiding current tail and corresponding losses (fig.06). IGBTs are very suitable for resonance converters with zero current switching where they offer a better cost/performance compromise than Power MOSFETs and can be operated at frequencies of several hundred kHz.
RESONANCE IN PWM CIRCUITS
The advantages of zero current switching with IGBTs can also be used in PWM converters: (this is similar to forced switching circuits as used with SCRs - improved MORGAN circuit (fig.D7).
- - - - - - - - - - - - ru 17/18 SCiS·THOIVISON - - - - - - - - - - - ·J U !kIlOI!:~@~~~I!:1Ta:J@1Il0I!:$ 823
APPLICATION NOTE
L
Taux
~
Fig. D7:Circuit using resonance in a PWM converter. With this circuit the IGBT is virtually free from turn-off losses and can be used at inaudible frequencies.
With these circuits it is possible to take advantage of the high current handling capability of IGBTs without any risk of loosing control as is the case with these earlier thyristor circuits. Thus PWM operation of IGBTs at inaudible switching frequencies is possible.
CONCLUSION Investing more effort into understanding and designing driver cirCUitry for Power MOSFETs and IGBTs opens the way to better performance, lower costs and new applications. Through suitable gate control, Power MOSFETs can be made even faster. However, it is also possible to slow them down in order to reduce RFl-filter requirements in
phase control, soft start circuits etc... Through zero current mode operation, the current tail of IGBTs can be avoided, and then IGBTs can be operated in PWM circuits at up to 20kHz and resonant converters even at 200kHz. Maybe some of the well proven thyristor circuit topologies could be used and even improved with IGBTs. The key to all these new applications with improved performance is in forgetting prejudice and thinking about what really happens inside the power semiconductor devices.
REFERENCES
1) A. Galluzzo, M. Melito, M.Paparo: How design rules influence high frequency switching behaviour of POWERMOSFETs, Proceedings of PEG'90, Long Beach
2) J.M.Bourgeois, B.Maurice: Losses of Insulated Gate Bipolar Transistor in H.F. resonant converters, Proceedings of lAS conference, IEEE, Oct. 89
3) B. Maurice: Environmental design rules of MOSFETs in medium power applications, Proceedings of PGIM '89, Munich.
4) H. Foch, P. Marty, J. Raux: Use duality rules in the conception of transistorised converters. Proceedings of International Power Conversion '80, Munich.
5) N.O. Sakal, R. Redl: Computer-aided design and optimization of regulated zerovoltage-switching single ended resonant DC/DC conveter, including voltage-control function, Tutorial Seminar, PEC '90
- - - - - - - - - - - - - ~ 18/- 18 ----------- t::;j ~~~~n':=:oo~l:
824
APPLICATION NOTE
INSULATED GATE BIPOLAR TRANSISTORS IN HIGH FREQUENCY RESONANT CONVERTERS
by J.M. Burgeois, B. Maurice
ABSTRACT
IGBT technology produces devices that are easy to drive, are capable of switching at high voltages and currents and operate at high current density. A common application for this class of device is in off-line motor drives that use them in a "hard" switching mode. Designs are now begining to be made that use the IGBT in resonant converters with "soft" switching and that operate at higher frequencies.
This paper discusses the operating limits of IGBTs in resonant circuits. In particular, this analysis considers the thermal balance and the maximum current density that can be achieved by IGBTs in this type of application. The major resonant sub-circuits are highlighted and the duality rules that permit the use of these circuits in place of other configurations, discussed. Finally, a practical circuit is given for driving and protection of IGBTs.
AN464/0492
1/12
825
APPLICATION NOTE
1. INTRODUCTION .
Resonant converters will operate at much higher frequencies than conventional designs of converters. For this reason they are attractive because using a higher operating frequency means that the size of passive components in the circuit will be smaller. The higher frequency is possible because the converter switching losses are lower. The extent of this improvement is dependent on the converter structure and mode of operation. Until recently resonant converters used SCRs, bipolar transistors or Power MOSFETs as switching elements. The purpose of this paper is to consider the use of IGBTs in resonant converters. IGBTs combine some of the advantages of bipolar transistors and Power MOSFETs. For example easy voltage drive, fast and efficient protection and low on-state dynamic resistance. The paper also analyses IGBT losses and the dependence of their maximum operating frequency on the converter structure and mode of operation. A practical example is discussed that uses a fast IGBT, the STGP1 ON50, which is rated at 10 Amps/500 volts.
2. RESONANT STRUCTURE
The resonant switch is the basic element of any resonant converter. It is a single tuned sub-circuit that includes a switching component, a diode, an inductor and a capacitor. Depending on the position of the diode, this resonant switch is uni- or bidirectional, thus providing half or full wave operation. The major feature of this type of sub-circuit is its ability to switch at zero current ,(or zero voltage). This reduces the switching losses as compared to "hard" switching circuits. This means that current and voltage do not occur simultaneously across the switch.
As a result the switch will only experience either a voltage or a current. There are two main resonant converter configurations:
a) A quasi resonant converter which uses one resonant switch excited in discontinuous operating mode by pulse frequency modulation. Because the current (or voltage) wave is whole (the waveform is unbroken) the switching behaviour of the resonant switch is maintained. Evaluation of the losses in the IGBT in these converters is made using the two basic operating modes: zero current mode (ZCM) and zero voltage mode (ZVM).
b) A resonant converter uses a minimum of two resonant switches in a symmetrical structure. It allows continuous operating mode operation which changes the switching conditions of the resonant switch: it is not a whole wave mode and zero current (or zero voltage) switching occurs, depending on the switching frequency, only at turn on or at turn off. So, a large fraction of the IGBT's losses can be' deducted from the quasi resonant analysis.
Section 3 gives an accurate analysis of IGBT losses in quasi resonant converters. The overview of switching conditions in resonant converters provides the basis for loss evaluation using the analysis of the previous section.
3. IGBTs IN QUASI RESONANT CONVERTERS
As already stated previously, in quasi resonant converters the IGBT operates as a single tuned resonant switch with a quasi sinusoidal current (or voltage) waveform. This analysis examines each mode.
2/12
--------~---------------- ~~~~~~~~:9~ 826
A~PLlCATION NOTE
3.1 IGBTs IN ZERO CURRENT SWITCHING QUASIRESONANTCONVERTER&
a. Switching: The IGBT's switching behaviour is analysed using the circuit shown in figure 1 - full wave mode zero current switching (ZCS) quasi resonant converter. Because the collector current is zero during switching (see fig 2 & 3), the only switching losses occuring are due to the internal discharge of the IGBT output capacitance at turn-on. The discharge current is not detectable externally, but the charging current appears in figure 3 when voltage is re-applied to the collector. Integration of the current waveform shows that the energy stored in the output capacitance of this IGBT is about 10llJ at 400V.
b. Conduction: Figure 4 shows that the current factor is low due to the discontinuous operating mode of the quasi resonant converter. For this reason it is important to be able to use the switch at high current
density and this is the major characteristic of an IGBT. Figure 5 shows the IGBT saturation at high current and its dependence on gate source voltage. The current saturation threshold is virtually independent of temperature (less than 10% between B5°C and 95°C) and conduction time (unchanged between 1Ilsec and 5Ilsec). An IGBT with a nominal current of 10A can conduct more than BOA without saturation. However, with a ZCS quasi resonant converter, the maximum operating current is limited by conduction losses as follows: Considering the maximum switching frequency (duty cycle < 50%) and the transfer characteristics given in figure 6, the conduction losses are:
Pcond < (1.4 Ipk/rc) + (0.11B Ipk2/4) watts
for a 30A peak Pcond < 40W - a maximum realistic value for a TO-220 package.
Fig.1: FUll-wave mode ZCS quasi resonant converter IG8T STGP10N50 10N500V.
Fig.2:Turn on switching circuit defined in figure 1
Vos = 100V/div
Rc = 50 Ohms
10 = 20A/div
t = 100nsec/div
--------------------------i,1 ~~~~~~~~~ ________________________3/_1_2
827
APPLICATION NOTE
Fig.3:Turn on switching circuit defined in figure 1
Vos = 100V/div
VGS = 5V/div
Tease = 50°C
RG = 10 Ohms
10 = 20A/div
t = 100nsec/div
.- · · ~
· - r,d,.I: till
flit ~f'li IIII I'll ·· '11 1,1, II1I .1-.,
· ~
~
I
":II!
,. · · r~
~
.,;, :
· ~I.
I· · · ·,.· .. 11 '11 ',' . 1liii' , Iitl 1111 fill I It I Ult I
~
"1\
· 11111 .. -
- I_J'...~_ -
·
·
Fig.4: Drain current and voltage wave form. Circuit defined in fig. 1 (a snubber is used in order to avoid voltage oscillations)
10 = 1Ndiv VOS = 100V/div t = 5msec/div
<::>0~ ' ~.::0-
>
L5
..~. ...\;><~/
"-
' / 16 V Single shot l8V
<[
co
kt' -/
l6V
~ rj
l4V
I f/"
I~ f/
l2V
~
IOV
1J1
8V
~~
[2V IdiV.J
Fig.S: Saturation test circuit defined in figure 1
10 = 20A/div VOS = 5V/div Vos = 100V/div
t = 1msec/div
Fig.6: Characteristics of STCP10N50
Tj = 100°C
VOS(on) = 1.4 + (0.118 x 1) for VGS = 15V
c. Operating range and limits: When the STGP10N50 operates over its full frequency ra~ge the peak current in this converter should be limited to 30A by the conduction losses. In any case the RMS current is compatible with die bonding:
IRMS = ~ / 12. = Ipk / 2
at maximum frequency with 30A peak IRMS < 15A. As there are no major switching losses (10 IlJ). a ZCS converter is able to operate at several hundred kilohertz.
- - - - - - - - - - - - - -- 4/12 -----------I..V ~~~~m~¥r::oo~:=
828
APPLICATION NOTE
3.2 IGBTs IN ZERO VOLTAGE SWITCHING RESONANTCONVERTER&
a. Switching: The IGBT's switching behaviour is analysed using the circuit in figure 7, a halfwave zero voltage switch (ZVS) quasi resonant converter. The intrinsic properties of an IGBT create specific losses due to the current tail induced by stored minority carriers, in spite of the "soft" voltage switching. Contrary to bipolar transistors, these carriers are not discharged rapidly as there is no access to the base and they induce losses when voltage is re-applied after current turn-off. Figure 8 shows current and voltage waveforms in the IGBT during conduction and after current turn-off. Figure 9 shows an example of the evaluation of the turn-off energy (Ect) by integration of the current, time and voltage. Current tail losses were measured with respect to temperature, switched current and
re-applied voltage. The results of these measurements are shown in figures 10 to 15. They show that turn-off losses are proportional to dV/dt when current and temperature are constant and proportional to the square of the current when temperature and dV/dt are constant.
- Current tail losses = Pct = K(dvldt,Tj) · 12 · f
- As K is proportional to dV/dt (ref: figures 13, 14,15 - gradients of the curves) and dV/dt is proportional to I in such an inverter, the losses can be expressed as:
Pct = K'(Tj) · 13 · f
where I = switched current.
As K' increases rapidly compared to Ti, the maximum switched current must be strictly limited and the heatsink sufficiently sized to avoid thermal runaway.
Vc;s
V~s
'u
Fig. 7: Half wave mode ZVS quasi resonant converter
Fig. 8: Drain current and voltage wave form.
Circuit defined in figure 7.
ID = 5A1div
VDSan = 1V/div
VDS = 100V/div VGS= 10V/div
- - - - - - - - - - - - - -------------l?ij ~~~m~r::I!~n
5/12
829
APPLICATION NOTE
b. Conduction. In this type of converter, IGBT conduction losses are not a constraining factor due to the low average current. They can easily be calculated by integration, (current x voltage) figure 8. c. Thermal balance. The circuit shown in figure 7 is used where:
switched current = Ip = 20A dV/dt = 1500V/sec
ton = 9.5 msec
The losses due to the current tail can be calculated by subtracting the conduction losses from the total measured losses (thermal balance). An alternative method is, to use the numerical integration as shown in figures 9 to 15: As the results are similar, the numerical integration allows easy calculation of the losses.
d. Operating range and limits. Considering the IGBT switching its normal current, the
Frequency
6kHz 8kHz
Eel (Thermal balance)
566mJ 725mJ
Eel (numerical integration)
420mJ 600mJ
:+:
- -- .- r- - - -- - r- -
~ .....
/V ~
7 /
t:7v-1,1"-I.I.--a
k~
'---ce -
k
-
-
I
\,b
'\
f\ - - - ~ ~h
lV
Fig. 9: Energy evaluation circuit defined in fig. 7. curve a: current tail (1 Ndiv) curve b: drain voltage (100V/div) curve c: (curve a) x (curve b) curve d: curve c x dt
,.d
>. ~200
Qo
c
Qo
44-
?c 100
t.. :J f-
200 400 600 800 dVIdt V lJi-sec
Fig. 10: Turn·off energy Ect 10A switching
-6/-12-----------------------~~~~~~~:~~------------~-----------
830
APPLICATION NOTE
f'>, jLJ
(lJ
c
(lJ
4- 300 4o-
I
E 200
:J f-
100
o
500 1000 1500
eN/eit V/jLsec
Fig. 11: Turn-off energy Eet 15A switching
f'>, jLJ
(lJ
c
(lJ
4-
't 500 E I
400
2 300
200
100
o
500 1000 1500
elV /elt V /jLsec
Fig. 12: Turn-off energy Eet 20A switching
>, jLJ
f' 400
(lJ
c
(lJ
4- 300 4o-
5 c 200
f-
100
>. jLJ
f' 400
(lJ
c
(lJ
4- 300 4o-
5 c 200
f-
100
Fig. 13: Turn-off energy Eet - Tj = 45°e
100
225
400 AMps2
e Fig. 14: Turn-off energy Eet - Tj = 800
", J.LJ
1" 400
'c"
..'..".. 300
o
..~.. 200
100
(switched current)
100 225
400 Anps2
Fig. 15: Turn-off energy Eet - Tj=110oe
maximum switching frequency can be evaluated with, for example, the following conditions:
Ipeak = 10A dV/dt = 500V/msec
Switching losses = 10W
(Safety margin = 33%) ref:- figures 10-15
Tj = 800 e operating frequency = 110kHz Tj = 11 ooe operating frequency = 80kHz
This shows that using IGBTs in this configuration is possible up to 80kHz with fast IGBTs.
----------------------------- ~~~~;~~~:oo~n --------------------------7-/-1-2 831
APPLICATION NOTE
4. IGBTs IN RESONANT CONVERTERS.
The switching conditions of this type of converter are dependent on the switching frequency because they work in the continuous operating mode. For this reason, close to the resonant frequency, the constraints on the IGBT are similar to those of the quasi resonant converter in the ZCS or ZVS mode, whereas above or below the resonant frequency, a different switching mode occurs.
4.1 Voltage excited resonant converter.
An example of a voltage excited resonant converter circuit is shown in figure 16. Voltage excitation requires a current load, i.e. a series resonant circuit.
a. Operating above the resonant frequency At switch-on: IGBTs operate in the ZCS mode without dV/dt and therefore have negligible losses. At switch-off: Currentand voltage are switched together; as dV/dt is generally reduced by using an external capacitor, the turn-off losses are limited to current tail losses. Consequently, in this situation, the results of the ZVS quasi resonant converter analysis can be applied again. Conduction in the on-state: The maximum conduction losses occur close to the resonant frequency. They can be calculated using the ZCS quasi resonant converter analysis.
An example:
Conditions: Device STGP10N05 IGBT
Tj = 110°C maximum
dV/dt = 1000V/msec
maximum peak current = 16A (close to f r)
maximum switched current"" 8A (f "" 2fr)
Considering that the maximum conduction
losses = maximum switching losses
maximum conduction losses =
(0.445 · I) + (0.0295 . 1}2 = 15W (for 16A)
maximum switching losses"" Eel' f
(for 8A see the curve in figure 15)
The corresponding operating frequency is from 30kHz (fr) to 60kHz (2fr). As in the case of the ZVS quasi resonant converter, the maximum switched current must be strictly limited and the heatsink sufficiently sized in order to avoid thermal runaway.
16A
BA
[\
r
b. Operating be/ow the resonant frequency: At switch-on: Current and voltage are switched together. The losses are due to the discharge of the IGBT's output oapacitance and to the recovery of the diode on the other IGBT.
v
Fig. 16: Voltage excited resonant converter
- - - - - - - - - - - - -8/12- - - - - - - - - - - - L." ~~~;m~~:9::
832
APPLICATION NOTE
The maximum losses can be evaluated as:
1/2 Vf(lpeak max/2 + IRMf dVdl
IRM = diode peak reverse current
At switch off the IGBT is operating in ZCM without switching losses. Conduction: the maximum conduction losses can be evaluated as for the ZCS quasi resonant converters because it is operating in full wave mode close to the resonant frequency.
An example: Conditions IGBT = STGP10N50
dlldt = 300Alsec
V = 300V
Tj = 110°C IRM = 16A
maximum peak current = 20A maximum switched current"" 1OA
Considering:
maximum conduction losses = maximum switching losses
maximum turn-on losses = 338J
maximum conduction losses = 24W
The corresponding operating frequency is
from 70kHz (f/2) to 140 kHz (q. Contrary to
the previous mode, there is no risk of thermal runaway and the IGBT seems to be a good alternative to SCRs in this type of high frequency converter.
4.2 CURRENT EXCITED RESONANT CONVERTER.
An example of a current excited resonant circuit is shown in figure 17. It is the duality of the previous circuit shown in figure 16. The current excitation requires a voltage load giving a parallel resonant circuit. The switching
behaviour depends on the operating· frequency.
a. Operating above resonant frequency:
When one IGBT is switched on there is reverse recovery current from the diode of the second IGBT through the capacitor. This means both current and voltage are switched. The maximum losses can be evaluated as:
1/2 f.V(IRM + 10)2 dVdl
where:
V = maximum switched voltage
IRM = diode recovey current
10 = maximum switched current
At switch-off: the serial diode recovery current reverses the IGBTs current and its collectoremitter voltage. Because of this the reverse recovery charge, Orr, of the series diode must be kept lower than that of the internal PIN diode of the IGBT as this would cause the IGBT's diode to exceed its breakdown voltage, and conduct the leakage current of the series diode. However, current tail losses can occur when re-applying voltage during the off state, and depend on the minority carrier lifetime versus the delay between the diode recovery and the positive collector voltage rise. The maximum turn-off losses occur close to the resonant frequency and are similar to those of ZVS quasi resonant converters. Conduction: The current flowing is continuous and the duty cycle is 50%. The losses are:
"" 1/2 10 ' VOS(on)
b. Operating below resonant frequer.lcy. At switch-on: The IGBTs operate in ZVS mode giving negligible switching losses. At switch-off: Current and voltage are
- - - - - - - - - - - - - -------------JFij ~~~~m&~:U!~~~
9/12
833
APPLICATION NOTE
switched-off. Consequently, losses can be evaluated using the ZVS quasi resonant converter results. Conduction: The duty cycle is not dependent on the frequency so the losses are similar to those above.
5. DRIVE AND PROTECTION CIRCUIT.
The analysis of IGBTs in resonant converters sh6ws that many different switching conditions can occur. The circuit shown in figure 18 is suitable for driving an IGBT gate as it provides the following functions: - Short circuit protection and current limiting. - Adjustable sinking and sourcing output current. - Very low output impedence after turn-off, masking the Miller effect.
6. CONCLUSION
This analysis shows that IGBTs are perfectly suited to resonant converters when the turn off switching is zero current mode. In this situation the switching frequency can rise to several hundred k Hertz giving a controlled current several times its own nominal current. IGBT's are an attractive replacement for more
traditional switching components already in use in resonant converters. They offer the following advantages when replacing:
SCRs: the IGBT provides high dV/dt immunity and virtually no dl/dt limit, no tq and very fast dynamic behaviour. It is very easy to protect under both dynamic and static conditions.
Bipolar Transistors: the IGBT offers very easy gate drive.
Power MOSFETs: IGBTs have a higher current density.
BIBLIOGRAPHY
1) Commutation and stresses of switching devices in static power converters. Henri FOCH/EPE
2) Resonant switches, topologies and characteristics. K.H.LlU, R.ORUGANTI and F.C.LEE IEEE Power elect. spec. conference 1985.
3) Generalisation of resonant switches and quasi resonant DC/DC converters K.D.T.Ngo/IEEE Power elect. spec. conf.198?
4) An unified analysis of converters with resonant switches S.FREELAND and R.D.MIDDLEBROOK/IEEE Power elect.spec.conf.198?
5) Power MOS Device Databook SGS-THOMSON Microelectronics
6) SGS-THOMSON POWER TRANSISTOR APPLICATION MANUALS
Fig. 17: Current ecited resonant converter
--10/12 ----------- '" ~~~m~r::oo~:= -------------
834
APPLICATION NOTE
T12 R7 Fig. 18: Gate drive circuit.
---------------------------~~~~;~~~:~~------------------------1-1-/1-2
835
APPLICATION NOTE
APPENDIX.
DUALITY CONSIDERATIONS OF AN ELECTRIC CIRCUIT
1. Every voltage source (or load) has a capacitive nature. Every current source (or load) has an inductive nature.
2. Connected source and load must always have opposing natures: - Capacitive source with inductive load - Inductive source with capacitive load.
3. A voltage source becomes inoperative when the output is open. A current source becomes inoperative when the output is shorted.
4. Every circuit has duality. The duality rules are set out below.
Voltage source, V
--1.:!:.
T
Loop network [Vi =0
Current source, 1 Node network [Ii =0
Inductance L Capacitance C Series resistance
Capacitance C Inductance L
Parallel resistance
"'". j
n switches time
n switches time (unchanged)
Resonant Circuit
Inductive lood Capacitive load Series oscillator
Capacitive load Inductive load Parallel oscillator
12112
---------------
ar."="'!=1
SGS.THOMSON
1lj]~1:1i@~~~I!:'ii'Ii@Ill~l:i!I
_ _ _ _ _ _ _ _ _ __
836
.~ ...,l S[R'GA]DS©O-O1@rHn[lOJ~©M1J'SOOO@~DN©~
APPLICATION NOTE
BIPOLAR JUNCTION TRANSISTORS, POWER MOSFETs OR IGBTs IN RESONANT CONVERTERS
by P. Fichera
ABSTRACT
Resonant switch topologies operating on the principle of zero-current and zero-voltage switching are discussed. Their advantages with respect to the conventional PWM converter are shown.· The main advantages and disadvantages of some resonant structures are considered
when the ideal active switch is either a bipolar junction transistor (BJT), a power MOSFET, or an insulated gate bipolar transistor (IGBT). Practical examples of power semiconductor choices in these resonant topologies are given.
AN465/0492
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APPLICATION NOTE
1. INTRODUCTION
The main advantage of resonant structures is the reduction of switching losses, and also less stress on the electronic switch occurs compared with PWM structures. These two advantages (lower switching losses, less device stress) are generally paid for in terms of higher conduction losses. The purpose of this paper is to present the elements that permit the most suitable choice of power semiconductor to be made in some types of resonant structures.
2. RESONANT SWITCH
The resonant switch represents the basic element of converters with resonance or quasi resonance. It consists of semiconductors and LC resonant elements. Depending on the configuration of the resonant elements one can obtain the structures of fig. 2 1,2 A family of quasi resonant converters (ORC) is obtained by simply replacing the
conventional chopper power switch with a resonant switch as shown in fig. 3. In each case there is controlled switching either at turn-on in the ZCS or at turn-off in the ZVS.
3. ZERO-CURRENT AND ZERO-VOLTAGE SWITCHED QUASI-RESONANT CONVERTERS (ZCS-QRC and ZVS-QRC)
3.1 ZCS-QRC This configuration permits the switch to be controlled at turn-on, while the turn-off occurs with zero current. The switched current, Is is a quasi-sine-wave and is reduced to zero at turn-off. Switching losses are due to: 1) turn-on switching (although these losses are much lower in comparison to the PWM converter), 2) internal discharge of the power semiconductor output capacitance Coss at turn-on (see waveforms fig.4) 7 3) rectifier diode switch-off.
v.
"
SOA
-----"7~,
ON
I')
, , I
Fig. 1
OFF v. Hard switching
SOA
, ----~~ ....
ON
"- ' ....
I
I
I
OFF
v,
Soft switching
-- 2112 ----------- Iiii ~~t1r:rr~:~ -----....,..-------
838
APPLICATION NOTE
s
Fig.2 ZC-OR switch (thyristor)
ZV-OR switch (Dual thyristor)
V
Load
IS't I r-- I
~ _ __ J
/ \
V
V
,- ----..,
I
I
I L,
f
I
f
T : f
Cr I
: s(
:-~_J
Fig. 3 ZCS-ORC
ZVS-ORC
------------lIii ~~~~m~r::O!~J: - - - - - - - - - - - -3/12
839
APPLICATION NOTE
3.2 ZVS-QRC
This configuration permits the switch turn-off to be controlled; the turn-on occurs with zero voltage (the capacitive turn-on problem of ZCS-ORC is eliminated). This operating mode is called "dual thyristor" because the switching properties follow the duality rules of the thyristor, i.e. spontaneous turn-on at zero voltage and controlled turn-off [Ref.1]. The voltage across the switching device is quasi sine wave and is reduced to zero at turnon. The only switching losses occur at turnoff as shown in the waveforms of fig.S.
4. WHICH SWITCH?
We are interested in analysing the behaviour of the two quasi resonant (OR) topologies when the active switch, S, is a BJT, a Power MOSFET or an IGBT. Table 1 shows the main features of each power semiconductor (V > 400V). Because the cost of a power semiconductor varies with the chip-size the curve of fig.6 gives a cost analysis.
4.1 THE PHYSICAL LIMIT OF A POWER BIPOLAR TRANSISTOR.
The presence of storage time, ts' limits the maximum frequency of operation. Extra losses are due to the presence of V CEsat(dyn) at turn-on.
4.1.1 A BIPOLAR JUNCTION TRANSISTOR IN ZCS.
The storage time, ts' limits the duration of td between the time that the current is zero and the re-applied voltage (td is in the order of ts). The transistor voltage does not reach zero instantaneously at turn-on (V CEsat(dyn)). This phenomenon could increase the conduction losses for a short time.
4.1.2 A BIPOLAR JUNCTION TRANSISTOR IN ZVS.
The storage time, ts' limits the maximum frequency of operation of the converter.
4.2 THE PHYSICAL LIMIT OF A POWER MOSFET.
If there are no economic limits the Power MOSFET is almost a perfect component for many applications, but has two real limitations: a) internal capacitance; b) the presence of the body drain diode. This diode is: b.1) a good diode during its turn-on behaviour (very low peak voltage) b.2) a poor diode during turn-off.
4.2.1. A Power MOSFET in ZCS
The Power MOSFET is not adapted well to ZCS operation because the body drain diode is subjected to very hard stress due to the recovery phenomenon. The only solution when using a Power MOSFET in the ZCS mode at high frequency (> 20kHz) is to add a fast diode (D2) and a Schottky diode (D1) as shown in fig.8 The maximum frequency will be limited by the losses due to the Power MOSFET internal capacitance.
4.2.2. A Power MOSFET in ZVS.
In this type of operation, as in the "dual thyristor" operation, the body drain diode is not subjected to stress after it's current becomes zero. In addition, the turn-on occurs at zero voltage and consequently the energy stored in the parasitic MOS capacitance is not lost. The nature of a Power MOSFET makes it very suitable for ZVS operation.
- - - - - - - - - - - - -- 4/12 ----------- 'V ~~~~~~r::oo~::
840
APPLICATION NOTE
1, C,
VS
Vs
[\ (
Is
!
I
I
I
I
10
QhI
I
I
I
II/I I
Fig. 4 ZCS-QRC (with bidirectional current switch) and corresponding waveforms.
/(J i
l;7'
Fig. 5 ZVS-QRC (with unidirectional voltage switch) and corresponding waveforms.
--------------------------~~~~~~~::~~ ------~----------------5/-1-2
841
APPLICATION NOTE
84: VeE
I)~e
ADVANTAGES
- Very Iowan-state voltage drop
- Reduced silicon area
- Low cost
DISADVANTAGES - Cost of base drive - Storage time (ts)
D
,~ ·
c
.~ ,
VOS
V 10
Va;,
,
- E. ~f---, ,"
IH
Ie
ADVANTAGES
DISADVANTAGES
- Low voltage drop is
- Cost
obtained with large
- In some cases
silicon area
dangerous
- Cheap gate drive
to use body
- Reduced turn-off
drain diode
delay time
- Anti-parallel body-
drain diode can be used
ADVANTAGES
- Lowvoltagedropat high current density
- Cheap gate drive
D ISADVANT AGES
- Presence of threshold voltage Eo
- Current tail effect at turn off
mm2/A
10
5
VeE
2V
()'?
~
~0"
~.~ ~~fI
n <to
... c.~
-l:~
,1!\..t' /. " ~<?>\\'J .l 1. .pf>1.
. illUlfl1J1fU L1-'
-
iir":ftr:rlJl
100
600
Vol1s
Fig. 6 Chip surface vs maximum rated voltage
--------------------------- 6/12
--------------~----------- ~~~~~~~v~:~~
842
zcs
APPLICATION NOTE
zvs
I 1.o1·f--_~~1I
'.
I
Presence of a dead time td which limits fmax (td is in the order of ts and depends on the base drive circuit)
V CEsat (dyn)
I
I
"
41
- The storage time (td) limits fmax
Fig_ 7 - The physical limit of Power Bipolar Transistors in quasi resonant circuits.
o
s
Fig.8 Disabling a Power MOS body drain diode
-------------- -------------- I:;i ~~~~m~¥r::~~J:
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843
APPLICATION NOTE
- t = 0.2 ms/div.
- VCE = 100V/div. -Ie = SA/div. - V9 = SA/div. - Te = SO°C
- dV/dT = 400V/ms
Fig. 9 IGBT behaviour during turn-off in ZCS mode. The waiting time, td, is not enough and a current peak, bigger than that due to the capacitive effect, appears due to the effect of the re-applied voltage.
4.3 THE PHYSICAL LIMIT OF AN IGBT.
The IGBT has an economic advantage in comparison to the Power MOSFET (smaller silicon area for the same voltage drop), but its turn-off is influenced by the bipolar transistor section. At turn-off. the minority carriers which remain in the basecollector junction of the bipolar section increase the turn-off losses (current tail effect). If the IG!3T turn-off is controlled by only acting on the gate. it is necessary to wait for a time, td' before re-applying the voltage. otherwise extra losses generated may make the device fail due to thermal run-away. This time. td' must be longer than the duration of the current tail effect (in the order of 3-411S for a 1000V IGBT)8.
4.3.1 AN IGBT IN ZCS.
The frequency is limited by td' consequently the IGBT in ZCS can attain a relatively high frequency (around 120kHz). The losses due to the internal IGBT capacitance in this frequency range are smaller than Power MOSFET losses. In fact. for a given current rating the IGBT capacitance is much smaller than the Power MOSFET capacitance. The only other limitations are the conduction losses.
4.3.2 AN IGBT IN ZVS.
The main limitation of the IGBT in this configuration is the high switching losses due to the current tail effect. A larger value capacitor. Cr. acting as a snubber. reduces dV/dt at turn-off and, consequently, turn-off losses 5.
844
APPLICATION NOTE
SUMMARY OF THE PHYSICAL LIMITS OF SEMICONDUCTORS TABLE II
- Storage time-> frequency limitation
- Storage time -> frequency limitation
BJT
- V CEsat(on) -> turn-on losses
Power MOSFET
- Recovery of body drain diode - Capacitive turn-on losses at high frequency - High voltage - Conduction losses
IGBT
- Deadtime -> frequency limitation - Von-state -> conduction losses
- Turn-off tail problems
5. TWO PRACTICAL EXAMPLES.
5.1 The first example we are going to consider is a single-switch ZCS-QRC with the following characteristics: 1.SkW - SOkHz - 220V mains. The switch current waveform will be characterized by:
Because the time t2 < t1 = 8jls (conduction time of the antiparallel diode), this time is large enough if compared with the fall-time, tf of an IGBT « 1jls) or the storage time, ts' of a bipolar transistor (1-3jls) there are no problems in using these semiconductors.
t1/T = 0.4 IAVG = SA
Ipeak = 20A
IRMS = 9A
, ............ _ , ./
T
--------------------------~I ~~~~~~:~~ ------------------------9/-1-2
845
APPLICATION NOTE
ANALYSIS OF DIFFERENT POWER SEMICONDUCTORS (Devices selected with similar current rating)
BUF420
450/850V - 20A ETD Bipolar Junction Transistor) [54 square mm. silicon area]. Conduction losses calculation gives Pcond = 8.1 W.
TSD4M451
(450V/R DS(on) = 0.15 Ohms at 100DC ISOFET) [176 square mm. silicon area] To obtain conduction losses comparable to BJT losses, it is necessary to choose a large silicon area Power MOSFET (P cond =12.1 W). The main disadvantages are: 1) turn-on capacitive losses 5.5W at 50 kHz due to the big chip-size (176 square mm total silicon area) 2) extra conduction losses (3W) due to the use of a power Schottky diode
STGH20N50 IGBT 500V/20A) [32 square mm. silicon area] conduction losses calculation 5 gives Pcond = 12W.
STGP10N50 (IGBT 500V/10) [16 square mm. silicon area]. Due to its over current capability a 10Al500V IGBT can be used in this application. Conduction losses calculation 5 gives Pcond = 18.6W.
CONCLUSION: IGBTs and BJTs are concurrent solutions. IGBT advantages are: 1) gate drive simplicity 2) saving in silicon area.
BJT advantage is due to the optimum ratio of conduction losses to device cost. However the storage time limits the BJT frequency operation to no more than 70kHz.
5.2 The second example we are going to consider is a single - switch ZVS-QRC with the following characteristics:
300W - 150kHz - 11 OV mains (± 20%): The switch current waveform will be characterized by:
(t1+t2)/T = 0.6
IAVG = 2A
Ipeak = 10A IRMS = 3.65A
Vs(peak) = 750V (max.)
T
--10/12 ----------- "" ~~~~m&~:oo?:= -------------
846
APPLICATION NOTE
ANALYSIS OF DIFFERENT POWER SEMICONDUCTORS. (Devices selected with similar current rating)
BUF410
(4S0/8S0V - 10A ETD bipolar junction transistor). The storage time ts
(1 - 3/1s) is comparable with t1 + t2 = 4/1s. The use of a BJT at this
frequency of operation is not possible. For the ETD BJT technology an upper frequency of operation is around 100kHz.
STH9N80
(800V/R DS(on) = 1.S Ohms at 100°C Power MOSFET). Conduction loss calculations give Pcond = 20W. Turn-off losses are negligible. The Power MOSFET body drain diode is not subjected to any stress and can be used as an anti-parallel diode.
STGH8N100
(1 000V/8A IGBT). At Iswitch = 1OA and dV/dt ~ 1OOOV//1s the IGBT turnoff losses can be evaluated at around 0.6-0.7mJ/Hz. It means roughly 10SW at 1S0kHz only for turn-off losses. Conduction loss evaluations give Pcond = 4.6W.
CONCLUSION: For this single-switch application, the Power MOSFET is the most suitable choice.
At the given frequency of operation and duty
cycle one obtains: t1 + t2 = 4 /1s
SUMMARY OF EXAMPLES
The physical limit of the semiconductors examined and the examples taken into consideration show that in a single switch ORC a correct choice of the switch is the following:
IF ZCS - ORC: Bipolar Junction Transistor (f < 70kHz) Power MOS (f < 20kHz). Higher frequency of operation could be obtained disabling internal body drain diode or using a FREDFET. IGBT (f < 120 kHz)
IF ZVS - ORC:
Bipolar Junction Transistor (f < 100kHz) (f = O.S to 1MHz) IGBT (f < 20 - 30kHz) Power MOSFET (0.5 MHz -1 MHz)
CONCLUSION
Each power semiconductor we took into consideration shows physical characteristics that limit its operation in single switch quasi resonant converters. In particular the bipolar solution is acceptable for both ORC topologies at frequencies lower than 100kHz. The power MOSFET solution is disadvantageous in applications at high
11/12
- - - - - - - - - - - - ! i i i ' ! SGS·lltOMSON - - - - - - - - - - - '], ~O©L1I@~~~!:1i'L1I@IIIIO©® 847
APPLICATION NOTE
RMS currents such as those in discontinuous ZCS-QRC. Despite this, power MOSFETs are most suited to the ZVS-QRC due to their fast switching times and the possibility of using the body drain. diode even with their inferior performance. The IGBT solution is today the most popular for resonant and quasi resonant applications. However in ZCS-QRC where its use seemed to permit very high working frequencies, the dynamic dV/dt phenomenon may lead the device to fail due to thermal runaway. This can be overcome by careful design and the use of an efficient heatsink.
References
1) Yvon Cheron, "La commutation douce dans la conversion statique". Edition Technique et documentation LAVOISIER - Paris.
2) Fred C. Lee, Wojciech A. Tabisz, Milan M. Jovanovic, "Recent developments in high frequency Quasi-Resonant and Multi-Resonant Converter Tecnologies". EPE Aachen, 1989 pp.401 - 410.
3) J.P.Ferrieux, F.Forest, P.Lienart, "The insulated gate bipolar transistor: switching modes". EPE Aachen, 1989 - pp.171 - 175.
4) J.M.Bourgeois, B.Maurice, "Losses of insulated gate bipolar transistor in H.F. Resonant Converters". IEEE Industry Applications Society Annual Meeting, 1989 - pp.1197-1204.
5) P.Fichera, "Analyse des pertes dans un IGBT'. Seminaire Technique 22 Septembre 89, Grenoble (SEE) - pp. 3.1-3.12.
6) Power Transistors - SGS- THOMSON Application Manual- 1st edition - pp. 91 - 97.
7) K. Rischmuller, "Improve efficiency of high frequency power conversion designs" Proceedings of P.E.C. Californill., February 1990.
8) R.Letor, M.Melito, "Safe behaviour of IGBTs
submitted to a dVldt". Power Conversion Munich
June 25-28, 1990 (samE) proceedings).
9) J.P.Arches, N.Bonnet, F.Oms, D.Revel, J.Roux, "Optimisation de la commutation de transistors
Mos haute-tension dans un onduleur a resonance a 500kHz". L'electronique de
puissance du futur, SEE, Bordeaux 1-13 juin '88.
-- 12112------------ '1i ~~~;m~~:~~:: --------------
848
l ~
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APPLICATION NOTE
AN ANALYSIS OF LOSSES IN AN IGBT
by P. Fichera
1. INTRODUCTION
Insulated gate bipolar transistors are now being used in a variety of switching applications. These range from automotive ignition, where they replace the mechanical contact breaker, to electric motor drives, where they provide an economic, easy to drive. chopper switch with high voltage capability. More recently work has been done in using these devices in various types of power supplies. They are attractive to use due to the high
impedance input, a MOS gate that requires a mimimum of only 8V and microjoules of energy to turn it on and off and the bipolar nature of the output that makes them capable of controlling high current densities. To obtain the optimum performance from IGBTs it is necessary to understand the limits imposed by the structure of the device and their particular operating conditions. This paper looks at the use of IGBTs in chopper circuits and shows how to evaluate the losses during switching and conduction.
AN466/0492
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APPLICATION NOTE
2. LIMITING FACTORS FOR IGBTS IN CHOPPER CIRCUITS
Chopper circuits operate at frequencies determined by the nature of the application and of the power switch employed to control the current flow. As is the case with Power MOSFETs, power is dissipated in IGBTs at turn-on of the device, during conduction and at turn-off. The major difference between IGBT and Power MOSFET switching losses occurs in the turn-off switching behaviour. Figure 1 illustrates the typical losses for an IGBT used in a chopper application.
2.1 TURN-ON LOSSES
It is not sufficient to know the rise time, tr, of the turn-on current. The free-wheeling diode used in conjunction with the IGBT, figure 8, is responsible for a large amount of the losses as a result of its reverse recovery current., Within a given application it is necessary to know the (dID/dt)on for this diode in order to evaluate the reverse recovery current, I RM. Once IRM is known it is possible to calculate the turn-on losses.
2.2 CONDUCTION LOSSES The following simple expression shows how to calculate the conduction losses.
where:
Pon = on-state power dissipation
IRMS = RMS current value for the application
IAVG = average current value of the
application
Eo,Ro = are parameters defined by the IGBT output characteristic Ie' Vee - see figure 2.
Eo = abscissa of the intersection between
the tangent to the output characteristic calculated at Ie = 10 and the Vee axis. Ro = inverse slope of the tangent to the output characteristic curve Ic' VCE' calculated at le=lo. The area B in figure 1 illustrates these losses.
I .~
- VGE =15V '--- Tj =100'C
/
/
Roy
10
J
V
/
0
v.
VERTICAL/DIV 2A
HORIZONTAL/DIV 500rN
Conduction Fig. 1 - Typical IGBT losses
STGPlON50 Eo = 1.3V
} AT 100'C
RO = 015 Ohl')s
Fig. 2 - Output characteristics of STGP10N50
-217- - - - - - - - - - - - l i f i ~~~~~~~:::: - - - - - - - - - - - - -
850
APPLICATION NOTE
2.3 TURN-OFF LOSSES
Calculation of the turn-off losses in an IGBT requires more information than just the fall time, t1 . On its own it leads to erroneous results. It is necessary to know how other parameters influence these losses. Most care has to be taken with the current tail phenomenon of the IGBTwhen it is operated in hard switching. Two parameters define the current tail: its amplitude, It, and its duration, tt.
A) THE INFLUENCE OF THE SUPPLY VOLTAGE ON TURN-OFF LOSSES.
The supply voltage and the current tail amplitude are directly proportional. However, the duration of the tail remains almost constant when the supply voltage is varied.
8) THE INFLUENCE OF DV/DT ON THE TURN-OFF LOSSES
A low dV/dt value at turn-off (imposed by an external circuit, e.g. a snubber) reduces the current tail amplitude, It. The tail duration does not change when dV/dt is varied.
C) THE INFLUENCE OF TEMPERATURE ON TURN- OFF LOSSES.
Operating temperature affects the duration and amplitude of It and tt. Experimental analysis shows that both increase in value by the same percentage as the temperature increases.
D) THE INFLUENCE OF THE GATE RESISTANCE, Rg(off)' The gate resistance does not affect the current tail. Varying Rg(off) controls the slope of dVI dt at turn off and consequently can give some reduction in the turn-off losses. A minimum value of Rg(off) is required to prevent oscillations occuring during turn-off (as is the case with power MOSFETs).
5 CALCULATING CONDUCTION LOSSES When calculating conduction losses at 1aaoc it is better to base the calculation on the output characteristics of the IGBT (Ie versus Vee) at a given Vge'
Table 1. Additional parameters required to calculate turn-off losses in IGBTs.
V
- the re-applied supply voltage
dV/dt - slope of re-applied supply voltage
Tj
- junction temperature
Rg(01f) - gate resistance at turn off.
3. SAMPLE CALCULATIONS.
It is possible, using the curves given in figure 9 and the energy curves characteristic of figure 1a for different operating conditions, to calculate the switching losses for a given set of conditions. This in turn allows the maximum operating frequency for the IGBT to be calculated. The basic circuit in figure 8 shows the configuration used for the STGP1 ON50 50aV, 1aA IGBT and its switching waveforms.
3.1 CALCULATION OF THE TURN-ON
LOSSES AT Tj = 100'C.
The value of the gate resistor during turn-on is 47 Ohms. USing the graph in figure 9a this gives a value for dl D/dton of 100Al!ls. As the IGBT controls dlldt it follows that the recovery current of the free-wheeling diode can be determined from the diode datasheet (graph of IRM versus dl/dt is shown in figure 9b). This gives a value of IRM = 10A. Applying the formula for the turn-on losses:
Wt(on) = 112 Vsupply (10 + IRM)2 · 1/(dl/dt)on
Wt(on) is calculated to be: Wt(on) = O.4mJ
-------------------------- ~~~~~~~~:~~-------------------------3/-7
851
APPLICATION NOTE
3.2 CALCULATION OF CONDUCTION
LOSSES AT Tj = 100oe.
The value of the parameters Eo and Ro have been evaluated from the graph of Ie versus Vee shown in figure 2.
Eo = 1.3V
Ro = 0.15 Ohms
Taking 'AVG to be 3.5A and IRMS as 5.8A, Pon can be calculated using the equation from section 2.2
Pon = 9.6W
3.3 CALCULATION OF THE TURN-OFF LOSSES.
A. High dV/dt (2500V/~s)
Using a value for Rg(off) =470hms and taking
into account the dV/dt curve of figure 10 a; at a switched current of 10A the energy dissipated in turning off is
B. LOW dV/dt (500V/~s)
Using Rg(Off) =47 Ohms and switched current
of 10A again W\(off) = 0.3 mJ/cycle.
Summarising these values show that the total power dissipated is dependent on the operating frequency. Accepting that .the maximum power that can
be dissipated from the device at 1oooe is 40
Watts for this device in a TO-220 package, it is simple to calculate that using high dV/dt the IGBT has an upper limit of operation of 20kHz . while with low dV/dt operation is possible up to 40kHz.
Ie
Wt(Off) = 1.1 mJ/cycle
Fig.4 - Influence of supply voltage on turn-off losses
Ie low dVNt
Fig. 3 - Turn-off losses
Fig. 5 - Ov/dt effect
-4/-7 ----------------------~~~~~~~~::=--------~--------------
852
APPLICATION NOTE
Ie
Fig. 6 - The effect of temperature on It and ~
Ie
v
Rg
Vcr
Fig. 7 - The influence of gate resistance
- - - _ _ < t - - - - 400V
BYT30P 600
+ 15V
I
.:t:,C
Fig. 8 - Basic circuit
------------- /iii ~~~~m&~:U&~~ -------------5/7 853
APPLICATION NOTE
(dil d-t)on
[A/fl,s]
300 200
I,
\
\~
Tj 0 100'C V = 400V
100
o 20 40 60 80 100 Rg(On)
9a Fig.9
IRM (A)
30 20
10
a p::
10
1 1
~
.<l
ill?
7
9b
Wt 0 ff r----.-~-,__-,--___,-.,--.______,
[mJ]
3
'k'''''
Vos '" 15V
"qo(l-47o hm'l
Tj =100 t
-/---j----t~
2500 IlS
2
W\ off ~~-rl- , [rnJ] "..,,-",hm"
'Ie", -15'1
3
lj_l0()OC
2
o
10
20
30 Iswitch[A]
o
10
20
(a) influence of dv/dt
(b) influence of Tj and V supply
Wt 0 f f r--'---r--'--~r----.-----,----,---. [mJ]
3
'bS=400V Vcs=15V
1.= 1roC I
2
o
20
30 Iswilch[A]
(c) influence of Rgoff, gale resistance at turn-off
Fig_ 10 (a,b,c) - Controlling factors for turn-off losses in a "2nd generation"500V/10A IGBT
6/7
--------------~~~~~~~~9~
--------------
854
APPLICATION NOTE
High dV/dt Low dV/dt
Wt(on)+Wt(off)
P(on)
Total Power Dissipated
1.5mJ/cycle 0.7mJ/cycle
9.6W 9.6W
1.5 · 10-3 · frequency + 9.6 W 0.7' 10-3 · frequency + 9.6 W
4. CONCLUSION
IGBTs are rugged, easy to drive and cost effective switches for high voltage chopper applications. They are capable of sustaining high current densities. Their operating frequency has been shown to be dependent on the operating conditions and a straight
forward method of estimating this was discussed. For applications such as motor drives they are robust and reliable alternatives to bipolar transistors and Power MOSFETs.
-------------------------~~~~~~~:~~------------------------71-7
855
APPLICATION NOTE
A NEW ISOLATED GATE DRIVE for Power MOSFETs and IGBTs
by JM. Bourgeois
INTRODUCTION
Isolated power switches are very often used for applications in motor drives, un interruptible power supplies, and AC switches. It allows the safety norms to be met and provides the operating isolation required when the switch is floating with respect to ground. Today, the isolated base drive design of bipolar power transistors is well understood (see bibliography), whilst those for Power MOSFET designs are less well known and are still improving. This paper highlights and uses the specific behaviour of a Power MOSFET, and area often neglected: the gate drive described capitalises on the opportunity to use the gate input capacitor as an no-state memory. Driving a transistor requires supplying signals and energy. If switch isolation is needed, optical links and lor transformers are used according to the specified norms and operating dV/dt. This paper proposes an innovative isolated gate drive using the memory effect of the Power MOSFET input capacitor and an associated pulse transformer that provides both signal and energy to this capacitor.
GENERAL CHARACTERISTICS OF A POWER MOSFET ISOLATED DRIVER
Safety norms impose a minimum creepage distance and clearance as well as insulation resistance between control circuit and power switches. These isolation requirements have to be respected by any opto-coupler, pulse transformer or auxiliary power supplies. Electrically, its power switches often float above ground and any isolation must withstand a dV/dt above 20V/nsec. Because a high dV/dt induces a large Miller effect, a low gate drive impedance has to be used during the off-state to avoid any spurious unwanted turn-on of the power switch. As these switches are generally used in PWM circuits, the minimum ON or OFF time must be as low as possible, so enabling a large duty cycle range to be available. Short circuit detection that, via the control circuit, ensures safe operation.
THE NEW CONCEPT
The basic principle consists in using the Power MOSFET input Capacitor to memorize its ON-state,
another auxiliary MOSFET to memorise the OFFstate and give a low gate drive impedance. Isolation is provided by a pulse transformer which charges or discharges the transistor input capacitance. The pulse transformer is used as a bi-directional energy/signal channel as follows:
· During the primary pulse, energy is transmitted and the state of the Power MOSFET gate is defined.
· After primary pulse and during the steady state, an alarm signal is transmitted from secondary to primary if a short circuit occurs in the power circuit.
The main advantages of this isolated gate drive are:
A High Operating Frequency Range: This driver is able to operate from d.c. to several hundreds of kiloHertz because the transformer delivers very short pulses:
- Continuous ON and OFF states are possible when automatic refresh pulses at about 1 kHz are used.
- High frequency operation is possible because pulse time and delay time are less than 1 msec.
Duty cycle is not limited. For the same reasons as in 3.1, the duty cycle range is large: the minimum ON time or OFF time is about 500nsec enabling the duty cycle to range from 0.01 to 0.99 at 20kHz.
No floating auxiliary supply: All the switch driving energy is supplied by the pulses from the transformer, the driver does not require an auxiliary power supply.
Low energy requirement. The energy supplied by the pulse transformer is, on averange, twice the gate capacitor stored energy. The global driver energy consumption is very small, hence the cost of the gate drive voltage supply is low.
Good ground-to-gate drive isolation: Because the pulse transformer provides the isolation, the creepage distance and clearance are easily adjusted to suit the requirements of the application.
Perfect dVldt immunity: The pulse transformer is sized so as to sustain 15 Volts for 500 nsec. This can be achieved by using a small ferrite torroid with
AN461/0392
1/6
857
APPLICATION NOTE
just a few turns. The primary-secondary electrostatic coupling effects are negligible and the immunity to voltage fluctuations is perfect. An additional benefit is that a torroid of less than 10mm external diameter can be used - possibly a surface mounting version.
Low Gate Drive output impedance during OFF state: During the OFF-state, a low impedance is maintained across the gate-source of the Power MOSFET which avoids any unwanted turn on should any external dV/dt be experienced.
Short circuit protection: The secondary circuit has an automatic short circuit protection; this protection is inhibited during turn-on pulses in order to mask the diode recovery current of the power circuit. It can operate with current sensing or a shunt resistor.
Alarm signal: When the short circuit protection operates, it discharges the Power MOSFET input capacitor through the pulse transformer. Then, it operates in reverse mode and transmits an alarm signal from the secondary to primary of the pulse transformer.
FUNCTIONAL DESCRIPTION
Figure 1 shciws a block diagram of the circuit. It is
made up of a primary pulse generator, a pulse transformer and an isolated secondary circuit operating without any auxiliary supply.
Secondary Circuit: Figures 2a to 2e allow a step by step analysis of the secondary circuit to be made as follows.
Turn ON pulse: Figure 2a shows the charge cur-
rent, i1, of the Power MOSFET Tp input capacitor
when a positive pulse is applied to the pulse transformer primary. The gate voltage, Vg, rises to V1, depending on the resistance Rc. When the primary pulse disappears, V1 is about zero and the diode D prevents Cg from being discharged. The Power MOSFET keeps its gate charge and remains in the conducting state.
Turn OFFpulse: Figure 2b shows the Power MOSFET input capacitor discharge current, 13, through Rd and Td. The discharge occurs when the capacitor, Cm, is charged through D2 by means of circuit W biasej by V2. Zener diode, Dz, is required to limit the gate-source voltage of Td at the beginning of the negative pulse, V2. Details of the circuit Ware given in figure 2c.
Fig4re 1 : Block Diagram
PRIMARY ClRCUI1
r------------------------.---
INPUT
ASILGANRAflL
~d!:!~l::~::::i=!:::~:::.,.J
r
SECONDARY CIRCUIT
J
o
2/6
--------------
~ ... , /
S!lGl~©SI¥·31@H~~IO<©MVOOS@IORlNU~
--------------
858
APPLICATION NOTE
Figure 2a: Charge current for the Power MOSFET, Tp, input capacitor when a positive pulse is applied to the transformer
Tp
He
11
Cg
Dz Vg
117.
positive pulse
D
Figure 2b: Power MOSFET, Tp, input capacitor discharge current
. He
Negative pulse
1l2~
~ - - r 12
'W I
'- -
Short circuit protection: A short circuit can be detected by means of a. shunt resistor, or current sense (see figure 2d and 2e). It induces a rise of Vs which charges Cp which in turn makes T3 conduct. The power transistor input capacitor is discharged through the pulse transformer and the transistor T3. It produces a current pulse in the transformer secondary enabling a short circuit to be detected via the primary winding.
Diode recovery current: Generally, power switches have an associated diode recovery current at turnon. This creates a brief over-current in the switch that requires masking from the short circuit detection circuit during this recovery time.
Due to the Miller effect, the current i1 lasts for as
long as the collector/drain voltage falls. Inhibiting short circuit detection by means of h masks all the diode recovery current.
This function is carried out by T5 which detects i1 through Rc and makes T4 conduct. The current 15
flows through T4 instead of charging Cp during the diode recovery time, avoiding spurious cunduction ofT3.
Application: Figure 3 shows the short circuit behaviour of the STHI20N50 (20N500V IG8T). Note that the short circuit protection acts immediately after a 400nsec delay, that is, after the turn-on pulse.
Primary circuit: The primary circuit can be made by simply using a full bridge with a single primary winding. The primary control sequence is described in Figure 4. A pair of sense diodes are located at the bottom of the left hand half-bridge; they control the demagnetisation current used to detect the short circuit alarm signal.
---------------------------- ~~~~@~~~:~~ ---------------------------3-/6 859
APPLICATION NOTE Figure 2c: Details of the circuit W from fig. 2b
Tp
~ --l~ --
,--,.-I--------------r---,rll'll'd
Figure 2d: Over current detection and short circuit protection
14
Figure 2e: Protection inhibition during diode recovery current
Figure 2a-2e:A step-by-step analysis of the secondary cir-cuit 860
APPLICATION NOTE Figure 3: Short circuit behaviour at turn ON with a 20A/500V IGBT - STH120N50.
lov/div collector vol,tage 100V/div
200 nsec.
collector current 10A/div Tj ~ 60°C
Figure 4: The primary circuit control sequence.
Typical pulse time: 500 nsec Primary supply voltage: 12V - 15V
I 1
I 1
I 0
OFF state
ON pulse positive pulse
1
I 0
I 1
OFF pulse negative pulse
ON state
5/6
861
APPLICATION NOTE
Figure 5 : The primary alarm signal· pulsed controlled driver with memory effect.
Pluse controlled driver with memory effeqt: primary alarm signal
u.
I primary
Normal conditions
V diode I primary
V diode
I primary
lusec/div
Figure 5 shows the primary circuit behaviour under normal cOl)ditions and with the power stage short circuited.
Normal conditions: The positive current pulse corresponds to the turn ON signal and is followed by the demagnetisation current. Tt:Je negative current pulse is due to the turn OFF signal. It is possible to see that the voltage across the sense diode is always positive during the turn ON pulse and the corresponding demagnetisation.
Short circuit conditions: The waveforms are similar to the previous ones, except for the current after the positive pulse. Due to the discharge of the input capacitor, Tp, through the transformer secondary, a negative current pulse occurs at across the primary at the beginning of the demagnelisation, inverting the voltage across the sense diode. By sampling and latching this voltage 100nsec after the end of the turn-ON pulse, it is simple to provide an alarm Signal.
If the alarm signal is not required the integrated circuit L293D, can be used to drive the pulse transformers. This is contains two full bridge drivers enabling it to drive 2 transformers. It makes an excellent interface between a digital control circuit and the two pulse transformers of an isolated bridge leg.
CONCLUSION
This new concept for a Power MOSFET driver is perfectly suited to drive floating and/or isolated switches. Moreover, it also provides important cost
reduction compared to standard solutions.
Its operating mode permits a large duty cycle range, requires no floating auxiliary supply, has perfect
dV/dt immunity and a short circuit protection feature
that provides an alarm signal to the grounded control circuit. Lastly, it is now feasable to make a fully SMD circuit due to the availability of SMD pulse transformers.
BIBLIOGRAPHY
1) Power semiconductors for high frequency ACIDC converters supplied on the 3801440V mains. - L. Perier J M Charreton - Application Notes - SGS-THOMSON Microelectronics.
2) Optimised power stages for high frequency 3801440Vac medium power switch mode supplies. - C K Patni L Perier - Application Note SGS-THOMSON Microelectronics.
3) Improved transistorised high power' chopper PCI 83 GENEVEA K Rischmuller SGS-THOMSON Microelectronics.
4) Simplified switch mode base drive circuit with the L4974 Smart Power I.C. - K Rischmuller Application Note - SGS-THOMSON Microelectronics.
5) Power Transistor Application Manual SGS-THOMSON Microelectronics.
-6/-6------------------------- ~~~~@~~'m~©' ---------------------------
862
863
APPLICATION NOTE
THE TRIAC
The TRIAC' is a semi-conductor device with has been specifically designed to operate as a controlled switch in an AC power system.
With the introduction of electronic component into industrial application, the utilization of the Triac as a complement, the utilization of the Triac as a complement to, or replacement for, electromechanical switches or relays and magnetic control systems, has been rapidly expanding in this field. In addition, its availability has led to the development of new control systems which were not feasible with the previously devices.
The advantages of the Triac are its noiseless oper
alion, its ability to be controlled at precise instants and without rebounds, its auto mati turn-off when the current reaches zero after the control has been removed, and its ability to withstand without wear an unlimited number of operating cycles when used in the conditions specified by the manufacturer.
We shall briefly describe the principle of operation of triacs used as controlled switches, then insist on the precautions required during utilization to maintain high reliability (section 2 and appendix 1) and, finally, give, in Section 3, examples of applications as on-off control switches, static relays and power variations units.
SYMBOLS AND TERMINOLOGY
Half wave: half cycle of the alternating input voltage Va. The polarity (positive or negative) of each half wave is defined with reference to the potential of the triac electrode AI.
Full wave: couple of consecutive half waves (one positive, one negative).
Trigger pulse: gate current pulse switching on the triac.
Firing: change to conduction of the triac until the current iT flowing through it reaches the value IL enabling it to remain in the conducting state up to the end of the half wave (until iT has dropped below IH): see IH and IL below.
Va: instantaneous value of the alternating input voltage (mains voltage, as a generate rule)
VRMS, IRMS: rms values of Va and of the load current.
VT, iT: voltage across the triac in the conduction mode, and current flowing through the triac.
VM: "breakover voltage": voltage applied, in the static state, between A2 and Al and beyond which the triac is changed to the conduction mode without gate current.
VDWM: minimum guaranteed value of VM (= peak working forward voltage: see 2.3).
IG: gate current, or trigger pulse peak value.
IGT: minimum gate current IG required to switch-on the triac (if permitted by the load conditions: see IL).
IH: "holding current": minimum value of iT required to maintain the triac in the on state (below which the triac turns off).
IL: "latching current": minimum value of iT required to hold the triac in the steady conducting state after the triggering pulese has been removed.
ITSM: non-repetitive peak overload current in the conduction mode.
IRsM: repetitive peak overload current in the conduction mode.
=: "angle of conduction" of the triac (=/rc represents the fraction of each half wave during which power is applied to the load).
<p: load current phase shift with respect to the input voltage Va.
di/dt: see 2-2
dv/dt, (dv/dt)c, : see 2-3.
"The word 'TRIAC" is an acronym for "TRlode for Alterning Current".
-A-N-30-1-/0-4-92--------------------- ~~~~@~~~:~~©~--------------------------1-/2-2
865
APPLICATION NOTE
1. OPERATION OF THE TRIAC AS A CONTROLLER SWITCH
1.1. STRUCTURE
Like the transistor or the thyristor, the triac consist of
alternate layers of p-type (majority carrier = holes) and
n-type (majority carriers = electrons) semiconductor materiaL In the case ofthe triac, the imbrication of these layers is such, that the device can be compared to a power monolithic integrated circuit. Figure A illUstrates a possible arrangement of the p and n regions (scale enlarged in the direction of thickness).
Layers P1 N2 P2 N3 form a thrystorTh 1 whose anode consists of layer P1, and the cathode, of layer N3.
Layers P2 N2 P1 N1 form a thyristor Th 2 with anode A2 on P2, which is, therefore and through the external metal connections, antiparallel connected with Th 1 as regards terminals A2 and A1.
Finally, layers P2 N2 P1 N4 form auxiliary element [' which couples gate G of the triac witb the cathode and anode gates of Th 1 and Th 2 in order to permit triggering of the triac in the various possible polarities of the gate and of electrode A2 with respect to electrode A1. Consequently, the triac can be roughly represented by the equivalent electrical schematic of Figure 1B.
Figure 1 : Structure of a Triac.
A : Example of a triac structure (vertically exaggerated sketch).
AI9
!
I
1
I1 I
.::.. :::.:~(Ol WI
P 1
P 1
1
(A 11
[ThIJ
(A 21
P 2
I
I P2
8 : Simplified Equivalent Schematic.
Al
G
C : Circuit Symbol.
D89AN301·01
At
Th 2
Th1
DB9AN301-02
A2
DB9AN301-03
2/22
--------------
1rt.."='!=1
SliG!rlSa©-I1m@H~~O[©~MOOS@ilOG©N'"
--------------
866
APPLICATION NOTE
With no pulse applied to the gate, the current cannot begin to flow spontaneously between A1 and A2. The triac is in the "blocked state".
The application of a current pulse to gate G causes Th1 and Th2 to change to the conducting state
(through auxiliary element fl, in accordance with
the polarity of the terminal voltage. Electrode A1 being taken as reference for the potentials, Th1 conducts during negative half waves (A2 negative with respect to A1) while Th2 conducts during positive half waves (A2 positive with respect to A1). The triac is said to be in the "conducting state" (refer to figure 3, P.7). When the gate current pulse is suppressed, for instance during a positive half wave, elementary triac Th2 continues to conduct and, consequently, the triac remains in the conducting state until the current decreases to almost zero, below the holding current of Th2.
1.2. OPEN-GATE STATIC CHARACTERISTICS
The study of the operation in conditions in which the voltages and currents change slowly, as in the case of a 50 or 60 Hz AC supply mains without any superimposed interference, can be carried out by starting from the IN static characteristics of the triac (plotted point by point or observed with the aid of a curve plotter) V (on the X-axis) is the voltage applied between main terminals A2 and A1, with A1 as reference, and I is the current flowing from A2 to A1 in the triac. The graph of figure 2 corresponds to the case where the triac is not controlled, i.e. where its gate is open (IG = 0). When a peak-amplitude alternating-current voltage Va lower than both VM in positive half-waves and V'M in negative half-waves, is applied to A2, current I always remains very low and, in any case, negligible when compared with the nominal operating current. The triac is in the blocking condition. When the load is a resistor R, its UV characteristic in this diagram is a straight line of slope 1/R, which moves parallel to itself when the instantaneous value Va of the supply voltage varies. The operating point moves along section A'A to the points of
intersection of the static characteristic of the trias in the blocked state, with the individual load straights corresponding to the various values of Va. However, when an overvoltage Vp higher than VM is temporarily applied to the circuit, the load straight can reach the position indicated by a dotted line, thus moving the operating point to B. Following the removal of the overvoltage, the operating point moves down along section CO of the static characteristic, where voltage V is low and the current high. Thus, this section corresponds to the conditions in which the triac is in the conducting state. It has been "fired" by overvoltage Vp. This hind of firing produces dangerous stresses in the triac and user circuit.
1.3. FIRING THROUGH GATE CURRENT
When a current IG is caused to flow between gate G and electrode A1, the blocking voltage decreases abruptly when this current reaches a critical value IG mini.
As long as IG is equal to, or higher than, IG mini, section MOM' of the characteristic of Figure 2 is replaced by section E'OE of the curve in dotted line (Figure 4), which joins together the "conducting state" characteristics O'x' Ox. Now, when the applied voltage varies from Va to + Va, the operating point describes curves C'C of these characteristics.
The current varies from IT to + IT and the voltage
across the triac varies from VT to + VT.
This voltage drop VT generally ranges from 1 to 2 V for a peak current iTeff -V 2 corresponding to the triac nominal current. Its maximum possible value VTM at 25°C is given for each triac in the applicable sheets of characteristics.
If IG is interrupted at instant t2 (Figure 3) when the instantaneous value of the current is still high, the operating point remains on the conducting-state characteristic drawn in full line on Figure 4, up to
instant b (point 0) when the current has decreased
to a sufficiently low value IH. The minimum anode current IH for which the triac remains conducting without gate current, is called holding current (or hypostatic current)' as in the case of the thyristors.
· As a matter of fact, there are two holding current values IH and I'H depending upcn the pclarity of V,. These two values are generally very close to each other.
--------------
&~ ..11
S[\jC]~S©J-i1l@H~~~O©lMiOOS@iOi:DN©~
3/22 --------------
867
APPLICATION NOTE Figure 2 : Triac Static Characteristics with Open Gate (not to scale).
A2
(flClng through breakover)
CONDUCTING STATE
A1
I
I (
I
, I
, I
I
~
,Va
, I
, I
I
IT
, , I
I
I
I
I
-=> '1Ta
I
1---------
v
D89AN30 1-04
IH is very low with respect to the triac nominal current (in the cold condition the maximum value of IH guaranteed by the specifications never exceeds a hundred mA, even for very large triacs; in the warm condition, the value of IH decreases considerably). Therefore, its influence on the operation as a switch does not have to be taken into consideration, as a general rule, in practical applications, except in operating conditions in which the load temporarily offers a high impedance at an instant at which the effective supply voltage is low.
The delay in the rise of the current following the application of the control does not exceed a few microseconds. But, to achieve steady firing, current IG must be applied for a sufficiently long time. The gate pulse duration must a least be long enough for a sufficient charge to be injected into the gate region. The minimum duration !J.. t of a rectangular-wave pulse of current IG having just the specified value IGT min is on the order of about
twenty /-ls. This required duration decreases when the value of IG increases.
______________ _4/_2_ 2 ____________ ~ i~@mgl'~9~
868
APPLICATION NOTE
If current Ic in the load does not immediately build
up (inductive load) it is necessary, in addition, to hold the gate current until the load has given pas-
sage to a minimum current IL. The 21atching cur-
rent" is equal to, or higher than, iH, depending upon
the respective polarities of A2 and G. It corresponds to point E on the conducting-state characteristic
(Figure 4).
Current IG applie dto the gate to fire the triac with either polarity of the supply voltage, can indifferently be of positive or negative sign with, however, triggering abilities which, for average-power triacs, can be somewhat different depending upon these polarities'. There are four possible cases which are determined in accordance with four "triggering quadrants" defined in Table 1.
Figure 3 : Waveforms in a gate-controlled triac with resitive load.
IG CONTROL CURRENT
____ ______________ ____ o~--~~------------------~~--
~
~
t 1
tl
v VOLTAGE ACROSS THE TRIAC
~Va
"-
/
I
\
/
'Ua /
\
/
/
/
o lr -----.-t~l.~\\~~~~~~v2T~/~/ ~~V~'T~~~~~~--------------Jf~----
: \
I
1\/
: '-,-/
I··
CURRENT IN THE TRIAC
Conduction ofTh2
I
I I I
I I I I I I I I I I
: Holding current
~OfTh2
____________ __ o ____
. ~
+-~~
~
- L_ _ _ _ _ _
, ____________ I '
__
~~
~~~
,
-- \ \ , , '
,,,,I
Conducted state
Blocked state
(Vr and IH exaggerated for clearness of figure).
D89AN3Dl·D5
Certain series are not specified in quadrat IV as regards firing current.
--
-----
---
---
~
~~~@m~~~~©~
5/22
--------------
869
APPLICATION NOTE
Figure 4 : Static Characteristics with IG = IGT (exaggerated around zero).
Steady firing pomt
________ ~~----------------------~~v
Load straight 1/R1 : ensures steady firing (iT> iL). Load straight 1/R2 : does not ensure steady firing (iT < IL).
D8gAN301~06
Table 1.
Triggering Quadrant
0.1 0.11 0.111 O.IV
Polarity with Respect
to A1
of A2
ofG
+
+
+
-
-
-
-
+
Firing Conditions for Small Triacs
IGT Low Medium Medium High
IL/IH ~ 1 2 to 5 ~ 1 1.5to 3
....,1 _61_22_ _ _ _ _ _ _ _ _ _ _ r=-= S~inC©IilSl@-Iml(~O~©IMI00S©UO\lJND~ -------------~-
870
APPLICATION NOTE
1.4. VARIOUS MODES OF CONTROL OF THE TRIAC
On Figure 3, instants t1 of gate current application were supposed to occur randomly with respect to input voltage Va. This operation is similar to that of an electromechanical relay; the difference, however, is that the triac switch becomes conducting at the precise instant (to within a microsecond) of application of the control, and blocks again, after the control has been removed, at the precise instant at which the current drops below IH (i.e. practically to zero with respect to the nominal current).
This precision can be made use of to carry out the control in exact synchronism with voltage Va, in order to sample periodically the voltage applied to the load over intervals of several half waves * (control by half-wave trains), or over half-wave fractions (control by conduction angle). By causing the respective durations of the "conducting" intervals to vary with respect to the "blocked" intervals, a variation of the power applied to the load is achieved.
Whenever permitted by the inertia of the user cir-
cuits, the control by half-wave trains offers substantial advantages when, in addition, the firing of the triac is allowed to occur only close to the point where the voltage across the triac goes through zero (i.e. just after zero crossing of the current). Since the triac will next stop conduction also at the zero crossing of the current, this mode of control always ensures a whole number of complete "conducting" half waves (Figure 5 a). On the other hand, triggering on going through zero eliminates any sudden variation of the current flowing through the load, which avoids parasitic radiations and strains in the triac and user circuits. With this type of control, the mean power allied to the load is merely:
n Ta P AV. = 2 T e VRMS olRMs (1 )
with: n = number of "conducting" half waves in each sampling period Te.
Ta = period of the mains current (20 ms in the case of a 50 Hz mains).
VRMS, IRMs = rms values of the input voltage and
current.
Figure 5 : Modes of Control of the Triac in Syncronism with the Mains Voltage (theoretical wav.eforms on resistive load).
1 - Triac controiled by ~ompletc hal!- waves
I I I I
Ucom ~I'=======::
..-1 Control sJ~na\
The tnac is triggered al !he Z2ro voltage pam',
and turns off at the lCro cur rent point
\/0 .... _ I I
I I I I[
D89AN301·07
Triac, controlled by conduction <1nC;le
adjustemenl of ""
1,J2 ~ duration of a half wave
~ ~ n· = phase shift of the trigger signal
~ trigger signal duration
Trigger signals in phase with the mains voltage
· The term « half wave" designates each (positive or negative) half of the mains current alternating wave.
D89AN301·08
----------------------------
~~~~@~~~~~©~
7/22
----------------------------
·871
APPLICATION NOTE
The fineness of adjustment of PAV obviously improves when Te increases with respect to Ta. A sampling period of 1 second permits adjustment in steps of 1/100. If the load does not not stand any dc component, it is necessary to add to the circuit a system of variation per couples of half waves (full waves) requiring, for the same fineness of adjustment, a double sampling period.
In many cases, however (for instance for light dimmers, for the control of highly loaded low-i nertia motors or for regulators with low time constant), it is necessary to sample the power at the frequency of the ac supply mains. To do this, it is only necess, ary to control the gate by current pulses occuring
with a phase shift (1t ex) with respect to the beginning of each half wave. Figure 5b illustrates the principle of this control, with waveforms obtained on resistive loads as well as a simple example of practical application. The conduction angle of the current is ex and the mean applied to the load is fairly equal to:
f P AV. = .1 (VRMS)2 ex sin2 ex. d ex 1t RL 0
or P AV. = 2 ex+ sin2 ex (VRMS)2
21t
R
Figure 6 : Triac Power Control.
8 Prmcip[p. of power control hy hrllf·w<1ve tmins (hurst contron
,f'I
I , , I
I
I ,
I I
,,...''I
J
I
I
I
n' conducting hatl waves
I
I
T e
fa I
I_----------~~----------~~
,,'11\
I I I I
, ,I
I
'J
D89AN301·09
RMS
l
12 10
, I
I ,
PAV/ P1800
1
V~
8
6
\ \,
-7
V
0,8
,, 0,6 I
4 2
o
o
--V 30'
~
0,4
"b2:........ 0,2 --. --- ~--.
. -- 60'
90· 120'
150
·
180 Conduction angle
In ful1line (right-hand scale) = Relative change of the power delivered to a resistive load RL
(operation at constant input power).
.
In dotted line (left-hand scale) = Change in the ratio IpliRMs of the peak current to the effectIVe
current on resistive load RL (operation at constant delivered current).
OB9AN301-10
:.v - - - - - - - - - - - - - - - _8/_2_2____________
~i§@m~m~alj
872
APPLICATION NOTE
Figure 6 b shows the change in the delivered power P as a function of conduction angle (1., when the input power is kept constant. As can be seen, the relationship between P and (1. is highly non-linear. To obtain a linear relationship between the mean vol-tage on the load and an adjustment voltage Vr, the latter must act on (1. with an inverse law.
Figure 6 b also shows (in dotted line) the curve of
the change in peak current Ip as a function of the
conduction angle with left kept constant, i.e. for a
constant power in the load. The curve clearly shows
the dangerous condition which exists in case of
operation at low power with a low conduction angel
when Ip exceeds the permissible repetitive surge
current.
.
1.5. OPERATION ON INDUCTIVE LOAD
In the case illustrated by figure 3, where the triac operates on a pure resistive load (cos <p = 1), the current reaches immediately the value VaiRL when the gate current IG is applied. This is a theoretical case, for the leads connecting the triac to the mains and load always offer an inductive component which slows down the rate of rise dildt of the current, and causes a slight phase shift of the instant of current interruption with respect to the zero input voltage point. With a load offering a high inductive component (cos <p lower than 1), inductance L limits the current rate of rise to:
di Va (3)
dt L
where Va is the instantaneous value of the input
voltage at the instant of application of the firing control. If the gate signal is applied for a duration which is long
with respect to that, Ta/2, of a ha~ wave of Va, the waveforms shown in full lines on figure 7 are obtained. Fol-
lowing a periodo of transition, current Ie reaches the value:
Va sin (wt + <p), with w= 211:
Lw
Ta
<p represents the phase shift of Ie with respect to Va, close to 12 when the load is highly inductive. After 11:/2 the control has been removed, the current is maintained in the load, as mentioned previously, until its instantaneous value drops below IH. But, due to phase shift <p, the value of the input voltage is different from zero at that instant. Consequently, the vol-tage across the triac increases suddenly up to value Va (close to Va), at a high rate of rise dVldt which is limited only by capactive elements possibly present in the circuit.
If the triac control had been removed at time 12, im-
mediately after reaching value IG (short-duration gate pulse), the current in the inductance might not have had the time to reach value IL of the triac latching current. Firing would not have taken place in a steady way, and the voltage would have increased again up to Va as indicated by the dotted lines on figure 7.
During operation on an inductive load with shortduring gate pulses, other unwanted conditions may be present when these pulses are applied at the beginning of each half wave of Va, within angle <po
Figure 7 : Waveforms with Inductive Load.
rot GATE CURRENT
o. ,.....11-----.1
11 ' 1'2
VOLTAGE
:
v ACROSS TRIAC
\
12 13
I" T
Conducting slate
- in lull line : long gate signal. - in dotted lines: effects of too short a gate signal.
DB9AN30H 1
873
APPLICATION NOTE
These conditions are represented by the full-line waveforms on figure 8: when the first gate pulse (a) appears, for instance at the beginning of a positive half wave, current Ic increases up to a value at least equal to that of the steady state current and, then, decreases again to a value below IH only after the time corresponding to angle <p during the next negative half wave. Since the new control pulse (a') already ends at t'2, i.e. prior to the cancellation of the current, there will be no gate current at 13 to fire agin the triac during the negative half wave. The next firing will not occur until t"1, through pulse a", during the subsequent positive half wave.
Thus, with this control, the triac behaves like a unilateral switch, conducting only on the positive half waves (similarly, if the first pulse (a) had appeared during a negative half wave, the current would pass only during negative half waves). This results in a rectifying effect introducing a high mean positive (or negative) current into the load. When the latter consists of a coil wound on a magnetic core with small air gap, or of a transformer primary coil, the operating point describes a large portion of the hysteresis loop. This presents the risk of creating a situation in which the core is almost satured, with the disastrous consequence of an extremely high surge current.
This abnormal operation woud not have taken place if the pulses had a duration equal to, or higher
than, that corresponding to angle <p, at the price higher control energy. The effect of the rectification phenomenon can suppressed through a powersaving means which consist in controlling the triac by pulse trains instead of only one pulse for each half wave. As a matter of fact, figure 8 shows (waveforms in dotted lines) that a new pulse (b')
occuring immediately after the current has been concelled, permits triggering again the triac during the negative half wave. There still remains a dissymmetry between the positive and negative current arches, but the rectifying effect can be considered negligible when the pulses are sufficiently closely spaced. The various modes of control illustrated by figure 5 in the case of a resistive load, can be used as well with an inductive load, provided the following precautions are taken: A) - For control by half-wave trains, the gate pulses should be centred around the zero point of the current that is to say when the voltage is re-applied. This permits ensuring re-firing of the triac immediately after the cancellation of the current (instant t"2 on figure 8). B) - For control by conduction angle, gate pulses of sufficiently long duration, or pulse trains starting from (1t - a) corresponding to the required opening angle, and ending toward the end of the half wave, should be used.
Figure 8 : Control by Wide Conduction Angle on Inductive Load with Short-Duration Gate Pulses.
GATE CURRENT
10
,
I
I "
1 I I 1 1 1
LOAO CURRENT
1
1\ 1 '
1 '.
1 "\ 1 "
1
"
:~:
1
1
1 1 1 1
- in full lines: Rectification effect due to the combination of a narrow pulse with a wide angle. - in dotted lines: Waveforms with two-pulse trains for each half wave.
D89AN301-12
-10-/2-2------------------------~~i~@~&'~~~I---------------------------
874
APPLICATION NOTE
2. SAFE-OPERATION PARAMETERS
The reliability of the triac is dependent upon a number of utilization precautions which cannot be taken without a thorough knowledge of the stresses or spurious phenomena to which the triac is liable to be exposed.
We shall examine the influence of thermal stresses and of current surges on its service life, and of overvoltages on its blocking capability. Finally, we
shall indicate a few means of protection against
these parasitic conditions.
2.1. THERMAL STRESSES
The data sheets give a limit value of the junction temperature: (Tj) max. When the effects of a hightemperature operating environment and of the increase of semiconductor self heating due to the dissipated power, cause the triac junctions to reach a temperature higher than (Tj) max, the result can be a temporary alteration of the performances, then a irreversible degradation gradually evolving to the complete destruction of the device when that situation remains unchanged for an extended period of time, or occurs repeatedly. Any degradation will be accelered in cases where an excessive temperature combines with other stresses (overvoltages, short spikes of current or of di/dt etc). In case where the occurence of such conditions in anticipated, appropriate measures have to be taken to keep the junctions at a temperature substantially lower than the maximum specjfied value..
Direct measurement of junction temperature Tj is hardly possible during operation. An approximation of its average value can be obtained from the case temperature tease, specified junction/case thermal resistance (Rth)jc and dissipated power PAV.:
Tj - Tease = (Rth j-c). PAV (5)
The data sheets often give curves of PAV versus condition angle ()(, showing a decrease of PAV, and consequently of the mean temperature, at small angles ()(. But, it is to be remembered that the instantaneous junction temperature at small conduction angles may rise substantially higher than Tj AV.
In case of full conduction, an excess value for the dissipated power can be easily calculated by considering that voltage drop VT in the triac is of the form:
VT = Vto + Rt.JT
In which Vto is the threshold voltage and Rt, is the dynamical resistance of the on-state characteristic. These 2 parameters are given in the data sheet of each part number. For a sinusoidal current ITAMS the power dissipation of the triac is: P = 2,121IT) ITRMS Vto + Rt.J~RMs
2.2. CURRENT STRESSES
In many practical applications the triac may have to withstand current surges. Let us mention more particularly:
- shor-circuits of the load,
- user circuits including a capacitive component,
- utilization with incandescent lamps (resistance when cold 10 to 20 times lower than when hot),
- utilization with coils wound on magnetic cores liable to saturation,
- spurious firing of the triac by high-energy overvoltages.
NON-REPETITIVE CURRENT SURGES
The dtasheet indicates a limit value ITsM for the peak of the non repetitive' current allowed to flow through the triac during one, half cycle of the supply mains.
As a general rule, this limit value is 6 to 7 times
higher than the nominal peak current ITM of the triac (i.e. 8 to 10 times higher than the nominal rms current). Most of the devices are capable of withstanding without destruction an even higher nonrepetitive current peak when its duration is lower than 10 ms. The specification give a limit value for the ex-
J pression i2dt for current surge durations ranging
from a few milliseconds to some ten milliseconds. This expression fairly well characterizes the operation of a cutout; its value is helpfull in selecting the "12t" of a fastacting fuse intended to protect the device against possible shor-circuits of the load. However, it should be used cautiously when the value of the permissible peak current is to be deduced from it, because it is only valuable to represent the surge capability of the triac for a given pulse duration within a narrow interval. For lower durations ranging from a hundred microseconds to a few milliseconds, the permissible non-repetitive current surge in the triac follows a curve closer to that given by the expression:
f i4dt = constant
as repsented on the theoretical curves of figure 9 .
·The device is supposed to withstand this non-repetitive anomaly alimited number of times (a hundred times, according to the JEDEC standards) during its lifetime
---------------
at='Y":l'
S[0G:[©S~m-~l~Hc:O'ifMOOS1llOj~N[~
11/22 ---------------
875
APPLICATION NOTE Figure 9 : Permissible non-repetitive current surge Ip in the case of a sine wave arch of duration '"C.
Ip/lTSM
o
by dl/dl (100A lrJac)
= Cons Will
- It-----~r-+---------~------~~~=--
(h)
D+--------4--------~----------~~------~6
10
100
10 3
4 2.10 4
fJS
D89AN301-14
Finally, for very short current-pulse durations, the permissible current surge is mainly limited by the rate of rise dildt of the current, which necessarily associated (figure 9).
The limitation by dildt occurs in a more critical way at the instant the triac is fired (willingly or accidentally) on a low-resistante load with low inductance. An examination of the waveforms of figure 3 shows that firing on a purely resistive load outside of the zero voltage point, entails an extremely fast increase of the current. Practically, there always exists, .fortunately, a small inductive component (due to the leads connecting the device to the mains and load) which limitis the rate of rise of the current. But, that rate of rise can reach prohibitive values at the instant the current reaches an high value due, for instance, to the presence of capacitances on the
triac terminals, or to a very low instantaneous value of the voltage (spurious firing by an overvoltage).
The harmful effect of a high rate of rise dildt can be explained, as for the thyristors, by the concentrations of current, and, consequently, by hot points, produced at the instant of the firing, due to the fact that firing first occurs in a very narrow region before spreading out over the full area of the junctions. Since the spreading speed of the conducting region increases when the gate current increases, the behaviour in the presence of non-repetitive high dildt values will be considerably improved when the triac is fired by a current IG rapidly reaching a high value.
-12-/2-2------------------------ ~~~~@~~~~9~---------------------------
876
APPLICATION NOTE
REPETITIVE CURRENT SURGES
Repetitive stresses with surge current values much lower than the limit value indicated for non-repetitive stresses can lead to an alteration of the triac performances as a result of the cumulative elevation of the instantaneous junction temperature which accompanies them. This is particularly the case when the triac operates continuously with a small conduction angle while delivering high power. This mode of operation corresponds to high peak currents during short periods of time. At the instant of each passage of the current peak, thereis a risk of the triac junctions reaching a prohibitive temperature. The knowledge of the global transient thermal impedance of both the triac and the heat sink, permits verifying that the instantaneous value of the junction temperature does not exceed (Ti) max. For very small conduction angles with a resistive or capacitive load, another limitation is given by the rate of rise dildt of the current in the repetitive state, as will be seen hereafter. The value of dildt repetitive is lower (in a ratio of 2 to 3, as a general rule) than the value of dildt specified for non-repetitive current surges. Such repetitive dildt values are particularly harmful when the circuit is capacitive. For asynchronous operation (figure 3) or for operation with a small conduction angle (figure 5b), it is highly recommended to connect a low-value resistor (a few tens of ohms) in series with the capacitances possibly present on the triac terminals. Operation with "zero voltage point" triggering (figure 5 a) does not give rise to any difficulty due to a repetitive dildt subce tge truac us fured at the precise instant at which the voltage, hence the current draw, is null. (but, non-repetitive di/dt values are still liable to occur when all the required precautions have not been taken for the avoidance of untimely triggering at instants at which the voltage value is different from zero).
2.3. BLOCKING CAPABILITIES
PEAK VOLTAGE AT BLOCKED STATE: VDWM.
In normal working conditions, with an input voltage of low frequency (lower than 100 Hz) free of strong parasitic transients, the triac behaves like an open circuit so long as no gate current is applied and that the ac voltage amplitude does not exceed the VDWM value guaranteed by the data sheet particular to this triac. That specified vol-tage VDWM is actually guaranteed for a value notably lower than VM and V'M (figure 2) throughout the authorized temperature range. For that voltage, the leakage current, "peak current in the blocked state", has a maximum value guaranteed at the maximum authorized temperature.
CRITICAL RATE OF RISE OF THE VOLTAGE IN THE BLOCKED STATE: "STATIC" dvldt.
During operation in the presence of parasitic transients, the triac may lose its blocking capabilities, even if the peak voltage of the transient does not exceed VDWM, but when its rate of rise dvldt is higher than a critical value. As a matter of fact, in such a case current CT dvldt developed across the spacecharge capacitance CT of the reverse biased junction with reverse bias in the blocked state, acts as a gate current liable to fire the triac. This susceptibility to steep voltage leading edges obviously increases with a higher sensitivity of the triac (low IGT) and a higher temperature of the semiconductor. The datasheets indicate a value of dvldt withstanding capability with a leading edge of 0.6 VDWM amplitude and with a junction temperature close to the permissible maximum. These values are typically on the order of a few hundreds of volts//ls for low-sensitivity devices and decrease down to some ten volts//ls for highly sensitive devices.
CRITICAL RATE OF RISE OF THE VOLTAGE DURING SWITCHING: (dvldt)c
The susceptibility to dvldt of the triac in the blocked state is based on the same phenomenon, and leads to values of the same order as in the case of the thyristors. However, in a conventional triac, the two elementary thristors Th1 and Th2 illustrated by figure 1 (section 1) being strongly coupled, one can expect reactions between these elements, which are liable to affect the blocking capabilities when the current cancels after each reversal of the input voltage polarity.
In extreme cases, this coupling can cause the triac to remain conducting without gate current, through the following process: when, following the suppression of the control signal, the current reverses in the load, for instance, by positive values (figure 11A), "internal thyristor" element Th2, which was in the conducting state, keeps stored charges. The discharge of these charges results in a reverse current (curve in full lines of figure 11 B) which can act as gate current for the other "internal thyristor" element Th1 of the triac and, thus, spontaneously fire the triac on the subsequent negative half wave.
However, the risk of spontaneous self-firing of the triac from one half wave to the other, exists only if the slope of the current decay (dildt)c at the instant of turn-off is too high.
With the usual passive loads of fairly linear IIV characteristics, the dildt at turn-off is proportional to IRMslTa. With a 50 or 60 Hz supply mains and a junction temperature lower than tvi MAX, the first unfavourable condition only arises, when the triac controls a very high rms current IRMs (high-power applications). However, there are risks of high dildt
____________________________ ~~i~~~g~~~~ _________________________1_3_/2_2
877
APPLICATION NOTE
* Figure 10 : Spurious re-firing by" commutating dv/dt" on inductive load (cos 1).
h l - - - - . . , . . . ......
O L -_ _ _ _ _ _ _ _ _ _~,-~~~-------
untimely
'\ firing
V81--/=- .....,
\ \
, of Th1
'", '-
\
__ oL=V=T ====\ \ =~~~~~
Jli.. _ 2It .IT
dt - Ta reverse
-,;
current of Th2
/---
IIe!!!.
\ ,-dt
,.I
'lJ"T
A : Application of the voltage at the instant of , commutation.
B : Exaggerated commutation region
D89AN301~15
values occuring on turn-off, even with effective currents of not very high nominal intensity:
a) when the frequency of the ac input voltage is much higher than 60 Hz
b) or when the triac switches the ac terminals of a single-phase rectifier with inductive load, or, still, in certain cases of switching on polyphase rectifers,
c) or, finally, after the passage of a high current surge, as can be the case when turn-on occurs on a load including a saturable core, or on lamps of very low resistance when cold.
However, on a resistive load there is a risk of spontaneous self-firing only when the junction reaches an instantaneous temperature higher than the specified limit value. (this situation can arise, for instance, following an overload, or when, through poor knowledge of the transiente thermal impedance, the user operates the triac at a small opening angle with high peak currents and a high case temperature). A second parasitic. phenomenon occurs when the load is an inductive one: since the inductive component of the load causes a phase shift of the current with respect to the voltage, the voltage across the triac tends to change, at the instant of
turn-off of Th2, from a very low value (VT at low current) to a high value which is the input voltage value at that instant (figure 10 A). The resulting voltage wavefront adds to the reverse current and additionnal current C dV/dt (in dotted line on figure 10 8) which contributes to the firing of the other element Th1. Conventionally, the immunity of triacs to self-firing is characterized by the value of dV/dt to be introduced by an inductive load at the instant of switching, in order to cause the spontaneous re-firing of a triac from one half wave to the other. This "com mutating dv/dt" parameter is generally given by the data sheets for a specified value of dildt on turn-off (as a general rule, the value corresponding to the nominal operating current at 50 Hz of the triac), and for specified values of the peak voltage and junction temperature (voltage VDWM and maximum permitted temperature, as a general rule).
In all usual circumstances, without turn-off dildt higher than the nominal value for the 50 or 60 Hz supply mains, the most appropriate precautions warranting the triac blocking capabilities at commutation, consist in selecting a device of not too high a sensitivity and, above all, in using a heat sink sufficient to prevent the instantaneous junction tem-
- - 14/22 - - - - - - - - - - - ~ ~~~@m~rtI~~91-------------
878
APPLICATION NOTE
perature from ever exceeding 80° to 90°C. An additional preventive measure in case of an inductive load is the addition, to the triac terminals, of an RC network limiting the rate of rise of the voltage. The dimensioning of such a protective network will be discussed later on. Spurious firing actions through dV/dt are detrimental to the triac only when the entail excessive overloads through surge current and di/dt.
3. APPLICATION EXAMPLES
The filed of application of the triac is extremely wide. As a matter of fact, it covers the control of all the equipment operating on alternating current. We shall merely give here the diagrams of a few examples of typical application, and recall, at the end of this note, the general precautions recommended for the utilization of triac (APPENDIX 1).
Before describing these examples, we shall add a few precisions of pratical order to the information given in Sub-section 1.3 about the control of triacs, by referring more particularly to Table I.
As can be seen on table I, the best gate sensitivity homogeneity with either polarity of the mains volt-
Figure 11.
age (applied to A2) is obtained in firing quadrants II and III, which corresponds to gate pulses of negative polarity with respect to A1 (figure 11 b). Recent triac control ICs are, generally, designed for this mode of firing.
But, when the latching current constitutes a critical parameter (operation at very low or highly variable current, or at low conduction angle on an inductive load), it is preferable to control the gate by alternate pulses in accordance with the mains voltage polarity (quadrants I, III, figure 11 a). The switches shown on figure 13 and 14, and the diac controllers which will be described in Sub-section 3.2 operate in these conditions.
When the control circuit does not directly deliver alternate pulses, or when the control power is insufficient with respect to the gate sensitivity of the triac to be used, there always remains the possibility of controlling that triac through low-energy pulses by inserting a sensitivie auxiliary static switch between A2 and G. Such a switch can consist either of a small triac (figure 12 A), or of a diode bridge switched by a sensitive thyristor (figure 12 B). Thus, the main triac will be fired in quadrants I, III, and its
Mains voltage a . Firing in quadrants I, III. b· Firing in quadrants II, III.
,
,
I
.,~,
~
(a) 7 -.0,l. III
,n ,~~
I
(0 I) I
0 ',
U I
(0111)
U
(b)~1
0: u .. IG
U I
(0111)
U (0.11)
U
D89AN301·21
Figure 12.
---JUL
Ig 1 k
A) 5 rnA control pulse
Bndge
---- TRIAC 19 ~ K 8) 0.1 rnA control pulse
D89AN30 1-22
--------------
tJr=..':Y:/-J=
SlIClU©S[R.l1@~H~[O©'iMirSn@iO!UN©®
15/22
--------------
879
APPLICATION NOTE
gate current automatically adjusted for the amplitude and duration required for steady firing of the triacs. 3.1. STATIC SWITCHES
The use of a triac as an "on/off" device in an alterning-current circuit represents the simplest application of that semiconductor switch. Such a utilization offers many advantages with respect to mechanical and electromechanical devices:
low control power with respect to the controlled power,
short response time on closing of the circuit, and absence of contact bounce,
possibility to select the firing instant within the phase,
in particular, possibility of firing at the zero voltage point, thus minimizing interference caused by the mains and environment,
no wear related to the number of switching cycles,
automatic breaking of the circuit at the zero current point, i.e. without arcing, even an inductive load.
MICROSWITCH-CONTROLLED STATI SWITCH (PERMANENT CONTACT).
With the circuit represented by the diagram of figure 13, the control energy is taken from anode A2 of the triac, i.e. directly from the mains power through the load, which permits providing a gate current of the
Figure 13: Asynchronous Triggering Through Microswith.
required intensity. As soon as triac T is fired, the voltage across it almost cncels, as well as the gate current which is thene exactly proportioned to achieve steady firing (R1 is of low value, 15 to 50 ohms, so that each re-firing after closing occurs near the zero voltage point, with a sufficiently steep leading edge).
"ON/OFF" SWITCH CONTROLLED BY MOEMENTARY-CONTACT SWITCH (fig. 14).
Closing of the "on/off" switch is controlled through a (momentary-contact) push-button switch M; operation is then ensured by the capacitor current which is in phase quadrature with the input Voltage.
Opening of the switch is then achieved either by short circuting between the control electrode and electrode "1" of the triac (momentary-contact switch A), or by opening the gate circuit.
STATI SWITCHES CONTROLLED AT THE "ZERO VOLTAGE POINT"
To meet the requirements of the standards concerning the limitation of interference injected into the mains through electrical house appliances, it is necessary to eliminate any sudden current surge at each firing and re-firing of the triac.
With single-phase voltage and a purely resistive load (cos cp = 1), this is achieved by firing the triac with pulses centred on the zero crossing of the mains Voltage. But, with a phase shift cp between
Figure 14 : Setup of an «On/Off» Switch.
I lk
220V
nov
rv
!
1
D89AN301-24
T = triac or alternistor
(C =0,1 (IF; R1 =33 n ; R2 = 100 Q)
D89AN301-23
load current and mains voltage (inductive load or polyphase circuits), it is absolutely necessary to synchronize the gate pulses with the voltage across the triac (see SUb-section 1.5) and not with the mains Voltage.
STATIC RELAY INSERTED ON ONE LEAD.
The switche shown by figure 13 can be inserted on one lead, without access to the other mains pole.
But, it cannot be directly used for the synchronization on a zero crossing of the AC voltage. However, it is possible to set up a static relay with zero-point firing, in accordance with the same principle of gate current supply from the voltage across the triac, by replacing the mechanical contact with the arrangement shown by figure 12 B, and by controlling the sensitive thyristor through a photocoupler (fig. 15).
______________ _16_1_22____________ ~ ~~©mU~~9~~
880
APPLICATION NOTE
The triac gate pulse is provided by the thyristor. Transistor Tr enables inhibiting firing of the thyristor depending on the instantaneous amplitude of the mains voltage and the photocoupler control. If the photocoupler is not supplied, transistor Tr is continuously saturated. It prevents firing of the thyristor.
When the photocoupler is controlled by the voltage divider consisting of resistor R1 and R2, transistor Tr is blo.cked only when the mains voltage is close to 0 V. The triac is then controlled at the mains zero voltage point.
Figure 15.
Th TL 106
TRIAC
,]b
220V
~~~~i:5
D89AN301 -25
STARTING OF AC MOTORS (figure 16). The triac is controlled by means of two zener diodes which detect, on the secondary side of a current transformer, the current surge due to the starting of the motor. The semi-conductor device operates
Figure 16 : AC Motor Starting Control
only during the time required by the motor to reach synchronism. Consequently, it is not necessary to use a large heat sink. Butthe compromise between I, R and the transformation ratio of TI has to be correctly adjusted.
If
I
220V
"r-' :::
I
0
I
I
· I
01 02
starting winding
o.\dl\lng
ccoacltor
R
TI : Current transformer 01, 02 : 12 V zener diodes BZV47C12
D89AN301-26
---------------------------~~i~©~g:i9~------------------------1-7-/2-2
881
APPLICATION NOTE
3.2. POWER CONTROLLERS
The systems for burst or phase control mentioned in Sub-section 1.4 (figures 5 and 6) are used to vary the average power delivered to a load (lamp, motor, heating elements, transformers etc).
We shall give the diagrams of a few power controllers as examples. By feeding back to their control terminals the information provided by suitable sensors coupled to the user circuits, it is possible to make up lighting, speed, pressure, temperature, voltage or current regulators.
OIAC CONTROLLERS.
This is the simplest method for power variation through phase control. In spite of its lowe accuracy, this method is applicable without particular difficulty for power control on resistive loads, or for speed variation of small motors.
To ensure a satisfactory adjustment range, and improve the reversibility of the adjustment, it is advisable to complete the circuit shown by figure 5 b, by an additional RC network, known as "antihysteresis" network (6.8 kQ and 100 nF on the light dimmer diagrams of figure 17).
Slave control of the phase angle by the ambiant lighting, or by an external light phenomenon bay be required to ensure a constant illumination level. With the circuit shown by figure 25 a, this will be achieved by connecting a photoresistor in parallel with the phaseshift capacitor for varying the charg-
ing voltage of the latter in accordance with the illumination level.
A variation of the luminous flux of a fluorescent strip light can be obtained in the same manner. This is a particularly attractive application, since the colour of the visible light produced by a fluorescent lamp is almost entirely independent of the luminous intensity, which is not the case with incandescent lamps. With the set-up shown by figure 17 b, highly progressive intensity variation is achieved over a wide luminosity range by connecting the triac in parallel with the fluorescent lamp. Thus, the lamp conduction angle corres-ponds to the triac off-state angle and, consequently, commences at the beginning of each mains voltage half wave.
Figure 18 illustrates a circuit used for speed control of a fan drive motor. Since this type of motor generally comes to a stop long before the conduction angle has decreased down to the triac turn-off point, no antihysteresis network is required. A limitation of the speed adjustment range (resistor R3, possibly adjustable) may be sufficient to avoid hysteresis problems.
However, in this example a partial anti hysteresis effect is accessorily produced by the circuit consisting of R1, R2 and dioded 01,02, the main purpose of which is to linearise the speed adjustment and, above all, to render it substantially independent of mains voltages variations.
Figure 17 : Luminosity Adjustment of an Incandescent (a) or Fluorescent (b) Lamp.
(8)
BALLAST'
,,,
220 V
rv
I F ,
, I
I
O---------------____--J ,I
(b)
D89AN301 ·27
882
APPLICATION NOTE Figure 18: Motor Speed Adjustment with Compensation of Mains Voltage Variations.
(01, 02, 03 = diacs 083)
D89AN301·28
3.3. SWITCHING OF TRANSFORM ERS
As a general rule, the switching of taps on the secondary does not give rise to any particular overload difficulties: it is only necessa:ry to comply with the previously given instructions relative to thermal dissipation (sub-section 2.1), and operation on inductive load (Sub-sections 1.5 and 2.3), particularly when the load on the secondary is a rectifier. When switching the primary connections (figure 19 a), applying power at a random instant can entail destructive current surges. Such current surges have two origins:
building up of the magnetizing current to a value twice that of the transformer nominal current,
remanence of the magnetic circuit consecutive to the preceding turn off, which can lead to its saturation when power is applied.
To avoid these two difficulties, it would be advisable to control the triac at the maximum of the supply voltage, and at a polarity of this voltage opposite to that in which the transformer remained at the preceding turn-off. Unless the switching of the primary of a transformer of very high induction is concerned, such a sophisticated control circuit is
not required, as a general rule, and the following recautions may be sufficient:
In the case of phrase control, or when there are no difficulties due to interference from the environment, proceed to a starting up at progressively increasing conduction angle. Figure 20 illustrates the example of a simple controller. Progressive energization is achieved at the opening of switch S through the charge of capaCitor C (2 to 10 IlF, 100 V), potentiometer P is used for ower adjustment in normal operation.
For on-off control at the zero voltage point, carry out the first firing of the triac at the beginning of a half wave whose polarity is opposite that of the half wave at the end of which the triac has ceased conducting.
In any case, these cares will be illusory if no precautions (as described in sub-section 2.4) are taken against untimely triac firing on violent interference or mains overvoltages occuring at any instant. Anyway, it is recommended, for these applictions, to use preferably "alternistors" of a rating overdimensioned with respect to the continuous-duty nominal current, and to protect the circuit by means of fast-acting fuses (refer to sub-section 2.2).
--------------
t>~ .'1/l
SGS-moMsoru UljJD©i&(g~~~©'iTIB(QJmJ©®
19/22
--------------
883
APPLICATION NOTE Figure 19 : Switching with Triacs on the Primary (a), or Secondary (b) of a Transformer.
a
--
b
Figure 20 : Diac Controller with Progressive Energization of the Transformer.
DB9AN301-29
Fast-acting fuse
220V
-Pt:::r S
~
Application of power
DB9AN301-31
20/22
-----~--------
.~ ...."
S~O©Gl1SI@·~1[lHJ<O©1lM1lSI@iOlDN©®
--------------
884
APPLICATION NOTE
CONCLUSION
The triac is a AC switch which changes from the blocked to the conducting state when a current or current pulses of any polarity are applied to the control electrode. Turn-on of the device can be achieved with precision in synchronism with the AC input voltage, while turn-off occurs when the current passes through zero following the control signal removal.
This permits setting up systems for the switching, variation or regulation of the power delivered to any load (lamp, resistor, transformer, motor). Provided
an appropriate heat sink keeps the junction temperature below the specified maximum value, the service like of the triacs used in these systems is almost unlimited.
Owing to the remarkable overloads capabilities of the triacs, users will but exceptionally experience difficulties as regards the reliability of these devices. We have insisted on the various cases of applications requiring particular precautions, in order to give all the information necessary to solve possible problems in the best possible way. Appendix I sums up all useful instruction, in relation with the parameters specified by the individual datasheets.
___________
"'"='"11=
SIloGiJOS©O-OT@~~H~©Oli'MOO@SillOO©iN\l
21/22 --------------
885
APPLICATION NOTE
APPENDIX RELATIVE CONSIDERATIONS TO A FEW TRIAC UTILIZATION PARAMETERS
Parameters
1) Thermal Stresse ITRMS: Triac Nominal Current (rms current at 80°C case temperature). RlhQc): Junction/case Thermal Resistance; see Sub-section 2.1
To be Particularly Consideredfor
Continuos Operational ITeff in High Ambient Temperature tamb
Precautions to be Taken (together or separately)
Suitable Heat Sink Its thermal resistance with respect to tamb should e at the most:
Permanent Operation at Small
Conduction Angle, with High Peak Currents
Tj - tamb - Rthdc) - Rtj(cd) P
Operation with High-frequency ac Input Voltage
2) Current Stresse ITSM: non repetitive peak overload current (peak current permissible during one period only) di/dt: critical rate of rise of the current at turn-on; see Sub-section 2.2
- Capacitive Load (or capacitor across the triac terminals) - Utilization on Incandescent Lamps (high current inc old condition)
- Windingson Saturable Core" transformer primary (magnetizing current) - Risk of Short-circuit on Load - Risk of Untimely firing occuring on overvoltages (see 4) below
With: P = Dissipated power: fig. 3, 4 Tj = max. permissible junction temperature: see Sub-section 2.1 and 4) below (untimely firing)
- Inductive Circuit (addition of L higher than a few hundreds of [lH); see figure 13 - At least 30 Q in series with possible capacitor - Triggering at zero voltage point - Triggering through gate pulse of steep leading edge, with peak much higher than specified IGT - Non-delayed fuse rated for less than 2/3 of triac ITeff
3) Holding of Firing Instantaneous output value (current in load) below which the triac turns off (IH) or does not steadily fire (IL) after the removal of the gate current (see Sub-section 1.3) a) at End Conduction: holding Current IH b) at Beginning of Conduction: Latching Current IL
- Highly Variable Loads (low currents) - Highly Inductive Loads (see fig. 7) - Presence of an LC Resonant Circuit (for instance, underdamped interference filter)
- Long trigger pulse or long trains of closely spaced pulses - RC network across triac terminal (see fig. 15) - Triac of Low IH (sensitive series)
4) Untimely Firing a) Firing through breakower (through momentary over-shooting
of the maximum specified voltage VDMW; see sub-section 2.3) b) Firing by dv/dt (critical rate of rise of the voltage in the blocked state-parasitic triac firing, without gate signal, by a voltage wavefront acting on the triac terminals c) Commutating dv/dt (critical rate of rise of the voltage at commutation-see fig. 11); spontaneous triac re-firing through the voltage slope on inductive load at the end of a current half wave
- High Mains Interference - Atmospheric Interference - Commutator-type Motors, intermittent contacts
- Under-dimensioned heat sink - High Input Voltage Frequency - Forced commutation, rectifiers switch inductive load
- Limit Junction Temperature (largely dimensioned heat sink); - ALTERNISTOR - RC Network on Triac Terminals
-22-/2-2------------------------ ~~ii@~~~~~~~---------------------------
886
APPLICATION NOTE
APPLICATION NOTE
THYRISTORS AND TRIACS, AN IMPORTANT PARAMETER: THE HOLDING CURRENT
By E. Leblanc
The purpose of this note is to familiarize the user of a triac (or a thyristo r) with the param eter IH : hypo· static current or holding current.
After a short definition, we will illustrate the importance of this parameter by concrete examples. Then we will describe how to measure it and finally its variation with the conditions of use and the sensitivity of the components.
In all cases we speak of triacs. However, the statements are also valid for thyristors.
DEFINITION
To keep an electromagnetic relay in the conducting state, it is necessary for a minimum current to circulate in its coil. Otherwise it would return to the blocked state. The same phenomenon can be observed for a triac. This minimum current which keeps the triac conducting is called the hypostatic or holding current (figure 1).
Figure 1 : Controlled by gate pulse IG, the triac is fired and a current IT flows through it, fixed by the main circuit. When the current IT falls below the triac hypostatic current IH, it is reblocked.
G
AN302/0289
: Reblocking of the triac
D89AN302-01
116 887
APPLICATION NOTE
APPLICATIONS Example 1 : Light dimmer (figure 2). Figure 2: Dimmer with Interface Suppression Coil and Capacitor (RFI filter).
Load
220 V
~
C
nlerference suppression LCfilier
D89AN302·02
Figure 3 : Current in the dimmer triac: The interference suppression filter produces oscillations. If 10> IH (as in the figure) the triac remains fired. But if 10 falls below IH, the triac will be blocked.
Example 2 : Motor Control (figure 4).
Figure 4 : Control of a Small Motor by Triac.
o
Induction motor
If the coil is a poor quality one, the oscillation is insufficiently damped. If the current in the triac falls below the hypostatic current, IH, this results in untimely blocking of the triac. It is fired at the next current pulse IG and is blocked again. The lamp flickers. This is known as the "flicker effect".
How can it be prevented? By eliminating the cause, i.e. using an appropriate interference suppression filter which does not produce extensive oscillations, and then by choosing a triac with a lower hypostatic current IH.
SGS-THOMSON Microelectronics has developped a triac specially designed for applications where a low hypostatic current IH is required, the BTA 06 400 GP.
This device is specified with a maximum holding current IH of 13mA in both current flow directions.
The designer wishes to control a small high-impedance motor (25000hms for example) by triac. He obtains the parts and an operating manual and carries out tests. The circuit operates smoothly. After one year of production, the manufacturer complains of low torque in his motor and blames the triac. What's happened?
_2/_6_______________________~~L ~i~@~~~~~~~~-------------------------
888
APPLICATION NOTE
Figure 5 : Voltage Accross the Triac and Current in the Circuit of Figure 4.
I~'"
I
v I I
, ' \
\ \
I
\
I
I ~IH+
"
, ,
\, ~IH--
,
I \
I
\
I
,
~
--'
T
D89AN302·05
The circuit was designed with a type of triac whose maximum specified holding current IH was 50mA. But the components used for the tests were more sensitive: IH + = 13mA and IH - = 8mA and the designer based his choice on these results. After a year of delivery, the component manufacturer continues to deliver parts which are in conformity with the spe-
cification but less sensitive: IH + =40mA and IH - =
20mA. The conduction time decreases (figure 5), the dissymmmetry is greater, a DC component appears and the motor loses torque.
To prevent this kind of difficulty, when designing the circuit it is thus necessary to take into account not the typical value of the sample used but the maximum value specified by the component manufacturer.
Example 3 :
Take the diagram of the previous example (figure 4), the control of a small high-impedance motor by triac.
This time, the designer selects a triac with a lower maximum specified holding current, IH. The motor seems to operate without problems. The motor is meant for mounting on out-door equipment. The equipmynt is installed in summerandworkswell. But in winter, the fault described above occurs. What has happened? The designer studied the operation of his circuit at an ambient temperature of 25°C. But the holding current IH varies with the temperature: when the temperature decreases, the holding current increases (we will study this variation in paragraph 4.6) and the phenomenon described in example 2 occurs. Thus when designing a circuit which is to operate at low temperatures, it is essential to take into account the corrected value of the holding current and not its value at an ambient temperature of 25°C.
These three examples illustrate the importance of this parameter and the different problems it can cause in a circuit if it is insufficiently known.
If the device is to remain in the conducting state, it is imperative that the circuit in which it is used ensures a current higher than the holding current IH of the device.
In our data sheets, for all the types of triacs, the hy, postatic current IH is specified as a maximum value. A suitable triac should then be chosen whose holding current IH is lower than the minimum value of the current in the circuit, if the triac is to remain in the conducting state; make the necessary corrections to compensate for temperature variations.
MEASUREMENT OF THE HYPOSTATIC CURRENT IH
Pushbutton P is used to fire the triac. The value of current IT is chosen much higher than the latching current. By increasing the value of the variable resistor R, current IT will decrease. The value of the hypostatic current IH is the value of IT read just before the triac is blocked.
The hypostatic current IH is always measured with the gate unconnected, i.e. disconnected from the trigger circuit. Only sensitive thyristors (IGT ~ 500f,lA) are measured with a 1kohm resistor connected between gate and cathode.
Forthe measurement to be regularly repeatable, the triac should be suitably fired. The following rules should be observed:
- Before decreasing current IT, it should be equal to at least 5 times the triac IL current.
- - - - - - - - - - - - ' - - - - -.r.".="1-1= SIlG:Si.mn©tOOOM@~S~OINl:©"JOO@~~C©ill--------------3/-6
889
APPLICATION NOTE
Example: BTA 12 600C
IL typ (01 and III) = 20mA thus IT = 500mA.
- if the IH current is measured by pulses (automatic testers, for example), the triac should consult for at least 500IJS before performing the measurement.
For a triac, the IH current has two values: (IH +) when electrode A2 is positive with respect to electrode A1 and (IH -) when electrode A2 is negative with respect to electrode A1. In the documentation only one value is given for both quadrants. This value is always the maximum value.
Example: BTA 12 600C : IH max = 25mA.
Depending on the production batch, IH can vary. However, the dispersion remains below the limits specified in the catalogue.
To give an idea of this dispersion:
- Sensitive triacs : IGT (01) 5mA (type T) 2mA::; IH ::; SmA (Specified IH max : 15mA). - Standard triacs : IGT (01) 50mA (type B) SmA::; IH ::;40mA (Specified IH max: 50mA).
Note: The minimum value of the IH parameter is never specified in the data sheets.
Figure 6 : Circuit for Measurement of the Holding Current IH.
VARIATION OF THE HOLDING CURRENT, IH a) Variation of current IH with the sensitivity ofthe devices and the direction of conduction (typical value)
For low components (thyristors and triacs whose rated current is less than 60A), the hypostatic current, IH, is related to the firing current, IGT (see figure 7).
Figure 7 : Ratio between the Holding Current, IH (A2 +) and Current IGT (01) for Sensitive and Standard Triacs.
IH +/IGT (01)
Sensitive triac 6 Arms (T type)
3
Standard triac 12 Arms(C type)
1.5
Example 1 :
BTA 06 600T: if IGT (01) =1.5mA then IH + =4.5mA. BTA 12 600C : if IGT (01) = 10mA then IH = 15mA.
G D89AN302·06
In the case of the triac (as distinguished from the thyristor) it is important to note that current IH - (electrode A2 negative with respect to A1) is generaly lower than IH + (see figure S).
Figure 8 : Ratio between Holding Current IH + . (A2 +) and Holding Current IH - (A2 -) for Sensitive and Standard Triacs.
Sensitive triac 6 Arms (T type)
IH + I IH 1.2
Standard triac 12 Arms (C type)
1.2
Example 2:
BTA 06 600T : if IH + = 4.3mA, IH - = 3.SmA.
BTA 12 600B: if IH + = 15mA, IH - = 12.5mA.
_4/_6______________________~~l ~~~@~~l~~©~------------------------
890
APPLICATION NOTE
b) Variation of the hypostatic current, IH, with the junction temperature:
The value of the hypostatic current is physically related to that of the firing current, IGT. These two parameters thus vary with the junction temperature in accordance with an analog law (see figure 9).
Example: Triac TO 220, type BTA 12 600C
IH = 20mA at Tj = 25°C,
thus IH = 14mA atTj = 110°C.
Figure 9: Relative Variation of the Holding Current IH, with the Junction Temperature, Tj (typical values).
IgtiTjJ
.lh(Tj]
Igt(Tj-25'C] Ih(Tj-25'C]
2.5
2 I'"
'"I'"
I
Igt
p, 1.5
r---~
l -I - Ih
~
0.5 1 J
f":: f:::: :::::: c:: ---- ---
Tj ('C)
o
-40-30-20-10 0 10 20 30 40 50 60 70 80 90100110
D89AN302-07
c) Influence of the reapplied voltage:
The rise time and the level of the reapplied reverse voltage across the triac after blocking have no influence on the value of its holding current, IH.
d) Influence of the external gate cathode resistor, RGK
The user can wire a resistor, RGK, between the gate and the cathode of the component, either to improve its behaviour under voltage at high junction temperatures (by-pass for leakage current) in the case
of sensitive thyristors, or because it forms part of the fliring circuit. This resistor has an influence on the holding current, IH, in different proportions depending on its resistive value and the sensitivity of the components:
1 - Sensitive thyristors (IGT:'; 5001lA) Resistor RGK connected between the gate and the cathode (figure 10) has an important influence on the IH parameter of sensitive thyristors. For certain applications, the designer would be well-advised to define a high impedance control circuit.
Figure 10: Variation of the Hypostatic Current, IH, of a Sensitive Thyristor (e. g. TLS 106-6) as a Function of the Gate-cathode Resistor (typical values).
5.5 F===1=t+tk=---l-I+ll--t-H-Il---l-.J-j.-Jj
5r---t-rtir--~~~r_--+_~~---+-+~
4.5 r---t-rtir---+-+"kIr_--+_~~---+-+~
A
3.5 1-----t-t-t1t--t-+H+-"~,+++i+---+--l-+H
3r---t-rtir---+-+~r_~~~~---+_+~
2.5 I---t-rtir---+_+~t---.p.d-l~---+_++H
21---t-rtir---+_+~t---+_~~---+_++H
1.5 1---t-H-tt-----t-+Ht------+-++11r-,..k:----H-+-H
1 1---t-rtir---+-++1t---+_~~'~~ ~~+H
.51---t-rtir---+-+~r_--+_~~--_+_++H
o o o
RGK (fl)
Note: The hypostatic current for sensitive thYristors IS always specified for RGC = 1000ohms.
Sensitive thyristor
DB9AN302·0B
-------------!~l ~~~~~~~~~~~-----_------5-/6
891
APPLICATION NOTE
2 - Standard thyristors, sensitive and standard triacs
A resistor between gate and cathode on one of these components has no significant influence on the value of its holding current, IH (on condition that it is not too low, RGe > 200hms).
e) Note:
We have seen that the more sensitive the triac (Low IG), the lower the value of the holding current, IH. Now, in certain applications, a sensitive triac (direct control by integrated circuit) with a high IH (or IL) may be useful.
In this case, the circuit of figure 11 could be used. The assembly is sensitive but has a higher hypostatic current.
Figure 11 : This Component, a «DARLINGTON TRIAC., combines a High Sensitivity with a High Hypostatic Current.
T1 : standard triac e. g. BTA 12 600B IGT (01) ~ SOmA
IH+ ~SOmA
T2 : sensitive triac e. g. TLC 336T IGT (01) ~ SmA
IH + ~ lSmA
D89AN302·09
CONCLUSION
The choice of a thyristor or a triac does not depend only on the voltage, the rated current and the sensitivity. Other parameters should be taken into account. The hypostatic current, IH plays an important role in many circuits. The value of this parameter varies with:
_ dispersion of characteristics at manufacture,
_ temperature,
_ eventually the control circuit (in the case of sensitive thyristors),
_ the direction of current flow.
Taking into account these elements, the designer can obtain satisfactory operation of his circuit in industrial real life applications.
Knowing the problems which could be created by this parameter, SGS-THOMSON Microelectronics has introduced a new triac, BTA 06 400 GP, now available for the designers. Its low holding current, specified with a maximum value, enables it to be used in most applications.
_6/_6_______________________~~l ~~~@~2~~~~©~-------------------------
892
APPLICATION NOTE
LATCHING CURRENT
An important problem concerning the utilization of components such as thyristors or triacs is the holding of the component in the conducting state after the trigger current has disappeared during firing. Very often, the firing problems supposedly due to the gate current IG or to the firing time tGT are in reality due to the latching current IL. After a definition we will illustrate the importance of this parameter by concrete examples. Then we will describe how to measure it and its variation according to the utilization conditions of the components.
By E. Leblanc
The study will be based on the triac. The points treated are valid for thyristors (except for the various conduction modes).
DEFINITION
The latching current, IL, of a triac is the minimum value of the main current (current flowing between electrodes A2 and Al) which enables the component to remain in the conducting state after the gate current IG has ceased (Figure 1).
Figure 1 : Controlled by the gate pulse, IG, the triac is fired, and a current IT flows through it, imposed by the main current. If the gate current IG is stopped before current IT reaches the value of the latching current IL, the triac is blocked (as shown in the figure).
Gate current IT
".
".
IL
".
, ". "'
Main current
AN303/0289
RL
IG
(T A2
A1 G
Da9AN303·01
1/10 893
APPLICATION NOTE
APPLICATIONS Example 1 : Control of a low power signalling lamp by triac. Figure 2 : Control of a Low Power Signalling Lamp by Triac.
Lamp(10 W)
220 V A:;I--
Main current
-,
/
\
I
\
\
I t
/ /
Current in the main circuit of the triac and gate current. The lamp power is too low (eg. : P s; 10 Wand the triac BTA 12.400 B) to impose a sufficient current (shown in dotted lines in the diagram) in the triac to keep it in the conducting state after interruption of the gate current IG. The triac does not conduct.
A BTA 12.400 B triac is used to control the flashing of a 10 W signalling light. The peak current in the circuit
b1G
Gate
current +-'-___--'-0--'--______
D89AN303-02
will therefore be 65 mAo This value is very close to that of the typical latching current given in the data book for this type of triac: 50 mA (quadrant 1, 3 and 4). Thus the user's case could be that described in figure 2, that is, a triac whose latching current IL in the first quadrant is equal to 70 mAo His triac will never be fired. For correct operation, the user should thus employ a sensitive triac (e.g. T08-6A IL : 8 mAl.
_2/_10_______________________~~l ~~~~~~~~~~~~-------------------------
894
Example 2 : Control of an inductive load by triac, Figure 3 : Voltage Accross and Current Through the Triac.
M
APPLICATION NOTE
G Control of an AC motor by triac
- - - - - - - - - - - - - -j
Gate current
VT
I
I
I
I
Voltage across the triac
IT
, IL4----------------r------'",.--
Current through the triac
\
-- \ ,,
D69AN303-03
In continuous lines : short gate signal : the triac does not remain in the conducting state because the main current did not reach the value of the triac latching current before suppression of the gate current.
In dotted lines: long gate signal: the triac is fired and remains in the conducting state until its current falls below the holding current IH after suppression of the gate current IG.
--------------~"'!L ~i~mVrr'~~~~~-----------3-1-10
895
APPLICATION NOTE
On a highly inductive load, the inductance limits the current rise time to :
dlT
Va
d,
L
(Va: power supply voltage at the time the gate signal is applied; L : load inductance).
Consider the operation on one full-wave of the power supply voltage. If the duration t1 of the gate current pulse IG is very small compared with a halfwave of the power supply voltage, the triac current cannot reach the triac latching current level in the firing mode considered (here the 1st quadrant). Thus firing will not take place and the voltage across the
triac increases. For triggering to be steady, the duration of pulse t2 should be long when compared with a half-wave of the power supply voltage. The current set up in the triac is imposed by the load impedance. The triac remains in the conducting state until the current falls below the holding current IH. It is blocked if the IG current pulse has ended.
Another method consists of applying a train of closely spaced pulses to the triac gate instead of a square wave.
The SGS-THOMSON Microelectronics applications laboratories have developed a number of triac control circuits, specially designed to work on inductive loads (see bibliography, ref. N° 1).
Example 3: Control by triac of a load whose power varies considerably.
Figure 4 : Control of an Arc Welding Set by Triac.
The designer of an arc welding set whose power is adjustable by triac, chooses a component capable of controlling high currents. Forexample, if the maximum current to be controlled is 40 Arms, the designer, for safety, will choose a triac rated at 60 Arms, thus a triac with a high latching current. Now, offload, the transformer magnetizing current could be very low or even below the triac latching current IL in one of the quadrants. This means that the triac could fire correctly in the first quadrant and then not fire if the next firing is to take place in the second quadrant where the IL is much higher. A considerable unbalance then occurs, generating a DC cur" rent heating the transformer and preventing the equipment from operating correctly.
Since the latching current IL increases with the size
D89AN303·04
of components, and thus with their rating, the user would thus be well advised not to select an excessively high rating for his triac in order to have the lowest possible latching current.
A.N : For this type of application, the SGS-THOMSON Microelectronics applications laboratories place at the disposal of designers a number of schematics meant for this type of circuit (see bibliography, ref. N°1).
These three examples illustrate the importance of the IL parameter and the problems that it can cause in a circuit. To ensure stable firing of a triac or a thyristor, it is absolutely necessary for the circuit which is controlled to impose a current which is higher than its latching current.
_~_10______________________~~L ~i~~~~~~~~~~------------------------
896
APPLICATION NOTE
FAVORABLE EFFECT OF AN RC CIRCUIT ON THE FIRING OF A THYRISTOR OR A TRIAC
In most inductive load applications of triacs or thyristors, the user connects an RC network between the anode and cathode of the device to eliminate the
risk of premature firing by transients or spontaneous firing by (dv/dt)c (case of triacs) (see figure 5). Capacitance C and the load impedance attenuate steep voltage transients transmitted by the mains or resulting from switching inductive loads.
Figure 5 : Reducing the Risk of Untimely Firing on Inductive Loads: the RC Circuit (called" Snubber»).
_I
D89AN303·05
This RC network has also a second advantage. In fact, the energy accumulated in capacitor C after turning off is fed back to the triac when firing. The speed at which the current increases in the triac during discharge of the capacitor is then limited only by the peak charge voltage of the capacitor and the in-
ductance of the circuit connecting the SNUBBER to the triac. The current amplitude is the quotient of peak charge voltage of the capacitor by the series resis-tance R. This circuit thus helps the current to rise very quickly above the latching current IL of the device (see figure 6).
Figure 6 : Favorable Effect of the RC Circuit for Firing on a Highly Inductive Load.
IT1 +-----.,-......,--
IL current level
/
/
dlT/dt
I : current in the load Ic : discharge current of capacitor C IT : I + IC : current in the triac
Note:
D89AN303·06
When using an RC circuit, it is not advisable to work with aseries resistance R which is too low. In fact, the combined
effect during firing of Jr, (figure 6) (equal to the quotient of the capacitor peak charge voltage and resistance R)
and the current slope dlTfdt (equal to the quotient of the capacitance charging voltage by the inductance of the connection between the triac and the RC circuit) could be dangerous for the triac. A value for R higher than 100 ohms is recommended.
--------------~~l ~~~~~~~~~~~~------------5-f1-0
897
APPLICATION NOTE
LATCHING CURRENT (IL) MEASUREMENT Figure 7 : Latching Current (IL) Measurement Circuit.
V=
v ±12V
D89AN303·07
The closing of contact C enables passageof the gate current whose is selected higher than that of the triac firing current, IGT to be measured. By gradually decreasing the value of resistance R1, while continuing to transmit pulses of gate current IG, the
main current IT is increased. As long as the value of
the IT current is lower than that of the device latching current Il, the device does not remain in the conducting state. The value of the latching current Il is the value of the IT current read as soon as the triac remains on, after suppressing the gate current IG.
Only sensitive thyristors (IGT ~ 500 ~A) are measured with a 1 KQ resistor between gate and cathode.
Parameter Il varies with the width of the gate current pulse IGT and its level. For the measurement to be reproduced correctly, the following rules should thus be observed:
Fix a sufficiently wide control pulse IG. The width of the pulse should be at least equal to 1 ms.
Impose a gate current IG sufficiently high with respect to that of the triggering current IGT of the device to be measured. An _IIG ratio higher than or equal to 1.2 is advisable..
GT
Example: BTA 12.600 C
IGT max (Q IV) = 50 mA therefore
IG = 60 mA
In the case of a triac, there are four latching current Il values that correspond to the four quadrants of triac operation:
- (Il + +) when the electrodes A2 and G are positive with respect to electrode A1.
-(Il + -) when electrode A2 is positive with respect to electrode A1 and electrode G is negative with respect to electrode A1.
- (Il --) when electrodes A2 and G are negative with respect to electrode A1.
- (Il - +) when electrode A2 is negative with respect to electrode A1 and electrode G is positive with respect to electrode A1.
_6/_10______________________~~l ~i~~~~~~~~~------------------------
898
APPLICATION NOTE
VARIATIONS OF LATCHING CURRENT Il WITH THE UTILIZATION CONDITIONS
a) Variations of the Il current with sensitivity of triacs and the various directions of conduction (typical values).
For the low power components (thyristors and triacs whose rated current is lower than 60A) the latching current Il is dependent on the value of firing current IGT (see figure 8).
Figure 8 : Ratio of the Latching Current IL in the Different Ouadrants to the Triggering Current IGT in the First Quadrant, for Sensitive and Standard Triacs (typical values).
6 Arms Sensitive Triacs (T type) 12 Arms Standard Triacs (8 type)
~I)
IGT(OI) 3.5 2
IL (all) IGT (01)
15 5
IL (0111) IGT(OI)
5 1.5
IL (01 V) IGT (01)
3 1.7
Example 1 : 8TA 06.600 T :
if IGT (01) ~ 1 mA then: IL (01) ~ 3.5 mA ; IL (all) ~ 15 mA IL (0111) ~ 5 mA; IL (QIV) ~ 3 mA
and 8TA 12.600 8
if IGT (01) ~ 15 mA then: IL (01) ~ 30 mA; IL (all) ~ 75 mA IL (0111) ~ 22 mA ; IL (OIV) ~ 25 mA
In the case of triacs, as opposed to that of thyristors, note that: as underlined in the table of figure 8, the current Il + - (electrode A2 positive with respect to electrode A1 and electrode G negative with respect to electrode A1 - 011) is much higher than the Il current in the three other quadrants.
In the data sheets two values are specified: one value for quadrants I, III and IV and one value for quadrant II. In general these values are typical.
b) Relation between the latching current Il and the holding current IH
The holding current value IH (see bibliography, note N° 2) is linked to the latching current value, Il. By definition, the Il current value will always be higher than the IH current value.
The Il/ IH ratio varies following the sensitivity of the triacs and their ratings (see figure 9).
Example 2:
8TA 12.600 C :
IL typ ~ 40 mA 01, III, IV
IL typ ~ 70 mA all
Depending on the production batches, parameter IL
shows dispersion. Shown below are approximate
values:
sensitive triacs :
IGT (01) 0;; 5 mA (type T): 01, III, IV : 2 mA 0;; IL 0;; 8 mA all: 10 mA 0;; IL 0;; 40 mA
standard triacs :
IGT (01) 0;; 50 mA (type 8): 01, III, IV : 15 mA 0;; IL 0;; 50 mA all: 50 mA 0;; IL 0;; 120 mA
Figure 9 : Ratio of the Latching Current IL to the Holding Current IH Depending on the Sensitivity and Ratings of the Devices (typical values).
IL / IH (1 )
Sensitive Triacs and Thyristors
IRMS 0;; 6 A
1.1 to 1.5
Medium Power Thyristors and Triacs 6A 0;; IRMS 0;; 60 A
1.5 to 2
High Power Thyristors and Triacs 60 A 0;; IRMS 0;; 300 A
2 to 5
(1) 1 st quadrant in the case of triacs.
----------------------------~'r~ ~i~@IH~~:~~~~-------------------------7-/--10
899
APPLICATION NOTE
c) Variations of the latching current IL with the junction temperature. The value of the latching current IL is physically
linked that of the triggering current IGT. These two parameters therefore way analogously with the junction temperature (see figure 10).
Figure 10 : Relative variations of the latching current il versus the junction temperature tj (typ. values). 1. Quadrant 2 2. Quadrants 1, 3 and 4.
2.5
2
,
'" ,
.5
I"
--I"--
...-r 2 ..l i'-.
-- :-::: j:::::., r-
.5
--l""-I-
°0 o
o
""" N
o.... ow
o Tj(OC)
o o
N
DB9AN303·0B
Example 3: Triac TO 220, type BTA 12.600 e
If IL (QI) = 20 mA at Tj = 25°C, then IL (QI) = 30 mA atTj=-40oe
d) Influence of the external gate-cathode resistor RGC
When using sensitive thyristors, the designer could wire a resistor RGC between cathode and gate to improve their voltage capability at high temperatures (shunting of leakage currents).
This resistor affects the value of the latching current IL in different proportions depending on its resistive value and the sensitivity of the component.
1. Sensitive thyristors (IGT < 500 IJA)
Resistor RGC connected between gate and cathode (figure 11) has an important influence on the latching
current IL of sensitive thyristors. For some applica-
tions, the designer would be well advised to define a high impedance triggering circuit.
Figure 11 : Variation of the latching current IL of a sensitive thyristor (e. g. TLS106-6) as a function of the gate-cathode resistance RGC (typ. values).
IL(mA)
o
9
I""-
8
7
6 5 4
3 2 1
0 ....
............ o
I"-
"-
" '"
o o
I"-...... I"--
o
8
o RGK(O)
§
Sensitive thyristor
G
DB9AN303·09
Note: The latching current of sensitive thyristors is always specified with a 1ODD-ohm gate-cathode resistor.
900
APPLICATION NOTE
2. Standard thyristors, sensitive and standard triacs
A resistor connected between the gate and cathode of one of these components does not have a significative influence on the value of its latching current IL (on condition that its value is not too low RGC > 20 ohms).
e) Variation of the latching current IL with the control conditions The latching current IL of a triac or a thyristor rated at less than 60 Arms varies with the amplitude and
the width of the triggering pulse IG. With a constant pulse width« SOilS), an increase in the amplitude of IG will lead to an increase in the latching current IL and vice versa, if the amplitude of IG is kept constant, a decrease in the width of the triggering pulse will lead to an increase in the latching current IL that can even lead to an absence of firing of the device (figure 12).
Figure 12 : Variation of the Latching Current IL versus the Width tp and the Level of the Gate Current IG (represented here as a multiple of the triggering current IGT of the triac under consideration) Triac BTB 16.600 B (quadrant 1) (typical values).
IL(~
, '100
SO
eo
" - 7D
(iiU
50
l""-
ra ·
it" =101GT
'\
i"o.,
~:a
=ISIGr
,........ i"-.... ~ !G=
2
IGT
- 40
SO
20
10
- o c
c
D89AN303·10
Negative biasing of the gate circuit (example: shape of the pulse in figure 13a) increases the latching current IL in considerable proportions. If the decreasing speed dlG/dt of the gate current is low
Figure 13a : Gate Current Pulse with Negative Current at the end of the Pulse: Increase of the Latching Current IL.
(example: pulse shape of figure 13 b) (less than 0.5 NilS) the value of the latching current approaches the holding current IH.
Figure 13b : Gate Current Pulse (diac controlled type) with tailing and without Negative Current: decrease of the Latching Current IL.
-
v
D89AN303-11
D89AN303-12
-------------------------~~l ~ii@~Y~~~~©~-----------------------9-/1-0 901
APPLICATION NOTE
In order to obtain the lowest possible values for the latching current IL, and thus ensure correct firing of the device, it is advisable to work with an amplitude of IG equal to 1.2 IGT and a width of the control current as high as possible. The firing technique using trains of closely spaced pulses ensures stable firing in total security. Control pulses with smooth tailing edges and without reverse current allo reducing the latching current.
CONCLUSION
The choice of a thyristor or of a triac does not depend only on the rated current, voltage and sensitivity. Other parameters also play an important part in the correct operation of a circuit and should be taken into account. The latching current IL is one of these. Its value varies with:
_ the way in which the device is controlled (shape of the gate pulse)
_ the temperature
_ the trigger circuit (case of sensitive thyristors)
_ the direction of the current.
Triac and thyristor applications involving highly inductive loads or loads with considerable variations of controlled power are the main applications where the latching current IL plays a determining role.
Taking these elements into account will enable the designerto obtain satisfactory operation of his circuit in industrial applications.
BIBLIOGRAPHIE
1 - "Control of triacs for inductive loads" : technical information TI 36/ SGS THOMSON
MICROELECTRONICS by X. DURBECQ.
2 - "Hypostatic current or holding current" by E. LEBLANC.
_10_/1_0______________________~~l ~i~@~g~i~~~~-------------------------
902
APPLICATION NOTE
The switching of a resistive load on the mains generates electromagnetic disturbances whose level is in keeping with the voltage at the time of firing. These disturbances can be reduced by switching on
o. the load when the mains voltage approaches
The convenience of firing control, the absence of rebound, and the response time of a semiconductor device enable designing static relays which guarantee this synchronous type of switching. The "mains zero" detection function can be obtained by a circuit using discrete components.
Figure 1 : Block Diagram of Static Relay.
DESIGN OF A STATIC RELAY
By X. Durbecq
This note provides a review of the principle of static relays as well as the method of calculation for the circuit component.
OPERATION A STATIC RELAY
The static relay consists of a power component, the triac, triggered by a circuit ensuring the func,;tions of "mains zero" detection and interfacing with the input signal.
--0 0--
Control
MAINS ZERO VOLTAGE
DETECTION
I
I
LOAD
l I
I
~ ~
Mains
~
j
D89AN306·01
OPERATING PRINCIPE The firing of the triac can only take place when the mains voltage is close to 0 volt (± 30 V max). For a long-duration input signal (> 10 ms), the triac is fired at the mains voltage zero. It continues to conduct
AN306/0289
for the full duration of this signal until the current drops to zero after disappearance of the input signal.
An input pulse « 10 ms) should coincide with the
passing through zero of the mains voltage to enable conduction of the. triac (figure 2b).
1/3
903
APPLICATION NOTE
'Figure 2 : Synchronous Static Relay: Waveforms Figure 2a : Long Duration Input Signal (> 10 ms). Figure 2b : Short Duration Input Pulse « 10 ms).
Mains voltage: V = 300 V/d.
Input signal: V = 10 V/d. Mains current: I = 1 Ald. T = 10 ms/d.
DB9AN306-02A
CHARACTERISTICS OF THE STATIC RELAY:
- Closing of the circuit when the mains voltage passes through zero (resistive and capacitive loads).
- Control of the static relay by very low signals (logic circuits, optocouplers, etc.).
- Insensitive to shocks and vibrations.
- High switching speed.
DB9AN306-02B
The triac is fired only when the input signal coincides with the passage through zero of the mains voltage. Mains voltage: V = 300 V/d.
Input signal: V = 10 V/d. Main current: I = 1 A/d.
T = 10 ms/d.
- No rebound. - No electromagnetic disturbances. - Opening of the circuit when the current passes through zero.
STATIC RELAY WITH DISCRETE COMPONENTS:
The triac triggering circuit consists of a transistor Tr and a sensitive thyristor Th. This circuit is biased by the mains voltage after full wave rectification (figure 3).
Figure 3 : Schematic Diagram of a Static Relay with Discrete Components.
Load
Mains
Triggering by closing control at mains zero voltage
2/3
904
DB9AN306-03
APPLICATION NOTE
OPERATION OF THE CIRCUIT:
Two distinct states can be observed:
1) Relay blocked: switch K open. As soon as the mains voltage passes through zero, the current in resistor Rl saturates transistor Tr, inhibiting the firing of thyristor Th by shunting the gate current transmitted by R2.
2) Relay fired: switch K closed. The voltage divider composed of resistors Rl and R3 results in blocking of transistor Tr, as long as the mains voltage is lower than Va (generally 30 V).
The current which flows through resistor R2, passes through the gate of the thryristor. The thyristor Th can therefore be fired only during this time To, which defines the mains zero operating tol.erance.
3) For R3, a resistor of relatively low value (4.7 kohms) is used in order to sufficiently bias all the types of transistors which replace switch K.
4) Calculatit:m of Rl : switch K closed.
Transistor Tr is saturated only if the mains voltage is higher than Va.
~ X R2 X R3 X (Va -1) Rl
0.7 X ~ X R2 + R3 X Va
The value of Rl determines the tolerance on voltage Va. The value selected for resistor Rl is the standard value immediately above the calculated value.
5) Calculation of Rg In order to have a gate current Ig sufficiently high to fire the triac, Rg is selected so that:
Rg«
Vo -4 - RL
Ig\ max triac
EQUATIONS OF THE CIRCUIT: Switch K closed. 1) Maximum firing time of triac, at the beginning of each half-period.
Va
To =
Vrmsxffxw
..If Vo «Vrms
2) Calculation of R2. A sensitive thyristor is used.
E.g. TLS 106-4 : Ig\ max = 200 flA at 25°C
Va - Vg\ max (Th) R2< ----~----~~
Ig\ max (Th)
ADVANTAGES
- Very low power dissipated in the control circuit. « 500mW). - Operation of the triac in quadrants 1 and 3 ensur-
ing a good symmetry of the latching current iL.
- High gate current available enables firing non sensitive tri acs.
DISADVANTAGES
- Utilization of a sensitive thrysitor requires the use of an R.C. circuit across the triac, to prevent untimely triggering by transients transmitted by the mains.
EXAMPLE OF APPLICATIONS: Figure 4: Static Relay with Discrete Components and Isolated Control.
4xlN4004
Load
0.111 400V 220 V ~
Th : TLS 106-4 or TS08xx
D89AN306-04
CONCLUSION
Using discrete components allows the design of simple circuits which achieve the synchronous static relay work.
Their main advantages are to provide a high gate current for the triac and to dissipate very low power.
3/3
905
APPLICATION NOTE
USE OF TRIACS ON INDUCTIVE LOADS
Although triac circuits are now well known by designers. The use of these components for inductive loads requires certain precautions which should not be neglected of optimum use is to be made of them. That is the purpose of this article which reviews the various triac control modes and recalls the principles which guarantee its correct operation.
PHENOMENA OCCURING WHEN THE CIRCUIT IS CLOSED.
The triac is known as a component which is essential in controlling power from an AC source (mains).
In most cases, the circuit has an inductive component : either because of the nature of the load itself: motors, transformers, ballast inductance ; or because of the source impedance: utilization of the secondary of a transformer, length of the supply line, etc. On inductive loads, the operating conditions vary considerably, when closing the circuit, depend-
By J. Bellin
ing on the control mode (gate current, polarity and width) and synchronization of the firing. In order to build an optimal control circuit it is indispensable to analyse the various possibilities.
FIRING
CONTROL SIGNAL
The triac is fired by a gate current Ig > Igt whose duration should enable the main current to reach the triac holding current value (IL).
The width of the control signal is determined by the rate of increase of the main current (di/dt), limited by the load inductance and by the choice of the firing quadrant.
The loading current, IL, is highest in the second quadrant (A2 positive with respect to A1, 19 negative) : (figure 1-a).
Figure 1 : Width of Control Signal Required as a Function of the Firing Quadrant (a) ; width of Control Signal Required as a Function of the Moment of Firing (b).
tI triac current
IL
quadranl tt
f------,..1ll I
quadranls I. ttl and IV
Ig quadranls I. Itt and IV
I I
a
I triac current
b _ _ OL---~~+4L+-----Ig
Quadrants Polarity
II III IV
A2
+ +
G
+
+
with Respect to A1
AN307/0289
Ig firing at peak II!lltage
D89AN307-01
1/5
907
APPLICATION NOTE
The rate of rise of the hlain current, difdt, is proportional to the amplitude of the power supply voltage at the moment of firing (difdt = VfL). The width of the firing signal required is less when firing occurs near the peak of the mains voltage than when its occurs around zero of that voltage (figure 1-b). To fire the triac and to ensure conduction in continuous operation, we can compare various types of control circuits.
GATE CURRENT CONTROL BY SINGLE PULSE To ensure correct operation, the gate pulse should
be synchronized with the triac current zero pOint and should be long enough to enable the main current to reach the latching current IL level (figure 2-a).
In case the pulse occurs before the triac current reaches its zero point (incorrect synchronization) or if its duration is too short to allow the main current to exceed the latching current IL, the triac conducts only during alternate half-cycles. The high DC component thus introduced in the load can produce considerable overloads due to saturation of magnetic materials.
Figure 2 : Gate Control by a Single Pulse Synchronized with Zero Current (a) ; in Case of a Single Pulse whose Duration is too Short, the Triac only Conducts during Alternate Half-cycles (b).
I triac current
[ triac current
D89AN307·02
GATE CONTROL BY PULSE TRAIN The control by gate pulse train eliminates problems of synchronization on the current. A recurrence frequency of several kilohertz guarantees correct operation of this type of control (figure 3). This procedure, whose results are satisfactory, is often used for controlling triacs in inductive circuits.
A variant of this principle consists in making use of a circuit which monitors firing and which delivers pulses to the gate as long as the voltage across the triac is higher than a threshold, usually fixed at about 10 volts (figure 4). This type of circuit enables delivering just the amount of gate current required for firing.
GATE CONTROL BY DC CURRENT Gate control by DC guarantees ideal firing but has the disadvantage of high consumption, specially when the control power supply is provided by the mains. In this case, it is preferable to use a negative current for the gate control (quadrants II and III).
Figure 3 : Gate Control by Pulse Train.
V mains voltage
I triac current
I D89AN307.03
- _2/_5 ----------J>."'!L ~i~~m~m~~~~~------------
908
APPLICATION NOTE
TRANSIENT PHENOMENA DURING TRIGGERING
Principles
During continuous operation, the magnetic field H, proportional to the current in the coil, varies with re-
spect to the induction B, with a delay as shown by the hysteresis cycle in figure 5. In transient operation, the induction can follow a different path and reach the saturation value Bs for which the magnetic field H (according to the coil current) increases very rapidly (figure 6).
Figure 4 : Firing Monitoring Circuit: the Control Signal is repeated until Firing.
Firing monitoring Control
Threshold vz
Figure 5 : Magnetic Field H with Respect to Induction B in Continuous Sinusoidal Phase.
D89AN307 ·04
Figure 6: Induction Bs Versus Field H Variation.
B
Bs
----- - - --:=-;::-:.;::-"-,,,,---
H
o
H
H k.nI
D89AN307·05
In the circuits controlled by a triac, opening occurs when the current is at zero. The induction thus has a remanent value Br, corresponding to H = 0 (figure 5).
D89AN307·06
When the triac begins to conduct, the transients depend on the instant of synchronization of the control signal with respect to the mains voltage.
------------------------~~l ~~~~~~~~~©~-----------------------3-/5
909
APPLICATION NOTE
FIRING AT ZERO MAINS VOLTAGE
Peak induction tends to the value:
Bmax = 2 Bn + Br,
thus in most cases reaching saturation induction Bs. The amplitude of the current proportional to the magnetic field H becomes very high; this type of control produces the highest transient overloads (figure 7-a).
In order to limit the over current during firing at zero voltage, control must be done by complete periods. Since the triac allows an integral number of halfcycles to pass, the polarity of the mains voltage at the moment of firing is the reverse of that at the moment the circuit is opened.
Peak induction thus reaches the value:
Bmax = 2 Bn - Br, because B rises between P and Q
on the hysteresis cycle.
The overload is lower than previously but still remains high (figure 7-b).
FIRING AT PEAK MAINS VOLTAGE Peak induction takes the value: Bmax = Bn + Br In general, the threshold of saturation Bs is not reached and amplitude of the current remains within acceptable limits (figure 7-c).
This type of synchronization is simple and efficient and should be adopted whenever possible on loads composed of materials which can be saturated.
Figure 7 : Transient Induction and Current at Beginning of Conduction.
V mai ns voltage
V mains voltage
V mains voltage
2 Bn + Br
B induction ,,'-'\, Bs i-----.f""=---=~.
tB induction 2 Bn - Br
Bsi--------.f="!.
B induction Bs 1-------::=
I--~----r-_r~~---- O~----------~-------
triac current
A : firi ng at voltage zero
B : firing at voltage zero conduction by complete periOds
C : firing at voltage peak
D89AN307 ·07
~~l _4!_5______________________ ~i~©~~~~?~~-----------------------
910
APPLICATION NOTE
FIRING AT INDUCTANCE PHASE SHIFT WITH CONDUCTION BY COMPLETE PERIODS
Firing atthe real inductance phase shift with conduction by complete periods places the magnetic field and the induction on the hysteresis cycle of continuous operation: consequently, transients are eliminated. However, the design of the control circuit for this firing mode is complex and consequently it is reserved for special applications.
Figure 8 : Firing by Phase Sweep.
FIRING BY PHASE SWEEP
The triac is first fired at the end of a half-cycle. Then progressively the difference of phase between the voltage zero and the instant of firing decreases until total conduction. With a sufficiently low sweep speed, any transient overload is thus avoided (figure 8). This procedure is widely used and gives very good results.
V mains voltage
V
f1 triac current
0
t
F r
I~'(
o n n
DB9AN307·0B
SPURIOUS FIRING
The control circuit plays an important role in normal operation. However, in case of spurious firing, the triac may have to withstand an accidental overload. The peak amplitude of the current which could flow
through the triac should be known to select its rating : the maximum current which could flow through the circuit should not be higher than the accidental overload capacity of the triac (ITsM). In this care the triac is oversized.
CONCLUSION
We have seen the essential points guaranteeing correct operation of a triac. If the circuit is closed on an inductive load, you need to :
Fire the triac:
With a sufficiently wide gate control signal, in the choosen quadrants (depending on whether higher sensitivity or a low latching current is required).
Avoid transient overloads:
By synchronizing the control signal with respect to the mains at the moment of firing (firing of the triac at zero voltage should be avoided).
Keep the triac in conduction: By selection of the type of control (avoid gate control by a single short pulse).
------------------------~~l ~~~@~~~~~~~~-----------------------5-/5
911
APPLICATION NOTE
CONTROL BY A TRIAC FOR AN INDUCTIVE LOAD HOW TO SELECT A SUITABLE CIRCUIT
By X. Durbecq
Today triacs are well suited to the requirements of switching inductive loads. Nevertheless many users still encounter difficulties when designing triac control circuits which are to be both economical and applicable to inductive loads.
The purpose of this article is to present different methods of triac control with their appl ications and to analyze their relative advantages and disadvantages.
A simple circuit offering all the guarantees of reliability is proposed for industrial loads.
TRIGGERING WITH SYNCHRONIZATION ACROSS THE TRIAC
The triggering circuit with "synchronization across the triac" (fig. 1 and 2) turns on the component at an angle ~ after the current drops to zero, such that
~ = OJ Tr.
Time Tr is defined by the time constant (P + Rt)C.
OJ = 2 . 1t . f with f = mains frequency.
Figure 1 : Typical Circuit: Synchronization Across the Triac.
T
Mains
c
p
At
Figure 2 : Synchronization Across the Triac. Shape of the Signals; General Case.
D89AN306-01
Mains voltage
Gate pulse
T
Triac voltage
q> : Current lag (full angle). ~ : Blocking of the component. a : Conduction angle.
Triac current
AN308/0289
T
/...--- ..
/
T
D89AN308-02
1/11 913
APPLICATION NOTE
This is the simplest possible circuit but in certain cases of utilization it can have an important drawback.
For example, consider a highly inductive load (L 0) / R > 4) where the triac is turned on with a con-
siderable delay ~ = 1000 after the mains voltage
zero (figure 3).
The duration of conduction a of the triac turned on at point A, is about 1500 · The triac is blocked at point B at a + ~ = 250 0 after the zero voltage point. At that instant a negative voltage is applied to the triggering circuitwhich turn on the triac at point C after an angle ~ of 1000 , i.e. 3500 from the starting point. The second turn-on will occur ata very low voltage
and the angle a' will be much smaller than a. The following period begins under similar conditions and the unbalance persists. This type of asymmetrical operation is not only unacceptable but can be dangerous (saturation of the load by a DC component). The unbalance is illustrated for a particular case, starting from zero of the mains Voltage. Other causes also produce this fault: variation of the load impedance, transient operation, modification of the adjustement... The reason for this is the principle of the circuit which does not take its reference from the mains voltage zero. Synchronization is by the voltage across the triac, which is a function of the current in the load.
Figure 3 : Synchronization Across the Triac. Shape of the Signals.
Mains voltage
Gate pulse
T
Triac voltage
T
Triac current
T 1---¥:.4----\-~---J~.~-~'----_
,
/ /
" "" ,\
...I....
, - -~
I full angle
D89AN308·03
Summing up, this first very simple triggering circuit, synchronized by the voltage across the triac, has: 1) Definite advantages: - Simple design and low cost. - Connection by two wires, without polarity. - Absence of a separate power supply. - Little power dissipated in P and Rt. 2) A serious disadvantage: Because of its principle, this circuit cannot be used for highly inductive loads with a narrow conduction
angle because it can result in unacceptable asymmetrical operation.
This very simple triggering circuit should be reserved for low-cost applications with the following characteristics:
- Resistive or slightly inductive loads.
- No stringent requirements concerning the accuracy of regulation.
- Variation on highly inductive loads between 85 and 100 % of the maximum power.
~2/~11~_____________________~~l ~~~~~~l~~~~-------------------------
914
APPLICATION NOTE
TRIGGERING WITH SYNCHRONIZATION BY THE MAINS VOLTAGE
This triggering circuit (figure 4) is synchronized by
the mains voltage. The pulses are always shifted by 1800 with respect to each other, whatever the type of load.
Figure 4 : Typical Circuit - Synchronization by Mains Voltage.
T
Mams
c
~
Figure 5 : Synchronization by the Mains Voltage: Shape of Signals.
Mains voltage Gate pulse
DB9AN30B-04
T
Triac voltage Tflac current
- " ~-
I
"- '\
,
T
/
/
I
T
/
./ -..... I full angle
lJl : Current lag at full angle. ~ : Blocking of component. a : Angle of conduction. S : Triggering delay angle.
DB9P.N30B-05
-------------------------~~l ~i~;~g~~R~~~----------------------~3~/1~1 915
APPLICATION NOTE
Angle 9, characterizing the delay between the mains voltage zero and the triggering pulse, can be adjusted by means of potentiometer P from 0 to 180° to vary the voltage across the load. The current in an inductive load (L.R) lags with respect to the voltage by an angle q> :
(tan q> = L.w / R).
For triggering angles 9 higher than q>,operation is perfectly symmetrical and stable.
This simple circuit can still present the risk of a fault in case angle 9 is smaller than angle q> (figure 6).
As an example, take the case of a highly inductive
load and an angle 9 = 60° . The triac is turned on at
point A (60°).
It will conduct during an angle CJ. greater than 180°, in the neighbourhood of 250° . It is blocked at point
B : (290°). The second triggering pulse occurs at point C : (9 + CJ. = 240°).
It has no action on the triac which is still conducting. The triac is not turned on for the other half-wave. As in the previous case, the operation is asymmetrical, and thus unacceptable.
Figure 6 : Synchronization by the Mains Voltage - Shape of the Signals for 9 < q> - Asymmetrical Operation.
Mains voltage Gate pulse
__ T ~~----~-+-----+--L---~~
Triac voltage
T
Triac current
To prevent this fault, it is necessary to insert a "stop" to maintain 9 > q> . This is possible for loads whose Land R parameters remain strictly constant. Experience shows that for the majority of inductive loads used in industrial applications (motor controls; transformers, etc...) it is not possible to insert the "stop" without considerably limiting the voltage excursion, since the values of Land R vary a great deal during operation. Summing up, this simple triggering circuit, synchronized by the mains voltage, is more developed than the previous one. It has: 1) Advantages : - Simple design.
I
~ /
I lull angle
T
DB9AN30B·06
- More accurate control than the previous circuit.
- No auxiliary power supply or transformer required.
2) Disadvantages:
- Connection of the circuit by 3 marked wires, instead of 2 without polarity in the previous circuits.
- Power dissipated in passive components P and Rt.
- Operation becomes completely asymmetrical if the control angle 9 is less than q>.
This triggering circuit can only be used for applications in which the phase shift of the load remains constant (air inductor) or if operation is restricted to values of 9 much higher than q>.i.e. at low voltage.
916
APPLICATION NOTE
TRIGGERING SYNCHRONIZED BY THE MAINS VOLTAGE AND SUITABLE FOR INDUSTRIAL APPLICATIONS
This new circuit is derived from the previous one by improving the triggering pulse generator. The improve-
ment consists in maintaining the triggering signal
e during each half-wave between values and 180°.
This is done simply by sending a pulse train after the
initial pulse so as to maintain the triggering order (figure 7).
Figure 7 : New Circuit - Triggering by Pulse Train Synchronization by the Mains Voltage.
Mains voltage Gate pulse
Triac voltage
Triac current
t A
!p : Current lag full angle. a : 1st angle of conduction. a 2 : 2nd angle. ~ : Blocking of triac.
e : Triggering delay time.
For example, suppose that angle !p is equal to 850
e and is equal to 600 · At the first pulse, the triac is
turned on at point A (600 ). It conducts for angle a 1 greater than 180° and close to 240°. It is blocked at point B but is immediately triggered at point B' by the
Figure 8 : Circuit with Triggering by Pulse Train Synchronization by Mains Voltage.
Mains
Ts RI
DB9AN30B·OB
DB9AN30B·07
next repetitive pulse. During the first half-waves, operation is slightly asymmetrical but gradually the durations of conduction become balanced (dotted line curve in figure 7).
Figure 8 gives the circuit diagram. A small sensitive auxiliary triac is used to produce the pulse train necessary for maintaining the control signal.
Capacitor C, compensating resistor Rt and poten-
e tiometer P define the angle or delay time constant.
The capacitor is charged from 0 V and diac D triggers as soon as its breakover voltage (Vbo) is reached. The angle is positioned identically for both half-waves.
A first pulse is applied to the gate of the main triac, T. A voltage pulse occurs across Rd and triggers sensitive triac Ts. Once it has been turned on, this triac bypasses potentiometer P. The remaining charging cycles of the capacitor have a much shorter time constant Rt x C.
- - - - - - - - - - - - - - r : : . " Yt1==l SIiGfSU©.1WH@[OHM~©S'GO'rOuO:QiIii.JU©:ll--------------"'.-5'/-11'
917
APPLICATION NOTE
A succession or train of pulses is applied to the gate of the main triac, T, enabling elimination of the defects explained above. The pulse train continues until the mains voltage crosses the 0 point. Triac Ts, supplied through a resistive load, is blocked.
For the following half-cycle, the capacitor load is once more based on the time constant determined by the potentiometer. The cycle is resumed in inverse.
Summing up, the improved triggering circuit synchronized by the mains voltage has a number of advantages.
- Simplicity of design. - Excellent accuracy of control. - Absence of auxilliary separate power supply. - Utilization of the circuit for all types of loads with different cos cp or variable cos cp values.
- No risk of failure over the whole adjusting range.
This circuit has been developed by the SGS-THOMSON Microelectronics applications laboratory and used with success for a wide range of equipment.
CONCLUSION:
The difficult conditions of an inductive environment require a critical choice of the triggering circuit. The first two circuits described leave the user a very limited adjusting range. A universal circuit can be obtained by taking into account two decisive factors
- To obtain perfect symmetry of the first gate pulses in both half-cycles, the triggering circuit should be synchronized by the mains Voltage. - The variation in phase angle enables perfect symmetry of the current if the triac is continuously triggered. The circuit described in the last paragraph combines these two principles in a very simple manner. It enables complete variation of power on an inductive load without particular problems. It can thus serves as the basis for a universal circuit for control by phase splitting on a inductive load.
.6/:11:::...:.-'--------------1I;r.=1-=l STIGiSi~-1(HQ:OiMruSlOQ:Nc;rLll'&iJiru@i%(Q;~--------------
918
APPLICATION NOTE
SYNCHRONIZATION ACROSS THE TRIAC Figure 9 : Example of an Application: Speed-control Circuit for a Small Asynchronous Motor.
N 3,3 nF 3pF 400 V
3,3 nF Ph
SYNCHRONIZATION BY THE MAINS VOLTAGE Figure 10 : Example of an Application: 220/110 V Step-down Circuit.
h. D_l/IF - I 4(){)V
OB9AN30B-09
220VRMS 1.5KE68A
l
1
110VRMS ZL
15 kll 4W
OB9AN30B-10
- - - - - - - - - - - - - - [ } , , "rf.::l:.-l= SGs.THornsorn [f:JJD@]l©"'~"'Ii;:ITIFJI[Ii/JD@:0---------------'--'---7-/1'1-
919
APPLICATION NOTE
NEW TRIGGERING CIRCUIT Figure 11 : Example of an Application: Power Variation Circuit for Arc Welding Transformer.
O.1!'F 400V
220 V
28. 27k 112W
1.5KE68A
+ -z- _
D89AN308-11
J...,l ::::.8/..:...11'--_ _ _ _ _ _ _ _ _ _ _
~~~(~m~:~~?~~-------------
920
APPLICATION NOTE
APPENDIX CONTROL BY TRIAC FOR INDUCTIVE LOADS
SUMMARY OF SOLUTIONS
A SYNCHRONOUS TRIGGERING ACROSS THE TRIAC
T
p
R
Synchronization across the triac based on crossing of the zero point by the current.
8 TRIGGERING SYNCHRONIZED BY THE MAINS VOLTAGE
T
Mains
Synchronization based on crossing of the zero point by the mains voltage
C NEW TRIGGERING CIRCUIT
Mains Ts.
Synchronization by crossing of the zero point by the mains voltage and generation of a pulse train from then onwards.
DS9AN30S-14
- - - - - - - - - - - - - - J J . . " "r'=!-l= S~DGIGSOO-l@H[IOllM1lSlOilNG'ii'OO@IiIlDIG:0---------------=.:.-'9-/1'1-
921
APPLICATION NOTE
TRIGGERING SYNCHRONIZED ACROSS THE TRIAC
SCHEMATIC DIAGRAM (see page 10-A)
RESISTIVE LOAD:
Current and voltage are in phase: good synchronization. No fault over the whole adjusting range.
INDUCTIVE LOAD: The current lags by TC 12. Two cases should be considered: - Broad conducting angle; narrow lag angle. The time separating two conducting periods is very brief. The positive and negative currents are practically equivalent. Little dissymmetry. Certain applications are covered by this case. e.g. speed-control circuit for AC motors. - Narrow conducting angle; broad lag angle. The flow of current in one direction is a function of the control and thus of the duration of the current flow in the previous direction. The triac can be triggered at the end of the mains half-cycle. In this case no current flows through the circuit and it acts as a rectifier.
ADVANTAGES OF THE CIRCUIT: - Connection by two wires without polarity. - No power dissipated by the passive components. - Excellent power variation circuit for resitive or slightly inductive loads. - With highly inductive loads, the circuit can only give satisfaction within the limits of a slight decrease in the conducting angle.
DISADVANTAGES: - For inductive loads, large current dissymmetry for a variation towards the narrowest conduction angles. For this type of application the circuit cannot be used atall.
TRIGGERING SYNCHRONIZED BY THE MAINS VOLTAGE
SCHEMATIC DIAGRAM·(see page 10-B)
RESISTIVE LOAD: No fault over the whole adjusting range.
INDUCTIVE LOAD: Two cases should be considered:
e - Delay. angle > the lag, <po
Correct synchronization of the triggering pulses enables balanced conduction for all variations up to the lag angle.
Certain applications use this principle:
e.g. 200 V - 100 Vrms step-down circuit.
e - Delay angle < <po
Triggering occurs before the lag angle is reached. The triac will conduct for an angle ex > 1800 · It is blocked after the gate pulse of the following halfcycle. The current does not flow in that direction. The circuit th us acts as a rectifier.
ADVANTAGES OF THE CIRCUIT - Accuracy of the triggering pulses. - Current operation with a resistive load but circuit too complex. - Excellent operation for power variation circuits limiting conduction to small angles with inductive loads.
DISADVANTAGES: - Connection by three wires. Necessity to obtain access to the mains terminals. - Permanent power supply with power dissipated by the passive components. - Impossible to adjust the delay angle to values approaching or inferior to the current lag. This circuit cannot be used for inductive loads where a variation close to the highest conduction angles is required.
NEW TRIGGERING CIRCUIT
SCHEMATIC DIAGRAM (see page 10-C)
RESISTIVE LOAD:
Absence of fault over the whole adjusting range.
INDUCTIVE LOAD:
Operation in the two possible cases:
e - Delay angle > <p
Balanced conduction due to perfect synchronization of the triggering pulses.
- Delay angle e < <p
For a conduction angle higher than 1800 , the triac is blocked after the 1st pulse of the following halfcycle. It is immediately retriggered by the next repetitive pulse. The two currents are mutually modified until a balance is reached.
922
APPLICATION NOTE
DISADVANTAGES OF THE CIRCUIT:
- Connection by 3 wires. Access to the mains terminals. - Permanent power supply with power dissipated in the passive components.
ADVANTAGES:
- Accuracy of the triggering pulses. - Correct operation for resistive loads. - Complete absence of faults for inductive loads.
Power variation over the whole range. Perfectly balanced positive and negative current.
------------------------~~l ~i~@~2:~~~~~--------------------~11~/1~1
923
APPLICATION NOTE
PROTECT YOUR TRIACS
By P. RAULT
In most of their applications, triacs are directly exposed to overvoltages transmitted by the mains. When used to drive resistive loads (temperature regulation), it is indispensable to provide them with eficient protection.
WHY PROTECTION? In a typical utilization circuit (figure 1), an overvoltage superimposed on the network voltage can turn on the triac by exceeding. its avalanche voltage. Un-
der these conditions, because of its internal structure, only part of triac is effectively turned on and can thus withstand only very low dild!. This explains the considerable danger of damage to the component when used to drive purely resistive loads. In reality, the dildt when turning on can, in this case, reach very high values (> 100 AlIlS) since only the inductance of the connections limits the rate at which the current can increase.
Figure 1 : Typical Circuit. The Triac is directly connected to the distribution network: risk of darnage.
R
Vmains
+
accidental overvollages
Control
D89AN328DQ1
WHAT WE PROPOSE
The principle of the protection which we have studied consists in turning on the triac by the gate, as soon as the voltage across it exceeds a certain value (figure 2), thus under conditions which ensure a high level of safety. To do this we use a bidirectio-
nal TRANSIL diode whose current/voltage characteristic is recalled in figure 3. When the voltage applied to the triac reaches th.e VBR voltage of the TRANSIL, the latter conducts, producing a current in the triac gate and turning it on (figure 4). The triac continues to conduct till the half cycle current passes through zero (figure 5).
Figure 2 : Protection of the Triac by a Bidirectional TRANSIL Diode. The Triac is turned on by gate (current i) as soon as voltage A2 exceeds the voltage VSR of the TRANSIL.
AN328/0489
D89AN328DQ2
1/4
925
APPLICATION NOTE
Figure 3 : Voltage-current Characteristic of a TRANSIL Diode. VSR Specified at 1mA (tolerance 5 or 10%) VCl limitation voltage, given for a high Ipp current level (from several amperes to several tens of amperes, depending of the type.
Current
Ipp
-t__ _~-~V~B=R========~__ +VBR c=========~L-~ Voltage
_______________ Ipp
D89AN328D03
Figure 4 : Characteristic of the TRIAC + TRANSIL Assembly.
.
Case of a 600V/12A triac protected by a 440V TRANSIL diode (the dotted line gives the charac-
teristic of the triac alone).
Current (rnA)
I , I -600 V -440 V
Current in the turned-<ln triac
/
This current
flows Ihrough
30
the g~t"
20
10
I Triac avalanche lone
0 10
I20 30
+440 V
(Transil VBR)
+600 V (Triac VDWM)
Voftage (V)
D89AN328D04
2/4 926
APPLICATION NOTE
Figure 5 : Behaviour of a Triac Protected by a TRANSIL Diode: (the triac is turned on by the gate at the beginning of the overvoltage and continues conductionthrough the rest of the half-wave).
+VSR
v
Overvollage
~I J'
I t..-"-
I I
I I
I I
I I , I ___________________ , .l ________________________________ _
I
I
Mains
I
/' voltage
< ~/I , - - - - .... .)
TRIAC \ voltage \
o~----------~~==========~------------~--~~
-VSR - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ITRIAC
/
_-- , , , o ~-,-',--....-...-. ---------,/-/ ~/-L--------------~--,-..-....-.. -----------------~
D89AN328D05
3/4
927
APPLICATION NOTE
THE ADVANTAGES OF THIS SOLUTION _The triac will always operate within the voltage limits
given by the manufacturer (± VPWM) and thus far from the avalanche zone. _Not much power is dissipated in the triac during the disturbance: when it is turned on, the dissipated power is localized in the protection component (the TRANSIL is made for that I). _The triac is turned on by a gate current which will ensure optimal di/d! conditions.
THE RESULT OBTAINED
We have carried out tests with repetitive overloads (1 Hz) under various conditions: Exponential shock waves of about 1ms, calibrated in voltage (up to 2000V) and controlled in di/dt (500Al~S maxi). The tests were carried out with steep-edged voltage pulses (dV/dt > 1OOOV/~s) and also with gradual slopes « 50V/ms). ~II these tests were successful: zero failure.
SELECTION OF THE TRANSIL DIODE REQUIRED FOR PROTECTING A TRIAC
VOLTAGE: VR Obviously the triac associated with the TRANSIL diode shmlld not be turned on by the maximum mains voltage. An additional safety margin should be given to prevent untimely turning on by the small
voltage· spikes, often repetitive, which are always present OrT a «normally» disturbed mains line.
\12 VR > Vmains x + safety margin
In the absence of accurate 'specifications, add 20% for the safety margin.
v"2 Example: 220V network:
VR > 220 + 20% = 375V
POWER
The TRANSIL only conducts when turning on the triac (t '" 1~s).
The current, during this time, can reach very high levels (several tens of amperes) in the case of disturbances with steep edges (> >1000V/~S), however the dissipated power remains well within the possibilities of TRANSILS. The BZW 04 (400W/1 ms) suffices iri all cases.
PRACTICAL EXAMPLE
Drive circuit for a 2kW heating element on 220V mains (figure 6).
The BZW 04.376 type TRANSIL perfectly protects
the BTB 16.600 B triac (VDWM = ± 600V).
The 100 - Q resistor, R, between the gate and A1 is not absolutely indispensable but it enables preserving the dV/dt characteristic of the triac which is reduced (by about 20%) by the junction capacitance of the TRANSIL between anode and gate.
Figure 6 : Practical Exampl~ of the Protection of a 12 or 16A Triac against Overvoltages.
2kW
220 V
'~
BTB 16600 B
or BTA 12 600 B
Control
D89AN328D06
CONCLUSION
With the protection circuit proposed by us, the triac always operates under perfectly defined conditions in case of overvoltages : _The voltage remains limited to the maximum speci-
fied for the triac
_Turn-on is ensured by a gate current.
This circuit, which we have tested in a number of different setups (different loads, high amplitude overvoltages, disturbances of long duration, etc...), enables a considerable increase in the reliability of circuits using triacs and is indispensable for driving resistive loads on highly disturbed networks.
4/4 928
APPLICATION NOTE
POWER CONTROL WITH 8T621 0 MCU AND TRIAC
Philippe RABIER - Laurent PERIER
INTRODUCTION
Microcontroller (MCU) systems are progressively replacing analog controllers even in low cost applications. They are more flexible, provide a faster time to market and need few components.
With an analog IC, the designer is limited to a fixed function frozen inside the device. With a DIAC control, features such as sensor feedback or enhanced motor drive can not be implemented. With the MCU proposed in this note (ST6210), the designer can implement his own ideas and test them directly using EPROM or One Time Programmable (OTP) versions.
The LOGIC LEVEL triac BTA08-600SW is a good complement to this MCU for low cost off-line power applications. This triac requires a low gate current, and can be directly triggered by the MCU, while still maintaining a high switching capability.
This application note describes the main aspects of a highly flexible, low cost power application designed around an ST6210 MCU and a LOGIC LEVEL triac.
Ilne3MCUBOARD~~
fl Neutral
BOARD OPERATION
Basic function
Light dimmers with DIAC or analog controllers are currently used today. These circuits have the disavantage that they can not easily drive inductive loads like halogen lamps on the secondary of a 220V/12V transformer. They are also limited in the choice of user interfaces.
A light dimmer circuit, supplied directly from the 110V/240V mains, has been realized using a MCU ST6210 and a LOGIC LEVEL triac. This circuit drives both resistive and inductive loads (e.g. halogen or incandescent lamps, transformers). The control method is such that the same board can drive a universal motor. The user interface is either a touch sensor, a push button or a potentiometer. The board contains a minimum of components therefore saving cost and space. The auxiliary supply is derived from the voltage across the triac.
Power control
The output power is controlled by the phase delay of the triac drive. In classical designs, the delay is refered to the zero crossing of the line voltage. The detection of the zero voltage normally requires an additional connection to the mains neutral. In order to avoid this connection and connect the circuit directly in series with the load, the trigger delay is referred to the previous zero crossing of the current (fig.1 ).
-AN-3-9-2-/0-5-91--------------------- ~~~~@~g~~~~~~ ---------------------------1/-9
929
APPLICATION NOTE
BOARD OPERATION (Continued) Figure 1. The·Power Control Is Based On The Monitoring Of The Zero Crossing Of The Current
Vpeak 2 Power
~ 2Z td 10 ms
V line VAK IA
Mains synchronisation
When the current in the triac is zero, the mains voltage is re-applied across the triac. Synchronisation is achieved by measuring this voltage. This voltage is monitored in each halfwave, which allows the detection of spurious open load conditions. The triac is retrigged with multipulse operation if it is not latched after the first gate pulse.
Changing operation from 50Hz to 60Hz can be achieved by making simple modifications to the microcontroller EPROM/ROM table defining the triac conduction angle versus the power level.
Operation with a transformer
Low power halogen spots use low voltage lamps (12V typ.) usually supplied through a low voltage transformer. The light dimming of these lamps is simple with this circuit.
A phase lag between current and voltage as high as 90 does not disturb the circuit because the control method is based only on monitoring the zero current crossing.
The risk of saturation of the transformer core is avoided because the controller includes the following features: At the start, the delay time between the first gate pulse and the synchronisation instant is greater than 5ms. This limits the induction in the transformer and hence reduces the risk of saturation.
Figure 2. First Gate Pulse Delay
V line
/ /
td I
k/;r-
/A
I magn
Saturation of the transformer at start is avoided.
-2/-9-------------------------- ~~ii@~~~~~~©~ ----------------------------
930
APPLICATION NOTE
BOARD OPERATION (Continued) The circuit starts on a positive halfwave and stops on a negative halfwave (fig.3). So it starts with positive induction and stops after negative induction has been applied. This helps to minimize the size of the magnetic material.
Figure 3. Hysteresis Cycle in off/start/stop Phases
B
Imagn
STOP
The timer is very precisely tuned in order to obtain precisely 1Oms delay between two gate pulses. As a result, the triac is driven symetrically in both phases so continuous voltage in the transformer is avoided. The voltage across the triac is monitored in order to detect a spurious open load condition on the secondary of the transformer. The inrush current at the turn-on of a lamp (halogen or incandescent) is also reduced due to the soft start feature of the circuit (fig.B).
Triac drive
The triac is mUlti-pulse driven. Therefore, inductive loads can be driven without the use of long pulse drives. As a result, the consumption on the +SV supply can be minimized and the supply circuit made very small.
The pulse driving the triac is SOflS long. The LOGIC
LEVEL triac is driven in quadrants 011 and 0111 with
a gate current of 20mA provided by two I/O bits of the ST621 0 in parallel. The LOGIC LEVEL triac has a maximum specified gate triggering current of 10 mA at 2S'C.
Before supplying the first drive pulse, the triac voltage is tested. If no voltage is detected, a spurious open load or a supply disconnection is assumed to have occured and the circuit is stopped.
After the first driving pulse, the triac voltage is monitored again. If the triac is not ON, another pulse is sent. The same process can be repeated up to four times. Thereafter, if the triac is not ON, the circuit is switched off.
User Interfaces
There are three different user interfaces: a touch control,.a push button or a potentiometer. Four modes can be selected on the board in order to define how the transmitted power is related to the user interface.
Three modes operate with the touch sensor or the push button. Dimming is obtained when the sensor or the button is touched for more than 400 ms. If the touch duration is between 60 ms and 400 ms, the circuit is switched on or off. A contact of less than 60 ms has no effect. Modes 1,2,3 differ in the way the ouput power is influenced by the contact on the sensor or on the button.
Mode 4 directly relates the transmitted power to the position of the potentiometer (fig.4).
All modes include a soft start function.
------------- @
~~~@m~~~~~©~
---
-
-
3/9
--------
931
APPLICATION NOTE BOARD OPERATION (Continued) Figure 4. User Interface
Sensor version
Sensor D'--'--'-----~~s=l---+-----'--r--c;l------'-~--+--+-P~t
Pmax I ~--l...
Mode 1 I
potentiometer version
Mode 4
P Pmax
Pmax
Mode 2
I
I
I
I I II II
U:Hi} ~ Pmax
I Mode 3
I
I
..
t
Vpot
I
VDD
Sensor Contact Duration Mode 1 Mode 2 Mode 3
< GOms No effect No effect No effect
GOms to 400ms
> 400ms
Switched ON to full power or switched OFF
Same sense of variation as previous action
Switched ON to previous level or Opposite sense of variation to
switched OFF
previous. action
Switched ON to full power or switched OFF
Opposite sense of variation to previous action
4/9
-------------
1~ It.""!1
SiliGlDS©IR-'T@~H~~©O1l0M0@[S1!OD©iNl'
-------------
932
~
",(II
Ill~
@.
~:i!
!,!O
~~
~O i!;lz
CD W W
t0o1
FUSE LINE
100 A2
BTA 08-600SW
LOAD
+5V 100k
~ ::
MODE
F~13 PB2 1? PB3
OV
I11 PB4
220k
10 I P85
I 14
P81
~NMI
TEST 6 20
vss
3 x 4.7M
:!! cra:::
oOJ
:t>
til :o0
!J1 o
Q t=l
§:
m"tI
:0
~
o
Qi' ca
5 z
TOUCH SENSOR
iil 3
(3 o
;s:t·
c
.CeD ,
1~ PUSH BUnON
OV
+5V
220k·
O;Dog:".M"
220k
- y 18p
OV
OV
POTENTIOMETER
OV
»
"'C
100u
r"'C-
6.3V
(;
~
1N4148
All resistors 1!4W unless otherwise specified
5 z
z
S
m
APPLICATION NOTE
HARDWARE
The circuit uses an Sbit MCU ST621 0 and a LOGIC LEVEL triac directly driven by the MCU (fig.5). It operates with 3 user interfaces, 4 modes of operation and 4 kinds of loads. When the board is dimming a resistive load, an RFI filter must be used in order to meet RFI standards (eg. VDE S75).
The ST621 0 includes 2K ROM, 64 bytes RAM, an Sbit AID converter that can be connected to eight different inputs, 4 I/O ports with 1OmA sink current capability and a timer. Hysteresis protection is included in series with each I/O pin. The ST621 0 is packaged in PDIP or SMD packages. The ports, timer and interrupts configurations can be chosen by software, providing great flexibility. With EPROM and OTP versions, the equipment development and preproduction can be carried out directly from the design lab thus providing a fast time to market.
The LOGIC LEVEL triac (BTAOS-600SW) has been especially designed to operate with MCUs. It is a sensitive triac (IGT=10 mA, IL=50 mAl trigged in quadrants QII and Qili. In this application it is driven by two I/O bits of the ST621 0 in parallel. This triac has high switching capabilities ([dl/dtjc=3.5 Alms), ([dV/dtjc=50 V/IlS), so in this circuit, it can operate without a snubber.
Total consumption of the board is less than 3mA with an SMHz oscillator. The board receives its supply only when the triac is off. So a minimum off time of the triac (2ms) is necessary to ensure its supply.
The 5V supply capacitance is mounted as near as possible to the MCU with very short interconnecting tracks in order to maximize the RFI/EMI immunity.
The touch sensor is a voltage divider between line and neutral potentials. It operates when the supply of the circuit is connected at the line potential and not at the neutral. The user is protected from electrical shock by a very high impedance (10Mn ) connecting the sensor to the circuit.
SOFTWARE
All the features are included in a 700 byte program. More than 1kbyte of ROM is available for additional features. The architecture of the software is modular in order to provide maximum flexibility.
The table relating the delay time to the power requirement contains 64 different levels. The conduction time of the triac can vary from 2ms to Sms. The user can easily adjust the minimum and maximum power levels because the corresponding delay times change with smaller increments at the top and bottom of the table.
The table can be easily modified in the ROM/EPROM space to meet different conditions e.g. 60Hz operation or varying loads.
Software versions cover the four user interface modes of operation without hardware change.
All inputs are digitally filtered, so that an input is valid only if it remains constant for 1OilS or more. This reduces the number of passive components required.
'The mains supply carries disturbances (e.g. glitches, telecommand signals) which can disturb the triac drive and generate lamp flickering. For this
Figure 6. Internal Timer Operation
~
N
01
II
10
4 ;1;
2
Vtriac
N . 01
line synchro
II
I 0
3 ,4,1, 2
gate drive timer modes
-- 6/9 ------------ ~ ~ii@mi~:~~©~ - - - - - - - - - - - - -
934
APPLICATION NOTE
SOFTWARE (Continued)
reason, the triac voltage is not used directly as the synchronisation parameter. The timing is carried out internally by the MCU timer. The period of operation can be slowly modified to follow the variations of the mains frequency but not the spurious disturbances. The mains synchronization signal is received every cycle. The corresponding mains period is measured and compared to the internal timer period. If a difference remains for a long time, the timer period is modified to follow the mains. This block acts like a low band filter which saves external filtering components. Each 50Hz period, the timer operation is separated in four steps (fig.6). The triac voltage synchronisation can only be validated during phase 4.
The software has been written with modular blocks (fig.?). It can be enlarged to other applications such as motor speed regulation, telecommand input or IR remote control with additional blocks.
Figure 7. Major Steps of the Software
PRACTICAL RESULTS Figure 8 shows the soft start operation with a halogen lamp operating from the secondary of a low voltage transformer and with a tungsten filament lamp. Figure 8. Soft Start With Lamps
Halogen tamp at the secondary of a transfonner
Triac anode current: 1A/div 200msJdiv Incandescent lamp
Initialization Read version
Line synchronization Sensor acquisition Power level requirement Delay time td1 in timer Calculation next delay Triac firing Delay time td2 in timer Calculation next delay Triac firing Delay time td3 in timer Delay time td4 in timer
Figure 9. Universal Motor Drive
Triac voltage VAK : 200V/div 2ms/div
0 f ---\ --- -
.r ""-.....
0
"-
V
./"
"-
Triac anode current: 2A!div 2ms/div
----------------
&r:'1=1-1=
SifJGD©ISiiI.@1~~H~©IOIIiMi1@SIi[OD©iN!'
7/9 ----------------
935
APPLICATION NOTE
PRACTICAL RESULTS (Continued)
Due to the soft start, the peak in-rush current is about 3 times the. nominal current compared with 10 to 15 times without soft start. This extends the lamp life time and prevents the input fuse· from blowing.
The figure 9 shows the current and voltage in a triac driving a universal motor.
SUMMARY
Microcontrollers (MCU) are in common use in most areas of electronics. They now penetrate the very cost sensitive arena of home appliance applications.
The application described in this paper shows that enhanced appliance circuits can be designed with fast prototyping time using a ST621 0 MCU and a BTA08-600SW LOGIC LEVEL triac. These circuits are low cost and provide more features with less components than classical solutions.
The circuit presented is an enhanced light dimmer operating from the 120V/240V mains. It drives
incandescent and halogen lamps supplied either directly from the mains or through a low voltage transformer. The same circuit can also drive· a universal motor. It includes soft start and protection features. Different user interfaces can be chosen: touch sensor, push button or potentiometer.
All this is achieved with only few components: a ST621 0 MCU in PDIP/PSO package with a BTA08600SW LOGIC LEVEL triac in T0220 package and some passive components.
Additional features like presence detection, IR remote control, homebus interface, motor speed control or 60Hz operation can be implemented from the existing solution.
Bibliography
Thyristors and triacs application manual 1989 Microcontroller based universal motor speed control . M.Queroll SGS-Thomson Microelectronics
Application Note:
Universal Motor Speed Control I P.Rault + Y.Bahout I SGS-THOMSON Microelectronics
-- 8/9 ------------ Fii ~i~@m~~l~~©~ --------------
936
APPLICATION NOTE
ANNEX: Choice of a triac driven by a MCU.
When the software includes a soft start, the inrush current in the load and therefore the current rating in the triac can be reduced.
When using a LOGIC LEVEL or a SNUBBERLESS triac the current rating of the triac can be reduced, keeping fast commutation characteristics. For instance, a LOGIC LEVEL triac BTA08-600SW can drive a 600W lamp and a SNUBBERLESS triac BTA10-600BWa 1200W universal motor.
LOGIC LEVEL triacs are optimized on the drive view point. Therefore they can be driven directly by the ST621X 1/0.
SNUBBERLESS triacs are optimized on the power view point, so they can drive loads which generate very strong dynamic contraints.
These triacs are specified in a way that their behaviour can be pre-determined. The tables below present with two examples the relation between the major application constraints and the key parameters of the triac.
LIGHT DIMMER
Constraint
Simple Drive No flicker
Max power on the load Max inrush current No flashing (1)
Flash over (filament failure)
Key parameters on a LOGIC LEVEL triac BTAOB-600 SW
IGT=10mA - VGT=1.SV IH = 2SmA IRMS = BA
(dl/dt)c = 4.SA!ms ITSM = BOA
Note1: When the lamp is cold (start or low light intensity), there must not be spurious turn· on of the triac (flashing) due to a high commutation dl/dl.
UNIVERSAL MOTOR DRIVE Constraint Simple drive
Max. start current Max. power on the load
Fuse sizing
Key parameters on a SNUBBERLESS triac BTA10-600 BW
IGT = SOmA - VGT = 1.SV
ITSM = 100A IRMS = lOA (dl/dtlc = 9A!ms dV/dt = SOOV/~s
12t = SOA2.s
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_ _ _ _ _ _ _ _ _ _ _9_/9
937
APPLICATION NOTE
TRIAC CONTROL BY PULSE TRANSFORMER
Ph. Rabier
Among the many ways to drive a triac the pulse transformer is one of the easiest. By applYing some simple rules it can be used to design an efficient triac triggering circuit without reduction of the commutation capability of the triac.
I. WHY USE A PULSE TRANSFORMER?
The use of pulse transformers in triac triggering circuits offers many advantages:
41 The area of the output pulse:
For a given magnetic material the voltage.time product Vo.to of the output pulse is constant. For each type of transformer the manufacturer gives the maximum voltage.time product under no load operation which corresponds to the figure 1.
51 The rise time tr :
This parameter tr defines the rise time of the output pulse as shown in figure 2.
-galvanic insulation between the power and gate drive circuit (a few kV).
-gate drive circuit with a few components.
-choice of the ~ate current polarity (triggering in the 2n and 3rd quadrants for SNUBBERLESS triacs).
Figure 1 : Voltage across the secondary winding for a rectangular pulse across the primary.
VS Vo
-optimization of gate signal (single pulse or train of pulses).
-possibility to drive several triacs with only one drive circuit
Vo/2
~
to
.. I
1
II. THE PULSE TRANSFORMER:
To optimize the triac and the pulse transformer in the application it is necessary to know the main characteristics of the transformer:
1I The transformer ratio: It is the N2/N1 ratio, where N1 corresponds to the primary winding and N2 to the secondary.
21 The Lp inductance: the primary winding inductance measured at a given frequency.
31 The Rp resistance: The primary winding resistance· .
Figure 2 : Specification of the rise time at the output of the transformer.
VS Vo G.7Vo
AN436/0592
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939
APPLICATION NOTE
Figure 3: Equivalent diagram of the transformer.
U N2/N1
The figure 3 shows the diagram of the secondary of the transformer:
11 Thecommutation .
Review: during the conduction a certain quantity of charges is injected into the triac. During the fall of the current most of them disappear by recombination. If the current decreases too fast the charges do not have time to recombine and some charge stays in the gate area. This can provoke a spurious firing.
The parameter which characterizes the commutation is the anode current slope (di/dt)c, that is to say the slope of current before zero crossing.
The specified value in the data sheet is the critical (di/dt)c. Above this value the triac is liable to fire spuriously. Figure 5 shows the spurious firing due to (di/dt)c.
III. GATE PULSE:
11 peak yalue .
The transformer ratio and the power supply of the primary winding define the secondary voltage. With the equivalent diagram and triac gate characteristics it is possible to determine the output current. This has to be higher than the specified gate triggering current (IGT). To have an efficient triggering it is suitable to use a safety coefficient of 2 :
IG > 2 IGT
21 Duration'
The Vo.to product defines the maximum pulse duration at the output of the transformer. The anode current has to be higher than the specified latching current (IL) at the end of the gate pulse. For drives with a pulse train we can sometimes use very short pulses ( for example tp =1 OilS with a 151ls cycle ).
For proper triac triggering the gate current rise time is very important in a circuit with very high dildt (>20 AlIlS) : case of resistive load.
IV. THE COMMUTATION:
The use of a triac with a pulse transformer neeqs some precautions in order not to decrease the commutation capability.
21 Case of a triac triggered by a transformer' When the triac is on, a voltage of about 0.6 V appears across the gate and cathode. This voltage is either positive or negative depending on the anode current polarity. A current i can flow through the secondary winding of the transformer (see figure 4). Due to the inductance of the transformer, at the end of the half wave the current i continues to flow in the gate and increases the risk of spurious firing at the next cycle. (figure 5).
Figure 4 : Use of a triac with a pulse transformeur : when the Triac is on a current i flows through the gate.
IA
~
I l§l
t II .. VGK
940
APPLICATION NOTE
Figure 5: Spurious firing of the triac. spurious firing
I ANODE
- 5A1div o ..--. .'-
.-
-'-
",-...
'-
VAK
::~~:;,:~ .lm~
The influence of the transformer can be estimated by measuring the critical (di/dt)c of the triac with and without the transformer.
Example : BTA06-400CW
The specified (di/dt)c of this triac is :
3.5 Alms min at Tj = 125°C
Measurement of a sample without transformer:
(di/dt)c = 6 Alms
Measurement with transformer:
(di/dt)c = 3 Alms -7 on this sample the commutation capability is divided by 2 !
It is necessary to consider this phenomena and to take some safety margin (in some cases the critical (di/dt)c of the triac + transformer can be lower than the specified (di/dt)c of the triac as shown in the previous example). This is very important in the case of transient currents higher than the nominal value, as is the case with the cold filament of incandescent lamp, load dispersion, etc ...
One has to take into account the maximum (di/dt)c in the application in all cases, especially in the transient state where (di/dt)c can be higher than it is in the steady state. The following example shows values for an incandescent lamp and universal motor.
NOMINAL CURRENT IARMS
STEADY STATE
I (di/dt)c
TRANSIENT STATE
I (di/dt)c
INCANDESCENT LAMP 1.35 A
0.6 Alms
2.6 Alms
UNIVERSAL MOTOR 3.8 A
1.7 Alms
5 Alms
V. THE SOLUTION:
To avoid the reinjected current through the transformer it is necessary to connect a diode in series with the gate (figure 6).
The drop voltage VF of the diode avoid the reinjected current. The triac is triggering in the 2nd and 3rd quadrants (figure 7).
Figure 6 : Bearing of the commutation capability.
IA
VF
I
~-=------.-_;1L-- VAK
]
- - - - - - - - - - - - - Jb."Y1l ~i~~jmg~~~~~ - - - - - - - - - - - - -3/5
941
APPLICATION NOTE Figure 7 : Correct running with diode.
no spurious firing
Figure 9: Equivalent diagram.
(Rp+R1)(N2/N1) Lp(N2IN1) 2
VF VGK
Figure 8: Typical application diagram.
given by the following
220V
VI. TYPICAL APPLICATION EXAMPLE: The D2 transil diode protects the triac against overvoltages (see "Protection of triacs and their control circuits" in the "Thyristors and Triacs Application manual"). The RC circuit across R1 allows an increase in the current in the transformer at the beginning of the pulse. When C is charged the resistance R1 limits the current through the transistor.
Where: tp is the pulse duration
Keep in mind that VGK is negative because the triac is triggering in the 2nd and 3rd quadrants.
In practice the area of the pulse has to be lower than 60 or 70% of the maximum voltage.time product Vo.to.
The maximum pulse duration in the output is : t _ 0.7 VO.to p- VF- VGK
These two formulae allow us to define the pulse transformer according to the triac sensitivity.
Example . Numerical application with a transformer having the following characteristics:
N2/N1 = 1
Lp = 2.5 mH
Rp = 0.6 Ohm
Vo.to = 250 VllS
Triac: BTA08-700CW
IGT = 35 mA VGK = -2 V at IG = 2 IGT (quadants II and III)
4/5
------------jI,-yl
~itmi~~~'------------
942
diode: VF = 0.7 V
power supply:
U = 12 V
R1 = 100 Ohms
tp max = 65 fls
IG = 70 mA
t = 21 fls
We have measured :
IG = 85 mA at t = 21 fls
APPLICATION NOTE
VII. CONCLUSION:
The pulse transformer provides an excellent method to trigger a triac when galvanic insulation is required. This system is appropriate to microprocessor systems.
Nevertheless it needs some precautions to avoid a decrease of the triac commutation behavior. This precaution is achieved by adding a diode in series with the gate.
- - - - - - - - - - - - - iA."!l ~i~@mgm~~~~~ - - - - - - - - - - - - -515
943
APPLICATION NOTE
NEW TRIACS IS THE SNUBBER CIRCUIT NECESSARY?
On inductive load triacs are designed with RC snubber : these commutation aid networks are
badly optimized in most of applications.
T. Castagnet
Figure 1 : Synoptic of application circuit with triac.
The subject of this paper is, first of all, to analyze the functions of snubber circuits for triacs and to propose calculation methods.
LOAD
But today snubber circuits must be reconsidered by taking into account the progress of the triac technology. This article explains how it is now possible to reduce or to eliminate the snubber, and thus simplify the AC switch function, thanks to the high performance in commutation of the SNUBBERLESSTM triacs.
MAINS
INTRODUCTION:
The triac is today the only bidirectional device able to control various loads supplied by the domestic and industrial mains. It is often designed with a network made of a resistor R and a capacitor C, the SNUBBER circuil.
This circuit improves the operation of the triac in its environment but what is its real function?
USE OF THE SNUBBER CIRCUIT ASSOCIATED WITH TRIACS.
The main function of this circuit is to improve the switching behavior of the triac at turn off : we will explain how and suggest some methods to define il.
DESCRIPTION OF THE TRIAC COMMUTATION.
The triac is a device similar to two SCR back to back with a common control area. At turn off the commutation of the triac is the transient phase during which the load current is passing through zero and the circuit voltage is reapplied to its terminals.
Figure 2 : Example of triac structure and its equivalent simplified circuit.
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945
APPLICATION NOTE
Figure 3 : Commutation on inductive load of BTB10-600BW
'"I···· !",L-"
.... t- ;.- $
I
---- !
----t!--
I
-
-j----
TRIAC VOLTAGE 100V/DIV
~
ov :!
~
.._.
"- ;?
OA TRIAC CURRENT 50mAIDIV
, - .
... .... ....
:t
" ~
TIME = 20~s1D1V
-----
CAPACITIVE
Tj= 125°C; dlT/dt = 2.3A/ms dV/dt 21VJJ.1s-------- CURRENT
PARAMETERS OF COMMUTATION.
For a given device and a determined junction temperature the risk of a spurious firing is possible. It is linked to:
The rate of removal of the triac current dlTfdt before zero crossing because it determines the quantity of stored carriers which could be injected in the gate area or the opposite thyr· istor;
The rate of rise of the reapplied triac voltage, dVfdt, which creates a current through the gate because of the junction capacitance.
The parameters which characterize the perform· ance of the triac commutation are the critical rate of removal of the current (dlldt}c and the critical rate of rise of voltage, (dVfdt)c : above these values the triac fires again spontaneously.
Figure 4 : Spurious firing at commutation for a BTB06-600S
TRIAC
~~~~..-., 4..-...~..~. \-..+..~...-..+..-..1..-.1~...¥..~. .}. ~~?J
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""tv
f-++-t-+-+--j\."\,~c-+-+--j TIME =
~
20~s/DIV
~+-~-4-r-~-+-~~r-~--1
........................ \ ........ " " ..... TRIAC
l'.. CURRENT I . . ~~~~~~~~~--~ ~ 50mAIDIV
Tj = 100°C; dlT/dt = 1.SA/ms dV/dt = 17V/~s
MAIN HYPOTHESIS ON COMMUTATION:
The analysis ot' commutation shows that:
At turn off a recovery current, IR,appears commonly when dlTfdt > 0.1 x (dlfdt}c; (see fig.3).
The circuit voltage Va is reapplied to the device when IT = IR;
The spurious firing is possible as far as there is a reverse current (made of recovery or Capacitive current) : mean while each dVfdt is able to provoke the triac refiring; (see fig. 4).
Figure 5 : Application circuit (a) and its equivalent diagram at commutation (b).
R
c
(a)
(b)
AIM OF THE SNUBBER CIRCUIT.
The today method to choose a triac on inductive load consists in :
- selecting one triac with RMS current, ITRMs, suitable with dlTfdt of circuit ; because for conventional triac the specified (dlldt)c values is linked to the current rating by the relation:
(dlldt)c= 2x I1 x fx -ffxITRMS
This value must be higher than dlTfdt of circuit.
- limiting the maximum reapplied dVfdt below the specified value (dVfdt)c·: this is the main function of the snubber circuit.
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946
APPLICATION NOTE
CHOICE OF THE SNUBBER CIRCUIT.
The aid circuit makes up a resonant circuit with the load. At turn off it limits the slope of reapplied voltage dV/dt but generates an overvoltage VM. Its choice results of a compromise in order to respect triac specification ((dV/dt)c and repetitive peak off state voltage (VORM).There are two possibilities:
11 for low VORM the resonant circuit must be damped, reducing VM and dV/dt- (§ 2 of annex) ;
21 with higher voltage possibilities the circuit can oscillate and the capacitor adjusts straightly the dV/dt (§ 3 of annex)
Today we use commonly triacs with VORM = 600 V or more. Therefore we suggest the second way because capacitor is smaller (reduced 4 times).
THE DISADVANTAGES OF THE SNUBBER CIRCUIT.
The snubber circuit improves the triac behavior but it imposes to the device stresses which limit its use.
At turn on the discharge of the capacitor creates a pulse current with high repetitive dlT/dt which can destroy the triac by local overheating near the gate. It is recommended to limit the amplitude of current with a resistor higher than 50 Ohms and the turn on dl/dt below 20 Nils.
Figure 6 : Triac turn on with snubber circuit
IT
R
c
Jl
The current, which flows through the snubber circuit when the triac is off decreases the off state quality of the switch : this leakage current (several mAl could create problems for small loads like electro-valves, micro motors .......
PROGRESS MADE ON TRIACS. PREDOMINANCE OF (dl/dt)c AND LIMITATION OF dV/dt :
The study of the commutation behavior of triac can be made thanks to the curve of the critical commutation performance of each sample (dlldt)c versus various reapplied (dV/dt)c.
Figure 7 : Critical (dl/dt)c versus (dV/dt)c for BTB10-600B sample
dlTldt (Alms)
............
10 C
dVldt
(VI~s)
- d -AREA OF SPURIOUS~FIAING AT ~OM~UTATION
For a conventional triac (IGT > 25 mAl the critical (dlldt)c is not much sensitive to the (dV/dt)c : so it represents the most significant parameter to characterize the triac behavior in commutation (fig.7). Without snubber circuit the (dV/dt)c is limited by the junction capacitance of the triac (point C).
In order to improve commutation behavior of triac and to eliminate the snubber circuit the parameter (dlldt)c has to be increased on all range of dV/dt.
We also notice the efficiency of the snubber circuit in commutation -(dlldt)c- is lower than two by reduction of dV/dt from its natural limitation ( point C ) to 0.1 V/IlS.
PERFORMANCES OF THE SNUBBERLESS TRIACS:
This analysis permitted the development of new. triacs with better performances in commutation : the SNUBBERLESS triacs which have got a new design with improved triggering mechanism and better decoupling of single integrated thyristors.
_ _ _ _ _ _ _ _ _ _ _ r.=-=
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_ _ _ _ _ _ _ _ _ _ _3_17
947
APPLICATION NOTE
For same size and gate sensitivity the improvement ratio on (dlldt)c is higher than 3.
Figure 8 : Comparison between conventional and snubberless 10 A
, triacs.
dlT/dt (Alms)
Tj= Tj max,
53D0 "-""'-~ __~_________________
20,
, -
.......
,
>3TIMES
,
10 5
---- - . _ . _ . _ . _ . _ . _ .
3
2 conventional
snubberless
1 _ k-~ _~~_ _~_ _~~~~~~ 0,1 0,2 0,5 1 2 5 10 20 50 100
dV/dt (V/us)
So we can specify now the commutation behavior with (dlldt)c for a value dV/dt from 0 to its
natural limitation by the junction capacitance (without snubber circuit),
Table 1 : Commutation specification (dl/dt)c of some SNUBBERLESS triacs (Alms)
CURRENT RANGE (A)
TRIAC SUFFIX AW BW CW
dl/dt on 50Hz sine pulse (Alms)
6
8
5
3.5
2,7
10
12
9
5.5
4.4
16
21
14 8.5
7
25
33 22 13
11.1
CONSEQUENCES ON APPLICATION CIRCUlTS:
The SNUBBERLESS triacs offer application ad.vantages:
- The function of commutation aid of the snubber circuit disappears : we can remove it ;
- In application the dlT/dt through the triac is not adjustable because it is given by the circuit (Va and L) ; its measure permits the choice of this triac with the commutation parameter, (dlldt)c.
- The commutation behavior is no more straightly linked to the current range and the high (dlldt)c allows a reduction of the die size, For example a universal motor of 1200 W - 220 V can be driven by a BTB 10-600 BW (*) instead of the BTB15-600B(**).
(*) 10 Amps SNUBBERLESS triac with VORM = 600 V and IGT = 50 mA; specified at 9 Nms without snubber. (**) 15 Amps conventional triac with VORM = 600 V and IGT = 50 mA; specified at 6.7Nms with dV/dt limited to 10 V/IlS.
IS IT ALWAYS POSSIBLE TO REMOVE THE SNUBBER CIRCUIT?
The answer is not in the affirmative because sometirnes it has other functions:
- improvement of the triac immunity against transients in the off state ;
- compensation of latching current at turn on (not dealt in this paper).
Switching on and voltage perturbations can provoke overvoltages and fast voltage variations across the triac:
- this one could break over when the overvoltages are higher than its repetitive peak off state voltage, VORM ; - due to the junction capacitance fast voltage variations create a gate current and could trigger the triac; the device limit is the rate of rise of the off-state voltage, dVIdt.
The snubber circuit can improve the triac behavior in off-state. But its efficiency is linked to the values of series inductance L at the oscillation frequency of perturbations (typically 100 kHz).
We could add a saturable inductor in series with the triac when L is too low : particularly this is the case of resistive load.
IMPROVEMENT OF THE IMMUNITY TO TRANSIENT VOLTAGES (STATIC DV/DT) :
When the circuit has its specific overvoltage suppressor, as clamping diodes (TRANSIL), the aim of the snubber circuit is to reduce only dV/dt for
-4/7- - - - - - - - - - - - J..'Yl. ~i~~mYml~~~~ - - - - - - - - - - - - -
948
APPLICATION NOTE
triac voltage lower than VDRM. It must be damped, limiting its overvoltage and the current in the suppressor. The § 2 of annex permits to choose the values:
R< 0.8x Lx (d%t)IVDRM
For a 1200 W motor with L (100 kHz) # 5 mH a BTB10-600BW triac needs a snubber circuit of 3.3 kQ and 1 nF (fig.8).
Figure 9 : Example of improved off-state immunity for triac
PROTEC,TION AGAINSTOVERVOLTAGES:
The snubber circuit could be a simple circuit in order to reduce overvoltage VM. It must operate as a low pass filter with minimum resistance (50 Ohms) avoiding turn on current stresses.
Figure 10 : Snubber circuit efficiency against overvoltage Vpp (Triac voltage<600V)
vpp (V) 1.500
1.000
VDRM
r-- ~
500
k ~
V
R",,500hms
,
,/
jf\ '0>
VPP!2~
~
150
tlo's)
5 7 10
JL.C .10E 5 (s)
Figure 10 shows the maximum allowed overvoltage Vp versus ;j LxC remaining the triac voltage below 600 V.
But the efficiency of this circuit is poor and we prefer use other ways of overvoltage protection : input filters and suppressor (see fig.8).
CONCLUSION: Used today as commutation aid network the snubber circuit can be well optimized thanks to higher blocking voltage VDRM : we obtain a reduction of the capacitor size.
But with the SNUBBERLESS triacs the aid function of the snubber circuit disappears. Because of the improvement of the commutation performance ( higher critical (dl/dt)c ) these new triacs offer a cost reduction by decreasing of their size, and permit to eliminate the snubber circuit in most of applications.
However the snubber circuit, associed to series inductance, could limit the off state voltage variations. But its efficiency against overvoltages is poor and we prefer to replace it by specific protection devices.
REFERENCES: - Improvement in the triac commutation 1989. P.RAULT SGS THOMSON-Microelectronics.
- Analysis and design of snubber networks for dv/dt suppression in triac circuits (RCA) AN 4745 - 1971 JE WOJSLAWOWICZ.
- For energy conversion and motor control triacs or alternistors.
Pierre RAULT and Jean Marie PETER THOMSON CSF for PCI September 1982.
------------- -------------1t."1l ~~~@m~m~~~©~
5/7
949
APPLICATION NOTE
Annex:
DETERMINATION OF THE COMPONENTS OF SNUBBER CIRCUIT.
· 1 - SNUBBER CIRCUIT OPERATION The load inductance L and the snubber circuit make up a resonant circuit across which the mains voltage is reapplied at turn off. The RC circuit limits dV/dt but generates an overvoltage VM which must be lower than VORM.
We can analyse VM and (dV/dt)max with their relative parameter versus the damping factor F :
Figure A1 :overvoltage (e) versus damping factor F.
e
r---...
.9
't---
. S
.7
'\
.6
\
.S
.4
'\
.3
f\
.2
.! !
.01
.05 .1
'----- r
.5
!O
Figure A2 : rise slope (0) versus damping factor F.
500
'00
100 50
/
!
.5
V
1
,.05
.0
.0 1
.Cl5 .f.
.5
5 10
e = VMIVa
o = R x C x ( d\fdt )MAXI Va
F = Rx -VCIU2
These curves show there are two intervalles where variations if F -due to the tolerance of tile components- don't almost modify the overvoltage value:
F> 0.5 and F < 0.1
Therefore these are the two methods in order to choose the snubber circuit.
· 2 - DETERMINATION OF THE SNUBBER CIRCUIT WHEN F > 0.5 :
VM is limited first of all (e < 1.3) thanks to the capacitor C ; the resistance R sets the slope (dV/dt)max .
R x {Cif/2> 0.5 and ( d\fdt)c > Va X RIL
However F must be low (F = 1) in order to reduce the capacitor and the resistor dissipation power PR :
C>4 x( Va)2/(L x (d\fdt)C 2 )
and
R< Lx (d\fdt )ciVa
with
PR < 2.C.Va2.f VMNa < 1.2 Va = Vac X {2 x sin<\> Vac = RMS mains voltage f = mains frequency
cos<\> = power factor of load L = inductance of load when zero crossing r = resistance of load
An inductive load of 2000 VA - cos<\> = 0.6 on 220 V-50 Hz mains can be controlled with a
-6/7- - - - - - - - - - - - ..."l ~i~~m~ll~~@~-------------
950
APPLICATION NOTE
triac specified @ (dV/dt)c = 10 V/',lS by using:
C = 30 nF and R = 3.5 kOhms
with L = 100 mH r = 40 Ohms PR = 0.23 W VM = 332 V (choose a triac with VORM = 400 V)
· 3 - DETERMINATION OF THE SNUBBER CIRUIT F< 0.1 :
dV/dt is optimized first of all (0 < 0.18) thanks to the capacitance C ; VM is only set by the resistance R :
Rx;/C/L/2<0.1 and (d%tlc>Va/(LxC)
The resistance value has to keep a sufficient value (F = 0.05) in order to limit stresses on triac at turn on (see 1.5)
and
R+ r< 0.1 x L x (d%t )clVa
with PR < 2.C.Va2.f e = VMNa <1.9 Va = Vac x;)2 x sin<jl
With the same load 2000 VA - cos<jl = 0.6 on 220 V-50 Hz mains and with the same triac:
C - 10 nF and R - 300 Ohms
PR = 0.08 W VM = 525V (choose a triac with VORM=600 V)
· 4 - COMMENTS: Today the triac offers blocking voltage VORM up to 800 V : so we suggest the second method because the capacitor is smaller, (reduced by 4) and the reapplied slope dV/dt is less sensitive to damping factor variation and so better controlled.
These values obtained by calculation are slightly overrated because the real slope of the reapplied voltage is limited also by the junction capacitance of triac.
- - - - - - - - - - J , . , , , . SGS-mOMSOM _ _ _ _ _ _ _ _ _ _7_17 ·J, . IR:IU©Ilil@Il!~m©lIllil@li(i]u:Gi0 951
APPLICATION NOTE
TRIAC + MICROCONTROLLER SAFETY PRECAUTIONS FOR DEVELOPMENT TOOL
Ph. Rabier
The goal of this paper is to analyse the different ways to configure a micro-controller and a development tool during the debbugging phase. The major problem is due to the direct connection of the computer I/O lines with the mains power. Some precautions have to be taken during the emulation in order to avoid destruction.
I - LOW COST POWER SUPPL V
In most low cost applications the step down transformer is not used and the power supply delivers low current, as shown for example in figure 1.
The consequence is that there is no insulation, the microcontroller is connected directly on the line!
When the software is emulated on the application board, the output port (RS232 port) of the computer is connected on the line via the emulator.
If some precaution is not taken "something" will be destroyed !
Figure 2 gives an example of an application using a triac and a microcontroller.
Figure 2 : Triac and microcontroller on the line.
Figure 1 : Uninsulated power supply.
ILINE
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ov
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Al G
A2 LOAD
In domestic appliance applications, one of the most important power switches is the triac.
The function of driving the triac becomes more and more complex. For this reason, microcontrollers are becoming more and more common. Furthermore, sensitive triacs with high commutation parameters, for example LOGIC LEVEL triacs can be triggered directly by the microcontroller without any buffer. Sensitive triacs and microcontrollers allow decrease in power consumption.
In this way the power supply can be optimized to reduce the cost. Optimisation can be achieved by removing the transformer.
In this case the micro-controller is supplied by an uninsulated +5 V power supply connected directly to the line, and a low level (OV) on the output ports of the micro-controller is needed to trigger the triac.
II - USE OF A DEVELOPMENT TOOL
During the debbuging phase, the micro-controller is removed and is replaced by the emulation probe. The circuit corresponding to the emulation phase of the previous example is shown in fig. 3.
The line is connected directly to the +5V of the emulator and a high (destructive) current can flow through the emulator and/or the computer.
AN438/0592
1/3
953
APPLICATION NOTE
Figure 3 : Circuit without protection (Beware: this circuit is dangerous).
.5V
Figure 5 : Optotriac drive.
100
LINE
LINE
(HIGH DESTRUCTIVE CURRENT)
III - INSULATED SYSTEM To avoid destruction of the development tool it is necessary to have an insulation between line and probe. This insulation can be achieved by optocouplers, pulse transformers, or insulation transformers. Figure 4 shows the topology of the most common insulation.
Figure 4 : Conventional insulation.
LINE
(Fram(lxlernal
inSulated powersupply)
POWER 1 DRIVE
The main advantage of a such system is the low cost of the optotriac, but it needs an isolated auxiliary power supply.
For a zero crossing optotriac, the triac is triggering with a gate current equal to the gate trigger current with a very low dlG/dt. This does not allow high dildt at turn on. That is to say the control of high .current resistive load is not recommended with this method.
21 The pulse transformer
Figure 6 shows the circuit with a triac and a pulse transformer.
The triac is working in the 2nd and 3rd quadrants.
Figure 6 : Pulse transformer insulation.
~~Ulse
·cstormer
LINE
11 Optotriac
Figure 5 shows the circuit with triac and optotriac.
The triac is working in the 1st and in the 3rd quadrants.
2/3
954
APPLICATION NOTE
This system is simple to use when the triac was initially driven by a buffer transistor, but it needs an external power supply. The high dlG/dt through the gate allows high current resistive loads to be driven. Due to the saturation of the magnetic material, this system cannot drive small loads because the gate current is cancelled before the latching current has been reached.
For more information refer to the application note "Triac control by pulse transformer".
3/ The line insulation transformer
In the previous examples,the insulation was between the triac and the microcontroller.
Figure 7: Insulation with transformers.
Another solution is to supply each equipment connected to the board from the mains through an insulation transformer.
If an oscilloscope is used, it also has to be separately insulated.
The main advantage of this system is that we do not need to modify the target system during the debbuging phase and it can be used with the microcontroller.
When a transformer is used between line and triac it should be noted that the line impedance is modified and then the behaviour of the triac, load and line set can be different (waveform of current).
IV - SUMMARY
New LOGIC LEVEL and SNUBBERLESS triacs can be connected directly to the microcontroller without buffers or insulation. Furthermore, low cost power supplies without a transformer are becoming more common. There is an increasing number of applications supplied directly from the mains, and the microcontroller is directly connected to it.
During the debbuging phase when connecting the development tool, a galvanic insulation is absolutely necessary.
This inSUlation can be done in 3 ways:
- With optotriacs : · Need modifications on the target system · Need external power supply
- With pulse transformer: · Need modifications (transistor to drive the pulse transformer) · Need an external power supply · Cannot drive small loads
- With insulation transformer: · No modification on the application board. · Modification of the line impedance due to the transformer between line and load.
Therefore a microcontroller operating on the mains with a triac may be directly connected to the line.
955
APPLICATION NOTE
IMPROVEMENT IN THE TRIAC COMMUTATION
P. Rault
In the last few years, the use of triacs has spread to all areas of electronics, including domestic appliances and industrial applications.
The use of triacs has been traditionally limited by their switching behavior in applications where there is a risk of spontaneous firing after conduction. In order to obtain the required reliability in today's equipment, the designer must take a certain number of precautions: over dimensioning of the device, switching aid networks (snubber), significant margin of security of the junction temperature,etc. This generally involves additional costs.
After a brief discussion of commutation problem when a triac is turned off, this article will describe the progress made in this area and the newest possibilities now offered to triac user thanks to the new series Logic Level and SNUBBERLES&M triac.
THE COMMUTATION PROBLEM OF THE TRIAC
In its electrical representation the triac can be compared to two thyristors mounted in anti-parallel and coupled with a control device which allows activation of this AC switch with only one gate (fig. 1a).
In considering the structure of a triac (fig. 1b), one notices that the conduction zones, corresponding to these two thyristors and which control the current in one direction and then in the other, narrowly overlap each other and the control zone.
During the conduction time, a certain quantity of charges is injected into the structure. The biggest part of these charges disappears by recombining during the fall of the current in the circuit, while another part is extracted at the moment of blocking by the inverse recovery current. Nonetheless an excess charge remains, particularly in the neighboring regions of the gate, which can provoke in certain cases the firing of the other conduction zone at the moment when the supply voltage of the circuit is reapplied across the triac. This is the problem of commutation.
For a given structure at a determined junction temperature, the switching behavior depends on:
11 The quantity of charges which remains at the moment when the current drops to zero. this number of charges is linked to the value of the current which was circulating in the triac approximately 100 microseconds before the cut-off. (This time corresponds to two or three times the life time of the minority carriers). Thus, the parameter to consider here will be the slope of the decreasing current which is called the commutating di/dt, or (di/dt)c. (fig. 2)
21 The speed at which the reapplied voltage increases at the moment when the triac turns off, which is called the commutating dv/dt, or (dv/dt)c. (fig. 2) A capacitive current, proportional to the (dv/dt)c, flows into the structure, and therefore injected charges are added to those coming from the previous conduction.
Figure 1 : (A) Simplified equivalent schematic of triac circuit. (8) Example of a triac structure.
AN439/0592
1/10
957
APPLICATION NOTE
Figure 2 : Triac voltage and current at commutation.
Ir (Triac current)
, , ,
Vr (Triac voltage)
Voltage in conducting Slate
CHARACTERIZATION
In order to characterize the switching behavior of a triac when it turns off, we consider a circuit in which we can vary the slope of the decrease in current (di/dt)c. In addition, we control the slope of the reapplied voltage by using, for example, a circuit of resistors and capacitors connected across triac to be measured. For a determined (dv/dt)c, we progressively increase the (di/dt)c until a certain level which provokes the spontaneous firing of the triac. This the critical (di/dt)c value.
Therefore, for different (dv/dt)c values, we note the critical (di/dt)c value for each sample. This makes possible to trace the curve of the commutation behavior of the triac under consideration.
Figure 3 represents the results obtained with a standard 12 Amp triac (lGT 50mA) and a sensitive gate, 6 Amp triac (lGT 10mA). For standard triacs the critical (di/dt)c is sightly modified when we vary the (dv/dt)c. For sensitive gate triacs, this parameter noticeably decreases when the slope of the reapplied voltage is increased.
Figure 3: Critical (di/dt)c versus (dv/dt)c (below the curve the triac turns on spontaneously.) A1 and A2 : The rate of re-application of the off-state voltage of these points corresponds to the mains
(sinusoidal wave form) at zero crossing. 81 and 82 : The (dv/dt)c is limited by a snubber at the values generally specified in the data sheets
(5V/lls or 10V/lls). C1 and C2 : These points are obtained without snubber.
W (dl/dt)c (Alms)
CRITICAL (dl/d~)c VERSUS (dV/d~)c
I
20 t--- ~-
Az
/ i I SAMPLE /11 1ZA TRIAC
10
J Vi '. 5 -r--
I" i""----
I'-;;- I I 1j=11QoC
:..... 2
r-.~ ~~z SAMPLE #2. 5EN51T1'11E TRIAC . c~··J
1
.1 .l!
.5
I
z
5 10 20 so 100 (dV/drlc (YljJ~)
-2/1-0 -----------~.,l ~~~@m~I~~~~~-------------
958
APPLICATION NOTE
In practice, the current wave form, and thus the (di/dt)c, is imposed by the circuit. Generally we cannot change it.
So, in triacs applications it is always necessary to know the (di/dt)c of the circuit in order to choose a triac with a suitable critical (di/dt)c. This is the most important parameter.
Suppose a circuit in which the (di/dt)c reaches 15 Alms. The triac N"1 characterized by the upper curve in figure 3 is not suitable in such a circuit even if the (dv/dt)c is reduced nearly to zero by connecting a huge snubber network across it.
APPLICATIONS IN BASIC CIRCUITS
When considering the constraints in commutation at the turn off of a triac, we can distinguish two cases:
1/ The use of a triac on resistive load (fig. 4)
In this case the current and the voltage are in phase. When the triac switches off (i.e. when the current drops to zero), the supply voltage is nullified at this instant and will increase across the triac according to the sinusoidal law:
V = Vm sinoot
Figure 4 : Current and voltage ware forms for resistive loads (A) Case On / Off switching (8) Case of phase control
IG,. """
I Triac
IGOo '/n""
. t
n0 0 0 r
I Triac
..t..
V Triac
. - , , ....
, ,
\ \
: \
.. :,,,..-
, \ \
\
r
, , I
I
'-~ Supply Voltage
(A)
V Triac (B)
-------------- -------------- &"'Yil ~~~~m~~~~~!S~
3/10
959
APPLICATION NOTE
Example:
For the European mains of Vrms = 220 volts at 50Hz, the slope will be:
(dv/dt)c = Vm x co = Vrms x -,f2 x co = 0.1 %8
This relatively low (dv/dt)c corresponds to points A1 and A2 on the curves in figure 3. As far as the (di/dt)c is concerned in the circuit, it depends on the load. For a resistance of loads Rand under a Vrms voltage, we will have:
(di/dt)c =Im x co =( Vrms x -,f2/R) x co
2/ The use of a triac on inductive load
In this case there is a phase lag between the current and the supply voltage (fig. 5).
When the currents drops to zero the triac turns off and the voltage is abruptly pushed to its terminals. To limit the speed of the increasing voltage, we generally use a resistive/capacitive network mounted in parallel with the triac. This "snubber" is calculated to limit the (dv/dt)c to 5 or 10 volts/1l8 according to the specified value in the data sheet. This case corresponds to points 81 and 82 in figure 3.The (di/dt)c is also determined in this case by load impedance (z) and the supply voltage.
Figure 5 : Current and voltage ware forms for inductance loads (A) Case On / Off switching (8) Case of phase control
I Triac
l"
o
"
I Triac
V Triac
, ,
\
. \
\
,
,
I
,
I
\ ,
\
'-' - ' I
"
Supply Voltage (A)
Cdl//dt)c
I
(B)
-4/1-0 - - - - - - - - - - L ' Y l ~~i@m~I1~~~©~------------
960
APPLICATION NOTE
THE USE OF A TRIAC WITHOUT A SNUBBER NETWORK
The triac can thus be considered as a switch which turns off at the moment when the current is cut off in the dampened oscillating circuit constituted by the loads Land R and the internal capacity of the triac Ct (fig. 6). In the case of a pure inductive load, the maximum reapplied (dv/dt) is:
(dv/dt)c = --.J2 Vrms x Irms x Ol/et
For example, the internal capacitance of a 12 Amp triac is about 70pF. Therefore, on inductive load, the maximum (dv/dt)c without snubber will be limited to 50 or 100 VIS according to the characteristics of the load.
It is interesting to know the behavior of the triac, in particular the critical (di/dt)c value, in these conditions. This characterization corresponds to the points C1 and C2 of the curve fig 3.
Figure 6 : Triac commutation on an inductance load without a snubber network
LOAD
LOAD
~
I o cSOOEooH R I
e1I1r- t"C
'IT t'lc
r
0
A progress: THE NEW TECHNOLOGY
To make significant progress in the triac area is to essentially improve the commutating behavior at the turn off of the triac. In other words the critical (di/dt)c has to be improved.
In order to reach this goal, a new structure has been developed. In this structure, the different active zones have been de-coupled to the
maximum in such a way as to separate the elementary thyristors and the gate area. This is made possible by sacrificing the gate triggering in the fourth quadrant. In practice this does not pose a problem because the gate drive circuits of a triac generally use two of the third first quadrants. (fig. 7)
Figure 7 : Basic gale drive circuits (the fourth quadrant is not used)
R
~OP10C(ItJPI.ELIR '.halOni.cl ®
311
®
®
- - - - - - - - - - - - - ~~l ~~~@m~I~~~©~ - - - - - - - - - - - - -SilO
961
APPLICATION NOTE
For a given technology, the commutating behavior of triacs depends on the sensitivity of the gate. The correlation between the critical (di/dt)c and the gate current for 12 Amp triacs is represented in figure 8.
In the same chart, we can see the results obtained with conventional triacs versus the new technology triacs. As can be seen, the progress that has been made at this level is significant.
1/ The performances and specifications
Figure 8 : Correlation between commutating behavior and sensitivity. (Measurements performed on several lots of 12 A triacs)
Critical (di/dt)c AimS 30
·
·
·
·
25
·
20
· ·
· 15
10
· NEW TECHNOLOGY PARTS I.3!iJ CONVENTIONAL TRIACS
5
Igt 3rd quadrant (rnA)
0
I
I
10
2D
30
40
50
60
The new technology has been put into place with the manufacturing of the two new series, Logic Level and SNUBBERLESS Triacs. In the data sheets of these new triacs a critical (di/dt)c limit is specified at the maximum junction temperature (Tj max).
a- Logic Level triacs
In this category we consider sensitive triacs in which the maximum gate current (IGT) is SmA for the TW type and 10mA for the SW one.
In the data sheets of the Logic Level triacs a minimum (di/dt)c is specified for the following cases:
* Resistive load with a (dv/dt)c of 01.V/lls.
* Inductive load with a (dv/dt)c of 20 V/IlS
For example the 6 Amp triac is specified as follows:
Symbol
Test conditions
Quadrant
tgt
VD = VDm,; IG = 90 mA
dlG/dt = 0.8 Alms
Tj = 25°C I - II - III
(dl/dt)c * dV/dt = 0.1 V/).ls
Tj = 110°C
dV/dt = 20 V4ts * For either polanty of electrode A2 voltage with reference to electrode A1.
TYP
MIN MIN
Suffix
TW
SW
2
2
3.5 4.5 1.8 3.5
Unit ).ls Alms
_6/_10_ _ _ _ _ _ _ _ _ JI>.. .'L S C i S · 1 H O M S O N - - - - - - - - - . " , iIlllD[:[i;]@I<~~(l;'jJITiI@If:IlD©ill
962
APPLICATION NOTE
b- SNUBBERLESS TRIACS
This series of triacs presently covers the range 6 to 25 Amps with gate currents of 35mA (CW type) and 50mA (BW type) according to the type required.This series has been specially designed so that the triacs switches from the on state to the off state without the use of an external snubber circuit.
Whatever the nature of the load, there is absolutely no risk of spurious firing at the turn off of the triac as long as it is functioning under the specified (di/dt)c value.
The SNUBBERLESS triacs are specified at critical (di/dt)c values which are greater than the decreasing slope of the nominal current in a sinusoidal configuration. For example, the slope of the current in a triac conducting 16 Amp when the current drops to zero is:
(di/dt)c = Irms x -ff x (J) = 7A1mS at 50Hz
The BTAlBTB16-600BW is specified at (di/dt)c = 14A1ms.
The following table summarizes the characteristics of the BW, CW SNUBBERLESS triacs which are presently available:
TYPE CURRENT 1 VOLTAGE
SUFFIX
BTA 1 BTB
06A 200 to 800V
BW
CW
BTA 1 BTB
08A 200 to 800V
BW
CW
BTA 1 BTB
10A 200 to 800V
BW
CW
BTA 1 BTB
12A 200 to 800V
BW
CW
BTA 1 BTB
16A 200 to 800V
BW
CW
BTA 1 BTB
20A 200 to 800V
BW
CW
BTB
24A 200 to 800V
BW
CW
BTA
26A 200 to 800V
BW
CW
21 The advantages and Applications
a - Logic Level
The goal of these triacs is to be controlled directly by logic circuits and microcontrolers like the ST6 series:
Outputs of ST6 can sink currents up to 20mA per 1/0 line, and therefore drive TW and SW.
These triacs are ideal interface for power components supplied by 110 or 220 volts, such as valves, heating resistances, and small motors.
IGT MAX (rnA)
50 35
50 35
50 35
50 35
50 35
50 35
50 35
50 35
STATIC dV/dt MIN (V/IlS) 500 250
500 250
500 250
500 250
500 250
500 250
500 250
500 250
WITHOUT SNUBBER (dl/dt)c MIN (Alms) 5 3.5
7 4.5
9 5.5
12 6.5
14 8.5
18 11
22 13
22 13
The specification of the critical (di/dt)c value on both resistive and inductive loads allows one
11 to know the margin of security of the circuit in relation to the risk of the spurious firing, which results in improved reliability, and
21 to optimize the performance of the triac to be used, which results in a cost reduction.
------------- -------------i.'1l ~~~~m~:~~~©~
7/10
963
APPLICATION NOTE Figure 9: Light dimmer circuit with ST6210.
LINE
FUSE
A2 BTA 08-400SW
100k
MODE 100kF
ov
220k
220k
22k
ov
19
15
18
ST621 0 14
20
3X4.7M
TOUCH SENSOR
PUSH BUTTON
ov
-r -r 10P
10P
ov
ov
ov
220k
POTENTIOMETER
OV
NEUTRAL
All resistors 1/4W unless otherwise specified
b - SNUBBERLESS Triacs
The commutation of SNUBBERLESS triacs is specified without a limitation (dv/dt)c. With the suppression of the snubber in the circuit, there is a noticeable cost reduction.
Each SNUBBERLESS triac series is specified with a critical (di/dt)c value and the static (dv/dt) at the highest possible level, taking into consideration the gate sensitivity (Igt). The minimum specified levels for these two parameters allows the use of these products in circuits where there is a need for high safety factor, such as:
1. Static relays in which the load is not well defined. With conventional triacs it is difficult to
adapt the snubber to all possible cases. SNUBBERLESS triacs resolve this problem. (fig. 10).
Figure 10 : Solid state relay diagram
INPUT
....._-1-1 OPTO INSULATED r - - , - - + - I
DRIVE CIRCUIT
ZERO CROSSING CIRCUIT
·964
Figure 11 : Motor control circuit using SNUBBERLESS triacs
(Ls + r = network for series protection)
APPLICATION NOTE
Figure 13 : Example of a circuit with high (di/dt)c
Inductive load (Motor, valve ...)
GATE: MIVE CIRCUIT
/
2. Motor drive circuits. Figure 11 shows an inversion circuit of an asynchronous motor where spurious firing of the triac, normally assumed to be in off- state, must be absolutely be avoided.
The critical (di/dt)c of SNUBBERLESS triacs is greater than the slope of the nominal current of the specific type under consideration. This is important for several applications, including : Circuits in which the (di/dt)c in a transient state is greater than in the steady state. This is the case for universal motors controlled by AC phase control circuit. The table in figure 12 shows how to the use of a SNUBBERLESS triac can optimize the efficiency of the circuit.
Circuits which generate wave forms with a very high (di/dt)c, such as inductive load supplied by a diode bridge (fig. 13). It is only limited by the parasitic inductance of the AC circuit.
Figure 12: Universal motor control: Triac choise must comply with maximum {dl/dt)c For example, a SNUBBERLESS 10 A triac is sufficient to control a 110 V AC 600 W moytor
POWER 600W
SUPPLY NOMINAL MAX CURRENT VOLTAGE CURRENT TO CONTROL
220V/50Hz 3 ARMS 110V/60Hz 6ARMS
3.5 A 7A
TRIAC RANGE
6A 10 A
1200W 220V/50Hz 6 ARMS 110V/60Hz 12 ARMS
7A 14 A
10 A 16 A
(dl/dt)e MAX (1) AA/ms 7 Alms
7 Alms 15 Alms
STANDARDS TRIAC
BTA10-600B BTA16-400B
(2)
BTA16-600B BTB24-400B
SNUBBERLESS TRIAC
BTA06-600BW BTA10-400BW
BTA10-600BW BTA20-600BW
(1) Maximum transient (dl/dt)c. This parameter depends very much on the type of the motor. (2) This type specified at 7 Alms munumum can be too small certain applications could need 25 A standard triac.
- - - - - - - - - - ~'9' SCiS·THOMSON - - - - - - - - -9- /10
·J I , ~O©OO@]~~©'iTOO@u;mJ©:ll
965
APPLICATION NOTE
CONCLUSION
Thanks to the recent progress made in triac technology, the designer now has at disposal devices with a commutating behavior which is compatible with all applications in the 50 or 60Hz range. This includes phase control and static commutation for loads going from a few watts to several kilowatts.
The capability of this new generation of triacs allows:
1/ To increase the reliability of circuits, particularly where there is a risk of spontaneous firing even in the most difficult configurations.
2/ To reduce the cost by using sensitive gate, LOGIC LEVEL triacs without the need for an interface between the gate and the logic circuit, or utilizing SNUBBERLESS triacs which are specified without a resistive/capacitive network.
Additionally, the limit of the (di/dt)c parameter is now listed in SGS-Thomson Microelectronics data sheets.
This permits the optimization of the circuit by specifying stricter guidelines in the choice of the component.
-10/1-0 - - - - - - - - - - ...'Yl ~~~@mym~~~©~------------
966
APPLICATION NOTE
TRIAC DRIVE CIRCUIT FOR OPERATION IN QUADRANTS I AND III
Ph. Rabier
New triacs with high commutation and dvldt performances are now available on the market.
Generally these triacs are only triggerable in the 3 first quadrants (case of SNUBBERLESS and LOGIC LEVEL triacs) as shown in figure 1.
This paper describes a trigger circuit supplying a negative gate current for quadrants II and III implemented in a system using a positive power supply.
Without a new design, just by adding a capacitor and a diode new W series triacs can replace conventional triac.
To drive the triac in the 2nd and 3rd quadrants a discharge capacitor is used as shown in figure 3.
Figure 3 : Basic diagram of the trigger.
+ Vee R2
LINE
Figure 1 : The quadrants of a W series triac.
R3
IA
+2 nd
3 rd
++ 1 sl
IG 4 Ih
NOT TRIGGEAABLE
I - PRINCIPLE:
Figure 2 shows the schematic of a system with a sensor, logic and positive power supply (with respect to the anode 1 of the triac).
Figure 2 : Synoptical diagram of a classical system.
11 Principle:
- The transistor is switched off, capacitor C is charged through resistance R2 and diode D.
The diode is used to avoid a capacitor load current through the gate of the triac. A schottky diode could be used to improve the voltage drop level lower than the gate non trigger voltage (VGo).
- When the triac is triggered, the transistor Tr is switched on, C is discharged through R1 and Tr and a negative current flows through the gate of the triac.
The capacitor C acts as a differentiation. We have to consider different parameters to define all the components:
- The gate trigger current of the triac (IGT)
- The time duration of the gate current
- The latching current (IL) especially for small or inductive loads.
AN44010592
1/5
967
APPLICATION NOTE
-21 R-ev-ie-w:
Definition of the latching current (IL) :
The IL of a triac is the minimum value of the main current which allows the component to remain in the conducting state after the gate current IG has been removed:
That is to say the gate current has to be higher than IGT until the main current reaches the latcing current.
Example: for the CW SNUBBERLESS triac: 01 - 03 : ILmax = 50 mA 02 : ILmax = 80 mA
With : gate pulse duration of 20l1s at Tj = 25°C
IL max is specified in the CW series triac data sheet. Statistically, for BW series triacs we can use the K ratio
K = ILmax/lGTmax
K = 2,3
Two solutions are possible:
- Triggering with a delay after zero voltage crossing such that the main current is higher than IL.
- Triggering at zero voltage crossing with a long discharge time in order to have no problem with IL.
II - THE CASE WITH A RESISTIVE LOAD:
.11 First solution: delayed pulse current (figure 4).
Figure 4 : Triggering with delay 11 after zero crossing.
:=IIIIIEIIJ
CURRENT
M" I
20mAlDIV
0.'_ 1111119111
The gate pulse is shown in Figure 5 : Figure 5 : Gate pulse.
IG 12
IGM/2 IGM
t1 calculation:
The triac has to be triggered when the main
current is higher than the latching current, that is
to say t1 min i~ := larcsin ( h max)
co where co = 2 . It . f
IRMS--!2
IRMS : minimum RMS current in the worst case (depending on line and load dispersion).
The curve given shows the minimum time versus IRMS current through the anode (figure 6).
Figure 6 : t1 time versus IRMS for different latching currents.
t1(us) 200
180 160
\
140 120
\
\1\
100
80
W SERIES
\
60 40
r-cw
SERIE~"'"
I I I
'-----
'----- ~
20
- r - I--
a o 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
IT(rms)(A)
The gate current calculation:
IGT is the maximum gate trigger current specified in the data sheet. To ensure a good safety
margin and good triggering we have chosen IG =
2.IGT with a pulse duration t2 higher than 20l1s.
-2/5- - - - - - - - - - - ! ' 1 l ~~i@m~f&'I~~~©'------C.-------
968
APPLICATION NOTE
All the components can be defined by the following formulae:
R1 max = (Vcc - VGK - VCE)/(2.1GT)
with VGK = 2 V at IG = 2.IGT
Cmin = t2/(R1.log2) with t2 = 20j.1s
R2max = 0,001/C
Curve 7 gives the minimum capacitance versus supply voltage for different sensitivity.
Figure 7 : Capacitance value versus supply voltage for different sensitivity.
C (uF) 2
1.8
1.6
1.4
II
1.2
1\
1
1\\
0.8
\
\~
0.6
W SERIES
0.4 r--
0.2
cw
SERIE~
I I
~l J
N==:::I::----
o 2 4 6 8 10 12 14 16 18 ~o 22 24 26 vee {V}
In this way the RMS current is lower than the full wave current, the RMS current/full wave current ratio is :
4 4) K' = 1 - 2 . + 2~ .sin ( 4 it
Figure 8 : Triggering at zero voltage.
.: ujifrWl1
III~IJ IIIII ,,,. f CURRENT
:::,:
Note : In figure 8, the pulse through the transistor base is cancelled before the capacitor is fully discharged to save energy.
All the components can be defined by the
-ff) following formulae: /2 min = ~arcsin (IR~~
+ 20j.1s
R1max = (VCC-VGK-VCE)/(2.IGT) Cmin = t2/(R1.1og2)
R2max = 0,001/C
In this way the RMS current is equal to the full wave current.
The calculation gives for a 6 Amps CW triac with a 2 Amps sine current and with an IL = 80 mA.
t1 = 90j.1s
K = 0,99
That means the losses are lower than 1%.
21 Second solution: Wide current pulse at zero crossing.
It consists of triggering the triac at zero voltage crossing voltage as shown in figure 8.
_ _ _ _ _ _ _ _ _ _ _ ~ SGS-THOMSON _ _ _ _ _ _ _ _ _ _3_/5
lilt..""!l ~O(l;w@rnlLrn(l;'ilw@IiIJO(l;~ 969
APPLICATION NOTE
31 Comparison between these two solutions: The calculation of all the components is shown
in the following table for 3 differents cases
Figure 9 : Component values for 3 differents cases: triac used: BTA08-600CW (IGT = 35 mAl
t1 min (IJS) t2 min (IJS) R1 max (0) C min (IlF) R2 max (0)
IRMs ~ 5 A
Vcc~10V
with delay
at zero crossing
36
0
20
56
105
105
0.275
0.77
3.7
1.3
IRMs ~ 2 A Vcc ~ 5 V
with delay
at zero crossing
91
0
20
111
34
34
0.85
4.7
1.18
0.212
IRMs ~ 5 A Vcc ~ 5 V
with delay
at zero crossing
36
0
20
56
34
34
0.85
2.37
1.18
0.42
III - CASE OF INDUCTIVE LOAD:
With an inductive load another problem occurs: the problem of the phase lag between load current and load Voltage.
It can be solved by taking into account:
If the phase lag is not constant a gate pulse train can be used, the calculation parameters are the same, except for R2 : the capacitor C has to be charged between 2 pulses so the equation is :
R2=(time between 2 pulses)/(5xC)
- the maximum phase lag to define a delay time td.
- the latching current to define the time t1
- the inductance to define the time t2= VIL at the moment when the triac is fired (t2 > 20flS) to have an anode current higher than the latching current IL.
The figure 10 shows the anode current and the gate current in the triac, is the case of an inductive load.
Figure 10 : Current through an inductive load.
une~
/ IL ' j '
.. / .
. /
, t2 .
IG
,,'-:
td
Anode current
IGT . 21GT -
IV - THE CASE OF A SMALL LOAD:
This trigger circuit can not be effectively used to drive small loads (like valves, fan etc ... ) because the latching current value is not very small compared to the load current. In this case a DC gate current is needed.
V - CONCLUSION:
In the case of controllers supplied by positive voltage this solution allows of the replacement of conventional triacs used in the 1st and 4th quadrants by SNUBBERLESS or LOGIC LEVEL triacs triggerable only in the 3 first quadrants without a new design but only by adding a capacitor and a diode.
Two configurations are possible:
First solution: Triggering after the zero voltage
crossing .
Advantage: capacitor value lower than 1flF.
Disadvantage : the need to have a delay after
the zero voltage crossing (delay system
needed).
.
Second solution Triggering at zero voltage crossing. Advantage : 100% of the power used in the load. Disadvantage : capacitor value of a few microfarads.
-4/5- - - - - - - - - - - i . . , l ~~~~my,m~~~~~------------
970
APPLICATION NOTE
With inductive loads (motor, transformer, etc... ) a pulse train can be used because of the phase lag between current and voltage.
With small loads (valve, fan, ... ) a DC gate current has to be used to drive the triac because of the latching current.
In case of logic or transistor failure, the capacitor C operates as an open circuit for DC current and avoids all triggering. This factor acts as a safety feature.
- - - - - - - - - - - - ..'Yl ~i~@ml&1~~~©~ - - - - - - - - - - - -5/5
971
APPLICATION NOTE
TRIACS FOR MICROWAVE OVEN
P. Rault
Triacs are now commonly used in microwave ovens as static switches to control the power transformer, the heating resistor for grill and sometimes the motor for plate rotation.
The conditions of operation of triacs for transformer control and for heater control are analysed here after in order to select the suitable device, to define the gate drive circuit and to implement an efficient protection.
10 to 16 Amp according to the line voltage but it is necessary to take into account an overload due to the magnetizing current through the transfomer at turn on. Due to the high turns ratio of this transformer this overcurrent can reach a peak up to 20 times the RMS current in steady state! To reduce the stresses at every switching on the circuit and particularly on the triac it is important to limit the overcurrent by using a proper triggering synchronization.
I . POWER TRANSFORMER CONTROL:
The magnetron of a microwave oven is generally supplied by rectified high voltage obtained with a 50/60 Hz transformer. The power supplied to the oven is controlled by a triac in series with the primary (fig.1).
Transient operation in inductive circuit with iron core: During continuous operation, the magnetic field H, proportinal to the current in the cOil,generates an induction B in the iron core with a delay as shown by the hysteresis cycle in figure 2A.
1/ Current stresses:
The power to be controlled is typically 1 to 2 KW and the nominal RMS current is in the range of
In transient operation, the induction can follow a different path and reach the saturation value BS
for which the magnetic field H (according to the coil current) increases very rapidly (Fig.2B).
Figure 1 : Magnetron power supply controlled by a triac.
r
T"'=' AC
~ HV
AN441 10592
1/8
973
APPLICATION NOTE
Figure 2 : A - Magnetic field H versus induction B (continous rating) B - Saturation induction BS
B
----- ...... Bs . - . - ----~-~-:..::-
H
o
H
H k.nI
In the circuits controlled by a triac, switching OFF occurs when the current is at zero. Thus the induction has a remanent value Br (positive
or negative), corresponding to H = 0 (Fig.2A).
When the triac begins 10 conduct, the transient
current depends on the instant of synchronization of the control signal with respect to the mains voltage.
FIRING AT ZERO MAINS VOLTAGE:
Peak induction tends to the value:
Bmax = 2 Bn + Br
Thus in most cases B reaches the saturation induction BS. The amplitude of the current proportional to the magnetic field H becomes
very high ; this type of control produces the highest transient overloads (Fig.3A).
In this case the transformer behaves like a short circuit and peak current is limited only by the series resistances of this circuit. Nevertheless it is possible to reduce the overcurrent if control at zero voltages done by complete cycles i-e the polarity at the moment of firing is the reverse of that at moment the circuit is switched OFF. Peak induction thus reaches the value :
Bmax = 2 Bn - Br.
The overload is lower than previously but still remains high (Fig.3B).
_2/_8_______________________ ~~l ~~~@~~~l~~©~ -------------------------
974
APPLICATION NOTE Figure 3 : Transient induction and current at beginning of conduction.
V mains voltage
V mains voltage
V mains voltage
B induction "
tB induction 2 Bn - Br
Bsl-----JF-~
B induction Bsl----...:.:,..
__ ~~--~~~~---- OL-----------4-----__ triac current
A : firing at voltage zero
B : firing at voltage zero conduction by complete periods
C : firing at voltage peak
FIRING AT PEAK MAINS VOLTAGE:
In this case the peak induction takes the value:
Bmax = Bn + Br
The level of saturation is not reached and amplitude of the current remains with in acceptable limits (Fig.3c).
--7This type of synchronization must be used for transformer control. See in appendix actual osciliogrammes of current through a transformer for different synchronization modes.
Figure 4 : A - gate control by single pulse synchronized with zero current B - gate control by pulse train.
:f\f V MAINS VOLTAGE o '--\--+----1~
TRIAC CURRENT
o e--I---\--~ o e-+----.,L-----I..
------------------------ J.:.-YL ~~~@m~I'~~~~~ -----------------------3/-8
975
APPLICATION NOTE
2/ Gate control:
After the first firing the gate pulse should be synchronized with the triac current zero point (FigAA).
The pulse duration must be sufficient to be sure the main current through the circuit reaches the triac latching current.(IL) A pulse train can be used to avoid the problem of misfiring or wrong synchronization (FigAb). A frequency of several, kilohertz garantees a correct operation.
Gate control by DC current is also an efficient method to keep the triac on in case of inductive load. To reduce the consumtion of this kind of trigger circuit a sensitive triac can be used as a driver (Fig.5).
Figure 6 : TRANSIL diode and RC network are necessary to prevent spurious firing by overvoltages and/or dv/dt.
I
P-=" AC
rY"Y'Y""'. ~ 1~~
FILTER
L
F
l
Figure 5 : Use of sensitive triac (5 rnA) as driver to reduce gate control circuit consumtion.
BTA16·600BW
BT A06·600TW (IGT < 5mA)
3/ Protection:
It is important to avoid as much as possible all risk of misfiring of triac specially by overvoltage. Transient voltages can be generated by internal mechanical switches used for security system (door, overbreak protection etc ....) or supperimposed to the line voltage. These last ones must be attenuated by a filter at the input. An efficient protection at the triac level consists in use of TRANSIL diode across the triac to clamp the spikes higher than its voltage ratings (VDRM) associed with our RC network to limit the off state dv/dt under the specified value. (Fig.6)
Nevertheless one accidental misfiring is always possible and in this case the triac must be able to hold the surge current. Therefore it is necessary to select a device with a sufficient ITSM(max peak current for 10 ms) for example 120 to 250 Amp.
4/ Prefered devices :
- Current ratings: The nominal RMS current through the circuit is not the main criteria but the surge current capability. We suggest the following current ranges. ITRMS = 12 A with ITSM = 120 A
ITRMS = 16 A with ITSM = 160 A
ITRMS = 25 A with ITSM = 250 A -Voltage rating:
VDRM = 600 V provides a good safety margin for 220 VAC mains. -Package: Insulated cases are generally. used to make easier mounting on chassis and thus reduce the cost. T0220AB and TOP3 cases are suitable for printed board assembly. If the triac is mounted close of transformer (far from electronics board) RD92 with "FAST ON" connections is a convenient solution. -Protection devices: A bidirectional silicon diode suppressor (TRANSIL) with a peak power capability of 1500 W (1 ms) is a good compromise if there is a filter (coil + capacitor) at the line input. In fact it is necessary to have a
-4/8- - - - - - - - - - - - ~.,L~~~@mR:l~~Al-------------
976
APPLICATION NOTE
current limitation (series indepance) in case of overvoltage. The breakdown voltage compatible with 220 VAC supply is VSR = 440 V. -Part numbers: triac BTA12-600B/BW(1) 12 Amp T0220 AB BTA16-600B/BW(1) 16 Amp T0220 AB BTA26-600B/BW(1) 25 Amp TOP 3 BTA25-600B 25 Amp RD 91
TRANSIL 1.5KE440CP
Figure 7 : Triacs in insulated cases (UL approved)
T0220 AB
TOP 3
I
Figure 8 : Controlled by the gate pulse, IG, the triac is fired, and a current IT flows through it. If the gate current IG is stopped before current IT reaches the value of the latching current IL, the triac turns off.
'l1-= IG>IGT , Gate c;~e:;;--~
Main current
RD 91
G
II. HEATING RESISTOR CONTROL:
1/ Triggering:
In this application the triac is used as a ON/OFF switch to control the power in the grill heater. It is the case of resistive load. Therefore it is absolutely necessary to trigger the triac at zero voltage in order to eliminate the turn on dr/dt stresses and RFI problems. To keep the triac on, a single gate pulse can be supplied at every zero crossing of voltage that is also the zero point of current in this case. The pulse duration must be calculated in order to allow the load current to reach the latching current (IL) of the triac.
(1) BW : SNUBBERLESS TRIAC series with high switching performance and high dv/dt capability.
For triacs with max gate triggering current of 50 mA the latching current is lower than 120 mA.
2/ Current rating:
For normal operation there is no particular current stresses efficient cooling is required to minimize the thermal fatigue due to the variation of junction temperature and consequently increase the life time of the equipment.
3/ Protection:
With the new generation of triacs, SNUBBERLESS triacs, the commutation (turn·off) is possible without external limitation of (dv/dt)c, that is to say without RC network even
- - - - - - - - - - - - - -------------I.:.'Yl ~~~illm2m~~~~
5/8
977
APPLICATION NOTE
if the load is inductive. In case of overvoltages the triac could be fired by exceeding its breakover voltage and generally it is distroyed because of the too high dildt, that is limited only by the inductance of the load (very low for a heating resistor) and of the wiring. A RC network across the triac cannot reduce the spikes because there is not enough inductance in series in the kind of circuit. ~RC snubber circuit in useless!
HOW TO PROTECT?
The solution consists in turning on the triac by a
gate current as soon as the voltage across it exceeds a certain value which ensures a high level of safety. To do it we use a low power (i-e low cost) bidirectional TRANSIL diode according to the
diagram. Fig.8 When the overvoltage reaches the breakdown voltage VBR of the TRANSIL the latter conducts and the current flows through the gate and turns the triac on. Fig.7
Figure 9 : Protection by TRANSIL the triac is turned on by the gate at the beginning of the overvoltage and continues conducting during the rest of the half cycle.
2kW
--220 V
Bm16600B orBTA12600B
Control
Ovcrvoltagc
fi ~
1"-
+VSR
I" I
I" I I I __________________ '1.________________________________ _
I
L
Mains
I
,/ voltage
, , I / - - ' , /
I"
I ~
TRIAC \. voltage \
\
-VSA - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 'TRIAC
, ,
/
/
---",,/
- - - - - - - - - - - - - _6/_8____________ jO,'Yl ~i~@m2ml~~©~
978
APPLICATION NOTE
What part number?
to protect a 600 V triac generally used for 220 VAC operation we recommend: BZW04376B or BT. for a 400 V triac (110 VAC mains) we propose a BZW04188B.
reduce peak inrush current, then triggering with pulse train synchronized at zero current point.
Protection : TRANSIL and RC network across the triac to avoid all risk of firing by overvoltage and/or dv/dt.
III . TO SUMMARIZE:
Transformer control:
Select triac with high surge current capability and with high transient immunity (SNUBBERLESS series). Triggering: first switching on, firing at peak line voltage to
Heating resistor control:
Triggering at zero voltage absolutely necessary. Protection :
* with SNUBBER LESS triac, RC snubber circuit is useless.
* TRANSIL diode connected between gate and A2 achieves an efficient protection against overvoltages.
- - - - - - - - - - - - - ~"'l ~~~@m~ll~l~~:r;~ _____________7_/8
979
APPLICATION NOTE
ANNEX
TRANFORMER CONTROL BY TRIAC Triggering at voltage peak --> peak current = 22 A
,----fli--1
0
,
---- ,----
-I
TRIAC VOLTAGE
r l 100 V I div
R --
-- ------"
20 ms I div
Triggering at zero voltage --> peak current reaches 130 A !
·'
· TRIAC VOLTAGE 100 V I div 20 ms I div (line voltage = 220 VAC)
CURRENT
1-- ------+-+---+--- - ---+--j---+-4
50 A I div
______ f-----!-i---+--f--- ----= ~-=-____
20 ms I div (unloaded transformer)
<------;t------'--'--L_--- _ c _ -_~---_
Steady state (without load)
A \
{
IV
A \
{
IV
A
~ {
IV
A
IA
\. r \. r
1\/
II/
TRIAC CURRENT 50 A I div
10 ms / div
_8/_ 8 _ _ _ _ _ _ _ _ _ _ t== SCS.THOMSON _ _ _ _ _ _ _ _~_ _
""'1L f!AJO©Iiil@!ll~I'i©1JIiil@UilO©®
980
APPLICATION NOTE
TRIAC & MICROCONTROLLERS THE EASY CONNECTION
Ph. Rabier
The aim of this note is to show how to connect an SGS-THOMSON triac and an SGS-THOMSON microcontroller.
Figure 2: Conventional drive in the 2nd and 3rd quadrants.
I . CONVENTIONAL SOLUTION
+VDD
For many years the triac has been used to
switch load on the AC mains and thanks to the
low cost of microcontroliers (JlC) this solution is
uC
widely used in the appliance market.
LIN
Ali the system use a buffer transistor between
the output port of the microcontrolier and the triac as shown in the figure 1.
Figure 1 : Drive in the 1st and 4th quadrants.
LINE
uC 11 '----r-,--Y
IG OV
Because of. the low sensivity of the triac in the 4th quadrant this type of drive is often unpractical, and is replaced by the topology of the figure 2 :
To save cost, manufacturers want to use fewer and fewer components and of course want to remove the buffer transistor, but a problem arises.
Due to the low output current of the microcontrolier, the triac had to be very sensitive and consequently was not able to withstand for example the static dv/dt, and the commutation.
II· NEW SGS·THOMSON SOLUTION
Two parameters have been improved :
- The sensitivity of the triacs.
- The output capability of the microcontroliers in terms of sunk current.
A microcontrolier is now able to drive one standard triac or several sensitive triacs,. without buffer transistors (see figure 3).
AN442/0592
112
981
APPLICATION NOTE
Figure 3: An easy connection
+VDO
SGS THOMSON
uC
THOMSON A2
TRIAC
LINE
Where:
Voo supply voltagage VOL output low voltage of the microcontroller VG gate - anode 1 voltage at IG
With:
Voo = +5 V VOL = 1.3 V VG = 1.5 V IG = 20 rnA
Therefore: RG = 110 Ohms
ov
Figure 4 shows the output capability of a range of controllers and the sensitivity of the triacs.
Figure 4: Triac and microcontroller characteristics.
MICROCONTROLLERS & OUTPUT CAPABILITIES
TRIAC
SENSITIVITY
GATE PARAMETERS
CONNECTION
ST621x SERIES ST622x SERIES
IOL=20mA AT VOL= 1.3V
IVSS=100mA
T & TWSERIES Tx05 SERIES
S& SW SERIES Tx10 SERIES
'IGT=5mA IGT=10mA
VG =1.5V AT
IG = 10mA
VG =1.5V AT
IG=20mA
1 PORTfTRIAC 1 PORTfTRIAC
C SERIES CWSERIES B & BW SERIES
IGT=25mA IGT=35mA IGT=50mA
VG =1.5V
2 PORTS IN PARALLELfTRIAC
AT IG =50mA
VG=2V
3 PORTS IN PARALLELfTRIAC
AT IG =70mA
VG =2V AT IG= 100mA 4 PORTS IN PARALLELfTRIAC
To take into account of the dispersion on RG , Voo and on the temperature variation, we generaly choose about:
IG = 2 .IGT (IGT=Specified gate triggm- current) tp > 20jJ.s
Where tp is the pulse duration of gate current.
EXAMPLE:
For +5V supply voltage and a LOGIC LEVEL triac with IGT = 10 rnA, we have :
III - CONCLUSION
Use SGS-THOMSON sensitive triacs driven by an SGS-THOMSON microcontrollers and remove the buffer transistors.
This can be achieved thanks to the high current capability of our microcontrollers which are compatible with our new sensitive triacs (T410, T, TW, S, SW series).
Furthemore a non sensitive triac can be driven by several output ports in parallel.
-2/2------------~~l ~i~~mgl~~~~~-------------
982
APPLICATION NOTE
SERIES OPERATION OF FAST RECTIFIERS
B. Rivet
The use of several rectifiers connected in series is necessary to obtain voltage ratings beyond the capabilities of single diodes and also when some special requirement, such as very low switching losses, oblige to implement several low voltage ultra fast diodes.
Rectifiers connected in series tend to share unequally the voltage across the string in blocking conditions because of the variations in reverse characteristics : leakage currents and turn off switching parameters.
To ensure that each diode operates within its voltage rating it is generally necessary to add a voltage sharing network.
This paper gives the rules of calculation of this auxiliary network and shows how this circuit could be optimized : reduction of power dissipation and cost.
I - STEADY STATE VOLTAGE SHARING:
The difference in blocking characteristics results in unequal steady state voltage (fig.1).
Figure 1 : Dispersion of diodes reverse characteristics. The reverse current through the string 01, 02, ....Dn is IR and the voltages across the diodes are respectively V1, V2j ...Vn.
In order to equlize the voltage, a resistor is connected across each diode (Fig.2).
Figure 2: Use of shunt resistors for steady state voltage sharing.
D1
D2
D3
Dn
~~ ~ 1~~ ~
~I V2 'I V3 'I I-v;;-']
1) Calculation of sharing resistors:
The calculation of these resistances is based on the worst case situation.
The maximum unbalance in blocking voltage when n diodes are connected in series occurs when (n-1) diodes have the maximum leakage current and one diode D1 has the lowest possible leakage current.
In this case D1 will support the highest voltage V1 and this tendency is aggravated by the assumption that the corresponding resistor R1 is at the upper limit of its tolerance (a), while all the others are at the lowest limit so,
R1 =R(1+a)
D2
R2 = R3 = .... Rn = R
Dn i I
In order to calculate the current in the string we
)
approximate the reverse characteristic with a
D1
straight line. We define the slope by the
IR
coefficient k according to fig.3.
Vn
V2
V1
VRRM
V
AN443/0592
1/7
983
APPLICATION NOTE
Figure 3: Reverse characteristic modelisation of a fast rectifier.
VR(I-k)
IR+ IRM(TJ).[k+ VRRM 1
With k = O.B
IRM IR
k.IRM
V L-~~~~-L~~~~~~~~.
VR
VRRM
So the leakage current IRM of diodes 02 ... On under the blocking voltage V2 ... Vn is :
Vn (I-k)
1R2 = 1R3 = ... IRn = IRM [kl VRRM 1
where IRM is the maximum leakage current at VRRM (maximum voltage specified for this diode), and at the operating junction temperature. For '01 the maximum reverse current at VRRM is
IRM-!;.IR
In these conditions the leakage current of diode 01 is:
V1(I-k)
IR1 = (/RM-!;.IR) (k+ VRRM )
Taking into account all these parameters, the voltage VI across the diode 01 is given by the relation:
V VM(I+a)(VRRM+(I-k)/RM RJ+k(n--I)(I+a)/';./R RVRRM
1 RIRM n(l-k)(I+a)+ VRRM (n+a)-RMFi (l-k)(1 +a)(n--I) (I)
The resistance R must be choosen to limit the 'voltage V1 under the maximum value VRRM specified for this rectifier. Thus:
R<
VRRM WRRM (n+a)- VM (I +a))
MR VRRM (I+a)(n--I )-IRM (l-k)(\+a)(nVRRM-VM)
(2)
For the to-day fast rectifiers we can use k=O.8
maximum reverse voltage VRRM. This current depends on the junction temperature (Fig.4). Generally in the data sheet the manufacturer specifies a maximum value IRM at VRRM at
Tj=100De.
When we know the operating junction temperature (Tj) it is possible to calculate IRM by using the following relation:
IRM(Tj) = IRM(IOODC) exp[-0.054(100-Tj)]
Figure 4: Reverse leakage current versus junction temperature. Example: BYT 261-1000 (typical value)
10 0_ __ IR(uA)
10000~~!",,!!!~~
100_~_
,~~~-L~-L~~~~~~
20 30 40 50 60 70 80 90100110120130140150 THoe)
3) ~ IR estimation In fact ~ IR is the sum ~ IR1 and ~ IR2 - ~ IR1 is due to the leakage current dispersion of the rectifiers in the same conditions of voltage and temperature. For the fast rectifiers to day available on the market the dispersion of the reverse current at
e VR = VRRM and Tj = 100D is about :
!;. IR1 = 0.6 IRM This dispersion varies from one batch to another. - ~ IR2 is due to the difference between the junction temperatures of each devie (~Tj).
2) IRM evaluation IRM is 'the maximum leakage current at the
-------------'- -2/7----------'----J,..,l ~~~~m~'~~~~~
984
APPLICATION NOTE
Figure 5: The variation AIR is the dispersion of IR at max operation junction
temperature (AIR1) plus the variation due to Tj (AIR2)
1- - - - - -- IR
IIRRM
02,D3·... Dn
~lRt 01
-
--
IR2
I-----~===::::;:--~TJ{IC) TJ
The junction temperature is given by the thermal resistance junction to ambient Rth (j-a) and the power dissipation due to the conduction losses (PC) and the switching losses (PS).
PC is linked to the forward voltage (VF) and PS is linked to the reverse recovery charge (ORR). So the variation of the junction temperature is:
~ Tj=~Rth (PetPS)+Rth (~VVFPet~QQRRPS)
F
RR
Where AVF is the dispersion of the forward voltage and ORR the dispersion of the reverse recovery charge.
For series operation, it is recommended to use pieces coming from the same lot, so the dispersion on the parameters VF, ORR and Rth is minimized;
In most cases the evaluation of ATj is difficult but, from experience, it is generally lower than 10°C.
We propose to take a safety margin and to use: ~IR = 0.S5 IRM
4) Simplified formula
The relation (2) is often used by using the following approximations
k = 1 : supposing the reverse current IRM constant, whatever the blocking voltage across the diode.
a = 0 : Neglecting the effect of the tolerance of resistors. thus:
R< n VRRM- VM (n-1)~ IR
As for the AIR the worst case is taken into account.
AIR = IR (100°C)
with IR = IR max at Tj max specified
R< n VRRM- VM (n-1) IR
This formula is "pessimistic" and induces a low resistance and then a high power dissipation.
5) Example
- Given Maximum blocking voltage: VM = 2500V Part number used: BYT12-P11000 Power dissipation per diode: P = 7W Case temperature: Tcase = 52°C
- Rectifier specification : VRRM = 1000V IR (Max at Tj=100°C) = 2.5mA Rth j-c = 4°CIW
- Problem:
Calculation of sharing resistors for 3 diodes in series.
- Solutions:
a) Simplified method : .n VRRM- VM
R< (n-1) IR
With Thus
n = 3 VRRM = 1000V VM = 2500V IR = 2.5mA Rmin - 100 kOhms
Power dissipation per resistor : 3.45 W! (with duty cycle 1) = .5)
b) Calculation with relation (2) :
R<
VRRM(VRRM(n+a)-VM(l+a))
MR VRRM (1+a)(n-1 )-IRM (l-k)(l+a)(nVRRM -VM)
General data for fast rectifiers :
~IR = 0.S5 IRM k = O.S
Intermediate calculations:
Tj = P.Rth j-e + Tease = soac
IRM = IRM(SO°C) = IRM(100°C) exp[-0.0054(1 OO-SO)] =0.S5mA
~IRM = 0.72mA
APPLICATION NOTE
Assuming we use resistors with 5% of tolerance,
then a = .10
Let:
Rmin = 220 kOhms
Power dissipation per resistor=1.58W(with 1'=.5)
6) Ouestion : is it possible to remove the sharing resistors?
With the relation (1) we can find the value of V1 when the value of R tends to infinite. Then we calculate the condition to have
V1 < VRRM
Solving we find
"'IR < (1-k) (n VRRM- VM)
IRM
VRRM(n-1)
In the previous example this condition should be
MR=5%
IRM
If is obvious that this condition is generally very difficult to meet without hard selection.
II - TRANSIENT VOLTAGE SHARING
1) The problem
When a diode is switched from the forward conduction to the reverse blocking state, a reverse current flows through the device during the reverse recovery time trr.
After this delay all the charges (minority carriers) stored in the junction are eliminated and the diode turns off. The time integral of the reverse recovery current is called reverse recovery charge (ORR).
Fig.6 defines the reverse recovery parameters. When a string of n diodes in series switches off, the diode which has the lowest recovery charge turns off the first and supports an important proportion of the total voltage VM and its maximum reverse voltage VRRM could be reached or exceeded.
Figure 6: Reverse recovery current waveform.
IF dlF/dt
/
QRR
Voltage sharing during the reverse recovery phase is achieved by using a shunt capaCitors string connected across the diodes (Fig.?).
Figure 7: Use of shunt capacitors for transient voltage sharing.
erg 01
02
03
On
I~
H
Ct
C2
C3
~~~
Cn
~
2) Calculation of sharing capaCitors
The calculation of capacitance C is also based on the worst case situation.
We assume that (n-1) diodes 02, 03 ... On with a reverse recovery charge ORR + tl.ORR, and one diode 01 with lowest value ORR.
We suppose also that the corresponding
capacitor C1 is at the lowest limit of tolerance (a)
while the others are at the upper limit
so:
C1 = C
C2 = C3 = ... = Cn = C(1 +a)
When all the stored charges of diode 01 have
been evacuated, the charge remaining in the
other diodes is tl. ORR.
At this time the voltage across 01 is V1 and the
voltage across the other diodes of the string is :
986
APPLICATION NOTE
V2 = Vs= ... Vn =~ VM-Vl
So these diodes can be assimilated to a capacitor
Co __/'.._O_R_R_ =_/'..--c0~RR-'-('c-n-c-1--,-)
Vn
VM-Vl
Figure a: Equivalent diagram when 01
swtches off. Diodes 02, 03, .... On
are equivalent to a capacitor
CD = ~QRR(n-1) I (VM-V1)
Dl
02
03
On
Figure 9: Example of reverse recovery charge specification. (case of BYW 51)
500 QRR (nC)
90% CONFIDENCE Tj"1250C
100
IF IF(av)
~ ~
/'
~
10
10
20
50
100
dIF/dt(A/us)
200
500
In these conditions the voltage across 01 is :
V /'..ORR (n-1) + C VM (ha)
1
C(n+a)
In order to limit the voltage across 01 under the
specified value VRRM we calculate C by solving
thus:
V1 < VRRM
C>
(n-1 )/'..ORR
(n+alVRRM-VM(1+a)
3) ORR and ~ORR consideration For a given diode the reverse recovery charge ORR is function of the circuit commutation conditions such as the magnitude of forward current (IF), the rate of decay of this current (dIF/dt) and the junction temperature.
Typical values of ORR are given in the data sheet of each part number (Fig.9).
QRR'IRMITj)/QRR-IRM[Tj-1250C]
1.50
1.25
~
1.00
~ ~
IRM
0.75
~ %
0.50
e----
0.25
0.00a
25
50
75 100 125 150
THoC)
For fast rectifiers coming from the same lot the dispersion of this parameter is low and we can use, with a good safety margin:
/'..ORR = .30 ORR
4) Is it possible to remove the equalizing capacitor?
In blocking state diodes have a junction capacitance. For a given diode this capacitance decreases with an increase in the applied reverse voltage according to Fig.10.
--------------------------~~l ~i~~~g~:~~~~-------------------------5/-7
987
APPLICATION NOTE
Figure 10 : Junction capacitance versus reverse voltage (example: BYT 261-1000)
100 C(pF)
F-1Mhz Tj-250C PER LEG
_ _ 10L-~LLLUUL~~LUDil
~-U~
1
10
100
1000
VR(V)
We have
Vl = L1.QRR (f}-1)+ VM CJn CJl (11+1 )+CJn
Auxiliary capacitors are not necessary if
V1 < VRRM
or
II. Q RR <
VRRM[CJ1
(n-1)+CJnj-VMCJn f}-1
Generally, the value of the junction capacitance at the operating voltage is very close to the value at VRRM (CJ1) so we can write
II.Q RR<
CJl
(n
VRRM-VM) f}-1
This condition can be met by using very fast rectifiers in applications where the dlF/dt is low (like in some resonant converters or flyback converters) and consequently low QRR.
When 01 has evacuated all its stored charge it
is equivalent to a capacitor CJ1 and the other
diodes 02, 03 ... On are equivalent to a
capacitor which is the sum of the junction
capacitance CJ2, CJ3
CJn and the
capacitance
Figure 11 : Equivalent diagram when 01 switches off in case of low QRR : The junction capacitances CJ1, CJ2; ....CJn, play the role of sharing capacitors.
III· EQUALIZATION BY TRANSIL DIODES
TRANSIL are avalanche diodes designed for operation in breakdowl1 characteristic and they are used as clamping device in a wide field of applications. To limit the voltage across the rectifiers of a string below the maximum value, TRANSIL diodes can be used according to diagram Fig.12.
Figure 12 : Voltage sharing by TRANSIL diodes.
Dl
02
03
On
Dl
D2
D3
Dn
n;;~:t:-r 6~ .;2
I -I -f-------->I i-->I
V1
V2
V3
Vn
Fig.11 shows the equivalent circuit
In the worst case CJ 1 is the junction capacitor of 01 at the maximum voltage VRRM Putting
CJ1 = CJ at VRRM
CJ2 = CJ3 ... CJn = CJ at VM-VRRM f}-1
TRANSIL operates as a voltage limiter at steady state, during the switching phase, and also in case of external voltage transients.
1) Steady state
In blocking condition the TRANSILS connected across the diode 01 (Which has the lowest reverse current) operate in the breakdown
-6/7- - - - - - - - - - - - J...,l ~~~~mgm~~~~~ ----~--------
988
APPLICATION NOTE
characteristic. The current through these TRANSILS is IR and the power dissipation is :
VSR.",IR.o (0 ~ duty cycle)
Where VSR is the maximum breakdown voltage of TRANSILS. In general this extra power dissipation is lower than in the case of sharing by resistors and TRANSILS in axial packages can be used.
2) Switching phase
When the fastest diodes of the string switches off the TRANSILS across it operate in breakdown characteristic and the reverse recovery current of the other diodes flows through these TRANSILS. The charge remaining in the string at this moment is :
(n·1) "'ORR
and we can estimate the maximum energy in the TRANSILS with
E < 1/2(n-1) . "'ORR. VSR
This relation does not take into account the losses due to the capacitive current through the string.
3) Example
GIVEN: Use of a 3-BYT12-PI1 000 for VM ~ 2500V Operating conditions:
Tj = 100°C dildt = 20Al~s F = 25 kHz 0= .5 RECTIFIER SPECIFICATION: VRRM = 1000V IRM at VRRM = 2.5mA at Tj = 100°C ORR = .5flC (in operating conditions)
PROBLEM: 3 TRANSILS diodes are connected in series across each rectifier. What is the suitable part number?
DESIGN STEPS:
- VSR calculation :
VBR max < -1030-0 ~ 333 V
- Power dissipation in steady state: P1< IR . VSR max.o
with
IR = .85 x 2.5 ~ 2mA
VSRmax = 330V
P1<330mW
- Power dissipation in switching phase:
P2=E.F<1/2 (n-1) ORR. VSRmax. F with t.ORR = .5 x .3 = .15~C
F = 25 kHz and n = 3 then P2 < 1.2W
- Max total power dissipation P1 + P2 1.530 W
Solution . 1.5 KE series can be used (1.5KE300CP)
CONCLUSION
When using several fast rectifiers in series it is necessary to make sure that any diode will not be subjected to continuous or transient voltages in excess of their ratings. In most cases, this is achieved by using sharing networks across each diode. It is important to optimize this circuit in order to reduce power consumption and to save space. Parallel resistor can be optimized by using the modelisation of the fast recovery diodes reverse characteristic proposed in this paper. Then, thanks to a good knowledge of the reverse current and its variation in the operating conditions (possibly by measurement and selection) it is possible to implement a resistor with a value as high as possible. Parallel capacitors also have to be reduced as much as possible with the knowledge the switching characteristics of the string in the actual conditions. The reverse recovery charge (ORR) is not always accessible with the datasheet and a measurement is often necessary. In certain applications using ultra fast diodes of the same lot, where the ORR, and therefore the t.ORR is very low, the sharing capacitor can be reduced to zero. In systems where there is a risk of external overvoltages or where there are transient states not well known, TRANSIL diodes are a solution to the sharing voltage problem in sofar as the total power dissipation of the TRANSIL string remains compatible with the existing packages for these devices.
References: 1. B.M. BIRD and K.G. KING: "An introduction to Power Electronics" 2. J.M. PETER - SGS-THOMSON Microelectronics: "Analysis and optimisation of high frequency Power rectification"
Ii." _ _ _ _ _ _ _ _ _ _ _ t== SCS-mOMSON _ _ _ _ _ _ _ _ _ _7_/7 l ~iD©~Iill[jU©1JIi\lIill}IJ[©§ 989
APPLICATION NOTE
TRANSISTOR PROTECTION BY TRANSIL : DISSIPATION POWER AND SURGE CURRENT DURATION
B. Rivet
I - INTRODUCTION
In a great number of applications, we find the diagram FIG.1 where a TRANSIL is used to protect a switch which controls an inductive load. The switch can be a bipolar or aMOS transistor.
The purpose of this paper is to calculate the dissipated power in the Transil and the pulse current duration.
Figure 1: Basic Diagram
VCl : clamping voltage VBR : breakdown voltage rd : apparent resistance
III - CURRENT IN THE TRANSIL
We can express the current i through the TRANSIL by the following formula:
. I=
f (p+
VBRmin-Vee r
)exp
(-r
Lt ) +
(
VBRmin-Vee
r
)
Ip is the current through the coil when the transistor switches off. The FIG.3 shows the current variation versus time.
+ v cc
~I ( 1"
~) l~~
··
00
II - CIRCUIT MODELISATION
When the switch tunis off we use the equivalent circuit represented FIG.2.
The worst case is to consider VCl = VBR min.
This hypothesis will be used in all formulas.
Figure 2: Equivalent Circuit
L
r
1~=r(*
TTl
VCl=VBRmin
IQ~rd VC
TVBR
.
Figure 3: Current Waveform
Ip
\
- " - - -'-----
VCC·VBR
t1 can be calculated by
t1 =_.b. 1n VBRmin-Vee
r (VBRmin- Vee - rIp)
IV - TRANSIL POWER DISSIPATION We can consider two cases, single pulse operation and repetitive pulses operation. al Single pulse operation In this case, in order to define a TRANSIL we need peak power Pp and the pulse current standard duration tp. Pp is given by
Pp = VBR min x Ip
AN444/0592
1/2
991
APPLICATION NOTE
If we assimilate the pulse current with a triangle the standard exponential pulse duration tp is calculated by the formula:
t = _ ~ In VSRmin- Vee p (2r) (VSRmin-Vee + rip)
The energy in the Transil can be expressed by :
W VSRmin.L[1 VSRmin-Vee I VSRmin-Vee]
r
p+(
r
) n( VSRmin- VeC+rlp)
When r tends to zero we find :
w=l LI 2 VSRmin
2 p (VSRmin- Vee)
b) Repetitive pulses operation
In repetitive pulse operation the power dissipation can be calculated by the following formula.
P=F x VSRmin.L[1 VSRmin- Vee In VSRmin-- Vee
r
P+(
r
) (VSRmin-VeC+rlp)]
When r tends to zero we find :
p= 1 LFI 2 VSRmin
2 P (VSRmin-Vee)
Where F is the commutation frequency.
v - EXAMPLE OF APPLICATION
Commutation of a coil supplied by a battery. The' different parameters of the application are :
Vcc = 14V L = 10mH r = 3 Ohms Ip = 4A
TRANSIL : 1.5KE36P VSRmin = 34.2V (cf data sheet)
a) Single pulse
We find
Pp = 34.2 x 4 = 136.BW
tp
= -
(1.4;~ 10 -
3 )
In
(34~2~~~:~X4)
tp = 1.0Bms
The data sheet gives Pp 1500W for tp = 1.0Bms
then this 1.5KE36P can be used in this
application.
b) Repetitive pulse operation
The commutation frequency is equal to 10HZ so
-3 p= 10X(34.2x10.10 )[4+(34.2-14) In ( 34.2-14 )]
3
3
34.2-14+3x4
= 9BOmW
Rth = 75°C/Wand Tj max. = 175°C
So Tj = P x Rth + Tamb.max.
With Tamb.max. = 50°C we find:
Tj = 0.9B x 75 + 50 = 123.soC < Tj max
So we can also use this Transil in repetitive pulse operation.
-2/2- - - - - - - - - - - - J...,l ~~1i,;mg~~~~~~ - - - - - - - - - - - - -
992
MONITOR &TV CIRCUITS
993
APPLICATION NOTE
VERTICAL DEFLECTION CIRCUITS FOR TV & MONITOR
by Alessandro MESSI
INDEX
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1/24 2. Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/24 3. Ramp Generator ............................................................. 3/24 4. Blanking Generator and CRT Protection .......................................... 4/24 5. Power Amplifier Stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4/24 6. Thermal Protection ........................................................... 5/24 7. Flyback Behaviour ........................................................... 5/24 8. Current - Voltage Characteristics of the Recirculating Diodes .......................... 11/24 9. Calculation Procedure of the Flyback Duration ......................................12/24 10. Application Information ........................................................12/24 11. Supply Voltage Calculation .....................................................14/24 12. Calculation of Midpoint and Gain ................................................17/24 13. Monitor Applications ..........................................................20/24 14. Power Dissipation ............................................................20/24 1.5. Blanking Pulse Duration Adjustment ..............................................22/24 16. Linearity Adjustment ..........................................................22/24 17. Facilities and Improvements ....................................................23/24 18. General Application and Layout Hints .............................................24/24 19. References .................................................................24/24
1. INTRODUCTION
In a general way we can define vertical stages circuits able to deliver a current ramp suitable to drive the vertical deflection yoke.
In Figure 1 is represented the more general possible block diagram of a device performing the vertical deflection.
Figure 1 : Block Diagram of a General Deflection Stage.
Blanking out
r---------~--~--~--~----------~Vs
Rl
01
C3
Zo
AN373/0390
R3
VERT. YOKE
R4
R5
'+l:' C5
+
CB
R7 R6
V90VERT-01
1/24 995
APPLICATION NOTE
Such a device will be called "complete vertical stage" because it can be simply driven by a synchronization pulse and it comprises all the circuitry necessary to perform the vertical deflection that is: oscillator, voltage ramp generator, blanking genetor, output power and flyback generator. At the right side of the dotted line in Figure 1 is represented the circuitry characterizing a "vertical output stage". This kind of device comprises only the power stages and it has to be driven by a voltage sawtooth generated by a previous circuit (for example a horizontal and vertical synchronization stage. In the first class there are the following devices: TDA1170D, TDA1170N, TDA1170S, TDA1175, TDA1670A, TDA1675, TDA1770A, TDA1872A, TDA8176. In the second class there are: TDA2170, TDA2270, TDA8170, TDA8172, TDA8173, TDA8175,
Figure 2 : First Kind of Oscillator Stage.
TDA8178, TDA8179. There is also a third class of vertical stages comprising the voltage ramp generator but without the oscillator; these circuits must be driven by an already synchronized pulse. In this third class there are: TDA1771 and TDA8174.
2. OSCILLATOR
There are two different kinds of oscillator stages used in SGS-THOMSON complete vertical deflections, one is used in TDA1170D, TDA1170N, TDA1170S, TDA1175 and TDA8176, the other in TDA1670A, TDA1675, TDA1170A and TDA1872A. The principle of the first kind of oscillator is represented in Figure 2. The following explanations will be the more general possible; we shall inform the readerwhen we refer to a particular device.
Jl
When the switches T1 and T2 are opened the Co capacitor charges exponentially through Ro to the value V+(MAX) determined by the integrated resistors R1, R2, R3 and R4. At this point the switches are closed, short-circuiting R3 and R4, so the volt-
EV90VERT·02
age atthe non-inverting input becomes V+(MIN). The capacitor Co discharges to this value through the integrated resistor R5. The free running frequency can be easily calculated resulting in :
v: v+ To = Ro' Co' log VR - (MIN) + R5' Co' log (MAX)
(1 )
VR - V (MAX)
V+ (MIN)
1 fo= --
To
with Ro = 360 kQ and Co = 100 nF, it results in 43.7 Hz. The oscillator synchronization is obtained reducing the superior threshold V+(MAX) short-circuiting the
R4 resistor when a vertical synchronization pulse occurs. The second kind of oscillator is represented in Figure 3.
2-/-24--------------------------~~~~~~~~~~~©~ ----------------------------
996
Figure 3 : Second Kind of Oscillator Stage.
VT
RO
,------------------,/
1
APPLICATION NOTE
Vo
When the switch T is in position 2, a constant
current Ico = V . I Ro flows through Co charging it
with a voltage ramp. When the voltage Vo reaches VO(MAX), T passes in position 1, so a constant
currentlco = ( VB . V' ) / Ro discharges the capac-
itor causing the inversion of the voltage ramp slope
V90VERT·03
at the output Vo ( t ). The discharges stops when Vo reaches the value VO(MIN) and the cycle takes place again. It is possible to calculate the free running frequency fo with the following formula:
To = (VO(MAX) - VO(MIN)' Ro' Co + (VO(MAX) - VO(MIN)' Ro· Co
(2)
V -
VB- V-
with VO(MAX) - VO(MIN) = 3.9V, VB = 6.5V, V . =
0.445V, Ro = 7.5kQ and Co = 330nF it results in :
fo = 43.8Hz. The oscillator synchronization is still obtained in the above mentioned way. In order to guarantee a minimum pull-in range of 14Hz the threshold value· has been chosen in Vp = 4.3V. The spread of the free running frequency in this
Figure 4 : Ramp Generator.
kind of oscillator is very low because it mainly depends from the threshold values VO(MAX), VO(MIN) and V . that are determined by resistor rates that can be done very precise.
3. RAMP GENERATOR The ramp generator is conceptually represented in Figure 4.
Vregulated Ix
height control
linearity cantral
V90VERT-04
3/24 997
APPLICATION NOTE
The Voltage ramp is obtained charging the group R1, C1 and C2 with a constant current Ix.
It is easy to calculate the voltage VRAMP That results in:
t
VRAMP (t) = (V(MIN) - R1' Ix) e- R1 . C + R1' Ix
(3)
where V(MIN) is the voltage in A when the charge starts and C is the series of C1 and C2. The resistor R1 is necessary to give a "C correction" to the voltage ramp. The ramp amplitude is determined by Ix = VREG / P1 ,so the potentiometer P1 is necessary to perform the height control. The voltage ramp is then transferred on a low impedence in B through a buffer stage. Te P2 potentiometer connected between D and B
performs the ramp linearity control or "s correction"
that is necessary to have a correct reproduction of the images on the TV set. The voltage ramp in B grows up until the switch T1 is closed by a clock pulse coming from the oSciilator; in this way the capacitors discharge fastly to V(MIN) that is dependent upon the saturation voltage of the transistor that realizes the switch. At this point the exponential charge takes place again.
4. BLANKING GENERATOR AND CRT PRO· TECTION
This circuit senses the presence of the clock pulse
Figure 5 : Amplifier Stage.
coming from the oscillator stage and the flyback pulse on the yoke. If both of them are present a blanking pulse is generated able to blank the CRT during the retrace period. The duration of this pulse is the same of the one coming from the oscillator. If for any reason the vertical deflection would fail, for instance for a short circuit or an open circuit of the yoke, the absence of the flyback pulse puts the circuit in such a condition that a continuous vertical blanking is generated in order to protect the CRT against eventual damages. This circuit is available only in the following devices: TDA1670A, TDA1675, TDA1770A and TDA1872A .. The stages we will consider starting from this point are common both to complete vertical stages and vertical output stages.
5. POWER AMPLIFIER STAGE
This stage can be divided into two distinct parts : the amplifier circuit and the output power. The amplifier is realized with a differential circuit; a schematic diagram is represented in Figure 5.
vs~_ _ _ _~_ _ _ _ _ _ _ _ _ _~_ _ _ _ _ _ _ _~_ _ _ _ _ _ _ _ _ _ _ _ _ _- - .
v -~-----I--I(
to power
The open-loop gain of the circuit is variable from 60dB to 90dB for the different integrated circuits. The compensation capacitor C determines the dominant pole of the amplifier. In order to obtain a dominant pole in the range of 400Hz, the capacitor
V90VERT-05
must be of about 10pF. As an example in Figure 6 is represented the boole diagram of the amplifier open loop gain for TDA8172.
4-/-24--------------------------~~~~@~~~~~~~ ----------------------------
998
APPLICATION NOTE
Figure 6 : Amplifier Open Loop Gain and Phase.
100
80
iii' 60
~
« z
(9 40
20
o
1
IIII
~l'l~
"
" PHASE
"
"
"
"
90
45
Vi'
OJ
0
~
OJ
e.OJ
UJ
- 45 (f) <I: I 0-
- 90
- 135 10 102 10 3 10 4 10 5 10 6 10 7
FREQUENCY, f (Hz)
V90VERT06
The output power stage is designed in order to deliver to the yoke a vertical deflection current from 1 to 2 Apeak, depending upon the different devices, and able to support flyback voltages up to 60V. A typical output stage is depicted in Figure 7.
Figure 7 : Power Stage.
zero, when 01 is turned off and 02 is turned on. When the flyback begins, Q2 is switched-off by 03 in order to make it able to support the high voltage of the flyback pulse. The circuit behaviour during flyback is explained in chapter 7.
BUFFER STAGE
-H--{)/-~--L-----l
6. THERMAL PROTECTION
The thermal protection is available in all the devices except the TDA1170 family and the TDA8176. This circuit is usefull to avoid damages at the integrated circuit due to a too high junction temperature caused by an incorrect working condition. It is possible to sense the silicon temperature because the transistor VSE varies of - 2 mV/ DC, so a temperature variation can be reconducted to a voltage variation. If the temperature increases and it is reaching 150DC, the integrated circuit output is shut down by putting off the current sources of the power stage.
The upper power transistor 01 conducts during the first part of the scanning period when the vertical deflection current is flowing from the supply voltage into the yoke; when the current becomes negative, that is it comes out of the yoke, it flows through the lower power transistor Q2.The circuit connected between the two output transistors is necessary to avoid distortion of the current at the crossing of
7. FLYBACK BEHAVIOUR
In order to obtain sufficiently short flyback times, a voltage greather than the scanning voltage must be applied to the deflection yoke. By using a flyback generator, the yoke is only supplied with a voltage close to double the supply during flyback. Thus, the power dissipated is reduced to approximately one third and the flyback time is halfed.
----------------------------~~~~@~~m~~~~ --------------------------5-/2-4
999
APPLICATION NOTE
The flyback circuit is shown in Figure 8 together with the power stage. Figure 8 : Output Power and Flyback stages.
BUFFER STAGE
Figure 9 shows the circuit behaviuor, to show operation clearly. The graphs are not drawn to scale. Certain approximations are made in the analysis in
V90VERT-08
order to eliminate electrical parameters that do not significantly influence circuit operations.
Figure 9 : Current in the Yoke andVoltage Drop on the Yoke during Vertical Deflection.
I
I
I
I
V1 during flyback
I
I
I
I
I
I
I
I
I
I
~______+I____-LI__~______~,~--~I----------------------+I--_t
to
t1
t2
t3
t4 t5 t6
t7
V90VERT.09
1000
APPLICATION NOTE
a} Scan period (t6 - t7) : Figure 10 During scanning 03, 04 and 05 are off and this causes 06 to saturate. A current from the voltage supply to ground flows through Os, Cs and 06 charging the Cs capacitor up to: VCs = Vs - VDs - V06SAT (4) At the end of this period the scan current has reached its peak value (Ip) and it is flowing from the yoke to the device. At the same time VA has reached its minimum value. In Figures 11 and 12 are depicted the voltage drop on the yoke and the currents flowing through Os and the yoke. Figure 10 : Circuit Involved during Scan Period.
I
V90VERT·10
Figure 11 : Voltage Drop on the Yoke and Current Flowing through Os.
V = 10V/div. I = 0.5A/div. t = 2ms/div.
Figure 12 : Voltage Drop on the Yoke and Current Flowing through the Yoke.
V = 10V/div. I = 1Ndiv.
t = 5ms/div.
v
'--
'-,....
' - - r--.
r--........ I'-........
...............
~
1
~
~
i'---
i'---
~ I
t
V90VERT-12
b} Flyback starting (to - t1) : Figure 13 08, that was conducting the - Ip current, is turned off by the buffer stage. The yoke, charged to Ip, now forces this current to flow partially through the Boucherot cell (h) and partially through 01, Cs and 06 (12). In Figures 14, 15 and 16 are represented the currents flowing through the yoke, the Boucherot cell and 01.
Figure 13 : Circuit Involved during Flyback Starting.
v
- - - ;-- '--
I' ....... -..............
.........
-..............
............
-r-
t V90VERT-11
V90VERT·13
1001
APPLICATION NOTE
c) Flyback starting (t1 -l2) When the voltage drop at pin A rises over Vs, 03 turns on and this causes 04 and 05 to saturate. Consequently 06 turns off. During this period the voltage at pin 0 is forced to :
VD = Vs - V04SAT
(5)
Therefore the voltage at pin B becomes:
Vs = Vcs + VD
(6)
The yoke current flows in the Boucherot cell added to another current peak flowing from Vs via 04 and Cs (Figures 14 and 15).
Figure 14 : Voltage Drop on the Yoke and Current Flowing through the Boucherot Cell.
V = 10V/div. I = 1A1div.
t = 1~s/div.
v ~ ~
f--
__VI
.,r1/
VI t\
[".1
I\ I\
) \ II \
"'-. V
I'
-
V90VERT-14
Figure 15 : Voltage Drop on the Yoke and Cur-
rent Flowing through 01.
V = 10V/div.
I = 1A1div.
t = 1~s/div.
!
- - I--
/
v
V
. / I----(
/.Y
/"'\
I \
I 1\ r-
_.
----~-'---
V90VERT-15
Figure 16 : Voltage Drop on the Yoke and Cur-
rent Flowing through the Yoke.
V = 10V/div. I = 100mAldiv.
t = 1~s/div.
~ l-I
-l.------"" V
/
~
- f..--"t-"
v f.---
/
yV
I
V90VERT·16
-8/-24------------------------- ~~ii@~gmf~~~---------------------------
1002
APPLICATION NOTE
d) Negative current rise (t2 - 13) : Figure 17
Figure 17: Circuit Involved during the Negative Current Rise.
r·lt~SD2 I
D2
cE
I
I
D
I I Ly I
Iece
It results in :
V90VERT·17
During this period, the voltage applied at pin A is :
\r-------------------------------~
VA= Vs+ VOl, VA = Vcs + Vo + VOl, VA= Vs- Vos- V06SAT+ Vs+ V02+ VOl, VA= 2· Vs+ VOl + V02- Vos- V06SAT
(7)
It is possible to calculate the current solving the following equation:
~ f VA = Ly Q!. +
i . dt + R· i
(8)
dt CD
where R = RF + Ry
Because the voltage at pin A is approximatively constant (error less than 2%) we can simplify the (8) in the following equation:
dt2 d 2 i R di
+ Ly Cit + Ly CD i = 0 (9)
i (t) =
Ip e2~M1_
1
e(-(X+ ~)t
_
Ip
e(-U- ~)t
1 _ e-2~M1
(10)
where:
f X =R- 2 Ly
~= ~ R2 4· Ly 2
Ly Co
t.Tl = 13- t2
Because of Ll.Tl is two orders of magnitude lower than the scan time, we can apply an exponential sum to obtain the following equation:
i(t)= Ip fXcosh(2~t.Tl)+ ~sinh(2~t.Tl)- U t _ Ip
(11 )
cosh(2~t.Tl)- 1
------------------------- ~ ~~~~n1g~fll~l~ ----------------------9-/2-4
1003
APPLICATION NOTE
Figure 18: Voltage Drop on the Yoke and Cur-
rent Flowing through the Yoke.
V = 10V/div.
I = 250mA/div.
- t = 100flS/div. y
V
L
'-
/ --,
1/ .~
/
~
/
II
Simplifying:
(a . i (t ) = Ip + _1_ ) t - Ip LlT1
V9DVERT-18
(12)
The slope of the current is therefore:
(R 1) -di = - + -
Ip (Ns)
(13)
dt
2 Ly LlT1
The current flows from the yoke to Vs through D1, Cs and D2, and it is depicted in Figure 18.
e) Positive current rise (h - t4) : Figure 19
Figure 19 : Circuit Involved during the Positive Current Rise.
Q4
V90VERT-19
When the current becomes zero, D1 turns off and 02 saturates; so the pin A voltage becames :
VA = Vs - V02SAT
VA = 2· Vs - Vos - V06SAT
- V04SAT- V02SAT
(14)
The current flows from +Vs into the yoke through 04, Cs and 02 and rises from zero to Ip as it can be seen in Figure 18. By using the previous procedure explained in section d), we can obtain the slope of the current:
(R 1) ddti = 2 Ly + ~T2 Ip (A/s)
(15)
f) Flyback decay (14 - 15) When the yoke current reaches its maximum peak, 02 desaturates and conducts the maximum peak current flowing from Vs via 04 and Cs into Ly; the current flowing through Cs is depicted in Figure 20.
Figure 20 : Voltage Drop on the Yoke and Current Flowing through Cs. V = 10V/div. I = O.5A/div.. t = 100flS/div.
- - '- ~ 1\ "'1 -
IV
V
./ V
V90VERT-20
An eventual antiringing parallel resistor modify the linear decay slope in an exponential one, as it can be seen in Figure 22. This continues until the buffer stage turns 02 on. The effect of the Boucherot cell during this periode is negligible (see Figure 21).
- - 10/24 - - - - - - - - - - - - ~ ~~~,~m~~8l?©~ - - - - - - - - - - - - - -
1004
APPLICATION NOTE
Figure 21 : Voltage Drop on the Yoke and Current
Flowing through the Boucherot Cell.
V = 10V/div.
I 100mA/div.
-..., r-
t = 100f.\s/div.
,v
\
I'"
r I I
V90VERT·21
g) VA pedestal (ts - t6) When VA reaches the value Vs of the supply voltage, the flyback generator stops its function. 03 is turned off and turns off 04 that open the
Figure 22 : Effect of the Resistor in Parallel connected to the yoke. V = 10V/div.
-~
v
\
., ,I -----
" /"\
II \)
I
U
--
V90VERT-22
connection between pin 0 and Vs. Therefore VB drops to Vs - VDB while VA= Vs- VDB- V02CEon At this point the normal scan takes place.
8. CURRENT-VOLTAGE CHARACTERISTICS OF THE RECIRCULATING DIODES.
The following Figures 23 and 24 reproduce the I - V odes 01 and 02 (see Figure 8). characteristics of the integrated recirculating di-
Figure 23 : I - V Characteristic of the Diode 01. V = 500mV/div. I = 200mNdiv.
Figure 24 : I - V Characteristic of the Diode D2. V = 500mV/div. I = 200mA/div.
/
V
I
I
I
if
I
/
: V
I J
V90VERT-23
These characteristics are useful in order to calculate the maximum voltage reached at pin A with the
/
II
/ V
I
/
V
/
formula (7) explained in chapter 7.
V90VERT-24
--------------------------- ---------------------------~~~~~~~m~~~
11/24
1005
APPLICATION NOTE
9. CALCULATION PROCEDURE OF THE FLY· BACK DURATION The flyback duration can be calculated using the following procedure (referring to Figure 25).
Figure 25 : Circuit Involved in the Calculation of Flyback Duration.
The voltage charges the coil with a linear current that can be calculated in the following way:
f ~y f i ( t) = JL..y.. V· dt =
23. Vs' dt (16)
i (t) =
-1- -3 Ly 2
Vs' t +
K
K is calculated imposing that the current at the beginning of the flyback is - Ip.
i ( 0) = - Ip
K = - Ip
i (t) = ~ Vs t - Ip
2 Ly
(17)
V9DVERT-2S
During the flyback period the voltage applied at pin A is about 2 Vs, as previously explained in chapter 7. The voltage drop across CD is approxirnatively a constant voltage little less than Vs /2. The voltage on the feedback resistor RF is :
VRF ( t ) = RF Iy ( t )
so in the period which we are considering it is negligible respect to Vsl2. The effect of the Boucherot cell during this period is not sensible as it can be seen in Figure 21 ; while RD acts principally during the fly back decay time (Figure 9: t4 - ts) reducing its slope and the resulting oscillations but doesn't influence the total flyback time as shown in Figure 22. So their influences are also negligible. Now the effective voltage drop across the yoke can be approximated to :
Figure 25 can be simplified as shown in Figure 26. Figure 26 : Simplified Circuit for the Calculation
of Flyback Duration.
V9DVERT-26
At the end of the flyback period the current will be . + Ip, so we can write:
Ip =
3 Vs -2 -Ly
tF -
Ip
The duration of the flyback period is then:
.± tF = Ip Ly 3 Vs
2 Iy Ly
3 Vs
(18)
10. APPLICATION INFORMATION
The vertical deflection stages producted by SGSTHOMSON are able to cover the complete range of applications that the market need for color television and high/very high resolution monitors. Television and monitor applications are not very different but in monitor field, in addition to the linearity and interlacing problems, we have to pay attention to the flyback time that must be very short for very high resolution models. In television applications the most important requirement is to choose the lowest supply voltage possible in order to minimize the power dissipation in the integrated circuit, reducing the dimension of the heatsink, and the power dissipation from the voltage supplier. These results can be reached very easily with SGS-THOMSON deflection stages because of the high efficiency of the flyback generator circuit used. In high resolution monitors one of the main problems is to reach the very short flyback time requested; the flyback generator, together with the high current and power dissipation capabilities, solve all the problems in a simple way.
-- 12/24 ------------- ~~~i@~g~~9©~ ------------------
1006
APPLICATION NOTE
In Figures 27, 28 and 29 are depicted three typical application circuits for the different kinds of integrated circuits available. Figure 27 : Application Circuit for TDA1170.
r-------------~------~--------~------~----~------------{)V5=26 v
f' sync, 50Hz
RB 3.30
3 RS
390KO
RI 5.6KO
llf---_+-----'
I 1-----<>---18
C6
TDA 1 170N 470pF
IOI--____~--------~-tR:':'I:50----_+
R6
5.6KO
18KO
12
P2 100
R3
R4
C8
100Kl 680KO O.IJlF
R7 47KO
R9 I.SKJ
YOKE Ry=lSO
Ly=30MH
Figure 28 : Application Circuit for TDA1670A.
+Vs
BLANKING OUT
R3 10Kl
13 1--~----15
II
14
2
6
TDA1670A
± 1%
4
CO
3
330nF :t5%
R2 ISKO
R4 · 180Kl
. C5 O.IJlF RS
470KO
RTI
sERvlcEll 220K
SWITCH
HEIGHT
15
R7 1.2Kl
RB 12m
C8 47JlF
IOV
· The value depends on the characteristics of the CRT. The value shown is indicative only.
V90VERT·27
YOKE
V90VERT·28
--~-----------------------------~ ~~~;~g~~~~~~
13/24 1007
APPLICATION NOTE
Figure 29 : Application Circuit for TDA8170.
Vs
Rl 10KO
IN4001
Dl I
I C3 I 220,.r
I
6
3
TDA8170
ty
!--a-:~} ----2'.-
Ly 24.6MH
Ry 9.60
R2
5.6KO
-l\nRSly
~
In the following chapters we shall do the calculation for television and monitor in order to choose the right voltage supply and external network for the yoke used and the current requirements.
11. SUPPLY VOLTAGE CALCULATION For television applications we shall calculate the
V90VERT-29
minimum supply voltage necessary to have vertical scanning knowing the yoke characteristics and the current required for the given application. Figure 30 shows the terms used in this section, while the circuit part involved in the following calculations is depicted in Figure 31.
Figure 30 : Parameters Used in the Calculation of the Supply Voltage.
Vs
'-------'-_ _t_f_ _ _ _ _ _ _ _ _T_S_ _ _ _ _ _ _ _----1 V SAT2
1-4-/2-4------------------------ ~~~~@~~~l~~~~
1008
V90VERT-30
Figure 31 : Circuit Involved in the Calculation of the Supply Voltage.
Vs
APPLICATION NOTE
Figure 32 : Saturation characteristic of the Upper Power Transistor.
VSATI
(V) 3.0
QI
2.0
I--' ----
- - - - - I--'
--I-
-- 1.0
V90VERT-31
Vs
supply voltage.
Vy
nominal voltage required to produce the
scanning current including the feedback
resistance and the 20% increasing for
temperature variations in the yoke
current;
Vy = ( 1.2 Ry + RF) Iy
(19)
VSAT1 = nominal output saturation voltage due
to the upper power transistor 01
(see Figure 32);
VSAT2 nominal output saturation voltage due
to the lower power transistor 02
(see Figure 33);
VOM
nominal quiescent voltage (midpoint) on
the output powertransistors;
Vc
voltage peak due to the charge of Co
capacitor;
Vc=
~
8 . Co
(20)
voltage drop due to the yoke inductance Ly;
~ L_Yt_~_I_y ~I _______V_L_=__
______(_2_1)______
o o
0.5
1.0
1.5
Ip(A)
V90VERT-32
Figure 33 : Saturation characteristic of the Lower Power Transistor.
VSATI (v)
1.5
v
V /
--- 1.0
- - - - - --
0.5
o o
0.5
1.0
1.5
Ip(A)
V90VERT-33
Vo
nominal voltage drop on DB diode in
series with the supply;
T
vertical scan period;
tF
flyback time;
I~ ~~V~s~~ ~ 2 ~ . ~
__________t_F_=__3 _
__________
----------------------------~~~i@~~~:~?©~ -------------------------1-5-/2-4
1009
APPLICATION NOTE
ts
scanning time;
ts = T - tF
Iy
peak to peak deflection current;
Ry
nominal yoke resistance;
Ly
nominal yoke inductance;
RF
feedback resistor.
· t"Vc. due to the tolerance of Co and yoke current regulation;
AVc= 1.1lyts - Vc
(27)
8 CO(MIN)
due to the tolerance of Ly (± 10%) and yoke current regulation;
Referring to Figure 30 it is easy to see that the minimum supply voltage is given by :
Vs = VOM+ VWP (22)
I
.
where:
I
AVL = 1.1 Iy 1.1 Ly V
.
ts
-L
(28)
'-------------------'
AVSAT1 AVSAT2
VSAT1(MAX) - VSAT1 VSAT2(MAX) - VSAT2
2Vy
VOM
+ VSAT2 + Vc + VL
(23)
and:
2Vy
VTOP =
+ Va + VSAT1 - VL - Vc
(24)
So we obtain:
I Vs = Vy + Vo + VSAT1 + VSAT2
I
(25)
For each parameter, it is necessary to calculate the factor p, expressing the percentual influence of every parameter variation on the nominal supply voltage, with the following formulas:
for VOM :
AV
P VOM
,fo_r_V_T_O_P_:_ _ _ _ _ _ _ _ _ _ _ _ _--,
I
AV
The (25) gives the minimum voltage supply if we do not consider the tolerances of the integrated circuit and of the external components, but the calculation, even if it was not realistic; it was useful in order to understand the procedure. Now we shall do the same thing considering all the possible spreads; we can in this way obtain the real minimum supply voltage. We shall follow the statistical composition of spreads because it is never possible that all of them are present at the same time with the same sign.
We must consider the following spreads: o t"Vy due to the variation of yoke and feed-
back resistance and yoke cu rrent, supposing a 10% of regulation range in scanning current and a precision of 7% for resistors;
AVy = ( 1.2 Ry + RF) 1.07 ( 1.1 Iy) - Vy (26)
L _ _--,-_ _ _ _P_=_V_T_O_P_ _ _ _ _ _---'
We have then to calculate the square mean root of the spreads expressed as :
So if we call :
I
VOM1
and:
VTOP1 =
We can write :
Vs = VOM1 + VWP1
(29)
1010
APPLICATION NOTE
An example of calculation will better explain the
procedure. We shall consider a 26", 1100 ,
neck 29.1 mm tube whose characteristics are:
Iy = 1.2 App; Ry = 9.6Q ± 7%; Ly = 24.6mH ± 10%.
We shall use a coupling capacitance Co of 1500flF with + 50% and - 10% tolerance and a feedback resistance RF of 1.2Q.
a) Nominal minimum supply voltage:
Vy = ( 1.2 Ry + RF) Iy = 15.264 V Iy· ts
Vc = 8. CD = 2 V
Ly· Iy _ 1.476 V
ts
VSAT1 = 1.25 V
VSAT2 = 0.68 V
Vo = 1 V YOM = 11.788 V
VTOP = 6.406 V
We obtain: Vs = 18.2V
b) Statistical minimum supply voltage:
tJ.Vc = 2.702V
VY!2
PVYM = YOM
VY!2
PVYT = VTOP
p2 VYM = 1.313. 10- 2 p2 VYT = 4.447. 10- 2
This is a real value for the minimum supply voltage needed by the above mentioned application. In this case we obtain a flyback duration of about:
2 Iy· Ly tF = - - - = 900 ~s
3 Vs
12. CALCULATION OF MIDPOINT AND GAIN For the calculation of the output midpoint voltage, it is necessary to consider the different feedback network for the applications of the various integrated circuits. We shall first consider the TDA1170 family, the TDA1175, TDA2170, TDA2270, TDA8170, TDA8172, TDA8173, TDA8175 and TDA8176. The equivalent circuit of the output stage is represented in Figure 34.
Figure 34 : Circuit Utilized for the Calculation of midpoint and gain for TDA1170, TDA1175, TDA8176, TDA2170, TDA2270, TDA8170, TDA8172, TDA8173 and TDA8175.
Vs
tJ.Vc = 0.445 V
p2 VCM = 1.421 . 10- 3 p2 VCT= 4.813. 10- 3
tJ.VL = 0.31 V
p2 VLM = 6.914· 10- 4
p2 VLT = 2.341 . 10- 3
Rs
tJ.VSAT1 0.45 V
p2 VSAT1T = 4.935· 10- 3
tJ.VSAT2 0.27V
p2 VSAT2M = 5.246· 10- 4
--JLjI= VOM1", YOM (1 +
13.268 V
= 0 J = VTOP1 VTOP (1 +
7.930 V
Vs = VOM1 + VTOP1 21.2 V
V90VERT·34
For DC considerations we shall consider the two
capacitors as open circuits. Because of the very high gain of the amplifier we can suppose: V- = YR. We can so write :
(30)
- - - - - - - - - - - - - - ~ ~~~r0m~~~~~;~ - - - - - - - - - - - - - - 17/24
1011
APPLICATION NOTE
where:
b = RF + Rs
Substituting into the (30) we obtain:
J - v = V (1 RA + RB
l a
R + RF + Rs
(Vi _ VR) RA + RB R1
(31 )
Let's consider now TDA 1670A, TDA 1675, TDA1770A, TDA1771, TDA1872Aand TDA8174.
The equivalent output circuit is depicted in Figure 35.
Figure 35 :Circuit Utilized for the Calculation of Midpoint and Gain for TDA1670A, TDA1675,TDA1770A, TDA1771 , TDA1872A and TDA8174.
Vs
VR
Vo
Vi
R
R1
R2 Vx
RA
11
12
13
Rc
Cc
R8
+
14
Cp
Rs
We can write:
I
-I, 12
(32)
I
,----,--.- - - - - - - - '
where:
V90VERT-35
I
12 + 13 = 14
(33)
'-------
b = Va - Vx
RA
Vx 14 = RB + Rs
with the (32) and (33) we can calculate the DC output voltage. It results in :
(34)
Referring to Figures 34 and 35, it is possible to calculate the transconductance gain of the power amplifier. For this calculation we shall do the follow-
ing approximations: - the capacitors are practically short circuits; - the gain A of the amplifier is very high (A --7 00).
1 -W -~ -------------------------. ~~~~~~~~~~~ ---------------------------
1012
APPLICATION NOTE
For the circuit represented in Figure 34 we obtain:
while for the application in Figure 35 the yoke current results in :
Iy =
~V'
R1 . Rs I
(36)
Iy = R2 + RA / / Rs / / Rc Vi
(37)
R1' Rs
Using the (31), (34), (35) and (36) it is possible to calculate the external feedback network for every
different yoke known the scanning current and the midpoint output voltage.
Figure 36 : Open Loop Gain and Phase for the Application Circuit in Figure 27.
GAIN
DB
60.00
PHASE DEG
45.0
-40.00 .......
.-..
.......
20.00
0.00 -20.00
'" .....
.....
- ~
........
-40.00
10
100
IK
10K
lOOK
FREQUENCY IN HZ
Figure 37 : Open Loop Gain and Phase for the Application Circuit in Figure 28.
GAIN
DB
60.00
t-40.00
"7
.....
20.00 .....
0.00
-20.00
.......
....... ....,
I"
........ ........
....-
r-- ./
r-.. ......
-180.0 1M V90VERT-36
PHASE DEG 45.0
0.0
-45.0
-90.0
-135.0
-40.00
-180.0
10
100
IK
10K
lOOK
1M
FREQUENCY IN HZ
V90VERT-37
-------------- ~ ~~~;mR~:.~~ --------------19/24
1013
APPLICATION NOTE
We can now consider the open loop gain of the whole system amplifier"plus external feedback net-
work. This calculation is useful in order to verify that no oscillations can occur at any frequency.
Figure 38 : Open Loop Gain and Phase for the Application Circuit in Figure 29.
GAIN
DB
40.00
PHASE DEG
45.0
20.00 r--
.....
o
0.00 -20.00 -40.00
........
"-
"' i'oo..
,.,.
........
-60.00
10
100
lK
10K
lOOK
-180.0 JM
FREQUENCY IN HZ
V90VERT·38
We shall consider some typical applications; the results are reported in Figures 36, 37 and 38. It is easy to verify that in all cases, when the gain reaches OdS, the phase margin is about 60°, so the stability of the system is assured.
13. MONITOR APPLICATIONS
In monitor applications the flyback time needed could be very smaller than the one we get using the minimum supply voltage calculation.
It is possible to reduce the flyback time in two different ways: a) increasing the supply voltage, when the nominal value calculated is lower than the integrated circuit limit; b) choosing a yoke with lower values in inductance and resistance and by supplying the circuit with the voltage needed for getting the right flyback time.
same as the one we have explained in the previous chapters for television applications.
14. POWER DISSIPATION
We shall now examine the power dissipation of the integrated circuit and the dimensions of the heatsink. To calculate the power dissipated we must consider the maximum scanning current required to drive the yoke IY(MAX) and the maximum supply voltage VS(MAX) because we have to dimension the heatsink for the worst case. The current absorbed from the power supply is depicted in Figure 39.
Figure 39 : Current Absorbed from the Power Supply during Scanning.
In both cases we have to calculate the biasing and the gain conditions using the nominal voltage and then we fix the supply voltage forthe flyback time requested with the formula (18) :
2 Iy Ly Vs = - - - -
3 tF
The calculation procedure for monitors is so the
ly/2=lp
T/2
T
t
V90VERT-39
- - 20/24 - - - - - - - - - - - - ~ ~~~~,i"Dmg:~,,~~~ - - - - - - - - - - - - - -
1014
APPLICATION NOTE
The equation of the curve is :
Iy i (1) = 2
~t
T
i(1)= 0
for 0 < t:o; T/2
(37)
for T/2 <t:o; T
To the previous one we have to sum the DC current necessary to supply the other parts of the circuit (quiescent current).
The power absorbed by the deflection circuit is then:
PA
fT/2
o VS(MAX)· i (t ). dt + VS(MAX)· IDe
f VS(MAX)
V2
o
(IY- (MA- X) 2
- IY(M- Ax) t} dt + VS(MAX)· T
IDe
The solution is :
PA = VS(MA'X) ( -IY(8MA-x) + IDe )
(38)
The power dissipated outside the integrated circuit is formed by the three following fundamental components : the scanning power dissipated in the yoke for which the minimum resistance of yoke RY(MIN) and the maximum scanning current IY(MAx)
must be considered, the power dissipated in the feedback resistance RF and that one dissipated in the diode for recovery of flyback. The power dissipated outside the integrated circuit is then:
PY
fT ( RY(MIN) +
o
Rf)
2
i (1).
dt +
fV2 0
Vo
i (t) .
dt
J 2
= (RY(MIN) + Rf) ( ( IY(MAX) - IY(MAX) t dt + Vo fT/2 (IY(MAX) - IY(MAX) t) dt
o 2
T
0
2
T
The solution is :
Py = 12 Y(MAX) ( RY(MIN) + Rf) IY(MAX)· Vo
(39)
12
+
8
The power dissipated inside the integrated circuit is :
Po = PA- PY
(40)
The thermal resistance of the heatsink to be used with the integrated circuit depends upon the maximum junction temperature TJ(MAx), the maximum ambient temperature TAMB and the thermal resis-
tance between junction and tab RTH (HAB) that is different for the various packages used. The thermal resistance of the heatsink is expressed by the following formula:
RTH J-AMB = TJ(MAx) - TAMB(MAX) R
PO(MAX)
- TH J-TAB
(41 )
-------------- ~ ~~;~~m~:~g1;~ --------------21/24
1015
APPLICATION NOTE
As an example we can calculate the dissipated power and the thermal resIstance of the heatsink for the 26", 110°, neck 29.1 mm tube for which we calculated the minimum supply voltage in chapter 11.
We shall consider the integrated circuit TDA1670A and we can suppose a maximum supply voltage of 25V. The power absorbed from the supply is :
(\3 J PA = 25 2 + 0.04 = 4.75 W
The power dissipated outside the integrated circuit is :
P _ 1.22 (9.6· 0.93 + 1.2) + 1.21
1.37 W
y -
12
8 -
therefore the power dissipated by the integrated circuit is :
When necessary, it is possible to use a trimmer system to adjust it very carefully.
PD = 4.75 - 1.37 = 3.38 W
The thermal resistance of the heatsink, considering the RTH HAB for the multiwatl package of 3°C/W, a maximum junction temperature of 120°C and a maximum ambient temperature of 60°C is :
120 - 60
RTH H-AMB = 3.38
3 = 15°C/W
For the same application with TDA1170S we have a thermal resistance for the heatsink of about 8°C/W.
16. LINEARITY ADJUSTMENT The complete vertical stages have the possibility to control the linearity of the vertical deflection ramp. There are two different methods to obtain the above mentioned performance.
a) For the first method we shall refer to Figure 41.
Figure 41 : Circuitry for Ramp Linearity Regulation.
15. BLANKING PULSE DURATION ADJUSTMENT
For the devices that have the blanking generator it is possible to adjust the blanking pulse duration. We shall consider as an example the TDA1670A; the circuit arrangement is depicted in Figure 40.
Figure 40 : Circuit Arrangement for Blanking Pulse Duration Adjustment.
The linearity regulation is obtained by means of RA, RB and RT2.
330nF
lN4148
R3
V90VERT-40
By adjusting R3 the blanking pulse duration will be adapted to the flyback time used and the picture tube protection will be ready to work properly.
In order to choose the right values of this components we suggest to follow the following procedure: 1 - Set the amplitude regulation potentiometer RTl for the nominal raster size; 2 - Disconnect the RA resistance; 3 - Adjust the linearity control potentiometer RT2 in order to obtain the top and the bottom of the raster with the same amplitude; 4 - In this condiotion the center of the raster must be narrower then the top and the bottom. If with RA
2-2-/2-4-------------------------~ ~~~©~~~g~~~ ------------------------~--1016
APPLICATION NOTE
disconnected the center is larger than the top and the bottom it is necessary to act on the feedback network. Referring to Figures 27, 28 and 29 it is necessary to increase the capacitors C11, C8 or C6; 5 - After increasing the capacitors it is necessary to repeat the linearity adjustment (R12 potentiometer) in order to get the top and the bottom with the same amplitude again; 6 - Connect the RA resistor and repeat the linearity adjustment (point 3 regulation); 7 - Check the top and the bottom amplitude comparing it with the center. If the center amplitude is still narrower it is necessary to reduce RA. If the center amplitude becomes larger it is necessary to increase RA.
Note : Every time the linearity conditions are changed (for adjusting or setting) before checking the linearity status, the point 3 adjustment must be repeated.
b) For the second method we shall refer to Figure 28. In this case the linearity regulation is obtained acting directly on the feedback network, that is substituting the Rs resistance with a potentiometer. This solution is cheaper than the first one, because it is possible to save the resistors RA, RB (see Figure 41), the potentiometer RT2 and to use only a capacitor instead of the series C1 and C2. On the other hand a disadvantage is due to the fact that the resistance Rs influences not only the linearity of the ramp but also the gain of the amplifier, as it can be seen in the equation (36). So to perform a linearity adjustment it is necessary to act at the same time on the potentiometer in the feedback loop and on the potentiometer RT1 (see Figure 41) in order to correct the vertical amplitude variations. On the contrary, in the method a) the linearity control network doesn't influence any other parameters. this is the reason why the a) method is generally adopted by all television set producers.
17. FACILITIES AND IMPROVEMENTS
In this section we shall briefly examine some facilities which may be useful to improve operations of the television set.
a) Blanking generator and CRT protection for TDA1170 family. At pin 3 a pulse is available which has the same duration and phase as the flyback and amplitude
equal to the supply Voltage. If the retrace duration is not sufficient for carrying out correct vertical blanking, for instance in the presence of text and teletext signals the circuit of Figure 42 can be used. The true blanking generator is formed by 01 ,R3 and C2 and the blanking duration is dependent upon the values of R3 and C2. The other components are used for picture tube protection in the event of loss of vertical deflection current. If for any reason there is no flyback, the transistor 01 is permanently inhibited and provides continuous switch off which eliminates the white line atthe center of the screen. Thermal stability and stability with the supply voltage is good in relation to the simplicity of the application.
Figure 42 : Blanking Generator and CRT Protection for TDA1170.
to pin6
32KO R,
BC238
IN4148
R,
AA116
to pin3 o---.t--r--=J-.--H---r-----[
10KO
D2
C2
Tc 22/,F
1 KO R2
l'
I
to pinl
V90VERT·42
b) Vertical deflection current compensation to maintain picture size with beam current variations.
Changes in the supply voltage or the brightness and contrast controls will bring out changes of the beam current, thus causing EHT and picture size variations. The rate of change of the picture size is mainly dependent upon the EHT internal resistance. In order to avoid variations of the vertical picture size it is necessary to track the scanning current to the beam current. Because the tracking ratio:
LlIYOKE . 100
(42)
LlIBEAM
varies from one chassis design to another, three suggested tracking circuits are shown in Figures 43, 44 and 45.
- - - - - - - - - - - - - - ~ ~~~m~vr;?~~9©~ - - - - - - - - - - - - - - 23/24
1017
APPLICATION NOTE
The circuit in Figure 43 adopts the straight forward technique of linking the vertical scanning current directly to the beam current .Its drawback lies in the fact that a long wire connection is required between the EHT transformer and the vertical circuit, and the layout of this connection could be critical for flashover.
Figure 43 : Circuit for Vertical Scanning Current Variation according with the Beam Current.
---~
I V90VERT-43
The circuit of Figure 44, which links the vertical scanning current directly to the supply voltage, is the simplest one. Its drawback could be incorrect tracking ratio and ripple on the supply voltage.To overcome the drawbacks of the preceding circuit it is usefull to filter out the supply voltage ripple and adjust the tracking ratio by transferring the supply voltage to a lower level by means of a Zener diode as shown in Figure 45. Tracking ratio is adjusted by choosing a suitable Zener voltage value.
Figure 44 : Circuit for Vertical Scanning Current Variation according with the Supply Voltage.
I OPEN
I
V90VERT-44
Figure 45 : Circuit for Vertical Scanning Current Variation according with the Supply Voltage.
V90VERT-45
18. GENERAL APPLICATION AND LAYOUT HINTS In order to avoid possible oscillations induced by the layout it is very important to do a good choice of the Boucherot cell position and ground placing. The Boucherot cell must be placed the most possible closed to the vertical deflection output of the integrated circuit, while the ground of the sensing resistor in series connected with the yoke must be the same as the one of the integrated circuit and different from the one of other power stages. Particular care must be taken in the layout design in order to protect the integrated circuit against flashover of the CRT. For instance the ground of the filter capacitor connected to the power supply must be near the integrated circuit ground.
19. REFERENCES 1) Television Deflection Systems - A. Boekhorst,
J. Stolk - Philips Technical library. 2) TV Vertical Deflection System TDA1170S -
SGS-THOMSON Application Notes.
3) TDA1670A Technical Note - SGS-THOMSON Technical Note.
4) TV and Monitor Vertical Deflection using TDA1670A - O. Cossutta, F. Gatti SGS-THOMSON Application Notes.
5) TDA1670A Flyback Stage Behaviour - A. Messi, G. Nardini - SGS-THOMSON Application Notes.
24/24 1018
APPLICATION NOTE
TDA8102A
by Fabio GRILLI
TECHNICAL INFORMATION
1. ABSTRACT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2. INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3. FUNCTIONAL DESCRIPTION ............................................... 3.1 Horizontal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Horizontal synchronism shaper circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 First phase comparator (<p 1) and phase adjustment interface circuit .. . . . . . . . . . . . . . . . . 3.4 Second phase comparator (<p 2) between flyback and oscillator ..................... 3.5 Phase shifter, output stage and start up circuit ................................... 3.6 Voltage regulator 8V ....................................................... 3.7 Vertical oscillator.......................................................... 3.8 S Correction circuit and DC linearity adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 Vertical amplitude regulation circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4. CONCLUSION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page
2
2
3 3 3 4 4 5 5 6 7 8
8
APPLICATION INFORMATION
5. HORIZONTAL SECTION .............. .. .................... .......... ......
5.1 Frequency............................................................... 5.2 Pull-in range ............................................................. 5.3 Internal sync width. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Phase adjustment range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 Flyback input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6. VERTICAL SECTION ...................................................... 6.1 Frequency............................................................... 6.2 Pull-in range ............................................................. 6.3 Amplitude adjustment range ................................................. 6.4 Vertical DC reference ...................................................... 6.5 Linearity correction ........................................................
7. LAY-OUT HINTS. . . . . . . . . . . . . . . . . . . . . . . . .. . . .. . . .. . .. . . . .. . . . . . . . . . . . . . . . .
8. ADJUSTING PROCEDURE ................................................. 8.1 Horizontal frequency ....................................................... 8.2 Vertical frequency ......................................................... 8.3 Vertical amplitude and horizontal phase ........................................ 8.4 Vertical linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9. COMPONENT LIST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page
10
10 10 10 10 11
11 11 11 12 12 12
13
13 13 13 13 14
16
AN374/0490
1/16
1019
APPLICATION NOTE
TECHNICAL INFORMATION
1. ABSTRACT
The system evolution in the monitor field leads to develop suitable I.C.'s whose performances and characteristics are mainly monitors oriented rather than TV oriented. The automatic frequencies raster preset of the monitor by computer and optical equipments leads to the adoption of Digital to Analog converters in order to set the different parameters, and consequently all regulation must be DC compatible. High scanning frequency and low jitter are additional factors that characterize the quality and the resolution of the monitor. In this note new circuit solutions on silicon, concerning the monitor field, are described. In a single I.C., making use of TTL compatible synchro pulses, horizontal and vertical processing functions and vertical ramp generation are implemented.
INTRODUCTION
In Fig.1 is shown the block diagram of TDA81 02A. Horizontal frequency and phase as well as vertical frequency, amplitude and linearity are all DC ad-
Figure 1.
justable on different terminals.The horizontal
phase adjustment within ± 45° is implemented on
first PLL (sync-oscillator) rather than on the second PLL (flyback-oscillator) allowing the raster to be centered in case of no standard phase sync position.
An additional feature makes the raster phase independent by the duty-cycle of the input synchronizing pulse thanks to an internal shaper circuit generating a standard sync pulse starting from the leading edge of input signal.
The vertical amplitude changes depending on a voltage amplifier whose gain is set on Pin 16 ; the peak to peak voltage of the sawtooth does not influence its average value which is maintained constant.
The current capability of the horizontal output stage (Pin 7) is such to directly drive an external darlington used as line power switch.
Since part of the jitter effect is due to the internal voltage reference circuits, an external pin connected to the Vco supply voltage is got available for noise filtering (Pin 19).
Vref
HOR. OUTPUT PULSE
DC VERT. FREO.
PRESET
V9DTDA81D2A·D1
2-/-16----------------------------~ ~~i@~~~~~~~ ------------------------------
1020
APPLICATION NOTE
3. FUNCTIONAL DESCRIPTION
Here following are briefly described all the functional blocks of TDA81 02A.
3.1 Horizontal oscillator
The circuit in Fig.2 is a Current Controlled Oscillator, it works charging and discharging the capacitor
at pin 2 between two thresholds VS1 = 2.5V and VS2 = 6.5V coming from an internal resistor divider.
This one is also used to provide a voltage reference at pin 1 (V1 = 3.5V) by means of a unity gain amplifier.
Figure 2.
An external resistor connected between Pin 1 and ground sets the current reference.
This current is mirrored with 0.5 : 1 ratio to charge the capacitor Co at Pin 2, and with 2 : 1 ratio to discharge Co.
The charging and discharging time ratio will result in 3: 1.
The differential switch 022-023 is driven by a S-R flip-flop, which changes its state every time that the peak of the triangular waveform reaches one of the two thresholds VS1 or VS2.
HOSC
6~
~5V \..
V90TOA8102A-02
3.2 Horizontal synchronism shaper circuit
The electric diagram shown in Fig.3 can be divided in three stages. The first of which is a negative edge detector able to set the S-R flip-flop each time that a negative edge of the sync pulse is applied to the input (Pin 4).
The second one is a differential stage that feeds the first phase comparator (<p1).
The third stage uses an external capacitor to produce a ramp on the Pin 5. As soon as the peak of the ramp reaches the internal threshold (6V) the external capacitor is suddenly discharged and the flip-flop is reset.
The horizonal sync pulse width on the collector of 059 will depend on the value of the capacitor at Pin 5.
Figure 3.
SYNC
Vref
5
~ ov
I
V90TOA8102A-03
1021
APPLICATION NOTE
3.3 First phase comparator (<pi) and phase adjustment interface circuit
In the circuit of Fig.4. a comparator squares the horizontal waveform using as voltage reference Vrefl which represents the output of the phase adjustment interface circuit.
If the voltage at Pin 10 changes in the range from 0.5V to 4.5V, the phase will shift of ± 45° between the sync and the flyback pulse.
Figure 4.
Vref
The rectangular waveforms that are the outputs of first differential amplifier are applied to another differential stage which is activated only during the horizontal sync pulse coming from the horizontal sync shaper circuit.
The product in terms of current of the sync signal and the oscillator signal is available at Pin 3.
Two clamp limit the maximum voltage range of Pin 3 (from 1V to 6V) and consequently the hold in
range of the ceo.
Vref1
DC HOR PHASE ADJ.
3.4 Second phase comparator (<p 2) between flyback and oscillator This circuit recovers dynamically the deflection delay of line output transistor.
The flyback pulse applied to Pin 8 (see Fig.5) is detected and clamped at a voltage level of 0.7V.
Figure 5.
HOSC SYNC
V90TDA8102A-04
This circuit is similar to <p 1, the substantial differences are two, the input pulse is the flyback pulse instead of sync pulse and the first differential stage is activated by S-R flip-flop of horizontal oscillator. The <p 2 output acts on the horizontal output stage in order to shift the output pulse to recover the deflection delay.
HOR FL YBACK INPUT
'--_ _ _ _ _ _ _ _ _ _ _ _C_HA_R_G_E_ _ _D_IS_CH_A_RG_E_ _ _ _ _ _ _ _ _ _ _ _V~90TD.A8102A-05
4-/1-6 -------------~~~~;~;9~~~~~ - - - - - - - - - - - - - - - -
1022
APPLICATION NOTE
3.5 Phase shifter, output stage and start up circuit
The storage time ts of the line output transistor is recovered by advancing the leading edge of the output pulse of ts with respect to the phase of the sync reference.
The triangular oscillator waveform (Fig.6a) is compared with internal threshold 81 and 82 whose voltages depend upon the voltage level present at
the output of phase comparator cp 2.
The voltage difference 81-82 is constant and this value fixes the duty-cycle of the horizontal output
pulse present at Pin 7.
Figure 6a.
During the positive slope of the oscillator the output pulse (Pin 7) is low when the triangular waveform voltage is in the voltage range established by 81 and 82; whereas during the negative slope of the oscillator the output pulse is always at high level thanks to a comparator drived by 8-R flip-flop of horizontal oscillator. As shown in Fig.6a, a transistor insures that the output pulse is low when the flyback pulse is present. At the switch on, the horizontal output stage (Pin 7) is inhibited until the power supply does not over-. come 8 V.
+vs
/ \ / \ / H",O::::SC='--_+--l Ping
Figure 6b.
~CKPULSE
II
II
OSCILLATOR RAMP
II
I A
B
b~I
.~l
:.
I,
I I
~ OUTPUT PULSE
-'
HOff II )
6.5V - 4.5V
2.5V
V90TOA8102-06A
About the maximun allowable delay, it depends on the flyback time and the working frequency (see Fig.6b). The PLL2 works in such a way to maintain the middle of the flyback exactly in correspondence between the crossing of the VREF = 4.5V and .the oscillator ramp. Then if you suppose to have zero delay time, the switch-off edge of the output pulse will rise at point "A" now if the delay time increases the switch-off edge will move to point "8" to recover the delay. The equation to calculate the to with a good approximation is the following:
Maximum Allowable Delay: to = ~ _ tFLY
2 2
V90TDA81 02-068
where tR is the rise time of the horizontal ramp = 3/4 T and tFLY is the flyback time.
- - - - - - - - - - - - - - - - ---------------~~~~;~g~l~~~~
5/16
1023
APPLICATION NOTE
3.6 Voltage regulator 8 V
The voltage reference, Fig.7, is a band·gap circuit that allows on the output a voltage reference equal to 2.622V that means a voltage VL = 8V. By means of zener zap is possible to adjust, during
the testing, the voltage reference from ± 6% into a ± 2% range.
VL feeds all the circuits of the vertical side and, by means of a unity gain amplifier, provides a voltage reference (VREF) at Pin 19 to supply all the circuits of the horizontal side. The unity gain amplifier is necessary to avoid all the possible interactions between the· horizontal and vertical sections. Moreover, to minimize jitter on the horizontal oscillator, is possible to connect an external capacitor between Pin 19 and ground.
Figure 7.
Vref V90TDA8102A-07
3.7 Vertical oscillator
A newconcept of vertical oscillator is implemented in this I.C. whose resistor divider, used to set the
lower and higher thresholds (Vlow = 2V ;
Vhigh =6.8V), is not com mutated .
The circuit shown in Fig.8 works charging an external capacitor connected at Pin 13 with a current set at Pin 12 and reflectd to Pin 13 through a current mirror.
As soon as the ramp gets Vm or Vhigh the capacitor is quickly discharged by a darlington, the voltage on the capacitor will fall down till to get the lower threshold; at this point the darlington will be driven off and the current will charge again the capacitor.
A buffer is used to decouple the ramp generator from other circuits (like linearity correction and amplitude regulation circuits).
The lower threshold is detected by a differential stage whose current generator is only activated during the discharge phase.
A comparator detects the higher threshold corresponding to the free running frequency; if no sync
pulse (negative edge) is applied on Pin 14, this stage is continually fed and the capacitor at Pin 13 is discharged when the vertical ramp reaches Vhigh. If the sync pulse is present the previous comparator will be inhibited and another comparator, which has the threshold at S.2V (Vin), will be activated.
This last comparator, when it is set going, is able to cause the discharge of the capacitor at Pin 13 if the vertical ramp is between the thresholds Vm and Vhigh. In this way the vertical synchronization is established. To guarantee that the vertical oscillator is locked in the Il)iddle of the pull-in range is necessary to adjust the current at Pin 12 until the peak of the vertical sawtooth, in locking condition, reaches the voltage equal to:
Vp = Vm + Vhigh 2
6V
that means Vpp = 4V.
6~/1~6-----------------------~~iiID~~~~~4 ---------------------------
1024
FigureS.
VL
APPLICATION NOTE
ENABLE
S
Q
R
Q
7
vasc
~~
14 VERT SYNC INPUT
V90TDA8102A-08
3.8 S Correction circuit and DC linearity adjustment
The circuit which is used to realize a new concept of vertical linearity regulation is shown in Fig.9.
A comparator squares the vertical sawtooth using as voltage reference a fixed value (4V) that is the average value of sawtooth.
This squared signal is used to drive a particular configuration of differential stage in order to obtai n, in terms of current, a triangular waveform which
Figure 9.
inverts its slope just when the original sawtooth crosses the voltage reference.
This current signal is converted in voltage by a resistor divider and transferred on Pin 18 through a buffer.
The peak to peak voltage on this pin depends on the maximum current that the output differential stage is able to handle, the value of this current can be externally regulated by means of Pin 17 through a transconductance amplifier.
+Vs VL
DC VERT. LINEARITY
ADJ.
An external feedback resistor in series to a capacitor (to avoid any DC offset) must be connected
V90TDA8102A-09
between Pins 18 and 12 in order to obtain the proper S correction as shown in Fig.1 O.
----------------------------~~i~@~~:~~~ ------------------------7~/1~6
1025
APPLICATION NOTE
Figure 10.
vase
(v)
6
4
2
V18
Feedback effect
t (ms)
3.9 Vertical amplitude regulation circuit
This function has been implemented using the circuit configuration that can be seen in Fig.11. It consists of an Op-Amp in non inverting input configuration and of a variable gain OTA whose gain can be set by means of the Pin 16 through a transconductance amplifier. Both the inputs of the two circuit handle the vertical ramp and the output of the multiplier is fed back to the inverting input. The control circuit is a transconductance amplifier that modulates the current of the variable gain OTA depending on the DC voltage applied on Pin 16.
Figure 1.1.
V90TDAe,102A·10
This circuit guarantees a gain adjustment of ± 20%
around the nominal value.
4. CONCLUSION
This new I.C. can be considered as a first step towards a new generation of serial bus compatible LSI circuits in which additional logic function can be implemented and all the O/A converters can be included.
It is assembled in 20 pins OIL plastic package able to dissipate the 0.7W required by a typical application.
V90TDA8102A·11
8-/-16--------------------------~~~~@~?~~~~~ ----------------------------
1026
APPLICATION INFORMATION
In Fig.12 is shown a typical application of the TDA8102 A with the TDA8172, which is a vertical booster; for further information regarding TDA8172 consult the note:
Figure 12.
o o z
~r
SGS-THOMSON "Vertical Deflection Stages for TV and Monitor" by A. MESSI
All the information is referred to the above mentioned figure.
- - - - - - - - - - - - - ~ ~~~~m2~~2~ - - -
V90TDA8102A-12
9/16 1027
APPLICATION NOTE
5. HORIZONTAL SECTION
5.1 Frequency The device is able to work from 15 KHz to 100 KHz. The free running frequency is fixed by the resistor at Pin 1 (R25) and by the capacitor at Pin 2 (C17) with the following formula:
5.2 Pull-in range
This range is determined by the ability of the first comparator (<p 1) to correct the difference between the sync frequency and the free running frequency and it is set by R24 and R25.
where Ko is typically 3.0476 ±5% (see data-sheet).
In the aplication of Fig.12, using R25 = 6.8kQ and
C17 = 1.8nF, we obtain:
IV3 - Vll is typically 2.5V, while Vl = 3.5V. This is the theoretical value calculated if the frequency adjustment is disconnected. In the application inf Fig.12 we have:
106
fa =3.0476 x 6.8 x 1.8 =26.808kHz
f .-
pull-In -
26808
32..55
566800000
-_ +- 2.3kHz
The maximum available current at Pin 1 is 1mA, so it must be RVl :::; 1mA.
25 By means of trimmer P4 , it is possible to adjust the horizontal free running frequency, that changes accordingly with the following formula:
where 0:::; Vp :::; 8V is the voltage at the central point of the trimmer (see Fig.13).
Figure 13.
When the frequency adjustment is connected the pull-in range changes due to the fact that in parallel with R25 are connected R26 + Pb (see Fig.13).
When the device is synchronized and perfectly tuned, V3 = Vl and the <p 1 will work in the best way.
C17, on the contrary of RZ5, is influential only for the free running frequency of the horizontal oscillator; it has no effect on the pull-in range, which doesn't change in percentage with respect to the free running frequency.
If you change the horizontal frequency changing RZ5 the pull-in range changes accordingly with the previous formula.
5.3 Internal sync. width
The internal sync. pulse is made by current generator (15) that charges an external capacitor at Pin 5 (C2l) up to the trigger threshold V5 = 6V.
t5 = 1 / (12 x fa) is recommended.
V90TDA8l02A·13
5.4 Phase adjustment range
The voltage range accepted at Pin 10 is from 0.5V to 4.5V, so the resistor divider must be dimensioned to supply these values.
In our application we have:
--' 10/16 .:...-'----------- ;;.:;y ~~~~lm2:~~u;~ - - - - - - - - - - - -
1028
APPLICATION NOTE
V10 min
V19 Rs R7 + P3 + Rs
8 39+47+5.1 5.1
= 0.447V
V19
R7 + P3 + Rs (P3 + Rs)
8 39 + 47 + 5.1 52.1
= 4.575V
3.5 x 106
fv = ( 6.S _ 2 ) x 220 x 62 = 53.4Hz
With the trimmer P5 is possible to change the current that charges C16 and consequently to change the free running frequency.
The current in C16 due to this correction become:
5.5 Flyback input
The resistor in series at Pin 8 (R27) must be dimensioned in order to have an input current included between O. 7mA and 2mA (typ 1mAl, according with the following formula:
where 0 ::; Vp ::; SV is the voltage at the central point of the trimmer (see Fig.14).
R _ Vfly - 0.6V 27 - 1mA
Figure 14.
6. VERTICAL SECTION
6.1 Frequency The device is able to work form 30Hz to 120Hz. The free running frequency is fixed by R21 and C16. The formula to calculate the free running frequency is the following:
fv =
Ie
(Vhigh - View) X C16
but
V90TDAS102A·14
V12 Ie = I = R21 ::; 0.5mA
then
f _
V12
v - ( Vhigh - View) X C16 X R21
where V12 = 3.5V, Vhigh =6.8Vand View = 2V.
In the application proposed the free running frequency is:
It is easy to substitute the new Ie in the formula in order to obtain the new free running frequency.
6.2 Pull-in range The vertical pull-in range is fixed by internal thresholds.
With reference to figure 15 :
- - - - - - - - - - - - - - ~ ~~~;mg~iP©~ - - - - - - - - - - - - - - 11/16
1029
APPLICATION NOTE Figure 15.
Vhigh
R 5
V19 + P2 +
R 6
(P2
+
R6)
8 39+47+5.1 52 .1
= 4.575V
V90TDA8102A-15
This system allows a vertical ramp amplitude vari-
ation of ± 20% around the nominal value; the value
of amplitude of vertical ramp at Pin 15 can be
determined with the following formula:
we can write :
fpull - in = f max - Iv
1 Imax=-t- t
v- s
(Vhigh - V m )
ts=(V' V)XtV =K14 X tV
high - low
Where K15 is typically 1 and K16 is typically 0.1 (as you can see on the data-sheet).
6.4 Vertical DC reference
The average value of the vertical ramp at Pin 15 is the half of V19, then with a resistive divider this DC voltage can be used as reference for the vertical booster as shown in Fig.12.
For a best noise immunity we suggest to lilter V19 with an electrolytic capacitor.
the value 01 K14 is 0.333 (see data-sheet).
6.3 Amplitude adjustment range The voltage range accepted at pin 16 is from 0.5V to 4.5V.
So the resistor divider must be dimensioned to supply these values.
In our application we have:
6.5 Linearity correction
The "S" correction is performed with the new concept described in chapter 3.8.
The adjustment is obtained varying the DC voltage at Pin 17 from 1.5 to 4.5V, then the resistor divider (R3, Pi and R4) must be dimensioned for obtaining this range of values.
In our application we have:
V19
R6
R5 + P2 + R6
8 39+47+5.1 5.1
= 0.447V
V17min 51 +47+2222 = 1.466V
1-2-/1-6-------------------------~~~i@~9M~~~r,~ ----------------------------
1030
APPLICATION NOTE
V17max 51 + 47 + 22 69
=4.6V
The "8" correction is not performed when the voltage at Pin 17 is 1.5V, while it is maximum when the Pin 17 voltage is 4.5V. You can verify this using the following formula:
V18pp = K18 (V17 - 1.5)
where K18 is typically 1. If the CRT requires a higher "8" correction, it is possible to obtain it reducing the value of R2o; however take care that CIS in series with R20 is a high-pass filter with the purpose to cut only the Dc. In our application we have:
cal amplitude, linearity and horizontal phase. Before starti ng these operations take care that the horizontal and vertical synchronization pulses are properly applied to the device inputs.
8.1 Horizontal frequency
Adjust P4 in order to obtain V3 = VI; in this way the
horizontal synchronisation is perfect, and the pull-in range is maximum in both directions.
8.2 Vertical frequency Adjust tile vertical ramp amplitude using Ps in order to have 4Vpp; in this way the vertical frequency value is in the middle of the synchronization range; as shown in Fig.16.
Figure 16.
Vosc (V) 6
V high --- - - -- - .- -- - -- -- --- - 6
ft 6.28 x 150 x 1
= 1.06 Hz
The "C" correction is obtained with a resistor in series to a capacitor connected between Pin 15 and the central point of the vertical DC feedbac:k of vertical booster (R19 and CI4). The value of R19 is strictly dependent on CRT used.
7. LAY-OUT SUGGESTIONS It is necessary to take care not to connect the horizontal output ground (Pin 6) directly to Pin 11, to avoid horizontal interference on vertical stages. The 15nF capacitors connected on Pins 10, 16 and 17 have the only aim to filter the DC control voltage against horizontal noise, so they must be connected as close as possible to the above mentioned pins.
8. ADJUSTING PROCEDURE Here following it is shortly described the procedure to adjust horizontal and vertical frequencies, verti-
Ramp at Pin 13
----{>
tu
--------------~l>
Vertical Sync.
V90TDA8102A·16
This operation is important because some internal circuits are dimensioned for a 4vpp ramp.
8.3 Vertical amplitude and horizontal phase Looking at the display correct P2 for the right vertical amplitude and adjust P3 in order to have the correct horizontal phase.
- - - - ' - - - - - - - - - - - - ~ ~~,~":J!1~~~B~ - - - - - - - - - - - - - - - 13/16
1031
APPLICATION NOTE
8.4 Vertical linearity If the vertical ramp at Pin 13 is correctly set the central point of the "M" waveform at Pin 18 will be at the center of the scan; in other case, using Ps, lead the central point of "M" in correspondence of the scan center (see Fig,17),
where: ts = scan time tv = 1Ifv = vertical period
Figure 17.
tsc ='scan centre tc = period centre
In this way the S linearity correction has a uniform behaviour on the top and bottom sides of the CRT. Now looking at the display, adjust P1 to obtain a right S correction and select R19 value to optimise the C correction,
4V
: Rampat '~ Pin 13
Vertical Scan
, , ,
-
-
--
-
--
-
-
-
-
-
-, , ,
--
,
-, ,
--
-
_
...
Waveform' at Pin 18
, ,
, ,
, ,
, ,
·
: tsc
:
~----':.ts
t9
~4r-------~Qr7_------~~tv
V90TDA8102A-17
-14-/1-6---------------------------~ ~~~@~2~:~©~ ------------------------------
1032
Figure 18: Solder Side.
APPLICATION NOTE
Figure 19 : Component Side.
V90TDA8102A-18
0 000
0 00 0
0 0
0
a
0 0
0 00
0 0
0
0
0
a 0
0
a
o· 0
0
0
0
0
V90TDA8102A-19
_____________ -----'--------~-- i:fi ~~~~;rng~~J!~~~
..:.15~/..:..:::16
1033
APPLICATION NOTE
Figure 20 : PCB Layout
VERTICAL AllPLlTlJIIE
-ADJ. VEIlTICAL !JlJ. ~RlZQOm"'cAyL
ADJ. HOIUZOlfUJ.
Pl!ASE ADJ. vnmCAL FREQUENCY ADI.
· . . . .CIlL).
8 ... G)
.CBS:).
'C!!D'
~i~
§
~i! ~~
1)
i;;
~
1 ·
· J
~
·0lD·
0 :~:.~®~ .=. ·CRtD·
'Cl!D'
0 cb":fu H·~0 on +· «ID ·· aD nu;
~I~I :~ §
8 .. I'
'1 ·
! ell. 'CR!D'
~ ·8 ~ ~ G ~
.. .~ ~Gl ~ ~ .·
s 0<.'0<.-
.CJt!C).
0
.Cl!D'
0
·
1 ·
mD·:~,,·:tiD--am:::>-.. ~
"'8. · · «ID
"
GD
~ ~
(TID: : 8~ @' W,~ ~· aD
. c = . '.4. C13 n
.. rn'DOI.TD' .c"
(2J
COWCTION
,
N
".0. +
.· ,~,
,
· I
ADJ.
·
§~B ~i ~5 ~~
~ !! S:!''-l
1:\:1" 0
V90TDA8102A-20
9. COMPONENT LIST
Component
R" R2, R23 R3 R4, R1Q, Rn, R26
R5, R7 R6, Rs
_R9
- -R'2 R'3 R'4
_R1S
f- R'6
~7
~-R'9
Value 3.3kQ 51kQ 22kQ 39kQ 5.1kQ 82Q/2W 10kQ 120Q 1.5Q 1.5kQ
1Q 2.7kQ 1.2kQ 33kQ
Component R20 R2l R22 R24 R2S R27 R2S, R29 P" P2, P3, Ps, P6 P4 C" C6, C9 C2, C'3 C3, C4, Cs, C,S C7 Cs
Value 150kQ 62kQ 220kQ 56kQ 6.8kQ 100kQ 2.2kQ 47kQ her. 47kQ ver. 100nF 470llF / 16V 15nF 1000llF / 25V 100llF / 16V
Component
C'0 Cn C'2, C'6 C'4 C,S
C'7 C'9 C20 C2l 0, IC, IC2 IC3
-Value 220llF / 25V 2200llF / 16V 220nF 10llF / 63V
11lF 1.8nF 2.21lF / 63V 22nF 220pF 1 N4001 L7812 TOA8102A TOA8172
-------.J
16/16 1034
APPLICATION NOTE
TEA51 01 A - RGB HIGH VOLTAGE VIDEO AMPLlFLIER BASIC OPERATION AND APPLICATIONS
SUMMARY DESCRIPTION .
1.1
1.2
1.3
1.4 1.4.1. IA.2. 1.4.3.
INPUT STAGE
OUTPUT STAGE.
BEAM CURRENT MONITORING
PROTECTjON CIRCUITS MOS Protection Protection Against Electrostatic Discharges Flashover Protection . .
II
11.1
11.1.1 11.1.2. 11.1.2.1. 11.1.2.2.
11.2
11.2.1. 11.2.2.
m
111.1
111.1.1. 111.1.2. 111.1.3. 1I1.1A.
111.2
111.2.1. 111.2.2. 111.2.2.1. 111.2.2.2. 111.2.2.3. 111.2.3. 111.2.3.1. 111.2.3.2.
FUNCTIONAL DESCRIPTION
VOLTAGE AMPLIFIER . . .
Bias Conditions .. Dynamic Operation. . .
White To Black Transition Black To White Transition
BEAM CURRENT MONITORING
Stationary State . . . . . . . Transient Phase . . . . . . . .
EXTERNAL COMPONENTS CALCULATION
COMPONENTS VALUE CALCULATION .
Feedback resistor . . . . . . . . Input resistor . . . . . . . . . . . Bias resistor . . . . . . . . . . . Current measurement resistor ..
DISSIPATED POWER
Measurement method .. . Results . . . . . . . . . . . . . .
Static power . . . . . . . . . . . . . . . . Measurement with sinusoidal input . . . . Measurement in a TV set . . . . . . . . . Design of external components . . . . . . . Heatsink . . . . . . . . . . . . . . . . . . Power rating of feedback resistor . . . . . . .
IV
APPLICATION HINTS . . . . .
IV.1
DYNAMIC PERFORMANCES.
IV.2
CROSSTALK . . . . . . . . . .
IV.3
FLASHOVER PROTECTION . . . . . . . . . . . .
IVA
OUTPUT SWING. . . . . . . . . . . . . . . . . . .
IV.5
LOW CURRENT MEASUREMENTS ....... .
By: Ch. MATHELET
Page 3
3
4
4
4 4 4 4
4 4 4 4 5 5 6 6 6
7 8 8 8 8 8 9 9 9 9 9 10 10 10 10
10 10
11
12
13
15
V
APPLICATION EXAMPLES ...
16
V.1
APPLICATION DESCRIPTION .
16
V.2
PERFORMANCES EVALUATION
16
V.2.1. Measurements conditions
16
V.2.2. Results.
16
V.2.2.1.
Bandwidth
16
V.2.2.2.
Crosstalk ..
16
V.2.2.3.
Transition times
16
AN377/0490
1/23 1035
APPLICATION NOTE
The aim of this Application Note is to describe the basic operation of the TEA51 01 A video amplifier and to provide the user with basic hints for the best utilization of the device and the realisation of high performance applications. Application examples are also provided to assist the designer in the maximum exploitation of the circuit.
· for automatic adjustment of cutoff and also, where required, video gain in order to improve the long term performances by compensation for aging effects through the life of the CRT. This adjustment can be done either sequentially (gun after gun) or in a parallel mode.
· for limiting the average beam current
GENERAL
The control of state-of-the-art color cathode ray tubes requires high performance video amplifiers which must satisfy both tube and video processor characteristics.
When considering tube characteristics (see fig 1314 on page 14),we note that a 130V cutoff voltage is necessary to ensure a 5mA peak current.However 150V is a more appropriate value if the saturation effect of the amplifier is to be taken into account. As the dispersion range of the three guns
is ± 12%, the cutoff voltage should be adjustable
from 130V to 170V. The G2 voltage, from 700 to 1500V allows overall adjustment of the cutoff voltage for similar tube types.
A 200V supply voltage of the video amplifier is necessary to achieve a correct blanking operation. In addition, the video amplifier should have an output saturation voltage drop lower than 15V, as a drive voltage of 130V (resp. 115V) is necessary to obtain a beam current of 4 mA for a gun which has a cutoff point of 170V (resp. 130V).
Note: For all the calculations discussed above, the G1 voltage is assumed to be Ov.
The video processor characteristics must also be considered. As it generally delivers an output voltage of 2 to 3V, the video amplifier must provide a closed loop DC gain of approximately 40.
The video amplifier dynamic performances must also meet the requirements of good definition even with RGB input signals (teletext, home computer...), e.g. 1mm resolution on a 54cm CRT width scanned in 521ls. Consequently, a slew rate better than 2000V/IlS, i.e. rise and fall times lower than 50ns, is needed. In addition, transition times must be the same for the three channels so as to avoid coloured transitions when displaying white characters. The bandwidth of a video amplifier satisfying all these requirements must be at least 7MHz for high level signals and 1OMHz for small signals.
One major feature of a video amplifier is its capability to monitor the beam current of the tube. This function is necessary with modern video processors:
A video amplifier must also be flashover protected and provide high crosstalk performances. Crosstalk effects are mainly caused by parasitic capacitors and thus increase with the signal frequency. A crosstalk level of -20dB at 5MHz is generally acceptable.
Table 1 summarizes the main features of a high performance video amplifier.
The SGS-THOMSON Microelectronics TEA51 01 A is a high performance and large bandwidth 3 channel video amplifier which fulfills all the criteria discussed above. Designed in a 250V DMOS bipolar technology, it operates with a 200V power supply and can deliver 100V peak-to-peak output signals with rise and fall times equal to 50ns.
The 5101 A features a large signal bandwidth of 8MHz, which can be extended to 10MHz for small signals (50 Vpp).
Each channel incorporates a PMOS transistor to monitor the beam current. The circuit provides internal protection against electrostatic discharges and high voltage CRT discharges.
The best utilization of the TEA 5101A high performance features such as dynamic characteristics, crosstalk,or flashover protection requires optimized application implementation. This aspect will be discussed in the fourth part ofthis document.
Table 1: Main features of a high performance video amplifier
Maximum Supply Voltage
220V
Output voltage swing "Average"
100V
Output voltage swing "Peak"
130V
Low level saturation (refered to VG 1)
15V
Closed loop gain
40
Transition time
50ns
Large signal bandwidth
7MHz
Small signal bandwidth
10MHz
Beam current monitoring
Flash over protection
Crosstalk at 5 MHz
-20dB
2-/-23--------------------------~~~~~~gv~~9~~ ----------------------------
1036
APPLICATION NOTE
I - DESCRIPTION
The complete schematic diagram of one channel of the TEAS1 01 A is shown in fig 1.
Figure 1.
9
feedback output
(~;)
Voo 5
R7
D.3 R10
20K
cathode output
cathode current
T4 T 1 350
R1 2.5K
350 T 2 .1--+--;-----, C
3pF
V90TEA5101A-01
1.1 INPUT STAGE
The differential input stage consists of the transistor T1 and T2 and the resistors R4,R5 and R6.
This stage is biased by a voltage source T3,R1,R2 and R3.
VB(T1) =
(1
+
R2 R3)
x
VB(T3)
==
3.SV
Each amplifier is biased by a separate voltage source in order to reduce internal crosstalk. The load of the input stage is composed of the transistor T4 (cascode configuration) and the resistor R7. The
cascode configuration has been chosen so as to reduce the Miller input capacitance. The voltage gain of the input stage is fixed by R7 and the emitter degeneratio.n resistors R5, R6,and the T1,T2internal emitter resistances. The voltage gain is approximately SOdB.
Using a bipolar transistor T4.and a polysilicon resistor R7 gives rise to a very low parasitic capacitance at the output of this stage (about 1.SpF). Hence the rise and fall times are about SOns for a 100V peak-to-peak signal (between SOV and 1S0V).
---------------- ~~~iG~~~~~~~ ----------------3/23
1037
APPLICATION NOTE
1.2 OUTPUT STAGE
The output stage is a quasi-complementary class B push-pull stage. This design ensures a symetrical load of the first stage for both rising and falling signals. The positive output stage is made of the DMOS transistor T5,and the negative output stage is made of the transistors PMOS T6 and DMOS T7. The compound configuration T6-T7 is equivalent to a single PMOS. A single PMOS transistor capable of sinking the total current would have been too large.
By virtue of the symetrical drive properties of the output stage the rise and fall times are equal (50ns for 1OOV DC output voltage).
1.3 BEAM CURRENT MONITORING
This function is performed by the PMOS transistor Ts in source follower configuration. The voltage on the source (cathode output) follows the gate voltage (feedback output). The beam current is absorbed via Ts . On the drain of Ts, this current will be monitored by the videoprocessor.
1.4 PROTECTION CIRCUITS
1.4.1. MOS protection
Four zener diodes DZ(I-4) are connected between gate and source of each MOS in order to prevent the voltage from reaching the breakdown voltage.Hence the VGS voltage is internally limited to ±15V.
1.4.2. Protection against electrostatic discharges
All the input/output pins of the TEA51 01 A are protected by the diodes Dl-D7 which limit the overvoltage due to ESD.
1.4.3. Flashover protection
A high voltage and high current diode Ds is connected between each output and the high voltage power supply. During a flash, most of the current is generally absorbed by the spark gap connected to the CRT socket. The remaining current is absorbed by the high voltage decoupling capacitor through the diode Ds. Hence the cathode voltage is clamped to the supply voltage and the output voltage does not exceed this value.
II - FUNCTIONAL DESCRIPTION
The schematic diagram of one TEA51 01 A channel with its associated external components is shown in fig.2
11.1 VOLTAGE AMPLIFIER
11.1.1. Bias conditions Vin = V,el
The bias point is fixed by the feedback resistor Rt,the bias resistor Rp, and by the internal reference voltage when Vin = V,et.
If Vois the output voltage (pin 9) :
Rt
Va = (1 + Rp) x V,et
(1 )
In this state Tl and T2 are conducting. A current
flows in R7 and T4 soTs is on. The Ts drain current
is fed to the amplifier input through the feedback
resistor. The current in R7 is:
.
I(R = VDD-Va-VGs(Ts)", VDD-Va
7)
R7
- R7
and the current in Ts and Rt is: I(T _ Va,- V,et _ Va
S) - -R-t-- = Rt
Thus the total current absorbed by each channel of the TEA51 01 A is :
-VD+DVa x (1- - -1)
R7
Rf R7
The cathode (pin 7) output voltage is:
Va + VGs(Ts) = Va
The beam current is absorbed by Tsand Rm. The voltage developed across Rm by this current is fed to the video processor in order to monitor the beam current.
11.1.2. Dynamic operation
The TEA51 01 A operates as a closed loop amplifier, with its voltage gain fixed by the resistors Rf and Re.
Since the open loop gain Ais not infinite, the resistor Rp and the input impedance Rin must be considered.Hence the voltage gain is
G = _Bf x
1
(2)
Re . 1
Rf
A 1 + (1 + Rp II Re II Rin)
-4/23- - - - - - - - - - - - ! f i ~i~@mg~~21;~ - - - - - - - - - - - - -
1038
APPLICATION NOTE
Figure 2.
c
~----------~~,----------------~----~~------~
9 feedback output
(:~)
voo
5~r-----~r-----~~~---------.
D5 ~~~~~71----,MA~-4
(:~)
R1 2.5K
input o---J\AAf\--l----0-----.!--t T1 350
R5
350 T2 R6
R4 3500
C 3pF R3 l.5K
11.1 .2.1. Input voltage Vin < Vrel (black picture)
In this case the current flowing in R7 and T1 decreases whilst the collector voltage of T4 and the output voltage both increase. In the extreme case, I(T1) = I(R7) = 0 and Va= VDD-VGs(T5)
In order to charge the tube capacitor the voltage is fed to the cathode output in two ways: · through the PMOS (with a VGS difference) for
the low frequency part · through the capacitor C for the high frequency
part (output signal leading edge) To correctly transmit the rising edge, the value of the capacitor C must be high compared to CL_
With the current values used (C = 1nF,CL = 10pF),
V90TEA51 01 A-02
the attenuation is very small (0;99)
11.1.2.2. Input voltage Vin > Vrel (white picture)
In this case,the current in R7 and T1increases with an accompanying drop of T4'S collector voltage until T1 and T4 are saturated. At this point:
= = Va Ve(T4) Vee
During a high to low transition (i.e. black-white picture), the beam current is absorbed in two ways: · through the capacitor C and the compound
PMOS T6-T7 for the high frequency part (faIling edge) · through the PMOS T8 and the resistor Rm for the low frequency part.
APPLICATION NOTE
11.2 BEAM CURRENT MONITORING
11.2.1. Stationary state
The beam current monitoring is performed by the PMOSTs and the resistor Rm. When measuring low currents (leakage, quasi cutoff),the Rm value is generally high. When measuring high currents (drive, average or peak beam current), Rm is generally bypassed by a lower impedance.
It should be noted that the current supplied by the three guns flows through this resistor.Hence,with too large a value for the resistor Rm,the cathode voltage of the tubes will become too high for the required operating current values.This is a fundamental difference between the TEA51 01 A and discrete video amps. In discrete video amps, the current monitoring transistor is a high voltage PNP bipolar which may saturate. In this case the beam current can flow through the transistor base and it is no longer monitored by the video processor. This
Figure 3.
effect does not occur with the TEA 51 01 A.
11.2.2. Transient phase: low current measurements
The cut-off adjustment sequence is generally as follows:
In a first step, the cathode is set to a high voltage (180V) in order to blank the CRT and to measure the leakage current. In a second step, the tube is slighly switched on to measure a very low current (quasi cut-off current). This operation is performed by setting the cathode voltage to about 150V and adjusting it until the proper current is obtained. The maximum time available to do this operation is generally about 5211S.
Fig.3 shows the simplified diagram of the TEA51 01 A output, the voltages during the different steps, and the stationary state the system must reach for correct adjustment.
/~~5V
Vc
~
/
I
180V I
,-------------------~;~19
C
Vc
lnF
181.5V
150V
1
r---l
R lKO
I
I
I
I
I
I
I
I
I
I
I
I
K I
I
I
*:CL: I
L. _ _ _ ..J
152.5V
181.5V
.. BLANKING
~~1 =RxC L= IOns
I {~2 =RxC = IJ.Ls
I
152.5V
:~
151.5V
CUTOFF
V90TEA5101 A-03
6-/-23--------------------------~~~~@~g~r~~~ ----------------~---------1040
APPLICATION NOTE
During the blanking phase, the tube is switched off, the PMOS is switched off and its VGS voltage is equal to the pinch-off voltage (about 1.5V). The voltages at the different nodes are shown in figure 3 (V(9) = 180V, V(k) = 181.5V). The falling edge of the cutoff pulse is instantaneously transmitted by the capacitor C. When the stationary state is reached, the cathode voltage will be 152.5V if the voltage on pin 9 is 150V, as the VGS voltage of the conducting PMOS is about 2.5V.
We can see that the voltage on C must increase by an amount of L'.Vc = 1V. This charge is furnished by the tube capacitor which is discharged by an amount of L'.VCL = 29V with a time constant equal to R x CL (10 ns). By considering the energy balance, we can calculate the maximum charge L'.Vmax that CL can furnished to C
L'.Vmax=-·I'VCCLXL'.VCL= 3V
Since this voltage is greater than L'.Vc, the capacitor C can be charged and the stationary state is
Figure 4.
reached without any contribution being required from the tube current,i.e. the whole tube current can flow through the PMOS and the adjustment can be performed correctly.
Considering higher voltage and beam current swings, the margin is greater because: · the voltage swing across the tube capacitor is ,
greater · the tube current is higher and the picture is not
disturbed even if part of the beam current is used to charge the capacitor C.
111- EXTERNAL COMPONENTS CALCULATION
The implementation of the TEA5101A in an application requires the determination of external component values. These components are Rf, Re, Rp
and Rm (see figA). The dissipated power in the Ie
and in the feedback resistor Rf must also be calculated in order to correctly choose the power ratings of the heatsink and resistors.
V1N(BLK)
j\{
,------------------7---,
1
1
41
1
19
+
t 1
1
1
1
17
f--I----I~
r'o'"
V
Video f-----' Proc
V90TEA5101A-04
--------------------------- ~~i~~~~~:~~~ --------------------------7-/2-3 1041
APPLICATION NOTE
111.1 COMPONENTS VALUE CALCULATION
From equations 1 and 2 in section 11-1, both the value of the DC output voltage and the voltage gain depend directly on the resistor RI. Hence RI must be determined first before calculating the value of Re and Rp in order to obtain the correct gain and DC output voltage.
R _
Vrel
p - VOU! (BLK) - Vrel Vin (BLK) - Vrel
RI
+
Re
- If Vin(BLK) = Vrel Rp =
Vrel
R
X I
yOU! (BLK) - Vrel
111.1.1. Feedback resistor RI
The value of RI must be as low as possible in order to obtain the optimum dynamic performance from the TEAS1 01A (see section IV-1). A typical value of RI is 39 k£1.
111.1.2. Input resistor Re
The voltage gain is calculated from the following formula (see section 11-1):
G=_Bt.
1
Re 1
RI
1+1\(1 +Rpl/Re l/ R)
For a 1S0V black level:
I Rp = 1k£1
with RI = 39k£1
*" - If Yin (BLK) Vrel :
Vin (BLK) =2.7V I Rp = 1.2k£1 I with RI = 39k£1
Re = 1.Sk£1 Or
Vin (BLK) = 6.7V I Rp = 680£1 I with RI= 39k£1
Re = 1.Sk£1 for a 150V black level
Since the open loop gain A is high enough (SOdB), we can approximate the calculation:
G@_Bt.
Re
where Re is generally implemented as a variable value for channel gain adjustment.
If the gain adjustment range Gmin, Gmax is known:
RI
RI
Re min = - G and Re max = -G.
max
min
With Gmin = 15 and Gmax =80 :
I Re min = 470fl
111.1.4. Cu rrent measurement resistor Rm
Rm must be determined by taking into account the quasi cutoff current leo and the input voltage Vc of the video processor.
,
Vc
Rm=-
leo
- With the videoprocessor TEAS031 D (Vc = 2V) : Rm = 120kQ with leo = 16J..lA
- With the videoprocessor TDA3S62A (Vc = O.SV) which requires a DC biased input "Black current stabilization" (pin 18), the schematic diagram is the following:
Figure 5.
Re will be made of a 2.2k£1 potentiometer and 470£1 fixed resistor.
111.1.3. Bias resistor Rp
Rp must be chosen in such a way that the black level output voltage VOUT(BLK) is equal to the cutoff voltage, which is a characteristic of the Wbe currentlyused, when the DC black level input voltage VIN(BLK) is the mean value of the adjustment range of the video processor. This is the optimum condition to ensure a correct adjustment during the lifetime of the tube. Rp can be calculated by considering the TEA51 01 A as an operational amplifier and applying the usual formula:
TDA3562A pin18
6 112V
120K \l
I C.o.
82KO
V90TEA5101 A-05
-- 8/23 ------------ ~ ~~~,;m~::~~©~ --------------
1042
APPLICATION NOTE
The DC bias is 12 x 12~! 82 = 5V
The quasi cutoff current is
a.5
( __1_ 1~
+
-~-)
~
x
1
x
10-3
=
10,uA
111.2 DISSIPATED POWER IN EXTERNAL COMPONENTS
The only components dissipating power are the TEA51 01 A and the feedback resistor. The dissipated power has a constant static component and a dynamic component which increases with frequency. The theoretical calculation is not sufficiently accurate to determine the correct dissipated power. The best way consists of measuring the power in different configurations of the circuit: steady state (no input), sinusoidal input,and in situ (in a TV set with a video input signal). The mea· surement method will be described first and then the results and calculations will be discussed.
111.2.1. Measurement method
The dissipated power can be determined by measuring the average supply current 100 (principally high voltage supply current Voo) and by subtracting the power dissipated in the external components from the calculated power delivered by this supply Voltage.
The power delivered by the high voltage power
supply is : P = Voo X 100
The power dissipated in the external components (principally the feedback resistor Rf) is:
.
3 x V2 OUT (AVG)
. for the static part: PSR =
Rf
.
for
the
. dynamic
part:
POR
=
~ 3 X-V2R OUTj(-RM-S-)
When the IC is driven by a sinusoidal signal (capacitive drive),the measurement and calculation are straightforward: VouT(AVG) = VouT(DC)
V M S ) _ VOUT (peak to peak)
oUT(R -
2 x -{2
With VOUT (DC) = 100V and
VOUT (peak to peak) = 1OOV and Rf = 39kQ
PSR = 0.8W POR = 0.1W
Measurements are more difficult to carry out when the IC is working in a TV set. VouT(AVG) can be measured with an oscilloscope (difference of level between AC and DC coupling) and VOUT (RMS) can be measured by connecting an RMS voltmeter to the feedback resistor. In this case we have the following results (see section 2.2.3):
VOUT (AVG) = 130V and PSR = 1.3W
VOUT (RMS) = 32V and POR = 80cnW
In each case, the term POR can be neglected as a reasonable approximation. Hence, the power dissipated by the IC will be:
Pi
= Voo
X
100·
3V2 OUT (AVG)
-------
Rf
and the power dissipated in Rf will be :
Pr = V2 OUT (AVG) Rf
111.2.2. Results
111.2.2.1. Static power
Table 2 shows the measured values of 100 and the calculated power for three values of Vout and for Voo = 200V
Table 2
~U(TV)
50
100
(rnA) e.-~-- -
16
Pi e.-. (W)
-~-----
3
P,
(W)
0.065
100
15
2.2
0.25
- - - -1-5_0. -
_ 14.6__ ~ 1.2
0.6
We can see that the static power dissipated in the IC decreases with VOUT increasing, but obviously the power dissipated by Rf increases as VOUT increases.
111.2.2.2. Measurement with sinusoidal input
Table 3 summarizes the results obtained from prac· tical measurements as functions of VouT(DC) and of the frequency (the three channels are driven simultaneously).
--------------
~
~~;~;m~:~~g~
9/23
---------------=-
1043
APPLICATION NOTE
Table 3.
VOUT (V)
(DO 1MHz (rnA)
(DO 7MHz (rnA)
VOUT (PP) 1MHz (V)
50
20.7
44.6
66
100
20
59.5
100
150
18
45
100
We can see that when driving the IC with a HF sinusoidal signal, care must be taken to avoid excessive temperature increase.
111.2.2.3. Measurement in a TV set We have determined the worst cases of dissipation in a TV set. These trials have been carried out on one particular TV set, and may not be representa-
Table 4.
VOUT(AVG) (V)
(DO (rnA)
Bright.max Noise Bright.min
148
22.2
188
23.3
. Bright.max Multiburst
131
23.6
Bright.min
158
22
VOUT (PP) 7MHz (V)
50
80
67
Pi 1MHz
(W)
3.9
3
1.7
Pi 7MHz
(W)
8.7
11
8.2
P, (W)
0.065 0.25 0.6
tive for all TV sets. In this particular TV set, the worst cases of dissipation occur with noise signal (from HF tuner) and with a multiburst pattem (0.8 to 4.8MHz) in RGB mode.
Table 4 summarizes the results in these two cases when the brightness control is set to min and max value (the contrast control is set to max).
VOO
Pi
P,
(V)
(W)
(W)
218
3.15
0.56
224
2.5
0.9
213
3.7
0.44
221
2.9
0.64
111.2.3. Design of heatsink and external components
111.2.3.1. Heatsink As discussed above, the power dissipated in the IC in a TV set can reach about 4W. In this case, a 12°C/Wheatsink seems to be sufficient. Such a
heatsink will give Ti = 115°C for Troom = 60°C.
The resulting margin guarantees correct reliability.
111.2.3.2. Feedback resistors 1 Watt type feedback resistors must be used, as they may need to dissipate 0.9W when the TV set is working and up to 1W when the TV is blanked
(VOUT = 200V), for example when the security of
the scanning processor is activated.
IV - APPLICATION HINTS
IV.1 DYNAMIC PERFORMANCES Figur~ 6 shows the simplified schematic diagram of the TEA5101A in AC mode.
Gf is the parasitic capacitor between the input and
the output.
Figure 6.
Cf
V90TEA51 01 A-OB
Cin is the parasitic capacitor between the input and ground. The voltage gain v'ersus frequency can be deduced from the formula (2) in chapter" section 1.2 :
G(s) = _
RI
X
1 .
Re (1 + RI GI s) 1 + _1_ (1 + ~ 1 + Reg Gin s)
A(~)
Req 1 + RI Gf' S
with Req=Rp-'/RellRin and A(s) open loop gain.
-10-/2-3-------~--------------~~ ~~~~~g~~~~~~ -----------------------------
1044
APPLICATION NOTE
A(s) is a second order function such as AO
1 + bs + as2
with a = 9 x 10-16 S2
b = 60 x 10-9 S
AO = 400
Assuming Req x Cin = Rf X Cf, we find:
G(s)~-
Rf
x -1 -x
1
Re (1 + Rf Cf s) 1 B 1 B b
B
2
+ AO + AO+B s+ AO+B as
with B = 1 +~ Req
We see that the closed loop amplifier is equivalent
to a combination of a second order circuit and a first
order one. The latter comprises the feedback resis-
tor and the parasitic capacitor between input and
output. With the current values
Rf = 39kQ
Re = 2kn
Cf = 0.5pF
Cin = 15pF
Rin = 14kQ
Rp = 1.2kQ
we have
Req x Cin = 10ns Rf x Cf = 20ns
B = 56 The second order circuit characteristics are: Natural frequency:
Fn = - -1 - x - AO+-B = 15MHz
2x7txa B
damping factor :
b
B
z = 2 x a x AO + B = 0.35
value of Cf is too low, the response curve will have a peak (due to the second order circuit). A "ringing" effect will be present on pulse-type signals and an instability and oscillation can occur at some frequencies.
This capacitor is generally too high. It consists of: o the self parasitic capacitor of the feedback
resistor .. the parasitic capacitor due to the PCB layout.
Practically,the best bandwidth performances are achieved by: .. the smallest input-output capacitor and
the smallest capacitor between an input and ground · using a feedback resistor with the smallest possible value but large enough to yield a sufficiently high gain. .. using a feedback resistor with small parasitic capacitance (typ 0.2pF). Some resistors have 0.5 or O.B pF parasitic capacitor.
The parasitic capacitors discussed above are usually the ones which need to be taken into account. However any other parasitic capacitor or inductor can modify the frequency response. For instance,a too large capacitor value between the feedback output and ground can create a dominant pole and cause a potential risk of oscillation.
IV.2 CROSSTALK Figure 7 shows the different parasitic links inducing crosstalk.
Figure 7.
The cut off frequency of. the first order circuit is :
fc =
1
= BMHz
2 x 7t Rf X Cf
The amplifier response is thus the combination of the responses of these two circuits. The contribution of the parasitic capacitor Cf to the frequency response is very important. If the value of Cf is too high, the contribution of the first order circuit will be of overriding importance and the resulting bandwidth of the amplifier will be too small. If the
The crosstalk can be caused by: .. parasitic coupling between the inputs (Cpi) · parasitic coupling between the outputs (Cpo) .. parasitic coupling between an output and a
near input of another channel (Cp).
11/23 1045
APPLICATION NOTE
Parasitic coupling may be capacitive or be caused by HF radiations.
The third type of parasitic coupling is predominant since it involves the addition by feedback at relatively high level(output) signals to relatively low level (input) signals. For example, a 0.1pF Cp parasitic capacitor between an output and the input of another channel will act as a differenciator with the
feedback resistor Rf = 39KO.
The transfer function of this integrator will be RI x
Cp X S (0.2j at BMHz) and thus the crosstalk will be -14dB .at BMHz. The .parasitic coupling between inputs and outputs must be minimized to achieve an acceptable crosstalk (-20dB at SMHz). This can be done by crossing only the input wires and separating the input and output leads. High voltage components and wires must be laid out as far as possible from small signal wires,even if this results in a larger circuit board.
HF radiations from the feedback resistor must not induced a voltage signal at the input of another channel. This can be achieved by: · spacing out the feed back resistors · mounting these resistors in the same direction
and strictly aligned one under another. · mounting these resistors 1cm above the PC
board · using ground connections to insulate the input
wires
IV.3 FLASHOVER PROTECTION
A picture tube has generally several high voltage discharges in its lifetime. This is due to the fact that the vacuum is not perfect coupled with the presence of metallic particles evaporated from the electrodes.Hence, short circuits (very brief fortunately) can occur between two electrodes,one of which is usually the anode (at EHT potential). An overvoltage can be induced on the cathodes or on the supplies even if a flash occurs on an electrode other than a cathode, because of the possibility of flashes in series or overvoltages due to inductive links on the video board or on the chassis. these overvoltages can destroy an IC particularly the video amplifier which is the most vulnerable since it is directly connected to the tube.
The tube manufacturers have made much progress in technology in order to reduce the frequency of flashes and their associated energy (increased quality of vacuum, internal resistance for "soft
flash" tubes). Nevertheless, some protection measures are suggested by the tube manufacturers: .. connect spark gaps on each electrode
(1 to 3kV or 12kV for focus) .. connect the spark gaps to a separated ground
directly connected to the chassis ground by a non inductive link " connect the cathodes or grids by protective resistors. These resistors must be able to withstand 12kV (20kV for focus)instantaneous voltages without breakdown and without any change of value following successive flashes. These resistors must be of a non-capacitive type. 1/2W (1W for focus) hot molded carbon type resistors are well suited for this application. o the grid and cathode connections on the PC board must be as short as possible and spaced well away from other connections in order to avoid parasitic inductions.
Furthermore, the TEAS1 01 A has been provided with an additional effective feature to improve the flashover protection.As described in section 1-4, a protection device has been included comprising a high voltage high current diode which is connected between each output and the high voltage power supply. The equivalent diagram of this protection is shown in Figure B.
Figure B.
V90TEA5101 A-DB
The flash current is diverted to the ground through the diode and the decoupling capacitor C. Two kinds of flashes can occur: 1) low resistance flashes during which the spark gaps are activated since the cathode voltage exceeds the breakdown value of the spark gap. In this case the equivalent diagram is the following:
- - 12/23 - - - - - - - - - - - - ~ ~~;~,[0mg~l~g~ - - - - - - - - - - - - - -
1046
APPLICATION NOTE
Figure 9.
It flash current (oo 1000A)
Lf inductance of the connection (oo 10!lH)
V90TEA5101A-09
Ctube previously charged to 28kV is instantaneously discharged during
~t = Ctube x ~IVt = 30ns
Since the voltage across the spark gap falls almost instantaneously to 2000V, the peak current I flowing into the diode is (assuming Vc is held by good decoupling) :
1= Ve x ~ t = 6A
Lf
To ensure a variation of Vc less than 10V, C must be
C >I X-~-t
~Vc
eg
C> 18nF
The decoupling must have good HF characteristics.
2) high resistance flashes in which the spark gaps are not activated. In this case the equivalent diagram is the following:
Figure 10.
r I Ctube
L1j'V . hF
Rt~ ~_~ID5
I
I
I
I I
\.J. 7
IL_II-_JI
vet C
V90TEA5101A-l0
= 2000
If V < 2 kV, I < -R- , I < 2A and Rt 12kQ
The time constant of the flash is Rt x Ctube = 12 !ls,
the decay time is approximatevely 30 !ls. The value of C must be
C >~t-x-l
~Vc
eg
C > 6!lF
in order to ensure a VC variation less than 10V.
The total decoupling will be made up by a 10!lF electrolytic capacitor connected in parallel with a 22nF plastic film capacitor with good HF properties.
It must be placed very close to the TEA5101 A to be efficient. Otherwise, the equivalent diagram will be the following (case of low resistance flash).
Figure 11.
Ctube
V90TEA5101A-ll
~Vc = I x ~ t + Lpl X I
C
~t
~Vt = 210V with LPl = 1 !lH and Lp2 = 0
In this case the VDD voltage can rise to a dangerous value (+210V increase) and the protection is not efficient.
If the connection between the socket ground and
*" the chassis ground is inductive (Lp2 0), the effect
is the same.
However in this case, all the TV IC's,and not only the TEA51 01A,will be exposed to destructive overVoltages.
IV.4 OUTPUT SWING The simplified diagram of this function is shown below (See Chapter II and chapter III ):
- - - - - - - - - - - - - - ~ ~~~Q.jn'~!:1~~l'! - - - - - - - - - - - - - - 13/23
1047
APPLICATION NOTE
Figure 12.
~~t:.······. C 1-1 I
TEA5101A
CRT
V90TEA5101A·12
The current delivered by a CRT is given by the characteristic curves (fig 13-14).
Figure 13.
,---------------~
HEATER VOLTAGE - 6.3V ANODE-TO-GRID No.1 VOLTAGE-
25kV GRID No. J-TO-GRID No.1 VOLTAGE
(EACH GUN) ADJUSTED TO PROVIDE SPOT CUTOFF.
The minimum value of Vk (due to all the voltage drops in the resistors and in the amplifier) is given by the equation (see fig 12 above):
Vk = (R + Ron + R1 + 3 X Rm) X It = Req X It (1)
with Ron: on state PMOS resistance
To find the maximum available current Itmax,we can draw the curves of the equation (1) on the tube characteristics. Itmax will be given by the intersection point of the curves.Since the tube characteristics are: It Vs Vcutoff + VG1- Vk the equation (1) must be changed to
It = VCUTOFF + VG1 - Vk
Req
(2)
Assuming VG1= 0, we can draw the curves of equation (2) for several.values of Vcutoff (eg 150V and 200V) and several values of Req (eg 5k,10k,15k,20k) (see fig 13 and 14). We can see from these. curves that Req must have the following values to allow the tube to source 4mA per gun:
Figure,-1-4-. -------------HEATER VOLTAGE - 6.3V ANDOE-TO-GRIO No, 1 YDLTAGE2SkY GRID No. 3- TO-GRID No. 1 VOLTAGE (EACH GUN) ADJUSTED TO PROVIDE SPOT CUTOFF.
200
400 600
VIDEO SIGNAL VOLTAGE PER GUN - V := Ycutoff - VG\~
V90TEA5101A-13
10
20
40 60 80 100
'DO
400 600
VIDEO SIGNAL VOLTAGE PER GUN - V = Vcutoff - YG,.
V90TEA5101A-14
-14-/2-3---------------------------~ ~~~@~~~~~~~ ------------------------------
1048
APPLICATION NOTE
Req ~ 5kQ or Req ~ 15k£!
for a 150V cutoff point for a 200V cutoff point
As Ron value is approximatively 1.7kQ, the measurement resistor must be as low as possible.
Working with higher cutoff point would be an alternative solution. But a 200V cutoff point seems to be too high a value since in this case the supply voltage would be greater than 200V and would affect reliability performances.
Another solution consists of connecting a zener diode as shown in Figure 15. With this device the high current operation of the TEA51 01 A is similar to that of a discrete amplifier (with PNP) operation.
Figure 15.
V90TEA51 01 A-15
For low currents, if the zener voltage is greater than the VGS voltage, the zener diode is biased off and the beam current flows through the measurement resistor. When the cathode voltage (pin 7) drop is limited because of the pin 6 voltage and when the pin 9 voltage continues to decrease,the zener diode is switched on when V7 - V9 = Vz. In this case the beam current is absorbed by the voltage amplifier and the tube can provide larger current values.Nevertheless, the pin 7 output voltage will follow the pin 9 voltage with a Vz difference.
Since the pin 9 voltage is internally limited to 14V, the output voltage will be limited to 22V with a 8V zener diode.
The CRT bias voltages shown on the previous curves are referenced to the G1 Voltage. The TEA51 01 A is referenced to ground. We can choose to work with a G1 voltage greater than ground and thus the low level saturation is not taken into account. In this case, the cutoff points must be in-
creased. When choosing VG1 = 12V, the cutoff
points will be adjusted to 170V (instead of 150V).
Since the power supply is 200V, 30V are available to ensure correct blanking operation. The DC output voltage must be increased by 12V from its previous value.
Note that all the phenomena described in this section concern a static or quasi-static (15kHz) operation (e.g. white picture or rather large white pattern on a black background). When current peaks occur (e.g white characters insertion or straight luminance transition), the peaks will be absorbed by the coupling capacitor and the voltage amplifier,and hence the tube will be able to source a greater current.
IV.S LOW CURRENT MEASUREMENTS
We have seen in section 11-2.2 how the beam current monitoring works (see fig.3 page 6). We have seen that the capacitor C must charge again after the blanking phase.
This charge is generally furnished by the tube capacitor independently from the beam current. However,if during the blanking phase, the output voltage is too low (e.g. the PMOS is reverse biased (- 20V) because of a too high leakage current or when measuring with an oscilloscope probe), the f..VC required to charge C again will be greater than the maximum charge available from the tube capacitor. Hence the beam current will have to charge C in a first step.
Since this current is rather low during the cutoff adjustement phase, a long time will be spent to charge C. The current absorbed by the PMOS and fed to the videoprocessor will not be equal to the beam cu rrent and the cutoff adjustement will not be correct.
Hence the reverse voltage across the capacitor C must be limited by a diode connected as follows:
Figure 16.
1 -------i:t-----
r
IN11~8
j-- --I .----
L-- ::=J---~
9
Jf---
[XJ6
V90TEA51 01 A-16
- - - - - - - - - - - - - - ~ ~~~(c]t~,g~~g~ - - - - - - - - - - - - - - 15/23
1049
APPLICATION NOTE
With this configuration, the voltage across C will be -0.6V max. Since this voltage must be 2.5V in the stationary state (see section 11-2.2), the voltage across C must be increased by 3.1 V and this charge can be supplied by CL. We can also slightly decrease the value of C. However if C is too low, the HF behaviour will be impaired.
v -APPLICATION EXAMPLES
V.1 APPLICATION DESCRIPTION
Figures 17 and 18 show two applications, one for a 45AX tube and the video processor TDA3562A (application 1), the other designed for S4 type tube and the video processor TEA5031 D (application 2). In these. two applications, the nominal gain is 28dB and the output black level is 150V. The quasi cutoff currents are respectively 1OIlA and 161lA for applications 1 and 2.
These applications are implemented using the same PC board especially designed to allow different options for tube biasing, power supply decoupiing and connections. This PC board allows also two different tube sockets (jedec B8274 or Bl 0277) to be connected. Both beam current monitoring modes (sequential and parallel) are possible.
The layout and the electrical diagram of the PC board are shown in Figu res 19 and 20.
V.2 PERFORMANCE EVALUATION
As seen in chapter IV, the dynamic performances (bandwidth, crosstalk) of the TEA5101A is very dependent on the PCB layout.Consequently, the evaluation board has been designed to obtain the best results.
To evaluate the performance, the best way is to work outside of the TV set by driving the amplifier by an HF generator (or a network analyser) while simulating the load conditions fixed by the CRT, since AC performances are directly determined by the load.
V.2.1. Measurement conditions
The schematic diagrams of the AC measurements are shown in Figures 21 and 22. The conditions are as follows:
· BIASING: VOUTDc= 100V by choosing R11 = R21 = R31 = 1.5kn and Voo = 200V
· AC GAIN = 50 by adjusting P1 0, P20, P30 · LOADING:
- by a 8.2pF capacitor and the probe capacitor (2pF), the sum is equivalent to the capacitance of a CRT with the socket and the spark gaps - the 1Mn resistors connected between each output and Voo allow the conduction of the beam current monitoring PMOS transistor in such a way that VAoc = VBoc= 100V. · DRIVING by a l!1F capacitor, the HF generator being loaded by 50n. · the dynamic power dissipated in the IC will increase with frequency. To avoid the temperature increasing, it is necessary to do very quick measurements or to use a low Rth (7°CIW) heatsink in forced convection configuration. Such conditions are not present in a TV set since the driving signal will be a video signal instead of a pure HF signal.
V.2.2. Results
V.2.2.l. Bandwidth
The curves Figures 23 and 24 show the frequency responses of one channel with 1OOVpp and 50Vpp output Voltages.
The bandwidths are approximatively 8MHz at 1OOVpp and up to 1OMHz at 50Vpp.
V.2.2.2. Crosstalk
The curves Figures 25, 26 and 27 show the crosstalk for this application.The crosstalk is almost the same for the six different combinations of the three channels. The worst value is -24dB at 5MHz.
V.2.2.3. Transition times
The curves Figure 28 show respectively the R, G, B rise and fall times of respectively 49 ns and 48 ns with a 1OOVpp output voltage (between 50 and l50V).
The difference between rise times of the three channels is less than 1ns..
The difference between fall times of the three channels is less than 2ns.
The delay time at rising output is 48ns.
The delay time at falling output is 50ns.
The difference between the delay times is less than 2ns .
The slew ra'te is about 2000VIIlS.
- - 16/23 - - - - - - - - - - - - ~ ~~~~;m~~~gL~ - - - - - - - - - - - - - -
1050
Figure 17 : Application 1 (45AX Tube, TDA3562A) - Electrical Diagram.
APPLICATION NOTE
PIO
Rin --iZJ
AI3 A cathode
Gin
o G cathode
Bin
A33 lkU1I2W
B cathode
---r:---CJ---<J VDD
.
47n
200V
C2
Cl
01,
250V
_ CHASSIS~ ___________________+-______~____~__~______~
GROUND
CRT GROUND
1----- ---- _. ------~~
~
~
liD LOW LEVEL CONNECTOR C\
<l
110 HIGH LEVEL CONNECTOR C2
o~-------------<~
HEATER
O-~-~---<l
o
CRT CONNECTOR
) ( PIN CONNECTION
L~_~_______~._____~ _ _ _ _ _ ~~ _ _
10kUl12W
G2 o~D---l~-X
I,F
~ 630V
V90TEA5101 A-17
~ ~~~u~~~~£t~ ~~~----------------------1-7-/2-3 1051
APPLICATION NOTE Figure 18 : Application 2 (PIL24 Tube, TEA5031 D) - Electrical Diagram.
R13
Rin
R cathode
R,5 1QOkn
Rcutoff
Gin
-0 G cathode
G cutoff
120kn
Bin
B cathode
-~-----~ B cutoff
R35 120kn
VDD 200V
_ CHASStS~ _ _ _ _ _ _ _ _ _~_ _ _- 4_ _~_ _~_ _~ GROUND
CRT GROUND
O~------------~~
HEATER
~
va LOW LEVEL CONNECTOR C1
0:
<l
1/0 HIGH LEVEL CONNECTOR C2
0
CRT CONNECTOR
) ( PIN CONNECTION
---------
1 Okll112W
G2 o-CJ'---t-I-~
I ~~~~nF
.I.
V90TEA5101A-18
- - 18/23 - - - - - - - - - - - - - ~ ~ii©m~~~~~
1052
Figure 19 : TEA51 01 A Evaluation Board Layout and Components View.
+
G2 VDD
--@D-
+ I II I 2211/630 22n/630
HEATER HEATER
-CJ-lOOK
+
--Q:K:J-
1/2W
~
\!5
o'"
APPLICATION NOTE +
+ +
-=-, 20K
-=-120K
G INPUT 12V
B INPUT
GND R INPUT R CUTOFF B CUTOFF
G CUTOFF
+
COMPONENT SIDE
V90TEA5101-19A
COPPER SIDE
V90TEA5101-19B
1053
APPLICATION NOTE
Figure 20 : TEAS-1 01 A Evaluation Board Electrical Schematic Diagram_
' 1 ~-=--= ~ ~~-~-:t---
Pl0 Rl0
Rin
voo
L t = Cl0 1nF R13 lkHl/2W
-----:J----D R cathode
R14
R cutoff
P20
Gin
o G cathode
P30 2.2kn
Bin ------¢-
8 cathode B cutoff
110 LOW LEVEL CONNECTOR C 1
<J
110 HIGH LEVEL CONNECTOR C2
o
CRT CONNECTOR
PIN CONNECTION
O.lfJF 250V
VDD 200V
l G1O-----
CRT GROUND
O>-------~~
HEATER
o---~ Rl 100kn -l
10kn 1/2W·
G20-0-1~-X
. I ~~~enF
.l
V90TEA51 01 A-20
--- 20/23 --------------- ~ ~iii(rnm2"~~~~~ -----------------
1054
APPLICATION NOTE
Figure 21 : Bandwith Measurement Configuration.
P1Q
I j -. '-- - - - _ .._-_.
["]R3192kl.l .
[ VDD
2.2kU
RIO
--- lW
-
--V-B-i :- .-. --. cij-5---I~ ---.
Rll
I
1
-t l'. I 15k!)
VREF
4.7'"
J/W J/w
1voo
.. ;-LJ-T t rJ1M!!
T 1 ~\~l l;2W
100llF
8~2i
/;)3
I
,»"
PASSIVE PROBE
J_~_--·20,dB
ATTENUATOR
-rr'-"'-' ACTIVE I PROBE I I -40dB
CL 2P
HP 3577 NETWORK ANALYSER
- 20dB
.~.[-=r--~.-
Figure 22 : Crosstalk Measurement Configuration.
V90TEA51 01 A-21
PlO
=f" - ~jr---w 2.2kU
RIO
11.1~390U
--c-----j
t7k!!
/,/L 8P2
/7/w
.
ACTIVE
is -J-----------~;;;"':l". __..J:~r
HP 3577 N!TWORK R [ - - - - - - -
ANALYSER
Ar---~~--------------------------l
ACTIVE PROBE - 40dB
_-==j- ---- - --
1VDD
P20
JJ r[_ t~FBV-DilJ:DJ----;--1--C--J-r . i--(,LJ---C ~1\JF
I2._2k/'u~
R20 3fl.9Jl
39kll 1W
~~
I~,~~u ~ /I
VREF
_ -- ·. -- ·. ' 47k!l
I _ C20 1I1 I 1nF R23
J" III.\! 112W I
IMU 100nF
li "If
8P2
~w1
V90TEA51 01A-22
- - - - - - - - - - - - - - - ~ ~~~~m~~~g~
21/23
1055
APPLICATION NOTE
Figure 23 : Frequency Response of R Channel
(100Vpp).
REF LEVEL I DIV
400QOd6
(,.000,1"
OFFSET 792523090QHz HAG (UDF) -2 912d~1
Figure 24 : Frequency Response of R Channel
.
(50Vpp).
REF LEVEL J DIV
40 GCOdB
50QOdB
QCFsn, ", '" 00"'
1"-
\
\
\
\
\
\
V90TEA51 0 1A·23
Figure 25 : Crosstalk between R Channel and G
and BOnes.
REF LEVEL I DIV
"OOOOdB
lDOOOd8
ns MARrEn 4 401 ~OOHz
NAG (UDF) 23C61 B
V90TEA5101A·24
Figure 26 : Crosstalk between G Channel and R and BOnes.
REF LEVEL I OIV
20000dB
10000dB
., t1ARKER 4922422CQQHz
MAG (UOF) ~4 384dB
-----~ --
100kHz
-
.d
~
---;:; ?
V
~ -""
V
/""
V90TEA5101 A·25
Figure 27 : Crosstalk between B Channel and R
and G Ones.
20000dB
IOOOOdB
MARKER 4983401 500Hz MAG IUDF) ·,80 144d8
V90TEA5101A·26
- ..
""r------
~
Y
b .-----/
V90TEA5101A·27
2-2-/2-3---------------------------~ ~~~~Di~~:~~ 1056
APPLICATION NOTE
Figures 28A and 288 : TEA51 01 A R Channel Step Response. TRIB: RISE 1FALL TIME 0.49.6ns
,
~·.:,.l":!.l,~.':~.':t,!'.:·~.:.j, ~.'.t".:.;~~EEEE "·. , .,..:·'.'..:.·.........L. . L..J..-. L.. . !!! i ,
= :!='<~= ;= 4= 1=:·=·: =: 41F: =: =: =jF:=··.=:=lF~.=·=·=1r~=.· =.~=Iit_ -:~:.: :, ':::,
TRIB:RISE/FALL TIME 048.4ns
V90TEA5101A·28A
TRIB: 020U :20ns TR3B: 0.50U :200s
V90TEA5101A·288
~~~~©~g~:~~~ ---------------------------2-3/-2-3
1057
APPLICATION NOTE
TV EAST/WEST CORRECTION CIRCUITS
SUMMARY
Page
GENERAL PRINCIPLES
2
1.1
INTRODUCTION ...................................................... . 2
1.2
DIODE MODULATOR PRINCIPLE ................................ , ... " .. . 3
1.3
PULSE-WIDTH MODULATOR PRINCIPLE ................................. . 6
1.4
GENERAL CONSIDERATIONS TO GENERATE THE CORRECTION PARABOLA .. . 8
1.5
1.5.1 1.5.2 1.5.3
ADJUSTMENTS ...................................................... . 10
Horizontal size adjustment .............................................. . 10 Pin cushion correction adjustment ......................................... . 10 Trapezium correction adjustment (keystone correction) ........................ . 11
1.6
PRODUCTS PRESENTATION ........................................... . 12
II
TEA2031A GENERAL DESCRIPTION .................................... . 12
11.1
INTRODUCTION ...................................................... . 12
11.2
PARABOLA GENERATION ............................................. . 13
11.2.1 Multiplier stage operation ............................................... . 13 11.2.1.a Operation without keystone correction ................................... . 14 11.2.1.b Operation with keystone correction ...................................... . 14 11.2.1.c Example of applications ............................................ , .. 15
11.3
LINE SAWTOOTH GENERATION ........................................ . 16
11.3.1 11.3.2
Role of resistors R7, R8, RT1 and D2 ...................................... . 16 Role of diode D1 and capacitor C3 ........................................ . 17
11.4
OUTPUT STAGE ..................................................... . 18
11.4.1 Operation of the output stage ............................................ . 19 11.4.1.a Output in the low stage ............................................... . 19 11.4.1.b Output in the high stage .............................................. . 19 11.4.1.c Output with commutation .............................................. . 20 11.4.1.d Conclusion ......................................................... . 20
11.4.2 Operation in association with the diode modulator ............................ . 21
11.5
11.5.1 11.5.2
SELECTION OF THE VALUES OF CAPACITORS C2 AND C3 .................. . 22
Selection of C3 ....................................................... . 22
Selection of C2 ....................................................... . 22
11.6
APPLICATION EXAMPLE ............................................... . 22
III
TDA4950 - TDA8145 GENERAL DESCRIPTION ............................ . 23
111.1
INTRODUCTION ...................................................... . 23
111.2
DESCRIPTION ....................................................... . 24
111.3
APPLICATION
27
AN393/0691
1/35
1059
APPLICATION NOTE
SUMMARY (continued)
Page
IV
TDA8146 GENERAL DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 28
IV.1
INTRODUCTION.. . . .... .. .. .. . ... .. .. .. . . . . . . ... .. . . .. . . ... .. . .. . .. ... 28
IV.2
INPUT AMPLIFIER AND RECTIFIER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 29
IV.3 VERTICAL CLAMPING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
IVA REFERENCE AND STARTING CIRCUIT. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . 30
IV.5 PARABOLA GENERATOR . .. . ... .. . ... .. . ... ... . . .. . . ..... . . .. ... .. . . ... 31
IV.6
PULSE-WIDTH MODULATOR AND OUTPUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
IV.? APPLICATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
V
TDA8147 GENERAL DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 34
V.1
INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 34
V.2
INPUT AMPLIFIER .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 34
V.3
VOLTAGE REFERENCE AND STARTING CIRCUIT.. .. . . . . . .. . .. . .. ... ... . . .. 35
VA
PWM MODULATOR AND OUTPUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
V.5
APPLICATION.. . . . ... . ... .. . ..... . . .. .. . . . . . ... . . .. ... .. . .. ... .. .. .. . 35
I - TV EAST/WEST CORRECTION GENERAL PRINCIPLES
1.1 -INTRODUCTION
All color picture tubes which are used in the present TV-sets have a magnetic deflection system. Using a homogenous magnetic field, we have generally a pillow-distortion of a rectangular picture on the screen. This is mainly due to the tangens relation between the deflection angle and the beam position on the screen
Using a well dimensioned and optimized inhomogenous magnetic deflection field, this distortion can be eliminated completely for picture tubes with a deflection angle of 90°. In the same way the pillow-distortion of 110° deflection tubes can be eliminated in the vertical direction (North-South direction). But until now the distortion in the horizontal direction (East-West direction) can not eliminated with special designed deflection yokes. A distortion remains in Figure 1.
Figure 1 : Test Grid on a 110° Color Tube
\ \
I ( /
\
/
J
J )
\
\\ \
V91E·W·01
In order to compensate this effect, the horizontal deflection current in the yoke must be modulated. This means a large amplitude of the deflection current in the middle of the screen and a small amplitude on the top and the bottom of the screen. The general behaviour of the deflection currents is illustrated in Figure 2.
--------------------------- 2~/3~5-----------------------~~i~~~~::~~~
1060
Figure 2: Horizontal and Vertical Yoke Current (TH = 64!!s, Tv = 20ms)
I YOKE horizontal
APPLICATION NOTE
I YOKE vertical
V91E-W-02
In this picture Tv and TH are the time periods for the vertical and the horizontal deflection. Note that the envelope of the horizontal yoke current must be a parabola with the same phase as the vertical saw-tooth current. This means an East/West correction can be reached by modulating the horizontal yoke current with a parabola.
There are different possibilities to modulate the
yoke current. The most convenient modulator is the so-called Diode Modulator described in the next chapter.
1.2 - DIODE MODULATOR PRINCIPLE Let us consider the basic circuit of the horizontal deflection unit as shown in Figure 3.
Figure 3 : Basic Circuit of the Horizontal Deflection Power Stage including Modulator
Line transformer
Ly: line yoke LM : modulator coil VM : modulator voltage Vo : supply voltage Sl and S2 : electronic switches
V91E-W-03
---------------------------- ~~~~@~~~~~~~~ -------------------------3-/-35-
1061
APPLICATION NOTE
For the sake of simplicity, the electronic switches (diodes and transistors) are drawn as simple switches S1 and S2. The deflection time TH of 64f..ls can be divided in two parts: the scan time Ts at which the electronic switches S1 and S2 are closed and the flyback time TF (S1 and S2 opened). The total time period is the
TH=TF+Ts (1.1)
We assume now that the line transformer LTR have a neglectable high inductance and the time behaviour is mainly determined by Ly, LM, Cy, CM. Small modifications are necessary to consider also the electrical characteristics of LTR, but they should not be discussed here.
During the scan time the inductors Ly and LM are directly connected to the voltage sources Vo and VM:
VLY = Va - VM } S1 and S2 closed
VLM = VM
(scan time)
(1.2) (1.3)
Neglecting any power consumption in possible series resistors, the current in the two inductors increases linear in time:
· t (Vo - VM) ILY = Ly
(1.4)
iLM = t ~MM
(1.5)
Since the current iLY and iLM must be zero-symmetrical (average value = 0), the peak value of iLY and iLM is obtained after half of the scan time Ts/2
· Ts (Vo - VM) ILY = 2 Ly
(1.6)
· Ts VM ILM= 2LM
(1.7)
After this time, S1 and S2 are opened and the energy in the inductors Ly and LM changes to the capacitors Cy and CM. We assume now the same resonance frequency for both LC parts
LyCy= LM CM = L C (1.8)
Under this condition, both capacitors Cy and CM have its peak voltage at the half of the flyback time TF/2. The energy in the inductors stored at the end of th,e scan pe riod
EL = ~ L (id is then (1.9)
completely transformed into the capacitor
c Ec =21 (Vc)2 (1.10)
Under this condition, we obtain the general equa-
tion for the peak voltage in the middle of the flyback
period
-1f 'Vc = - IL + Vinit (1.11)
This voltage is the addition of the initial voltage and the voltage increase due to the energy transfer. With (1.6) and (1.11) we get
2 II.
II.
VO-VM Ts
VLY = VCY = - -VLy Cy + (Va - VM)
Ts = (Vo - VM) (1 - 2-VCC) (1.12)
in the same way (1.7 and 1.11) we obtain
II.
II.
Ts
VLM = VCM = VM (1 - 2-VCC) (1.13)
The resulting peak voltage during the flyback time at the line transformer is then
II.
II. II.
Ts
VLTR = - VLY - VLM = Vo (2-VCC- 1) (1.14)
Please lAote that in this circuit, the horizontal flyback voltage VLTR (1.14) is independent from the modulation voltage VM, though the yoke current ILY can be changed via the modulator voltage VM (see 1.6)
An overview of the currents and voltages is given in Figure 4.
4~/3~5-----------------------~~~i@~~m~g~ ---------------------------
1062
Figure 4 : Currents and Voltages of the Basic Circuit
APPLICATION NOTE
Vo(
,T ~
/
-1)
2 v LC
independent from V M r-~--~------------------------+---I------.. t
V91E-W-04
For a practical application, a large capacitor Cs can be inserted in series to the yoke to get an S-correction of the deflection current ILY. Simultaneously, the voltage VM can be grouded to have a simpler
handling of the modulator driver. The switch S1 is a standard high voltage power transistor (e.g. BU508A or S2000AFI), the switch S2 can be replaced by 2 diodes as shown in Figure 5.
Figure 5 : Standard Diode Modulator with Class-A Modulator Driver
Line transformer
:e, ~'21'" S sic
,j _~c~~s1
e.g. BU508A or S2000AFI
,j
CM\;r' r ?~ :-..."''"
1M
( jVM) -
~
V91E-W-05
------------------------------ ~ ~ii~~~~~~~~ ----------------------------5/-3-5
1063
APPLICATION NOTE
Normally, the current 1M into the modulator voltage source is positive and VM must only be realized as a variable resistor (e.g. transistor TM).
Many manufacturers use this simple diode modulator with such active load. A disadvantage of this application is the power consumption in the power transistor TM (-2W). Under ideal conditions, VM should have no power consumption (average
iM = 0), but in practice the coils and the line transformer are not free from parasitic resistors. Furthermore a reasonably large power is used from the various loads on the line transformer.
An improvement from the power consumption point of view is the use of a switched power stage VM. For this purpose, an additional inductance Ls (5 ... 20mH) is used and connected as shown in Figure 6.
Figure 6 : Standard Diode Modulator with Class 0 Modulator Driver (pulse-width modulator)
Line transf,::o,-,rm,--e:.:.r_~..-_ _ _~_ _ _~
]
Point A is biased from a pulse-width modulated rectangular wave. The frequency is arbitrary, for a simple pulse-width modulator, The horizontal line frequency is used normally.
Figure 7 : Pulse-Width Modulator
V91E·W·06
1.3 - PULSE·WIDTH MODULATOR PRINCIPLE The pulse-width modulator for driving the diode modulator contains mainly one power comparator with the external circuitry shown in Figure 7.
1 . · IYOKE
verticalL\
A
~
·
\. t
vpar 0--1
+ - } - - < f - - - - -
to diode modulator
VOUT
flyback pulses from the line transformer
V91E-W-07
6=/=35~-------------~~i~~~g~:R~~ ---------------
1064
APPLICATION NOTE
The working frequency is determined by the linear saw-tooth voltage biasing the positive comparator input. It is generated by the flyback pulses of the line transformer. The current sink on the positive input discharges the capacitor Cs during the scan time Ts and yields the negative slope of the sawtooth voltage. The negative input is biased from a parabola voltage, its generation is discussed later.
To improve the performance of this pulse-width modulator, a feedback path RK is provided compensating variations in the power supply Vcc of the comparator. The capacitor CK together with Rin and RK serves as a low-pass filter to suppress the line frequency coming from the comparator output.
If the current Is in the inductor Ls (see Figures 6 and 7) is only positive, the output stage can have a simple darlington transistor and a diode as seen in Figure 8.
Figure 8 : Comparator Output Stage, only positive modulator current Is is allowed
If the darlington stage is switched on, the current Is is flowing through TA and TB into ground. Otherwise, the diode D is conducting and Is flows into the supply voltage. The power, consumed normally in LM (see Figure 5) is then redelivered into this supply voltage. A greater flexibility in the design of the diode modulator can be reached, if the current Is is allowed to have negative values. For this case, the comparator power stage must be realized as push-pull stage (see Figure 9).
Figure 9 : Comparator Output Push-pull Stage, negative and positive modulator current Is allowed
1
OUT
(YYY\- __ 10 diode
Ls
modulator
V91E-W-08
V91E-W-09
Due to the voltage drop across the transistors and diodes, the transition from positive values Is and negative values Is yields a voltage step on the output as illustrated in Figure 10.
Figure 10: Voltage on the comparator output by zero crossing of Is
VOUT
vee
V91E-W-10
- - - - - - - - - - - - - - ~ ~~~;~~I~~~ - - - - - - - - - - - - - -7/35
1065
APPLICATION NOTE
In this case the steps in the output voltage produce an additional· undesired modulation of the yoke current. Then you can see some irregularities in the vertical lines of the test grid on the screen. With the aid of a reasonable large fedback factor (small RK, small Cs, large parabola amplitude) this effect becomes neglectable.
1.4 - GENERAL CONSIDERATIONS TO GENERATE THE CORRECTION PARABOLA
The correction parabola which drives the pulsewidth modulator (Figure 7) must have the same frequency and phase as the vertical deflection current in the yoke. Therefore, the parabola can be generated directly from the vertical saw-tooth signal which drives the deflection output stage. Principally there are two different kinds for generating the parabola:
a) integrator-network (linear)
b) functional-network (non linear)
Let us consider first the integration method: The vertical saw-tooth signal can be described with the following simple equation, valid for one period
t Ssaw-tooth(t)=A Tv
O<t<Tv
(1.15)
where A is the amplitude, Tv the time period and t the time.
Integrating this signal we get
I It t
t
A 2
Ssaw'-tooth (t)dt =
0,
0 A -Tv dt = 2 Tv t
(1.16)
Since the relation between the current and the
voltage on a capacitor is given by
I Vc (t) = ic (t) dt (1.17)
the parabola can be obtained directly from the coupling capacitor Cy in the vertical output stage as illustrated in Figure 11.
Figure 11 : Vertical Output Stage and Corresponding Voltages
~;
+ . Vertical Yoke(
v c ·'! . .: l i .C = :··.··!' t
DC-fee~
· v 4 t h AC j,""~ok ~ CY
,, ..
: : ·
·
VRYj1 jv RY
Ry
. .
: : ·
·
..
,"
Due to the aging and the temperature dependence of this (electrolytic) capacitor Cy, some manufacturers prefer to generate the parabola from the voltage drop across Ry (VRY) with the aid of a separate integrator. Due to the small amount of active and passive components, this integration method is the usual method to realize the East/West correction circuit with discrete elements.
The functional network realization requires a quite larger amount of active components and is therefore especially suited for integrated circuits. The input signal for this kind of parabola generation is
~,
V91E-W-11
also the vertical saw-tooth signal corresponding to (1.15). With the aid of a functional (square) network, the square of this signal can be formed according tothe following equation:
Sparabola = k (Ssaw-tooth - SO)2
;v - = k (A
AO)2
(1.18)
and is illustrated in Figure 12.
Thereby, k is the gain and Ao is a DC-level which allows to adjust the. symmetry of the parabola ("trapezoidal" or "keystone" correction).
8-/3-5------------------------~~ii©~~~~~~~ ----------------------------
1066
Figure 12: Generation of the Parabola with Functional Network
APPLICATION NOTE
Sparabola
_ ~ _ _ ~~ _____~__~______ _ ~v~ _____~ t
V91E-W-12
Comparing the two methods, the following properties are evident:
- the parabola amplitude using the integration method is frequency dependent: assuming a constant amplitude of the saw-tooth signal, the amplitude of the parabola is linear in the time period Tv (see 1.16) . This means different adjustments between 50 and 60Hz TV-sets. The functional (square) method gives a frequency-independent amplitude of the parabola, if a constant saw-tooth signal is provided.
- during the flyback time of the saw-tooth signal, the functional network produces a second (parasitic) parabola as shown in Figure 12
Although this parasitic parabola is present during the vertical flyback time (dark screen) this small parabola (like a spike) produces a damped oscillation of the diode modulator. The result is a damped sinusoidal vertical line on the top of the screen, if a test-grid is on the screen (the vertical lines are similar to a crutch-stick).
The maximum amplitude of this oscillation is present on the left and right top of the screen. Though its amplitude is normally only about 3mm, this effect must be suppressed.
This can be reached by two different methods:
- the linear saw-tooth voltage generating the parabola must have an extremely small flyback time. Then the very small parasitic parabola is integrated in the capacitor CK of the comparator
and has no effect (see Figure 7). The saw-tooth voltage coming from the vertical oscillator fulfills this requirement wherefore the deflection yokecurrent has a too large flyback time.
- another possibility is to hold the parabola signal constant during the flyback time as illustrated in Figure 13. This behaviour can be reached by providing a parabola output limitation and then overmodulating the functional network during the flyback time.
Figure 13: Modified parabola: constant during the Jlyback time
Vpar
V91E-W-13
--------------------------- Fjj ~~~~G;~~;9mJ~R~ --------------------------9/-3-5
1067
APPLICATION NOTE
Overcoming the problems of the parasitic parabola, the functional method should be preferred due to the independence of the frequency (SO/60Hz compatibility).
The nonlinearity which forms the parabola can be realized in two different ways:
- use of an analog multiplier
- forming a nonlinear network by piece wise linearization.
1.5 - ADJUSTMENTS
1.5.1 - Horizontal size adjustment
Adjustment of horizontal amplitude is made by modifying the mean cyclic ratio (duty factor) of the output pulses. When this mean cyclic ratio is minimum, the picture width is maximum, because the output is more frequently in the low state, and therefore the highest current is drawn from the diode modulator and the deflection current is maximum.
Figure 14: Horizontal Size Adjustment
To change the mean cyclic ratio of the pulse train (in addition to the change due to the parabolic shape of the signal) it is necessary to change the continuous level of the sawtooth pulse train (see Figure 14).
The rise of the continous level of the parabola is due to the increase of the cyclic ratio, as we have seen above. The value of pincushion correction is not modified since the parabola peak-to-peak amplitude is kept the same. Only the mean cyclic ratio varies, i.e. also the horizontal scan width.
1.5.2 - Pincushion correction adjustment
Pincushion correction is made by varying the peakto-peak amplitude of the parabola. The greater this amplitude,the greater the variation of the output signal cyclic ratio is between the ends and the top of the parabola, and therefore the more important is the parabolic modulation of the current drawn from the diode modulator (see Figure 15).
Line sawtooth l\iWI.+\i-\-l-\4cU·"\I\ . 4- signal and vertical
parabola
~
Jn~nUnUnUnUnUnUnUnUnL
_PW"'"<" signal
· t
Broad picture
4- Deflection current
Narrow picture
V91E-W-14
1-0-/3-5-------------------------~~i~~~~~f~~~ ----------------------------
1068
Figure 15: Pincushion Correction Adjustment
APPLICATION NOTE
Line sawtooth · signal and vertical
parabola
. t ~. -----~----~---
-~~-~---.--~--~-----~----~
tumrnwLrrR nnnnnnnnnn · PWM output I UUUUUUUUL ~ t signal -----.---.--------~-.-~
:, r(~~:(~~~~~~f~~~!~~!~(r~ ~:~'O"
correction
correction
V91E-W-15
1.5.3 - Trapezium correction adjustment (keystone correction) Trapezium correction is made by modifying the symmetry of the left and right sides of the parabola (Figure 16).
Figure 16: Keystone Correction
Line sawtooth +- signal and vertical
parabola
.. t
~WJlJlllJUl[1 nnnnnnnn~ nn ~--~----
J~~UUUUUUUUL
.
+-
·t
PWM ou1put signal
Top 01 picture
Bottom 01 picture
Picture broad at top and narrow at bottom
Topol picture
Bottom 01 picture
Picture narrow at top and broad at bottom
V91E-W-16
- - - - - - - - - - - - ~ ~~;~©m~:c~8~ - - - - - - - - - - - - 11/35
1069
APPLICATION NOTE
1.6 - PRODUCTS PRESENTATION
11- TEA2031A GENERAL DESCRIPTION
All the East/West correction devices are with class D diode modulator driver. Concerning the frame parabola generation, TDA4950, TDA8145 and TDA8146 use a non-linear network whereas TEA2031 A uses an analog multiplier. TDA4950 and TDA8145 generate a parabola with a fixed shape; this shape is different between the two devices and makes the TDA4950 intended for standard CRT and TDA8145 for square tubes. These two devices have a parasitic parabola suppression (during vertical flyback time) by current limitation. TDA8146 has a programmable parabola shape generation by segments which makes it suitable for different CRTs. It has also a parasitic parabola suppression by pulse during vertical flyback.
All the devices can support a keystone correction adjustment (parabola symmetry) and have 50/60Hz capability. Some others adjustments are possible (picture width ...).
Finally, another available device the TDA8147 has been designed for use in the East/West pincushion correction by driving a diode modulator but since this device has not the parabola generator and is drived by a PWM, it is very useful in digital TV-sets.
A detailed description about all the devices is done in the next chapters.
11.1 - INTRODUCTION
The TEA2031 A circuit comprises (see Figure 17) : an analog multiplier that uses a frame sawtooth signal applied on Pin 1 so that the current on Pin 7 has a parabolic modulation. This multiplier operates in current differential mode and uses a reference DC voltage, selected according to the continuous level of the sawtooth voltage, and applied on Pin 2. The level of this DC voltage also serves to correct trapezium distortion. - a reference ,voltage available on Pin 3 that can
be used (via a voltage divider) to provide input 2 of the multiplier with a reference voltage. - a current generator, producing a line frequency sawtooth signal by integrating the line flyback signal and generating current available on Pin 8. - a comparator controlling the output stage by using the line sawtooth signal applied on its +input (Pin 8) and the parabolic signal generated by the multiplier and applied on its -input (Pin 7). An output stage that can absorb or deliver current and comprises a diode connected to the DC voltage supply in order to limit the voltage applied on the output terminal during line flyback. This stage enables the diode modulator of the line scan circuit to be driven directly with a maximum current of 0.5A. This maximum current that the output can absorb is not limited by the size of the transistors but by the maximum power dissipated by the package (Minidip).
1070
Figure 17: Block Diagram
APPLICATION NOTE
a 11.2 · PARABOLA GENERATION
Using a fixed continuous current and vertical sawtooth current, the multiplier generates an output current on Pin 7 with parabolic modulation.
V91E·W·17
11.2.1 . Multiplier stage operation The multiplier inputs (Pins 1 and 2) operate in current differential mode (Figure 18).
--------------------------- ~~ii©~~!l~~~ ______________________~1=3/~35
1071
APPLICATION NOTE Figure 18: Multiplier Stage
TEA2031A
~W.
VREF = 6.5V
The output current is given by :
i7 = i7DC - k (i1 - id
i7Dc and k depend on the current reference on Pin 3.
Remarks: As we can see, the two inputs can be inverted and the slope of the sawtooth has no influence on the parabola shape.
V91E·W·18
11.2.1.a - Operation without keystone correction
In order to eliminate supply and thermal drift influences, R1 is taken equal to R2. In this case, V1DC = V2DC (Figure 19).
11.2.1.b - Operation with keystone correction
In order to correct keystone correction, V2 voltage becomes adjustable. In this case, the parabola shape presents a dissymmetry (Figure 20).
"-y,- 1.:....4/c.3.:..5:.._ _ _ _ _ _ _ _ _--.,- ~'L SGS-1HOMSON - - - - - - - - - - - ~1I©IiiI@Ili~IIiIU©$
1072
APPLICATION NOTE
Figure 19: Operation without Keystone Correction
Figure 20: Operation with Keystone Correction
v,
4V
3V V2 { 2.5V·
2V 1V
V2 =V, DC
= 2.5V
10ms
V91E-W-19
11.2.1.c - Example of applications
1. Sawtooth coming from the horizontal:vertical processor (e.g. TDA8185, TEA2028B, ... ) In this case, V1DC = 2.5V (Figure 21). For practical reason, the DC voltage comes from internal voltage reference.lmpedance value seen between Pin 3 and ground must
10ms
V91E-W-20
be 22k.Q for best conditions of operation (to have the good internal current reference).
2. Sawtooth coming from the vertical output stage (Figure 22)
In this caseV1Dc = OV and R1 = R2 + ~ RT2
Figure 21 : Sawtooth coming from HIV Processor
TEA2031A
:;:~:~.-~~~-'
ov
Typical Frame Saw-tooth
V91E-W-21
------~~--------~----~~-- ~ ~~~@~?~~~?©~ --~~~----~~~----~~1~ 5/3~5 1073
APPLICATION NOTE
Figure 22: Sawtooth coming from Vertical Output Stage
[> I v"";~,
OVN- J Yoke
1
t
TEA2031A
11.3 - LINE SAWTOOTH GENERATION
The line sawtooth signal is applied as a reference at the +input terminal of the. comparator. It is obtained by integrating the line fly back and the constant current discharge of capacitor C3 in Pin 8 (Figure 23).
11.3.1 - Role of resistors R7, RB, RT1 and 02 By means of the voltage divider bridge comprising resistors R7, RT1 and R8, a signal that is the image of the line flyback signal applied on R7, is obtained
Figure 23: Line Sawtooth Generation
on the slide contact of potentiometer RT1. The peak amplitude of this signal depends on the nominal voltage of the Zener diode 02 and on the adjustment of RT1. The role of Zener diode 02 is to maintain a constant amplitude of the signal on the slide contact of RT1 whatever the variations in amplitude of the line flyback signal.
This diode 02 can be also replaced by a single diode connected to a regulated 12V or 15V power supply.
.,."
R7
D2 RT1
Line Sawtooth
18 N\I\
Parabola (50Hz)
/V\
R8
TEA2031A
V91E-W-23
1-6-/3-5-------------------------~~~~~~9~:9©~ ----------------------------
1074
APPLICATION NOTE
11.3.2 - Role of diode 01 and capacitor C3
During line flyback, diode 01 rapidly charges capacitor C3 at the potential available on the slide contact of RT1. Then during line scanning, 01 is blocked and C3 is discharged at constant current (about 50IlA) through Pin 8. The peak-to-peak amplitude of the line frequency sawtooth signal obtained in this way depends di-
rectly on the value of capacitor C3 since it is defined by the discharge current of the capacitor and the line period (Figure 24). This amplitude can be calculated using the following equation:
C3 dt· is
Vs (peak-ta-peak) =
where Dt = duration of line and is = current in Pin 8.
Figure 24: Peak-to-peak Amplitude of Sawtooth Signal versus Two Different Values of C3 (with RT1 = constant)
C3 = 10nF
C3 = 3.3nF
~~/--~~--
Line Flyback Voltage on RTI Slide Contact
Sawtooth Signal on C3
250mvj
O.8V
Same Peak Level
OV -1==="'---'===--=-""-------------- -- --------- - -----1> t
t
Line Flyback Voltage on R7
-
-
r-
-
-1----- _____ OV
-----I-f-------- ___ ----/> t
\
V91E-W-24
The continuous level of this sawtooth signal is set by adjusting potentiometer RT1 (Figure 25). Figure 25: Continuous Level of Sawtooth Signal for Two Different Adjustments of RT1
Voltage on RTI Slide Contact
j Sawtooth Wave I on C3
Continuous Level
ov -1===-'-
----------1> t
V91E-W-2S
- - - - - - - - - - - - - - ____________ ~ ~~:~;j~~,~j~.2~
17/35
---'-'-'-C...:...
1075
APPLICATION NOTE
11.4 - OUTPUT STAGE The output stage is controlled by the comparator fed by signals applied on its inputs, i.e. the saw-
Figure 26: Output Stage
tooth signal at line frequency on +input (Pin 8) and the parabola at vertical frequency on -input (Pin 7) (see Figure 26).
TEA2031A
V91E-W·26
The comparison between the 50Hz parabola and the sawtooth signal at line frequency (16kHz) produces pulses at line frequency with a duty cycle that is modulated at vertical frequency. This allows, by
means of the diode modulator, the modulation of the line scanning current during each field period in order to carry out the pincushion correction (or East/West correction) (see Figure 27).
Figure 27: PWM Output Signal (with adaptation of time scales)
20ms
Input +
Pin 7 Input Pin 8
Continuous Level
OV ~----------------~------------------~--~
V91E-W-27
The role of the filter C2 and RT3 + R6 is to suppress the line frequency of the feedback output signal.
-- 18/35-------------- ~ ~~~(~mg~~l~~~ -------------------
1076
APPLICATION NOTE
11.4.1 - Operation of the Output Stage
The operation of the output stage can be considered as 3 separate cases according to the 3 possible states of output Pin 5.
Figure 28: Output in Low State
11.4.1.a - Output in the low state (Figure 28)
In this case resistances R6 and RT3 are connected to the ground, therefore they are in parallel with R5, according to the following diagram.
TEA2031A
The continuous level and the peak-to-peak amplitude of the parabola are at their minimum when the RT3 value is minimum. It is possible to calculate the voltage for a given point of the parabola (Pin 7) using the following equation:
v . R5 . eR6 + RT3)
7b =' 17' R5 + R6 + RT3
The capacitance of C2 is neglected as this capacFigure 29: Output in High State
V91E-W-28
itor is equivalent to an open-circuit at vertical frequency.
11.4.1.b - Output in the high state (Figure 29)
In this case, resistances R6, RT3 and R5 form a voltage divider bridge which returns on Pin 7 and capacitor C2 part of the continuous voltage available on the output terminal that is added to the parabola voltage.
The equivalent circuit diagram is the following:
TEA2031A
Continuous level is maximum when RT3 is minimum
ov .j---'-~~~~~~~-
V91E-W-29
It is possible to calculate the voltage for a given point of the parabola (Pin 7) with the following equation:
V7h =' i7 . R5 . eR6 + RT3) + V
R5
R5 + R6 + RT3 5 . R5 + R6 + RT3
~~~~~~~~~~~~~- ~ ~i~@mg~~~~t~ ~~~~~~~~~~~~~ 19/- 35
1077
APPLICATION NOTE
IIA.1.c - Output with commutation In this case and if capacitor C2 is eliminated, Figure 30 gives the signal obtained on Pin 7. It
Figure 30 : Output with Commutation (without C2)
corresponds exactly to the levels and amplitudes of the parabolas for output in the high state and the low state, linked by 16kHz commutations.
Parabola level
-
for high state
output
-
16kHz commutations
20ms
ov
In normal circuit configuration, capacitor C2 is connected and constitutes a filter with R6 and RT3. The Figure 31 : Output with Commutation (with C2)
Parabola level ~- for low state
output
· t
V91E-W-30
preceding signal is filtered and is transformed into the signal shown in Figure 31.
Mean continuous level as a function of the cyclic ratio of the output pulses
OV t +------------------'~
V91E-W-31
The 16kHz line frequency component has disappeared in the signal and only the 50Hz parabola remains, but slightly modulated at line frequency by the C2 charge when the output is in the high state, and by the C2 discharge when the output is in the low state; this gives a tiny triangular modulation signal.
We see that, when the cyclic ratio increases, the continuous level of the parabola also increases and approaches its maximum level when the output is in the high state. Conversely, when the cyclic ratio decreases, the continuous level of the parabola also decreases since it approaches its minimum continuous level when the output is in the low state.
So the continuous level of the parabola depends only on the cyclic ratio of the output pulse train. This level can be calculated by means of the following
equation: Vmean = M . V7h + (1 - M) . V7b
where
M : output pulse cyclic ratio
V7h : mean level on Pin 7, output blocked in the high state
V71 : mean level on Pin 7, output blocked in the low state
IIA.1.d - Conclusion
For a given parabolic current i7, the parabola peakto-peak amplitude depends only on resistance values R5,R6 and RT3. Therefore by adjusting RT3, it is possible to obtain a more or less pronounced parabola and so adjust the importance of pincushion correction.
The continuous level of the parabola depends principally on the mean cyclic ratio at the output, and much less on the adjustment of RT3.
2~0/~ 35-------------~~~~~~~~~~~ - - - - - - - - - - - - - - - -
1078
APPLICATION NOTE
11.4.2 - Operation in association with the diode modulator In the majority of cases, the system operates by drawing more or less high current from the modulator through the connecting inductor. The current through terminal Pin 5 of TEA2031 A is entering into
Figure 32: Operation with Diode Modulator
the circuit. It flows, either to the ground when the output is in the low state, or to Vcc through the internal diode when the output is in the high state and the output voltage tends to exceed Vcc. The circuit can also produce current.
LS
ilf(j(j1__
V91E·W·32
- - - - - - - - - - - - - - ~ ~~~;,ru~M~g~ - - - - - - - - - - - - - - 21/35
1079
APPLICATION NOTE
Figure 33: Output Oscillagrams
Current in connecting inductor LS
t OA +-----"'------"-~
OA -+++++-H+t-H++H-++HH+t-H- Line deflection
current
V91E-W-33
11.5 - SELECTION OF THE. VALUES OF CAPACITORS C2 AND C3 Correct operation of TEA2031 A depends partly. on the choice of these values for two reasons: - for a given amplitude of the parabola, the impor-
tance of fi nal pi ncushion correction at the output of TEA2031 A is determined by defining,by means of C3, the amplitude of the line sawtooth wave. - the absence of oscillation at circuit output is controlled through adjustment of the value of C2 as described below.
11.5.1 - Selection of C3 As seen before (chapter 11.3.2), the value of C3 and only this value (in the limits of the available voltage on the slider of RT1) can fix the value for the
amplitude of the line sawtooth wave. Now this amplitude must be greater than the parabola amplitude (Pin 7) but not so far in order to have a correction amplitude sufficient but permitting also an horizontal amplitude adjustment: - if the line sawtooth wave and the parabola have
the same amplitude, the pincushion correction is maximum but the horizontal amplitude adjustment range is non-exutent - if the line sawtooth amplitude is much greater than the parabola's one, we will have a large range for the horizontal amplitude adjustment, but it will be to the detriment of the pincushion correction amplitude. Once the desired line sawtooth amplitude has been fixed, we can calculate the value of C3 with the following formula
C3 = Ot· ia Va
where
Ot : line scan duration (around 53Jls) ia : Pin 8 current (around 50JlA)
Va : line sawtooth peak-to-peak amplitude (Pin 8)
11.5.2 - Selection of C2 The selection of C2 is related to the values of R5, R6 and RT3. The value of C2 must be large enough to avoid any risk of oscillations at output for the entire range of adjustment of potentiometers RT1 and RT3. The value of C2 must be small enough not to influence the shape of the vertical frequency parabola.
11.6 - APPLICATION EXAMPLE
A typical application diagram is given in Figure 34.
2·2/~35~-------------~~~j@~g~~R~ - - - - - - - - - - - - - - -
1080
Figure 34: Typical Application
JL
R7
02 BZX 46C15
APPLICATION NOTE
vee 24V
o
C1 10~F
+~
Output 3> (to diode
modulator)
Typical frame sawtooth
V91E-W·34
111- TDA4950 - TDA8145 GENERAL DESCRIPTION
111.1 - INTRODUCTION The TDA4950 and TDA8145 consist mainly of 5 parts as seen in the simplified circuit diagram (Figure 35). 1. Full-wave rectifier for the input current liN. 2. Current limiter in order to limit the rectified cur-
rent liN to the maximum value of 40/lA (with
this functional block a suppression of the parasitic parabola is possible, see chapter 1.4}.
3. Parabola network producing the current IA = k(liN}2 (k = constant).
4. Comparator and output stage working as a pulse-width modulator for driving the diode modulator.
5. Voltage reference and current reference which produces the reference current IREF via exter- . nal resistor RI between Pin 3 and Ground.
------------------------------ ~~i~~~9~~~~ ------------------------2~3~/3~5
1081
APPLICATION NOTE Figure 35: Simplified Circuit Diagram for TDA4950 - TDA8145
~----------~~~--------------------------~~r_----~
I
----~-------~
I I--------------------~
II
Jl
a'"
". II
II ~
I I
I I -if>
I I
I I
I I
I I
u
I I
>'
I I
L _________ J
I
'-----~___fu I .g
Ifl
I l!'
I
~ .3:
1 "5
Ill..
I I I
111.2 - DESCRIPTION
Let us consider the blocks in detail: The input amplifier OP1 drives the transistor 05 or 06. They offer two different signal paths, depend-
V91E-W-35
ing on the sign of the input current liN.
Assuming that liN is negative, the feedback loop is closed via the transistor 05 and the output current IC5 is given by
24/35
--------------
~
~~~@~~~Q~!?CG~
-------------
1082
APPL:ICATION NOTE
- (~)= (~) IC5 = IE5 1 + ~5
hN 1 + ~5
where ~5 is the current gain of the transistor 05. ~5 can be assumed to be more than 100, so the mismatching between IC5 and liN is less than 1%.
For a positive current liN the output voltage of OP1 decreases: 05 is switched off the current liN is the emitter current IE13 of 06.
Its collector current IC6 is given by
!6~6 IC6 = liN (1 )
Since the maximum input current is 40~, the current gain of this PNP transistor is still high enough. to give a reasonable small error. This current biases the current mirror 08 and 09. A good matching between the current ICB and IC9 must be provided. Thus the current Is is given by
!5~5 - liN (1 ) liN < 0
Is =
+ liN. ( 1 +~6~6 )
liN> 0
Neglecting the base current of 06 and 05, Is is nearly the absolute value of liN.
Note that for both signal paths, the OP1 has a feedback factor of 1. This means OP1 must be frequency compensated for unity gain.
The transistors 03 and 04 work as a normal current
mirror if the current Is plus IE is smaller than the
cu rrent liim :
.
21s < him
In this case the excess current is shunted via the PNP transistor 01.
If the current Is becomes higher
Is> hi\fl/2
the transistor 01 switches off and 02 picks up the current Is from the rectifier which exceeds the maximum value of him/2.
Using the proposed reference resistor RI between Pin 3 and Ground (11kQ) the current IE can be described with
JliN
1 IE = 40llA
liN < 40llA
The parabola network produces an output current IA which is approximately a parabola: IA = k IE2
The parabolic behaviour IA is obtained via piecewise linear approximation. For this purpose the identical resistors Rz are connected with the four emitters. The four different biasing currents iz, 3iz, 5iz, 7iz yield four different threshold voltages, so the four emitter currents of 011 are switched stepwise. A schematic illustration of the single emitter currents IEQ11 (1...4) of 011 as a function of the current IE is given in Figure 36.
Due to the exponential character of the emitter current as a function of the base emitter voltage, the output current IA is smoothed.
For designing the values of Rz and iz of this parabola network we must take a compromise between the smoothing effect and the temperature dependence. Small values of Rz and iz yield small threshold voltages for the 4 emitters of 011 . This means a good smoothing of the edges, but a worse temperature dependence.
Large values of Rz and iz yield the opposite result. Practical experiences show that a value of 0.5V for the 4th emitter (R13 7iz) for IIN= 0 gives an acceptable cmpromise.
Due to different values of resistor Rz, the TDA8145 is adapted to flat square tubes (see Figure 37 for the two different shapes of the parabola).
1083
APPLICATION NOTE Figure 36 : Transfer Characteristic of the Parabola Network
Figure 37: Parabola Shapes for TDA4950 and TDA8145
VPAR (V)
II
J
rl
/
vi
V 0.5
-,,- ......
r\.
~ TDA4950
\\
TDA8145
,r
~
\\
2ms
V
t(ms)
V91E-W-37.
The parabolic output current IA produces a corresponding voltage drop across an external resistor between Pin 7 and Ground (18kQ). The additional constant current source 10 shifts the D.C. voltage level to achieve an appropriate operating point of the comparator. Its non-inverting input is connected with a horizontal saw-tooth voltage. For this purpose an external capacitor is connected with Pin 8 and Ground which is discharged with the internal current source Ie. It will be charged with the positive
V91E-W-36
flyback pulses produced in the line transformer during the flyback time.
Due to the linear saw-tooth voltage on Pin 8 this comparator works as a pulse-width modulator. The output of this comparator controls the output stage. If the output of the comparator OP2 is high, 021 and 012 are saturated. Therefore, the Darlington outPl:Jt transistor 019,020 is switched off. The transistor 013 and the resistor R5 acts as a current source biasing the current mirror 014, 015. The transistor 016 is switched on.
If the output of OP2 becomes low, 012 and 021 are switched off. In this case the current in 014 and 015 dissappears and 016 is switched off. Synchronously the darlington stage 019 and 020 is saturated.
In order to achieve a fast commutation from 016 to 019/020 an active discharging of 016 is provided with the aid of. the transistor 017. During a normal operation range if the output current iouT is positive, only the Darlington stage (019, 020) Clnd the diode D1 are necessary to drive the external inductor. With the aid of 016 and the intrinsic substrate diode D4 the output current iOUT can become negative, too; so that the modulation range of the diode modulator becomes larger.
2-6-/3-5-------------------------~~~~@~~'lJ?~ ~-------------------------1084
APPl.ICATION NOTE
The Zener diode Z1 serves as the voltage reference. With the aid of the diodes 02 and 03, a good temperature compensation can be achieved.
Using an external resistor of RI = 11 kQ between
Pin 3 and Ground we get an accurate and temperature independent current reference to bias the internal current sources.
111.3 - APPLICATION
A standard application diagram is given in Figure 39. Pin 2 is biased from a linear saw-tooth voltage, the resistor RIN produces the input saw-tooth current. The non-inverting input (Pin 1) is connected with an adjustable voltage (keystone correction). With the aid of this trimmer, the symmetry of the parabola can be adjusted in order to correct a trapezoidal error in the colour picture tube. A further adjustment trimmer is responsible for the picture width and influences only the DC-level of the comparator input (Pin 8). (Since the discharging current sink on Pin 8 is constant, the amplitude of the horizontal saw-tooth voltage (Vpp) remains constant).
The thrid trimmer is in the feedback path and is responsible for the parabola correction factor. With the aid of this trimmer the distortion on the screen can be changed from pillow-distortion up to an over-correction (tu n-d istorsion).
For some applications the keystone adjustment trimmer is not necessary (small trapezoidal error of the picture tube). In this case, a symmetric parabola should be produced.
This can easily be obtained by AC-coupling the input (Pin 2) as seen in Figure 38.
Figure 38: AC-coupled Vertical Saw-tooth Voltage, no Keystone (trapezoidal) Correction
--1+ CIN
RIN
V91E-W-38
Figure 39: Standard Application Diagram of TDA4950 and TDA8145
vee o---~----~
26V
East-West amplitude
47nF
-II---;;b
12kQ
v"
-1 V91E-W·39
- - - - - - - - - - - - - - - - ~ ~ii;~~~:~e~ -~------------2-7/- 35
1085
APPLICATION NOTE
In order to avoid any distorsion, the time constant CIN . RINShouid be at least 10 times larger than the time period (CIN' RIN > 10· 20ms). On the other hand a too large time constant yields an undesired bouncing effect in the East/West correction. The DC voltage on Pin 1 is arbitrary. For the sake of simplicity, connect Pin 1 with Pin 3. Another possible application with parasitic parabola suppression is given in Figure 40.
The input current into Pin 2 is generated via the voltage drop on RM. Due to the common mode rejection of the input operational amplifier, the voltage change during the vertical scan time (sawtooth voltage) has nearly no effect. During the flyback time, a positive pulse (> Vcc) is present on Pin 1 and Pin 2. With this flyback pulse the current limitation in the parabola generation circuit is activated and limits the parabola amplitude. Since the flyback time is relatively long, this limitation is nec-
essary to suppress the parasitic parabola (see chapter 1.4).
IV - TDA8146 GENERAL DESCRIPTION
IV.1 - INTRODUCTION
The TDA8146 was designed for TV and monitor sets with various types of picture tubes, where a programmable parabola is mandatory. The complete block diagram is shown in Figure 41.
The following features confer to this IC an ali-purpose su itability : '- programmable parabolic current generator
- parasitic parabola suppression during vertical flyback
- output sink current up to 800mA and source current up to 100mA
- vertical current sense inputs ground compatible
Figure 40: Application of TDA4950 and TDA8145 with Parasitic Parabola Suppression
vee
RI
Deflection unit
V91E·W·40
2-8-/3-5=------------------------~~i~@~gL~~R~~ ----------------------------
1086
Figure 41: Block Diagram
APPLICATION NOTE
OUT
IGND
c
PW Z GND IREF
IV.2 - INPUT AMPLIFIER AND RECTIFIER The input circuitry (Figure 42) is designed for a common mode range up to 12V. Figure 42: Input and Rectifier Principle Diagram
V91E-W-41
The voltage drop on R1 gives on IGND (Pin 3) : VR1 = R1 ·IREF
The operational amplifier OP regulates the current through R2, thus: IR2 = (VR1 - VIN) / R2 = (R1 . IREF - VIN) / R2
V91E-W-42
- - - - - - - - - - - - - - - ~ ~~~~~gu~~~~t~ - - - - - - - - - - - - - - - 29/35
1087
APPLICATION NOTE
For VIN > 0, we note the output current of the input amplifier IN :
IN = IREF - IR2 = IREF - (Rl . IREF - VIN) I R2
For VIN < 0, we note the output current of the input amplifier Ip :
Ip = IR2 - IREF = (Rl . IREF - VIN) IR2 - IREF
The rectifier is formed by 02, 03 and 04. For VIN > 0, IN flows through 02 to the rectifier output, thus IR = IN. For VIN < 0, Ip flows through 03 from Vs into the output of the input amplifier. 04 reflects the Ip current, thus the rectifier output currrent will be IR = IPM = Ip.
If the sign convention of IR is considered, we have:
)+ IR = 1(R1 . IR;( - VIN) IREF 1= IIREF (~~ - 1 ~I~ 1
In our case, Rl = R2 = 1OkQ and IREF = 120).lA
~I~ Thus, IR = I I
If VIN is a symmetrical saw-tooth with GND as the average value and 1.6 Vpeak'le-peak, the rectified peak current will be :
Figure 43 :- Vertical Clamping Principle Diagram
Reclified
Sawtooth CUrrent IR
IRP=~=80).lA 10·10-
IV.3 - VERTICAL CLAMPING To avoid the parasitic parabola during the vertical flyback time a vertical clamp circuit was used. The vertical clamping principle is presented in Figure 43. The rectified sawtooth current IR Flows through 02 to the output. When V goes over Vs, 01 switches off and 02 on. IREF flows now through 01 to the output and IR through 02 to the ground. IRC = IREF is now the clamped value of the output current.
IV.4 - REFERENCE AND STARTING CIRCUIT Figure 44 presents the complete voltage and current reference circuitry.
The reference current is IREF = 1~'~:n = 82).lA
To guarantee the start of the device, it is necessary to choose the value of the resistor R5 in order to have a minimum current of 56).lA.
I RC
'"':~.
j-~-~~~ Rectified and Clamped
Sawtooth Current '-------i--0 IRC
V91E-W·43
3-0-/3-5 -----~------------------~~i~©~~~:~~ ----------------------------
1088
Figure 44: Reference and Starting Circuit
APPLICATION NOTE
T1
Current Reference
R5 100kO
IV.5 - PARABOLA GENERATOR Figure 45 presents the simplified circuit diagram of the parabola generator. Figure 45: Parabola Generation
Parabolic Output Current
PAR 12
V91E-W-44
Note: · It is possible 10 replace the ~witches S4 and S5 by this configuration in order to have a continuous shape variations.
V91E-W-45
1089
APPLICATION NOTE
The parabolic behaviour of the parabola output current is obtained via piecewise linear approximation. Two external pins permit an external adjustment of the parabola shape (these pins can be connected to ground or to resistors).
The parabolic output current on Pin 12 Produces a
Figure 46: Parabola Correction
corresponding voltage drop across an external resistor between Pin 12 and ground.
As it can be seen in Figure 46 the parabola can be corrected in the following limits:
VC5/VC = K5 = 1.07 with Pin 5 to GND
VC4/VC = K4 = 1.17 with Pins 4 and 5 to GND
VF
during fly back
--I-----I~---I----t-------_t-- V SE
-O.8V -O.6V
·O.3V
+O.8V
An application specific correction can be thus obtained for various picture tube types.
V91E-W-46
IV.6 - PULSE-WIDTH MODULATOR AND OUTPUT The simplified diagram of the pulse-width modulator and output is presented in Figure 47. Figure 47: Pulse-width Modulator and Output
C PAR 11
Q60 I-----<~_j 7 OUT
V91E·W-47
3~2~/3-5-------------------------~~~~~~~~:~~ -----------------------------
1090
APPLICATION NOTE
The non-inverting input of the comparator (Pin 11) is connected to a horizontal saw-tooth voltage. An external capacitor connected on Pin 11 is charged during the flyback time and then discharged by the internal current source generating the saw-tooth voltage.
Due to the linear saw-tooth voltage on Pin 11, the comparator works as a pulse-width modulator. The output of this comparator controls the output stage. If the output of the comparator is high, 067 and 064 are saturated. The Darlington output configuration 065/066 is switched off. 062 acts together with R53 as a current source, biasing the current
Figure 48: Application Diagram
mirror 058/059. The transistor 060 is switched on.
If the output of the comparator becomes low, 064 and 067 are switched off. The current through 058/059 disappears and 060 is switched off. Synchronously the Darlington stage 065/066 is saturated. In order to achieve a fast commutation, an active discharging of the 060 base charge is provided with the aid of 063.
IV.7 - APPLICATION
An application diagram is presented in Figure 48. The internal Zener configuration on Pin 9 can be useful in certain application.
+27V
~ >Om"
1UTodiode modulator
· Note: depending on flyback voltage V91E-W-48
33/35 1091
APPLICATION NOTE
v - TDA8147 GENERAL DESCRIPTION
V.1 - INTRODUCTION The TDA8147 was designed as an interface Ie between the digital circuitry and the diode modula-
Figure 49: TDA8147 Block Diagram
tor in digital chassis. The complete block diagram is shown in Figure 49.
. PW : modulated . Parabola
Jl
H
Pinning for 8 + 8 OIL package
V.2 - INPUT AMPLIFIER
The pUlse-width modulator of the TDA8147 is working with input voltages from 1V to 23V. To have the same range for the parabola voltage an input amplifier is necessary. Digital TV sets deliver an analog parabola or a PWM-signal with small amplitude (2V to 3V).
An additional signal ground (SGND Pin) separates the digital ground from the deflection circuit ground.
The internal feedback loop of the amplifier gives a voltage gain
Av = 1~.5 + 1 = 4.5 (see Figure 50)
Figure 50: Input Amplifier
SGND
V91E·W-49
AMP
6
V91E-W-50
3~4/~ 35~~~~~~~~~~~--~~~i@~~~~~~~~ ~~~~~~~~~~~~~-1092
APPLICATION NOTE
V.3 - VOLTAGE REFERENCE AND STARTING CIRCUIT The voltage reference and starting circuit have the same configuration as for the TDA8146 (see paragraph IV.4).
V.4 - PWM MODULATOR AND OUTPUT The PWM modulator (Figure 51) has the same configuration as for the TDA8146. So see paraFigure 51 : Application Diagram
graph IV.6 for explanation.
V.5 - APPLICATION A Standard application diagram is given in Figure 51. Since all the adjustment of the parabola are made by the digital processor, only the feedback loop of the PWM modulator must be carefully designed. The TDA8147 is well-suited for new TV concepts with 32kHz line frequency.
pw modulated Parabola
Pinning for 8 + 8 OIL package
V91E-W·51
--------------- ~ ~~~~m~mc~~~~ ---------------35/35 1093
APPLICATION NOTE
SUMMARY
TEA2028
GENERAL DESCRIPTION
II
MAIN FUNCTIONS . . . .
III
PIN CONNECTION (TEA 2028 B)
IV
INTERNAL BLOCK DIAGRAM ..
V
V.1 V.1.1 V.1.1.1 V.1.2
V.2 V.2.1 V.2.1.1 V.2.2
V.2.2.1
FUNCTIONAL DESCRIPTION ..
INTERNAL VOLTAGE AND CURRENT REFERENCES 1.26 V voltage reference Generator block diagram .. Current reference . . . . . .
LINE SYNC. EXTRACTION . Black level locking . . . . . . Application. . . . . . Memorizing the sync pulse 50% value
TIcO Ral'ia caIcu Iall.an . . . . . . . . . .
V.2.3 Sync pulse detection . . . . . . . . .
V.3
FIRST PHASE LOCKED-LOOP STAGE "cj>1" .
V.3.1 Phase locked-loop "cj>1" block diagram
V.3.2 Functional duty of individual blocks
V.3.2.1
Phase comparator . . . . .
V.3.2.2
Low-pass filter . . . . . . . . .
V.3.2.3
VCO centered on 500 kHz . . .
V.3.2.4
Divider stage . . . '.' . . . . .
V.3.3 Functional description of building blocks
V.3.3.1
Phase comparator "cj>1" . . . . . . .
V.3.3.2
Low-pass filter . . . . . . . . . . .
V.3.3.3
VCO (Voltage Controlled Oscillator)
V.3.3.3.a 503 kHz Ceramic Filter. . . . . . .
V.3.3.3.b Simplified Block Diagram of VCO .
V.3.3.3.c Characteristics of the External Filter .
V.3.3.3.d Study of the Internal Amplifier . . . .
V.3.3.3.e Characteristics of the non-linear Amplifier "A4" .
V.3.3.3.f Voltage-frequency transfer characteristics of VCO
V.3.4 "cj> 1" time constant switching .
V.3.5 Video identification stage
V.3.5.1
Block diagram . . . . . .
AN407/0591
TEA2028-2029
By : J-M.MERVAL I B. O'HALLUIN
Page
4
4
5
6
7 7 7 7 7 7 8 9 9
10
10 11 12 12 12 12 12 12 12 12 13 14 14 15 16 16 18 18 18 18 19
1/55
1095
APPLICATION NOTE
SUMMARY (continued)
V.3.6 Characteristics of loop <\>1
V.3.6.1
Locking accuracy .
V.3.6.2
Dynamic study . . . .
V.3.6.2.a Long time constant ..
V.3.6.2.b Short time constant .
V.3.7 Phase comparator inhibition.
V.4
LINE SAW-TOOTH GENERATOR
V.5
SECOND PHASE LOCKED LOOP "<\>2" .
V.5.1 Duty of different building blocks .
V.5.1.1
"<\>2" phase comparator .
V.5.1.2
Low-pass filter . .
V.5.1.3
Phase modulator.
V.5.1.4
Flip-flop . . . . .
V.5.1.5
Output stage . . .
V.5.1.6
Line deflection stage .
V.5.2 Operation of building blocks.
V.5.2.1
Phase comparator "<\>2" .
V.5.2.2
Low-pass filter f(p) . . . .
V.5.2.3
Phase modulator. . . . .
V.5.2.4
Line flip-flop (TEA 2028 only)
V.5.2.4.a Block Diagram .
V.5.2.4.b T10 Calculation
V.5.2.4.c 16 ms Window .
V.5.2.4.d Auto-set to "1" .
V.5.2.4.e Maximum "T1 0" value as a function of "C1"
V.5.2.5
Line output stage & inhibitions .
V.5.2.5.a Inhibition at start-up . . . .
V.5.2.5.b Inhibition during line flyback
V.5.2.5.c Safety inhibition . . . .
V.5.2.6
Line deflection stage . . . .
V.5.3 Characteristics of loop "<\>2" . .
V.5.3.1
Study of the static error . .
V.5.3.1.a Phase shift error in case of no adjustment.
V.5.3.1.b Study of shift adjustment. . . . . . . . .
V.6
VERTICAL DEFLECTION DRIVER STAGE
V.6.1 Frame sync extraction . . . . .
V.6.2 Frame saw-tooth generator . . . .
V.6.2.1
60 Hz standard switching . . .
V.6.3 Functions of frame logic block . . .
V.6.3.1
50/60 Hz standard recognition .
V.6.3.1.a 50 Hz Standard Recognition ..
V.6.3.1.b 60 Hz Standard Recognition ..
V.6.3.2
Vertical synchronization window - Free-running period
V.6.3.3
Frame blanking signal . . . . . . . . . . . . .
V.6.3.4
Frame blanking safety (TEA 2028 only) . . . .
V.7 V.7.1 V.7.2 V.7.3 V.7.4
SWITCHING POWER SUPPLY DRIVER STAGE Power supply block diagram . . . . . . . . . . . General operating principles . . . . . . . . . . . Electrical characteristics of the internal regulation loop Power supply soft-start . . . . . . . . . . . . . . . .
Page
19 19 20 21 21 21
22
23 23 23 23 23
24 24 24 24 24 24
25 25 26 26 26 26 26 27 27 27 27 27 30 30 30 30
31 32 32 33 33 34
34
34 34 36 36
37 37 38 38
39
-2/-55-------------------------~~ii@~~~~g~ ---------------------------
1096
SUMMARY (continued)
V.7.5 V.7.6 V.7.6.1 V.7.6.2
. V.8 V.8.1 V.8.2
Protection features . . . . . . . . . . . . TV Power supply in standby mode . . . .
Regulation by primary controller circuit Regulation by TEA 2028 . . . .
MISCELLANEOUS FUNCTIONS . . . . . Super sand castle signal generator . . . . Video and 50/60 Hz standard recognition output
VI
TEA2028 APPLICATION DIAGRAM . .... .
APPLICATION NOTE
Page 40 41 41 41 42 42 42
43
TEA2029
VII
TEA2029 : DIFFERENCES WITH TEA2028
44
VI1.1 GENERAL . . . " . . . . . . . .
44
VI1.2 PIN BY PIN DIFFERENCES .. .
44
VI1.3 TEA 2029C PIN CONNEXTIONS .
45
VII.4 FRAME PHASE MODULATOR .
46
VII.5 FRAME BLANKING SAFETY .
47
VI1.6 ON-CHIP LINE FLIP-FLOP . . .
48
VI1.7 AGC KEY PULSE . . . . . . . .
48
VIII
APPLICATION INFORMATION ON FRAME SCANNING
IN SWITCHED MODE (TEA2029 ONLY) .
49
VIII. 1 FUNDAMENTALS . .
49
VII 1.2 GENERAL DESCRIPTION . . . . . . . . . . . . . . . .
49
VII 1.3 TYPICAL FRAME MODULATOR AND FRAME OUTPUT WAVEFORMS
50
VIII.4 FRAME POWER STAGE WAVEFORMS.
50
VII 1.5 FRAME FLYBACK . . . . . . . . . . . .
51
VII 1.6 FEED-BACK CIRCUIT . . . . . . . . . .
52
V1I1.6.1 Frame power in quasi-bridge configuration
52
VII1.6.1.1 Choice of "r" value . . . . . . . . . . .
52
VII1.6.1.2 Influence of r3 value . . . . . . . . . .
52
VII1.6.1.3 "S" Correction circuit in quasi-bridge configuration
53
V1I1.6.2 Frame scanning in switched mode using coupling capacitor
53
V1I1.6.3 Frame safety . . . . . . . . . . . . . . . . . . . . . . . .
54
VII 1.7 FRAME SCANNING IN CLASS B (WITH FLYBACK GENERATOR) .
54
V1I1.7.1 Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . .
54
IX
TEA2029 APPLICATION DIAGRAM
COMPLETE APPLICATION WITH TEA2164 .
55
- - - - - - - - - - - - - ~ ~~~.;mg~l~.~~ - - - - - - - - - - - - -3/55
1097
APPLICATION NOTE
I - GENERAL DESCRIPTION
As depicted in figure below, the TEA2028 combines 3 major functions of a TV set as follows: - Horizontal (line) and vertical (frame) time base
generation for spot deviation. The video signal is
Figure 1
used for the synchronization of both time bases. - On-chip switching power supply controller syn-
chronized on line frequency.
Miscellaneous Power Supplies
Horizontal
oen
Power Amp. 1 - - - - - - - '
~ co
N o
N
Z
Miscel!aneous
<{
Power Suplies
Oi
This integrated circuit has been implemented in bipolar 12L technology, and various functions are digitally processed. In fact, resorting to logic fu nctions has the advantage of working with pure and accurate signals while full benefit is drawn from high integration of logic gates (approx. 110 gates per mm2).
The main objective is to drive all functions using an accurate time base generated by a master 500 kHz oscillator.
Also, horizontal and vertical time bases, are obtained by binary division of reference frequency. This has the advantage of eliminating the 2 adjustments which were necessary in former devices.
One section of this integrated circuit is designed to drive a switching power supply of recent implementation called "master-slave". Switching takes place on the primary side (i.e., directly on mains) of a transformer. The device ensures SMPS Control, Start-up and Protection functions. Control signals go through a small pulse transformer thereby providing full isolation from mains supply.
This new approach fully eliminates the bulky mains transformers used in the past. In addition, it offers
optimized power consumption and reduction of TV cost-price.
" - MAIN FUNCTIONS - Detection and extraction of line and frame syn-
chronization pulses from the composite video signal. - Horizontal scanning control and synchronization by two phase-locked loop devices. - Video identification. - 50 or 60Hz standard recognition for vertical scanning. - Generation of a self-synchroriized frame sawtooth for 50/60Hz standards. - Line time constant switching for VCR operation through an input labeled "VCR" (Video Cassette Recorder). - Control and regulation of a primary-connected switching power supply by on-chip controller device combining: · an error amplifier · a pulse width modulator synchronized on line
frequency · a start-up and protection system
-- 4/55 ------------- ~ ~~~~;mW~l~9c~ ---------------
1098
APPLICATION NOTE
- Overall TV set protection input
- Frame blanking and super sandcastle output signals
III - PIN CONNECTION (TEA2028B)
Frame blanking safety input for CRT protection in case of vertical stage failure.
Pin Number
Description
1
Horizontal output monostable capacitor
2
Frame blanking safety input
3
Frame saw-tooth output
4
Frame blanking output
5
Frame ramp generator
6
Power ground
7
SMPS control output
8
Supply voltage (Vee)
9
SMPS regulation input
10
Horizontal output
11
Super-sandcastle output
12
Horizontal flyback input
-
13
Horizontal saw-tooth generator
14
Current reference
15
SMPS soft-start and safety time constant capacitor
16
«>2 phase comparator capacitor (and horizontal phase adjustment)
17
Veo phase shift network
18
Vcooutput
19
Veo input
20
Frame sync time constant adjustment capacitor
21
Substrate Ground
22
<P 1 phase comparator capacitor
23
VCR switching input
24
Video and 50/60Hz identification output (Mute)
25
Video identification capacitor
26
Horizontal sync detection capacitor (50% of peak to peak sync level)
27
Video input
28
Safety input
Package: DIP28
1099
I~ ~
0 0
470 !l
~
.4.7k!J:
!'i:(I)
2.2~F
@~
~C!»
VCR Switching
'~~""'~6"
Input
50/60 Hz Video Standard
~cn
,~~
Identification OutPut
~
»
2
o'"
'C"D
N
<D
6
'"
3.J2kil, 1 %
T-X A, I 1'7'"
TEA 2028 B I
I~ ii! I\J
:<
Z
m-I
:0
»Zr
»
"tJ
r"tJ
» 0
-I
(5
Or J 0
Z Z
0
0
~
C
-mI
i>
G>
:»0
5:
+135V
v~c. Frame
Blanking
2.7Mn
APPLICATION NOTE
V. FUNCTIONAL DESCRIPTION
Majority of the on-chip analog functions were computer simulated and results such as temperature variation, technological characteristic dispersion and stability, have led to the enhancement and implementation of actually employed structures. A parallel in-depth study of the device implemented in form of integrated sub-sections is provided to analyze the overall performance in a TV set.
V.1 -Internal voltage and current references V.1.1 - 1.26V Voltage reference For optimum operation of the device, an accurate and temperature-stable voltage generator independent from Vec variations is used (Band-gap type generator).
The generated 1.26 V is particularly used as refer-
ence setting on input comparators.
V.1.1.1 - Generator block diagram
Figure 3
In practice, maximum drift due to temperature can be +0.23 mVfC
i.e., ± 1.5 % for a L'.T of BOoC.
V.1.2 - Current reference This is implemented using the 1.26V generator in combination with an external resistor.
Figure 4
1ref
tVBE1
t I 1.26V
__ Band Gap __________.JI
Rex! .3.32 kn, 1 %
with 'A = K· T = 25.7mV at +25'C q
dd'TA = 1q:<. = +0.OB6mVrC
dVBE = VBE(25') - 1.26 =-2mV/oC
dT
T
If A'A = 1.26 - VSE
Then: Vo = 1.26V (temperature-independent)
IREF = 114 = V14 = 1.26 + VSEI - VSE2
REXT
REXT
Let's 114 = I and VSEI = VBE2
then: IREF = R1.26 = 3BOllA
EXT
91 AN2028/29-04
Thus, it follows that IREF is accurate and independent of both Vcc and temperature.
A set of current generators proportional to IREF current are used in various circuit blocks.
V.2 - Line sync. extraction
Horizontal and vertical time bases should be synchronized with corresponding sync. pulses transmitted inside the infra-black portion of video signal. The duty. of this stage is to extract these sync pulses. The output signal, called composite sync, contains the vertical sync which is transmitted by simple inversion of line sync. pulses.
The vertical sync pulse is then extracted from this composite signal.
--------------
~
~~;~~)~~~~~~~
7/55
--------------
1101
APPLICATION NOTE
Figure 5
Video Input Signal
Composite Sync. Output Signal
I ...
~I
The main advantage of this arrangement is its ability to operate at video input signal levels falling within 0.2V to 3V peak-to-peak range and at any average value. The operating principle is to lock the black level of the input signal (pin 27) ontointernaly fixed voltage
V.2.1 - Black level locking
Figure 6
V
Vpp~~
Video
C27
I__ Frame Sync.
91AN2028/29·05
(VN) and then memorize the average voltage of the
sync pulse by using an integrating capacitor con-
nected to pin 26.
.
Finally, the composite sync signal is delivered. by a
comparator the inputs of which are driven by V50% and video signals.
n- V
Vp
:..dS1
. - - - - - - - + -....
~VN = 2V
1\ I 1\ I I\ I
~..JL
The video signal is applied to pin 27 through the coupling capacitor "C27". Since the sync pulse amplitude is generally equal to 1'/3 of Vpp (i.e. 66mV to 1V) and in order to obtain a good precision of the black level, the sync pulse should be amplified by a coefficient of - 14 before being applied to the comparator "Ct". This comparator will charge the
91 AN2028/29·06
"C27" capacitor as long as VS1 > VN. VS1 will stabilize at VN during the line flyback interval "T,' if the average charge of "C27" capacitor is nil for one TH period.
IcllD is calculated such that the locking occurs at the middle of the back porch.
-8/5-5 -------------~~~~@~g~~i~ - - - - - - - - - - - - - - -
1102
Figure 7
APPLICATION NOTE
VN (2V)~f----:~.!..f-+------===~--,------
IIe
__·_ -5!JA~~ ~~~-------~~---.~~==
I
91 AN2028/29-07
The to.VS1 produced by 10 during the line trace which is:
must be equal to b.VS1 during the time interval "t1 ", i.e. :
It follows that:
substituting TH = 64 fls, tr = 12 fls, ts = 4.7 fls (which are standard and constant values) into above
equatI.On: JI;c; = 6.23
V.2.1.1 - Application Atle = 5flA ==> 10 = 31 flA
- With C27 = 220nF, b.Vs will be
14x 25 x2502 = 16 mV
whieh yields 0.8 % maximum error in black level
with respect to VN = 2V at the beginning of retrace
time - Due to transposition on amplifier stage, the black
level voltage on pin 27 is equal to 2V. - In practice, at low amplitude video signals, it is
recommended to insert a low-pass filter before the "C27" capacitor so as to attenuate the chrominance sub-carrier and the noise components. The aim is to reduce the phase variations of the detected sync pulse and thus enhance the horizontal scanning stability.
Figure 8
, ,
~~~-CJ-4r_2~20~
Chroma Burst
~.100 pF ,I
WE
91AN2028/29-08
V.2.2 - Memorizing the sync pulse 50% value
The objective is to memorize the voltage corresponding to 50 % of the line sync pulse VS1 by using an external capacitor connected to pin 26.
----------------~~~~~~~TI~~g~ --------------------9-/5-5
1103
APPLICATION NOTE
Figure 9
A 2R 11
tVS1 + vo
v~c
'. b. "~:lJ
VN + Vo --
1
0
1
1
V50%1 ,.'.";:b--;'t !
, I
1
b.
A
I }N
1
1
1
rC26
~~
o
.
I
10:
I
1
1 1
F - 1
.. t
1
i V26! !
1 1 1
V50% ::::::l;7"1
1
1 == ... t
I
91 AN2028/29-09
The overall arrangement comprises two comparators.
- Comparator C2 : delivers an output voltage "V1" by comparing VS1 + Vo, V26 and the voltage drop across two resistors.
- Comparator C3 : which delivers a constant output current thereby maintaining on capacitor "C26", the voltage V50% corresponding to 50% of peak to peak sync pulse.
During the line scanning, diode "D" is reverse biased : VS1 + Vo = V1 < V26 and C3 will deliver a current 10 which will discharge the capacitor.
During sync pulse interval, VS1 + Vo = Vp + Vo, diode "D" begins conducting and thus: V1 = (Vp + Vo) - (2 R il). Since the capacitor has been slightly discharged ~ V1 > V26, comparator C3 begins charging the capacitor until C2 is brought to equilibrium. At this time,
I i 1 ="2
w h ere
.
I
=
V26 -
Vo R
VN
i
.
thus V1 = Vp + Vo - 2R"2 = Vp+ VN + 2Vo - V26
and
V1
=
V26
~
V26
=
VP+VN --2-
+ Vo
=
V50%
A high value C26 capacitor will thus memorize the voltage level corresponding to 50% of the line sync. pulse.
V.2.2.1 - ~ Ratio calculation
During the line scanning period (TH - Ts), the
capacitor C26 will loose a charge equivalent to :
10 (TH - Ts).
This energy must be recovered before the end of
sync pulse such that: Ic· ts > 10 (TH - Ts)
therefore
JIc;;
>
TH -t
- ts s-
JIc;; > 12.6
In practice, for C26 = 100nF, 10 = 251lA and Ic = 800llA
V.2.3 - Sync pulse detection
. This function is fulfilled by comparing the inverted video signal (VS1 + Vo) whose black level is con. stant at 2V, with the sync 50% voltage level on pin 26.
-10-/5-5------------------------~~~i@~~~~~~~ ~--------------------------
1104
Figure 10
APPLICATION NOTE
V50%
26.f------{
JL
Frame Sync.
Separator
V;''I 'V
~ ./"""-+-___
LS
I
- ____ r - ~ tc::.T -- LS
LS O--C::J---{
lJlJ
250 ns ~ I I
Line Sync. Output toward Phase Comparator 'l'1
On video C Recognition Output
91AN2028/29·10
Comparator C4will deliver the line sync pulse (LS) which will be used for 3 functions:
- Horizontal scanning frequency locking: output to $1 phase comparator.
- Frame sync extraction for vertical scanning synchronization.
- Detecting the presence of a video signal at circuit input.
The LS signal in two latter functions is filtered for noise by using combination of current generator I and a zener diode equivalent to a capacitor. Using this extraction technique at a very noisy video signal yields remarkable display stability. The device also provides for scanning synchronization at aerial signal attenuation of approximately
75dB, i.e. 15 to 20dB better than other sync processors.
V.3 - First phase locked-loop stage "$1" This stage is commonly called the first Phase Locked-Loop "$1 ". Its duty is to lock. the frequency and the phase of the horizontal time base with respect to the line sync signal.
In the absence of transmission (i.e. lack of line sync), the horizontal scanning frequency is ob-
tained by dividing the output frequency of a VCO
device. This VCO oscillates at approximately 500kHz and uses a low frequency drift ceramic resonator. This method eliminates the need of horizontal frequency adjustment.
- - - - - - - - - - - - - - - ~ ~i~~mg~~Ii~E~ - - - - - - - - - - - - - - - 11/55
1105
APPLICATION NOTE
V.3.1 - Phase locked-loop "(j>1" block diagram
Figure 11
,..-----------,
I Phase Comparator
I
~~INII
i
I
I
A
Ii
~~
I
i i :
I I
I
'-_ _ _ _ _ _ _ _ _ _ ...JI
~ -~OUT
Low·pass Filter 1--_ _ _---,
F(p)
By-32·Divider <01 V.C.O.
Stages
B (kHz/V)
Horizonlal Frequency
o
Ceramic Resonator
91AN2028!29·11
V.3.2 - Functional duty of individual blocks
\0.2. 1 - Phase comparator The duty of this comparator is to issue an output current proportional to the phase difference between (j>IN and (j>OUT. V.3.2.2 - Low-pass filter This filter suppresses the parasitic component containing the sum of phases, smoothens the phase difference component and determines the timing characteristics of the loop. V.3.2.3 - VCO centered on 500kHz
Figure 12
This is a voltage-controlled oscillator which generates an output frequency proportional to the voltage applied to its input.
This voltage is delivered by low-pass filter.
V.3.2.4 - Divider stage It is used to divide the VCO frequency (500kHz) by 32 so that it can be compared with the line sync signal frequency of 15625Hz.
\/'.3.3 - Functional description of building blocks
V. 3.3.1 - Phase comparator '\j) 1"
40UT
I
V'Pt Signal
I
I
1..26~
1.26V
Video Recognition
2 !
_
1mA
Mute - 0 _.
VCR~l"
VCR Mode SwitchinQ
41N I I
~: LS~
~
Long !.pi Inhibition
The comparator is functionally equivalent to a signal multiplier.
-12-/5-5---------------------------~ ~i~~~~~:~~~
1106
91 AN2028!29·12
APPLICATION NOTE
Let's assume that: iLS = I sin (OOHt + !\lIN) and V~1 = k cos (OOHt + !\lOUT) then: I. = -iL2S' -k [ sm. ¢IN - "'""out) + sl.n(2ooHt + "'""IN + <!>out)]
Figure 13
\ ,
I
/
" ' .... _-",,,,/
+1H-~-I o~~--~~------~~----~
-1
..
91AN2028/29-13
- the low-pass filter will suppress the 2fH frequency component
- !\lIN - !\lOUT difference being low: sin (!\lIN - !\lOUT) ~ !\lIN - !\lOUT
- the output current will be therefore proportional to the phase difference between the signals compared.
In other words, the average current over one period is:
iAV x TH = I(~+I'.t)-I (~- t-.t)= 21 t-.t
Figure 14
.
IAV
=
t-.t 21TH
and
t-.t
=t-.T~H
The comparator conversion gain is thus:
A =.i.- =J. (inNrd) M) 1t
Later in our discussion we shall consider the two possible values of the current I.
For the time being, let's define these values as follows: - I = SOOIlA for "long time constant" or normal
operation - I = 1.SmA for "short time constant" VCR mode or
synchronization search (Mute). The values of A are therefore: - ALONG = 0.16 mAird - ASHORT = 0.47 mAird Use of comparator inhibition signal is quite useful under noisy transmission conditions. It eliminates risk of incorrect comparison during the line scanning phase which would be due to the noise present on LS signal. Horizontal phase and image stability are thus highly enhanced.
Characteristics of this inhibition signal will be discussed at the end of. this chapter.
\1.3.3.2 - Low-pass filter - Its main function is to reject the 2fH (31 kHz)
frequency component delivered by the phase comparator. - It also defines the characteristics of the loop in transient mode. The filter is built around two sub-sections which determine the stability and the response time of the loop in the following modes of transmission: - Normal or VCR modes. See section V.3.6 "Dynamic study of <jl1".
R1
F)I nFI (4.7kQ) C1 (2.2 Il
C 10
VCO 91 AN2028/29-14
---------------------------- ~~~~~~g~~~~~ -------------------------1-3-/5-5
1107
APPLICATION NOTE
R is the dynamic input resistance of the VCO. The filter transfer function may be defined as follows:
f(p) = iV = Z(p)
Z(p)=R.
1+R1C1p
1 +p(RC+R1C1 +RC1)+RR1CC1 p2
The second order terms of the denominator can be converted to first order products as a function of frequency as follow:
Figure 15
20 16g If!
1+j~
Idl)=R
11
(1 + 1.112)(1 + 1.113)
with R1 = 4.7kQ, R = 500kQ, C1 = 2.2~F, C = 10nF we obtain:
-
11
=
1 2nR1
C1
= 15.4Hz
1
- 12 = 2n(RC1 + RC + R1C1) = 0.14Hz - 13 =3.43kHz
20 log R
I
I
~
° I ~~1I0~.1~4H~z-71~15~.4-H-z --3-.4-3 k~H~z II~~~--~--
t I
I
I
~]l:~
2
\0.3.3 - VCO (Voltage Controlled Oscillator)
Its function is to generate a frequency proportional to a control voltage issued externally, by the lowpass filter in our case.
The period of the output signal is used as timing reference for various functions such as, horizontal and vertical time bases. The frequency range must be short and accurate:
- It must be short since the power dissipated within the horizontal scanning block is inversely proportional to the line frequency.
- The accuracy is required if the adjustment is to be omitted.
91 AN2028/29·15
The basic arrangement is to employ a ceramic resonator (or ceramic filter) which has quite stable characteristics as a function of frequency. A filter whose resonating frequency is a multiple of line frequency (15625Hz) is to be selected. An example is 32 x 15625 = 500kHz.
a. 503 kHz Ceramic Filter
Figure 16
Figure 17
Symbol
Equivalent Circuit
o--lo~
91 AN2028/29·16
R1
L1 C1
~~
Co 91 AN2028/29·17
-14-/-55------------------------- ~~~~@~~If~~~ ----------------------------
1108
Where:
R1 =7D, L1 = 1.26 mH, e1 =78 pF, eo =507 pF
- Series resonance frequency: 1
fs = 2rc'l'I1CT = 503kHz
- Parallel resonance frequency:
fp = fs . --\I 1.+"C~o" = 540kHz
- Tolerance within the resonance area: 503kHz ± 0.3 %
- Temperature stability:
±0.3 % of fa at ,1T = 100 De
b - Simplified Block Diagram of veo
Figure 19
Figure 18
APPLICATION NOTE
I
). ........ Vl
: ,,,,
a)
'i"3
N a
N
« Z Oi
Non-linear
R
220 n 18
Rl 1k.n8 17
ICl 150 pF 2200
Cl 503 kHz
The overall arrangement is equivalent to a variablephase amplifier configured in closed loop with the external passive filter.
The system will oscillate if the open-loop gain is OdB and if VOUT leads VIN.
In closed-loop oscillating mode, the phase variation of V18lViN imposed by V22 will result in same VouTIV18 variation but of opposite sign.
This phase change will finally correspond to a change in frequency.
Figure 20
C Il.5nF
91 AN2028/29-19
V22 Phase Conlrol
91 AN2028/29-20
------------------------------ ~ ~~~@~g~f~~~ ------~-------------------1-5-/5-5
1109
APPLICATION NOTE
c. - Characteristics of the External Filter The ceramic resonator behaves as a capacitor at f < fs (fs : series resonance frequency) and as an inductor at frequencies falling between its two resonance frequencies. Combined with a "R.C" network to generate a 90° phase lag, the overall arrangement will exhibit the following characteristics:
Figure 21
~VOUT!V'B (Degrees)
-30 -20
-90 -10
-150
480
500
520 Frequency (kHz)
440 U 503 kHz
,,,~D
2.4 kU
2.4 kQ resistor =pin 19 input resistance Figure 22
Thus, a variable (24° to + 135°) phase lead with a gain higher than 10 dB, must be implemented on-chip so as to enable the system to enter into oscillation. The frequency dead points correspond to the maximum internal phase variations. This phase shift is
controlled by voltage V22 whose value of 5.6V ± 0.7
is determined by two diodes.
From the above Figure, the non-linearity of phasefrequency characteristics is clearly apparent. If linear voltage-frequency response is required for a symmetrical gain of ljJ1 loop, it would then be necessary to implement a non-linearity, on the phase control amplifier A4, but,in the opposite direction. d. - Study of the Internal Amplifier
Let's study the gain and phase response of VV18 IN
as a function of V22.
V22 = v~ where K is a non-linear coefficient
To start with, the "Vc" voltage of comparator "A3" is taken as reference parameter.
The dynamic representation of the output stage can be depicted as below (figure 22).
with: 12' = 1 . i2R C (at f = 500kHz)
+Joo 1 1
I
· ,
i2
R1C100=
1=>
12
=1
+- .J
and Z = R1 + ~C « R~ i ~ il
JOO
R1
;2 =? ;1
;18
tR
Z
V18
.,
12
!'-!
!'-!
91 AN2028129-22
R1 C1 network produces -45° phase lag of "i" with respect to "i2", around 500kHz.
i1 AND ;2 calculation as a function of "Vin" on pin 19 - A1 Am.p. llfVleS1r:-R=c-=1-2-0=0 21
Vln dr1 57
dr : dynamic resistance = ~
-
A2
AmpII'f'ler
:
i2 VS2
=
1 2dr2
=
1 54
~ - i2 = -VS1xi-2 = 0.395 -7 .12 = 0.39 VIN
VIN VIN VS1
· i2 is in phase with VIN therefore: i3 = -i2 = -0.39 VIN
-16-/-55------------------------- ~~~~i~~~~g~ ----------------------------
1110
APPLICATION NOTE
Figure 23 : Vector representation of V18IVIN
VOUT phase variation = f (Vc) VIN
/
V1s @il(max)
Ril
-R(i1 +12l
--~----~~~~~--
Figure 25 : Vc = F(V22)
Vc(mV)
91 AN2028/29-23
- A3 Amplifier:
i1 = i3 - (~~ ~+ ) = - 0.39 VIN ( -4~c + ~)
"VIN" always leads the "iJ" by 180, only the amplitude of i1 is a function of Vc (See figure 23).
VOUT =-R h(1 +jR1C1f1l)+i2
VIN
1 + J(R1 + R)CWl
j (~- ~~ i1 = - 0.39 VIN
and i2 = 0.39 VIN
The following figure 24 illustrates the characteristics of V181VIN phase versus Vc. - Phase variation determined by Vc falls between
+240 and +1350 range - The gain is higher than 10 dB. The pin 18 output
signal of 30 to 40 dB has a rectangular component (See figure 24).
e. - Characteristics of the non-linear Amplifier "A4"
This is a differential amplifier whose equivalent feed-back resistors of emitters vary as a function of its input Voltage.
Figure 24
Figure 26 : 122 = F(V22)
122(~) 0.7
91 AN2028/29-25
0.6
0.55 - - - - - - -dV22 ",33 MD.
0.5 dV22 "" 1
di l2
di22 _ :
0.4 +-82~0-kLQl-': ~--:",....::V2.2 (V)
5.6 6 6.5 91 AN2028/29-26
The maximum output voltage swing is set by two "clamp" diodes connected to "V22" input.
f. - Voltage-frequency transfer characteristics of VCO
The transfer characteristic is linear and centered at 5.6Vat 500kHz operating frequency.
- T transfer = :~ =22.4kHzlV and once it goes
through five divide-by-two stages:
T= 22.4 = 0.7kHzlV 32
0
t-- A
+ 10 0
0
+2a
·
~ )'--... / /
~
- 150
-100
50
20
20IogV-("dB) V,N
~ ~ ~ + 40 + 30
+ 20
t-
0 +20 +50; r
Vc (mV) +100
91 AN202B/29-24
- - - - - - - - - - - - - - - ~ ~~~;;1tlg~~~~~ - - - - - - - - - - - - - - - 17/55
1111
APPLICATION NOTE
Figure 27
520 'N :I: ,:0
1gwz3sa0 -- -
uaw : . ~
az: 48or-V
518kHz /
V
J- T = 22.4 kHzIV
I I
/ I I , I I I
5 5.68 6
7
PIN 22 VOLTAGE "V2i' (V)
91AN2028/29-27
V, 3.4, - "<1>1" time constant switching
When switching between stations or receiving signal via a VCR, the loop locking interval must be as short as possible so as to avoid unwanted visible effect on the picture, In fact, since the synchronization between the VCR motor drive and the playback head is rather imperfect, it will produce frequency and phase fluctuations in the output composite video signal. Under these conditions, phase locking interval must be "short" (VCR Mode),
In the case of broadcast transmission, this loop must also filter all pliase variations produced by noisy sync signal. In this case, its locking time constant must be "long" (normal mode).
In other "jungle" circuits, this time constant switching is carried out by capacitor switching within the filter loop. In our case, this function is achieved by changing the current amplitude of the phase comparator. This a.mplitude changing modifies the open-loop system gain and therefore the damping coefficient and the locking time constant. The device will be in short time constant mode under the following two conditions: - VCR Mode or SCART Connector Mode:
This mode is enabled by a low state on pin 23. V23 < 2.1 V. - Transmitter search and tunning. In order to accelerate the capture, a "Video Identification" stage will detect the presence or the absence of a video signal on input pin 27, and deliver accordingly a signal called "Mute".
V.3.5 - Video identification stage
This stage will detect the coincidence between the line sync pulse (if present) and a 2f.ls pulse issued from the logic block. This 2f.ls pulse at line frequency is positionned at the center of line sync pulse when the first loop "<p1" is locked. This sampled detection is stored by an external capacitor connected to pin 25. The video recognition status is also available on pin 24 so as to enable Sound Muting during station search process and the inhibition of Automatic Frequency Tuning.
-18-/5-5-------------------------~~~~@~g\~~9~ ----------~----------------
1112
V.3.5.1 - Block diagram Figure 28
APPLICATION NOTE
The video recognition signal is delivered by a hysteresis comparator. The recognition time "Tr" is adjustable by an external capacitor, as soon as q>1 is locked: - IC25(Av) = Ic x ~ 64 I-1s
and:
- TR = C25 x -I-VH- = 1.96 x 105 X C25
C25(AV)
- with C25 = 4.7 nF => Tr = 1 ms (which is clearly quite last)
Figure 29
<P1~ 1 I
Line Sync. I : I
LS - - " 4.7 ~ L - -
2J.lS~
iC(25)
I i
I
: with Video
iC(25)
I I I I
: without Video I
Mute.
outPUo~.!.---I=--f!f-V-H-Y-S-T=-ol.I~~
VL VH
V25
4.6 V
91 AN2028/29·27
V.3.6 - Characteristics 01 loop cj> 1
\1.3.6.1 - Locking accuracy Let's study the phase error "q>OUT - q>IN" under steady state conditions: The open-loop gain is :
_ T(p) _ AB I(p) -I
Where:
· A = 0.16 mAird (long time constant)
· A = 0.47 mAird (short time constant) · B = 0.7 kHzlV or B = 4.4 103 rdls
_ I( ) - R x
1 + "t1P
P - (1 + "t2P) (1 + "C3P)
Where: · R = Dynamic input resistance 01 VCO. II a phase step 01 /lq> is applied to the input, the following would be obtained as a function 01 (p) :
M> cPIN(p)=-
P
Using the last value theorem: lim I(t) = lim p .I(p)
Let's calculate lim (q>IN - q>OUT) p-.O
- The closed-loop gain is :
_ H _ ~ _ ABI(p) _ cPOUT(p)
(p) - 1 + T(p) - P + ABI(p) - cPIN(P)
= that is :pli-m.op (cPIN - cPOUT)
lim 'A:I(O) --; 0
p->O P +
It is therefore deduced that the system can lollow
all input phase variations without producing any
static error.
.
In practice, there will be a slight error due to the input bias current "IB" 01 VCO, which is 0.551-1A at fa = 500kHz. This DC current is delivered by a
phase comparator which will generate a phase
error 01 :
---------------~~~i~~~M~~~~ - - - - - - - - - - - - - - - 19/55
1113
APPLICATION NOTE
- long time constant:
L1<PLONG =_I_B- = 0.55 x 10-3 = 3.4 x 10-3rd
ALONG
0.16
or 35ns in L1t
- short time constant:
L1<PSHORT
= -
IB A-
-
;:
12ns
SHORT
These two errors cause a horizontal picture displacement. On a large screen of 54cm wide, this will be : 64 - 12 = 52/ls, which for both modes corresponds to a shift of :
L1LINE -- M'LONG5-M2)SHORT x 520--0.24 m. m
It is obvious that such displacement can be fully neglected.
Response to a Frequency Step
The input phase is : <PIN(t) = L1mt
which as a function of (p) is : <PIN(p) = L1~
P
The accuracy is :
I.1m (<PIN -
p->O
<POUT)
=I'1m p->O
L1m
P
+
A
8
f()
0
=
L1m A8R
where R = 500KQ at f(o)
In this case, the phase error depends on both, the magnitude of the frequency step and the static gain A8R.
In general, ~: which is the open-loop static gain, is
taken into consideration.
Figure 30 : On Screen Display.of Time Constants
L1m =A8R = 21tL1f =A . 21t . 8' . R
L1<P
L1t x 21t
= L1f
21t.
=> L1t A8'R x TH (8' In kHz/V)
· In normal mode: ALONG = 0.16 mAlrd
. =>
MM =
5.5kHz//ls
R = 500kQ
· In VCR mode: ASHORT = 0.47 mAlrd
=>
L1f L1t
= 16.5kHzI/ls
Note : The capture range is specified within
± 500 Hz with respect to 15625 Hz.
Numerical Example Let's suppose that in VCR mode there is a fre-
quency variation of ± 100Hz, this will yield a phase variation of 0.1/16.5, i.e. ± 6ns which, on a 54 cm
wide screen, will produce a horizontal shift of
L1L1NE = ± 0.06 mm !
It is obvious that an excellent image stability is thus obtained.
V. 3.6.2 - Dynamic study The loop response in transient mode is quite important. It determines the overall system stability and the phase' recovery time, which are imposed by the external filter "f(p)". The close-loop transfer Junction is equivalent to a second order system. These time constants are in practice displayed on screen by a bar delivered by a special pattern generator representing the phase errors. The following optimized results were obtained from filter f(p) connected to pin 22. Filter component values are: R1 = 4.7kQ, C1 = 2.2/lF, C = 10nF
1 - - - - - + 411S - -
,.- ""'1 ~____~_--------- N
"'......
n
Normal mode Long time constant
VCR mode Short time constant
91 AN2028/29-29
Where: N : number of lines required for phase correction n : number of lines required for the horizontal oscillator to fully stabilize
-20-/5-5------------------------~~~~©~y~~~~ ---------------------------
1114
APPLICATION NOTE
a. Long time constant · At 6t of 4!ls =; N=18 lines, i.e. 'tLONG = 1.15ms. System oscillations are perfectly damped. Image stability with a noisy video signal is very satisfactory.
b. Short time constant · At 6t = 4!ls =; N = 5 lines, i.e. "CSHORT = 0.32ms · n = 5 lines
One should notice fast phase recovery, naturally
Figure 31
followed by bounced oscillations due to the characteristics of a second order device. As given in application diagram section 6, an other alternative would be to use the following component values :R1 = 3.9kQ, C1 = 4.7!lF, C = 1SnF
V.3.7 - Phase comparator inhibition
The phase comparator is disabled under two conditions : - During frame sync pulse (see figure 30)
Inverted Pulses for Frame Sync.
VidOO ~~l~-r~~~JL/JW~Lx'r~-r-..-'r-"'~
Composite Sync.
FrameSync. (FS)
Frame <t'1 Inhibition (FRI) Frame Blanking
4
y ,I/' L ' - - - - . . . " f -
S Inhibition
':
__ (normal mOd9i7UW?J/1/1/1/1IllTml'nhibilion711/11!11///Tmllh~
'l\ --"~l
n ,-1 ,-1 17~;rbsenceofFramelnhibilion n_,~~~~
Comparator~UI
Current
I 1
'I' 'i ( 'I j' ' r r - U U U I J
I.._J L._
'l\
Inh(ibFiRlioI n+
Si FS)
g
n
al-
-
-
.
J/
l
l
! I
I I
T
/
I
I
I /
I
I I !
lI
I
T
!
Il/
!
1
1/1
1 I
11.1, 1'
-
,,i
'
-
-
-
-
-
-
-
(VCR Mode)
91 AN2028129-30
Inverting the line sync pulse contained within the video signal will provide the frame sync pulses required for the synchronization of vertical scanning.
Since the current supply to comparator tj>1 is controlled by the line sync pulse, the comparator must be inhibited at the time of line sync inversions so as to avoid occurence of phase errors at the beginning of each frame.
This inhibition is activated during FRI (Frame Retrace Inhibition) issued by frame logic circuitry. If tj>1
is locked before the vertical scanning synchronization occurs, (e.g. when switching between channels), and since FRI phase is not yet correctly positioned, the <p1 must be further inhibited by FS signal which is the extracted frame sync pulse.
- During line scanning (see figures 31 and 32)
This inhibition will eliminate the occurrence of all possible phase errors due to a noisy sync signal or parasitics during the line scanning phase. It yields excellent display stability at noisy video signals,
---------,-------- ~ f~;~~~m~~·~2~ - - - - - - - - - - - - - - - 21/55
1115
APPI,..ICATION NOTE
Figure 32
video"')
.
"'""""""-
r
onPin27 ~
0.3 flS: ...-:-~--::-:c:;
line Sync. _ _ _ _-:i-f-...J 2.35: 2.351L.._ _ _ __
'PI Signal
-fls-I-flS
t
! I
Line.'nhibition 1'~~~it(o~r;A 5.8 f1S
6.5 ~s
Figure 33 : <jll Inhibition logic block diagram
Video Reco'gnilion Mute
91AN2028/29·31
VCR
- <jl1 Inhibition in long time constant mode
(VCR = 0)
· S'NH(LONG) = Mute. (FRI + FS + BLK . LlNE,NH) and
· SINH(SHORT) = 1
Inhibition is activated during, frame sync, FRI and each time line trace interval - except at frame beginning between lines 8 and 21. - <jl1 Inhibition in short time constant mode (VCR = 1) · S'NH(SHORT) = Mute. (FRI + FS) = S'NH(LONG) In VCR mode, inhibition is disabled during line trace since phase or frequency variations are not taken into account instantenously.
V.4 - Line saw-tooth generator Before going through a detailed study of the second phase locked loop "<jl2", let's have an overview·of the line saw-tooth generator which has been mainly 'implemented for <jl2 phase variations and also the phase modulation of the switching power supply. It uses the combinqtion of an external capacitor connected to pin 13 and art internally implemented constant current generator to generate a saw-tooth voltage at line frequency. Its frequency is determined by the reset frequency of the capacitor "Cd. This reset signal is issued by
Figure 34
91 AN2028/29·32
U.-r;
,
3.5 VVIp3p 64~
To
'P2andSMPS
'lA/
a [I
[:
I I I I I I I,
I t
I I I I I
-+--t-<
6.Sp.s tRESET
91 AN2028/29·33
the line logic circuitry at a period multiple of VCO period (x32).
· Ic = K . IR = K· 1.26 = 200l-1A
R14
V
le(TH - treset)
13PP =
C13
K x 1.26(TH - treset) 3.48V
R14' C13
VCE(SAT)Tl = 20 mV => V'3(MAX) =.3.5V
In sync mode:
· T H = 641-1s, tRESET = 6.51-1s
· K = 0.527 ± 2 % ·
- - 22/55 - - - - - - - - - - - - - Eii ~~~©I/j~~[~2~· - - - - - - - - - - - - - - -
1116
APPLICATION NOTE
V.5 - Second phase locked loop "G>2"
This stage controls the horizontal deflection of the electron beam i.e., the horizontal picture scanning. The frequency of operation, in the absence of video signal, is a multiple of the VCO frequency, i.e. 15625Hz - 500Hz. When video signal is present, the scanning frequency is synchronized with the video signal through the first phase locked-loop "G>l". The output rectangular waveform signal drives the line switching transistor. This transistor, when turned-off, generates what is commonly called the "line flyback". In order to obtain a horizontally centered picture, the line flyback (LF) must coincide with the blanking time on tube cathodes. The turn-off delay is due to transistor base storage time. This time varies in different TV sets as the transistors employed may have different operating characteristics which are functions of temperature variations, power rating and base drive. Therefore, it follows that in order to obtain stable image centering, the line flyback must be phase-
locked with respect to the video signal. The second phase-locked loop also offers the possibility of horizontal phase-shift adjustment.
Figure 35
Blanking Time
Video
Signal
on Cathodes I
I
Line
I
Yoke
I
Current 0 i="!,~+---7-"""'i"'1'~-'-1_ _
l I
Line Transistor I J Collector Current I
I : ; LI Liin f\:e~~if\!
Flyback l121ls
~ __
9·
T H = 64 IlS
~ 5.~saturation
"li) :5
Turn-off
~~
1~//;,
f- E
I I
~ 15 --H- Turn-off Oelay
~()
91AN2028/29·34
Figure 36 : Second Phase Locked Loop" G>2" Block Diagram
V.5.1 - Duty of different building blocks V.5. 1. 1 - "G>2" Phase comparator This block generates a current proportional to the phase difference between the phase reference "G>2" and the middle of the line flyback to be phaselocked. 11.5.1.2 - Low-pass filter
· Rejects the parasitic component "sum of phases"
· Smoothens the "phase difference" component
· Allow "phase adjustment" by generating an error within the loop
11.5.1.3 - Phase modulator
Uses the line saw-tooth voltage to convert the voltage delivered by the low-pass filter into a phase corresponding to the line transistor turn-off control signal.
---------------- ~ ~~~@m~j~(~9c~ --------------2-3/5-5
1117
APPLICATION NOTE
\/.S. 1.4 - Flip-flop Generates the turn-off control signal for a constant time (fixed by the external capacitor), the phase of which is set by the modulator. V.5.1.S - Output stage
'. Delivers the control signal for line transistor driver
· Disables the output during start-up and protection phases
\/.S. 1.6 - Line deflection stage · Generates the saw-tooth current for line yoke · Generates the high voltage required by picture tube and other supply voltages
The line flyback information is provided by the EHT transformer V.5.2 - Operation of building blocks To provide an easier understanding of the subject, the "$2" loop study will be covered as a function of various time intervals and not as a function of phase. \/.S.2.1 - Phase comparator "$2" The operation is identical to that of "$1" loop.
Figure 37
- - - - - - . - - Vee
+ - -__ Filler F(p)
At : I = 550 IlA and TH= 64 IlS "A" will remain constant since "I" is a multiple of "IREF" current on pin 14. Figure 38
~deoon Cathodes
91 AN2028/29-37
\/.S.2.2 - Low-pass filter f(p) The horizontal phase-shift adjustment is taken into account: Figure 39
91 AN2028/29-36
The V~2 signal issued by logic block is phased with respect to the middle of line sync pulse on pin 27 and delayed by a 2.6 Ils interval so as to be at the middle of blanking time on video cathodes.
The output current c'ompoRent "2fH" is rejected by the low-pass filter.
- The average current is i = 21~:
Where: t,t = tiN - tOUT - The conversion gain is therefore:
i, 21 A='M=TH= 17IlAiIlS
'P2 Comparator
+-----
Vee
Horizontal p
R
Phase
Adjust
r---------
I Phase Modulator
I
t !RIN
V I
liN
- IL _____'_" _ _
91 AN2028/29-38
--- 24/55 ------------,- ~ ~~~©~~:cfi!~~· ---------------
1118
- Filter V : f(i) transfer characteristic is given as :
V: Zi + ~ . K· Vee - Z . liN
Where:
·
Z:
1 RINIIRII--
C·p
· RIN, liN : modulator input characteristics
In Dynamic Mode
-
V:
Zi
=}
f(p)
=
V -;-:
Z(p):R-' -
I
1 +1:p
Where:
· R': RIN II R (R» Potentiometer P)
· 1:: R' . C : Filter time constant /
The network behaves as a first order low-pass filter
whose cut-off frequency at -3 dB is :
1 L3d8 : 21tR'C
Filter component values - R: 470kQ and C : 22nF
· In practice, (K E [0,1]) Vec : 12 V - RIN : 25MQ , liN: 0.65JlA (base input current) F-3db : 15.7 Hz with adjustment and 0.3Hz without adjustment
\1.5.2.3 - Phase modulator This is built around a comparator which converts the filter voltage to a rectangular waveform such that its rising edge phase, variable as a function of filter voltage "V", will trigger the line transistor turnoff control circuitry. The conversion gain is determined by the slope of the line saw-tooth applied to comparator.
Figure 40
91AN2028/29·39
APPLICATION NOTE
Figure 41
V13(tl 3.5 V -
V - ----------------
11 H>--_..;:12c-=_f.c.(V_'_-->.._. ,
I I
V'OUT '-::--:--------T:..--H---=--=--=-1-->-
V<jl2I1INL.(~~2)-----'
,
I
I~I
I'OUT A
! tOUT
91AN2028/29·40
- Transfer characteristic is given by :
Llt'OUT: Llt13 : B: 16.4JlslV LlV LlV13
therefore t2 : B. V Let's consider the delay interval between "tOUT" and the reference time "tiN" where tOUT is the middle of line flyback :
· tOUT - tiN: t2 + td + t1 - tH Where: · t1 : 4.3Jls (Reset for V13 and V$2 are signals coming from line logic block and are synchronized on line sync.) · td : 2 to 15Jls (Delay between leading edge of output signal - pin 10 - and the middle of line flyback)
· tH: 64Jls · tOUT - tiN: B.V + td - 59.7Jls
\1.5.2.4 - Line fJip-flop(TEA202B only for TEA2029 refer to Section VII. 6) It generates a constant duration rectangular signal used to turn-off the line transistor. It is triggered by the rising-edge of the phase comparator output voltage and reset after capacitor on pin 1 is charged.
--------------------------- ~~[~~~~~f~~~ ------------------------2-5-/5-5
1119
APPLICATION NOTE
a. Block diagram "V'OUT" will set the flip-flop thereby allowing the capacitor "C1" to be charged by current "Ic" delivered through current generator. The voltage across capacitor begins rising until it reaches "VREF". At this time, comparator "C" is triggered, the output of which will in turn reset the flip-flop. The capacitor "C" is consequently discharged by current ID - Ic.
Figure 42
16 ~s Wi~
V'ouT---!L-
A
I'OUT
,t'OUT
~
Q 1--_....jT,;;.10 to
V10 Output Stage
91 AN2028/29·41
b. T1 0 Calculation
T10 = C1 . tN1 C1· VREF
Ie
Ie
"Ie" is a fraction of "IREF" on pin 14
Ie = IREF = VREF = 1441lA ex ex· R14
no ~ = ex· R14· C1 = 2.64 x R14x C1
· R14=3.32kQ~T10=29 s
· C1 = 3.3nF
11
T10 is independent from temperature and
Vee
ex has a maximum dispersion of ± 3% from
device to device
Figure 43
1S~
Set -A----r1--
I _ Window
~ _l1l1e
~
~L- Auto-set 1 I
,
I
V'OUT-+-!l---------J
1--1-\-- I 11
I 1I
V1
I :
(1.26 V)
----1--- .......
I I
t
r I Vref
: I; I : : t
: II I
i~'
1
I
~
V10~L..-...-t L -
1I 1, II 1,
~ !MaXimum
~ , '
Phase Variation
I I T10
16 ~s -I--t-
91 AN2028/29.42
c. 161ls Window This window is generated by .the line logic circuitry and sets the maximum phase variations of the output signal "VlO". Also, for protection purposes, should "VIS" voltage equal "0", the output signal will be always present and have a maximum phase shift of 161ls with respect to the falling-edge of the line saw-tooth.
d. Auto-set to "1" To provide protection, this function will trigger the flip-flop if the modulator is disabled, i.e. V16> VI3(MAX) ...
e. Maximum "Tl0" value as a function of "C1"
T10(MIN) : 16Ils(window) + 4lls(auto set) = 20llS
~ Cl(MIN) = 2.3 nF
T10(MAX)
:
for
Cl . VREF Id _ Ie
+
Cl. VREF Ie
s;
641ls
~ TlO(MAX) = 40llS ~C1(MAX) = 4.6 nF For normal operation, C1 value has to be chosen between 2.3nF and 4.6nF. If pin 1 is grounded, output signal (pin 10) is inhibited and goes high.
_26_/5_5_ _ _ _ _ _ _ _ _ _ _ ~ SGS-mOMSON _--'-_ _ _ _ _ _ _ _ __
'".,L [i:j]nIi:OO@~~~©"iiOOw.'Il~~
1120
APPLICATION NOTE
V.5.2.S - Line output stage & inhibitions Figure 44
Line Flyback
Input
TlO OutPUI~
To line "Driver"
Logic 1 for Security
at pin 28
91 AN2028/29-43
· Open-collector output V10(SAT) < 1.5V at
i10(MAX) = 20mA
The line output (pin 10) will go high if either the following three inhibitions is activated:
a. Inhibition at start-up This is generated by a hysteresis comparator which is driven by "KVcc" and the "1.26V" reference voltage. This inhibition is mandatory since the device will operate only at Vcc ::: 5 V.
Figure 45
z
,Q=~ !::~
m <D
i: -; 1
~~d-5> 0
. VHYST = 0.5 V
:;
5.5. 6
SUPPLY VOLTAGE (V)
b. Inhibition during line flyback
The output signal pin 10 is high during line transistor turn-off. The leading edge of output signal pin 10 turns off the line transistor after a delay interval (storage time).
The line transistor turn-off generates an overvoltage on the collector corresponding to the line fly-
back pulse. During this interval, in order to avoid transistor destruction, the pin 10 output must absolutely remain high.
This is done internally with the line flyback pulse (pin 12), which forces pin 10 output to high level during the line flyback time.
c. Safety inhibition The device has a security input terminal "pin 28". If a signal lower than VREF (1.26V) is applied to this pin, line and power supply outputs are all inhibited.
This function is particularly useful for TV chassis protection. Referto section V. 7.5 for further details.
V.S.2.6 - Line deflection stage This chapter will cover a general description of the "horizontal deflection stage" employed almost commonly in all recent TV sets.
Deflection of electron beam is proportional to the intensity of magnetic field induced by the line yoke. This yoke is equivalent to an inductor. The deflection is therefore proportional to the current through inductor.
In order to obtain a linear deflection from left to right as a function of time, a saw-tooth current must be generated within the yoke. The approach is to apply a switched DC voltage to the line yoke.
- When K is closed:
E
ryt
iL(t) = - (1 - e - L)
ry
- 1:: is always higher than half of trace time:
ry
ttrace = TH - tLF = 64 - 12 = 26/1s
2
2
2
Figure 46
Deflection Yoke Resistance
iL(t) ry
Deflection Yoke Inductance (L)
91AN2028/29-45
------------------------------ ~ ~~~@~R~~~~~ ---------------------------2-7/-5-5
1121
APPLICATION NOTE
- "iL" variations as a function of ti me :
L) CdiLit
=LE
e
_I}'t L
~
L E
( for
t
«
fy
The current will therefore be linear as a function
of time iL(t) = ~ . t from "t1" to "12" which is the
L second portion of the line trace interval.
- Current at the end of trace: 1M = LE .-tTR2AC-E
- Energy stored within inductor: W = ~ . L· I~
If the switch is opened at t = t2, the "L.C" combination will enter into oscillation, the energy stored within inductor is transfered to the capacitor, which will return it to the inductor and so on.
The circuit period is classically given by : T=21t·~
If "K" is closed at time ''13'', the inductor will once
again have a voltage "E" across its terminals. The current falls linearly until "t4". This phase corresponds to the first half of line trace interval.
The overvoltage across C is :
V -
p-
E
2 ttra~ ce +
E
during tLF = 1t~
Th at
· .
IS.
V =
P
E
!TRACE· 2tLF
1t
+
E
In practice, E is higher than 100V.
- tTRACE = 52~s =} Vp ::>: 780V - t LF = 12~s
Note that this overvoltage is almost 8 times higher than the source voltage "E". This overvoltage is applied to the primary winding of a "step-up transformer" (EHT Transformer) in order to generate the high voltage required by picture tube anode.
In practice, the power switch "K" is built by a combination of "High Voltage Switching Transistor" and "Fast Recovery Diode".
Figure 47
Endaf Trace
if K remains
/
open
,"'-,
I
,
O~------~~~~/--~\~~~-
i~ o~-----+--~----~~-
ic
Vc
Vp
,-,
I
\
E
__ -1.'__"-
O+-------~--~--~/---\~~
\
I
-, I
V V~o~--; tLF ,-, ~
91 AN2028/29-46
-28-/5-5------------------------ ~ ~ii@m?:m:~~ --------------------------
1122
APPLICATION NOTE
Figure 48 : Simplified diagram of the horizontal deflection stage
EHT
E TRANSFORMER ~ VEHT(anode)
"'\J (Rc"".dby SMPS) +
~ ~
1" " ""I
~~ _ _ _ _ .M..IlLocolianeous Powe, Supplies
+12V
IT,
Line Flyback
LINE
(pm 12. TEA2028)
o
r--.Y-'2~~, Iy
ID
INPUT
If considered in average value, it is seen that the voltage across capacitor "CS" is almost equal to the source voltage "E". The saw-tooth current through this capacitor will produce a parabolic ripple around "E", which will thus modify the equivalent source of the line yoke and induce a modified current of "S" shape within the yoke. This "S" current is used to produce a linear picture as a function of the picture tube geometry.
The basic arrangement can be reconstructed by assuming that the equivalent inductor "L" is the transformer "Lp" and line yoke inductors put in parallel (since VC S(AV) = E).
The output pin 10 of TEA2028 is applied to a matching stage called "line driver" the output of which drives the power transistor "T". The matching stage is necessary for optimized base drive.
At middle of trace, the transistor enters into saturation and its current rises linearly. V1 0 will then issue a control signal to turn the transistor off. The transistor will be in fact turned-off after a delay interval "ts" (storage time) varying from 2 to 8)ls depending on application. The system will then enter into oscillation during its half-period thereby generating the line flyback. At the end of flyback time, the line yoke current is negative while the voltage across capacitor "C" has fallen to zero. The energy transfer automatically takes place by the recovery diode during the first portion of trace time.
91 AN2028/29-47
Also, it is clear that the line scanning phase with respect to video signal is determined by the risingedge of pin 10 output signal.
High level duration (T10) of pin 10 output signal
Figure 49
S Correction
IY~\--
o
Tr c
At..
0IfilIDJY
,
I
I
I
---~_i veEl
I
I
(T: -t.___",O_--L.i
._. I
t 1:: 12Jls r 12V r-i'f--::----,
Vl~ +__-1-+:_2_T9l.0:..JlS_~____
, I
.. t
, ,
I
IT,
I -\--J.- Is I : (tum-off delay)
o
, ,
,,,II
I I
:-I-l------u~I.Ll.LLLcW.:l.h--.-... t
----------------- ~~~~~~g~:g~ ----------------- 29/55
1123
APPLICATION NOTE
must be higher than the delay interval "tS(MAX)" +
the flyback time (Le. 8 + 12 = 20lJ.s) and must
turn-off before the end of diode conduction:
T10
<
ts(MIN)
+
tLF
+
tTRACE -2-
='>
<
40IJ.s
In practice, one will select the pin 1 capacitor C1 = 3.3nF to yield T1 0 = 291J.s.
V.5.3 - Characteristics of loop "<\1z"
The function to calculate is a time with respect to the origin time set by "V$Z". In fact, it is an easy task to inter-relate the horizontal displacement (in mm) to a time interval specified in IJ.s. For a large screen width of 540 mm, the horizontal scanning time :64 - 12 = 521J.s, which corresponds
to : = 10mm/lJ.s.
Figure 50
,
LFA,
tOUT
91 AN2028/29·49
· i = A . (tiN -tOUT)
(1 )
·
V =
Z
.
i
+
~.
R
K·
Vce -
Z
. liN
(2)
· tOUT - tiN = B . V + td - 59.71J.S
(3)
· Z =R-' 1 + 'tP
· R' = RIN II R
· A= 17IJ.NIJ.s
· 't= R'C
· B = 16.4lJ.slV The open-loop dynamic gain is :
ABR' · T=ABf(p)=ABZ=--
(4)
1 +'tp
The system exhibits the characteristics inherent to
a first order circuit and is therefore stable.
combining equations (1), (2), (3) and (4), the tOUT
delay is found as follows:
Z
BZhN to - 59.71J.s BA . KVee
tOUT = tiN - 1 + T + 1 + T + 1 + T
~~_t_
Dynamic Error
Error term
gain term due
= 1
to the
due to delay
input
current
"hN"
t
Error term due to phase
shift adjustment (if applicable)
It is therefore clear that the second phase-locked loop does not cause any dynamic delay. This can be explained by the fact that the phase modulator responds instanenously to all variations of "<\1z".
V.5.3.1 - Study of the Static Error tiN = 0 (phase of V$z) is taken as timing reference. The equivalent impedance of F(p) filter is :
· R' = 460kQ (R II RIN) : if an adjustment is applied to pin 16, or
· Modulator input resistance RIN = 25MQ : without adjustment
a. Phase shift error in case of no adjustment Equation (5) becomes: T _ BRINIIN to - 59.71J.S
OUT - 1 + T1 + 1 +T1
with: T1 = ABRIN Where:
· RIN = 25MQ · liN = 0.65mA · td = 10lJ.s · T1 = 6.8 x 103 = 76dB
tOUT = - 46ns } which
corresponds to a picture shift of 0.46 mm!
The error is quite negligible and thanks to rather
high open-loop gain, the display accuracy with respect to the phase set by "<\12", is very satisfactory.
b. Study of shift adjustment With R, P network connected to pin 16, the tout becomes:
R'
- BR'liN to - 59.71J.s BR · KVee
tOUT=~+1 +T2 + 1 +T2
With: T2 = ABR' (where R' = R II RIN) andKE [0;1]
Substituting the following values into above equation:
· R = 470kn · R' = 470kQII 25MQ = 461kn · A = 17x1 O·s NlJ.s
· B = 16IJ.sIV ·td=10lJ.s ·T2=125 · Vee = 12V
tOUT = - 38ns - 390ns + 1.5lJ.sxK
therefore tout = 1.5xK - 0.43 ( in IJ.s ) If K varies between 0 and 1 ~ tout [- 0.43ms to 1.07IJ.s] which corresponds to a picture displacement of : L1L1NE [- 4mm to + 11 mm].
-30-/5-5------------------------~~~~~~2~~~~~~ ---------------------------
1124
APPLICATION NOTE
Shift variations as a function of Vee (with adjustment)
dtout BFR-'· K BRR'· K K
dVee = 1 + T2 ~ ~ ~ AR
1d~~c = KxO.12J.lSIV
= 0.34mmlV
at KNOMINAL = 0.28
Therefore, a constant Vee must be applied to the potentiometer.
variations of a coil mounted on the picture tube.
A saw-tooth current at frame frequency will go through this coil commonly called "frame yoke". Frame period is the time required for the entire screen to be scanned vertically.
C.C.I.R. and N.T.S.C. TV standards require respectively 50Hz and 60Hz Frame Scanning Frequencies. Also, a full screen display is obtained by two successive vertical scannings such that the second scanning is delayed by a half line period with respect to the first.
V.6 - Vertical deflection driver stage
This stage must constantly drive the vertical spot deflection. Such deflection will horizontally scan the screen from top to bottom thus generating the displayed image. Similar to horizontal deflection, the vertical deflection is obtained by magnetic field
This method increases the number of images per
second (50 half imagesls or 50 framesls in 50 Hz standard). This scanning mode called "Interlaced Scanning" eliminates the fliker which would have been otherwise produced by scanning 25 entire images per second.
Figure 51 : Block Diagram of the Vertical Deflection Stage
H/2
rTopol Pictu((]
Frame Saw-tooth
"'''' '" [\, ... t LBottomof
,
Picture
I
lFRAME
1 YOKE
The circuit will generate a saw-tooth voltage which is linear as a function of time and called "frame saw-tooth". A power amplifier will deliver to the "frame yoke" a current proportional to this sawtooth Voltage. It is thus clear that this saw-tooth voltage reflects the function of the vertical spot deflection; which must itself be synchronized with the video signal. Synchronization signals are obtained from an extraction stage which will extract the useful signal during line pulse inversion of the composite sync signal.
Synchronization occurs at the end of scanning, in other words, when the saw-tooth voltage at pin 5 is reset. This function is accomplished by the "frame logic circuitry" of full digital implementation.
This processing method offers various advantages:
- Accurate free-running scanning frequency
91 AN2028f29-50
eliminates the frequency adjustment required by previous devices. - Digital synchronization locked onto half line frequency thereby yielding perfect interlaced display and excellent stability with noisy video signal.
- Automatic 50/60 Hz standard recognition and switching the corresponding display amplitude.
- Optimized synchronization in VCR mode.
- Generation of various accurate time intervals, such as narrow "sync windows" thus reducing considerably the vertical image instability in case of for instance, mains interference, superimposed on frame sync pulse.
- Generation of vertical blanking signal for spot flyback and to protect the picture tube in case of scanning failure.
- - - - - - - - - - - - - - - ~ ~~~.Dm~,~C~~?c~ - - - - - - - - - - - - - - - 31/55
1125
APPLICATION NOTE
V.6.1 - Frame sync extraction The main duty of this stage is to extract the frame sync pulses contained in composite sync signal. Figure 52 : Sync extractor block diagram
5.6V
Frame
~c
Two current generators are used to charge and discharge the integrated capacitor "C". The discharge generator (Ie + 10) is driven by the composite sync signal.
The t:,.Ve across capacitor is: _ 10 . ~YNe
During frame trace, the capacitor is discharged at each line sync pulse thereby generating a t:,.V of -0.94V with respect to 5.6V and then recovers the charge by current "Ie". The comparator output remains low.
V.6.2 - Frame saw-tooth generator Figure 53
FR~;;:O~;;L~;l
+
I
, , I
60Hz.. I
T
--+I,I
Frame
__7~_:)t__ ..J --'L
· 'c=2~ { · 'c+ID=9~
· C=35pF
91AN2028/29·51
The discharge time is 27!!s at the first line sync inversion applied to comparator input. The voltage "Vc" then falls from 5.6V to 0.2V and triggers the comparator "Co" which will deliver a frame sync pulse when "Ve" crosses the 2.8V level. The overall arrangement behaves as an integrator and will therefore suppress any noise susceptible to be present on input signal. An external capacitor pin 20 can be added to the integrated capacitor C to increase the frame sync time constant.
+
+E (200V)
+ - - _ Frame Saw-tooth
Output
The frame saw-tooth is generated by an external RC network on pin 5. The time constant "R5 x C5" is much higher than the frame period. Therefore, the generated saw-
91 AN2028/29-52
tooth is quite linear. The',network is discharged by an internal transistor, controlled by the frame logic block.
1126
Figure 54
APPLICATION NOTE ~v - - - - - - - - - - - - - - - - - - -
1.26V (VREF)
--I
I
I
I
I I
1
1~~1
1
~
20ms (50Hz)
I
II-·~---="'-'-'----'.----·II
91 AN2028/29-53
V.6.2.1 - 60Hz STANDARD SWITCHING
The NTSC standard requires a vertical picture scanning frequency of 60Hz, i.e. a saw-tooth period of 16.66ms.
In order to obtain an identical deflection amplitude whatever the standard (50 or 60Hz), the saw-tooth amplitude for both periods must be the same.
60Hz standard recognition is performed automatically by the frame logic block, which will issue a signal to drive a current generator ."£>160". This current will be summed with the external charge current and will increase the saw-tooth slope, so as to yield same saw-tooth amplitude to that set in 50Hz standard. This current is centered around 14/1A and is a fraction of IREF applied to pin 14.
Employing the recommended component values for network can nected to pin 5, this current will result in identical amplitude in both standards.
eNs
= -160 -x T-60
= -150 -X T-so
=0>
160
= 150
X
60
-
= 1.2
X
150
Cs
Cs
50
150 =~ = 200V = 74~A => 160 = 88~A
Rs 2.7MQ
therefore £\160 = 14~A
V.6.3 - Functions of frame logic block
This section is fully implemented by 12L logic gates. It is clocked by an accurate "H/2" clock running at
half line period (32/1s). The required periods and time intervals are obtained by counting the clock pulses. For the sake of clarity, timing signals so obtai ned are labeled by the line number corresponding to video signal.
The time corresponding to "x" scanned lines with respect to the beginning of frame saw-tooth (RESET) is therefore:
Ix = 64/ls (x - 1) + 32/1s
Figure 55
SY~
I~I__~_'_I~
I [
RESET (Counte:) -32-11-S---':'-----
I
HI2~
-:Lt ~t
Frame
Saw-Ioolh
(pin 3
I
I
LX
I I
t
IX 1.<--[
)/ - J
I
--------------- ~~~~~~~m!g~ --------------- 33/55
1127
APPLICATION NOTE
Figure 56 : Block Diagram
..rt..
Frame Blanking
FRllnhlbltlon
(~1)
BINARY DIVIDERS
HI2 (3~5)--i I--I--I-H+++H-Reset
t--- -------- -I
(11
010
Jl..n... 64115
.J"""I....J 32.768ms
50!60Hz
\/.6.3.1 - 50160 Hz Standard recognition This function is performed by two shift registers which are loaded by sync pulses (if present) and if these pulses fall within the time interval specific to each standard. These intervals are called "Register Windows"and labeled "WR(50)" and WR(60).
Figure 57
L247
L2Tl
1309 L315
I
I
I I
_ _ _-1' WR(60Hz) I!-_ _...J~!--_ __
I 15.773ms
17.696ms 19.744ms 12o:128ms
I
I
60Hz
j
s y n c - - -1-6. 66m !-' ...J. -5-
I '
50Hz
,
Sync --2-!Omi-S- - -
91 AN2028129·56
a. 50 Hz Standard Recognition
This identification is considered valid if two sucessive sync pulses applied to 50 Hz shift register fall within the 50Hz window "WR(50)". At the time of synchronization capture, the first pulse will reset the counters. The second pulse, if present, will then trigger the 50Hz identification 20ms later
[10(50) = 1].
The identification is not valid if two sucessive 50Hz pulses are not detected. Identification signal is also used to reduce the vertical synchronization window in 50Hz standard thereby offering excellent noise immunity against noise susceptible to be present in sync signal and hence good display stabilitx.
b. - 60 Hz Standard Recognition
This identification is validated after three sucessive sync pulses at 16.6~s period have been detected. Three pulses are necessary to ascertain the identification prior to switching the saw-tooth amplitude. The identification signal [10(60) = 1] is also used to reduce the synchronization window and, in case of one or two missing pulses close to 60Hz, to set the free-running frequency.
\/.6.3.2. - Vertical synchronization window - Freerunning period
In the absence of sync pulse various free-running periods are specified. Since vertical scanning must be always active, these free-running periods must be higher than those of 50 and 60Hz standards so as to ensure synchronization. An other window, allowing synchronization only at the end of scanning, is also necessary. Upon syn-
1128
APPLICATION NOTE
chronization, this window will allow vertical flyback only at the bottom of screen. This window should be narrow for good noise immunity but also wide enough to yield, upon synchronization, a capture time unperceptible on screen.
In our case, as long as no standard identification takes place the window will remain wide, and once one of the standards has been identified, the window will be considerably reduced.
In VCR mode, this window will be always wide since
frame frequencies delivered in high-speed search, slow review and picture pause modes are very much variable and must be taken into consideration.
In the absence of transmission (Mute = 0), synchronization is disabled (so as to avoid incorrect synchronization due to noise) and the free-running frequency is around 50Hz. This will eliminate the occurrence of picture overlay at the end of trace at a lower free-running frequency.
Figure 58 : Definition of Synchronization Windows and Free-running Periods
No Transmission
(Mute =OJ
Muled
1050 =a , lOGO =a
or
VCR Mode
Mute =1
loso = 1
5QHz Standard
L247 Register's ,
l2n
+
t t L309 L315
L.361
+
W~~~>~~__~~~____~:~_
1
I
I:
I
WR_=_O__~!______T!______i~~!_____ :
I
I
Free-running Period
Reset
1
L I
: : 'i
I:
: I I
WR(WIDE)
r~I /.../....//////...Ir. ////////;//,/II //II ////II/~~
Reset
1
1:
i
1 ,
WR(50)
I
1, ,I
,
I
~~_________
,
I
Res_e_t____7:____~~------~i~---------
IDSO = 1
W~~_ _ _ _ _ _~_ _ _ _ _ _ _ _ _ __
60Hz Standard
Reset
L----------l.----------------~----'91AN2028/29-57
Maximum capture time
The worst case capture time occurs when the first sync pulse just precedes the sync window.
Let's find the number of periods necessary for the capture to occur, i.e. tn = O.
TL-Tw
=>n=T T
,TL=23ms, Tw=7.3ms
L - SYNC
· 50Hz: the number of periods is 6 => TCAPTURE(MAX) = 120ms
· 60Hz: the number of periods is 3 => TCAPTURE(MAX) = 50ms
Figure 59
Wide
_ _T L _ _
Window
s Frama e w.t~~ I ~w
Sync Pulses
I I
I
,iI I=I -:t1-=IJ:=I-:t=2 I
:~
o
,
I,·
I
I
I~
tN=O (capture)
91 AN2028129·58
________________ _________-L_______ ~ ~~~@~g~:~~~
35/55
1129
APPLICATION NOTE
V.6.3.3 - Frame blanking signal This signal is necessay to blank the display during each frame fly back. It is triggered at the beginning
Figure 60
of frame saw-tooth flyback. The duration of this signal is 1.344 ms (or 21 lines).
FlrstFrame TI.JLJLILJLIIfl~
I
1
:
1
,,, l u~ Second Frame
U
LJLJnULnJLnJUn,-U,,
-U,,-U,,
-, U
,-
-
,Url'i-U...:.
-U-
;U- U- U.wt
:
1
I
I
I
1
I
I
--lI
Frame Blanking
,,'
I
I
(pin 4)
I ...
1.344ms
.. :
(21 lines)"
:
· 24 lines for TEA 2029
11I \ 'jLL22
r\
---11~~
:. I I 12llS
ff\ I 20llS I I
L335
I I~---
91 AN2028/29-59
This "frame blanking" signal is available through pin 4 (TEA2028 only) which is an open-collector output. It is also present within the normalized super sandcastle signal on pin 11 (TEA2028 and TEA2029).
V.6.3.4. - Frame blanking safety (TEA2028 only, for TEA2029 refer to section VII.S)
Figure 61 : Block diagram
Its duty is to protect the phosphor coating of picture tube in case of any problem with vertical deflection function such as scanning failure.
A signal to monitor correct scanning is provided by the frame yoke and applied to pin 2.
In case of any failure, all frame blanking outputs are disabled and go high thereby blanking the entire screen.
12
FY~~~I~ 10DkQ
2 j-t::1--<f--1
[~
1.26v
Frame Blanking (no safety)
o--I-'i--''i--lc_--V2
-70""
, t
J : I I
V2 (1.26V)
-
-
"
-""-rf
_
:
-
-
-
:
Frame Yoke
..y:~"""'J
Current
91AN2028/29-60
During trace phase, the voltage across frame yoke has a parabolical shape due to the coupling capac-
itor in series with yoke. During frame flyback, the current through frame yoke must be rapidly in-
1130
APPLICATION NOTE
verted. Conventionally, a two-fold higher supply voltage is applied across the yoke. This will produce an overvoltage called "flyback". The safety monitoring status is detected on the falling-edge of flyback, i.e. at the beginning of scanning. A difierentiator network is used to transmit only fast voltage variations. The required pulse is then compared to 1.26 V level. Frame blanking goes high in the absence of negative pulse (zero deflection current) or if the pulse does not fall within the first 21 lines (exagerated over-scanning).
V.7 -Switching power supply driver stage Switching takes place on the primary side (mains side) of a transformer by using TEA2164 SMPS
V.7.1 - Power supply block diagram
Figure 62
Controller manufactured by SGS-THOMSON Microelectrics. Required voltage values are obtained by rectifying different voltage outputs delivered through secondary windings. The horizontal deflection stage is powered by one of these outputs delivering around hundred volts.
This voltage source must be regulated since any voltage fluctuation will yield variations of the horizontal display amplitude.
The TEA2028 monitors this voltage and transmits the regulation signal to the primary controller circuitry via a small pulse transformer. The characteristics of this regulation signal are directly related to the conduction period of switching transistor.
LIne Deflection
Stage
TEA 2028
91AN2028/29-61
------------------------------ ~ ~~~@~~~~~~ ---------------------------37-/-5-5
1131
APPLICATION NOTE
V.7.2 - General operating principles
A fraction of the 135V output voltage to be regu~ lated is compared to the 1.26V reference voltage. Resulting error signal is amplified and then applied to phase modulator ,"M1", which will deliver a square waveform at line frequency whose duty cycle depends on the value of input voltage "V9".
A second phase modulator "M2" will determine the conduction period as a function of voltage on
pin 15. This function is mandatory for system startup.
A 2811S window is used to limit the conduction period of the primary-connected transistor.
Supply output (pin 7) and line output (pin 10) will be disabled if any information indicating abnormal operation is applied to safety input (pin 28). Consequently, all power stages are disabled and the TV set is thus protected.
V.7.3 - Electrical characteristics of the internal regulation loop Figure 63
The phase modulator implemented by a simple transistor "T1" will compare in current mode, the image of amplified input (h) with saw-tooth current (i2) at line frequency. With "i2" rising, as soon as the
sum of "h + i2 - IDc" goes positive, the transistor
enters into saturation thus determining the output conduction period.
A low-pass filter implemented by combination of a
1OOpF capacitor and the input impedance of tran-
sistor "T1", attenuates all frequency variations
higher than the' line frequency.
.
· Input Amplification: dh
A = dVIN = 3.3111YmV
· Modulator conversion gain:
B
dtouT =-d-'-
=
-0.558I1s/I1A
11
91 AN2028/29·62
· Overall gain of the internal loop :
~ dtouT
=
-1
.911S/mV
. 1 x --f
(fa
=
15kHz)
IN
1 + j_
fa
Figure 64 : Conduction period (pin 7) versus Input voltage (pin 9)
tON (pin 7)
281l"
I I I
10/1& --TI -----
I
I i : -jl---ilf-_~~~:--~ VIN (pin 9) 1-:----1-----,.: 9.5mV 5.2mV 91 AN2028/29·63
-38-/5-5-------------------------~~~~@~~~~~~©~ ----------------------------
1132
APPLICATION NOTE
SMPS WAVEFORMS For discontinous mode "f/yback" configuration The primary-connected transistor is turned-off during the line flyback. All interference signals due to switching and susceptible to affect the video signal will not therefore be visible on screen.
Figure 65
V13~
11'2~
LF 28fLS (max)
. V7 ,
PRIMARY PULSES
-t:!IJr,I - ---L -- -y__-__-_-l-y--
~~~~~~~ , ,
SECONDARY : I
RECTIAER DIODE
I,, , CURRENT
,
135V __ 1_ I
! n SECONDARY
U WINDING 0 L
0''.,
VOLTAGE
on~ v
o00 v 0
91 AN2028/29-64
Regulation Characteristics The following characteristics have been measured on a large screen and yield excellent results:
· 135V voltage regulation as a function of mains voltage : better than 0.5% for mains voltage variations of 170VRMS to 270VRMS (P = 60W at 135V)
· 135 V voltage regulation as a function of load: better than 0.5% for a delivered' power of 35W to 120W.
This type of power supply offers the following advantages:
· Overall efficiency enhancement : better than 80%
· Reduction of interferences by synchronization on horizontal frequency
· Full protection of the primary-connected transistor in case of short-circuit or open-load on secondary terminals
· Can provide 1W to 7W, for TV standby mode operation (refer to TEA2164 application note).
V.7A - Power supply soft-start
When the TV set is initially turned on, control pulses are not yet available and consequently the controller block on primary side will impose a low-power transfer to the secondary winding. This power is produced by an intermittent switching mode called "Burst Mode". As soon as the Vcc supply to TEA2028 exceeds 6V level, line and SMPS outputs are enabled. Since the filtering capactitors on secondary side cannot charge up instantaneously, the voltage to be regulated would not yet be at its nominal value. Without conduction period limitation upon start-up, the device will set a maximum cycle of 28/1s which will result in a high current flow through the primary winding and thus through the switching transistor which will in turn activate the protection function implemented on primary side. Consequently, the primary controller block will be inhibited and the set will not turn-on. A start-up system has been implemented within TEA2028 to overcome this problem. This soft start system, will upon initial start-up, use the image of the falling voltage on pin 15 to increase progressively the conduction cycle. The phase modulator "M2" compares this voltage with line saw-tooth voltage and delivers the corresponding limitation cycle. During supply voltage rising cycle [Vce (pin 8) < 6V], the capacitor pin 15 will charge up rapidly while the voltage across it follows Vee. At Vee:::: 6V, the capacitor is discharged via an internal current generator and the voltage across it decays linearly. At V15 ::; 3.5V (line saw-tooth peak-to-peak voltage), phase comparator "M2" delivers a low conduction period which will gradually increase. The conduction period (pin 7) will rise until the secondary voltage reaches the value set by potentiometer "P". When this occurs, the loop is activated.
---------------------------- ~~ii©~~~:~~~~ -------------------------3-9-/5-5
1133
APPLICATION NOTE
Figure 66
tzi:
SUPPLPYIVNOSLTAGE
.
12V--
(V)
6 ---_--.
, I
PIN15
VOLTAGE (V)
t , 13 6 :~. ;;:5 -~~
, ,
I
· ,
5·5V - -I [ ' \
t SMPS CONTROL
OUTPUT VOLTAGE (pin 7)
t OUTPULTINVEOLTAGE
(pin 1 0 ) ' :
' ..:
,
:
~ '~ C; Soft·start area
r I
'"
I
: JlllllnWZRegulated Mode/ZlZlZI)
' !
.,,'
VIII/]//)IIIZZI Active State 7Z1z/ZZ? mJ
· LIne output (pin 10) and thyristor control output (pin 4) for TEA 2029
"'1
.. t .. t ... t
91 AN2028/29·65
The pin 15 discharge current value is 1OOJlA for a duration of 2Jls line frequency.
2 Therefore 10(Av) = 100 x 64 = 3.1 JlA
Figure 67
~h-
1.75 3.5 PIN 15 VOLTAGE
(V)
91 AN2028/29-66
Conduction period limitation voltage (pin 15) TON(LlM) = 56Jls -16 x V15 (in Jls)
V.7.5 - Protection features
As soon as a safety signal (V ~ 1.26 V) is applied to pin 28, line and supply outputs (pins 10 and 7) are both disabled. Capacitor "C15" begins charging
up until the voltage across it reaches 4 V (K x Vcc).
Outputs are again enabled and conduction period gradually increases as it occurs upon initial startup. The device will be definitively inhibited if the cycle of events is repeated 3 times. For the device to restart, the internal 3-bit register should be reset which requires the Vcc to fall below 4 V.
-40-/5-5---------------------------~~~~@~~~~~~~ ------------------------------
1134
APPLICATION NOTE
Figure 68
"P~IN(28';R-----------H---------+Jr---- :::J::
PIN15
I
2
:3
.. 1
~~
:
i
(V) 4 _____ 1..-_
I
3.5 ------~-
kd!,I
PIN 7
.! : VOLT~ AGE'
PIN 10
"
,
I I
i Soft-start area
I
,lit/!!I14!1A " IIflllOI7l1i
1>1
J Active area
1-: Fulllnhlbltlon
VOLTAGE)lmd VlllzzblZZl VlZZIII/OJ .. 1
* Line output (pin 10) and thyristor controt output (pin 4) for TEA 2029
91 AN2028/29-67
Pin 15 charging current: IC(Av) = - IO(AV) =- 3.1!LA
V.7.6 - TV Power supply in standby mode
\I. 7.6.1 - Regulation by primary controller circuit
This mode of regulation called "Burst Mode" is performed only by the primary controller circuit and is activated in the c<).se of missing control pulses or in the absence of power supply to TEA2028. In this mode, power available through secondary winding is limited. Refer to TEA2164 Application Note for further details. Higher powers can be obtained by using the regulation feature offered by TEA2028. In this case, the horizontal output (pin 10) must be disabled.
Figure 69
\1.7.6.2 - Regulation by TEA2028
In this case, all that is required is to disable the line scanning function thus reducing the overall power by 90%.
The device power supply regulation loop remains active, for minimum conduction period to be 1.5 ms the power delivered through secondary must be higher than 3 W.
Line Output Inhibition Two alternatives are possible: - Grounding flip-flop pin 1 - Apply a voltage higher than 3 V to pin 12.
R2 RI
LF Inputlnhlbltlon "" V12> 3V
91 AN2028/29-68
--------------- ~ ~~~wm~~~ru?~~ ______________41_1_55
1135
APPLICATION NOTE
V.S - Miscellaneous functions
v.a.1 - Super sandcastle signal generator
This signal used in video stage, is available on pin 11. It has 3 levels at specified time intervals:
· 2.5 V level Used for vertical blanking at each frame flyback. Its duration is 21 lines and is generated by the frame logic. This level will be maintained if vertical scanning failure is detected on pin 2.
Figure 70
· 4.5V level
Used for horizontal blanking, its du ration is determined by comparing the line flyback signal on pin 12 to an internal voltage of 0.25V.
· 10 V level
This signal is used by color decoding stage. Its duration of 4~s is determined by line logic circuitry. With respect to the video signal on pin 27, this level is positioned such that it is used to sample the burst frequency transmitted just after the sync pulse.
VIDEO SIGNAL (pin 27)
--,,-,---,I
' -_ _ _.;11
-rrII O.3~s 10V I i 4~s I I 4.5V I
SUPER
--Line Blanking· (12I's) _
SAND CASTLE
~
(pin 11) 1------FrameBlanking ( 2 1 I i n e S ) - - - - - _ L -
91 AN2028/29-69
v.a.2 - Video and 50/60Hz standard recognition output
A 3-level signal is available at pin 24 for video identification (Mute) and for 50 and 60Hz standards recognition.
Figure 71
+Vcc
+Vcc
Vccrr--
V24
Vccl2r~
O---i;-J __.
Without Video
160HZ
50Hz
Standard Standard
I
Transmit
- - Identification
91 AN2028/29-70
42/55 ---------------
~
~~~(~~~"I~~Rt;~
1136
V+cc
~
~(I)
ljin
V+GC
'@CIl
~:i!
5.6kQ
Ii
50/60Hz Standard &
Video Identifica.tion
Output
V
Video Input
~
:t>
Z
~''o""
~
.".
~
W
~
CD
':i
--J 01
15kn J
lN4148
I 1<1 T
TEA 20288
V+cc Safety Input
+V EHT
TRANSFORMER
!ltLF
~J
J IL _____
"11
to'
~
e:
(i3
m-I
--J :t>
N oN
N
00
:t> "C "rC('5
~
(5
Z
:o ;
Gl
:0 :t>
is:
1 nF
II-
»
"C
"C
VonicaJ
j'"
Phase Shift
(5
oz~
z
S
m
APPLICATION NOTE
VII - TEA2029 : DIFFERENCES WITH TEA2028
VII.1 - General The TEA2029 has quite the same functions compared to TEA2028.
The main difference is that the TEA2029 incorporates a frame phase modulator intended to work
VI1.2 - Pin by pin differences
Pin number TEA2029C
with a switched mode vertical stage using a thyristor. The TEA2029 can also be used with a linear vertical power amplifier such as the TDA 8170.
TEA2028B
Capacitor for horizontal output duration
1
Differential inputs of the frame error amplifier
adjustment
(including frame blanking safety in case of
(29J.ls typo with c1 = 3.3nF)
vertical stage failure).
2
Vertical blanking safety input
4
Frame output for thyristor control
Vertical blanking output (21 lines duration)
10
Horizontal output (26J.ls typo duration)
Horizontal output (duration is adjustable)
11
Supersandcastle output (with a frame blanking duration of 24 lines)
Supersandcastle output (with a frame blanking duration of 21 lines)
12
Negative horizontal flyback input (115 Vpp through a 47 kQ resistor)
positive horizontal flyback input (1 OVpp through a 47kQ resistor)
20
Positive AGC key pulse output (low level when no video)
Capacitor for frame sync. time constant adjustment
Safety input
Safety input
28
(inhibition of SMPS, Horizontal and Frame
(inhibition of SMPS, Horizontal outputs when
outputs when V28 > 1.26V)
V28 < 1.26V)
-44-/5-5---------------------------~1ii~~~~~~~ ------------------------------
1138
APPLICATION NOTE
VI1.3 - TEA2029C Pin connections
Pin number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Description Frame error amplifier non-inverting input Frame error amplifier inverting input Frame saw-tooth output Frame output (for thyristor control) Frame ramp generator Power Grou nd SMPS control output VCC Supply voltage SMPS regulation input Horizontal output Supersandcastle output Horizontal flyback ioput Horizontal saw-tooth generator Current reference SMPS soft-start and safety time constant <1>2 phase comparator capacitor (and horizontal phase adjustment) VCO phase shift network VCOoutput VCOinput AGC key pulse output Substrate Ground <1>1 phase comparator capacitor VCR switching input Video and 50/60Hz identification output (Mute) Video identification capacitor Horizontal sync detection capacitor (50% of peak to peak sync level) Video input Safety input '
Package: DIP28
~ ~~~(~,m~(~~~~~ - - - - - - - - - - - - - - - - 45/55
1139
APPLICATION NOTE
VII.4 - Frame phase modulator
The Tranconductance Amplifier "A1" converts the differential input voltage into two output currents "ls1" and "ls3".
· A1 transconductance =-ISV1 =1011NmV IN
·
B transconductance
=
IS2 V2
= 4011NV
·
Transfer
characteristic
=
v b.tOUT
b. IN
= 6.411s/mV
The filter time constant is maximum near the oper-
Figure 73
= ating point when IS1 IS2
In this case: · The base current of T1 = "ls2 - IS1" · The filter band-pass = 15kHz
The maximum conduction period of "4011S" is determined by the horizontal logic circuitry.
The frame frame flyback is detected by transistor "T3".
There is no feed-back during frame flyback and "ls3" is maximum (higher than 14) which will drive the "T3" into conduction.
B
r--_--"'Tl
Filter
14
V~I
Horizontal Saw-tooth
~! '--_ _--I V2
3.5V
Safely Frame Logic to
Super Sand Castle
I.F.
641lS
Phase Limitation (Horizontal Logic) Horizontal Flyback
Safely&OnlOff Switching Voltage .
Figure 74
Frame Output
91 AN2028/29·72
VtS
~I
I ! 40~ max
Horizontal Flyback
· Frame Output
,t~,
Horizontal Saw-Iooth
-i-\...
6us
91 AN2028/29· 73
-46-1-55---------------------------~·~~~@Ir~~~:8~' ------------------------------
1140
APPLICATION NOTE
VII.5 - Frame blanking safety
- During trace: IS3 < 14 =; T3 is blocked. - During flyback : IS3 > 14 =; T3 conducts. In the absence of flyback detection or if the flyback interval is longer than the blanking time, the
Figure 75 : Frame Blanking Safety Block Diagram
sandcastle low level remains constant at 2.SV so as to protect the picture tube in the absence of frame scanning.
S From Frame Counters
R
IF BlK' Q
Q BlK'
R
Q
S
Blanking
Output to Super
Sand Castle
if
RESET
91AN2028/29·74
· "IF" signal is delivered by Frame Error Amplifier (see Frame phase modulator figure)
. if is high during the Frame Flyback interval
Figure 76
I
I
~ I f
~r-------'L
f
I I
_+-1---!nL.-f f f
~
------.1
--.-J11--1
24 lines
L-
RESET BLANK'
51 Blanking output
--IL-
I I
I
~
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
f
I
I
I
I
I
f
I
~
~i--------
Normal Operation
Too Long Flyback Pulse (FRI)
91AN2028/29·75
---------------
~
~~~i~m~~(~il~~
47/55
---------------
1141
APPLICATION NOTE
VII.6 - On-chip line flip-flop Figure 77
-----------------------------------------~
161J,sWindow
I
~
A~MAX
LF
I I
I I I I
10 S1. OUTPUT
Figure 78
::J1l7[
I
: I
I
I
:: ::
!:1
Vto
~ I
I
I
I
= A¢MAX 16/-ls
261lS 91 AN2028/29-77
VII.7 - AGe key pulse
Figure 79
91AN2028/29-76
TlO = 35 x Tvco - K· R14 . C13 = 70 x 10--6 - 4R14 . C13
Where Tvco is the Vco period of oscillation on pin 18. - If in synchronized mode: · Tvco = 2~s · R14 = 3.32kQ
· C13 = 3.3nF
ThereforeT10 = 26J..ls (nominal value)
VIDEO SIGNAL (pin 27)
~_ _ _-'II'
S~~~L
fl>~s 12V r-+-'----i-1-~-1,L....-----,J
OV
(pin 20) --'::':"---'
l
1-
Without
Video Signal
91AN2028/29-78
As illustrated below, this signal is used in some TV sets to perform sampling window for Automatic Gain Control of picture demodulation network.
This system is called "clamped" AGC, and locks the demodulated line sync amplitude and hence sets
the video signal amplitude.
This signal generated by line logic circuitry is correctly positioned by the first phase locked loop "<jl1" and includes the line sync pulse of the video signal. This is an open-collector output.
--- 48/55 -------------- ~~~~@~gl~fr9~~ ------------------------
1142
APPLICATION NOTE
VIII - APPLICATION INFORMATION ON FRAME SCANNING IN SWITCHED MODE (TEA2029 ONLY)
VIII.1 - Fundamentals The secondary winding of EHT transformer pro-
vides the energy required by frame yoke.
The frame current modulation is achieved by modulating the horizontal saw-tooth current and subsequent integration by a "L.C" network to reject the horizontal frequency component.
Figure 80 : Block diagram
-------T-E-A--2-0-2-9-------,!
I I I
: I
I
~ TRANSEFHOTRMER ,'::
l 500"H
) vL,~.4c7"F)I _Vo
ITO
Iy
FRAME YOKE (90')
N
______________________ J
VII1.2 - General description
The basic circuit is the phase comparator "C1" which compares the horizontal saw-tooth and the output voltage of Error Amplifier "A". The comparator output will go "high" when the horizontal saw-tooth voltage is higher than the "A" output Voltage. Thus, the pi n 4 output signal is switched in synchronization with the horizontal frequency and the duty cycle is modulated at frame frequency. A driver stage delivers the current required by the external power switch. The external thyristor provides for energy transfer between transformer and frame yoke. The thyristor will conduct during the last portion of horizontal trace phase and for half of the horizontal retrace. The inverse parallel-connected diode "D" conducts
Frame Reference Saw-tCOlh
Vl
I :r: +24V
OOCO~F)I
91 AN2028/29-79
during the second portion of horizontal retrace and at the beginning of horizontal trace phase. Main advantages of this system are:
· Power thyristor soft "turn-on" Once the thyristor has been triggered, the current gradually rises from 0 to IP, where IP will reach the maximum value at the end of horizontal trace. The slope current is determined by, the current available through the secondary winding, the yoke impedance and the "L.C." filter characteristics.
· Power thyristor soft "turn-off" · The secondary output current begins decreas-
ing and falls to 0 at the middle of retrace. The thyristor is thus automatically "turned-off". · Excellent efficiency of power stage due to very low "turn-on" and "turn-off" switching losses.
------------------------------~ ~~~;~~~:~~t~ ---------------------------4-9-/5-5
1143
APPLICATION NOTE
VIII.3 - Typical frame modulator and frame output waveforms Figure 81
Fra~:w~~~:~nce -.71-----------.--;1:1_C--_-----
/1 /I
IL y----t7f---L L/ !: -------- ~/ Horizontal
Saw·tooth
1
I
n J i - II II
I I
' L
Ga~;'~:~al ~---------
~----------~ : I
Horizontal
: I
Ryback
I 1
I
I
, :
r
I
I I
I
I
I I
I
I
I I
I
I
{ITHYRIST~ ~ /I' . ITO
---/·v V IDIODE ----V
r-.. ______ / \ .
! f
V
Beginning of Frame Trace
End of Frame Trace
VIII.4 - Frame power stage waveforms
Figure 82
sov I--
J-- 5m,
~hHYRISTOR r '
0
1010DE
'TO 5ms/div
'THYRISTOR }
o
Iro 1A/div
1010DE
-II···
~ III 1--
VFLYBACK
vc
26V
Figure 84
91 AN2028/29-80
10/ls!diV 1Ndiv
lTD current at the end
of scanning (toN(MAX)l
10V/div
ov
VGK Voltage
Figure 83
91 AN2028/29-81
91 AN2028/29-83
Figure 85 : Different horizontal conducting times during frame .
10/ls!dlv 1A!div
lTD current at the beginning of scanning
(IONIMIN))
1 Dv/div
VaK Voftage
91 AN2028/29-82
10)!sidiv 1A1div OA
v"
10V/div
91 AN2028/29-84
1144
Figure 86
Figure 87
APPLICATION NOTE
100llsJdiV 1A1div
j ITHYRISTOA ITO 1010DE
Vc: 50v/div
28V
The bias voltage "VB" is supplied by the secondary winding of EHT transformer. The parabolic effect is due to the integration of frame saw-tooth by the filtering capacitor "C1 ".
Iy· T /:"vB = 8 . C1 = 0.95V
Where:
· Iy : Peak-to-peak yoke current = 380mApp
· T: 20ms
· C1 = 100011F
VII1.5 - Frame flyback
During flyback, due to the loop time constant, the frame yoke current cannot be locked onto the reference saw-tooth. Thus the output of amplifier "A" will remain high and the thyristor is blocked. The scanning current will begin flowing through diode "0". As a consequence, the capacitor "C" starts charging up to the flyback voltage. The thyristor is triggered as soon as the yoke current reaches the maximum positive value.
91 AN2028/29·86
EHT transformer winding (for 900 tube: Yoke => L = 120mH, ry = 60Q) Figure 88
L
-- I c
f /
...... '\
(DIODE
\
LOAD YOKE
"\. (THYRISTOR J / " ' - - _ /
· VLF = 21 OVpp
· IYOKE = 380m App · L = 500llH · C = O.471lF · VLF = 9.2 Iy(pp) . ry · Flyback duration = 1ms
91 AN2028/29-87
1145
APPLICATION NOTE
VII1.6 - Feed-back circuit V111.6.1 - Frame power in quasi-bridge configuration Figure 89
Frame Reference
Saw-tooth
R2
~
Reference de
Adjust
v+
R'2
Frame Amplitude Adjust
FRAME YOKE
Iy
This stage measures the frame scanning current in
differential mode and compares it to the reference
saw-tooth on pin 3.
The overall configuration is built around two sym-
metrical networks:
· "R1, R2, R3" network: determines the dynamic
saw-tooth voltage
· "R'l, R'2, R'3" network: sets the bias voltage and
the d.c. shift control.
a.c.
. gain:
G
=-RR2
=-IVy
.
0'.
.
RM
1 IN
where:
· Iy : Peak-to-peak Yoke Current
· VIN : Peak-to-peak saw-tooth voltage (pin 3)
· 0'. E [0,1) : amplitude adjustment
VIII. 6. 1. t- Choice of "R" value
The saw-tooth generator output is an emitter follower stage. Pin 3 output current must therefore be always negative.
R « R1
VIN(MIN)
VBIAS - VIN(MIN)
Where:
· VBIAS : Bias voltage for pins 1 and 2
· VIN(MIN) : Saw-tooth voltage low level
91 AN2028!29-88
Example:
· R1 = 22kQ · VBIAS = SV
R1
=> R = 10
· VIN(MIN) = 1.26V
VIII. 6. 1.2 - Influence of R3 value
R3 sets the bias voltage for pins 1 and 2. This voltage should be lower than S.SV so as to enable the frame to function upon initial start-up at
Vee = 6V.
If the bias voltage is higher than this S.SV level, the d.c. open-loop gain will fall thereby rendering the system more sensitive to d.c. drift.
Satisfactory results are obtained at VBIAS values falling within 4V to SV range.
R3 = R,
VSIAS
Vs (V'N(MEAN) . G) - VSIAs(1 - G)
Where: VIN(MEAN) : saw-tooth mean value (pin 3)
Capacitor "C" connected between pins 1 and 2 determines the system stability. Its value must be appropriately calculated as a function of "R1, R2 and R3" values so as to reject the line frequency component.
1146
APPLICATION NOTE
VIII. 6.1.3 - "S" Correction circuit in quasi-bridge configuration Figure 90
TEA 2029
01
R4
02
YOKE
100n
Ve
I
91 AN2028/29-89
The "S" correction waveform is obtained using the non-linear "VDIODE" versus "IDIODE" characteristics of "01" and "02" diodes.
The signal pre-corrected by "01", "02" diodes and the feed-back signal through "R5", are summed at "A". The "S" correction level is determined by the ratio between "R4" and "R5" resistors.
V111.6.2 - Frame scanning in switched mode using coupling capacitor Figure 91
I TEA2029C 1 I I I 1 I __________ ...JI
LInearity
+VS
.,.....-Adjustment
--=--+--ll--+--=-+--~- --- - tP---]
10kn
220kn I
R3
I
(680kO)
l (b)
56kil
To Safely Input
The parabolic voltage at (a) is integrated by "R2, C2" network and used for "S" correction. The "S" waveform voltage at (b) is added to the
91 AN2028/29-90
.saw-tooth voltage at (c). The "S" level is determined by "C2, R2, R3" network.
---------------- ~~~i@~g~~~~~~ ---------------- 53/55
1147
APPLICATION NOTE
V1I1.6.3 - Frame safety In case of failure in the loop, the thyristor may remain turned-off while the inverse parallel-connected diode conducts. This will result in a hazardeous situation where the voltage across the cou-
piing capacitor "Cp" will reach an excessively high value. To avoid such situation, the voltage at point (a) should be applied to the "Safety" input pin 28 after it has gone through the matching network "R4, R5".
VIII.7 - Frame scanning in class B with flyback generator
VIII. 7.1 - Application diagram
Figure 92
TEA 2029C
Pin 14
+24V
200V (TEA 2029)
ch ,mnf '~...._-,.
I ~ 470nF
1nF 13kn
220
Q
:
1SnF 10kQ
--{D--- 2 -- 3 __ ...JI
N.C.
150kQ
680kQ 470kQ
+12V _-=110k-n--+
Frame saw· tooth
100nF
1000~F
Vertical Phase Shift
3.3kn
2.2kn
15kn '-----t::>-------J 100n
Verticat Amplitude Adjust
91AN2028f29·91
--- 54/55 ------------- ~~~~©~~~~~l:l ----------------
1148
~
",en
~;
~:=1e3n1:
,~O C0lZ
.....
(J1 (J1
.j>. 0;
co (J1
a!. Secondary Ground (isolated from mains) -& Primary Ground (connected to mains)
TEA 2029C
~ ~X
I: 3 ·
m .... -0 -I
CD <D
~- l>
eN CD I\)
OJ 0
-0 I\)
-0 <D
gl>
- !o_!.l."'"rO'0
:~;: (")
s:~
-m10z
~O
~:;
"","G>
JJ
l>
5:
»
"'0
n"r'0-
»
o-i
Z
Z
S m
APPLICATION NOTE
TEA5170
SECONDARY CONTROLLER FOR MASTER-SLAVE STRUCTURE
By : T. PIERRE
SUMMARY
Page
INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
"
OPERATING PRINCIPLES OF MASTER-SLAVE STRUCTURE .................
2
11.1
MASTER-SLAVE MODE .................................................
2
11.2
BURST MODE ........................................................
2
11.3
OPERATION OF A MASTER-SLAVE SUPPLY IN TV APPLICATION. . . . . . . . . . . . . .
3
III
DESCRIPTION OF TEA5170 .............................................
4
111.1
BLOCK DIAGRAM .....................................................
4
111.2
OSCILLATOR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
111.2.1 Operation in free-running frequency mode .......................... . . . . . . . . .
5
111.2.2 Operation in synchronized mode ..........................................
5
111.3
ERROR AMPLIFIER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
lilA
PULSE WIDTH MODULATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
111.5
OUTPUT STAGE ......................................................
?
111.6
Vcc MONITORING .....................................................
?
IV
TV POWER SUPPLY APPLICATION BUILT AROUND TEA5170 ................
?
IV.1
MAIN APPLICATION CHARACTERISTICS ..................................
?
IV.2 COMPONENTS EXTERNAL TO TEA51?0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
?
IV.3 FREE-RUNNING OSCILLATION FREQUENCY ..............................
8
IVA ERROR AMPLIFIER COMPENSATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
IV.5 SYNCHRONIZATION SIGNAL MATCHING STAGE ...........................
9
IV.6 SOFT-START PERIOD DURATION. . .. . . .. . .. . ... . . . .. . . . . . . . . .. . . . . . . . . . .
9
IV.? TRANSFORMER CHARACTERISTICS .....................................
9
IV.8 OPERATION. . .. . . .. . . .... ... . . . . . . . .. . . . . ... . . . .. . . . . . . . . . . . . .. . . .. . . 10
IV.8.1 START-UP.................................................. .... ..... 10
IV.8.2 STAND-By.................................................. ........ . 10
IV.8.3 SYNCHRONIZED MODE ................................................ 10
IV.9
DELAY TIME IN SYNCHRONIZED MODE ......... : . . . . . . . . . . . . . . . . . . . . . . . . .
10
IV.10 ELECTRICAL DIAGRAM ................................................ 11
V
DC-DC CONVERTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
V.1
ELECTRICAL DIAGRAM ................................................ 12
V.2
OPERATION.. .. . . . .. . . . . . . . .. . . .. .. . ..... . .. . . . . . . .. . . . . . . .. . . . . . . . ..
12
V.2.1 Open-load Protection ................................................... 12
V.2.2 Short-circuit Protection .................................................. 13
V.2.3 Demagnetization monitoring .............................. . . . . . . . . . . . . . . . . 13
VI
CONCLUSION
13
AN408/0591
1/13
1151
APPLICATION NOTE
I - INTRODUCTION
The TEA 5170 is designed to work in the secondary part of SMPS, sending pulses to the slave TEA2164 which is located on the primary side. of the main transformer. The function of the regulation and synchronization are carried out by the TEA5170. An accurate regulated voltage is obtained by duty cycle control. The TEA5170 can be externally synchronized by a frequency higher or lower than the free-running frequency. This feature is particularly suitable for TV applications.
\I - OPERATING PRINCIPLES OF MASTER-SLAVE STRUCTURE
This architecture offers two modes of operation: · Master-slave mode (for normal operation)
Figure 1
· Burst mode (used during start-up and stand-by phases)
11.1 - Master-Slave mode In this configuration, the master circuit located on the primary side, issues PWM pulses used for output voltage regulation. These pulses are sent via a pulse tranformer to the slave circuit (Figure 1). In this mode of operation, the falling edge of PWM signal may be synchronized by an external signal (e.g. by line flyback signal in TV applications).
11.2 - Burst Mode During start-up and stand-by phases, no regulation pulses are issued by the master circuit and thus the slave circuit operates in burst mode. In this config- . uration, the slave circuit determines the switching frequency and the burst period. (See figure 2)
Figure 2 : Burst Mode Operation
PWMh
Signal
tPulse
Input _
o ·
~
Base t"-----ry7---.L>...--.,..,.r------
11/1 Current
[k/)
V
V ~
91AN5170·01
I Burst Period. . - _I
- - - typ .. 30ms - - - - ;
t
I
I
I
I
I
I
I
I
I
I
COLLECTOR CURRENT ENVELOP
1-- Switching Period
DETAIL OF ONE BURST
91 AN5170·02
1152
APPLICATION NOTE
11.3 - Operation of a Master-Slave Supply in TV Application
The arrangement generally employed is depicted in Figure 3. On the secondary side, a microcontroller is connected to the remote control receiver which issues control signals for stand-by and normal modes of operation. (Figure 4).
· In stand-by mode, the device power consumption is low (few Watts). The master will no longer send any control pulses to the slave which will consequently begin operating in burst mode.
Power supply regulation is performed by the slave circuit through the auxiliary winding.
Figure 3
· In normal mode of operation, the master circuit issues the PWM signal for regulation. The power supply operates in master-slave mode. The master circuit is simultaneously synchronized with the line flyback signal.
· Power supply start-up. As soon as the VCC(START) threshold is reached, the slave circuit begins operating in burst mode. While the secondary voltages are being stabilized, the microcontroller holds the TV set in stand-by mode.
Once the start-up phase is terminated, the set may remain in stand-by mode or switch into normal mode of operation.
_ _ _ _ _ ~ _______ ____ e _______ M ______ 0 _________ 0_ 00 eo 00.°. ______ 00 ____ eo 00 _0 00 00 0_ 00 0 _ _ _ _ _ _ -.
Muting Conlrol
MAINS INPUT
R
,
. P2
c
Pl : Output voltage adjustment in normal mode
Pulso Transformer
pz : Output voltage adjustment In stand-by __ - _____ - ___ - __ - - - - - - - - - - - - - . __ - - - _.0 _. __________··_. __ · ____ · ____________________ . - - - - - '
91 AN5170-03
---------------- ~ ~~~":;m~,l'~l~2~ ----------------3/13
1153
APPLICATION NOTE
Figure 4
TEA 2164 Vee Voltage
VCC1START)
CD ®
pP supply voltage Stand-by
L~_~E_LAY_~--+,i.,--0~_P~~--jl..,-~~
itl
: 12
)II t
---- start-up-------I-S-t-'"-d_-b·;+I-·---N-"-m'atf':p~.-,,-tlO-"---~·-tI---S-ta-"-d--b-y-Z70-
· T BURST: burst period
· TDELAY: time COrlStanl g~nera\ed by f1P * B : burst envelop lout 01 regulalLQn) * b : burst envelop (w,lh stand-by regulatJon)
:: I cQmm~nds Is~ueo by uP
SYSTEM DESCRIPTION: WAVEFORMS
91 AN5170-04
III - Description of TEA 5170 The TEA 5170 is a fixed frequency PWM signal generator operating in voltage mode regulation.
111.1 - Block Diagram
Figure 5
-<1,,+ LOGIC
(Sync.)
L.._ _ _- ' COMPARATOR
~
POWER OUTPUT STAGE
Inverting
Input
4/13 1154
Your
GND
Vee
PWMOUT
91 AN5170-05
APPLICATION NOTE
111.2 - Oscillator The oscillator generates a linear saw-tooth signal and sets the free-running frequency. This oscillator can also operate in synchronized mode.
111.2.1 - Operation in free-running frequency mode. (See figure 6).
111.2.2 - Operation in synchronized mode The oscillator is synchronized by forcing the sawtooth return.
Enabling the synchronized mode (Figure 7) The synchronized mode is enabled when the signal pulse on pin 8 (Rt) coincides with the oscillator
Figure 6
saw-tooth return. The "Ct" capacitor charge current is then multiplied by a factor of 0.75. The TEA5170 will remain in synchronized mode as long as the synchronization pulses fall within the following window: (0.8 T1 + T2) < TSYNC < (1.33 T1 + T2) Where:
· T1 : Ct charge time in non synchronized mode. · T2 : Ct discharge time
Synchronization signal (Figure 8)
Synchronization signal is applied to pin 8 "Rt" and the capacitor "Ct" is discharged when voltage "VAt" exceeds the "2.7 V" threshold.
V,hl = IV VII12 =2V
.----...:......,
VCI~_______-_--_--_2V
-------- - - -
---tv
..JL
"~:"1
n·
1-----'
Comment: The internal current generator used to charge the "Ct" capacitor is disabled for the entire phase where "VRt" is higher than 2V. Thus, in order to maintain Figure 7
I
I I
..
I
I I
1 - I----Tl---,~
T2
! - - - T : period~
Tl =0,5xRl xC, T = C, (0,5 x R, + 1330)
T2= 1339xc,
91 AN5170-06
the saw-tooth shape of the oscillator signal, the "VAt" voltage should fall to 2V before the capacitor "Ct" full discharge.
, -t'--------' ' - - - - - ' ,---'-'------'---~ ~ V
-
..
'< ASYNCHFlONTZED
MODE
)
91 AN5170-07
- - - - - - - - - - - - - - - ~~~~~~~~~~ -------------5~ /13
1155
APPLICATION NOTE
Figure 8
2:R~1- --- ----A~
,, , ,, ,
111.3 - Error Amplifier (Figure 9) The on-chip error amplifier can be accessed through its inverting and output terminals. The non-inverting input is internally tied to reference voltage level.
Comment: An internal inverting amplifier sets the correct phase polarity of the error amplifier output signal for regulation.
111.4 - Pulse Width Modulation (Figure 9) The TEA 5170 is a PWM signal generator operating Figure 9
91 AN5170-08
in voltage mode. The pulse width is determined by comparing the error signal "VOM" with the oscillator saw-tooth.
When the error signal "VOM" exceeds the regulation range, internal threshold components' will set a minimum conduction timetoN(MIN) and also limit the maximum conduction time tON(MAX).
At initial start-up, a soft-start function implemented by linear charge of soft-start capacitor "C(S-STARTJ" is used to vary gradually the tON(MAX) threshold. The output pulse width varies from tON(MIN) to tON (MAX) nominal value for VC(S-START) voltage variation of 0 to 2V.
1 \ r AOmuptlpifuietr _ _ _ _ _ _/ \
VpIN5
, - - - Vp1N6
l z \ Z ; \ PWM ~/'\.
Inputs
VOM ( "
LI._.1_ D. J.%~I t
L J I
I
I I
I:
91 AN5170-09
-- 6/13 ------------ ~ ~~~~~~~~2~ - - - - - - - - - - - - - -
1156
Figure 10
APPLICATION NOTE
1mA
1mA
LOGICAL CONTROLLER
-~-- -- 3 -
111.5 - Output Stage (see figure 10)
The output stage operates in on/off mode. For a supply voltage higher than 8V, the output signal value is independent of the supply voltage. (Typical value: 7V)
111.6 - Vcc Monitoring
Vcc Rising : When Vcc reaches the value "VCC(STARTj", an internal switch enables the operation of the output stage and the soft-start capacitor begins charging.
The internal logic circuitry becomes operational before Vcc has reached the "VCC(START)" value.
Vcc Falling: When Vcc falls below the "VCC(STOP)" level, the negative output stage is switched-on, the transistor is turned off and the soft-start capacitor is discharged.
IV - TV POWER SUPPLY APPLICATION BUILT AROUND TEA5170 (Figure 15)
General structure and operational features of this power supply were outlined in section 1.
The details covered below apply to a power supply configuration using the slave "TEA2164" device.
(Refer to TEA2164 data sheet and application note "AN40910591 " for further details).
91AN5170-10
IV.1 - Main Application Characteristics
Characteristic
Value
Input voltage
170VAC to 270VAC
Output power
20Wto 120W
Output power in stand-by mode
1Wt06W
Switching frequency
32kHz
Synchronization on line flyback Signal (positive)
IV.2 - Components External To TEA5170
Component Value Calculation
Also refer to TEA2164 application note "AN409/0591" for calculation methods applicable to other power supply elements. The external components determine the following parameters: · Operating frequency · tON(MIN) · Soft-start · Error amplifier gain
Ideal Values · Period of operation "Tosc" : 32~s · tON (MIN) duration : 1.2~s · soft-start duration: 20ms · Error amplifier gain:
· DC gain GDC = 35 · AC gain at 1/10 x Tosc: GAC = GDc/5 = 7
-------------- ~ ~~~~~ru~~_~U{~~ --------------7/13
11.57
APPLICATION NOTE
IV.3 - Free-Running Oscillation Frequency
For efficient use of TEA5170 and TEA2164 synchronization windows, the periods of both devices are determined as folows :
TOSC(5170) = 1TS.Y0N6C
TOSC(5170)
TOSC(2164) = 1.223
Where: · TSYNC : line flyback signal period · TOSC(5170) : TEA5170 free-running period · TOSC(2164) : TEA2164 free-running period
Numerical Application Period of synchronization signal being
T SYNC = 32/-1s :
TOSC(5170) TOSC(2164)
TSYNC 1.06
TOSC(5170) 1.223
24.711S
30.211S
30.2 1.223
The TEA5170 free-running period is determined as follows:
TOSC(5170) = Ct (0.5 x Rt + 1330)
Figure 11
Where:
C _ tON(MIN) - 0.5 x 10-6
t -
1330
· Rt = 105kQ (1%)
· Ct = 560 pF (2%)
IV.4 - Error Amplifier Compensation
· A high DC gain is required for good accuracy.
· For stability reasons, the AC gain must be at-
tenuated so as to avoid injection of the switching
frequency component into the regulation loop.
.
R2 + R1
· DC Gain: GDC = R3 x R2 x R1
'.
R3X1~ R2+ R1
· AC Gain. GAC =
1 x R2 x R1
R3 +.,J.O..l-C
Assumptions:
· R2 > > R1 since VOUT > 10 VREF so the value of
R2 does not modify the result of calculation and
only R1 and R3 influence may be taken into consideration.
· R1 = 2.2kQ, R3 = 75kQ
· With cut-off frequency in AC regulation mode:
·
fc =
1 10 x Tosc
~
C = 2.2nF
c
t
VOUT
I
91AN5170·11
1158
APPLICATION NOTE
IV.5 - Synchronization Signal Matching Stage (Figure 12) The synchronization signal is generated from the line flyback. The pulse amplitude is given by :
VPIN8(MAX) = _._R_ With Rt > > R VSYNC R+ Rp
The pulse time constant is (R+ Rp)C and should be
Figure 12
lower than the saw-tooth fall time. Thus, for a line flyback signal amplitude of 50V :
R = 6.8kQ, Rp = 75k£2, C = 150pF
Comment: Practical and theoretical values may differ slightly since the rise time of the line flyback signal is not generally negligible.
EHT
TRANSFORMER
~c
IV.6 - Soft-Start Period Duration
In this application, the duration of soft-start is around 20ms,
With:
o CIS-START) = TIS-START) x 2 x 10-6 = 47nF
Figure 13
orr 3
ffil A O[X~ 6J- ° o[b~ a 1" :,',11 7
0
° ",221
I,7' !!f1i'
91 AN5170-12
IV.7 - Transformer Characteristics (Reference: G4453-02 OREGA)
Winding
Pin
Inductance
np
3-6
680 ~H
nAUX
7-9
7 ~H
n2
19-13
592 ~H
n3
19-20
12 ~H
n4
14-17
5 flH
n5
22-21
25 ~H
- - - - - - - - - - - - - - Fii ~~~;j~~~~g~ - - - - - - - - - - - - -9/-13
1159
APPLICATION NOTE
IV.S - Operation
IV.S.1 - Start-Up
The power supply of TEA5170 begins rising gradually upon initial start-up of the primary circuit. When Vee reaches the value Vee(START) = 4V, the oscillator has already begun running and the softstart capacitor "C(S-START)" begins charging. The conduction time is tON(MIN) and rises gradually.
IV.S.2 - Stand-By
This function is externally activated by grounding the "stand-by" input thereby disabling the power supply of TEA5170. (Figure 15).
To return to normal mode of operation, this pin should be left floating.
IV.S.3 - Synchronized Mode
The differentiator at synchronization input will transform the line flyback signal into a rectangular pulse whose time constant is around 1ms. In this mode of operation, there is a lapse of time between the falling edge of the synchronization signal and the real transistor turn-off (Figure 13). In TV applications, this time should be less than the line flyback duration so as to avoid the occurrence of on-screen visible disturbances. t1 and t3 times are specific to TEA5170 (t1 + t3 = SOOns typ.) t4 is specific to the primary circuit (= SOOns typo with TEA2164).
Only t2 = tON(MIN) and t5 = tSTG of the switching
transistor can be modified according to individual application requirements.
IV.9 - Delay Time In Synchronized Mode Figure 14
~-'~ SIGNAL
VAt
k\------2.7V I :~ - - - - - . 2V
II I
II I
,I I
~~ I--if-Tl
OSVCOILLTLAAGTOER : I . _ _- - - - - - - - - - - - - -
(TEA 5170)
I,
I
I
r ~ T3 v,&~'/;1, 1----..".:
(TEA 5170) _
.
oJ~, lL_~______~~i.-~__- ~ .________________________
!UI
I
I
1 COLLECTOR
CUR<RIeEl NT
l I
I
f-T.-i
L -__________ _______________________ ~
1160
~
A~cnn
cjCl)
~~
~3: ",CI)
~~
~ ~
.~ w
MAINS
220VAC
4x lN4007
150/lF 385V
l2Oko 2W
OREGA
G4453·02
BY21B-600
3
.Oil13
~1~ PLA 811
12V
l20500/lVF
470/lF
II
19
25V
'6
orr°
~~~8! l000/lF
~
25V
";~!:,oFOOO:~
21
40V
- : l ' ' _ _ - - - I '
r-
10/lF 16V
2.7nF
ug -+1'6--~.um -c::J -------///~I. ~tVnF/~ 1000
2700
° ~
POUT: 120W
»z · I: 32kHz
~
~
'"
Pulse Transformer
.- PI
47kll
120ku
--, 2.2 ko
I
135 V
t"oT1· :<
c:
~
0
Cti
~ !!!
01
g(1)
C'j'
!!!.
C iii'
(Q
iil 3
7.SV Stand-by
Controt
Sync. Input
l> "tI
6.Bko
n"rt-I
~
5 z
z
S m
APPLICATION NOTE
v - DC-DC CONVERTER
(9V ± 40% => 24V , 1.5W) (Figure 16) This low power converter employs a transformer wound on a low-cost ferrite former. The configuration is protected against open loads and short-circuits.
Transformer characteristics · Primary inductance: 53.5 ~H
· Transformation ratio for 24V : ns I np = 2
Regulation Characteristics
· Line regulation at 4.9V to 15V : 24V ± 0.22% · Load regulation for (O.4PMAX - PMAX) :
24V± 0.12% · Power range: 0.24W to 1.6W · Efficiency: 40%
V.2 - Operation
· The period of operation is determined by Rt and Ct components.
· Minimum conduction duration: 0.6 ~s · Free-running period: 29 ~s
· Soft-start period duration: preset at 100 ms.
V.2.1 - Open-load Protection
In case of low load values, the minimum conduction time tON(MIN) with respect to the period of operation is too high to maintain the output voltage at its nominal value. The only solution to stabilize the voltage is to increase the period of operation by reducing the charge current of the oscilator capacitor Ct. This is obtained by injecting additional cur-
rent into resistor Rt as soon as the output voltage
VOUT rises.
V.l - Electrical Diagram Figure 16
---...----------------'1 . I1--I:1- 5V~~3V
Np Ns 2~gvF., ~b ~J 24V
BY10~;OO ~ lN4148
r-----t-----t-I
_.....
j;
'(r
·3.9kO[! J47ko
..._ . , , - t-----------------~
91AN5170·16
- - - - - - - - - - - - - - ~1_2/_1_ 3 ____________ ~ ~~~(;~9~~2~
1162
APPLICATION NOTE
V.2.2 - Short-circuit Protection
When the current through transistor becomes substantially high, the transistor is saturated and induces a high dlc/dt . The diode on switching transistor base is then forward biased and begins deviating a portion of the base current. This phenomenon is self amplified and therefore results in rapid transistor turn-off.
V.2.3 - Demagnetization Monitoring
In order to avoid magnetic flux runaway, thetransistor should be driven into conduction only once the transformer has been fully demagnetized. While the transformer is being demagnetized, the secondary-connected rectifier diode is forward biased and thus maintains the error amplifier output at 0 potential. The allowed conduction period is consequently tON(MIN).
VI - CONCLUSION
The TEA5170 requires a very simple configuration and yet offers excellent regulation quality combined with synchronization possibility for flyback-type converters.
The TEA5170 can be used in converters operating at 16 kHz to over 100 kHz frequency range.
Access to error amplifier and soft-start input are some of the remarkable features offered by this device whose application areas are by no means limited.
The TEA5170 belongs to the family of master controller devices characterized by their outstanding flexibility of use and application performances.
- - - - - - - - - - - - ~ ~~S-TIJ~~~~~. - - - - - - - - - - - - 13/13
1163
APPLICATION NOTE
TEA2164 MASTER-SLAVE SMPS FOR TV & VIDEO APPLICATIONS
By : B. O'HALLUIN
SUMMARY
Page
INTRODUCTION
2
1.1
MASTER-SLAVE STRUCTURE .................. .
2
1.1 .1
Block diagram . . . . . . . . . . . . . .
2
1.1.2 Fundamentals . . . . . . . . . . . . . .
3
1.1.3
Principles of regulation . . . . . . . . .
3
1.1.4 Advantages offered by this architecture.
3
1.2
STAND-BY IN BURST MODE . . . . .
3
II
THE TEA2164 INTEGRATED CIRCUIT . . . . . . . .
4
11.1
DESCRIPTION ............... .
4
11.2
TEA2164 SIMPLIFIED BLOCK DIAGRAM ...................... .
5
11.3
PIN CONFIGURATION
5
11.4
OPERATING MODES.
5
11.4.1 General description ..
5
11.4.2 Synchronized mode ..
6
11.4.3 Burst mode . . . . . . . .
6
III
APPLICATION EXAMPLE
7
111.1
CHARACTERISTICS & APPLICATION DIAGRAM.
7
111.1.1 Characteristics . . . . . . . . . . .
7
111.1.2 Application diagram . . . . . . . . . . . . . . . .
7
111.2
TRANSFORMER CALCULATION ............... .
10
111.3
SWITCHING TRANSISTOR & ITS BASE DRIVE ........ .
12
111.3.1 Current limit calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
111.3.2 Switching transistor . . . . . . . .. . . . . . . .
12
111.3.3 Switching aid (snubber) network . . . . . . . . . . .
13
111.3.4 Base drive . . . . . . . . . . . . . . . . . . . . . . .
13
111.3.5 Reopy Resistor calculation . . . . . . . . . . . .
14
111.3.6 Calculating the value of resistor connected to V+ .. .
15
111.4
INPUT PULSES & OSCILLATOR .......... .
15
111.4.1 Input pulses (Pin 6) . . . . . . . . . . . .
15
111.4.2 Oscillator (Rosc ,Case - pin 7 and pin 8)
15
111.5
STAND-BY . . . . . . . .. . .....
16
111.5.1 Very low frequency oscillator . . . . . . . . . . .
16
111.5.2 Regulation in stand-by mode . . . . . . . . . . . . . . . .
16
111.5.3 Maximum power in stand-by operation . . . . . . . . . . .
16
111.5.4 Booster circuit for higher stand-by output power . . . . . .
17
AN409/0591
1/30 1165
APPLICATION NOTE
SUMMARY (continued)
111.6 111.6.1 111.6.2 111.6.3 111.7 111.7.1 111.7.2 111.7.3 111.7.4 111.8
IV IV.1 IV.2 IV.3
START-UP ..
Start-up resistor Selfcsupply .. Secondary controller circuit start-up.
PROTECTION FEATURES Overload protection . . . . . . . Short-circuit protection . . . . . Repetitive overcurrent protection
Overvoltage protection ..
OSCILLOGRAMS .....
APPLICATION VARIANTS ALL MAINS APPLICATION
117 VOLTS APPLICATION
APPLICATION WITHOUT STAND-BY
I - INTRODUCTION
The TEA2164 is a Switching Power Supply Controller circuit designed to operate in Master-Slave structure. This device is located on the primary side of power supply and requires the addition of other controller device such as TEA2028 or TEA5170 connected to the secondary side.
1.1 - Master-slave structure
1.1.1 - Block diagram
Figure 1
Page
18 18 18 18
19 19 19 19 19
20
26 26 28 29
The main application of this circuit is in switching mode power supplies operating in discontinuous mode flyback configurations used in TV receivers at 60 W to 150 W power ratings. The device incorporates a "Burst Mode" feature which offers excellent functional efficiency in "Stand-by" mode of operation.
MAINS
-AcT
IN SLAVE
91AN2164·01
-2/30- - - - - - - - - - - - - {:7fi ~~~~~JHg~~Hr:t - - - - - - - - - - - - - -
1166
APPLICATION NOTE
1.1.2 - Fundamentals The "Master" device located on the secondary side of the power supply performs the following functions: - Output Voltage Control: Monitors the Conduction
Period of the "Slave" circuit so as to provide Output Voltage Regulation as a function of Mains and Load variations. - Switching Frequency Synchronization on Horizontal Scanning Frequency The "Slave" circuit provides for the following functions: - Power supply start-up - Optimized Switching Transistor base drive - Power supply regulation during stand-by operation - Protection agai nst · Overloads · Short-circuits · Open-loads · Missing control pulses normally delivered by
secondary block.
1.1.3 - Principles of regulation
A fraction of the voltage to be regulated is obtained from a voltage divider network and compared to an internal reference voltage. The error voltage delivered by comparator is used to modulate the duration of the output pulse delivered by PWM (Pulse Width Modulation) Controller. The frequency of these pulses is determined by an internal oscillator synchronized on the horizontal scanning of the TV set. PWM output signal is differentiated and forwarded towards the primary controller via a small low-cost pulse transformer which provides galvanic isolation between primary and secondary sections. The differentiated positive signal pulse will turn the transistor on while the negative pulse will turn it off. Conduction period variation will determine the amount of energy stored within the transformer during each cycle so as to maintain a constant output voltage whatever load and mains voltage variations.
1.1.4 - Advantages offered by this architecture
The "Master-slave" architecture offers the following advantages: - Excellent output voltage regulation - Main output voltage is not influenced by signifi-
cant variations of auxiliary voltages (no sound interference within image display, even at audio power levels as high as 2 x 30 W).
- The coupling between transformer primary and secondary windings is no longer a critical requirement for regulation; which allows use of low-cost transformers (such as SMT5 series manufactured by OREGA)
- Synchronization on TV line scanning frequency will suppress anyon-screen interference produced by power transistor turn-off, and eliminate the need of additional output voltage filtering components.
- All power supply protection features are implemented on primary. side thereby allowing efficient and fast response to : · Current limitation · Overvoltage protection · Persisting overloads
- Other protections can be implemented to limit or disable the duration of regulation pulses issued by PWM, in case of failure detected within any section of the TV set.
1.2 - Stand-by in burst mode
The secondary power required in stand-by mode is often quite low (1 W to 5 W in majority of cases). Instead of operating the system at low tON duration, which is a difficult task with discontinuous mode transformer, the TEA2164 offers a "Burst Mode" to perform the stand-by function. - T1 : Burst duration
Figure 2
COLLECTOR CURRENT 1c'
--T1-
T'-----
91 AN2164·02
- T2 : Burst period (period of VLF oscillator) The Tl/T2 ratio is fixed internally. The TEA2164 allows the switching transistor to conduct only for typically 13% of the internal VLF oscillator period. A pulse train ''Tl'' called "Burst" is thus obtained. The repetition period "T2" can be set externally by capacitor "Cl" connected to pin 1O. In this mode of operation, the power transferred to the secondary windings is very low. The collector current envelope has been optimized to yield efficient soft start and to minimize the audio
---------------- ~~~~;~~~~R~ ----------------3/30
1167
APPLICATION NOTE
noise generated by switch mode transformer. Also, the free-running frequency "fose" is shifted towards 20kHz so as to eliminate all audible noise in standby mode. In this mode, the secondary output voltages are regulated by a feed-back loop on primary side. The TEA2164 will switch from synchronized mode (regulation by mastercircuiton secondary side) to burst mode (stand-by) as soon as the synchronization pulses, normally delivered by secondary block, are no longer available. It is therefore obvious that the most efficientsolution to implement the burst mode is to cut supply to master which will consequently be unable to deliver any synchronization pulse. The stand-by function in burst mode offers the following advantages: - Eliminates the need for auxiliary stand-by power
supply and therefore its costly building elements such as stand-by mains transformer, relay or other specific components. - Good power supply efficiency, thanks Ito burst mode, allows low mains power consurl1ption in stand-by.
11- THE TEA2164 INTEGRATED CIRCUIT
11.1 ' Description
The TEA2164 is cased in a 16-pin OIL package. The 4 center pins (2 on each side) are connected together and used to evacuate the heat. The device includes the following functional blocks: - A free-running oscillator which can be synchro-
nized on the frequency of pulses issued from secondary. - A Very Low Frequency (VLF) oscillator used for burst mode. - An input stage to shape positive and negative input pulses. - An output stage with two complementary amplifiers: · one, to provide the positive base current to turn
the switching transistor on, · the other,to provide the negative base current
requi~d to turn the transistor off. The positive base current is proportional to the collector current. - A sophisticated protection system featuring:
· Collector current limitation at 2 threshold levels · A device to memorize the occurrence of over-
loads and short-circuits, and to disable the power supply completely after a pre-determined time constant. · Vee monitoring device with 2 thresholds : - Upper threshold: for overvoltage protection - Lower threshold with hysteresis :. for system
start-up - Supply Voltages:
· one pin for general supply (Vee) · one pin for power supply of the positive output
stage (V+)
· four pins for power supply of the negative output stage (V-) (according to application type, these pins can be grounded)
· one pin for ground connection
·~4/~3~O_________________________ ~~~~@~~~~~~~~ ____________________________
1168
11.2 - TEA2164 Simplified block diagram Figure 3
APPLICATION NOTE
-Vee
11.3 - Pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Ground Icopy C2 vvInput Rosc Cosc R1 Cl ICMAx vv-
Output v+ vcc
TEA 2164 GROUND
91 AN2164·03
Batwing DIP16 (plastic package)
11.4 - Operating modes 11.4.1 - General description The TEA2164 can operate in two distinct modes: - "Normal" (or synchronized) mode:
Synchronization and regulation by secondary controller circuit. · "Burst" mode: In this mode, the TEA2164 operates as a standalone device. This mode is used upon start-up and in stand-by mode.
------------------------------ ~~ii@~9~~~~©~ ----------------------------5/-3-0
1169
APPLICATION NOTE
Two additional modes are also available: - Long interval safety mode : the device is fully
turned-off although it is correctly supplied (pin 3 capacitor has stored the occu rrence of repetitive overcurrent) - Start-up mode: the device is in low-consumption mode, its Vcc has not yet reached the VCC(START) threshold. The normal start-up sequence is : · Start-up Mode · Burst Mode · Synchronized Mode
11.4.2 - Synchronized mode
In synchronized mode, control pulses delivered by secondary block are differentiated and then applied to pin 6 input.
Figure 4
The positive pulse will synchronize the internal osciJlator by discharging the "Cosc" capacitor, which will generate a constant width pulse called "START" signal to be applied to positive stage output amplifier. Similarly, the negative input pulse generates a "STOP" pulse which is applied to negative stage amplifier whose output is used to turn-off the switching transistor. The "START" signal is disabled under following conditions : - voltage applied to Vcc terminal is higher than
+15V - current protection device has detects a collector
current higher than "lc(M2)". If the current reaches "lc(M1)" threshold, the current limitation device will generate the "STOP" pulse.
IC(M2) OR
Vee 2: 15V
IN
INPUT STAGE
14 uuT
le(M!)
1c(M2)
11.4.3 - Burst mode If no control pulses are present at device input terminal, the TEA2164 will operate as stand alone in burst mode.
The switching frequency is given by the internal oscillator whose value depends on external components "Rosc" (pin 7) and "Cosc" (pin 8).
The "START" signal is generated by the oscillator
91AN2164-04
and is used to turn the switching transistor on.
Transistor turn-off is performed by "lc(M1)" current limitation through soft-start block or by "tON(MAX)" value set by resistor "R1" connected to pin 9 (or voltage applied to pin 9).
The VLF oscillator will enable the "START" signal for 13% of its periode duration.
- - 6/30 - - - - - - - - - - - - i:ii ~~iir;m~~~'1~~ ----------~---
1170
Figure 5
OSClLLATOR
IC{M2) OR
Vee ~ 15V
APPLICATION NOTE
14 OUT
VERY LOW FREQUENCY OSCILLATOR
91 AN2164-0S
III - APPLICATION EXAMPLE (120 W - Discontinuous mode flyback power supply with stand-by in burst mode)
111.1 - Characteristics & application diagram
111.1.1 - Characteristics
- Discontinuous mode flyback SMPS - Standby function using the burst mode of
TEA2164 - Switching frequency:
· Normal mode: IS62SHz (synchronized on horizontal deflection frequency)
· Stand-by mode: 19kHz - Nominal mains voltage: 220VAC (SOHz or 60Hz) - Mains voltage range: 170VAC to 270VAC - Nominal output power: 120W - Mains power consumption:
· Normal mode: 150W max · Stand-by mode : SW (with 3W at secondary
side) - Efficiency:
· Normal mode: 8S% (under nominal conditions) · Stand-by mode: 60% - Regulation performance at high voltage output: · better than O.S% versus mains variations of
170VAc to 270VAC · better than O.S% versus load variations of 3SW
to 120W
- Overload and short-circuit protection with complete power supply shut-down after a pre-determined ti me constC!nt
- Open-load protection by output overvoltage detection
111.1.2 - Application diagram
The first diagram illustrates the primary block built around TEA2164.
The system is set into stand-by mode of operation by the switch connected to +ISV supply.
Regulation pulses can be generated by a PWM device such as TEAS170 or delivered by a deflection circuit such as TEA2028 or TEA2029 which includes on-chip power supply regulation.
The second diagram depicts the full application diagram for a complete TV set power supply and scanning built around TEA2164 and TEA2029.
A microprocessor will introduce lOOms delay interval for the system to start-up in stand-by and then to switch into normal mode (synchronized and regulated by TEA2029).
- - - - - - - - - - - - - - ~ ~~~@m~~'Ir~2c~ - - - - - - - - - - - - - -7/30
1171
APPLICATION NOTE Figure 6: TEA2164 typical application
Fusa '.6A
220VAC ± 200/..
Malns Input
4 x 1N4007
'OOuF 365V
300""
BA157
100ka
(2W1
'BA157 BA157
OREGA
r - - - - , Q ·· '73.04
I
BY216
33ka
(1W1
.25V ~--~r-~---------- ,2A
(NldlG'
110 kn
"V Small Signal Primary Ground ~ Power Primal)' Ground
ClSecondsty GroUnCl (isQlarecf from Mains)
a,2m (1 WI
100U
~GlIOUND
l--;I;: - - r:-.-..r.-3-3-0-uic:Jf-.-.-.r--..L....-. REGULATION
91 AN2164·06
1172
.....
220VAC Mains (nput
300kn I I 2, 47~F
385V
SA 157
~
~cn
C0rq,elnIn
f.!..
TEA 2164
~i!
!8li=0 :
~cn
~~
e. ~~3
;100nF
~
}z >
~
~
~
-..J W
~
a
6
""
<l PrImary Ground (connBClBd fO Mains) ""-2 s.concmry Ground (isolated from Mains)
TEA 2029C
"to"
e::
iil
-..J
err
mAHSFOR~R
s:(f)
j J 1 i--IIQ!
\J (f)
Qo Cl.
I "'
rI
. I
·
LiNE .24V
'.I..!...., FLYBACK
~
oCnD-"
:::J
o(") 3
"0
CD
r0-
m
"0
"Q.
0"
!'l.
0"
:::J
Cl.
0;"
(Q
iil 3
AGC PULS:JL
MIITEOIIT &
SO/60Hz
lDEtrrlFICAnON
»
"'\J
"r'\J
(5
V]....
~
ElII CORREcnON
o z
z
S m
APPLICATION NOTE
111.2 - Transformer calculation
The power supply must meet the following specification requirements:
- Mains voltage range: 170VAC to 270VAC (50Hz
or 60Hz)
i.e. 200Voc to 380Voc taking into account the
supply ripple
.
- Output power: 1OW to 120W max i.e. 150W at input
- Switching frequency: 15625Hz
- Main output voltage: +135V
Figure 8
IPL1 /1
bJ .. t
1st
i b
.. t
V'C'E'1-!!V=RH:: --t .. t , ' :toN!tdm: I '---T---.!
91AN2164·06
The transformer primary inductance "Lp" and transformation ratio "n2/n1" are to be calculated while taking into consideration limits related to conduction time "tON" and switching transistor currents and voltages (Ic and VeE).
Following conventional expressions are employed:
(2)
tdm = n2 x V'N x tON
n1
VOUT
combining (1) and (2)
I tON = V1'N X -V2P,N x T x Lp
combining (3) and (4)
(3) (4)
I (5)
First limit: The system should always operate in
discontinuous mode
I therefore: tON(MAX) + Idm(MAX) $ T
I (6)
The worst case is specified with PIN(MAX) and VIN(MIN) :
n2
( 1 n1) " - - + - - ,rc;- <
V IN(MIN) VOUT P -
T 2P'N(MAX)
(7)
Second limit: Maximum voltage across the switch-
ing transistor:
I VCE(MAX) = V'N(MAX) + VR
(8)
n1 where: VR = VOUT x n2
Third limit: Maximum current through the switching transistor :
2P'N(MAX) x T
IC(MAX) =
Lp
(9)
To minimize the voltage across the power switch, we shall select a reflected voltage of VR = 150V.
Therefore:
n2 = 135V = 0 9 n1 50V ' · In order to take full advantage of the transformer ferrite core, one shall select the extreme limit of demagnetization:
--- 10/30 ------------- ~ ~~~@~,g~~R~~ ------------------------------
1174
APPLICATION NOTE
therefore:
tON(MAX) + tdm(MAX) = T
1 2
Lp = _ _T_ x [ VIN(MIN) x VOUT
(10)
2PIN(MAX) VOUT + nn12 VINIMIN)
64 X10-6 ( 200 x 135 J2
Lp = 2 x 150 x 135 + 0.9 x 200
Lp = 1.55mH
Characteristics of the ferrite core used in this case will require 80 primary and 72 secondary turns.
TRANSFORMER SPECIFICATIONS - Reference: OREGA- SMT5 - G.4173-04 - Mechanical Data:
· Ferrite: 850 · 2 cores: 53 x 18 x 18 (THOMSON-LCC) · Airgap: 1.7 mm
- Electrical Data:
Pin Number Wire Size Number of Turns (mm)
Primary 3-6
Forward
2-1
Flyback
7-9
Secondary
+ 135V
19-13
+15V
17-14
+25V
21-22
80
0.45
3
0.45
7
0.45
72
0.45
9
2 x 0.45
14
2xO.45
Induelance (I1 H) 1550
3 14.5
1240 22 52
Using this transformer: - maximum voltage across the switching transis-
tor: VCE(MAX) = VIN(MAX) + VR
VCE(MAX) = 380 + 150 = 530V
- maximum current:
IC(MAX) =
2PIN(MAX) x T Lp
2 x 150 x 64 x 10-6
1.55 X 10-3
= 3.5A
- Maximum conduction time at PIN(MAX) :
tON (MAX)
=
- 1v
IN(M(N)
..,}2
X
P(N(MAX)
x
T
x
Lp
tON(MAX) = 2~0 ..,}2 x 150 x 64 x 10-6 x 1.55 x 10-3
tON (MAXI = 27.3115 - Minimum conduction time at PIN(MIN) :
-v- tON(MINI = 1- ..,}2 x P1N(MIN) x T x Lp IN(MAX)
tON(MIN) = 3~0 ..,}2 x 12.5 x 64 X 10-6 x 1.55 x 10-3
tON(MIN) = 4.1115
Comment:
When using high value secondary filtering capacitors or if the switching transistor storage time is too long, the system start-up at high mains voltages may be difficult. In fact, upon start-up, the secondary filtering capacitors are discharged which will result in very long demagnetization time. According to both, transformer characteristics and minimum conduction time, the transformer is magnetized and the peak primary current begins rising (the current does not any longer begin rising from zero). In worst case, the current can reach the threshold level "1C(M2)" which will consequently prevent the power supply start-up. Two solutions are available:
· Reduce the number of secondary turns which will decrease the demagnetization time (but also increase the switching transistor reflected voltage)
· Reduce the primary inductance while keeping the transformation ratio constant (which will also increase the RMS and peak current values)
Under all circumstances, an efficient transistor base drive combined with a not too long storage time (3.5f!s to 4f!s) are required.
- - - - - - - - - - - - - - - ~ ~~;~~)~lm~~(P:J1I - - - - - - - - - - - - - - - 11/30
1175
APPLICATION NOTE
111.3 - Switching transistor & its base drive 111.3.1 - Current limit calculation Figure 9
IT '"1~0- - +r-1r0-: ·
.... VIPIN 6) fr--+~.>.....----- v"",-" t
_" t
- IC(MAIXC ) r ~ :t -~ --a ~7! --I
I I
I
I: ;
.
~
i
I!
" t
Vc{Ml)~--~~---- + : V{PIN III
~ \ ~ I
,
'
I
I
I
I
-!--'-
Is
91 AN2164-09
The "Rs" resistor sets the switching transistor collector current limitation value. Power supply reliability is directly dependent on the value of this resistor, which is calculated as a function of the' maximum power required from the secondary winding. Lets set the secondary power limit at 150W value:
PIN
= -PO-UT
n
=}
PIN
= 175W
(with efficiency n = 0.85)
IC(MAX) =
2PIN(MAX) x T Lp
_ 12 x 175 x 64 x 10-6
\I IC(MAX) =
1.55 x 10-3
= 3.8A
The storage time at this current value is approxi-
mately 41ls (with BU508A).
The collector current slope at nominal mains volt-
age is 0.2A!lls .
.
The current )imitation threshold level must there-
fore be fixed at 3A.
The "IC(M1)" voltage threshold is typically 0.84V :
therefore: Rs = 0.:4 = 0.280
In practice, the selected value is Rs = 0.270 At minimum mains voltage level, the slope is smaller and the maximum current therefore becomes:
IC(MAX) = 00'8247 + 200 -3 X 4 x 10-6 = 3.6A
. 1.55 x 10
At maximum mains voltage level, the slope is sharper and the maximum current therefore becomes:
I C(MAX)
=
0.84 0.27
+
380 1.55 X 10-3
x
4
X
10-6 41A =.
111.3.2 - Switching transistor
It was demonstrated that under normal operating conditions, the maximum collector current value is around 4.1 A while the maximum collector voltage is approximately 530V.
Factors such as the overvoltage produced at the time of transistor turn-off, transformer leakage inductance and peak currents generated in the event of short-circuits, must be also taken into account.
At the time of transistor turn-off and under worst case conditions (maximum mains voltage, significant overload), the "VCE" voltage across the transistor can reach 1OOOV. Therefore, a transistor with VCES ~ 1200V must be seleCted.
In case of short-circuit, transformer is magnetized and the collector current value will reach 5A (with 0.270 measurement resistor and 1.35V typo VC(M2) threshold). Therefore, a transistor with IC(MAX) ~ 7A must be selected.
- - 12/30- - - - - - - - - - - - - '-W ~~~@m~,r~'Ic~~?c~ - - - - - - - - - - - - - - -
1176
APPLICATION NOTE
The BU508A and equivalents are perfectly suitable.
111.3.3 - Switching aid (snubber) network
The "Snubber" network is built using a combination of "R , C , D" components to limit the dV/dt slope and to reduce the collector current rise up at the time of transistor turn-off.
Switching losses at turn-off which are proportional
to "V x I" product are thus minimized.
· C = 2.2nF Figure 10
· R = 220Q
· D: BA159
· T: BU508A Whatever load and input voltage conditions, it must be ensured that the system will operate permanently within the safe operating area of the transistor.
A 1OOQ resistor connected between transistor base and emitter terminals will improve the voltage behaviour.
lOon
111.3.4 - Base drive A bipolar switching transistor requires a positive base current to enter into saturation while a nega-
Figure 11
91 AN2164·1 0
tive base current is necessary to turn it off. The shape of base current waveform is illustrated in the following Figure.
19
I I
3 :41 5 I
91AN2164·11
1 - Constant amplitude pulse to turn the transistor on (duration depends on oscillator saw-tooth return)
2 - Base current proportional to the collector current (Ieopy function on pin 2)
3 - Saturated base current to limit the circuit power dissipation (function implemented through the re-
sistor in series with pin 15)
4 - On-chip delay interval of "0.7I1S" to prevent simultaneous conduction of positive and negative stages
5 - Negative base current to remove the charge stored within base (storage time - duration of which depends on type of switching transistor)
-----'---------- ~ ~i~@m~,.,,(~~9c~ - - - - - - - - - - - - - - 13/30
1177
APPLICATION NOTE Figure 12
· L = 2_5flH · R = 100 · C = 47flF · D : 1N4001
The base drive circuit is a "capacitive coupled" device. There is therefore no need to apply a negative voltage "V -" to pins 4, 5, 12 and 13 which will be grounded. P.C.Board tracks connected to these pins must be wide enough to allow efficient evacuation of the power dissipated by device.
The positive base current goes through 3 diodes connected in series. Capacitor connected across these diodes will be charged to a value equal to 3 times forward diode voltage drop. This voltage is sufficient to turn the transistor off. This capacitor must be selected to withstand the effective current through it, which is mainly the negative turn-off current.
The inductor in series with base, limits the dlB/dt slope· and thus the base current, at the time of transistor turn-off. The inductance value must be adjusted to yield efficient turn-off while the negative
Figure 13
91AN2164-12
current delivered by TEA2164 should not exceed -1 .7A . The 100 resistor connected across this inductor helps the damping of base current oscillations at the beginning of transistor conduction. Comment:
In order to avoid all problems at TEA2164 output stage, it is recommended to connect a 1N4444 diode between the output terminal (pin14) and the ground, as illustrated in Figure 12 above. In case of capacitive drive and if a negative voltage appears across output terminal (due to inductor L), this diode will deviate the current towards ground thereby preventing reverse bias of the negative output stage.
111.3.5 - Rcopy Resistor Calculation
This input is used to set the switching transistor forced gain, that is, to deliver the base current necessary for a required collector current.
Input pin 2 can be considered as a virtual ground terminal and therefore:
Rs x Ic = Reopy x leopy
Also, the current gain between input (pin 2) and the output (pin 14) is :
1000 => IB = 1000 x Icopy
The forced gain is therefore:
91 AN2164-13
A forced gain of 2.25 (BU508A) with Rs = 0.270 will yield: Rcopy = 6000
In practice, one would select the optimal value by observing the dynamic aspect of the saturation voltage on an oscilloscope. This is why Rcopy = 3900 is selected with BU508A.
-14-/3-0------------------------- ~~~~~~~~~~~ ----------------------~----
1178
APPLICATION NOTE
111.3.6 - Calculating the value of resistor connected to v+
In order to prevent high current flow through the
integrated circuit and also to limit the power dissi-
pation, the output stage is operated in saturated
mode in high positive output currents.
The maximum recommended positive base current is 1.2A.
Selected maximum power supply voltage is +12V.
Lets calculate the resistor value required to yield a maximum current of +I A.
The voltage drop across three diodes connected in
series is typically 0.9V x 3 = 2.7V at IA.
The base-emitter saturation voltage of BU508A is
around 1V. The TEA2164 output stage voltage drop
is approximately lAV.
Therefore:
R = 12V-1V-(3xO.9V)-IAV =69£2
~
lA
.
Preferred value Rv+ = 6.8£2 is selected. Figure 14
Comment: - It is obvious that the maximum 18+ value is
directly dependent on the power supply voltage. Therefore, Vcc variations as a function of mains voltage, through the forward self-supply winding, must be taken into consideration. - All calculated values must be optimized on the prototype board by taking into account all operating conditions of the switching transitor to be used.
111.4 - Input pulses & oscillator
11104.1 - Input pulses (pin 6)
The regulation PWM and sync pulses issued by the controller circuit on secondary side are sent to the primary side through a pulse transformer that ensures galvanic isolation between primary and secondary sections. The PWM pulse is differentiated by the pulse transformer. The input signal (pin 6 ofTEA2164) frequency must
Pulse Transformer
91AN2164-14
fall within the sync window:
0.65 fosc < fSYNC < fosc
The positive drive pulse will turn the transistor on while the. negative pulse will turn it off. Prior to transistor turn-off, the positive base current is interrupted and then after a constant time interval, the negative base current is applied to turn the transistor off. For appropriate system operation, the amplitude of
pulses applied to input pin 6 must fall within ± 0.5V to ± 1V range.
The pulse transformer can be built by 2 few turn windings wound on a tore or ferrite rod. 111.4.2 - Oscillator (Rosc , Cosc - pin 7 and pin 8) The free-running frequency is given by :
lose =
1
0.4 x Rose x Case + 470 x Case
Choice 01 fosc must take into account the following constraints:
· fosc must fall within the sync range: 0.65 x fosc < fSYNC < fosc
· the free-running frequency fosc must not fall inside audible frequency range in stand-by mode: fosc 2': 20kHz
The sync frequency value used in TV applications is 15.7kHz.
The free-running frequency "fosc" value is selected to be 19kHz so as. to iall at the center of sync frequency range. This lrequency is close to 20kHz and is therefore not audible.
The value 01 "Cosc" capacitor determines the oscillator saw-tooth discharge time. This time has a direct inlluence on "tON(MINj" used by TEA2164 and therefore should not be too long so as to allow a
- - - - - - - - - - - - - - ~ ~~~(llig1e2~(~~~c~ -~-----------15- /30
1179
APPLICATION NOTE
low "ton(min)". We shall select Cosc = 1.2nF The corresponding value of Rosc is calculated as follows: .
Rose
1
470 = 10Bkn
0.4 x 19 x 103 x 1.2 X 10-9 0.4
Selected value is : Rosc = 11 Ok!) The tolerance of these components is calculated as a function of maximum admissible free-running frequency dispersion while also taking into account the minimum and maximum limits of the horizontal scanning frequency.
111.5 - Stand-by The system will enter into stand-by mode by simply disconnecting the power supply to the secondaryconnected PWM regulation device (TEA5170 or TEA2028). In the absence of control pulses normally delivered by the secondary block, the TEA2164 will switch to "burst" mode in which case,
Figure 15
the power transfer falls to a low value.
111.5.1 - Very low frequency oscillator
The period of this VLF Oscillator is determined by capacitor "C1" connected to pin 1O. ForC1 = 100nF, the VLF oscillator per.iod is approximately 30ms. The typical burst duration is therefore 3.9ms - which is 13% of the VLF oscillator period. The ripple ratio of secondary output voltages in stand-by mode depends on VLF oscillator period and hence on the value of capacitor C1.
111.5.2 - Regulation in stand-by mode
A feed-back loop connected to pin 9 is· used to modify the maximum conduction period in burst mode and to allow the regulation of secondary output voltages in stand-by. The feed-back information is delivered by the selfsupply flyback winding of TEA2164. This signal, once rectified and filtered, is an image of secondary voltages. This voltage is applied to an adjustable
divider bridge and then to pin 9 which is used for output voltage adjustment in stand-by operation. It is recommended to choose the voltage values in stand-by slightly lower than nominal values used under normal operating conditions. A 'l'nF capacitor has been added to pin 9 which will improve the
91 AN2164·15
filtering of the regulation voltage. 111.5.3 - Maximum power in stand-by operation The collector current envelope shape varies as a function of the secondary power consumption in stand-by.
-16-/3-0-------------------------~~i~@~~~~~Jl ----------------------------
1180
APPLICATION NOTE
It follows that the power which may be tranferred to the secondary winding in stand-by is therefore limited.
The maximum power in stand-by can be estimated as follows:
Figure 16
91AN2164·1B
PSB(MAX)
~
PMAX·
-3- x 0.13
x
ISB ISYNC
=} P(SBMAX) ~-1530 x 0.13 x
19 x 103
3
8W
15.7x10
Comment:
- at PSB = PSB(MAX) , C3 capacitor (pin3) is slowly
charged and the voltage on pin 3 will reach the protection threshold value (3V typ.) and the SMPS is shut down.
Figure 17
111.5.4 - Booster circuit for higher stand-by output power
When higher stand-by output power is required, it is possible to add a network on pin 10, which modifies the shape of the VLF oscillator saw-tooth and increase the T1/T2 ratio.
The burst duration "T1" is not modified, only the VLF oscillator period "T2" is shorter, which will increase the available stand-by output power.
TEA 2164
r--- ---- - -..,
t I
: 1~
VLF
I
OSCILLATOR I
IL- _ _ _
_
_
_ Di_ sch_ar_ ge
:
.J
r--------,
I
Vec I
I 1Skn 47kQ I
I I
I
I
trVCl
1n0F0:I
I
I
150
kQ
I
~ _______ J
VC1 4V
1.2V
"~~
~: 1
.. t
I~ T1
I I
t----- T2 -----i
T11T2> 13%
91AN2164·17
--------------- ~ ~~i;;mg~,~2~ --------------- 17/30
1181
APPLICATION NOTE
111.6 - Start-up
111.6.1 - Start-up resistor
Upon initial system start-up, the mains filtering capacitor is charged through the rectifier diode bridge. Figure 18
The voltage across the device power supply capacitor (pin 16) is low and less than the "VCC(STARTj" value. The TEA2164 is therefore in low consumption state. The supply voltage capacitor "C16" begins charging through a high value (1 OOkQ) resistor "RSTART" connected to the rectified mains voltage.
RSTART
(100kn)
iCC(STARn
"'---11
CIS
(220I1F)
The capacitor charge up time is given by :
t
VCC(START) X C's
CHARGE = V,N
RSTART - ICC(START
9 x 220 x 10-6
0.85s
tCHARGE
310 (0.8 x 10-3)
100x 10-3
At minimum mains voltage level : tCHARGE = 1.2s
- The power dissipated within "RSTART" resistor is :
P = (VIN - Vcc)2
RSTART
(310-12)2
.
P =.
3 = 0.9W (P = 1.4W at Mains max level)
100 x 10
An application variant is '4'hen the start up resistor is directly connected to non-rectified mains.
In this case and in order to obtain an identical start-up time, the value of "RSTART" resistor must be divided by 1t. The power dissipation is thus reduced by approximately 30%.
111.6.2 - Self-supply
As soon as the voltage on pin 16 reaches the VCC(START) level of 9V, the TEA2164 will start-up and deliver the base drive pulses to the switching transistor at internal oscillator frequency (set by Rasc and Casc). The duty cycle of these pulses gradually increases (soft-start). During this cycle of operation, the device does not receive any control
91AN2164·18
pulse from the secondary controiler circuit and therefore operates in "Burst mode". The start-up will correcty take place if the device is rapidly self-supplied, that is, before the voltage across the supply capacitor on pin 16 falls below VCC(STOP) threshold. TheTEA2164 is supplied by two distinct secondary windings, one connected in flyback and the other in forward configuration. The forward voltage will rapidly provide the supply required by TEA2164 whereas the flyback voltage will begin rising slowly and depends on various secondary time constants. Main advantage of the flyback voltage is that it provides a regulated supply voltage proportional to the secondary Voltages. A +12V voltage has been selected for device power supply at nominal mains voltage level. A lower value such as +1OV can be selected which will also reduce the power dissipation. Note however that since the overvoltage protection threshold is internally" set at +15V, then the lower is the supply voltage level the greater will become threshold margin. At nominal mains voltage, the forward voltage value is selected to be 1V below the flyback voltage value so that, the supply voltage at maximum mains voltage, will not rise much above its nominal value (and will remain below 15V threshold level).
111.6.3 - Secondary controller circuit start-up
After a time interval required for the secondary
- 18/3-0 ------------~. ~~tm~m~i!~11 - - - - - - - - - - - - - -
1182
APPLICATION NOTE
power supply capacitors to charge up, the secondary-connected regulation controller circuit will be powered and as soon as its supply voltage "Vcc" reaches the "VCC(START)" level, it will begin delivering regulation and synchronization pulses. The TEA2164 will receive these pulses and will consequently switch from "Burst Mode" to "Normal Mode" synchronized and regulated by the secondary controller circuit. The secondary controller circuits (TEA2028, TEA2029 and TEA5170) have a "soft-start" function. This system allows better transition when switching from stand-by mode to normal mode.
The TEA2028 and TEA2029 controllers have no "tON(MIN)" function, and for this reason, it is necessary to choose lower voltage in stand-by mode than in normal mode. Otherwise, switching from standby mode to normal mode will not be possible (secondary controller circuit will not issue regulation pulses as long as the output voltage remains above its nominal value).
The TEA5170 has a "tON(MIN)" function, butit is also recommended to choose the stand-by voltage under the nominal value so as to avoid overvoltage when switching from stand-by mode to normal mode. For further details on secondary controller circuits,
Figure 19
please refer to TEA5170 and TEA2028-TEA2029 Application Notes (AN407/0591).
111.7" Protection features
111.7.1 - Overload protection
The current limitation is set by resistor "Rs" as a function "1C(M1)" threshold, such that the power transfer is limited at 150W. If the load connected to secondary requires higher power, the current limitation is activated and will limit the power transfer by lowering the output voltage.
111.7.2 - Short-circuit protection
In case of short-circuit, the secondary voltage falls to zero and the time required for the transformer to demagnetize becomes very long. The collector current will no longer start at zero level but at the final value of the preceding period. The current value will rapidly reach "1C(M1)" and then "lc(M2)" threshold levels.
Only the "lc(M2j" threshold will disable the device and switch it into "Burst Mode". The device will re-start at the beginning of the following VLF oscillator period. However, if the short-circuit still persists, the "lc(M2)" protection threshold is once again activated.
Ic
IC(M2) -------------------------- ---
COLLECTOR
CURRENT
"Ic· (Burst Mode)
IA
~
(
--Tosc--
t 91AN2164·19
111.7.3 - Repetitive overcurrent protection
Each time that "lc(M1j" or "lc(M2)" thresholds are reached, an event counter will charge up the capacitor "C2" connected to pin 3. If the overload persists, the voltage across capacitor will reach the 3V threshold level and TEA2164 is consequently disabled (no power transfer to secondary will take place).
To exit this protection mode, the mains voltage must be disconnected during a time interval long
enough for all capaCitors to fully discharge. The system can re-start only once the capacitors have been discharged.
111.7.4 - Overvoltage protection
If an overvoltage (produced by improper adjustment or failure) appears at secondary terminals, the primary flyback voltage will rise and if the +15V threshold level is reached, the TEA2164 is disabled.
---------------------------- ~~~@!r~~~~~~~ ------------------------1-9-/3~0
1183
APPLICATION NOTE
An overvoltage would be also generated if the load on secondary terminals is disconnected. In this case, if the secondary controller device is not equiped with tON(MIN) feature (TEA2028 , TEA2029), it will stop sending the regulation pulses and the TEA2164 will consequently enter into "Burst Mode".
If the secondary controller device has a "tON(MIN)" function (TEA5170), the protection is performed at the primary side by the +15V overvoltage threshold level.
111.8 - Osciliograms Figure 20
1 · NORMAL MODE: Base Current
VPIN 6 : 1V/div
Is: 1A!div
Mains: 220VAC Load: 90W
Scale: 10flS/div
Figure 21
2. NORMAL MODE: Primary and Secondary Currents
JI, Mid"
Is: 1A!div
Mains: 220VAC Load :90W
Scale: 10f1S/div
-20/3-0 - - - - - - - - - - - - ~·~~;~;)m~,~~~~~ - - - - - - - - - - - - - -
1184
Figure 22 Figure 23 Figure 24
APPLICATION NOTE
3 - NORMAL MODE: ColleCior-emitter Voltage VPIN 6: 1V/div
VCE: 200V/div IC: 2A!div
Mains: 220VAC Load :90W
Scale: 1O~/div
4 - NORMAL MODE: Current Limitation Voltage
oJ VPIN 6: 1V/div
0J1 VPIN 11 : O.5V/div
J Ic: 2A!div
o
Mains: 220VAC Load :90W
Scale: 10).1Sldiv
S. NORMAL MODE: Oscillator Saw-tooth
o} VPIN 6: 1V/div
l VPIN B : 1V/div -1.6V
Mains: 220VAC Load :90W
Scale: 10~/div
Ic: 2A!div
---------------- ~ ~~i©m~~u~J?(C~ ---------------- 21/30
1185
APPLICATION NOTE Figure 25
Figure 26
Figure 27
6· NORMAL MODE: V+ Supply Voltage
VPIN6: 1V/div
12V VPIN 15 : 5v/div
Mains: 220VAC Load :90W
Scale: 101LS/div
Ic: 2Ndiv
7· NORMAL MODE: Output Voltage VPIN 6 : 1V/div
VPIN 14 : ,2V/div O.SV
Ic: 2Ndiv
Mains: 220VAC Load: 90W
Scale: 101LS/div
8. NORMAL MODE: Flyback and Forward Voltages (TEA 2164 Power Supply)
VFORWARD : 5v/div
VFlYBACK: 5V/div
o
Mains: 220VAC
Load :90W
Scale : 10l!Sldiv
- - - - - - - - - - - - - - - ~ 22/- 30 ------------- ~ ~~~~m~mlil~'G~
1186
Figure 28
APPLICATION NOTE
9· NORMAL MODE: Transistor tum-off
Figure 29 Figure 30
VCE: 200v/div IC: 1A1div
o
Mains: 220VAC Load: 90W
Scale: SOOnsldiv
10· NORMAL MODE: Saturation Voltage
18 : o.5A1div
Mains: 220VAC Load :90W
Scale: 2J.1S.'div
01 VCE(SAT): W/div
11 · NORMAl MODE: Safe Operating Area
Ic : O.5A1div VCE : 100V/div
Mains: 220VAC Load :90W
--------------------------~--- ~ ~i~;~~~f~9c~ ----------------------------2-3/-3-0
1187
APPLICATION NOTE Figure 31
Figure 32
Figure 33
12· STAND-BY MODE: VLF Oscillator
VPIN 10 : 1V!div
Ic :c.5Ndiv
o
Mains: 220VAC Load :3W
Scale: 5ms/div
13· STAND·BY MODE: One Burst
VPIN 10 : 1V/div Ic: O.5Ndiv
Mains: 220VAC Load :3W
Scale: 500~s/div
14· STAND·BY MODE: High Frequency Oscillator
. VPIN 10 : 1V/div 1.6V
Ie :O.5Ndiv
o
Mains: 220VAC Load :3W
Scale: 101lS/div
::.24~/::.30=--____________ ~ ~~~@m~"~'Ifg~ - - - - - - - - - - - - - -
1188
Figure 34 Figure 35
APPLICATION NOTE
15· START·UP SEQUENCE
Ii Start Mode
C!I Burst Mode
-12V III Normal Mode
1. V""" 2Vidt.
Scale: 200ms/div
1 Ie: 1Ndiv
16· OVERLOAD PROTECTION (Pin 3)
1'0 ,N""
-0
Scale: 200ms/div
Figure 36
17 · SHORT-CIRCUIT PROTECTION (Pin 3)
Ic:2NdiV VPJN 3 ; 'J.VlOiv
Scale : SOms/div
- - - - - - - - - - - - - - ~ ~~~~I~tgm~R:~ -------------25~ /30
1189
APPLICATION NOTE
IV - APPLICATION VARIANTS V.1 All mains application
IA wide input voltage range application can be configured around TEA 2164. We have built a power supply delivering 90W output power at mains input voltage range of 90VAC to 260VAC. Difficulties encountered in such application are given below: - Very wide regulation range: if a discontinuous
mode flyback transformer is employed, the conduction time would be highly variable. The "tON(MAX)" duration is determined as a function of maximum power output and the minimum mains voltage level. The "tON(MINj" duration is determined as a function of minimum power output and the maximum mains voltage level. - Start-up at minimum mains level : appropriate selection of start-up resistor and self-supply windings. - Optimized switching transistor base drive and appropriately dimentioned protection features to operate over the whole mains voltage range: both, the base current, and supply voltage values and hence the self-supply windings, must be ap-
propriately calculated.
FEATURES
- Discontinuous mode flyback SMPS
(Lp = 0.84mH)
- Standby function using the burst mode of TEA2164
- Switching frequency: · Normal mode: 15625 Hz (synchronized on horizontal deflection frequency) · Stand-by mode: 19 kHz
- Mains voltage range: 90 VAC to 260 VAC - Mains power consumption:
· Normal mode: 110 W max · Stand-by mode:
6.7W (at 110V) 9.8W (at 220V) (without degaussing coil) - Efficiency: · Normal mode: 83% (at 11 OV) 80% (at 220V) (measured with 86W output power)
- - 26/30 - - - - - - - - - - - - ~ ~i~@mR~~~~~
1190
FUSE 2A 90VAc to 260V AC MAINS INPUT
~
~(I) ifjl:\
2ilCII @ cco.of
~:c
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~~
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&12
'" ~
~
~
~
o
\l Small signal primary ground
~ Power primary ground
~ Secondary ground (isolated from mains)
~ ~ (.,
"
BA157 I 10n (2W) I
G.4388.00 Lp = 0.84mH
13
BY218
12 3
20
19
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BA159
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Sland-by Switch
0
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10kn
AUDIO
0
+20V,O.6A
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AUDIO
3
GROUND
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PULSES
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117V AC ::20%
4 x BY254
220llF (250V)
39k!l (2W)
SA 157 4.7fl (3W)
222o5V~FI·
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BY~218
SA157 20
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.. I"" '"
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1000
BA159
V Small signal primary ground ~ Power primary ground c::::J Secondary ground (isolated from mains)
~
» z
~
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CD
0.1Bfl(1W)
33k!l
~_
~ 0.45A
~+12V Stand·by
Switch
__ ~~v
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"'II
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a- ~ ~ s· 6 3. ea. ......
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~::E9?.»O(J)
~ S' ~i" ~
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PJ CI> ;!,
0
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5.s:~ .. 55
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CI> ~ ~
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c::
fa
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f~fCiI~>:":OT
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o , ~ Q. - 0
APPLICATION NOTE
IV.3 - Application without stand-by
The application arrangement is simplified if the stand by function is not required: - The "Master" circuit on the secondary side is
permanently powered and as a consequence the transistors used to cut its power supply are no longer needed and can be eliminated. - The feedback used for "stand-by" regulation func-
tion on the primary side configured around pin 9 of TEA 2164, can be simplified.
- The value of "C1" capacitor connected to pin 10 of TEA 2164 used to set the burst period and therefore its duration, is increased (1 flF or 2.2flF) so as to enable full load system start-up as soon as the first burst is available.
-------------- ~ ~~e~m9,~~pm --------------29/30
1193
o w
CD -I»
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!'lo
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gf-6'
0."0
&0 ;~"
c 0
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2.gs
3
en
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2..
APPLICATION NOTE
TEA2037
HORIZONTAL &VERTICAL DEFLECTION CIRCUIT
By : B. D'HALLUIN
SUMMARY
Page
INTRODUCTION
2
II
FUNCTIONAL DESCRIPTION OF TEA2037 .
2
11.1
GENERAL DESCRIPTION
2
Block diagram ..
2
Pin description. . . . . . .
3
Package . . . . . . . . . .
3
11.2
SYNC. PULSE SEPARATOR .
3
11.2.1 Extraction of sync. pulses from the composite video signal . . . . . . . . . . .
3
11.2.2 Negative TTL sync. (Monitor application) . . . . . . . . . . . . . . . . . . . .
3
11.2.3 Frame sync extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
11.3
LINE OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
11.4
LINE OUTPUT STAGE . . . . .
5
11.5
PHASE COMPARATOR (PLL) ..
5
11.5.1 Functional description . . . . . . .
5
11.5.2 Phase comparator operation
6
11.5.3 Output filter . . . . . . .'. . . . . .
7
11.6
FRAME OSCILLATOR ...... .
8
11.7
FRAME OUTPUT AMPLIFIER . . . . . . . . . . . .
8
11.8
FRAME FLYBACK GENERATOR . . . . . . . . . .
9
11.9
SHUNT REGULATOR ...... .
10
11.10 THERMAL CONSIDERATIONS .. .
10
III
APPLICATION EXAMPLES ... .
11
111.1
MONITOR APPLICATIONS .... .
11
111.1.1 Low-cost monitor (French Minitel) . . . . . . . . . . . . . . . . . . . . . .
11
111.1.2 Monitor with geometry and frequency adjustments . . . . . . . . . . . . .
12
111.1.3 High Frequency Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
111.2
BLACK & WHITE APPLICATION . . . . . . . . . . . . . . . . . . . . . .
14
111.3
USING COMPOSITE TTL SYNCHRONIZATION SIGNALS
15
111.4
DIRECT FRAME SYNCHRONIZATION . . . . . . . . . . . . . . . . . . .
15
111.5
CONSTANT AMPLITUDE 50/60 HZ SWITCHING . . . . . . . . . . . . .
15
111.6
MODIFYING THE LINE OUTPUT DURATION . . . . . . . . . . . . . . . . . . . . .
16
111.7
STARTING THE TEA2037 FROM +6V POWER SUPPLY . . . . . . . . . . . . . . .
16
IV
DESIGN CONSIDERATION . . . . . . . . . . . . . . . . . .
17
IV.1
PRECAUTION FOR INTERLACED SCANNING . . . . . . . .
17
IV.2
PRINTED CIRCUIT BOARD LAYOUT . . . . . . . . . . . . .
17
AN41 010591
1/17
1195
APPLICATION NOTE
I - INTRODUCTION
The TEA2037 is a horizontal and vertical deflection circuit for monitors and black and white TV sets.
This device includes all functions required for deflection, namely:
- Line and frame sync separation
- Line oscillator with phase comparator
Driver stage for line deflection darlington transistor
- Frame oscillator
- Frame amplifier with flyback generator for direct drive of the vertical deflection yoke.
The TEA2037 is particularly well-suited for low-cost monitors since it is cased in a low-cost package and requires a few number of external components and hence optimized for small displays.
However, application areas are by no means limited. Sophisticated applications requiring various adjustment possibilities such as for display geometry and centering settings (amplitude, linearity, ...) and operating at different line and frame frequencies (line frequencies up to 64kHz). are readily configured around TEA2037.
In large screen applications, addition of a heatsink mounted on TEA2037 will enable the vertical deflection yoke current to be boosted to 2A peak-topeak.
Figure 1 : Block Diagram
II - FUNCTIONAL DESCRIPTION OF TEA 2037
11.1 - General description
The TEA2037 is a 16-pin DIP package. The 4 center pins (2 on each side) are connected together and used as heatsink. From composite video or TTL-compatible sync. signals, the device will extract and generate all signals required for the line scanning darlington transistor and direct drive of the frame yoke. The following functional blocks are implemented on-chip:
Line and frame sync. separator . Li ne oscillator Line phase comparator Line output stage Frame oscillator Frame amplifier - Frame flyback generator
Shunt regulator The common device power supply is implemented by the on-chip shunt regulator. In order to optimize the drive to frame deflection yoke and also enable appropriate use of the flyback generator, the frame. amplifier is powered by an independent supply. The ground is connected to the 4 center pins of the device.
1196
APPLICATION NOTE
Pin description
1
Frame Oscillator
2
VCC2 (Flyback generator power supply)
3
Flyback generator output
4, 5 Ground
6
Frame feed-back (frame amplifier inverting
input)
7
VCC2 (positive power supply for frame output
stage)
8
Frame output (direct drive to frame yoke)
9
Line oscillator
10 Phase comparator output
11
Phase comparator input (line fly back)
14 Line output (drive to line darlington transistor)
15 Video input (or TIL-compatible sync.)
16 VCC1 (shunt regulator)
Package
Figure 3
..t
i,,~,
~O~ ... 91AN2037-03
The sync. detection level is set at 1.6 V. The value of R2 is typically 1 MQ (fixed for a good internal bias). Resistor R1 limits the output current of pin 15. Figure 4
Batwing DIP16 (plastic package)
IL2 - Sync_ pulse separator The TEA2037 extracts, first the line and frame sync. pulses from the composite video signal and then the largest pulses, i.e., the frame syncs. 11.2.1 - Extraction of sync. pulses from the composite video signal (TV application).
Figure 2
I IL TE_A2_03_7 _ _ _
LSl LS2
Video Input ---. R2
91 AN2037-02
Composite
1 5 kQ 1D?,nF
Video ~,I--'---I15
1 22DPF
1 MQ I
h
IL T_E_A_20_3_7 _
91AN2037-04
As illustrated in the above Figure, it is recommended to employ a low-pass filter which will suppress high-frequency harmonics susceptible to produce jitters on line sync signal in composite video TV applications. 11.2.2 - Negative TTL SYNC. (Monitor application)
Figure 5
I
I VR I LI __
TEA 2037
TIL
10 kn
Sync ---{:::Ji----J
91 AN2037-05
- - - - - - - - - - - - - - - ~ ~~G~,;;m~:~I!~:~ - - - - - - - - - - - - - -3/1-7
1197
APPLICATION NOTE
Figure 6
Figure 8
I \rmrrummnrrnnnu
.. t
§ t g'"
S~/:- Vz ~:-----~
~
VZ/2--------------~------------
~>
.. t
91 AN2037-0B
11.3 - Line oscillator
Figure 9
In monitor application, the sync. signal is generally separated from the video signal. In this case, the sync. signal is applied to pin 15 through a single limiting resistor. Similar to the former case, the sync. is detected when the input voltage falls below 1.6 V level.
11.2.3 - Frame sync. extraction
Figure 7
VCC1 ~~-----C~------~-i~
C ~
----,
I I I I I I
J
I
TEA 2037 II
I
91AN2037-09
Figure 10
91 AN2037-07
This function is processed internally and hence does not require any external component. Line and frame sync. pulses are distinguished by an integrated capacitor which is more or less discharged during each sync. pulse interval as follows:
if the sync pulse duration is short, i.e. it is line sync, then the capacitor is slightly discharged on the other hand, if the pulse width is larger, the capacitor is fully discharged and an internal frame signal is thus generated.
UJ
~ 6.6
!:i §2
az'"::
Line I
-Period-
91AN2037-10
-4/-17--------------------------~~~~©~~~~ru~©~ ----------------------------
1198
APPLICATION NOTE
The line saw-tooth is generated by charging an external capacitor on pin 9 via a resistor connected to VCCl (pin 16). The capacitor is discharged via an internal 1.4 kQ resistor. The saw-tooth amplitude is set by two on-chip threshold levels: - lower threshold: 3.2 V - higher threshold: 6.6 V The free-running period is approximately given by the following relationship .:
Tose ~ 0.85 RC
The phase comparator will modify the capacitor charge by injecting a positive or negative current
Figure 11
so as to produce correct phase and frequency relationships with respect to the synchronization signal.
11.4 - Line output stage
The line output stage has been designed for direct base drive of the horizontal scanning darlington transistor.
The low level interval on pin 14, i.e. the power line transistor blocking period, is determined by the time when the voltage of the line oscillator capacitor (pin 9) is below 4.8 V (internally set threshold level). In a typical application, this interval corresponds to 22).ls at 64).ls free-running period.
Vcc
Rl 6.6V~
3.2 V --LilliJ-- --
Saw-tooth
I
I
I
I
J
J I
_____ ~~3~ ___
Line Yoke
Rl : 470 Q R2 : 10 Q R3: 47 Q
C : 2.21lF D: 1N4148 T: BU184
91AN2037-11
Figure 12
PIN 9 VOLTAGE 64.6
(V)
.8
3.2 I
PIN 14 VOLTAGE
I I I
22 Jlsi
V(sat) 1!;::=t~==!:==1-----1-
11.5 - Phase comparator (PLL)
11.5.1 - Functional description The duty of phase comparator is to synchronize the horizontal scanning with the line sync pulse and ensure correct line flyback during the horizontal blanking phase.
Figure 13
DARLINGTON VeE
YOKE CURRENT
91AN2037·12
Line Flyback 91AN2037·13
--------------- ~ ~i~~m~~~J?r~ ---------------5/17
1199
APPLICATION NOTE
The line flyback signal (i.e. the pulse on the collector of the line scanning transistor) is compared with the line sync. signal issued by sync. separator. If the detected coincidence is incorrect, the compa-
11.5.2 - Phase comparator operation
Figure 14
rator will then generate an appropriate positive or negative current so as to charge or discharge the line oscillator capacitor thereby providing for frequency and phase locking.
.J-..-+-- V{roll
- 11
Figure 15
Line Flyback
-1M L
01-------- Saw·tooth ·_____~
(pin 11)
VCrs')
, )
m Inlemal
--.J :, L Line sync Pulse
riU. Output current .. (pintO) -
91AN2037-15
The line flyback signal goes through integrator network R1 C1 the output of which, a saw-tooth signal, is applied to comparator input (pin 11) via capacitor C2.
91AN2037-14
The comparator input stage is formed by the differential pair T1 and T2. T3 and T4 transistors are arranged in current mirror configuration and thus:
is = i2
The sum of currents going through T1 and T2 transistors is determined by the current generator
"I" so that: I = h+ i2.
The comparator output current is the difference current through the differential pair, i.e. :
The comparator is enabled by T5 transistor only during the line sync. interval. Transistor T6 inhibits the phase comparison during the frame sync. interval. During the first portion of the flyback, the voltage at comparator input (pin 11) is lower than the reference Voltage. T1 is off and T2 conducts; consequently the comparator output goes positive:
ioUT~+1
During the second portion, the input voltage ex-
1200
APPLICATION NOTE
ceeds the reference voltage and as a result, the comparator ouput falls to negative level:
iOUT = - I
If the line flyback is in retard with respect to the horizontal sync. pulse (which is the case of too long line periods), the interval for which the phase comparator's output current is positive would inFigure 16
crease. This current is then filtered and applied to the line oscillator capacitor (C5) thereby accelerating its charge-up phase and hence reducing the line period.
Inverse action takes place if the line flyback is in advance - the negative current at comparator's output will rise, C5 is charged more slowly and the line period is thus increased.
JL
I
I
I
I
I
I
I
vera!) - - - - - : - -
I
I
I
I
I
I
--0L-
I
-1-
THELINEFLYBACK INRETARD WITH RESPECT TO THE UNf SYNC PULSE
11.5.3 - Output filter Figure 17
Line Flyback
Saw-tooth (pin 11)
Internal Line sync Pulse
Output Current (pin 10)
JL
I
I
I
I
I
- - - - II - -
I
I
I
I
I
I
~
+ I
THE LINE FL YBACK IN ADVANCE WITH RESPECT TO THE UNE SYNC PULSE
Figure 18
91AN2037-16
1, = 2rr(R3+ R4) C3
R3+R4
13 = 2rrR3R4C4
---------------- ~ ~~~~;m?::~f?~ ----------------7/17
1201
APPLICATION NOTE
The duty of the output filter is to ensure the stability of the locked loop and its characteristics will have a partial influence on capture range and also on capture time. The holding range, which is larger than the capture range, depends on the ratio of the current available at the comparator output and the charging current of the line oscillator. The holding range does not depend directly on the cut-off frequencies of the output filter. But, as the voltage range at the comparator output is limited, a too high value for R4 will limit the holding range. The sync. pulse duration has significant influence on capture range and also on the holding range of the device. The output current duration is directly related to synchronization pulse width.
First the R5 x C5 product is selected to yield the required free-running line oscillator frequency. Then, the value of C5 capacitor is selected as follows: · for monitor applications (large holding range)
low value; e.g. :2.2 nF @ 16 kHz,
1 nF @ 32 kHz · for TV applications
higher value; e.g. : 4.7 nF @ 16 kHz Finally, the filter components are selected to match the required capture range.
(R4 :s 100 kQ to prevent comparator output
saturation)
11.6 - Frame oscillator
Similar to line oscillator, the frame saw-tooth is generated by charging an external capacitor on pin 1 through a resistor connected to VCC1.
Figure 19
VCC1
_
-
_
-
-
-
c
:
}
-R -
-
-
.
.
.
-
-
-
C
I ~
r--- 16 - - - - - - - 1
I TEA 2037 I
500n
Frame Sync Pulse
91AN2037-19
Figure 20
~
w ~ 3.1
~ 2 r;:,:::-:::<c:::::-:=o"":
§ ~3~1~ ==Ii
....
I
!
,0:(
~
l
j
!
I
I
! t
r
I
r
Sync Period
91 AN2037-20
The capacitor is discharged via an internal 500 Q
resistor. The saw-tooth amplitude is set at two
on-chip threshold levels.
The free-running period is approximately given by :
I
Tosc~O.15RC
I
Synchronization is achieved by period reduction . The frame sync. pulse issued by the sync. separator will modify the current through the resistor bridge which is used to set the saw-tooth threshold levels. The minimum synchronized frame period (MSFP) is given by:
MSFP ~ Tose 1.8
11.7 - Frame output amplifier
The frame saw-tooth generated by frame oscillator is first inverted (Gain: - 0.4) and then applied to the non-inverting input of the frame amplifier. The output current capability of this amplifier is as high as
± 1A thus enabling to drive vertical deflection yokes
requiring 2A peak-to-peak.
As a function of dissipated power, the device may require the addition of a heatsink.
A feed-back loop is connected to the inverting input of the frame amplifier (pin 6). As the CRT screen is not part of a sphere centered on the deflection center point, if the yoke is actually driven· by a saw-tooth waveform, the image is expanded at the top and bottom. The yoke must therefore be provided with an "8" waveform current, by applying linearity correction. The circuit configuration depicted above does not require any linearity adjustment - only an amplitude
-8/1-7 --------------~~~~@~~~~~~~ - - - - - - - - - - - - - - - -
1202
Figure 21
Frame Saw-tooth
'----c:::J---J p
Rs
Figure 22
FRAME YOKE
Cl
91 AN2037-21
APPLICATION NOTE
Vertical Amplitude: Frame current amplitude is determined by the value of measurement resistor "R1 ", potentiometer "P" settings and the value of "RS" resistor.
11.8 - Frame f1yback generator The output stage of the vertical amplifier includes a frame flyback generator connected to pin 3. During the vertical scanning flyback time, the value of the yoke inductance "L" must be taken into account since the time constant UR is no longer negligible. In television applications, the frame blanking time is 1.6 ms. Thus when UR > 1.6 x 10-3, it is necessary to increase the supply voltage to the frame output amplifier so as to reduce the flyback time. This surplus is required only for the frame flyback and energy is wasted by boosting the supply to the amplifier at all times (during the frame scanning time, the minimum voltage is substantially RI, where I is peak-to-peak frame current). The configuration of the flyback generator is depicted in Figure below:
Figure 23
adjustment potentiometer "P" has been provided for.
D.C. Feedback: The C1 capacitor is charged to approximately 1/2 x VCC2. Divider bridge formed by R2 + R4 and RS networks will set the d.c. feedback. The component values of this divider network will be choosen to avoid saturation at top and bottom of the output voltage. (pin 6 biasing voltage is approximately 0.6 V)
- Linearity Correction : A parabolic signal at frame frequency is available on "+" terminal of the C1 capacitor. This signal is integrated by R2, C2 network. An "S" waveform is thus obtained, which is applied to pin 6 via resistor R4.
Any correction to this "S" waveform depends on C1 and C2 values. The linearity correction depends on ratio: R2/R4
9tAN2037-23
During the second half of the vertical scanning time, transistor T2 conducts and capacitor C is charged to Vee through 01 , 02, R3 and T2. (Switch K open)
On fJyback, switch K closes and pin 3 is connected to Vcc. The voltage at pin 7 (Vec2), which was equal to Vce - VDt, is almost doubled during the flyback time. The only external components required are therefore 01,02 and C.
In addition to reducing the fJyback time, the flyback generator reduces the power consumed by the power stage, and can in certain cases avoid the
--------------- ~~~~@~g~~~?~~ ---------------9/17
1203
APPLICATION NOTE
Figure 24
'J\.J~' t
91 AN2037-24
need to use a heatsink. Diode D2 is a low-signal diode (1 N4148) but diode D1 must be appropriately rated since the positive current in the first part of the saw-tooth is supplied to the yoke through D1 and T1. A 1N4001 is generally used. 11.9 - The shunt regulator The TEA2037 incorporates an internal shunt regulator which delivers the common supply voltage Vcc to various blocks such as oscillators, comparator, sync separator and so on. The voltage on pin 16 is 9.7 V (9 V min, 10.5 V
max). The value of the series resistor R must be so
calculated to obtain a 15 mA current on pin 16 - this Figure 25
11.10 - Thermal considerations
In order to ensure reliable device operation, the dissipated power should be accurately determined. Calculation will allow an evaluation of the dissipated power and should be completed by package temperature measurements in actual applications. According to results obtained, a heatsink mayor may not be required. · Power drawn from VCC1 supply:
Pl = Vcc, .1,
Where h is the current through the shunt regulator (pin 16) · Power drawn from VCC2 supply:
Where:
- Ipp = peak-to-peak current through the vertical deflection yoke.
12 = Pin 7 quiescent current.
VCC2 = Pin 7 voltage. · Power dissipated in deflection yoke and the
measurement resistor:
R Vee -----I=r--.----<~-- Vee,
r-----
I TEA2037 I
91 AN2037-25
current ca.n be 10 mA min. and 20 mA max. The external current supply from VCC1 to both oscillators (i.e. line and frame) can be neglected in majority of cases. The resistor value is found to be 1.2 kO at Vcc = +28V. At Vcc = + 12 V, and taking into account the voltage tolerance on pin 16, a 150 0 series resistor must be used.
Where:
- Ry = Frame deflection yoke resistance
RM = Measurement resistor value Thus, the overall power dissipated in the integrated circuit is :
Po = Pl + P2 - Py
In application using the flybackgenerator, the VCC2 specified above becomes "VCC2 - Vo", where Vo is the voltage drop across the series diode.
-10-/17--------------~~~~~~~mf~~~~ ---------------------
1204
Figure 26
Vee2 Vee
APPLICATION NOTE
Figure 27 Frame Yoke Current
Frame Yoke Ly, Ry
91AN2037-26
III - APPLICATION EXAMPLES
111.1 - Monitor applications 111.1.1 - Low-cost monitor (French Minitel Type)
CHARACTERISTICS
Screen: 9" Monochrome
,
Frame deflection yoke: 72 mH, 40 n,
220 mA peak-to-peak
Vcc = + 25 V without flyback generator Frame flyback time: 1.2 ms
Figure 28
91 AN2037-27
- Vertical frequency: 50 Hz (20 ms) Vertical free-running period: 24.5 ms Horizontal frequency: 15 625 Hz Capture range: ±5/ls Holding range: ±1 OIlS Input signal: composite video Dissipated power: 1.15 W Only one adjustment: vertical amplitude
Video - t 1.5 kn
Input 100 nF 1 MQ
FLIlnYfbL'1C5 kQk~22 nF
47 nF;t
100 nF
l
1 kQ
91AN2037-28
--------------- ~ ~~~~m~~~~9CG~ --------------- 11/17
1205
APPLICATION NOTE
- This is a low-cost application used in French Minitel type configurations and requires minimum number of additional components and adjustments. The input is a composite video signal at line frequency = 15 625 Hz and frame frequency of 50 Hz. The free-running horizontal frequency is determined by the component values of RC network on pin 9. Since no adjustment is available, precision components must be used to ensure correct synchronization:
. [R = 35.7kQ, 1% and C = 2.2nF,
2% for fH = 15 625Hz]
The capture range is large enough to compensate for possible variations.
Synchronization range of the vertical oscillator is quite large which consequently allows use of less accurate components:
[R = 910 kQ, 5 % and C= ,180 nF, 5 %]
- Since the frame flyback time is short enough at supply voltage used 11ere, the flyback generator is not used in this application.
111.1.2 - Monitor with geometry and frequency adjustments
CHARACTERISTI CS
Screen: 12" Colour Frame deflection yoke: 18 mH, 10Q, 500 mA peak-to-peak
Vcc = + 12V with flyback generator
Frame flyback time: 0.7 ms Vertical frequency: 50/60 Hz Vertical free-running period: 23 ms (adjustable) - Horizontal frequency: 15.7 kHz (adjustable)
Capture range: = ±5f..ls
Holding range: ±10f..ls Input signal: negative TTL sync (line + frame) Dissipated power: 0.9 W Adjustments: · Vertical amplitude · Vertical linearity · Vertical frequency · Horizontal frequency · Horizontal phase-shift
Figure 29
1N4002
P1 ," Vertical Amplitude P2 : Vertical Linearity P3 ," Vertical Frequency
P4 : Horizontal Frequency Ps : Horizontal Shift
1~2·3 switching: Vertical Position
1N4148
100 nF
lS 10kn
mSync_C=J--\
f L 1SkQ 22nF
_,.,.1 Line~
Flyback
A..,.
VCC1 47 nF:t;
47 kn
VCC1
-12-/-1-7--------------------------- ~ ~~~@~~~~~~~~
1206
91AN2037-29
111.1.3 - High frequency monitor
CHARACTERISTICS Screen: 14" Colour Frame deflection yoke: 11 mH, 7 Q, 750 mA peak-to-peak Vec = + 14 V with flyback generator Frame flyback time: 0.6 ms Vertical frequency: 72 Hz Vertical free-running period: 16 ms (adjustable)
Figure 30
2.2!l
Vee ---4--[::::J--T-~~r---'
+14V
"6F:' .'g3~.
1 N4002
APPLICATION NOTE
Horizontal frequency: 35 kHz (adjustable) Line flyback time : 5.5~s Capture range : 5~s (@sync pulse = 4.7~s) Input signal: negative TTL sync (line + frame) Dissipated power: 1.4 W (heatsink required) Adjustments: · Vertical amplitude · Vertical linearity · Vertical frequency · Horizontal frequency
P1 : Vertical Amplituda P2 : Vertical Unearity P3 : Vertical Frequency P4 : Horizontal Frequency
l..f 10k!l
TTL Sync --C:J--i
fL. 1 Line ---c:1J5 -k!-l-r2I2 nF
Flyback
·___
47nF ;;\;
1N4146
100 nF
1F1rammHe oYo7ken
47kn 68kn
180n
VCC1
1 n
Line Darlington
91AN2037·30
~ ~~~~~g~~~~~~ ---------------- 13/17
1207
APPLICATION NOTE
111.2 - Black & white TV application
CHARACTERISTICS Screen: 20" B & W 110°
- Frame yoke: 30mH. 120. 850mA peak-to-peak - Vee = + 24 V with flyback generator - Frame flyback time: 1ms - Vertical frequency: 50Hz - Vertical free-running period: 24.5 ms - Horizontal frequency: 15625 Hz (adjustable)
Figure 31
Capture range: ±2 ~s Holding range: ±4.5 IlS Input signal: composite video Dissipated power: 2.3 W (100 Crw - heatsink required) Adjustments: · Vertical amplitude · Vertical linearity · Horizontal frequency
P1 : Vertical Amplitude P2 : Vertical Linearity
P3: Horizontal Frequency
1N4002
24 V 2.2 k!l
r--l.+--{=J--- Frame Blanking
Video 1.5 k!l 100 nF
r Input~
220 PF
~
LlnfL 15k!l 22nF
FIYbaCk~
47 nFJ:
+_..,'OOl .-__1N_4_14_8____
680U
91 AN2037-31
1208
APPLICATION NOTE
111.3 - Using composite TTL synchronization
Since the threshold level on input pin 15 is internally set at 1.6 V, the device can directly accept TTL signals. However, a series resistor is required to limit the current sunk by the on-chip transistor (pin 15).
Figure 32'
II REFERENCE I
LT~":O~ ___ _
101cQ ~
91 AN2037·32
If c~mposite sync signal is not available, line and
frame sync signals can be recombined at circuit input as illustrated below.
Figure 33
llr\eSyne Input
IL________~I
FrameSynt Input
~ Ok!ll 15 . L~~OE
91AN2037·33
Figure 34 : Application example
Frame Sync
,,"" ,'----------',
_ - - : c " SkOc - ' - r - - - l 1 5
I
------;!'" - 3300: ~L---..
I L2~~~
47,",
Note : Specified component values are purely theoretical and must be calculated to meet specific application requirements.
91AN2037-34
This arrangement is particularly interesting in applications where the available signals differ from those commonly used. An example is the case where the frame signal is of quite long duration (sometimes as long as frame blanking period). In
such case, efficient synchronization can be achieved by differentiating the signal so that it will behave as a signal of only few lines duration which is the condition required for appropriate frame and line sync separation and also a picture without flag effect.
111.4 - Direct frame synchro.nization The vertical scanning can be directly synchronized by the frame oscillator (pin 1) and without any need of using the synchronization input (pin 15). Figure 35 illustrates an example: In this case, only the line sync pulse is applied to pin 15.
Figure 35
Vee, __~----,~---t-----l16
680 kQ 10 kil
TEA 2037
SL
Positive Frame Sync
1 220 nF
LIl __-§-__
u~
NegatIve UneSync
91 AN2037-35
111.5 - Constant amplitude 50/60 Hz switching In applications requiring 50/60 Hz standard switching feature, the arrangement shown below allows to maintain the amplitude of the oscillator sawtooth (pin 1) constant thus yielding uniform vertical scanning.
Figure 36
VCC1--------1>----
60 Hz Amplitude Adjust
60Hz
T50Hzr - - - - -
I
TEA 2037
I VERTICAL
I
I OSCILLATOR
91 AN2037-36
---------------- ~~~~@~g~f~~~~ ---------------- 15/17
1209
APPLICATION NOTE Figure 37
Figure 39
~ ~ 3.1/-_ _ _ _---'Up'-pe---"Th---,"',-,'hc:.0'-=-d_ _
!g:;
Constant
:z 0:
Amplitude
~--~~~~~~~~~_t
R,
I
TEA 2037
Vee
I L
R,
91AN2037-37
A practical application configuration is illustrated below.
Figure 38
vcc, _ - - -.......- - - - - ,
2.2kQ
10k(}
r-
910knl
TEA 2037
1150nF: T
50 Hz : T conducts
60 Hz : Tturned·off
91 AN2037-38
111.6 - Modifying the line output duration
The line output pulse duration is determined by two internally set threshold levels. This interval can be altered by modifying the charge current of the line oscillator (pin 9)
Figure 41
91 AN2037-39
Figure 40
i 6.6rn---------------------
o 4.8 -----
>
I
I
~ 3.2, g: _
?:.
!'
:
r
l ~
l
I
I
! I
~ t
~
1: ! 1
..~
>
::
I
t
__ ~===-~====~-==--
t
91 AN2037·40
111.7 - Starting the TEA2037 from a +6V power supply
The line oscillator of TEA2037 is capable of starting at a low supply voltage « 6V). The period of oscillation is practically the same as at nominal operation. It is thus possible to initiate the line scanning at a reduced supply voltage (e.g. +6V) and then supply the overall configuration by the power available on the line transformer.
EHT
+ 25 V
COO TIIANSFORMER
1210
LINE YOKE
91AN2037-41
APPLICATION NOTE
IV - DESIGN CONSIDERATIONS
IV.1 - Precautions for interlaced scanning The links interconnecting the ground terminals of Vcc and VCC1 power supplies, as well as those of device decoupling capacitors, must be kept to as short as possible A high value decoupling capacitor can be used for Vcc supply, provided that a good quality low series resistance capacitor is employed. Interlacing is very sensitive to decoupling quality. The value of the decoupling capacitor can vary from 22llF to 100llF. The interconnecting links between the frame oscillator capacitor, the line oscillator capacitor and TEA2037 grounds must be kept to as short as possible.
Perfect line and frame synchronization is achieved by observing the above guidelines and recommendations.
IV.2 - Printed circuit board layout - The usual precautions observed in design of TV
timebase pc boards must be employed The line output stage handles high amounts of voltage and current. Components employed must therefore be appropriately rated, the width of and the clearance between the wiring tracks should be carefully selected. All connections must be as short as possible and all signals at the line frequE?ncy gathered at this section.
- The supply to the frame scanning section of the circuit must not be influenced by the horizontal scanning function, particularly when interlaced scanning is used.
- Generally speaking, interactions on the pc board between the high-gain/low-Ievel and the highcurrent sections of the output stages must be minimized by as much as possible. As indicated in previous chapters, the four center pins of the device must be earthed. The pad used for this purpose must be as large as possible since it acts as the heatsink for the device. A cruciform pad underlying the circuit should be employed.
There should be a single connection to the chassis earth terminal.
- - - - - - - - - - - - - - ~ ~~~;JmR:~g~ _____________1:.,:7.:..,/1...:,7
1211
THERMAL MANAGEMENT
1213
.!.''=1:L-= S~D©GOOS@~[-L1~©H'jOj'OMO@[St(O!]DN©~
APPLICATION NOTE
THE POWER DIP (16+2+2, 12+3+3) PACKAGES
by R. Tiziani
INTRODUCTION
This Application Note is aimed to give a complete thermal characterization of the (16+2+2) power DIP (modified 20 lead DIP with 4 heat transfer leads) and of the (12+3+3) power DIP (modified 18 lead DIP with 6 heat transfer leads) in association with thermal modules integrated on the PCB.
Characterization is performed according with recomendations included in G32-86 SEMI guideline,
by means of a dedicated test pattern developed by SGS-THOMSON. It refers to:
1. Junction to pin thermal resistance RthO-p)
2. Junction to ambient thermal resistance Rth(j-a)
3. Thennal resistance in DC and pulsed conditions, with a typical extemal heat sink.
Most of the experimental work is related to the thermal impedance, as required by the increasing use of switching techiniques.
Figure 1. POWER DIP application on PC board
5-10798
Experimental conditions
The thermal evaluation was performed by means of the test pattern P638, which is a 80x80 mils2 die with a dissipating element formed by two transistors working in parallel and one sensing diode. In order
to characterize the worst case of a high power
density IC, the total size of the element is 3000
mils'2, with a power capability of 20 W. Measurement method is described in Appendix. A.
AN467/0492
1/13 1215
APPLICATION NOTE
Samples with the indicated characteristics were . prepared:
Package
Frame Material
Frame Thickness
Frame Thermal Conductivity
DIP (16+2+2) Copper O.4mm
3.9W/cmDC
DIP (12+3+3) Copper O.4mm
3.9W/cmDC
Measurement of junction to pin thermal resistance Rth(j-p) is performed by holding the package (with the heat transfer leads soldered on a copper plate)
against a water cooled heat sink, according with fig. 2. A thermocouple placed in contact with the plate measures the reference temperaturE!. For junction to ambient thermal resistance Rth(j-a) the samples are suspended horizontally in a one cubic foot box, to prevent drafts. The effect of "on board" external heat sinks shown in fig. 1 is quantified, using a test board which has
two 4 x 4 cd dissipating areas, one of each side
of the package. These areas are mechanically reduced in order to study the effect of their size on thermal performance. The measurement circuit shown in fig. A3 is used for all of the thermal evaluations.
Figure 2. Measurement of Rth(j-p)
PRESSURE eLi PPI NG
-
CONNECTION THIN WIRES
I r-'-'=t
HEAT TRASFER LEAD
SIGNAL LEAD -~\\'~'11~~~~,\~\. .:_::;___ SOLDERED JOINT
COPPER FOIL - - ._ / { WATER-COOLED COPPER-BLOCK
\
LTHERMAL GREASE
THERMOCOUPLE
5-9783
JUNCTION TO PIN THERMAL RESISTANCE
The dependance of Rth(j-p) on the dissipated power is negligeable compared to the absolute value: starting from 1 Watt to 10 Watts the Rth(j-p) increases of about O.5C/W due to the lowering of silicon thermal conductivity with the increasing of ·temperature. An important contribution to Rth(j-p) is given by the silicon die and in fig. 3,4 is showed the relationship between Rth(j-p) and the dissipating area existing on the silicon die (power diodes, poVlier transistors, high current resistors), for differ- .
ent die sizes.
In the figures two curves area reported: the lower one is referring the Rth(j-p) measured at the pin stand-off, the upper one is referring to the Rth(j-p) measures at 1.5 mm from the pin stand-off (1.5 mm is the typical thickness of FR4 board).
The upper curve must be used for the application in which the heat sink is placed in the lower side of PCB and the lower curve must be used when the heat sink il'j placed on the upper side of PCB.
2/13 1216
"~ '11 Si'GIIDS©O-O1@H~~O~mOMO@SU!OJDN©® - - - - - - - - - - - - - -
Figure 3· POWER DIP 16+2+2 Rlh(j.p) vs on die dissipating area
APPLICATION NOTE
POWER DIP 16+2+2
15
14 ...................
T
H E
13
R
M 12
A
l
11
R
E
S 10
I
S T 9
A
N C
8
E
P638 THERMAL JEST CHIP
························b·I·E··PAb'·~··1·52··x··1·60 sq. mils
= DIE SIZE 160 x 160 sq.mils
for heat sink on PCB lower side
U·pin) 7
for heat sink on PCB upper side
(CIW)
6 0
2
4
6
8 10 12 14 16 18 20 22
DISSIPATING AREA (x 1000 sq. mils)
Figure 4 · POWER DIP 12+3+3 Rlh(j.p) vs on die dissipating area
POWER DIP 12+3+3
13
12
T H
E 11 R M
A 10 L
P638 THERMAL TEST CHIP
DIE PAD = 165 x 220 sq. mils DIE SIZE = 160 x 160 sq.mils
R E
9
S
I S
8
T
A
N 7
C
E
forh.eatsin~.onPGBlo'Ner.side...
U·pin) 6
for heat sink on PCB upper side
(CIW)
5 0
2
4
6
8 10 12 14 16 18 20 22
DISSIPATING AREA (x 1000 sq. mils)
--------------------------- ~~i~~~~~'~~1 -------------------------3-/1-3
1217
APPLICATION NOtE
JUNCTION TO AMBIENT THERMAL RESISTANCE
Fig. 5,6 give the junction to ambient thermal resistance Rth(j-a) of the package vs dissipated power; it evidences the effect of the board in improving the exchange of the heat towards the ambient. The upper curve refers to samples suspended in. air, with eight thin wire connecting the dissipating tran-
sistors and the sensing diode. The lower curve is obtained with a very large heat sink (35 11m thick
4 x 4cni copper area for each side) while the other
curve refers the packages mounted on board with no heat sink.
Rth is decreasing when power is increased, due to a better heat transfer efficiency at higher temperature.
Figure 5 - RthU.a) of DIP (16+2+2) package vs dissipated power
POWER DIP 16 + 2 + 2
110~-----------------------------------------,
P638 THERMAL TEST CHIP: DIE PAD ~ 152 x 160 sq. mils
T H E 90 R M A L
DIE SIZE 160 x 160 sq.mils DISSIPATING AREA DIE ~ 80 x80 sCl:mils
FLOATING IN AIR
R E S I S T A N C E
O-a)
(C/W)
70
MOUNTED ON PCB:
50 ~ ·········~c-c·"")I(:lIb-~---J)~K="==."W'!I)IIT(EH-'--N'--O"-'.H:.:.;.*E'*.A:.:..:.:T.::S::I.N:::K:~*
WITH COPPER HEAT SINK 32 sq. em area
* * 30L---__L-____)IL ( -____L-__~L-__~ )I(____~ )I(______
o
Q5
1
1.5
2
~5
3
a5
DISSIPATED POWER (Watt)
4/13
~ ~~~m~~~91 ----------------------
1218
APPLICATION NOTE
Figure 6 - Rth(j-a) of DIP (12+3+3) package vs. dissipated power
POWER DIP 12 + 3 + 3
100r---------------------------------------------.
P638 THERMAL TEST CHIP: DIE PAD = 165 x 220 sq. mils
T H E R M A L
R E S I S T A N
C
E
(j-a)
(C/W)
DIE SIZE 160 x 160 sq. mils DISSIPATING AREA DIE", 80x80 sq,mils
80
FLOATING IN AIR
60
" * ~~---;j'~-*M~~O( ~UN~TE-D~(*ON-P-CB-~:( --4
40
WITH NOHEAT SINK
* * * * * WITH COPPER HEAT SINK 32 sq_ cm area
2 0 L -_ _ _ _J -_ _ _ _- L_ _ _ _~_ _ _ _ _ _L __ _ _ _~_ _ _ __ L_ _ _ _~
o
0.5
1
1.5
2
2.5
3
3.5
DISSIPATED POWER (Watt)
The effect of on board heat sinks with different size is summarized in fig. 8,9; thermal resistance in given vs the side I of the two thick copper squares, obtained in the lower side of the test board and dedicated to heat dissipation (see fig. 7 for test board). Standard thickness of 35).!m was used for the characterization as the most part of PCb application but a large improvement can be easily ob-
tained with a thicker copper heat sink on board: 70).!m and 105).!m (respectively 2 and 3 oz.) are strongly increasing the thermal performances of the considered POWER DIP application. These solutions can be attractive for low complex PC board with a cost saving in avoiding large external heat sink or forced ventilation.
Figure 7 - Test board with two "on board" square heat sinks vs side I
P.C. BOARD
1219
APPLICATION NOTE
Figure 8 - Rlh(j-a) of POWER DIP 16+2+2 vs side I for heat sink on the PCB lower side
50
T 45·
H E R M 40 A L
R E
35
S
I
S T 30
A
N
C
E 25
(CIW)
20 0 0.5
POWER DIP 16 + 2 + 2
P638 THERMAL TEST CHIP
DIE PAD = 152 X 160 sq. mils DIE SIZE: 160 x 160 sq.mils
"ON BOARD" COPPER AREA THICKNESS:
35J.1m
70j.1m
10!}lm 1.5 2 2.5 3 3.5 4 4.5 5 5.5
side I ( em) on PCB heat sink
Figure 9 - Rlh(j-a) of POWER DIP 12+3+3 vs side I for heat sink on the PCB lower side
POWER DIP 12 + 3 + 3
45
P638 THERMAL TEST CHIP
T 40
H E
R M 35 A L
R E
30
S
I
S T 25
A
N
C
E 20
(CIW)
Pd = 2 Watt
10!f1m
15 0 0.5
1.5 2 2.5 3 3.5 4 4.5 5 5.5 side I ( em ) on PCB heat sink
-6/-13------------------------- ~~~~gml~~ ---------------------------
1220
APPLICATION NOTE
TRANSIENT THERMAL RESISTANCE
The effect of single pulse of different length and height, is shown in fig. 10,11 for POWER DIP 16+2+2 and 12+3+3. Thicker copper heat sink on
PCB is effective also for short pulse width (less 1 sec.). Due to a significant thermal capacitance a correspondingly long risetime, single pulse up to 10W can be delivered to the system for 1s with acceptable junction temperature increase.
Figure 10 - DIP 16+2+2 Transient thermal resistance for single pulses
Power DIP 16 + 2 + 2 SINGLEPULSE
T H E R M A L 10
I M P
E D A
N C
E
MOUNTED ON BOARD
P638 THERMAL TEST CHIP
die size: 160x160sq.miis
Pd.~2Wl.ltt ...
A = 35 um thick no heat sink B = 35 um thick 4x4 sq. cm on board Cu area
C = 105 um thick 4x4 sq. em on board Cu area
(CIW) 1
0.001
0.01
0.1
1
10
100
TIME OR PULSE WIDTH ( sec. )
1000
_ _ _ _ _ _ _ _ _ _ _ _ 51'1 SGS-THOMSON _ _ _ _ _ _ _ _ _ _ _7_/13
'], 1:ilD©OO@~~rn©mill@UiIlD©® .
1221
APPLICATION NOTE
Figure 11 - DIP 12+3+3 Transient thermal resistance for single pulses
POWER DIP 12+3+3
SINGLE PULSE
T
H
E
R
M
A L
10
MOUNTED ON BOARD
P638 THERMAL TEST CHIP die size: 160x160 sq.mils
I M P E D A N C E
(C/W)
C = 105 um thick4x4 sq.cm pn board Cu area 1 ~~~Will_ _LLLUWL-J-L~lliL~~illllL-L~LW~-LLL~
0.001
0.01
0.1
1
10
100
TIME OR PULSE WIDTH ( sec. )
1000
Repeatition of pulses with defined Pd, period and duty cycle DC (ratio between pulse length and signal period), gives rise to an average temperatu re increase:
~Tavg = Rth X Pdavg = Rth X Pd X DC
Junction temperature is oscillating about the mean value as qualitatively shown in fig. 12. The transient thermal resistance corresponding to the upper limit (peak transient thermal resistance) is reported in fig. 13,14 and depends on pulse length and duty cycle. It can be noticed that DC becomes less effective for longer pulses.
8/13
---------------------------
~~i~@~~~m~~
---------------------------
1222
Figure 12
APPLICATION NOTE
T E
M
P 50
E R
A
T 40
U R E
R 30
I S E
20
(A.U.) 0
20
40
60
80
100
TIME (A. U.)
Figure 13 - Peak Transient Thermal resistance of DIP (16+2+2)
POWER DIP 16 + 2 + 2
P638 THERMAL TEST DIE
P
E
A
DC=(].5
K
T
DC = 0.4
R A 10 DC=0,3
N
S
I
E
N
T
QC,,;().1
..... PULSE WIDTH
R
t
DC = DUTY CYCLE = - - - - -
h
PULSE PERIOD
Pd = 5 Wat~
mounted on PCB with 35 urn thick 4x4 sq.cm on board area
_ _ 1L-~LLUllll--L~~llL~-LLU~
~~llWL-~LU~
(OW) 0.1
10
100
1000
10000
TIME OR PULSE WIDTH (millisec.)
______________ 51 SGS·1HOMSON ____________9_/13
·J II [ljJG©IliI@~[.~©'ir]l@j!G©i0
1223
APPLICATION NOTE
Figure 14 - Peak transient thermal resistance of DIP (12+3+3)
POWER DIP 12+ 3 + 3
P638 THERMAL TEST DIE
P E A
K
T 10 R A N S I
E
N
T
R
DC = 0.1
t
h
(C/W)
'1 0.1
PULSE WIDTH D,C. = DUIYCYCLE,,= -".,-".,-".,--."..~
PULSE PERIOD
mounted on PCB with 35 um thick 4x4 sq.cm on board area
10
100
1000
TIME OR PULSE WIDTH (millisec.)
10000
-10-/1-3------------------------ ~~ii@~~~19~ ---------------------------
1224
APPLICATION NOTE
APPENDIX
TEST PAITER P638 For thermal measurement Test patterm P638 is designed for thermal measurement following SEMI guideline G32 (see SEMI
Standard Handbook, 1986/87).
It has two bipolar power transistor with area of about 3000 sq. mils and one sensing diode (see Fig. A1). The lay-out is optimized in order to have a uniform temperature, once the two transistors are powered: the sensing diode is placed at the center of this area.
Figure A1 - P638 test pattern
: ::
:
:
: : :
.... ...
CB E
p N E BC
--------------------------- ~~it~~~~~~~ ----------~-------------11-/1-3
1225
APPLICATION NOTE
Die size of single unit is 80 x 80 sq. mils; wafer thickness is about 280 microns.
The relationship between the forward voltage VI of the diode at a constant current of 100 IlA and the
temperature is linear, with a coefficent K = 1.85
mV/C (see Fig. A2).
Therefore changes ~Tj in junction temperature of the dissipating element formed by the two transistors, can be easily obtained from the diode for-
ward voltage drop:
~ Tj= (Vf1- Vf2) K
(V12 is the diode forward voltage at ambient temperature and Vf1 is the voltage when the transistors are dissipating).
For thermal resistance evaluation the measurement circuit is showed in Fig. A3.
Figure A2 - Calibration curve (sensig diode).
CALIBRATION CURVE
P638 TEST PATTERN
mV
:::-------"'---------1-- aF
-.------1----- wR
I
A 650 ------------'
Id = 100 uA
R
·
I
D
600
a V
L
T
A
: :550 ---------
I
:I -1I----_--
G
E
o
~
~M
M
100
1~
140
160
TEMPERATURE ( C )
Figure A3 - Measurement System
1 U
10
-12-/1-3------------------------ ~~i~~i~'9~ ---------------------------
1226
Tipical conditions are:
Pd (Watt) 0.1 0.2 0.3 0.5 0.75 1.0 1.5 2.0 3.0 5.0 10.0
Vee (Volt) 1.0 2.0 3.0 5.0 7.5 10.0 15.0 20.0 15.0 25.0 25.0
Ie (rnA) 100 100 100 100 100 100 100 100 200 200 400
Each transistor is able to dissipate up to 10 Watt due to presence of second breakdown.
APPLICATION NOTE
----------------------------- ~~f~@~g~~~~ -------------------------1-3-/1-3
1227
APPLICATION NOTE
DESIGNING WITH THERMAL IMPEDANCE
BY T.HOPKINS, C.COGNETTI, R.TIZIANI REPRINT FROM "SEMITHERM PROCEDINGS" S.DIEGO (U.S.A.) 1988.
ABSTRACT
Power switching techniques used in many modern control systems are characterized by single or repetitive power pulses, which can reach several hundred watts each. In these applications where the pulse width is often limited to a few milleseconds, cost effective thermal design considers the effect of thermal capacitance. When this thermal capacitance is large enought, it can limit the junction temperature to within the ratings of the device even in the presence of high dissipation peaks. This paper discusses thermal impedance and the main parameters influencing it. Empirical measurements of the thermal impedance of some standard plastic packages showing the effective thermal impedance under pulsed conditions are also presented.
INTRODUCTION
Power switching applications are becoming very common in many industrial, computer and automotive ICs. In these applications, such as switching power supplies and PWM inductive load drivers, power dissipation is limited to short times, with single or repeated pulses. The normal description of the thermal performance of an IC package, Rth(j -a) (junction to ambient thermal resistance), is of little help in these pulsed applications and leads to a redundant and expensive thermal design.
This paper will discuss the thermal impedance and the main factors influencing it in plastic semiconductor packages. Experimental evaluations of the thermal performance of small signal, medium power, and high power packages wil be presented as case examples. The effects of the thermal capacitance of the packages when dealing with low duty cycle power dissipation will be presented and evaluated in each of the example cases.
THERMAL IMPEDANCE MODEL FOR PLASTIC PACKAGES
The complete thermal impedance of a device can be modeled by combining two elements, the thermal resistance and the thermal capacitance.
The thermal resistance, Rth, quantifies the capability of a given thermal path to transfer heat. The general definition of resistance of the thermal path, which includes the three different modes of heat dissipation (conduction, convection and radiation), is the ratio between the temperature increase above the reference and the heat flow, DP, and is given by the equation:
L1T L1T Rth=--
L1P L10
L1t
Where: L10 = heat L1t = time
Thermal capacitance, Cth, is a measure of the capability of accumulating heat, like a capacitor accumulates a charge. For a given structural element, Cth depends on the specific heat, c, volume V, and density d, according to the relationship:
Cth=cdV
The resulting temperature increase when the element has accumulated the heat 0, is given by the equation:
L1T = L10/Cth
The electrical analogy of the thermal behaviour for
a given application consisting of an active device,
package, printed circuit board, external heat sink
and external ambient is a chain of RC cells, each
having a characteristic time constant:
.
'1:= RC
To show how each cell contributes to the thermal impedance of the finished device consider the simplified example shown in figure 1. The example device consists of a dissipating element (integrated circuit) soldered on a copper frame surrounded by a plastic compound with no external heat sink. Its equivalent electrical circuit is shown in figure 2.
The first cell, shown in figure 2, represents the thermal characteristics of the silicon itself and is characterized by the small volume with a correspondingly low thermal capacitance, in the order of a few mJ/C. The thermal resistance between the junction and
AN261/0189
1114 1229
APPLICATION NOTE
the silicon/slug interface is of about 0.2 to 2 °C/W, depending on die size and on the size of the dissipating elements existing on the silicon. The time constant of this cell is typically in the order of a few milliseconds.
The second cell represents the good conductive path from the silicon/frame interface to the frame periphery. In power packages, where the die is often soldered directly to the external tab of the package, the thermal capacitance can be large. The time constant for this cell is in the order of seconds.
From this point, heat is transferred by conductionto the molded block of the package, with a large thermal resistance and capacitance. The time constant of the third cell is in the order of hundreds of seconds.
After the plastic has heated, convection and radiation to the ambient starts. Since a negligible capacitance is associated with this phase, it is represented by a purely resistive element.
Figure 1 : Simplified Package Outline.
When power is switched on, the junction temperature increase is ruled by the heat accumulation in the cells, each following its own time constant according with the equation: ~T = Rth Pd [1 - e(II1)]
The steady state junction temperature, Tj, is a function of the Rth 0 a) of the system, but the temperature increase is dominated by thermal impedance in the transient phase, as is the case in switching applications.
A simplified example of how the time constants of each cell contribute to the temperature rise is shown in figure 3 where the contribution of the cells of figure 2 is exaggerated for a better understanding.
When working with actual packages, it is observed that the last two sections of the equivalent circuit are not as simple as in this model and possible changes will be discussed later. However, with switching times shorter than few seconds, the model is sufficient for most situations.
Figure 2 : Equivalent Thermal Circuit of Simplified.
< MOLD ~-~-..:.:r!~F"-,RACHMIP E 5-10621
R fh si R th frame R th mold
T'L_~1J1-· ~L-I~J---l-LUT_ Ja~.mb
C In 51 C Ih frame C th mold
~-106n
Figure 3: Time Constant Contribution of Each Thermal Cell (qualitative example).
2/14 1230
'.118' 8.B'
B.t
·
tB
tIl
tBBB
T1t'E OR Pl.l..SE UIOTII ( A.U.)
APPLICATION NOTE
EXPERIMENTAL MEASUREMENTS
When thermal measurements on plastic packages are performed, the first consideration is the lack of a standard method. At present, only draft specifications exist, proposed last year and not yet standardized (1).
The experimental method used internally for evaluations since 1984 has anticipated these preliminary recomendations to some extent, as it is based on test patterns having, as dissipating element, two power transistors and, as measurement element, a sensing diode placed in the thermal plateau arising when the transistors are biased in parallel.
Figure 4.
The method used has been presented elsewhere (2) for the pattern P432 (shown in figure 4), which uses two small (1000 sq mils) bipolar power transistors and has a maximum DC power capability of 40 W (limited by second breakdown of the dissipating elements).
A similar methodology was followed with the new H029 pattern, based on two D-Mos transistors (3) having a total size of 17.000 sq mils and a DC power capability of 300 W on an infinite heat sink at room temperature (limited by thermal resistance and by max operating temperature of the plastics).
a) P432 Test Die
b) P432 Measurement System
D.C. SUPPLY
PULSE GENERATOR
D.C. SUPPLY
FAST DVM
5 -1062311
3/14 1231
APpLICATION NOTE
Using the thermal evaluation die, four sets of measurements were performed on an assortment of insertion and surface mount packages produced by SGS-Thomson Microelectronics. The complete characterization is available elsewhere (4). The four measurements taken were:
Figure 5.
1) Junction to Case Thermal Resistance (Power
Packages)
2) Junction to Ambient Thermal Resistance
3) Transient Thermal Impedance (Single Pulse)
4) Peak Transient Thermal Impedance (Repeated
Pulses)
.
a) H029 Test Die
4/14
1232
b) H029 Measurement System
D.C. SUPPLY
FAST DVM
STORAGE
SCOPE
5-10624 11
Figure 6 : Set-up for Rth (j - c) Measurement.
APPLICATION NOTE
PRESSURE CLIPPING
CONNECTION THIN WIRES
1WATER-COOLEO COPPER SLOCK
~THERMAL GREASE
THERMOCOUPLE
5-97&5
The junction to case thermal resistance measurements were taken using the well known setup shown in figure 6 where the power device is clamped against a large mass of controlled temperature.
The junction to ambient thermal resistance in still air, was measured with the package soldered on standard test boards, described later, and suspensed in 1 cubic foot box, to prevent air movement.
The single pulse transient thermal impedance was
measured in still air by applying a single power pulse of duration to to the device. The exponential temperature rise in response to the power pulse is shown qualitetively in figure 7. In the presence of one single power pulse the temperature, /!,.Tmax, reached at time to, is lower than the steady state temperature calculated from the junction to ambient thermal resistance. The transient thermal impedance Ro, is obtained from the ratio /!,.Tmax/Pd.
Figure 7 : Transient Thermal Response for a Single Pulse.
Tamb _L__+--____---=="'-____
Pd J_____ .Il-_ __
10
5-978L
5/14
1233
APPLICATION NOTE
The peak transient thermal impedance for a series of repetitive pulses was measured by applying a string of power pulses to the device in free air. When power pulses of the same height, Pd, are repeated with a given duty cycle, DC, and the pulse length,
tp, is shorter than the total time constant of the sys-
tem, thetrain of pulses is seen as acontiuous source with mean power level given by the equation:
Pdavg = Pd DC
Figure 8 : Transient Thermal Response for Repetitive Pulses.
(Pb/Sn) die attach. The tab of the package is a 1.5 mm thick copper alloy slug. The thermal model of the MULTIWATT, shown in figure 9b, is not much different from that shown in figure 2. The main difference being that when heat reaches the edge of the slug, two parallel paths are possible ; conduction towards the molding compound, and convection and radiation towards the ambient. After a given time, convection and radiation taked place from the plastic.
Figure 9.
a) MULTIWATT Assembly
-Yb:~0\ I I I I I I I
' ...mb - - - i - - - . - - - - - - - - - - -
Pd'
b) Equivalent Thermal Circuit
On the other hand, the silicon die has a thermal time constant of 1 to 2 ms and the die temperature is able to follow frequencies of some kHz. The result is that Tj oscillates about the average value:
ATjavg = Rth Pdavg
The resulting die temperature excursions are shown qualitatively in figure 8. The peak thermal impede ance, Rthp, corresponding to the peak temperature, DTmax, at the equilibrium can be defined:
Rthp =ATmax/Pd = F (tp, DC)
The value of Rthp is a function of pulse width and duty cycle. Knowledge of Rthp is very important to avoid a peak temperature higher than specified values (usually 150·C). .
EXPERIMENTAL RESULTS
The experimental measurements taken on several of the packages tested are summarized in the following sections.
MULTIWATT PACKAGE The MULTIWATT (R) package, shown in figure 9a, is a multileaded power package in which the die is attached directly t9 the tab of package using a soft solder
R th mold
T I
C th SI
C th frame
R th
S -10625
TC'tmb
Using the two test die, the measured junction to case thermal resistance is :
P432
Rth U c) = 2'C/W
H029
Rth U c) = O.4"C/W
The measured time constant is approximately 1 ms for each of the two test patterns, but the two devices have a different steady state temperature rise.
6/14
1234
APPLICATION NOTE
The second cell shown in figure 9 is dominated by the large thermal mass of the slug. The thermal resistance of the slug, Rthslug is about 1 °CfW and the thermal time constant of the slug is in the order of 1 second.
The third RC cell in the model has a long time constant due to the mass of the plastic molding and its low thermal conductivity. For this cell the steady state is reached after hundreds of seconds.
For the MULTIWATT the DC thermal resistance of the package in free air, Rth j a, is 36 °CfW with the P432 die and 34SCfW with the H029 die.
Figure 10 shows the single pulse transient thermal impedance for the MULTIWATT with both the P432 and H029 test die. As can be seen on the graph, the package is capable of high dissipation for short periods of time. For a die like the H029 the power device is capable of 700 to 800 W for pulse widths in the range of 1 to 10 ms. For times up to a few seconds the effective thermal resistance for a single pulse is still in the range of 1 to 3 °CfW.
The peak transient thermal impedance for the MULTIWATT package containing the P432 die in free air is shown in figure 11.
POWER DIP PACKAGE
The power DIP package is a derivative of standard small signal DIP packages with a number of leads connected to the die pad for heat transfer to external heat sinks. With this technique low cost heat sinks can be integrated on the printed circuit board as shown in figure 12a. The thermal model of the power DIP, shown in figure 12b accounts for the external heat sink on the circuit board by adding a second RC cell in parallel with the cell corresponding to the molding compound.
In this model, the second cell has a shorter time constant than for the MULTIWATT package, due in large part to the smaller quantity of copper in the frame (the frame thickness is 0.4 mm compared to 1.5 mm). Thus the capacitance is reduced and the resistance increased.
The increased thermal impedance due to the frame can partially be compensated by a better thermal exchange to the ambient by adding copper to the heat sink on the board. The DC thermal resistance between the junction and ambient can be reduced to the same range as the MULTIWATT package in free air, as shown in figure 13.
Figure 10 : Transient Thermal Response MULTIWATT Package.
'e"n
"~"'
Pd .. 2 II ILoal! 9 In air
:=
!':l
III
'"""'
HE'l 2
diD siz .. 34.808 q.mi l:5
e on die dt ~lpalin9 co .. 16.6 ~q.mt l~
Pd .. 2 lJa l rrounlcd on board
B.BBI
B.Bl
B.l
lB
lBB
lBBB
TltE OR PULSE LJIoru ( s )
7/14 1235
APPLICATION NOTE Figure 11 : Peak Thermal Resistance MULTIWATT Package.
Figure 12.
'"u"-
28
DC - 0.5
..,
l!:! I!'
:.II.;">,;
!'" .i'..!"...i. 19
:z::
---------- B.4
8.3
~ 0.2
-
~
I!l Uaz::I
f!!
~"a":
5
~
~ ~
Pd - 5 IJaH free air
DC-DUTY eve E____ - _f.UJ._~_"!. DJ!L ___
PULSE REPETI ION PERIOD
B.1
19
10B
1999
TIrE DR PULSE LJIDTH ( 1115 )
a) Power DIP Package
o q~~ R th mold R!hSi R thlr~mel-y~ Tamb
Tj
C th mold
C thsi
LA~~ C thtrame y~Tamb
5 - 10626
C th board
b) Equivalent Thermal Circuit
8/14
1236
APPLICATION NOTE
Figure 13 : Rth (j - a) vs. PCB Heat Sink Size 12 + 3 + 3 Power Dip.
- ''""
~
u
...
z:
''""
'~"
...a:
0 ~
z:
~
t:;
..,z:
::J
'."..
tJ
1\
\
~ ~
az::
~ ~
''"..""".J
~
....
Pd · 2 LbH
~ --.
!!l '"
~
H.IIB II.SII 1.IIH 1.SH 2.HH 2.SI1 3.HH 3.S0 4.00
1 ( em )
As a comparison, figure 14 compares the thermal performance of the power DIP and the MULTIWATT package. It is clearly seen that even though the DC
thermal resistance may be similar, the MULTIWATT is superior in its performance for pulsed applications.
Figure 14 : Transient Thermal Impedance for Single Pulses in Power DIP and MULTIWATT Packages.
S0
~
SIN LE
Pd - 2
DIP(12.3. ) wilh
6 SU. eM 0 BOARD
HEAT SINK AREA
IR
e.l
Ie
lBB
TIf""E OR PULSE IJIDTH ( 5 )
IBBB
9/14
1237
APPLICATION NOTE
STANDARD SIGNAL PACKAGES
In standard, small signal, packages the easiestthermal path is from the die to the ambient through the molding compound. However, if a high conductivity frame, like a copper lead frame, is used another path exists in parallel. Figure 15 shows the equivalent thermal model of such a package. The effectiveness of a copper frame in transferring heat to the board
can be seen in the experimental results in DC conditions.
Table 1 shows the thermal resistance of some standard signal packages in two different conditions ; with the device floating in still air connected to the measurement circuit by thin wires and the same device soldered on a test board.
Table 1 : Thermal Resistance of Signal Packages
Package DIP 8 DIP 14 DIP 16 DIP 20 DIP 14 DIP 20 DIP 24 DIP 20 SO 14 PLCC 44
Frame Thickness & Material (OA mm Copper) (OA mm Copper) (OA mm Copper) (OA mm Copper) (0.25 mm Copper) (0.25 mm Copper) (0.25 mm Copper) (0.25 mm Alloy 42) (0.25 mm Copper) (0.25 mm Copper)
Rth (i-a) Floating 125-165 98-128 95-124 85-112 115-147 100-134 67-84 158-184 218-250 66-83
°C/W on Board 78-90 64·73 62-71 58-69 84-95 76-87 61-68
133-145 105-180
48-72
The transient thermal resistance for single pulses for the various packages are shown in figures 16 through 20.
The results of the tests, as shown in the preceding figures, show the true capabilities of the packages. For example, the DIP 20 with a Alloy 42 frame is a typical package used for signal processing applications and can dissipate only 0.5 to 0.7 W in steady state conditions. However, the transient thermal impedance for short pulses is low (11 C/W for tp = 100 ms) and almost 7 Watts can be dissipated for 100 ms while keeping the junction temperature rise belowaO'C.
The packages using a 0.4 mm Copper frame have a low steady state thermal resistance, especially in
the case of the DIP 20. The thicker lead frame increases the thermal capacitance of the die flag, which greatly improves the transient thermal impedance. In the case of the DIP 20, which has the largest die pad, the transient Rth for 100 ms pulses is about 4.3'CIW. This allows the device to dissipate an 18 Watt power pulse while keeping the temperature rise below 80'C.
As with the previous examples the peak transient thermal impedance for repetitive pulses depends on the pulse length and duty cycle as shown in figure 14. With the signal package, however, the effect of the duty cycle becomes much less effective for longer pulses, due primarily to the lower thermal capacitance and hence lower time constant of the frame.
Figure 15.
t
5 - 10627
a) DIP Package Mounted on PCB 10/14 1238
P 1h mold
Tamb
~Tamb
S _10621111
C th l~d C th board
b) Equivalent Thermal Circuit DIP Package on PCB
APPLICATION NOTE
Figure 16 : Transient Thermal Impedance DIP 20 (alloy 42).
188
-
:3
u "
...
V SINC LE P .JLSE
Pd · 1 W II mounle on board
/
~ a:
~
In W
/
'~" 18
~
V
on die di:)~ipDling a eo .. 2.666 ~q.mil:t
tz-:
I!l
Iazn::
I!'
I
die pad· 25 x 1GB q.mil~
B.81l1
8.Bl
B.l
III
TIrE OR PULSE WIDlll ( 5 )
10B
lBBIl
Figure 17 : Transient Thermal Impedance 0.4 mm Copper Frame DIP Packages.
TIllE OR FULSE WID T~ ( 5 J
11/14 1239
APPLICATION NOTE
Figure 18 : Transient Thermal Impedance 0.25 mm Copper Frame DIP Packages.
IIIB F=="'j====j==="j====q:===:q===""l
on die i&&lpalin area = 2. Be &q.mlls
28 mount.ed an boa,..d Pd · 2 tt SIrlGL PULSE
DIP 28 : DIP 24 :
BB x 135 ... mi I. 18 x 128 · · mib 58 x 28B ... mil.
B.B81
·O.BI
B.I
I
19
nno: OR PULSE WIDTH ( s )
IBB
IBBB
Figure 19: Transient Thermal Impedance 0.25 mm Frame PLCC Package.
,
58
SIt GLE PULSE
~
.':":.
mounl donSMPC 5 board
Pd · !Joll
/
Ij z:
1=
...I!l
III 18
'"...J
i!:
V
'V
'~"
t-
/
od · 2Se die
2Se "'l.rnl ·
ili
die ize · 35. 88 eq.mile
IzI:I
~
V
on die dl slpatlng a ea = 2.BBB sq.mils
0.881
0.01
3'.1
Ie
lee
188e
nno: OR PULSE L/loTli ( 5 )
12/14 1240
APPLICATION NOTE Figure 20 : Transient Thermal Impedance 0.25 mm Copper Frame S014 Package.
1DD
:..3.
u
;'ir1";=:
''""
..J
18
~
''~""
0z-: ~ Uz:l
e0::
SING E PULS
5 Wall --->\<- - 2 Wall
mount.d on 5M CB1 B 5G5 board
ID
lOu
TItI: OR PL1.5E WIDTH ( ms )
1000
10000
Figure 21 : Peak Thermal Impedance 0.25 mm Copper Frame 14 Lead DIP.
~S8
~
~
u
~
0~ ,
w
'a"!
;::
:.'".3. ~
!!l
'" 10
I'"-
~ Wn.
t
0.1
D': = 0.5
8.4 8.3 8.2
0.1
· I
I
I
I
I
-
~/
~~/~/
I /- /
+-..........--..-~-~ //
--
//
-",.,..-
/
/ / Pd · 2 WaH
-------- moun d on board
~ die pad = lOB. E:'; S'1omils
I
coppe rrome lh ickne::." '" 6.4 rrvn
DCoDUTY eye E:- · __ . f.U.!.",!,. ~Ll .TtL ____
I
PULSE REPETIT ON PERIOD
10
180
T1~t[ OR PULSE WIDTH ( WI> )
13/14
1241
APPLICATION NOTE
CONCLUSION
This paper has discussed a test procedure for measuring and quantifying the thermal characteristics of semiconductor packages. Using these test methods the thermal impedance of standard integrated circuit packages under pulsed and DC conditions were evaluated. From· this evaluation two important considerations arise:
1) The true thermal impedance under repetitive pulsed conditions needs to be considered to maintain the peak junction temperature within the rating for the device. A proper evaluation will result in junction temperatures that do not exceed the specified limits under either steady state or pulsed conditions.
2) The proper evaluation of the transient thermal characteristics of an application should take into account the ability to dissipate high power pulses
allowing better thermal design and possibility reducing or eliminating expensive external heat sinks when they are oversized or useless.
REFERENCES
(1) SEMI Draft Specifications 1377 and 1449, 1986
(2) T. Hopkins, R. Tiziani, and C. Cognetti, "Improved thermal impedance measurements by means of a simple integrated structure", presented at SEMITHERM 1986
(3) C. Cini, C. Diazzi, D. Rossi and S. Storti, "High side monolithic switch in Multipower-BCD technology", Proceedings of Microelectronics Conference, Munchen November 1986
(4) Application Notes 106 through 110, SGSTHOMSON Microelectronics, 1987
14/14
1242
APPLICATION NOTE
THERMAL MANAGEMENT IN SURFACE MOUNTING
The evolutionary trends of integrated circuits and printed circuits boards are, in both cases, towards improved periormance and reduced size, From these points of view, a factor of major importance has been mutual thermal interaction between ICs, even those with low dissipation.
It follows then that thermal design of medium and high density applications has evolved to include factors such as power effects, die size, package thermal resistance, integration level of active devices and substrate type. Added to this a trend towards greater use of switching techniques exists.
Today, in order to design reliable application circuits, it is necessary to have complete data on package thermal response characteristics. In fact, it is a well known and long established fact that device lifetime has an exponential relationship with junction temperature.
PRELIMINARY CONSIDERATIONS
Heat dissipation for DIPs with a low thermal conductivity frame (e.g. Alloy42) is due to convection and irradiation from an emiting area corresponding to the silicon die and the package die pad.
Since heat transmission through the lead frame is very poor, dissipation does not depend greatly on substrate type. In fact, samples soldered on printed circuit boards, or inserted in connectors have nearly the same dissipation capability as samples suspended in air. The difference, in the range of just 10%, is commonly ignored and specifications for insertion ICs only give one thermal resistance value, which is more than adequate for good thermal design.
The question then arises, is the approximation valid for SO and PLCC packages?
The answer is no !Thermal characteristics for these devices are influenced by many factors.
1) Device Related Factors
size of the dissipating element
dissipation level
pulse length and duty cycle
2) Package Related Factors
· thermal conductivity of the frame
· frame design
3) Substrate Related Factors
· thermal conductivity of the substrate
· layout
Therefore a number of parameters can change the thermal characteristics. These cannot be described by a single thermal resistance, in fact a set of experimental curves gives the best presentation.
JUNCTION TO AMBIENT THERMAL RESISTANCE Rth(j-a)
RthU-a) represents the thermal resistance of the system and comprises the silicon die, the package, and any thermal mass in contact with the package to dissipate heat to the ambient.
At a given dissipation level Pd, the increase in junction temperature L\Tj over ambient temperature Ta is given by :
L\Tj = RthU-a) X Pd
Rthlj-a) is made up of many elements both within the device and external to it. If the device is considered alone, Rth(j-a) is given by the dissipation path from the silicon die to the leadframe, to the molding compound, to the ambient. Experimental values are very large in this condition, especially for small packages such as Small Outline types. However, this situation is not met in practice and experimental data included in the present work indicates the worst case (floating samples). In most applications, Suriace Mount Devices are soldered
onto a substrate (commonly epoxy glass (FR4) and
are in thermal contact with it through the soldered joints and the copper interconnections. In this case, the heat generated by the active circuit is transferred to the leadframe and then to the substrate. A new dissipation path thus exists in parallel with the previous one whose efficiency depends on the thermal conductivity of the frame and on the length of the printed circuit's copper tracks. Figure A shows the experimental module.
AN262/0189
1/14 1243
APPLICATION NOTE
Figure A : Device Soldered to the Best Board, for Junction to. Ambient Thermal Resistance Measurement.
TEST DEVICE
p?
TEST BOARD
L.P'
5-10673
CONNECTION PINS
In high power applications R- .. Rhs and RthU-a) = Rth(j-c) + Rhs
JUNCTION TO PIN THERMAL RESISTANCE Rth(j.p)
In medium power packages RthU-p) is the thermal resistance of the heat transfer leads, from the junction to the external heatsink. In most cases the external heatsink is integrated on the board. Figure C shows the experimental setup.
Figure C : Junction to Pin Thermal Resistance
Measurement.
JUNCTION TO CASE THERMAL RESISTANCE Rth(j-c)
Rth(j'c) is the thermal resistance from the junction to a given area of the peackage's external surface where a heatsink is applied. In signal packages, a suitable area is its upper surfac~. Measurements are made with the samples in good thermal contact with an infinite heatsink (fig. B).
Figure B : Junction to Case Thermal Resistance Measurement.
PRESSURE CllPP1NG
CONNECTION ===.,.
THIN WIRES
I HEAT TRASFER LEAD
;~~~~§§~5_=-~-:."sOLDERED JOINT·
-7 WATER-COOLED ' - -THERMAL
COPPER-BLOCK
GREAS~
THE RMOCaUPLE
5-9783
PRESSURE CLIPPING
WATER- COOLED COPPER - BLOCK
THERMAL GREASE
THI!RMOCOUPLE
5-9150
When a heatsink of thermal resistance Rhs is attached to the package, the following relationship is valid:
Rhs x RRth(j.a) = RthU-c) +
Where R- takes into account all the othfr dissipation
paths (i.e. junction/frame/substrate). R is the lowest with low thermal conductivity frames.
TRANSIENT THERMAL RESISTANCE FOR SINGLE PULSES
The electrical equivalent of heat dissipation for a module formed by an active device, its package, a PCB and the ambient, is a chain of RC cells, as shown in fig. D, each with a characteristic rise time ('1:) = RC.
Figure D : Equivalent Thermal Circuit Simplified Package.
R th si R th frame R th mold
Ti
C th si
C th frame C t h mold 5-10622
2/14
1244
APPLICATION NOTE
The thermal capacitance of each cell is a measure of its ability to accumulate heat and depends on the specific heat, volume and density of the constituent materials.
When power is switched on, the junction temperature after time it is governed by the heat impedance of the cells, each of which follows its own time constant - this is analogous to the exponential charge of RC cells in an electrical circuit.
For a pulse lenght to, the effective Tj can be significantly lower than the steady state Tj (fig. E) and the transient thermal resistance Rth(to) can be defined from the ratio between the junction temperature at the end of the pulse and the dissipated power.
Figure E : Temperature Rise for Single Power Pulse.
Figure F : Temperature Rise for Repeated Power Pulses.
lamb
I I
I I
I
I
, , -~-l---~~-
S-97BL
Obviously, this parameter is smaller for shorter pulses and higher power can be dissipated without exceeding the maximum junction temperature defined from a reliability point of view. The knowledge of transient thermal data is an important tool for cost effective thermal design of switching applications.
PEAK TRANSIENT THERMAL RESISTANCE FOR REPEATED PULSES When pulses of the same height Pd are repeated with a duty cycle, DC, and a pulse width to, which is shorter than the overall system time constant, the train of pulses is seen as a continuous source of mean power Pdavg, where: Pdavg = Pd x DC However the silicon die has a time constant in the order of 1 to 2ms and is able to follow frequencies in the kHz range. Thus junction temperature oscillates about an average value given by : Tjavg = Rth x Pdavg as is graphically shown in fig. F.
The thermal resistance corresponding to the peak of the steady state oscillations (peak thermal resistance indicates the maximum temperature reached by the junction and, depending on duty cycle and pulse width, may be much lower than the DC thermal resistance.
EXPERIMENTAL METHOD Measurements were performed by means of the especially developed thermal test pattern P432, which is designed according to the Semiconductor Equipment and Materials Institute (SEMI) G32 guideline. Test chip P432 is based on a dissipating element formed by two npn transistors, each with 1OW power capability, and one sensing diode (fig. G). The diode is placed on the temperature plateau generated when the two transistors are biased in parallel, and gives the actual junction temperature Tj of the dissipating element, through the calibration CUNe (fig. H) of its forward voltage Vf versus temperature at a constant current of 100flA.
Figure G : ~hermal Test Pattern P432.
3/14 1245
APPLICATION NOTE
Figure H : Calibration Curve of P432 Temperature Sensing Diode.
V,
(mV)
"
680
I"
I"
MB'JTIZ 01
600
Figure J : Test Board Lay-out for SO Packages (150 mils body width) Board size is : 23 x 42mm2.
500
.' ld =100 JJA
1
1
400
1
20 40 60 00 iOO 120 T (OC)
Transistor size is intentionally limited to 1000sq. mils, in order to simulate high power density, characterizing a worst case. Die size, which is found to have little influence on thermal resistance when a copper frame is used, is slightly smaller than the die pad size and never exceeds 30k sq mils even in the largest packages such as high pin count PLCCs.
The measurement setup is shown in fig. I. it is compatiblewith DC and AC supplies and has an accuracy of better than 5%.
Figure'l : Experimental Setup.
Figure K : Test Board Lay-out for SO Packages
(3000 mils body width) Board size is 38 x 43mm2.
Figure K : Test Board for PLCCs Board size is 58 x 58mm2.
The advantages offered by the test pattern are: · high power capability · repeatable VI and temperature coefficient
(1.9mv(C) of the sensing element high resolution in pulsed 'conditions (1 OOIlS) · better correlation from one package to another. Both Alloy 42 and copper frames were considered for narrow SO packages (150mils body). For wide SO (300mils body) and PLCC packages only copper frames were examined. Suitable test boards were deyeloped (figs J, K and L).
4/14
1246
APPLICATION NOTE
MEDIUM POWER PACKAGES
While surface mountsignallCs are readily available, almost all power ICs are still assembled in traditional insertion packages.
Medium power 8M packages (Pd < 2W) can readily be derived from existing small outline and chip carrier packages by modifying the leadframe - in much the same way that Powerdip packages were derived from standard Dips.
This approach is particularly attractive because the external dimensions of the package are identical to existing low power packages, allowing the use of standard automatic assembly and test equipment. Frame modification is aimed at obtaining a low junction to pin thermal resistance path for the transfer of heat to a suitable external heats ink. A number of leads are connected to the die pad for this purpose. Two possibilities are considered here: a medium power PLCC44 with 11 heat transfer leads (fig. M) and a medium power 8020 with 8 heat transfer leads (fig. N).
A cost effective heat spreader can be obtained on the board by means of suitably dimensioned copper areas. The heat transfer leads are soldered to there areas (fig. Ml , Nl).
Figure M : Lead Frame for Medium Power PLCC44.
Figure N : Lead Frame for Medium Power 8020.
Figure M1 : Test.80ard for Medium Power PLCC44.
Figure N1 : Test Board for Medium Power 8020.
5/14
1247
APPLICATION NOTE
THERMAL DATA OF SIGNAL PACKAGES
SUMMARY OF JUNCTION TO AMBIENT THERMAL RESISTANCE IN STEADY STATE POWER DISSIPATION (SGS'THOMSON test board)
Die Size (millinches)
808 Alloy 42 Copper
90 x 100 94 x 125
8014 Alloy 42 Copper Copper
98 x 100 78 x 118 98 x 125
S016 Alloy 42 Copper
98 x 118 94 x 185
S016W Copper
120 x 160
S020 Copper
140 x 220
PLCC-20 Cu
180 x 180
PLCC-44 Cu
260 x 260
PLCC-68 Cu
425 x 425
PLCC-84 Cu
450 x 450
Rth (i·a) values correspond to low and high board density
Power PO [W] 0.2 0.2 0.3 0.5 0.7 0.3 0.5 0.7 0.7 0.7 1.5 1.5 2.0
Rth(j-a) [OC/W] on Board 250-310 130-180 200-240 120-160 105-145 180-215 95-135 90-112
77-97 90-110
50-60 40-46 36-41
SUMMARY OF JUNCTION TO CASE THERMAL RESISTANCE
PLCC20 PLCC44 PLCC68 PLCC84
Die Pad Size (millinches) 140 x 140 260 x 260 425 x 425 450 x 450
Rth(j-a) [DC/W] 25 13 10 9
JUNCTION TO AMBIENT THERMAL RESISTANCE IN STEADY STATE POWER DISSIPATION
Figure 1 : S08.
Rth j-a
!
. \ ("e/wl
i
260
........... " -
I-'IS9T1Z 02 DIE PAD=94x125sq milS.
IN AIR
220 I---- I-- ,
I
I
-f------ 1--
,
180 ......
~
I----I-
-140 _....... r-: ,
I
100
I
0,2
Of,
06
MOUNTED ON: SM, PCB1A BOARD
BOAR~- 5M PCBI
ALUMINt 08
I Plot (W)
Figure 2: S014.
Rlhj-a
t"e/wl
MIl9 TIZ OJ
I
DIE SIZE::; 60 x90 sq. mils
ioa i'... ........ r--..
.60
-........ .....
'-120
80
04
I I
FLOATING IN Al
I
~OUNTEO ON:
SM PCB 14 BOARD
SMPCB 180ARD
AlUMINA
1.2
1.6 Ptot(W)
6/14
1248
Figure 3 : S016.
,210
......... i"--.
180
-140 ....
--100 ....
60
Figure 5 : PLCC20.
1-18911Z 04
I
OlE SIZE =60.90 sq. mils
I tI r-- FLOArNG AIR
OU~TEO ~N'
SMFU31ABOARD
SMPCB1BO:{
ALlt'Nl
OB
1.2
1.6 Ptot (W)
M89 TIZ. 05
DIE SIZE :=80xllOsq. mils DIE PAD =140.oclt.Osq.mils
\ 160
r- [\" r----: __ rr= - .........
-_~O'TlNG IN AIR
--- 120
100
h P 60
~ ;;;;:.
60
0.4
as
I I
MOUNTED ON" SM PCB SA BOARD
-_. __L l . ._-
5MPCB580ARD
l J
1.2
Figure 7 : PLCC68.
Rthj_a tOCIW)
60
'I
\
55
~..
50 !\.
........
45
M!!9TIZ 05
DIE SIZE = 35.000 sq. mils DIE PAD =425)(4255 mils
-~G[NAIR
40 i'-
35 0.5
MOuNTED ON SM PCg6ARD
I
1.5
I
2.5 PtcdW)
APPLICATION NOTE
Figure 4 : S020.
Rthj _a I'C)
140 120 100 80
M89't,Z 07
JI I I
\
DIE PAO=Il,Q x220sq. mils DIE SlZE:= 5000 sq. mils
[\"
I I I I
.......... r -
FLOATiNG IN AIR
I I I I
"......... ""-
II I I
MOUNTED ON SM PC82A BOARD
"I
......." -
MOuNTED ON SMPCBZ BOARD
I
0.4
DB
1.2
Figure 6 : PLCC44.
M 89TIZ. 0 B
I
so
70 60
\
OlE SIZE:= 35.000 sq. mils DIE PAD = 260. 260 sq.mils
"- I _\ ~
I
~/,£;INAIR
-"""""-r- MOUNTED ~:
'" M PCB SA 8OARO
50
I
"'- "'"-i-- J;MPCB '5 BOARD
1
,
40 0.5
Figure 8 : PLCC84.
!
i
i
1.5
2.5 PtotlW)
Rthj_a ("C/W)
MB9TIZ 09
DIE AREA =35.000 sq. mils DIE PAD !: 450ll.t.50sq mils
50 45
"" "'-..
"'"- - - FLOATING IN AIR :----
40
._--
"-
-~NTED ON 5M PCB 5 BOARD
35
U5
1.5
2. 5 Pt o t ( W )
7/14
1249
APPLICATION NOTE
JUNCTION TO AMBIENT THERMAL RESISTANCE VS BOARD LAY-OUT (area of copper tracks on the board)
Figure 9 : 8016.
Rthj_a ("C/W)
130
,20
110
100
MB9 TIz'lO
1\ \
\
DIE SIZE:;: 60 Jt90sq. mils BOARD AREA =0.72 sq. mils
Pd ::: lW
\
\
- r\ "- ~
90
40
80
120
150 AI (xl(X)O
sq.mlls)
Figure 11 : PLCC44.
Rthj-a
('e,We) 62 60 56 56 54 52 50
1 I I! I
\'
\1 I
-'1
\ i
1\'
I \
!
I I
M89 TIZ 11
1 1
DIE SIZE =35.000 Sq mils
DIE PAD::: 260 x 260 sq. mils ~-
Ptol ::: lW
I
1
I
!
I
I
!
I
.I I
I
I
!,
'+L
1 j
:
-H-+ 1 1 i
100 ZOO JOO 400 500 600 .0.\ (xIODO sq mils)
Figure 10: 8020.
Rthj-a ('CIW)
M89 TIZ 12
Ptol :lW DIE SIZE =SOOOsq mils BOARD SIZE:;: 2.8 sq. Inch
110
f\
100
1\ ~ .........
90
'"1""-
80
-
r - S016WIDE
f-
SO 20
10 50
150
250
350 At (x 1000
sq. mils)
Figure 12 : PLCC20.
Rthj-a ("CIW)
100 95 90 65 80 15
10
MB9TIZlJ'
1 !
I
I
I 1 IP'o' ~lW
:i/: 1 i :~:~ ~~z~ ;l~g:,'ig~· -~-
I ,,I
\
,
T
\
: ,
I
1
I 1
I
'{
I i
I
I\.
I
i
~ I-
I I
.r-.... 1
I'l
I
,
I
!
;
50 100 150 200 250
At (x 1000 sq mils)
8/14
1250
APPLICATION NOTE
TRANSIENT THERMAL RESISTANCE FOR SINGLE PULSES
Figure 13: SOB.
R'h ("CIW )
100
SINGLE PULSE MOUNTED ON SMA:81 BOARO
Ptol =lW
M89Hl,II,
/ 'I - -
Figure 14: S014, 16.
R'h {OCIW )
100
SINGLE PULSE PIOI ::: 1.SW
60
40
V
V
10
60
40
/7
20
SO 14 5016
V
10
M~ 89
/
V
IE SIZE ::60x90 sq. mils
- IE 00 ::94 x12Ssq. mils
pN DIE Ad :: 2000sq. mils
10
Figure 15: S020.
R,h ("GW)
SINGLE PULSE MOUNTED ON SM peal BOARD
Ptol -lW
40 20
10 _.
/
/
/
MB'lTIZ I;'
/ /
/
I
ON DIE Ad :: 2000 sq. mils DIE PAO=l.l,O 11.220 sq. mils DIE srZE:: 5000 SQ_ mils
10
Figure 17 : PLCC6B.
M89TI-16
Rth
('C/W)
c---
~1~~~~ED~S~MPCB5
Pto t=2W
~ BOARD
~
~
20
V
10
/
V
/
/
DIE SIZE:: 35.000sq mils DIE PAD:: 300 x 300 sq. mils ON DIE Ad :1.000sq.rnils
10
~
MOUNTED ON 5MPCBl BOARD
OrE SIZE:: 60)( 90 sq. mils ON DIE Ad :::lOOD sq. mils
-
10
Figure 16 : PLCC44.
R'h
/ ("(IW) !------ ~\~;~L;~MPCB5 BOARD PIOI :: 2.W
20
V
10
M8911l18
L ~
/
II
L
V
DIE SIZE:: J5.000sq. mils ~I_E PAD:: 260 x 260sq mils
N DIE Ad::; 2. 000 sq. mils !------
Hr'
'0
107 T{ 5)
Figure 18: PLCCB4.
R,h ("(IW )
20
10
SINGLE PULSE MClLNTEP ON SM PCBS BOARD P tot =2W
/
M89TIl19
-;z ~ I-----
-/
/ V
V
DIE SIZE '= 35.000 sq. mil s
= DIE PAD 350 1\ 350 sq. mils
ON DIE Ad =2.000 sq. mils
10
9/14 1251
APPLICATION NOTE
PEAK TRANSIENT THERMAL RESISTANCE FOR REPEATED PULSES
Figure 19: 8014.
Rih ("C!wl
M89TIZ22 M'UNTED ON SM FeB 1BOAHC
Ptot =ZW
10
DC =0.5
50
4
OJ 30
0.1 20
- -- ---~ ..........: / ~ /
~v
~ DUTY CYCLE =PUl ~U~~~~~~~~ PERIOD
10
10
Wi T (ms)
Figure 21 : PLCC44.
M89iIZ.]) R'h
'"CIW) i-----t-===-;;t==""',6"'---j
30 OC"O.5
0.4 20
0.3
0.1 10
10
10 2 T (ms)
Figure 20 : 8020.
OC=O.5
-M89TI110 -..
---- ---
0.1 10
10
.I
L----
---; ~
..- ./
tot=ZW
O~ ~
I-""""' MOUNTED ON SM pca2 BOARD
DC=DUTYCVClE PlJLS:~~~E~ID;:RIOD
f----
10
Figure 22 : PLCC68.
102 T (ms) M89T1Z 21
OC=0.5
0.2 10
-~
0.1
/'
./'
(l()5
~
Plot:: ZW MOUNTED ON SM PCBS BOARD
DIE PAD:: 300 ;J( 300 sq. mils
DC =CUTY CYCLE
PULSE WIDTH
PULSE REPEl PERIOD
10
10 2 T(ms)
Figure 23 : PLCC84.
Rth :OCIW)
" lIZ.2t.
DC =0.5 20
10 - 0 . 2
--~
---01
V-
0.05
~ Ptol "SW MOUNTED ON 5i'Y1R:85 BOARD
DIE PAD=J5D J:350sq, rnils
PULSE WIDTH OC= DUTV CYCLE
PU..5E j:£PETIT. PERIOD
10
10 2 T (ms)
10/14
1252
APPLICATION NOTE
THERMAL DATA OF MEDIUM POWER PACKAGES
80(12+4+4) PLCC (33 + 11) " with 6 sq. em. on board heat-sink.
Rth(J-p) [OC/Wj (AVERAGE) 14 12
Rth(l-a)" [OC/Wj 50 41
JUNCTION TO PINS THERMAL RESISTANCE VS ON DIE DISSIPATING AREA
Figure 24: SO (12 + 4 + 4).
RthJ_p ('Clwl
I
15
M8911Z 25
Figure 25 : PLCC (33 + 11).
Rlhj_c ('CIW)
t.o189TI128
11,'.5
"" "-
" - "
r-
OlE SIZE ~ 20.000 sq mils
DIE PAO::140x220sq mIls
13
12
\6 Ad "'.1000
Sq.ffit(S)
12
11 Ad :: 35.0.0.0. sq. mils 1
J
10 10. 12 Ad(xlOOO sq mils)
JUNCTION TO AMBIENT THERMAL RESISTANCE VS AREA ON BOARD HEAT-SINK
Figure 26: SO (12 + 4 + 4).
Rthj_a ("CfW)
1\
15
\
10
\
MB9TIZ2fi
DIE SIZE - 120. x 130. sq. mils DIE PAD::: 140. x 220. sq. mils Ptot :IW
65
\
'\,
.......
I"--..
50
45
11/14
1253
APPLICATION NOTE
Figure 27 : PLCC (33 + 11).
M89 Til n
Plot = 1.5 W
Tcopper = 35 ~ 50
"-
.6
"-
~
............
42
i'-..
~
38
TRANSIENT THERMAL RESISTANCE FOR SINGLE PULSES
Figure 28: SO (12 + 4 + 4).
Figure 29 : PLCC (33 + 11).
Rth :"CIW)
50
SINGLE PULSE
MOUNTED ON BOARD wn H:
NO HEAT
20 10
M891IZ 37
10
Figure 30 : PLCC (33 + 11).
M aC~T I2_30
Rth
("C/W ) 20
I ,.,..
....- "./
. NOHEAT/
16 14
IV ~~Ol" ~
HEAT SINK = 2 sq em
12
/
SINGLE PULSE MOUNTED ON SMPC86 SOARD
10
I
o
T (s)
pulse length = 1 - lOs.
12/14 1254
pulse length = 0.1 - 10ms.
APPLICATION NOTE
PEAK TRANSIENT THERMAL RESISTANCE FOR REPEATED PULSES.
Figure 31 : PLCC (12 + 4 + 4).
Rth (OC/W)
M8!) TIZ. 31
MOUNTED ON BOARD WITH 9sq. em COPPER AREA HEAT SiNK DIE PAD;: IloO x 220 sq. mils
'0 j--'o:;.::c'-'-o"'OS'-t-_ _-,.._ _-"!'===-d
Figure 32 : PLCC (33 + 11).
DC= 0.5
20 F=O::-'::j--==:::j:::-::::=t~~
0.'
0.2
to
0.1
to
10 2
T (ms)
APPLICATION EXAMPLES O.F THERMAL DATA
Good thermal design begins with system and reliability considerations. This turn is based on correct consideration of ambient and device temperature parameters.
The ambient temperature Ta defined for applications can range from 50 to 55°C, as is common in many consumer and computer applications, through to 80°C or more in applications such as automotive systems. The ambient temperature depends on the various heat and cooling sources surrounding the device. An important factor in device lifetime is junction temperature -lifetime is approximately halved when junction temperature Tj is increased by 10°C. The maximum junction temperature commensurate with
EXAMPLE 1 : Maximum dissipation for S016 packaged device soldered onto an FR4 board (1 oz copper) under the following conditions:
· Ambient temperature: Ta = 70°C
· Maximum Junction Temperature: Tjmax = 130°C
The average length of the 12mils wide copper line connected to each pin is 80mils, soldering pads are 30 x 40mils. The total are is thus:
A = [(80 x 12) + 1200 x 16] = 34560sq.mils
OC ;: DUTY C'l'CLE :_-,-P~UL=SE=-w",IO::cT,,-H_ _ PULSE REF£TnION PERIOD
10-'
to
10 2 T (ms)
good reliability, takes into account the activation energy of the failure mechanisms which may differ for various silicon and packaging technologies.
In plastic packages the maximum Tjmax is 150°C, but lower values (100 to 120°C) may be specified in high rei applications such as telecoms.
When Tjmax and Ta are known, their difference Ll.Tj indicates the permissible junction temeperature rise for a given device. For a given power dissipation Pd, the thermal design must ensure that the product Pd x Rth(j-a) is lower than Ll.Tj ; where RthO·a) is the thermal resistance of the device from the junction to the ambient at temperature Ta. This takes into consideration the many elements connected to the heat source and includes the leadframe, moulding compound, substrate and heatsink, if used.
SOLUTION
From fig. 13, the value for Rth(j.a) is 125°C/W for a copper frame package. Comparing figs. 5 and 6, a value of about 240°C/W can be assumed for Alloy 42 packages. The allowed rise in junction temperature is : Ll.Tjmax = 130 - 70 = 60°C
Maximum dissipation is given by Ll.Tjmax/RthO-a).
Therefore:
60/125 = 0.48W for Copper frame 60/240 = 0.25 for Alloy 42 frame
13/14 1255
APPLICATION NOTE
EXAMPLE 2 : Junction temperature for an S020 packaged device soldered on FR4, under the following conditions: · Ambient temperature Ta = 70°C · Dissipated Power Pd = 0.6W
EXAMPLE 3 : To determine the size of an integrated heatsink for a medium power application using a PLCC (33 + 11) under the following conditions:
Ambient temperature Ta = 50°C Max. Junction Temperature Tjmax = 150°C · Dissipated Power Pd = 2.2W
SOLUTION A total trace-area of 200k sq.mils is assumed,this then gives, from fig. 14 : · Thermal Resistance Rth(j.a) = 90°C/W
IITj = Pd x Rth(j.a) · t,Tj=0.6x90=54°C · Junction Temperature Tj = 54 + 70 = 124°C
SOLUTION By calculation the application needs an Rth(j-a) of : (150 - 50)/2.2 = 45.5°C/W From figure 32 the on board heatspreader can thus be defined as needing an area of about 2 sq.cm.
EXAMPLE 4 : Given the application described in example 3 determine the maximum pulse width for a single 4W pulse superimposed on a continuous 1.5W dissipation
SOLUTION
The continuous steady state junction temperature at 1.5W dissipation is :
Tjss = (1.5 x 45.5) + 50 = 11B.25°C
The single pulse is allowed to cause a maximum increase of (150 - 11B.25°C) = 31. 75°C.
The related transient thermal resistance is (31.75/4) = 7.9°C/W
From figure 33, the corresponding pulse width can
pe interpreted as being in the order of 200ms.
EXAMPLE 5 : In a medium power application using an SO (12 + 4 + 4) calculate the average junction temperature and the peak te!"peratur~ for repeated pulses under the followmg condItions :
· Ambient temperature Ta = 70°C
· On board heatsink area A = 9 sq.cm.
Pulse length = 100ms
· Pulse height = 5W
· Duty cycle = 20%
SOLUTION
From figure 31, the thermal resistance is found to be 49°C/W. Thus the average junction temperature can be calculated:
Tjavg = (5 x 49 x 0.2) + 70 = 119°C
From figure 36, the peak thermal resistance is given as around 15°C/W. The peak temperature can thus be calculated as :
Tp = (5 x 15) + 70 = 145
14/14
1256
APPLICATION NOTE
THERMAL CHARACTERISTICS OF THE MULTIWATT PACKAGE
INTRODUCTION This Application Note provides a complete thermal characterization of the Multiwatt ® package (multilead double TO-220 - fig. 1). Characterization is performed according with recomandations included in the G32-86 SEMI guideline, by means of a dedicated test pattern. It refers to : 1. Junction to case thermal resistance Rth(j.c) 2. Junction to ambient thermal resistance Rth(j.a) 3. Junction to ambient thermal impedance for sin-
gle pulses and repated pulses, with different pulse width and duty cycle; 4. Thermal resistance in DC and pulsed conditions, with a typical external heat sink. Most of the experimental work is related to the thermal impedance, as required by the increasing use of switching techniques. Figure 1 : Multiwatt Assembly.
EXPERIMENTAL CONDITIONS The thermal evaluation was performed by means of the test pattern P432, which is a 20K mils2 die with a dissipating element formed by two transistors working in parallel and one sensing diode. In order to characterize the worst case of a high power density IC, the total size of the element is 2K mils2 with
By R. T1ZIANI
a power capability of 20W. Measurement method is described in Appendix A.
Samples with the indicated characteristics were prepared: Package Multiwatt 15 leads
Frame Material
Copper
Slug Thickness
1.5mm
Slug Thermal Conductivity
3.9W/cmoC
Die Attach
Soft (PbSn)
Measurement of junction to case thermal resistance Rth(j.c) is performed by holding the package against a water cooled heat sink, according with fig. 2. A thermocouple placed in contact with the slug measures the reference temperature of the case.
For junction to ambientthermal resistance Rth(j.a) the samples are suspended horizontally in a one cubic foot box, to prevent drafts.
Both DC and pulsed conditions are used; in the second case the contribution of package thermal capacitance is effective and transient thermal resistances much lower than the steady stata Rth(j.a) can be found, according to pulse length and duty cycle.
The effect of the external heat sink is quantified, using as test vehicle the commercially available heat sink THM7023 especially developed by Thermalloy for the Multiwatt package, whose thermal resistance in still air is about g"CIW.
The measurement circuit shown in fig. A3 was used for all the thermal evaluations.
JUNCTION TO CASE THERMAL RESIS· TANCE
The dependance of Rth(j-c) on the dissipated power is reported in fig. 3.
It is well known that the main contribution to Rth(j-c) of power packages in given by the silicon die.
AN257/0189
1/8
1257
APPLICATION NOTE
Figure 2 : Measurement of Rth U-c).
PRESSURE CLIPPING
Figure 4 : RthU-c) Thermal Resistance vs. Die Size and on Die dissipating Area.
RTHj_c ("CIW)
MB8MUll 02
CONNECTION THIN WIRES
THERMOCOUPLE
Figure 3 : Rth U-c) of Multiwatt Package vs. Power Level.
M88MUL1.01 RTHj--c
(·CIW) 1-:-+-+-t----i-t-+--+-+-1---1
P1,32
2.5 1-:-+-+-t----i-'--t-+--+-+-1---1
23 1~t:t=t=Ft=rt-H I--
2.2 die size ::20.000 sq.mils dissipating area:: 2.000 sq. mils
2.1
1.5
~ diE" size ,,51'1 sq. mIls
...,.,
1.5
.......
12K
.......
20K
I"-r-
15K
05
10
15
JUNCTION TO AMBIENT THERMAL RESISTANCE
In medium power applications (1.5-2W), the Multiwatt package can be used without external heat sink, thanks to the significant size (about 3.5cm2) of its integrated thermal mass_
Its RthU-a) has two contributions: the RthU-c), mainly due to the silicon die (as shown in fig. 4) and the thermal resistanc~ of the copper slug Rth slug.
Figure 5 : RthU-a) of Multiwatt Package vs. dissipated Power.
M6BMLJlT 03
I,
Pl.3Z
- I........ ........ .......
r - .........
FREE AIR
MOUNTED ON PCB SOARD
9 PtotlW)
FOR DEVICES OTHER THAN THE TEST PATTERN P432 THE CALIBRATION CURVE OF FIG. 4 IS NEEDED. It shows the relationship between RthU-c) and the dissipating area existing on the silicon die (power diodes, power transistors, high current resistors), for different die sizes.
20
l -I - - MOUNTED ON THM 7023 HEAl SINK
10
DIE SIZE:: 20.000 sq. mils
= OISSIPATIf\(3 AREA WOO sq. mils
1.0
2.0
3D
4.0 Ptot(W)
218 1258
APPLICATION NOTE
Fig. 5 gives the relationship between Rth(j.a) and the power dissipation level for the P432 test pattern is still air, on PC board and on a commercial heat sink.
IN ORDER TO HAVE AN ACCURATE VALUE FOR OTHER DEVICES, WITH DIFFERENT DIE SIZE AND DISSIPATING AREA, VALUES OF FIG. 5 SHOULD BE CORRECTED THROUGH THE CALIBRATION CURVE OF FIG. 4 CORRECTION TERM IS ALWAYS IN THE RANGE OF 0-2"C/W; THEREFORE, IT AFFECTS THE Rth(j.a) OF NO MORE THAN 5% IN STILL AIR OR WITH THE PACKAGE MOUNTED ON PC BOARD.
TRANSIENT THERMAL RESISTANCE IN PULSED CONDITION (without external heat sink)
The effect of single pulses of different length and height for the Multiwatt package without any external heat sink is shown in fig. 6.
This behaviour is discussed in Appendix B. Due to
a significant thermal capacitance (C = 2JI"C) and correspondingly long risetime (1: = 80s), single pul-
ses up to 30W can be delivered to the Multiwatt package for 1s with acceptable junction temperature increase.
IN ORDER TO HAVE ACCURATE Rth (to FOR OTHER DEVICES, WITH DIFFERENT DIE SIZE AND DISSIPATING AREA, VALUES OF FIG. 7 MUST BE CORRECTED AS DESCRIBED IN EXAMPLE 2 OF THE LAST SECTION.
Figure 6 : Transient Thermal Resistance for Single Pulse.
Repetition of pulses with defined Pd, period and duty cycle DC (ratio betwen pulse length and signal period), gives rise to oscillations in junction temperature as described in Appendix B.
The transient thermal resistance corresponding to the upper limit of the curve of fig. B4 (peak transient thermal resistance) is reported in fig. 7 and depends on pulse length and duty cycle. It can be noticed that DC becomes less effective for longer pulses.
TRANSIENT THERMAL RESISTANCE IN PULSED CONDITION (with external heat sink)
Characterization has been repeated with acommercial heat sink (Thermalloy THM7023) in order to have an example of the effect of an external thermal mass on the impedance of the thermal module.
Relationship between transient Rth and pulse length is reported in fig. 8.
The effect of the increased thermal capacitance is evident in fig. 9, where thermal data of fig. 6 and 8 are compared: it can be noticed that the curves are definitely different for pulses longer than 1s, corresponding about to the rise time of the slug. The effect of the thermal mass is to keep low the heating rate of the silicon die thus allowing a better power management of long power pulses. This conclusion has general validity and can be applied to other heat sinks than the one considered in this note.
Figure 7 : Peak Transient Rth vs. Pulse width and Duty Cycle.
M88MUL105
R'h l"CJW )
I
i P432]
I
I I
: .I
[ !
10
f-
DC:: 0.5
10 <
0.3
I
i I~I--l-
q i 10 ~I ~
I !
-I
iJ-r-I Pd~5W
-
!
FREE AIR
I I
PULSE WIDTH
i
DC:Dun C'iClE PUlSE REPEl. PERIOD
[ I
01 03 06 1
I I
3 6 10
II II
30
100 300T(rrS;
3/8 1259
APPLICATION NOTE
Figure 8 : Transient Rth for single pulses, with Heatsink.
M 88~ULT 06
I F<J21 ! I I ! I I DIE SIZE:: 20.000 sq.mils DISSIPATING AREA =2000 sq. mils MOUNTED ON THM1023 HEAT SINK
10
-I
I
~ ~-
f-
f-
-+' rt- ,
j
_-;-r ; I.........
,/
I
Pd:: 5W
f-
711:1
10
Figure 9 : Comparison of Transient Rth for single pulses, with and without Heat Sink.
I I
) P~J2
20
~ I
J tM88MUlT 07
DIE SIZE;: 10.000 sq. mils DISSIPATiNG ARE A:: 2000sq. mils frREE AIR
Po =2w
- + ID f-
/ -- f-e-
I
V y i J...,."",i::=='~NTED ON THM ~102J f~HEAT SINK
~I I i 1~~15WI J j
ID
APPENDIX A
The thermal resistance evaluation is performed with the especially designed test chip P432 which has two bipolar power transistor and one sensing diode (fig. A1). The active area is about 2000 mils2 on a 35000mils2 chip. Its lay-out was optimized in order to have a uniform temperature area, once the two transistor are powered; the sensing diode is placed at the center of this area.
Figure A1 : Test Pattern P432 Lay-out.
The relationship between the forward voltage VI of the diode at the constant current of 100rtA and the temperature is shown in fig. A2. The curve calibrates the junction temperature through the voltage drop of the diode.
The measurement circuit is shown in fig. A3. A storage oscilloscope or a fast digital voltmeter can be used for recording the VI value.
4/8 1260
Figure A2 : Calibration Curse (sensing diode).
Vf (mV)
I"
680
I"
"
M89TlZ 01
600
500
Id::: IOO fJA
I
400
I
20 40 60 00 100 120 T I"e)
Figure A3 : Measurement Circuits.
APPLICATION NOTE
APPENDIX B - THERMAL MANAGEMENT IN PULSED CONDITION
THERMAL RESISTANCE AND CAPACITANCE
The electrical equivalent of heat dissipation, for a thermal module formed by the active device with its package and the external heat sink is shown in fig. 81.
To each cell of the thermal chain are associated a value of thermal resistance Rth ("C/W) and a value of thermal capacitance Cth (J/'C). The former informs about temperature increase due to the element represented by the cell; as, in the example under consideration, heat transfer is mainly based on conduction for the silicon, the copper integrated heat sink and to metallic body of the external heat sink Rth can be calculated from the relationship:
y Rth= KxS
where K is the thermal conductivity of the material, the length of the conductive path and S its section.
Thermal capacitance Cth is the capability of heat accumulation; it depends on the specific heat of the material and on the volume effectively interested by heat exchange (this means that the parts which are not heated during heat dissipation DO NOT contribute to thermal capacitance). Thermal capacitance is given by:
Cth = d x Ct x V
where d is the density of the material, Ct its specific heat and V the volume interested to heat accumulation.
The last element of the network, assumed as purely resistive, is due to convection and radiation from the external heat sink towards the ambient.
5/8 1261
APPLICATION NOTE
Figure 81 : Electrical Equivalent of Multiwatt Package Mounted on the External Heatsink.
SILICON
Rt h';;' 2°C/W
T J
SLUG '" 0.5 ·C/W
Cth';;' 10- 3 J/oCW
L=~2ms
'" 2J I·C "-'Is
HEATSINK AIR
'" I·C/W
gOC/W
....., 100J/·C "-'1005
5-9781
Each cell has its own risetime '"C , given by the product of the thermal resistance and capacitance:
'"C = Rth x Cth
The value of the time constant determines whether a cell approaches equilibrium rapidly of slowly: if Rth or Clh increases, equilibrium is reached at a slower rate. The following relationship is valid for each cell:
I'lT = Rlh x Pd [1 - e·t/r 1(1)
Typical values of Rth, Cth and '"C for Multiwatt application are shown in fig. 81.
When power is switched on, temperature increase is ruled by subsequent charging of thermal capacitances while the value reached in the steady state depends on thermal resistances only. Qualitative behaviour of the network of fig. 81 is shown in fig. 82.
Figure 82 : Qualitative Tj increase (network of fig. 81) for repeated Power Pulse.
SO 100 150 200 250 300. J 50 400 450 500 TH£ ( SEC)
6/8 1262
APPLICATION NOTE
SINGLE POWER PULSE
When the pulse length has an assigned value, effective Ti can be significantly lower than the steady state Tj (fig. B3.).
Figure 83 : Effect of a Single Power Pulse.
tance Rth peak) is now given by fig. 5, and can be obtained if pulse length and duty cycle are known ; Pdmax is derived from the same figure.
Figure 84 : Junction Temperature increase for repeated Pulses.
S-9781.
Tamb
For any pulse length to, a transient thermal resistance Rth (10) is defined, from the ratio between the junction temperature at the end of the pulse and the dissipated power. Obviously, for shorted pulses, Rth (to) is lower and a higher power can be dissipated, without exceeding the maximum junction temperature Tj-max allowed to the IC from reliability considerations. Fig. 7 and 9 of this Application Note give experimental values of Rth (10) for the two cases of the Multiwatt package without and with external heat sink.
REPEATED PULSES
When pulses of the same height Pd are repeated with a defined duty cycle DC and pulse length is short in comparison with the total risetime of the system (many tens of seconds) the train of pulses is seen by the system as a continuous source, at a mean power level of
Pdavg = Pd X DC
The average temperature increase is :
~Tavg = Rth x Pdavg = Rth X Pd X DC
On the other hand, the silicon die (1: s = 1- 3ms) is able to follow frequencies of some KHz and junction temperature oscillates about the average as qualitatively shown in fig. B4.
The thermal resistance corresponding to the peak of the oscillation at equilibrium (peak thermal resis-
APPLICATION EXAMPLES
EXAMPLE 1 - MAXIMUM Pd FOR SINGLE PULSE OF ASSIGNED LENGTH
PROBLEM : define the maximum Pd for a single pulse with a length of 20ms in the case of Multiwatt package used without heat sink. Ambient temperature is 50'C ; maximum temperature is 130'C. Die size is 20K mils2, with dissipating area of 2K mils2 (as in P432 test pattern).
SOLUTION : allowed temperature increase ~T is 80'C. Having a RthO-a) of 39'C/W, Multiwatt package can dissipate about 2W in steady state. From fig. 7 the transient thermal resistance corresponding to one single pulse of 20ms is Rth (20ms)P432 = 2.2'C/W. A peak of 8012.2 = 36.3W can be applied to the ci rcuit.
EXAMPLE 2 - CORRECTION FOR DIE SIZE AND DISSIPATING AREA
PROBLEM : correct the results obtained in example 1, for assigned die size and dissipating area. Practical case : IC having a die size of 35K mils2 with a dissipating area of 20k mils2.
SOLUTION : from fig. 5, thermal resistances of P432 and of the IC under consideration are Rth P432 = 2.3'C/W and Rth(j-C)IC = 1.2'C/W.
7/8 1263
APPLICATION NOTE
As the length of the pulse is 10-15 times longer than the rise time of the silicon, the die (first cell offig. B1) can be assumed to have reached its equilibrium condition.
Rth (20ms) found in previous example has to be corrected in order to take into account the new value of Rthu·c) :
Rth (20ms)lc = Rth (20ms)P432 .
- Rth(j-c)P432 + Rth(j.c)IC =
= 2.2 - 2.3 + 1.2'C/W = 1.1'C/W
= A single pulse of 80/1.1 72W can be delivered to
such device.
When the pulse has the same order of silicon rise time "t P432 is about 1ms) another type of correction is needed. In first approximation, 't increase with dissipating area with the relationship:
tiC = V20KIC/2Kp432 x ,P432 '" 3.1 ms
Expansion of the exponential term of relationship (1)
= limited to the first term term, is : Rth IC (to) Rth P432 (to) /3.1
= for to = 1ms : Rth IC (1 ms) = 1.05/3.1'C/W 0.34'C/W
= A single pulse of 80/0.34 235W can be delivered
to such device.
EXAMPLE 3 - Rth WITH REPEATED PULSES
PROBLEM: find the peak power which can be dissipated by Multiwatt package without heatsink, when power is continuously switched on 10ms and switched off 90ms. Ambient temperature is 50'C, maximum temperature is allowed to be 125·C.
SOLUTION: a maximum t.T = 75'C has to be considered. Fig. 5 indicated that for a pulse width of 1Oms
and a duty cycle of 0.1, Rth peak is 6TCIW. Maximum
= Pd is 75/6.7 = 11.2W, with an average temperature
increase t.Tpeak of 39 x 0.1 x 11.2 43'C.
8/8
It..,~ I SIi\GIIn«S:Ui·l1@~HIl.OIWirMUil@Sll!Oln©Ni!I
1264
APPLICATION NOTE
THERMAL CHARACTERISTICS OF THE PENTAWATT-HEPTAWATT PACKAGES
INTRODUCTION This Application Note is aimed to give a complete thermal characterization of the Heptawatt and Pentawatt package (fig. 1, 2). Characterization is performed according with recomendations included in the G32-86 SEMI guideline, by means of a dedicated test pattern. It refers to : 1. Junction to case thermal resistance Rth(j-c) 2. Junction to ambient thermal resistance Rth(j-a) 3. Junction to ambient thermal impedance for
single pulses and repeated pulses, with different pulse width and duty cycle; 4. thermal resistance in DC and pulsed conditions, with a typical external heat sink. Most of the experimental work is related to the thermal impedance, as required by the increasing use of switching techniques. Figure 1 : Pentawatt.
Figure 2 : Heptawatt.
By R. TIZIANI
EXPERIMENTAL CONDITIONS
The thermal evaluation was performed by means of the test pattern 'P432, which is a 15k mils2 die with a dissipating element formed by two transistors working in parallel and one sensing diode. In order to characterize the worst case of a high power density IC, the total size of the element is 2k mils2 with a power capability of 20W. Measurement method is described in Appendix A.
Samples with the indicated characteristics were prepared:
Package
Pentawatt - Heptawatt
Frame Material
Copper
Slug Thickness Slug Thermal Conductivity
1.25mm Typ. 3.9W/cmoC
Die Attach
Soft (PbSn)
Measurement of junction to case thermal resistance RthU-c) is performed by holding the package against a water cooled heat sink, according with fig. 3. A thermocouple placed in contact with the slug measures the reference temperature of the case.
For junction to ambient thermal resistance Rthu-a) the samples are suspended horizontally in a one cubic foot box, to prevent drafts.
Both DC and pulsed conditions are used; in the second case the contribution of package thermal capacitance is effective and transient thermal resistances much lower than the steady state Rthu-a) can be found, according with pulse length and duty cycle.
The effect of the external heat sink is quantified, using as test vehicle the commercially available heat sink THM7023 (Thermalloy) whose thermal resistance in still air is about g'C/W.
The measurement circuit shown in fig. A3 was used for all of the thermal evaluations.
JUNCTION TO CASE THERMAL RESISTANCE
The dependance of RthU-C) on the dissipated power is reported in fig. 4. The absolute value and the behaviour with the dissipated power are the same for
AN258/0189
1/8 1265
APPLICATION NOTE
both packages as the slug thickness and the die attach are equal. Figure 3 : Measurement of Rth U-c)-
PRESSURE CLIPPING
It shows the relationship between RthU-c) and the dissipating area existing on the silicon die (power diodes, power transistors, high current resistors), for different die sizes.
Figure 5 : Rth U-c) Thermal Resistance vs. Die Size and on Die dissipating Area.
Rth j_e ('CfW)
MBBPENTA 02
CONNECTION THIN WIRES
\ '.5
I~ ......... OIE SIZE:: 5K sq. mils
,5
- "'- ...... . . .r- F=::::: 12K
I-- ,OK
Figure 4 : Rth U-c) of Pentawatt and Heptawatt Package vs. Power Level.
M6BMULT 01 RTHj_c
('C1Wl l--+-+--+--+-+_I--+-+--+---1 P1,32 '.5 1-+-+-+-+-+-1-+-+-+---1
- '.l It-t=t::j::::~t=rt-t1
,.,
d,e size ",20.000sq.mils
'.1
dissipating area:: 2.000 sq. mils
'.0
9 Ptot(W)
It is well known that the main contribution to RthU-c) of power packages is given by the silicon die. FOR OTHER DEVICES THAN THE TEST PATTERN P432 THE CALIBRATION CURVE OF FIG. 51S NEEDED.
12 Ad (ll 1000 sq mils)
JUNCTION TO AMBIENT THERMAL RESISTANCE
In medium power application (1W), the Pentawatt and Heptawatt packages can be used without external heat sink thanks to the significant size (about 1.5cm2) of its integrated thermal mass.
An effective cost solution for higher power application (1.5-2.0W) is using a copper area heat sink.
An board with the external leads bent down as shown in fig_ 7.
Fig. 6 gives the relationship between RthU-a) and the power dissipation level for the P432 test pattern in still air, on PC board, on integrated heat sink on board and on a commercial heat sink.
IN ORDERTO HAVE AN ACCURATE VALUE FOR OTHER DEVICES, WITH DIFFERENT DIE SIZE AND DISSIPATING AREA, VALUES OF FIG. 6 SHOULD BE CORRECTED THROUGH THE CALIBRATION CURVE OF FIG. 5 CORRECTION TERM IS ALWAYS IN THE RANGE OF 0-2'C/W ; THEREFORE, IT AFFECTS THE RthU-a) OF NO MORE THAN 5% IN STILL AIR OR WITH THE PACKAGE MOUNTED IN PC BOARD.
2/8 1266
Figure 6: Rth O-a) vs. dissipated Power (heptawatt).
Rth J~a r:-,--,----,--,--,--~----'=="""
('CIWJ
100 1--'.+--+--1-+-+--,-
80
60
20
10
30
40 Plot (v.:)
Figure 7: Pentawatt Soldered on Copper Heatsink on P.C Board.
PC BOARD
APPLICATION NOTE
TRANSIENT THERMAL RESISTANCE IN PULSED CONDITION (without external heat sink)
The effect of single pulses of different length and height without any external heat sink is shown in fig. 8.
This behaviour is discussed in Appendix B. Due to
a significant thermal capacitance (C = 1JtC) and a correspondingly long risetime ('t = 80s), single pul-
ses up to 20W can be delivered for 1 s with accept-
able junction temperature increase.
3/8
1267
APPLICATION NOTE
Figure 8 : Transient Thermal Resistance for Single Pulses (heptawatt).
Rth
(·crw)
60
40
51 NGLE PULSE Pd := 2W MOUNTED ON BOARD DIE SlZE:::120 ~ 130 sq. mils
Adiss:: 2000 sq. mils
M!l8PENTA.04
20
10
10
IN ORDER TO HAVE ACCURATE Rth(to) FOR OTHER DEVICES, WITH DIFFERENT DIE SIZE AND DISSIPATING AREA, VALUES OF FIG. 7 MUST BE CORRECTED AS DESCRIBED IN EXAMPLE 2 OF THE LAST SECTION.
Repetition of pulses with defined Pd, period and duty cycle DC (ratio between pulse length and signal period), gives rise to oscillations in junction temperature as described in Appendix B.
The transient thermal resistance corresponding to the upper limit of the curve of fig. B4 (peak transient thermal resistance) is reported in fig. 9 and depends
Figure A1 : Test Pattern P432 Lay-out.
on pulse length and duty cycle. It can be noticed that DC becomes less effective for longer ~ulses.
Figure 9 : Peak Transient Rth vs Pulse width and Duty Cycle (heptawatt).
Rth MOUNTED ON BOARD '·C/W )
MBS PENTA. 05 Ptot :I.W
DC =Q5
20 10
0<
- I.--- l---
0.2
-- ---- 0.1
--- -- DC::: DUTY CYCLE:= PULSE ~~~TIT~~~T~ER1OD
10
APPENDIX A
The thermal resistance evaluation is performed with the especially designed test chip P432 which has two bipolar power transistor and one sending diode (fig. A1). The active area is about 2000 mils2 on a 15000 mils2 chip. Its lay-out was optimized in order to have a uniform temperature area, once the two transistor are powered; the sensing diode is placed at the center of this area.
4/8 1268
APPLICATION NOTE
The relationship between the forward voltage Vj of the diode at a constant current of 100ilA and the temperature is shown in fig. A2. The curve calibrates the junction temperature through the voltage drop of the diode.
The measurement circuit is shown in fig. A3. A storage oscilloscope or a fast digital voltmeter can be used for recording the Vj value.
Figure A2 : Calibration Curve (sensing diode).
V,
(m\l) 680
I"
"
MB9TIZ 01
600
Figure A3 : Measurement Circuit.
D.C. SUPPLY
D. C.
SUPPLY
PULSE
GENERATOR
500 Id ::100 fJA 1 1 1 1
400 20 40 60 00 100 120 T (OC)
D.C.
SUPPLY
FAST DVM
STORAGE SCOPE
APPENDIX B - THERMAL MANAGEMENT IN PULSED CONDITION
THERMAL RESISTANCE AND CAPACITANCE
The electrical equivalent of heat dissipation, for a thermal module formed by the active device with its package and the external heat sink is shown in fig. B1.
To each cell of the thermal chain are associated a value of thermal resistance Rth (C/W) and a value of thermal capacitance Cth (JrC). The former in-
forms about temperature increase due to the element represented by the cell ; as, in the example under consideration, heat transfer is mainly based on conduction for the silicon, the copper integrated heat sink and to metallic body of the external heat sink Rth can be calculated from the relationship:
1 Rth= - -
KxS
Where K is the thermal conductivity of the material, 1 the length of the conductive path and S its section.
5/8
1269
APPLICATION NOTE
Figure 81 : Electrical Equivalent of Pentawatt and Heptawatt Package mounted on the External Heatsink.
SILICON Rth?' 2·C/W
SLUG
..... 0.5 ·C/W
T j
Cth~ 10- 3 J/·CW
L= ....2ms
~ lJ/·C ""'0.5s
HEATSINK AIR
rv IOC/W
Tamb
...... 100J/·C ---100 s
5 - 9954
Thermal capacitance Cth is the capability of heat accumulation; it depends on the specific heat of the material and on the volume effectively interested by heat exchange (this means that the parts which are not heated during heat dissipation DO NOT contribute to thermal capacitance). Thermal capacitance is given by:
Cth = d x Ct x V
where d is the density of the material, Ct its specific heat and V the volume interested to heat accumulation.
The last element of the network, assumed as purely resistive, is due to convection and radiation from the external heat sink towards the ambient.
Each cell has its own risetime 1:, given by the product of thermal resistance and capacitance:
1: = Rth )( Cth
The value of the time constant determines whether a cell approaches equilibrium rapidly or slowly: if Rth or Cth increases, equilibrium is reached at a slower rate. The following relationship is valid for each cell :
tlT = Rth x Pd x [1 - e-II1:] (1)
Typical values of Rth, Cth and 1: for Heptawatt and Pentawatt application are shown in fig. B1.
When power is switched on, temperature increase is ruled by subsequent charging of ther~ mal capacitance while the value reached in the steady state depends on thermal resistance only. Qualitative beahaviour of the network of fig. B1 is shown in fig. B2. Figure 82 : Qualittative Tj increase (network of
fig. B1) for repeated power pulse (heptawatt).
50 100 150 200 250 300 350 ~oo 450 500 TIrE ( SEC )
6/8
1270
APPLICATION NOTE
SINGLE POWER PULSE
When the pulse length has an assigned value, effective Tj can be significantly lowerthan steady state Tj (fig. B3.).
Figure 83 : Effect of a Single Power Pulse.
tained if pulse length and duty cycle are known ; Pdmax is derived from the same figure.
Figure 84 : Junction Temperature increase for operated Pulses.
5-9194
For any pulse length to, a transient thermal resistance Rth (to) is defined, from the ratio between the junction temperature at the end of the pulse and the dissipated power. Obviously, for shorter pulses, Rth (to) is lower and a higher power can be dissipated, without exceeding the maximum junction temperature Tj max allowed to the IC from reliability considerations. Fig. 7 and 9 of this Application Note give experimental values of Rth (to) for the two cases of the Heptawatt package without and with external heat sink.
REPEATED PULSES
When pulses of the same height Pd are repeated with a defined duty cycle DC and pulse length is short in comparison with the total risetime of the system (many tens of seconds) the train of pulses is seen by the system as a continuous source, at a mean power level of
Pdavg = Pd x DC ,
The average temperature increase is :
L'>Tavg = Rth x Pd avg = Rth x Pd x DC
On the other hand, the silicon die (1: Sl = 1 + 2ms) is able to follow frequencies of some kHz and junction temperature oscillates about the average, as qualitatively shown in fig. B4.
The thermal resistance corresponding to the peak of the oscillation at equilibrium (peak thermal resistance Rth peak) is now given by fig. 5, and can be ob-
APPLICATION EXAMPLES
EXAMPLE 1 - MAXIMUM Pd FOR SINGLE PULSE OF ASSIGNED LENGTH
PROBLEM : define the maximum Pd for a single pulse with a length of 20ms in the case of Heptawatt package used without heat sink. Ambient temperature is 50"C ; maximum temperature is 130"C. Die size is 15k mils2, with dissipating area of 2k mils2 (as in P432 test pattern).
SOLUTION: allowed temperature increase L'>T is 80°C. Having a RthU·a) of 60"C/W, Heptawatt package can dissipate about 1.3W in steady state From fig. 8 the transient thermal resistance corresponding to one single pulse of 20ms in Rth (20ms)P432 = 2.2"C/W. A peak of 80/2.2 = 36.3W can be applied to the circuit.
EXAMPLE 2 - CORRECTION FOR DIE SIZE AND DISSIPATING AREA
PROBLEM: correct the results obtained in example 1, for assigned die size and dissipating area. Pratical case: IC having a die size of 15k mils2 with a dissipating area of 10k mils2.
SOLUTION: from fig. 5, thermal resistance of P432 and of the IC under consideration are Rth P432 = 2.3°C/W and RthU-c)IC = 1's"C/W.
As the length of the pulse is 10-15 times longer than the risetime of the silicon, the die (first cell of fig. B1)
7/8 1271
APPLICATION NOTE
can be assumed to have reached its equilibrium condition.
Rth (20ms) found in previous example hasto be corrected in order to take into account the new value of RthO'C)'
Rth (20ms)lc = Rth (20ms)P432-
- RthO·c)P432 + RthO'c)IC =
= 2.2 - 2.3 + 1SC/W = 1.4°C/W
A single pulse of 80/1.4 '" 57W can be delivered to such a device.
EXAMPLE 3 - CORRECTION FOR SINGLE PULSES OF 1-3ms
PROBLEM: Correct the results of example 2, for pulse length of 1ms.
SOLUTION: when the pulse has the same order of magnitude of silicon rise time (T P432 is about 1ms) another type of correction is needed. In first approximation it is considered that remains constant when the dissipating area gets higher and the Rth for the silicon die decreases as the reciprocal of the dissipating area. From relationship (1) :
~T = Rth (1 mS)P432 x 2K!1 OK x Pd x [1- e-tlT] for to =
1ms:
.
RthlC (1 ms) = 1.05/0SC/W '" 0.21°C/W
A single pulse of 8010.21 '" 380W can be delivered to such a device.
EXAMPLE 4 - Rth REPEATED PULSES
PROBLEM: find the peak power which can be dissipated by Heptawatt package without heatsink, when power is continuously switched on 10ms and switched off 90ms. Ambient temperature is 50°C. maximum temperature is allowed to be 125°C.
SOLUTION: a maximum ~T = 75°C has to be con-
sidered. Fig. 9 indicated that for a pulse width of 10ms and a duty cycle of 0.1, Rthpeak is 8SCIW. Maximum Pd is 75/8.5 = 8.8W, with an average temperature increase ~Tpeak of 60 x 0.1 x 8.8 '" 68°C.
REFERENCES
"Improved thermal evaluation, by means of a simple integrated structure" T. Hopkins, C. Cognetti, R. Tiziani - SEMI THERM (USA, 1986).
8/8 1272
APPLICATION NOTE
RESISTANCE TO SOLDERING HEAT AND THERMAL CHARACTERISTICS OF PLASTIC SMDs
INTRODUCTION
Surface Mount Technology (SMT) has introduced a number of new technical problems, which have delayed the conversion from insertion assembly.
This is not strange: what readily available source of expertise existed a few years ago?
Plastic SO packages were introduced in Europe in the early '7Os and widely used in hybrids, but hybrid assembly has little relationship with the placement, soldering, handling tools now considered for SM PCB production. Was it surprising that even the semiconductor suppliers with sound experience in SO production could not give all of the answers needed by the PCB manufacturer?
Japanese experience in SMT based consumer products is impressive : 87% of components used for cameras are in SM versions. However, the degree of complexity and performance of consumer products are somewhat different from the industrial, automotive and telecoms applications the Western world is interested in. On the other hand, in 1985 the percentage of SMDs (active and passive) used in industrial systems produced in Japan was 16.6% in telephones, 5.5% in automotive applications, 5.1% in cable communication, 0.7% in minicomputers1 ; that is, a level similar to US and European production, presumably with a similar level of expertise.
In the past few years confidence in SMT has increased. More experience exists, which is the result of an expensive learning phase covered by both SMD manufacturers and users.
The reliability of plastic SMDs has an important place in this work. It needs a new approach in comparison with equivalent insertion devices, due to the completely different use.
In 14 years of production, no distinction was made in the authors' company between SO and DIP, from the point of view of reliability. They had the same reliability targets and similar evaluation methodology; the former was often hot plate soldered on leaded ceramics for more convenient handling but no difference in long-term reliability existed.
With SMT, this is inadequate. Negative effects due to the various assembly processes, and to some
By C. Cognetti, E. Stroppolo and R. Tiziani
thermo mechanical influence of the board, can limit the device life.
The present work is focused on SMDs soldered onto a plastic substrate, by means of the most common industrial processes, and takes into account two aspects of reliability:
1. Resistance to soldering heat, i.e., the suitability to withstand the thermal shock associated with the soldering cycle, without reducing reliability. This information is obtained by performing moisture resistance tests. Data about SO packages will be presented. For PLCCs, evaluation is in progress and will be concluded in the first half of 1988.
2. Heat dissipation, which influences the failure rate. This information is obtained with test patterns and test boards designed by SGS-THOMSON Microelectronics and includes thermal impedance in pulsed conditions. A few case studies will be included in this paper but comglete characterisations are available elsewhere. 2
RESISTANCE TO SOLDERING HEAT
In through-hole technology, devices are inserted from the upper side of the board and wave soldered from its lower side.
Only the lead extremities reach the temperature (250-260°C) of the molten solder; the maximum specified soldering time of 10s is short enough to avoid over-heating of the package body, which generally does not exceed 120-130°C during the whole process.
This temperature is lower than the moulding compound glass transition temperature (160-170°C) and the risk of permanent damage to the package structure or to the silicon die is excluded.
Device reliability is defined almost independently of the soldering time and temperature; devices under reliability test are mounted on sockets, thus neglecting the effect of the assembly process.
On the contrary, in all industrial SMT processes, devices are soldered in a high temperature ambient (215-260"C), with high heating rate, and the plastic package is kept in glass transition conditions
AN26410289
1110 1273
APPLICATION NOTE
(figure 1) for a relatively long time (up to 60s). This situation was never encountered before.
Concern over reduced reliability is justified and explains the trend towards defining SMD reliability after the soldering cycle, in order to include the effects summarised in table 1.
Figure 1 : Thermal Expansion of Moulding Compounds, Compared with the Temperature of Different Soldering Techniques.
Figure 2 : SM PCB1 Test Board.
IUdfPfi1l1rlfr~T
Uffi1T1frT Iu,u1TrfrT
dPlt~ dPlt~
j ----- ----- -----
Uffi1TrfrTUffi1TIPr?Uffi1TlPr{
dPlt~ dPlt~ dPlt~
----- ----- -----
Uffi1TrfrT Uffil1rPrf Uffi1TlPr{
dPlt~ dPltl\U dPlt%
SMPCB1.
Table 1 : Factors Affecting SMD Reliability on Printed Board.
SMD Package
Design and Structure Internal Contamination Thermomechanical Properties
Volume and Thermal Inertia Water Content Lead Solderability
Assembly Process
Soldering Method Soldering Time/temperature
Contamination Level (flux) Rinsing
Substrate
Thermomechanical Properties Thermal Dissipation
EXPERIMENTAL
Reliability tests are performed on parts soldered onto test boards (4.5 in. x 6.5 in. FR-4 substrates).
SM PCB1 test board can accept SO-8, 14, 16. It is pre-grooved, in order to be cut in 35 positions, having the lay-out shown in figure 2 ; the SMD footprints are electrically connected to through-holes, with a pitch of 100 mils and placed in two parallel rows, 600 mils apart. Commercial pins inserted in the throughholes give the possibility of using the same equipment needed by DIPs.
The soldering processes from table 2 were used for SO packaged bipolar Operational Amplifiers and CMos Standard Logic. In order to simulate a rework, the soldering cycle was repeated on a number of devices. Soldering is followed by the usual rinsing in water or Freon, with or without ultrasonics.
Table 2 : Soldering Processes Evaluated with SO Packaged Devices.
Pre-heating Soldering
Double Wave Double Wave Double Wave Triple Wave Vapour Phase Infra-red
120'C/30s 120'C/30s 110'C/30s 110'C/30s
160'C/30s
225'C/4s 250'C/4s 250'C/3.4s 260'C/3s 215'C/20s > 210'C/60s
Number of Cycles 1 1
1,2,3,4 1.2.3 1,2 1
The reliability evaluation was performed by means of the following tests:
Operating Life Pressure Pot THB
HAST
Thermal Cycles Thermal Shocks
150"C 121 "C/2atm 85"C/85% RH 15V (bips) 6V (CMos) 130"C/85% RH 15V (bips) 6V (CMos) - 55/+ 150"C (30/5/30 min) - 55/+ 150"C (5/1/5 min liquid)
130"C/85%RH Highly Accelerated Steam Test (HAST) has an acceleration factor of about 18-20 (ref. 3) in comparison with 85C/85%RH, and the concrete possibility of reaching wear-out exists with this test, after an acceptable time.
For PLCC packages a similar methodology is followed. At the time of writing, only partial data are available, which will not be included here.
2/10 1274
APPLICATION NOTE
EXPERIMENTAL RESULTS Experimental results are summarised in tables 3-6.
Table 3 : Cumulative Reliability Data after Multiple Wave Soldering.
Test Vehicles: LM2904 (SO·8), LM2901 (SO·14) and M74HC74 (SO-14)
Double Wave
22S'CI4s 2S0'CI4s
Triple Wave
260'CI3s
Operating Life 1000h
0/lS4
0132
Pressure Pot 96h
0/104
0162
THB 8S'CI8S%RH 1000h 2000h
1/10S'
0/32 0132
HAST 130'C/85%RH 100h 200h
0/64 0/64
Thermal Shocks SOO
01231
0/77
, Parametric Failure
Table 4 : Reliability Data after Vapour Phase Reflow.
Test Vehicle: LM2901 (SO·14)
215'C/20s 21S'CI40s
Operating Life 1000h
0132
Pressure Pot 96h
0132
THB 8S'CI85%RH 1000h 2000h
0132 0132
HAST 130'C/85%RH V ~ lSV 100h 200h 372h 4S8h 63Sh
0/S6 0lS6 0/24 2124 SI22
0/12 0112 1112 1111 3/10
Thermal Cycles SOO
0132
All failures due to pad corrosion
Table 5 : Cumulative Reliability Data after Infra-red Reflow.
Test Vehicles: M74HCOO and M74HC74 (SO·14)
> 210'C/60s
Operating Life 1300h
0134
THB 8S'C/85%RH 1300h
0134
HAST 130'C/8S%RH 100h 200h SOOh 672h
0/32 0/32 0/32 0132
Thermal Cycles 7S0
0170
Table 6 : Cumulative Reliability Data in Multiple Wave Soldering with Repetition of the Soldering Cycle,
Test Vehicles: LM2903 (SO·8), LM2901 and M74HCOO (SO·14)
Double Wave 250'CIS.4s
Triple Wave 260'Cl3s
Number of Cycles
123 4 123
Pressure Pot 96h S04h
0156 0lS6
100 Thermal Cycles (- 40/150'C) Followed by Pressure Pot
96h 168h 240h
0/30 0130 0160 0130 0130 0160 0130 0130 0/60
HAST 130'C18S%RH V ~ 6V
100h SOOh 1000h 1150h 1300h
0132 0132 0132 1/32' 0/18 0118 0118 0118 1118 1/18" 17117 17117"
· Parametric Failure .. Pad Corrosion
COMMENTS ON THE RELIABILITY RESULTS
Previous results do not reveal negative effects due to the exposure of SM devices to the soldering heat, for all of the industrial SMT soldering methods, in combination with the most common solders and cleaning solvents (Freon, water with and without ultrasonics),
Wear-out in the HAST test (130'C/85%RH) is between 1100 and 1300 hours when the soldering cycle is repeated up to 4 times with high temperature (250-260'C) multiple wave soldering, which is considered to transfer the highest thermal stress to the package body.
Pad corrosion is the final failure mechanism for all samples.
This performance is about 7-10 times better than the 2000-3000 h THB 85'C/85%RH, which is currently requested as qualification target in moisture resistance biased tests. Therefore, the reliability of surface mounted deVices considered in this work is high enough to meet the most stringent requirements of the professional market.
No evidence of cracks in the plastic case was found in the previous evaluations. This effect (referred to also as 'pop corn' effect) is attributed to some anom-
3/10 1275
APPLICATION NOTE
alous thermal expansion of the package in the soldering phase, caused by water absorbed by the plastic encapsulation: a thermal treatment at a temperature higher than 100°C for a few hours is suggested in order to remove the absorbed water.4 As this thermal pre-conditioning should be performed shortly before soldering, a serious problem arises in the assembly line. Such thermal annealing is not practical when the parts are supplied in plastic tapes or sticks: they should be removed from the packs by the user, heat treated, and packed again with additional costs and risks (co-planarity). In this company's experience, the 'pop corn' effect can be completely avoided by controlling the frameencapsulant interface, which is the easiest path for the water. Furthermore, experience has indicated that water at that interface does change the expansion characteristics of the package. About five years ago, the curve of figure 3 was found in some parts (coming from lots affected by the 'pop corn' problem) using Thermo-Mechanical Analysis (TMA). Devices under test were placed between the probes of the TMA transducer and their expansion characteristics recorded. In the first ramp (5°C/min), package expansion was much higher than the moulding compound expansion between 50 and 10aoC ; over 1aaoc, it returned on the curve typical of the encapsulant. Cooling down and repeating the measurement, only the lower curve of figure 3 was covered. This behaviour was attributed to water having penetrated between the frame and the plastic body, whose expansion was responsible for the package deformation during the slow heating in TMA. When the parts were soldered on the substrate, cracks could occur due to the much faster heating rate.
Figure 3 : Thermal Expansion of SO Packages.
1/10
III
The problem was solved when the possibility of controlling the water content was found, by means of an improved frame design and some dedicated production steps.
Millions of parts assembled in recent years showed no evidence of the 'pop corn' effect, without any preconditioning before use.
The same solutions are successfully adopted for PLCC packages.
THERMAL CHARACTERISTICS
Correlation between reliability and junction temperature Tj is known:
the device lifetime is roughly halved when Tj is increased by 10'C.
Mainly due to this fact, thermal dissipation is a second factor which caninfluence SMD reliability: a reduced body means worse dissipation and higher power density on the board.
As careful thermal design is the key to improved reliability, a systematic characterisation of SM packages was performed, in order to study the main factors affecting thermal dissipation at both levels of package design and board design.
In the course of this work, the need for some critical revision of the way of producing and using thermal data was evident.
A point which cannot be under-evaluated is the choice of measurement method, a:s will be discussed later.
Another important point is the following: the common way of specifying the junction to ambient thermal resistance Rth(j-a) is to associate one value of Rth(j-a) to each device.
In the majority of data books, including this company's previous literature, little information is given on the experimental conditions used to obtain that value: the dissipated power and, above all, the kind of interconnection between the package and the measurement set-up (wi~es, socket or board), which in some cases can become a far from negligible heat transfer element.
Ignoring this contribution was probably justifie with packages having a low thermal conductivity frame, such as Alloy 42 or Kovar.
For those packages, heat spreading was limited to the silicon die and to the die pad; thermal dissipation was little affected by the surroundings and the measurement assembly had little influence on the final value of Rth(j-a).
4/10
1276
APPLICATION NOTE
This is not the case concerning the same packages with a copper frame, introduced a few years ago to achieve a higher power capability; due to better thermal conductivity of the leads they are much more sensitive to external dissipating media, eventually used for the measurement.
Similar statements are valid for SMDs and become more important on account of their reduced dimensions.
The concept is summarised in table 7, where the thermal resistance of some dual-in-line (DIP), Small Outline (SO) and Plastic Leaded Chip Carrier (PLCC) packages is given. The influence of the frame thermal conductibity is remarkable; but likewise remarkable are the differences obtained for the same package, when it is connected by thin wires (and 'floating' in still air) or soldered on a PC board during the measurement.
Table 7 : Junction to Ambient Thermal Resistance (C/W) for DIP and SM Packages in Different Experimental Conditions.
n DIP 14 Leads
Alloy 42 0.25mm Cu 0.25mm
n SO·14 Leads
Alloy 42 0.25mm
Cu 0.25mm
Power Pd[W)
'Floating' in Air
On SGS Test Board
Ratio
0.5
156
0.6
125
138
1.13
90
1.39
0.4
280
0.6
190
195
1.43
105
1.80
PLCC·44 Leads ("')
Cu 0.25mm
1.0
70
52
1.35
die size: (') = 0.095 in. x 0.110 in. (") = 0.060 in. x 0.090 in. (''') = 0.180 in. x 0.180 in.
Especially for SO packages the influence of the substrate on thermal dissipation is noticeable. This fact can help to explain the following points:
1. The Rth(j-a) values published by different SMD suppliers are distributed in too wide a range (more than 70'CIW for SO packages) which handicaps a correct thermal design. Most of the difference is probably due to different test boards, and the availability of standardised measurement methodology should help to give more accurate information.
2. The board lay-out contribution shou Id be studied, in order to quantify the effect of device density: a suitable distance between two or more dissipating elements can be an effective solution for improved reliability.
3. Specification of thermal characteristics should include more elements (power level, board density, package design) which cannot be summarised in one single thermal resistance value, as was commonly the case with Alloy 42 DIPs.
A set of experimental curves was obtained for each SM package,2 which gives the relationship between these factors ; if used to feed back the board design, they should help to achieve a better thermal performance.
The most significant results will be discussed here.
Moreover, two other factors will be considered.
1. The thermal capacitance of the package, which is significant especially in· higher pin count PLCCs ; it delays Tj increase during power transients and is important in switching applications.
2. The frame design in association with a suitable board design; a low resistance thermal path can be obtained with modified frames; heat is then conveyed to copper areas obtained on the board and dissipated power can be increased to 2W with SOs and PLCCs.
EXPERIMENTAL METHOD
When thermal measurements on plastic packages are performed, the first consideration is the lack of a standard method: at present, only draft specifications5 exist, proposed in 1986 and not yet standardised.
The experimental method used in this company since 1984 has anticipated these preliminary recommendations to some extent, as it is based on the P432 thermal test pattern (figure 4) having two npn transistors, with 1OW each power capability. A sensing diode is placed on the thermal plateau ariSing when the transistors are operating in parallel and gives the actual value of Tj, through the calibration curve of its forward voltage Vf (at constant current) vs temperature.
Transistor size, which is not fixed by the documents proposed for standardisation, was intentionally limited to 1000 mils2, in order to simulate a high power density and characterise the worst case. Die size, which is found to have some influence on thermal resistance when copper frame is used, is slightly smaller than the die pad size and never exceeds 30000 mils2 in larger packages, such as high pin count PLCCs.
The measurement set-up is shown in figure 5. It is compatible with DC and AC power supply and has an accuracy better than 5%.
5/10 1277
APPLICATION NOTE
The advantages offered by the test pattern are: (i) high power capability (wider evaluation range) ; (ii) repeatable electrical characteristics (Vf) and
temperature coefficient (1.9mV/C) of the sensing element (accuracy) ; (iii) high resolution in pulsed conditions (evaluation down.to 100s pulses) ; (iv) better correlation from one package to another. Alloy 42 frames and copper frames were used for narrow SO packages (150 mils body) ; only copper frames were considered for the others : wide SO (300 mils body) and PLCC packages. Suitable FR-4 test boards were developed, which will be described case by case. Figure 4 : Test Pattern P432 Layout.
Figure 5 : Measurement System.
Samples soldered op the FR-4 test board shown in figure 2 have an approximately halved thermal resistance ; by reducing the copper pattern length of the test board, different component densities are simulated: thermal resistance is increased by about 30% when the track length has the minimum value.
Dependence of the thermal resistance on the total area of the traces connected to the package is represented by the curve of figure 7. It quantifies the effectiveness of the board lay-out to spread the heat and dissipate it towards the ambient and can be conveniently used for determining the thermal resistance value associated with a given board design.
Figure 6: RthG-a) of SO-14 Package vs. Power Level.
- SO
14 COPPER
"'-.... -......... I"---
- ---r--
floa ing i air
~U" ed on : 'H PC 1A 5G bo~
r-----
I--
-~
'H PC to 56 boo!"
I
SH PC 1 SG bo~
alumi a
B.lf1 0.28 B.38 1:1.48 B.58 ILED 8.78 B.Ba 8.ge 1.BB 1.18 DISSIPATED PDLIR ( Lklll )
Figure 7 : Rth(j-a) of SO-14 vs. on Board Trace Area.
- SO
14 COPPER
THERMAL CHARACTERISTICS IN DC CONDITIONS Thermal characteristics of the SO-14 package in DC conditions are shown in figure 6. The upper curve is related to samples floating in still air and connected to 8 thin wires needed for biasing the disSipating transistors and the sensing diode of the P432 test pattern.
6/10
1278
\
1\
.... Boo ~ area· B. 2 sq. inch
Pd
"""......r------
28
040
68
80 lE1B 128 148 168 lBB 2BB
1lI:ACE AREA ( X 1888 sq. 11115 )
APPLICATION NOTE
Figure 8 : RthU-a) of SO-14 with Copper (SGSTHOMSON) and Alloy 42 Frame.
so - 14
~:-
---......
-----r-RLLOV 0112' flW£
mgynlod on SN P BtU 5GS oard Pd - .S U
~
leoPPEo n AI£
,
DIE AREA ( x Hlle! sq. mils )
Comparison of low conductivity (Alloy 42) and high
conductivity (copper) frames is shown in figure 8.
The data obtained forthe different SM packages are
summarised in table 8 ; the two thermal resistance
values refer to the two extreme cases of a low density and a high density board.
Table 8 : Summary of Junction to Ambient
Thermal Resistance in Steady State Power Dissipation (SGS-THOMSON test boards)
Die Pad Size Power (milinches) Pd [W]
Rth(j-a) [OC/W] on' Board
SO·8 Alloy 42
90 x 100
0.2
250·310
Copper
95 x 100
0.2
160·210
50·14 Alloy 42 98 x 118
0.3
200·240
Copper
78 x 118
0.5
120·160
Copper
98 x 125
0.7
105·145
50·16 Alloy 42 98 x 118
0.3
180·215
Copper
94 x 185
0.5
95·135
SO·16W Copper 120 x 160
0.7
90·112
50·20 Copper 140 x 220
0.7
77·97
PLCC·20 Cu
180 x 180
0.7
90·110
PLCC·44 Cu
260 x 260
1.5
50·60
PLCC·68 Cu
425 x 425
1.5
40·46
PLCC·84 Cu
450 x 450
2.0
36·41
RthU·a) values correspond to low and high board density
THERMAL IMPEDANCE IN PULSED CONDITIONS The electrical equivalent of heat dissipation for a module formed by the active device, its package, the board and the external ambient is a chain of RC cells each having a characteristic risetime 1: = RC. Thermal capacitance is the capability of heat accumulation and depends on the heat capacitance of the materials, their volume and their density. When the power is switched on,. the junction temperature after a time t is the result of the subsequent charge of the RC cells, according to the well known exponential relationship:
~Tj = Rth x Pd x (1 - etl1:) When the pulse length 10 is an assigned value, effective Tj can be significantly lower than the steady state Tj (figure 9) and a transient thermal resistance Rth(to) can be defined, from the ratio between the junction temperature at the end of the pulse and the dissipated power. Obviously, for shorter pulses, transient thermal resistance is lower and a higher power can be dissipated without exceeding the maximum junction temperature defined in reliability considerations. In a similar way, when pulses of the same height Pd are repeated with a defined duty cycle DC and the pulse is short in comparison with the total risetime of the system, the train of pulses is seen as continuous source at a mean power level:
Pdavg = Pd x DC
Figure 9 : Qualitative Tj Increase for Single Power Pulse.
Tmax -+--~
J _____ I < - '_ _ __ to 5-978.(,
7/10 1279
APPLICATION NOTE
On the other hand, the silicon die has a risetime of 1·2ms and is able to follow frequencies of some kHz: junction temperature oscillates about the aver· age value:
~Tjavg = Rth oX Pdavg
as qualitatively shown in figure 10.
The thermal resistance corresponding to the peak of the oscillation at the equilibrium (peak thermal re· sistance) gives information on the maximum tem· perature reached by the device and, depending on DC and pulse width, can be much lower than DC thermal resistance.
Figure 10 : Qualitative Tj Increase for Repeated Power Pulse.
Figure 12 : Transient Thermal Resistance for PLCC·84 on Board.
84 LEAD PLCC
/'
/I II
i ._)
V
,,, Tmin~ -----'-,---'--~'"'-------="'-'---
I
I, ,
lamb _ _,_ _ _ _ _ _ _ _ _ _ _ __
~ :
Figure 11 : Test Board for PLCC.
10
1013
10013
TIr£ OR PULSe WIDTH ( Ift5 )
H10aa
The example is now given of a high pin count PLCC, which has a large thermal capacitance, due to its volume and weight.
Temperature increase for 84 lead PLCCs soldered on the 8M PCB5 test board (figure 11) for single pul· ses of different length is given in figure 12. A rise· time of 50·60s is typical for this package, having a thermal resistance of 38'C W in steady state (see table 8).
For single pulses, the effective thermal resistance is
much reduced and acceptable junction temperature
is observed even for high power pulses. 10W can
be delivered for about 1s (9'CIW) and 5W for 10s
(18'CIW).
0
Peak thermal resistance for repeated pulses, with different duty cycles, is represented in figure 13 and the above considerations are valid in this case also.
Figure 13 : Peak Transient Rth for PLCC·84 on The Board.
84 LEAD PLCC
~I o.
The knowledge of thermal characteristics in the AC
condition is a valid tool to reduce redundancy (and
'.1
cost) in the thermal design of pulsed applications.
8/10 1280
18
Hi8
lBae
TItt: OR PlLSE IJIOlli ( laS )
APPLICATION NOTE
MEDIUM POWER APPLICATION The lack of power packages suitable for SMT requirements (standard outline, automatic handling) is known. A simple way to achieve power dissipation in the medium range (1-2W) is to transform the available signal packages and modify their frame to obtain a high conduction path. In figure 14 the frame of medium power SO and PLCC packages is shown : some leads are connected to the die pad, in order to have a low junction-to-pin thermal resistance Rth(j-p). Typical values of this parameter are in the range of 1215·CIW, with a high conductivity lead frame. Modification involves the internal part of the frame only, while the external dimensions of the package are not changed; the solution offers the undoubted advantage of being compatible with existing handling and testing tools. The heat produced by the IC, and conveyed externally by the heat transfer leads, Gan be cost effectively transferred to the ambient by means of dedicated copper heatsinks, integrated on the board.
Figure 14: Medium Power SO and PLCC Frame.
In figure 15, the layout of test boards used for the thermal characterisation of medium power SO-20s (with 8 heat transfer leads) and PLCC-44s (with 11 heat transfer leads) is represented. The area of the integrated heatsink can be optimised for cost reduction, depending on the dissipation level. In figure 16 the relationship between the Rth(j-a) of the PLCC (33 + 11) and the total dissipating area is given. It can be noticed that, with 6-7 sq cm of substrate, the thermal resistance of PLCC-44s can be decreased from 55·C/W to 40·CIW, for 1.5-2W dissipation. A similar performance is possible with the medium power SOs.
Figure 15 : Test Boards for Medium Power SO-20 and PLCC-44 Package.
Figure 16 : Rth(j-a) of Medium Power PLCC-44 vs. Dissipating Area on Board.
!>I
~
~ 5l
~
~ \l'
~
~ *
~ ;;
~
~ :I
<t
~
~
~
'\ ~
"~
mounl d on 5M PCB6 lJa rd
Cb" DlSSI ~TED PO R · 1-
COPPE TInCKN 55 ~ 35 micron
~ ~
r------
2
3
4
5
6:
ON BORRO HEAT -SINK RRER ( "'q. en )
CONCLUSIONS
In SMT, two main reliability related concerns are resistance to soldering heat and heat dissipation.
RESISTANCE TO SOLDERING HEAT
After extensive evaluation of devices soldered on plastic substrates by means of the three industrial soldering methods (multiple wave soldering, vapour phase and IR reflow), no reliability degradation was found.
The following soldering conditions are possible with SO packaged devices: · Multiple Wave: T = 250 - 260·C/t = 4s (repetition
allowed) · Vapour Phase: T = 215·C/t = 20s (repetition
allowed)
· Infra-red: T > 210·C/t = 60s (Tmax = 225·C)
9/10
1281
APPLICATION NOTE
No crack in the plastic case was evidenced during the above work or in the field, in recent years of production, and no thermal preconditioning was needed. However, this result was obtained after optimisation of the frame design and of the production process. Its extension to the totality of the products existing on the market might be too arbitrary, but it is possible to conclude that the structure of SM packages, when associated with suitable materials and processes, is able to meet the user's requirements.
A similar evaluation is running for PLCC packages and will be completed in the first half of 1988.
HEAT DISSIPATION
Some considerations have been made about the consequence of the lack of some standard evaluation methodology. To standardise test chips and test boards is very important, in order to reach a better knowledge and a better information exchange.
By means of an internally developed test pattern and suitable test boards, three points have been studied:
1. The influence of the substrate on thermal dissipation, whose effect has to be taken into account much more than for insertion packages. With a proper layout it is effective in reducing thermal resistance. For example, dissipation of copper
frame SO package can become better than the equivalent Alloy 42 DIP and only 10-20% higher than the equivalent copper DIP.
2. The thermal impedance, whose value is much more suitable for the thermal design of switching applications and can contribute to reduce the cost of the system.
3. The new medium power SO and PLCC packages, which offer the possibility of cost-effective power dissipation in the range of 1.5-2W, still maintaining a standard outline.
REFERENCES
1. Nakahara, H., 'SMT Expands Options in Japan', Electronic Packaging and Production, Vol. 26, No.1, p. 58, January (1986).
2. SGS-THOMSON Application Notes 106 to 110 on SO-8, 14, 16, 16W, 20 and PLCC-20, 44 (33 +11),68,84.
3. Peck. D. S., 'Comprehensive Model for Humidity Testing Correlation', Proceedings IRPS, p. 44 (1986).
4. Fukuzawa, 1. et ai, 'Moisture Resistance Degradation of Plastic LSI by Reflow Soldering', Proceedings IRPS, p. 192 (1.985).
5. SEMI Draft Specifications 1377 and 1449 (1986).
10/10 1282
APPLICATION NOTE
HANDLING AND MOUNTING ICs IN PLASTIC POWER PACKAGES
Integrated circuits mounted in plastic powerpackages can be damaged, or reliability compromised, by inappropriate handling and mounting techniques. Avoiding these problems is simple if you follow the suggestions in this section.
Advances in power package design have made it possible to replace metal packages with more economical plastic packages in many high power applications. Most of SGS-THOMSON Microelectronics power driver circuits, for example, are mounted in the innovative MULTIWATT® package, developed originally for high power audio amplifiers. Though the intrinsic reliability of these packages is now excellent the use of inappropriate techniques or unsuitable tools during mechanical handling can affect the long term reliability of the device, or even damage it. With a few simple precautions, careful designers and production engineers can eliminate these risks, saving both time and money.
BENDING AND CUTTING LEADS
The first danger area is bending and cutting the leads. In these processes it is important to avoid
straining the package and particularly the area where the leads enter the encapsulating resin. If the package/lead interface is strained the resistance to humidity and thermal stress are compromised, affecting reliability.
There are five basic rules to bear in mind:
· Clamp the leads firmly between the package and the bend/cut point (figure 1).
Bend the leads at least 3mm from the package (figure 2a).
Never bend the leads more than 900 and never bend more than once (figure 2b).
· Never bend the leads laterally (figure 2c).
· Make sure that he bending/cutting tool does not damage the leads.
Figure 1 : Clamp the Leads between the Package and Bend/cut Point.
w
W Plastic
m packag~1 I
~:~h~~~~~g or culling
Spaced? W
'0039
Clamp mechanism
Figure 2 : Bend the Leads at Least 3mm. from the Package, never Bend Leads more than 900 and never Attempt to Splay the Leads Out.
3.0min
-"':====':':::3 RIGHT
§I I-I]."''
AN26010489
5-5)72
114 1283
APPLICATION NOTE
INSERTION
When mounting the IG on a printed circuit board the golden rule is, again, to avoid stress. In particular:
· Adhere to the specified pin spacing of the device; don't try to bend the leads to fit non-standard hole spacing.
· Leave a suitable space between the IC and the board. If necessary use a spacer.
Take care to avoid straining the device after soldering. If a heatsink is used and it is mounted on the PC board it should be attached to the IC before soldering.
SOLDERING
The greater danger during soldering is overheating. If an IC is exposed to high temperature for an excessive period it may be damaged or reliability reduced.
Recommended soldering conditions are 260°C for ten seconds or 350°C for three seconds. Figure 3 shows the excess junction temperature of a PENTAWATT package for both methods.
It is also important to use suitable fluxes for the soldering baths to avoid deterioration of the leads or package resin. Residual flux between the leads or in contact with the resin must be removed to guarantee long term reliability. The solvent used to remove excess flux should be chosen with care. In particular, trichloroethylene (CHCI : CCI2) - base solvents should be avoided because the residue can corrode the encapsulant resin.
Figure 3 : The Excess Junction Temperature of a PENTAWATT Package in the suggested Soldering Conditions.
TJ (Oe)
350·C soldering bath I
5-'51369 E.xposed to air
150
TJ ("C)
260·C soldering bath
150
100
h
50
260.C
Solder
5-5368
Exposed to air
: ,
, ,
'.5mm:
I
:
a
20 40 60 80 100
140
180
220
Time (~C)
HEATSINK MOUNTING
To exploit the full capability of a power device a suit-
able heatsink must be used. The most important as-
pect from the point of view of reliability is that the
heatsink is dimen'sioned to keep the junction tem-
perature as low as possible. From a ,mechanical
point of view, however, the heatsink mustbe desi-
gned so that it does not damage the IC. Care should
also be taken in attaching the IC to the heatsink.
The contact thermal resistance between the device
and the heatsink can be improved by adding a thin
layer of silicon grease with sufficient fluidity to en-
sure uniform distribution. Figure 4 shows how the
thermal resistance of a MULTIWATT package is im-
proved by silicone grease.
'
An excessively thick layer or an excessively viscous
silicon grease may have the opposite effect and
could cause deformation of the tab.
Figure 4 : The Thermal Resistance of a MULTIWATT Package is improved by Silicon Grease. Here Thermal Resistance is plotted against Grease Thickness.
Rth r--'-_"'---r_-.-_,.-~_G::;:-~":c:.,J6
(OC/W)
100
50
a
10
20
30
40
50
60 Time(sec)
0.05
0.10
0.15 Th(mm)
2/4 1284
APPLICATION NOTE
SGS-THOMSON plastic power packages - MULTIWATT, PENTAWATT and VERSAWATT - are attached to theheatsink with a single screw. A spring clip may also be used as shown in figure 5. The screw should be properly tightened to ensure that the package makes good contact with the heatsink. It should not be too tight or the tab may be deformed, breaking the die or separating the resin from the tab.
The appropriate tightening torque can be found by plotting thermal resistance against torque as shown in figure 6.
Suggested tightening torques for 3MA screws are 8Kg/cm for VERSAWATT, PENTAWATT and MULTIWATT packages. If different screws, or sping clips, are used the froce exerted by the tab must be equivalent to the force produced with these recommended torques.
Even if the screw is not overtightened the tab can be deformed, with disastrous results. If the surface of the heatsink is not sufficiently flat. The planarity of the contact surface between device and heatsink must be better than 50llm for PENTAWATT and VERSAWATT packages and less than 40llm for MULTIWATT packages.
Figure 5: MULTIWATT, PENTAWATT and VERSAWATT Packages are attached to the Heatsink with a Single Screw or a Spring Clip.
Figure 6 : Contact Thermal Resistance depends on Tightening Torque.
c:. ~~eJ7
R'h ('OW )
0.8
'\
~~~~~~TT
" 0.6
r-.....
i"-
~hOU' .u;,on~ .J..
0.4
"'r-..... siliclne tC'as~ ap~ied
0.2
Torqu~ (Kg/em)
Figure 7 : The Heatsink Tab may be deformed it a Washer or a Wide-headed Screw is not used.
hpat-sink
Similar problems may arise if the screwhead is too narrow compared to the hole in the heatsink (figure 7). The solution here is to use a washer to distribute the pressure over a wider area. An alternative is to use screws of the type shown in figure 8 which have a wide flat head. When self-tapping screws are used it is also important to provide an outlet for the material deformed as the thread is formed. Poor contact will result if this is not done. Another possible hazard arises when the hole in the heatsink is formed with a punch: a circular depression may be formed around the hole, leading to deformation of the tab. This may be cured by using a washer or by modifying the punch.
3/4
1285
APPLICATION NOTE
Figure 8 : The recommended Screw Type Looks Like this.
Serious reliability problems can be encountered if the heatsink and printed circuit board are not rigidly connected. Either the heatsink must be rigidly attached to the printed circuit board or both'must be securely attached to the chassis. If this is not done the stresses and strains induced by vibration will be applied to the device and in particular to the lead/resin interface. This problem is more likely to arise when large boards and large heatsinks are used or whenever the equipment is subjected to heavy vibrations.
, ... ·oo..a
I
4/4 1286
APPLICATION NOTE
TO 220AB - TOP 3 - TOPLESS THERMAL RESISTANCE AND MECHANICAL ASSEMBLY
The behaviour of a semiconductor device is directly related to the temperature of its silicon chip.
To preserve the performances of the component and to ensure optimal reliability, is to limit temperature by mastering the heat transfer between the chip and the ambient atmosphere.
The purpose of this note is to underline the importance of the mechanical assembly of the component on its heat sink by comparing different possibilities.
A - IMPORTANCE OF THE MECHANICAL ASSEMBLY
1 - THERMAL RESISTANCE
Review: The thermal resistance (Rth) of a semiconductor assembly is the parameter which characterizes its aptitude to channel the heat flow generated by the junction during operation.
AT (OC/W)
It is expressed by : Rth = P
Where P is the power dissipated by the component.
When a semiconductor component is assembled on a heat sink, the total thermal resistance should be taken into account. It is given by the following equation
Thermal resistance between junction and case
RthU-c) = Tj - Tc
-p-
Tj : Junction temperature
Tc : Case temperature
This value is specified in the data sheets and it varies according to the type of component.
Thermal resistance between case and heat sink or contact thermal resistance.
Rth(c.h) = Tc - Th
-p-
By O. DELA PATELLIERE
Th: Heat sink temperature Thermal resistance between heat sink and ambient air.
It is related mainly to the quality of the contact.
Rth(ha) =-T-h -pTa-
Ta : Ambient temperature
The thermal balance is elGpressed by the equation:
Tj - Ta = P X RthU - a) where the thermal resistance between junction and ambient air is :
RthU-a) = RthU-c)+ Rth(c-h) + Rth(h-a)
This equation of thermal balance helps to calculate the junction temperature of the component. A junction temperature which approaches the maximum temperature of the component could lead to a decrease in the electrical characteristics and a reduction of the safety margin. A temperature exceeding the maximum junction. temperature· risks damaging the semiconductor device. The junction temperature should be known at all times.
2 - TYPES OF ASSEMBLY The conventional assemblies can be divided into two types: _ assembly on heat sink, _ assembly in the air (without heat sink).
The choice of the assembly results in a compromise between the following criteria: _ convenience of use: the component should be con-
nectable and accessible for testing or replacement, _ cost, _ possibility of heat dissipation, _ mechanical resistance, _ aging and fiability.
AN314/0289
1/6
1287
APPLICATION NOTE
TYPES OF ASSEMBLY AS A FWNCTION OF THE POWER (P) AND THE TYPE OF CASE USED BY
THE COMPONENT.
.
Power Range P ~ 50 W
2 W < P < 50 W .PS,2W
Types of Cases
TOP 3
I' I TO 220
TO 220
TOP 3
TOP 3
I TOPLESS
Types of Assembly Heat Sink with Cooling Fins
Plain Heat Sink
Assembly in the Air (printed circuit board)
B - ASSEMBLY OF TOP 3 AND TO 220 ON HEAT SINKS
Among the various parameters of assembly on heat sinks, three are particularly important: _ the shape and condition of the heat sink surface, _ the pressure ofthe component on the heatsink, _ the contact grease (different types exist).
The layer spread on the flat heat sink surface should be thin and uniform. The Rth(c-h) of contact without grease ~ 1.5Rth (c-h) of contact with grease.
1 - AITACHMENT BY SCREW (figure 1)
Example: TO 220
Rth (c - h) ; 2°CfW for F ; 25N
Rth (0- h) ; 1.5 x 2 ; 3°C/W for F ; 5N
with F ; force
Advantages _ good mechanical resistance _ easy and quick disassembly _ easy to perform for short series.
Figure 1 : Attachment of the TO 220 or TOP 3 (insulated) by M3 Screw.
Contact grease
Nut
D89AN314·01
2/6 1288
APPLICATION NOTE
Figure 2 : Relative Variation of the Thermal Resistance of the Contact as a Function of the Pressure and the Tightening Torque for an M3 Screw like Figure 1.
Multiplication factor K = Alh (c-h)lAlh (c-h) (25 N)
'-._2.5
2
1.5
\
\~
0.5
-
o
10
20
30
40
Pressing force F (N)
o
0.5
1.S
2
Tightening torque C (M /I. N)
089P.N314·02
The contact thermal resistance of assembly by screw changes with the pressure of the case on the heat sink. This force depends on the tightening torque (figure 2).
Disadvantages : _ deburring of the heat sink hole _ mastering of the screw tightening torque _ assembly not suitable for long series.
2 - ATIACHMENT BY RIVET (figure 3)
Advantages : _ good mechanical resistance _ quick assembly suitable for long series
Disadvantages: _ difficult to disassemble _ risk of deforming the plastic case during assembly _ deburring of the attachment hole _ difficult to master the force applied by the riet.
3 - ATIACHMENT BY CLIP
Two types of assembly by clip exist 4a and4b)
(figures
Figure 3 : Attachment of the TO 220 or TOP 3 (insulated) by Rivet.
Rivet
Heat sink
D89AN314·03
3/6 1289
APPLICATION NOTE
Figure 4 : Example of Attachment by Clip a. for TOP 3 (ref. mP 18055) b. for TO 220.
, ....... ,
/' \
".l ~" !
o
Heal sink
30 + 0.3
r :3
.r.o.
2,3
12
3,18
(Dimensions in mm)
Advantages : _ rapidity of assembly and disassembly (automat-
ization), _ low cost, _ facility in controlling the pressure exercised by the
component on the heat sink, _ stability in time.
Example: Clip MP 18055 F=20N
D89AN314-04
Disadvantages: _ difficulty in positioning the case with respect to the
heat sink. N.B. : The fact of using a non-insulated component for an application in which the case should not be at the same potential as the heat sink makes the use of an insulator necessary (mica). This insulator whose thickness is about 0.1 mm introduces an additional thermal (contact) resistance of :
- R1h (e-h)=0.8 °CIW for the TO 220 case { Mica insulator - Rth (e-h) '" 0.5 °CIW for the TOP 3
4/6 1290
APPLICATION NOTE
C - ASSEMBLY IN THE AIR (WITHOUT
HEAT SINK) OF THE TO 220 - TOP 3 TOPLESS
The components in direct contact with the air (on a
printed circuit board) can only dissipate low power.
For example:
TO 220:
Tj _ T a 110 _ 50
Maximum dissipated power = - - = - - - = 1W
Rth U- a)
60
The evacuation of the heat produced during operation takes place at several levels : _ the case,
_ the connections,
_ the soldering points of connections on the PC board.
The influence of the length of connections, on one hand, and the area of copper at the soldering point, on the other hand, is given on figure 5 and figure 6.
Figure 5 : Relative Variation of the Thermal Resistance (junction-air) as a Function of the Length L of Connections.
----
Length L (mm)
D89AN314'()5
THERMAL RESISTANCE VALUES (junction-air)
Rth (i-a) (OC/W)
TOPLESS 75
TO 220 60
TOP 3 50
Figure 6 : Relative Variation of the Thermal Resistance (junction-air) as a Function of the Area of Copper at the Soldering Point.
Rth U-a)/Rth U-a) (1 em')
1.2
1.1
\.
\ r\. ""- ....... I ' - ~ I - .
.9
.8
Area (cm"l
D89AN314.()6
5/6
1291
APPLICATION NOTE
CONCLUSION
When designing assembly of a plastic-case semiconductor device on a heat sink, several precautions need to be taken, particularly never to exceed the maximum junction temperature (Tj max.).
The best assembly system is the one which satisfies
the thermal requirements in the simplest manner. The clip assembler, in most cases, meets these requirements. This assembly, because of the ease with which it can be performed, the uniform pressure exercised on the case and the low cost, enables obtaining optimal contact thermal resistance and mechanically reliable assembly.
CHART FOR EVALUATION OF A FIAT HEAT SINK
·C/W
Copper
r:=f-l'=""::' 100
. . . r-'---'~ -+-~
"-,-
,--
I-H t--I-
Rth(h·a)
I
,1\
l\
20
10
~ ~
Thickness (e) of the pJatcinmm
·CIW 100
Aluminium
I ,1-Ll \ \
I
;0
l
1\ 20
~~
Thickness (e) ot the plateinmm
10
.,,~
'&
~~
"l~ '" .'-
2
"\: ~
5
t- ~
~
t\'
t--..
......
t-...
0.5
"r:::
2 5
2
'" ~ ~ I'S:: l '
0.5
r" t'--
i""""
~
2
r---. 5
1
1
o
10
20 em
o
10
20 em
100 ·CIW
Steel
t 50
Rth (h-a)
I
20
10
,1\ \
~
1\
~ ~ Thickness (e) ot the plateinmm
~
.~~ ~
~
Conditions: - Bare convector - Vertical - Semiconductor device at-the centre . No ventilation - x 0.7 if painted black - square
=I length of one side of the square with an area S
5 - - _.
3
o
.~ ~ b ~ .......
r--.. i"""- 2
f' r--. 5 I
to
20 cm
Example: Copper heat sink. thickness e = 1 mm
= = Rth (h-a) S"CIW I 10 cm
D89AN314·07
6/6
1292
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AUSTRALIA
NSW 2220 HURTSVILLE Suite 3, Level 7, OtiS Hous.e 43 Bridge Street Tel. (61-2) 5803811 Telelax: (61-2) 5806440
HONG KONG
WANCHAI 22nd Floor - Hopewell centre 183 Oueen's Road East Tel. (852) 8615788 Telex: 60955 ESGIES HX Telelax: (852) 8656589
INDIA
NEW DELHI 110001 LiasonOffice 62, Upper Ground Floor World Trade Centre Barakhamba Lane Tel. (91-11) 3715191 Telex: 031-66816 STMIIN Telelax: (91-11) 3715192
MALAYSIA
PETALING JAYA, 47400 l1C, Jalan SS21/60 Damansara Utama Tel.: (03) 717 3976 Telelax: (03) 719 9512
PULAU PINANG 10400 4th Floor - Suite 4-03 Bangunan FOP-123D Jalan Anson Tel. (04) 379735 Telelax (04) 379816
KOREA
SEOUL 121 8th Iloor Shinwon Building 823-14, Yuksam-Dong Kang-Nam-Gu Tel. (82-2) 553-0399 Telex: SGSKOR K29998 Telelax: (82-2) 552-1051
SINGAPORE
SINGAPORE 2056 28 Ang Mo Kio - Industrial Park 2 Tel. (65) 4821411 Telex: RS 55201 ESGIES Telelax: (65) 4820240
TAIWAN
TAIPEI 12th Floor 325, Section 1 Tun Hua South Road Tel. (886-2) 755-4111 Telex: 10310 ESGIE TW Telelax (886-2) 755-4008
JAPAN
TOKYO 108 Nlsseki - Takanawa Bid. 4F 2-18-10 Takanawa Minato-Ku Tel. (81-3) 3280-4121 Telelax: (81-3) 3280-4131
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. Nn license is granted by implication or otherwise under any patent or patent (ights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all informatinn previously supplied. SGS-THOMSON Microelectronics products are nnt authorized for use as critical components in life support devices or systems without express written approval of SC:;S-THOMSON Microelectronics.
© 1992 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - United Kingdom - U.S.A.
EMERGING TECHNOLOGY SALES, INC. . Manufacturers Representative
373 Sinclair Frontage Road Milpitas, CA·95035 (408) 263-9366 FAX (408) 263"9566
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