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NCP1095 Product Preview PoE-PD Interface Controller, IEEE 802.3bt Description The NCP1095 is a member of the ON Semiconductor Power over Ethernet Powered Device (PoE-PD) product family, and allows the device containing the NCP1095 based PD to become an IEEE 802.3af/at and -3bt compliant powered equipment. It incorporates all the required functions for operation within a PoE system such as detection, classification and current limiting during the inrush phase. The NCP1095 supports high-power applications (up to 90 W PoE) through an external pass transistor. A power good pin guarantees proper disabling/enabling of the adjacent main DC/DC converter. The classification result pins allow for operation according to the assigned power Class (up to Class 8). The NCP1095 also offers Autoclass support and indicates when a short Maintain Power Signature can be implemented. In addition an auxiliary supply detection pin allows NCP1095 to be used in applications where power can be supplied by either PoE or by a wall adapter. Features · Fully Supports IEEE 802.3af/at and -3bt Specifications · Supports Up to 5-Event Physical Layer Classification · Assigned Power Level Up to 90 W · Supports Autoclass · 135 mA Typical Inrush Current Limiting · Open Drain Power Good Indicator · Support for Short MPS · Pass Switch Disabling Input for Rear Auxiliary Supply Operation · Proprietary 100 W+ Applications · Over Current Protection · Over Temperature Protection · Junction Temperature Range of -40°C to +125°C · Available in 16-pin TSSOP · These Devices are Pb-Free and are RoHS Compliant This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. www.onsemi.com RELATED STANDARDS IEEE 802.3bt-2018 D3.7 16 1 TSSOP-16 CASE 948F MARKING DIAGRAM 16 NCP1095 AL YYWW 1 NCP1095 A L YY WW = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device NCP1095DBR2 Package TSSOP-16 (Pb-Free) Shipping 2500 / Tape & Reel NCP1095DB TSSOP-16 (Pb-Free) 96 / Tube For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2018 1 February, 2019 - Rev. P1 Publication Order Number: NCP1095/D NCP1095 VPP 1 CLA 2 CLB 3 AUX 4 COSC 5 ACS 6 DET 7 VPN 8 NCP1095 16 NCL 15 NCM 14 PGO 13 LCF 12 RTN 11 GBR 10 PGATE 9 PSNS Figure 1. Pin-out NCP1095 in 16-pin TSSOP (Top View) PIN DESCRIPTION Signal Name Pin No. VPP 1 CLA 2 CLB 3 AUX 4 COSC 5 ACS 6 DET 7 VPN 8 PSNS 9 PGATE 10 GBR 11 RTN 12 LCF 13 PGO 14 NCM 15 NCL 16 Type Power Output Output Input Analog Input Output Power, Ground Input Output Output, Open Drain Power Output, Open Drain Output, Open Drain Output, Open Drain Output, Open Drain Description Positive input power. Connect to the positive terminal of the rectifier bridge Connect a class signature programming resistor to VPN. See classification section for recommended values Auxiliary supply detection input. Referenced to VPN Connect a 1 nF capacitor between COSC and VPN. This pin is pulled to VPP during the detection phase Autoclass enable/disable input. Pull to VPN to disable Autoclass; leave floating to enable Autoclass Connect a 26.1 kW detection resistor between DET and COSC. This pin is pulled to VPN during the detection phase Negative input power. Connect to the negative terminal of the rectifier bridge Positive current sense line. Connect to the positive side of the external sense resistor (and the source of the external pass transistor) Gate driver for the external pass transistor Control output to disable the active rectifier bridge. This pin is referenced to VPN DC/DC controller power return. Connect to the drain of the external pass transistor Long Classification Finger Indicator. This pin is referenced to RTN. Connect with a pull-up resistor to the logic supply Power Good Indicator. This pin is left floating when the power good signal is active. Referenced to RTN. Must be used to enable/disable the main DC/DC converter after NCP1095 Class result MSB output. This pin is referenced to RTN. Connect with a pull-up resistor to the logic supply Class result LSB output. This pin is referenced to RTN. Connect with a pull-up resistor to the logic supply www.onsemi.com 2 NCP1095 VPP 1 DET 7 5 COSC Oscillator Detection CLA 2 CLB 3 ACS 6 Classification AUX 4 IEEE Interface Shutdown (AUX supply prio) VPORT Monitor Switch Control & Current Limit Assigned Class Indicator Long Class Finger Active Bridge Control Power Good Indicator 15 NCM 16 NCL 13 LCF 11 GBR 14 PGO 8 9 10 12 VPN PSNS PGATE RTN Figure 2. NCP1095 Block Diagram NCP1095 www.onsemi.com 3 NCP1095 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Min Max Unit Conditions TJ TS VPP Junction temperature Storage temperature Input Power Supply -40 +150 -55 +150 -0.3 72 °C °C V Voltage with respect to VPN RTN Pass switch drain connection, application -0.3 72 ground V Voltage with respect to VPN, Pass switch in the off state PSNS Pass switch sense resistor voltage -0.3 3.6 V Voltage with respect to VPN DET Voltage on pin DET PGATE Pass switch gate drive voltage -0.3 11 V Voltage with respect to VPN PGO Power Good output -0.3 72 V Voltage with respect to RTN NCM Class result MSB output NCL Class result LSB output LCF Long Class Finger output ACS Voltage on AUTOCLASS pin -0.3 72 V Voltage with respect to VPN CLA, CLB Voltage on CLASSA or CLASSB pins GBR Active bridge control output COSC Voltage on pin COSC AUX Auxiliary supply detection input ESD-HBM Human Body Model 2 kV Per EIA-JESD22-A114 standard Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. THERMAL CHARACTERISTICS (Note 1) Symbol Characteristic Typical Value qJA Thermal Resistance, Junction-to-Air 90.3 1. qJA is obtained with 1S2P test board (1 signal 2 plane) and natural convection. Refer to JEDEC JESD51 for details. Unit °C/W RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit TJ VPORT (Note 2) Junction Temperature Input Power Supply (VPORT = VPP VPN) -40 +125 °C 0 57 V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 2. Refer to ABSOLUTE MAXIMUM RATINGS for Safe Operating Area. www.onsemi.com 4 NCP1095 ELECTRICAL CHARACTERISTICS (All parameters are guaranteed for the recommended operating conditions unless otherwise noted) Symbol Parameter Min Typ Max Unit Condition DETECTION CHARACTERISTICS Rdetect Equivalent detection resistance 23.7 VoffsetIC Detection offset voltage (IC part) 26.3 0.2 kW RDET = 26.1 kW ±1%; V 1 V VPORT 10.1 V CLASISFICATION CHARACTERISTICS Vcl_th Class/Mark current switchover threshold 10.1 (Note 3) 12.5 V VPORT rising or falling Vcldis Classification current disable threshold 20.5 (Note 3) 24.5 V VPORT rising or falling Iclsigq Vcsr Quiescent current during classification CLASS driver voltage (Note 3) during class event 200 316 500 8.5 9.15 9.7 mA VPORT = 12.5 V V 12.5 V VPORT 20.5 V Iclsig0 Iclsig1 Iclsig2 Iclsig3 Iclsig4 Imark tfce RclassA,B = 4.5 kW ±1% RclassA,B = 909 W ±1% RclassA,B = 511 W ±1% RclassA,B = 332 W ±1% RclassA,B = 232 W ±1% IPP during mark event range Short/Long first class event threshold 1 4 9 12 17 20 26 30 36 44 1.5 2.4 4 75 88 tacspd Change to class signature `0' current 75.5 87.5 timing RC OSCILLATOR CHARACTERISTICS fosc Frequency of the oscillator 26.8 duty Oscillator duty cycle 50 PASS SWITCH CURRENT CONTROL STATE CHARACTERISTICS Iinr Inrush current 105 135 160 Vdrain_pg RTN PowerGood threshold voltage (Note 3) 0.7 0.8 0.9 Vgate_pg PGATE PowerGood threshold voltage 6.9 8.5 10.0 (Note 3) Vpgo_low PGO output low voltage - 0.15 0.50 tminpgo Minimum time the PGO pin is held low PASS SWITCH ON STATE CHARACTERISTICS Idd_on Operating current Ioc Over current detection level Voc RTN overcurrent detection voltage (Note 3) 80 120 180 200 336.7 500 5.0 6.4 8.0 1.1 1.2 1.3 UNDER-VOLTAGE LOCK-OUT CHARACTERISTICS UVLO_H VPP UVLO threshold voltage (Note 3) 32 34 36.1 UVLO_L UVLO_hyst VPP UVLO threshold voltage (Note 3) UVLO threshold hysteresis 30.4 32.2 34.2 1.68 1.80 1.92 mA 12.5 V VPORT 20.5 V mA 12.5 V VPORT 20.5 V mA 12.5 V VPORT 20.5 V mA 12.5 V VPORT 20.5 V mA 12.5 V VPORT 20.5 V mA VPORT = 10.1 V ms RDET = 26.1 kW ±1%; COSC = 1 nF ±2% ms Autoclass enabled kHz RDET = 26.1 kW; COSC = 1 nF % mA 25 mW Sense Resistor V RTNVPN falling V PGATE-VPN rising V Isink = 2 mA. Referenced to RTN ms mA A 25 mW Sense Resistor V RTNVPN rising V VPORT rising V VPORT falling V www.onsemi.com 5 NCP1095 ELECTRICAL CHARACTERISTICS (continued) (All parameters are guaranteed for the recommended operating conditions unless otherwise noted) Symbol Parameter Min Typ Max Unit Condition RESET CHARACTERISTICS Vrst VPP reset threshold voltage (Note 3) 2.81 3.85 4.9 AUXILIARY SUPPLY DETECTION CHARACTERISTICS V VPORT falling AUX_H AUX input high level voltage (Note 3) 2.0 2.5 2.9 V AUX_L AUX input low level voltage (Note 3) 0.5 0.75 1.05 V AUX_hyst AUX threshold hysteresis 1.2 1.7 2.2 V AUX_pd AUX internal pull down 180 265 380 kW VAUX = 0.5 V CLASSIFICATION RESULT INDICATOR CHARACTERISTICS Vlow NCL, NCM or LCF output low voltage - 0.15 0.50 V Isink = 2 mA. Referenced to RTN GRB CHARACTERISTICS Vgbr_low GBR output low voltage (Note 3) - 0.15 0.50 V Isink = 2 mA PASS SWITCH OFF STATE CHARACTERISTICS Idd_off Poweroff current THERMAL PROTECTION CHARACTERISTICS - 260 - mA VPORT = 57 V TSD Thermal shutdown threshold 150 - - °C Junction temperature Thyst Thermal hysteresis - 15 - °C Junction temperature Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Voltage referenced to VPN. www.onsemi.com 6 RJ45 DA+ 1 DA- 2 DB+ 3 DC+ 4 DC- 5 DB- 6 DD+ 7 DD- 8 NCP1095 SIMPLIFIED APPLICATION SCHEMATIC DATA + BS termination Vpd,A Vpd,B GDC GDC U2 IN2 G2 FDMQ8205A G1 G3 OUTP G4 OUTN IN1 U3 IN2 G2 FDMQ8205A G1 G3 OUTP G4 OUTN IN1 D1 C1 Vport U1 1 7 RDET 5 COSC 2 RCLASSA 3 RCLASSB 6 VPP DET COSC CLA CLB ACS 8 VPN NCP1095 CPD 4 AUX 14 PGO 15 NCM NCL 16 LCF 13 11 GBR RTN PGATE PSNS 9 10 12 RSNS T1 Figure 3. General Application Schematic To DC/DC Controller To mC TYPICAL BILL OF MATERIALS Reference Designator Description U1 U2, U3 PoE Interface GreenBridget Rectifier D1 TVS Protection C1 VPP decoupling capacitor COSC Oscillator capacitor CPD VPP bulk capacitor RDET Detection resistor RCLASSA Classification resistor A RCLASSB Classification resistor B RSNS Current sense resistor T1 Pass switch Value (Nominal) NCP1095 FDMQ8205A 58 V 100 nF/100 V 1 nF 10 mF/80 V 26.1 kW 232 W 332 W 25 mW 100 V/40 mW Tolerance ±10% ±2% ±20% ±1% ±1% ±1% ±1% Manufacturer ON Semiconductor ON Semiconductor Part Number NCP1095 FDMQ8205A Littelfuse Walsin Murata Panasonic Panasonic Panasonic Panasonic Yageo ON Semiconductor SMBJ58A 0805B104K101CT GRM1885C1H102GA01D EEEFK1K100XP ERJ3EKF2612V ERJ8ENF2320V ERJ6ENF3320V RL1206FR-070R025L FDMC8622 www.onsemi.com 7 NCP1095 APPLICATION INFORMATION The NCP1095 is a Power over Ethernet Powered Device (PD) interface controller with an external n-channel MOSFET load switch. Powered Device Interface The NCP1095 is located at the interface of the PD and will interact with the Power Sourcing Equipment (PSE) over the Ethernet cable. NCP1095 allows the device to be powered by an IEEE 802.3af/at or -3bt compliant PSE. It provides a detection signature, classification handshaking, inrush current limitation and operational overcurrent protection. A block diagram is shown in Figure 2. Each section will be explained in more detail below. Detection During the detection phase, the PSE will check if a valid or a non-valid detection signature is present. This will enable the PSE to differentiate between equipment supporting PoE requesting power and equipment either not supporting PoE or not requesting power. In order to be able to present a valid detection signature to the PSE, a 26.1 kW resistor must be inserted between the COSC and DET pins of NCP1095. During the detection phase all blocks of the chip are in power-down except for an internal reference, a comparator and two switches. When the voltage at the PD power interface is within the detection range, the COSC pin is pulled to VPP and the DET pin is pulled to VPN, resulting in the PD presenting a valid detection signature. The offset voltage of the input rectifier bridge should be between 0 and 1.7 V in the detection range (2.7 V VPD 10.1 V). When the PSE has detected a valid detection signature and continues towards powering on the PD, the COSC and DET switches are turned off in order to reduce the current consumption of the PD. VPP COSC RDET DET 1,2 V VPN Figure 4. Detection Circuit Classification A PD is characterized based upon the maximum power level it requires at its power interface during operation. The IEEE 802.3bt standard supports up to 71.3 W PDs and defines 8 power Classes: Class 1 up to Class 8. The PD must conform to a Class with a power level that is at or above the maximum power the PD requires. Table 1 lists the different Classes and the corresponding power level they stand for. Based on the Class the PD conforms to, two resistance values are listed. The RclassA value must be inserted between CLA and VPN. Likewise, the RclassB value must be inserted between CLB and VPN. Eventually, when implementing a Class 1, 2, 3 or 4 PD, the CLA and CLB pins can be shorted together to the same single resistor. Table 1. CLASSIFICATION RESISTOR VALUE PD Class PD Power RCLASSA (Note 5) RCLASSB (Note 5) 0 (Note 4) 13 W 4.5 kW 4.5 kW 1 3.84 W 909 W 909 W 2 6.49 W 511 W 511 W 3 13 W 332 W 332 W 4 25.5 W 232 W 232 W 5 40.0 W 232 W 4.5 kW 6 51.0 W 232 W 909 W 7 62.0 W 232 W 511 W 8 71.3...90 W 232 W 332 W 4. 3bt compliant PDs should use Class 1, 2 or 3 instead of Class 0. 5. All resistors must be 1% accurate. Once the PSE device has detected the PD device, the classification process begins. The NCP1095 is fully capable of responding and completing classification with all PSE types described in the 802.3af/at and -3bt PoE Standard. The Class requested by NCP1095 during classification is determined by the resistors connected to the CLA and CLB pins. Depending on the power the PSE is able to deliver to the PD, the PSE will generate a different number of class-mark events. This will determine the amount of power the PD is allowed to use. Next to that, the NCP1095 is able to distinguish between a 3bt compliant PSE and a 3af/at compliant PSE. Therefor a 1 nF capacitor must be inserted between COSC and VPN. The classification results will be written to the status outputs NCL, NCM and LCF. The offset voltage of the input rectifier bridge should be between 0 and 2 V in the detection range (14.5 V VPD 20.5 V). During a class event, the power dissipation in the Rclass resistor can be significant (Vcsr2/Rclass) and its package size must be chosen properly. When the port voltage rises above Vcldis the class drivers will be disabled in order to limit the power dissipation. www.onsemi.com 8 NCP1095 Inrush Current Limiting When the PSE has successfully assigned the PD to a specific Class in correspondence with the power the PSE is able to deliver, the PSE will increase the voltage at its power interface up to its internal power supply voltage. NCP1095 will enter the inrush current control state once its port voltage rises above the UVLO_H threshold. In this state, NCP1095 will control the charging of its port capacitance CPD located between VPP and RTN by operating the pass switch transistor in the active region. The current through the pass switch is regulated by monitoring the voltage over an external sense resistor RSNS = 25 mW. NCP1095 will limit the inrush current well below the PSE inrush threshold while charging its port capacitance. The nominal level of the inrush current is 135 mA typ. The NCP1095 will exit the inrush current control state when the voltage between RTN and VPN is smaller than 0.8 V and the gate voltage rises above 8.5 V. At this stage, the port capacitance can be considered to be fully charged, and NCP1095 will enter the normal operation mode with the pass switch completely turned on. If due to an output short error condition, the inrush current control state will be aborted to protect the pass-switch. In order not to be considered as a short, the port capacitance should be chosen not to have too high a value (above 835 mF). Class 1 and 2 PDs should operate according to their power Class 50 ms after the UVLO_H threshold was crossed. Therefore it is recommended to limit the port capacitance to 59 mF for Class1 PDs and to 99 mF for Class2 PDs. PGO Indicator While in the inrush current control state, the PGO output will be held low by NCP1095. VPP VPP VPP VPP 14 PGO Load RT1 EN to DC/DC Q1 14 PGO Load RT1 Q1 NCP1095 D1 RTN NCP1095 D1 VPP VPP RTN EN to DC/DC This PGO output MUST be used to hold off the adjacent main DC/DC converter as well any significant load present between VPP and RTN. This is important in order not to further increase the already significant stress in the pass-switch during inrush. Figure 5 shows how to hold off a significant load and a DC/DC converter which has either an /EN, EN or UVLO input. System Start-up Once NCP1095 exits the inrush current control state, it will make the PGO output floating, indicating the main DC/DC converter - and eventually the system - is allowed to start. This also indicates NCP1095 will no longer actively limit the current and/or the power, as the pass switch is on and will be left turned on. PDs requesting Class 4 or higher need to take into account that they can be underpowered and need to implement some basic functionality with Class 3 power level. Also, the microcontroller will only be able to read the classification result after system startup. Therefore the main DC/DC converter and the system must be able to start up with Class 3 power (or lower for Class 1 and Class 2 PDs) and turn on higher power loads only if this is allowed by the PSE assigned Class. Even when being assigned to Class 4 or higher by the PSE, the PD is only allowed to use this increased power level 80 ms after the UVLO_H threshold was crossed. The nominal delay introduced to charge the port capacitance can be calculated from the formula below. Cpd (mF) @ Vpd (V) tcharge (ms) + 127 (eq. 1) As an example, it typically takes 80 ms to charge a 203 mF capacitor to 50 V. Depending mainly on the chosen port capacitor value, this 80 ms delay may or may not yet have passed when the NCP1095 exits the inrush current control state. NCP1095 has an additional internal timer that prevents PGO to become floating before it is expired (tminpgo = 120 ms typ). Load RT1 14 PGO Q1 NCP1095 CT D1 RT2 RB RTN UVLO to DC/DC Figure 5. PGO Interfacing www.onsemi.com 9 NCP1095 NCM and NCL Indicators The state of the NCM and NCL outputs provides information about the power level that the PSE has assigned to the PD during classification. These status outputs are actually only relevant for PDs requesting Class 4 or higher as those need to take into account that they can be underpowered. See Table 2 to determine the assigned power based on the NCM and NCL outputs and the requested Class. An underpowered PD can eventually be assigned to Class 3, 4 or 6. Table 2. CLASSIFICATION RESULT OVERVIEW Requested Class NCM NCL Assigned Class Assigned Power 4 open open 3 13 W open low 4 25.5 W low X 5 open open 3 13 W open low 4 25.5 W low X 5 40 W 6 open open 3 13 W open low 4 25.5 W low X 6 51 W 7 open open 3 13 W open low 4 25.5 W low open 6 51 W low low 7 62 W 8 open open 3 13 W open low 4 25.5 W low open 6 51 W low low 8 71.3...90 W PDs assigned to Class 8 may consume greater than 71.3 W as long as they guarantee not to exceed the 90 W power limit at the PSE power interface. Operation beyond 71.3 W is, however, only possible if additional information is available to the PD regarding the actual link section DC resistance between the PSE and the PD. The application should always operate at or below the assigned power limit. Failing to do so will result in the PSE disconnecting the PD. LCF Indicator The state of the LCF output provides information (retrieved during classification) about the type of PSE the PD is connected to. · LCF is left floating: The PSE is categorized according to 802.3af/at (PSE Type 1 or Type 2). · LCF is low: The PSE is categorized according to 802.3bt (PSE Type 3 or Type 4). Maintain Power Signature There is a minimum amount of current a PD needs to draw in order to allow the PSE to determine if the PD is still connected. This is called the Maintain Power Signature (MPS). If the PD no longer maintains this, the PSE may disconnect the power. IPORT 16 mA 10 mA 7 ms Short MPS MPS 75 ms 250 ms Figure 6. MPS The current needs to be at or above a certain current threshold (IPort_MPS,Min) during at least a certain amount of time (TMPS_PD,Min). If this has been the case, the current may fall below the threshold for at most a certain dropout period (TMPDO_PD,Max). Whether or not the lower power short MPS may be used depends upon the state of the LCF output. Table 3. MPS TIMING LCF open TMPS_PD,Min 75 ms low 7 ms TMPDO_PD,Max 250 ms 310 ms For PDs requesting Class 4 or less the MPS current threshold will always be 10 mA. For PDs requesting Class 5 or above the MPS current threshold will depend upon the assigned Class (which in fact can be determined by the state of the NCM output). www.onsemi.com 10 NCP1095 Table 4. MPS CURRENT Assigned Class 4 5 IPort_MPS,Min 10 mA 16 mA An important remark is that the PD load current will be low-pass filtered by its port capacitance and the actual resistance of the cable. This should be taken into account when generating current pulses for MPS. The PD needs to maintain the MPS as soon as its port voltage rises above the UVLO_H threshold. Depending on the amount of port capacitance and the type of PSE it is connected to, the time duration of the inrush current control state might or might not be enough (TMPS_PD,Min) to count as the first valid current pulse. In combination with 3bt PSEs this will usually not be a problem as it typically takes 7 ms to charge just a 17.8 mF cap to 50 V. In combination with 3af/at PSEs the situation is different as it typically takes 75 ms to charge a 217 mF cap to 44 V. Autoclass 802.3bt foresees an optional extension of classification known as Autoclass. This allows a 3bt certified PSE to better allocate its power among different PDs. When the ACS pin is connected to VPN, Autoclass is disabled. When the ACS pin is left floating, Autoclass is enabled and NCP1095 will request an Autoclass measurement to a 3bt type of PSE during classification. If Autoclass is enabled and the LCF output is low, the system must go to the maximum power state according to its assigned Class no later than 1.35 s after power has been applied, and keep the maximum load active until at least 3.65 s after power has been applied. During this period, the PSE will measure the maximum power draw of the PD and allocate this amount of power to the PD. Peak Power and Transients Although the PoE standard allows the PD to draw slightly higher peak power during a short time, making use of this is not recommended. It is best to keep this additional margin only to be able to withstand voltage transients on the PSE side. The required recovery time for transients also limits the amount of the port capacitance that can be used. Under Voltage Lockout If the port voltage falls below the UVLO_L threshold and remains low for a sufficient amount of time, NCP1095 will enter the poweroff state, turn off the pass switch and transition further to the offline state (pd_reset set to TRUE). Once the port voltage falls below the reset threshold Vrst, pd_reset will be set to FALSE and the NCP1095 will re-enter the idle state and can again be detected as a PD requesting power. Operational Current Protection In the normal operation mode, NCP1095 will monitor the current through the pass switch and provide protection against soft and hard shorts. Soft shorts are detected if the current is above the short circuit threshold IOC (6.4 A typ) and a time out delay of 960 ms is passed. After this time-out delay the pass switch is disabled. A hard short is detected if the voltage across the pass-switch and sense resistor is above VOC (1.2 V typ). The pass gate is switched off within 18 ms in this case. Thermal Shutdown The NCP1095 includes a thermal shutdown which protects the device in the case that the junction temperature is too high. An on-chip sensor monitors the temperature. Once the thermal shutdown threshold (TSD_H) is exceeded, all functions are disabled and the device goes into the offline state. The device will remain in offline until the junction temperature drops below TSD_L and the port voltage falls below the reset threshold Vrst. www.onsemi.com 11 PSE DETECT VPD TPON 0-400 ms CLASSIFICATION VPORT_PD(min) NCP1095 TAUTO_PSE1 1400-1600 ms TAUTO_PSE2 3100-3500 ms UP POWER_ON 50-75 ms PSE REFERENCE PD REFERENCE IPORT TLCF 88-105 ms t TAUTO_PD2 TAUTO_PD1 3650 ms 80-1350 ms INRUSH STARTUP MAXIMUM POWER TACS 75,5-87,5 ms V(VPP-RTN) t mC active and starts the application t V(PGO-RTN) PPD,Max 120 ms,typ Inrush Power Class 3 80 ms t Power Class 8 Power Class 7 Power Class 6 Power Class 5 Power Class 4 Power Class 3 t Figure 7. Complete Start-up Diagram of a Class 8 PD with Autoclass www.onsemi.com 12 NCP1095 PoE System Overview The overall PoE standard distinguishes between four Types of PSEs and four Types of PDs. · Type 1 PSEs and PDs behave according to 802.3af/at · Type 2 PSEs and PDs behave according to 802.3at · Type 3 and 4 PSEs and PDs behave according to 802.3bt Table 5 gives an overview of the system parameters that are allowed and required for operation at a certain power level (assigned Class). An important parameter is the cable DC resistance (determined by cable type and length). In general a Cat 5 cable is required when using a Type 3 or Type 4 PD or PSE in the system or when both PSE and PD are of Type 2. Operation over 4-pair is reserved for Type 3 and 4 PSEs. Table 5. SYSTEM PARAMETERS OVERVIEW Assigned Class PSE Type Minimum Cabling Type 1 1 Cat 3 (Note 6) 2 Cat 3 3, 4 Cat 3 2 1, 2 Cat 3 3 Cat 5 (Note 7) 4 Cat 5 3 1 Cat 3 1 Cat 3 (Note 8) Number of Powered Pairs 2p 2p/4p 2p 2p/4p 2p 2p 2 Cat 3 3, 4 Cat 5 2p/4p 4 2 Cat 5 2p 3, 4 2p/4p 5 3, 4 Cat 5 4p 6 3, 4 Cat 5 4p 7 4 Cat 5 4p 8 4 Cat 5 4p 6. Critical for: 44 V/4 W source connected to 3.84 W load over 20 W. 7. Critical for: 50 V/6.7 W source connected to 6.49 W load over 12.5 W. 8. Critical for: 44 V/15.4 W source connected to 13 W load over 20 W. PD Type 1 3 1 3 1 1 2 1 2 3 4 2 3 4 3 3 4 4 4 Requested Class 1 2 0, 3 0, 3 4 0, 3 4 3, 4/5/6 7/8 4 4/5/6 7/8 5 6 7, 8 7 8 Standard 802.3af/at 802.3bt 802.3af/at 802.3bt 802.3af 802.3at 802.3af/at 802.3at 802.3bt 802.3at 802.3bt 802.3bt 802.3bt 802.3bt 802.3bt www.onsemi.com 13 NCP1095 Auxiliary Supply To support applications connected to non-PoE enabled networks and to minimize the bill of materials, the NCP1095 supports drawing power from an alternate or local power source and allows a simplified design with auxiliary supply priority. NCP1095 has a high voltage compliant AUX input pin. When pulled high, it will turn off the pass switch. This feature is useful for PD applications where the auxiliary supply has to be dominant over the PoE supply. When the auxiliary supply is inserted into a PoE powered application, the pass switch disconnection will move the current path from the PSE to the rear auxiliary supply. Since the current delivered from the PSE will go below the DC MPS level (as specified in the IEEE 802.3af/at, -3bt standard) the PSE will disconnect the PoE-PD. The auxiliary supply is connected between VPP and RTN with a serial diode D1 between VPP and VAUX+, as shown in Figure 8. It is recommended to use the circuit with PNP transistor in combination with an auxiliary supply. VPP Q1 VPP D1 VAUX + Cb VPN Rt 4 NCP 1095 AUX RTN PGATE PSNS Rb 9 10 12 Rbb VAUX - R SNS RTN Figure 8. AUX Pin Interfacing If a too low aux (10.1 V...24.5 V) is inserted before the UVLO threshold was crossed by the PSE, the class driver could become unintentionally activated. If this is the case, the additional current draw can be easily prevented by taking a lower upper detection threshold (< 10.1 V). GBR Output If the AUX input pin of NCP1095 is pulled high, it will immediately drive the GBR pin low. This allows the GreenBridge input rectifiers to be disabled. The GBR pin must be used to disable the GreenBridge when a high voltage (> 30 V) auxiliary supply is used in order to be sure the PD does not source power. Dual-signature PD Up to now the description has been for a PD compliant to IEEE 802.3af/at or a single-signature PD compliant to IEEE 802.3bt. The IEEE 802.3bt standard also introduces the concept of a dual-signature PD. These have a separate input bridge rectifier and PD controller for each alternative or mode (A and B). The maximum input average power is different for a Class 5 dual-signature PD (35.6...45 W) compared to a Class 5 single-signature PD. More general, a dual-signature PD uses a different class B resistance value. Table 6. CLASSIFICATION RESISTOR VALUE PD Class RCLASSA (Note 9) RCLASSB (Note 9) PD Power 1 909 W 4.5 kW 3.84 W 2 511 W 4.5 kW 6.49 W 3 332 W 4.5 kW 13 W 4 232 W 4.5 kW 25.5 W 5 232 W 332 W 35.6...45 W 9. All resistors must be 1% accurate. The NCM, NCL and LCF outputs behave in a similar way. Table 7. CLASSIFICATION RESULT OVERVIEW Requested Class NCM NCL Assigned Class Assigned Power 4 open open 3 13 W open low 4 25.5 W low X 5 open open 3 13 W open low 4 25.5 W low X 5 35.6...45 W The MPS timing is the same for dual-signature PDs and can be retrieved from Table 3 based on the LCF output. The MPS current threshold however is always 10 mA for dual-signature PDs (on each pairset), even if assigned to Class 5. Dual-signature PDs never have Autoclass implemented, so ACS should be connected to VPN. Reference All information regarding Power over Ethernet over 4 Pairs can be found in document IEEE P802.3btt/D3.7. This draft is an amendment of IEEE Std 802.3t-2018. www.onsemi.com 14 RJ45 DA+ 1 DA- 2 DB+ 3 DC+ 4 DC- 5 DB- 6 DD+ 7 DD- 8 NCP1095 SIMPLIFIED APPLICATION SCHEMATIC WITH AUXILIARY SUPPLY DATA + BS termination Vpd ,A Vpd ,B D3 GDC GDC U2 IN2 G2 FDMQ8205A G1 G3 OUTP G4 OUTN IN1 U3 IN2 G2 FDMQ8205A G1 G3 OUTP G4 OUTN IN1 D1 C1 Vport Auxiliary Supply VAUX(+) VAUX(-) Rt Q1 Cb Rb Rbb D2 U1 1 VPP RDET 7 DET 5 COSC 2 RCLASSA 3 RCLASSB 6 COSC CLA CLB ACS 8 VPN 9 RTN NCP1095 PGATE PSNS 4 AUX 14 PGO 15 NCM 16 NCL LCF 13 11 GBR 10 12 RSNS T1 CPD To DC /DC Controller To mC Figure 9. General Application Schematic with Auxiliary Supply www.onsemi.com 15 NCP1095 PACKAGE DIMENSIONS TSSOP-16 CASE 948F ISSUE B 0.15 (0.006) T U S 16 2X L/2 L PIN 1 IDENT. 1 0.15 (0.006) T U S C 0.10 (0.004) -T- SEATING PLANE D 16X K REF 0.10 (0.004) M T U S V S 9 J1 B -U- J N 8 K ÇÇÉÉÇÇÉÉK1ÇÇÉÉ SECTION N-N 0.25 (0.010) M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. A -V- G N F DETAIL E H DETAIL E -W- MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C --- 1.20 --- 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.18 0.28 0.007 0.011 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0_ 8_ 0_ 8_ SOLDERING FOOTPRINT 7.06 1 16X 0.36 16X 1.26 0.65 PITCH DIMENSIONS: MILLIMETERS www.onsemi.com 16 NCP1095 GreenBridge is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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