1 Introduction
Configurable continuous SRAM address is a new and beneficial feature on the MCXA series. Continuous SRAM address offers the following benefits:
- Convenient for DMA operation leveraging the continuous SRAM address mapping.
- Suitable for applications that require a large continuous SRAM region, such as graphic display.
This application note considers MCXA156 as an example to demonstrate how to configure and use a continuous SRAM address.
2 Memory map and architecture
This section describes the memory map and memory architecture of MCXA156.
2.1 Memory map
Table 1 shows the memory map of MCXA156, which can also be found in the attachment of the Reference Manual. The address of SRAM X0 Alias follows the end of SRAM B2, offering a continuous address space with SRAM A0, A1, A2, A3, B0, B1, and B2. As a result, there are a total of 128 KB SRAMs with continuous address.
| Start address (hex) | End address (hex) | Size (KB) | Description |
|---|---|---|---|
| 04000000 | 04001FFF | 8 | SRAM X0 (Slave Port 0) |
| 04002000 | 04002FFF | 4 | SRAM X1 (Slave Port 0) |
| 20000000 | 20001FFF | 8 | SRAM A0 (Slave Port 1) |
| 20002000 | 20005FFF | 16 | SRAM A1 (Slave Port 1) |
| 20006000 | 20007FFF | 8 | SRAM A2 (Slave Port 1) |
| 20008000 | 2000FFFF | 32 | SRAM A3 (Slave Port 1) |
| 20010000 | 20017FFF | 32 | SRAM B0 (Slave Port 3) |
| 20018000 | 2001BFFF | 16 | SRAM B1 (Slave Port 3) |
| 2001C000 | 2001DFFF | 8 | SRAM B2 (Slave Port 3) |
| 2001E000 | 2001FFFF | 8 | SRAM X0 Alias |
Note: The SRAM X0 Alias region is reserved by default.
2.2 Memory architecture
Figure 1 shows the memory architecture of MCXA156. To access the SRAM X0 Alias region address, enable the corresponding CPU0_SBUS, DMA0, and USB0 bits of the AHB matrix remap control (remap) register in the SYSCON module. As a result, the CM33 System Bus, DMA, and USB FS can access up to 128 KB continuous address. After enabling the bits of remap, both SRAM X0 (0x04000000-0x04001FFF) and SRAM X0 Alias (0x2001E000-0x2001FFFF) region can be accessed. When the SRAM X0 Alias address is accessed, the address gets translated to the corresponding SRAM X0 address. Then the user can access the SRAM X0.
Figure 1. Memory architecture: A block diagram illustrating the memory architecture of the MCXA156. It shows connections between the CM33 core, DMA, USB FS, and the Multi-layer AHB matrix to various memory blocks including ROM, Flash, SRAM X0, SRAM X1, SRAM A0-A3, SRAM B0-B2, and SRAM X0 Alias. A legend indicates which components can access these blocks directly and which require remap bits to be enabled. The diagram specifically notes that CM33 accesses SRAM X0 Alias via the System Bus and SRAM X0 via the Code Bus.
3 SRAM X0 Alias usage limitations
This section lists the limitations on SRAM X0 Alias usage as follows:
- Enable the corresponding remap bit before accessing the SRAM X0 Alias region.
- Consider the value of the stack pointer (SP). The user usually wants to define a continuous SRAM address in the linker file and allocate the stack region at the end of the SRAM. The stack pointer is 32-bit and the stack region must be 32-bit aligned, so the initial stack pointer address is usually the defined SRAM end address plus one.
If the user wants to use the SRAM X0 Alias region, the initial stack pointer has to be 0x20020000. The ROM checks the stack pointer before jumping to the extended bootloader. For the MCXA156 extended bootloader, the valid stack pointer region is 0x20000000 to 0x2001FFFF and 0x04000000 to 0x04002FFF, so 0x20020000 is an invalid address. This is the stack pointer limitation of SRAM X0 Alias usage.
4 Workarounds
This section describes the two workarounds to configure continuous SRAM address.
4.1 Workaround to allocate the STACK space to form continuous SRAM address
To allocate the STACK space at the end of a valid stack pointer region and enable remap bits, perform the following steps:
- Set the initial stack pointer to 0x2001FFFC, which is a valid stack pointer address for ROM validation and is 32-bit aligned.
- The SRAM space from 0x2001FFFD to 0x2001FFFF can be used for data to check the safety of a stack pointer.
- Then, enable the corresponding remap bit before using the stack.
4.2 Workaround to cheat the ROM to validate the SP value successfully to form a continuous SRAM address
To cheat the ROM and form a continuous SRAM address, perform the following steps:
- Set the first word of the vector table to a valid stack pointer value.
- Then, enable the corresponding remap bit.
- Set the SP register to the desired value before using the stack.
Note: The SP value in the vector table is only for ROM checking, not for the real SP value. Therefore, take care when using the SP value in the vector table in the application code.
The following sections describe the detailed steps of this workaround for different IDEs. To modify the project code to implement the continuous SRAM address in the MCUXpresso IDE, perform the following steps: Figure 2. SRAM settings in MCUXpresso IDE: A screenshot of the MCUXpresso IDE showing the memory configuration settings for the MCXA156. It details the memory regions like Flash, SRAM, and SRAMX, along with their addresses and sizes, indicating how to adjust them to include the SRAM X0 Alias region. Figure 3. Set the first word of the vector table in startup_mcxa156.c: A C code snippet showing the definition of the vector table in Figure 4. Enable remap and configure the SP register in startup_mcxa156.c: A C code snippet demonstrating the To modify the project code to implement the continuous SRAM address in IAR IDE, perform the following steps: Figure 5. SRAM settings in linker file: A C preprocessor directive snippet showing how to define symbols and memory regions in a linker script for IAR IDE, specifically adjusting Figure 6. Set the first word of the vector table in startup_MCXA156.s: An assembly code snippet for Figure 7. Enable remap and configure SP register in startup_MCXA156.s: An assembly code snippet for To modify the project code to implement the continuous SRAM address in the Keil IDE, perform the following steps: Figure 8. SRAM settings in linker file: A C preprocessor directive snippet showing how to define symbols in a linker file for Keil IDE, specifically adjusting Figure 9. Set the first word of the vector table in startup_MCXA156.S: An assembly code snippet for Figure 10. Enable Remap and configure SP register in startup_MCXA156.S: An assembly code snippet for 4.2.1 MCUXpresso IDE
startup_mcxa156.c. It highlights the _vStackBase which serves as the initial stack pointer for ROM validation.ResetISR function. It shows assembly instructions to enable the remap bit (writing to 0xE000ED08 and 0x40091200) and configure the Stack Pointer (MSP) and MSPLIM registers with the correct stack region values.4.2.2 IAR IDE
m_data_end to include the SRAM X0 Alias region. Also, modify the DATA_region to reserve the SRAM X0 region to ensure data security, as shown in Figure 5.m_data_end and DATA_region to accommodate the SRAM X0 Alias.startup_MCXA156.s showing the vector table, where the first entry (DCD sfb(CSTACK)) points to the initial stack pointer for ROM validation.startup_MCXA156.s demonstrating the Reset_Handler. It includes instructions to mask interrupts, configure the Vector Table Offset Register (VTOR) and MSPLIM, enable remap by writing to 0xE000ED08 and 0x40091200, and set the Stack Pointer (MSP) to the desired value.4.2.3 Keil IDE
m_data_size to include the SRAM X0 Alias region, as shown in Figure 8.m_data_size to include the SRAM X0 Alias region.startup_MCXA156.S showing the vector table, where the first entry (.long Image$$ARM LIB STACK$$ZI$$Base) points to the initial stack pointer for ROM validation.startup_MCXA156.S demonstrating the Reset_Handler. It shows instructions to mask interrupts, configure VTOR and MSPLIM, enable remap by writing to 0xE000ED08 and 0x40091200, and set the Stack Pointer (MSP) to the actual stack region value.
5 Demo validation
This section provides a demo for validating SP register, read and write for boundary unaligned address, and DMA access to continuous SRAM address. Table 2 describes the hardware and software requirements. To set up this demo, perform the following steps: The first word in the vector table, the initial stack pointer, has a value of 0x2001f000, which is a valid value for ROM, as shown in Figure 11. Figure 11. Initial stack pointer value: A screenshot from a debugger showing register values. It highlights the The corresponding remap bits are enabled, and the value of the SP register is the end address of SRAM X0 Alias plus one, as shown in Figure 12. The above operation is completed before using the stack. Figure 12. Enable remap and configure the SP register: A screenshot from a debugger showing register values. It highlights the SYSCON remap register (e.g., Figure 13 shows the read and write test for boundary unaligned address as follows: The 32-bit *p_test address is not 4 bytes aligned and spans SRAM B2 and SRAM X0 Alias, the read and write works fine. Figure 13. Access to boundary unaligned address: A text output showing the results of a read/write test. It indicates that a 32-bit test point address This demo also tests the DMA access to this continuous SRAM address in Active and Low power mode, and it works fine. The destination buffer spans between RAM B2 and RAM X0 Alias, and DMA can transport normally as shown from the log information in Figure 14. In Power Down mode, the SYSCON register is in retention state, and can still use DMA partial wakeup to transport data on continuous SRAM address. Figure 14. DMA access to continuous SRAM address: A text output showing the results of a DMA access test in both Active and Power Down modes. It displays source and destination buffer addresses and data, confirming successful data transfer to and from the continuous SRAM address range, including during power-down states using DMA partial wakeup. Figure 15 shows that the MCU is in Power Down mode and uses DMA partial wakeup to transport data on continuous SRAM address. Figure 15. Power consumption measurement: A graph showing power consumption over time. It illustrates periods of "Power Down" and "DMA partial wakeup," with summary values for current consumption.5.1 Hardware and software requirements
Category Description Hardware Software IDEs supported: 5.2 Set up
5.3 SP register validation
sp (Stack Pointer) register with the value 0x2001f000, which is a valid value for ROM validation.CPU0_SBUS, DMA0, USB0 bits enabled) and the sp (Stack Pointer) register with the value 0x20020000, which is the end address of SRAM X0 Alias plus one.5.4 Read and write test for boundary unaligned address
0x2001DFFF (last byte of SRAM B2) was written with 0xFFFFFFFF, and the updated value read back was 0xffffffff, demonstrating that unaligned access across SRAM B2 and SRAM X0 Alias works correctly.5.5 DMA access to continuous SRAM address test
6 Summary
This application note introduces how to configure and use the SRAM X0 Alias to form a continuous SRAM address, and provides a demo to validate the feasibility of continuous SRAM address.
7 Note about the source code in the document
Example code shown in this document has the following copyright and BSD-3-Clause license:
Copyright 2024 NXP Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8 Revision history
Table 3 summarizes the revisions to this document.
| Document ID | Release date | Description |
|---|---|---|
| AN14377 v.1 | 26 July 2024 | Initial public release |
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