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Wistron Schematics Diagram. PCB Layout. Block Diagram - Schematic Diagram

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Document Document

5

4

3

2

1

D

D

Berry DG15 Discrete/UMA Schematics Document

Arrandale

Intel PCH

C

C

2009-10-12 REV : X00

B

DY :None Installed

B

UMA:UMA platform installed

DIS:DIS platform installed

Madisan:gDDR3 1GB platform installed

Colay :Manual modify BOM

A

<Core Design>

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

Cover Page

Size

Document Number

A3

Berry

Rev
X00

Date: W ednesday, October 14, 2009

Sheet 1

of

92

5

4

3

2

1

5

4

3

2

1.Madison-LP; 1GB

##OnMainBoard

Berry Block Diagram

(64Mx16b*8) 2.Park-XT;512MB
(64Mx16b*4)

(Discrete/UMA co-lay)

(1 and 2 co-lay)
D

VRAM
1GB/512MB 4
85,86,87,88

Project code : 91.4HH01.001

PCB P/N

: 48.4HH01.0SA

1

CPU DC/DC

ISL62883

47

INPUTS OUTPUTS

+PWR_SRC

+VCC_CORE

39,

SYSTEM DC/DC

TPS51218

49

INPUTS
+PWR_SRC

OUTPUTS
+1.05V_VTT

D 4

DDR3 800MHz

Intel CPU

Revision

: 09909-SA

SYSTEM DC/DC

RT8205B

46

INPUTS

OUTPUTS

Clock Generator
SLG8SP585
7

AMD Graphic
Madison-LP / Park-XT (Discrete only)

PCIe x 16 (Discrete only)

Arrandale

DDRIII 800/1066 Channel A DDRIII 800/1066 Channel B

DDRIII Slot 0

800/1066

18

DDRIII Slot 1

800/1066

19

+5V_ALW2

4

+3.3V_RTC_LDO

+PWR_SRC +5V_ALW

+3.3V_ALW

+15V_ALW

SYSTEM DC/DC

TPS51116

50

INPUTS

OUTPUTS

80,81,82,83,84

FDIx4x2

8,9,10,11,12,13,14

PCIE x 1 USB x 1

Mini-Card
802.11a/b/g

+1.5V_SUS

4

+PWR_SRC +0.75V_DDR_VTT

+V_DDR_REF

SYSTEM DC/DC

TPS51611

53

SPI LPC Bus
I/O Board Connector

C

Discreet/UMA Co-lay

(UMA only)

DMIx4

INPUTS

OUTPUTS C

PCIE x 1

10/100 NIC

RJ45

+PWR_SRC

+CPU_GFX_CORE

HDMI
57
LCD
54

HDMI Level 57 shifter
LVDS(Dual Channel)
RGB CRT

Intel PCH HM57

PCIE x 3

Realtek RTL8103T

SATAx1 / USB2.0x1

ESATA/USB Combo

CONN

4
VGA

RT8208B

89

INPUTS

OUTPUTS

+PWR_SRC

+VGA_CORE

TI CHARGER

5

CRT

14 USB 2.0/1.1 ports ETHERNET (10/100/1000Mb)

SATA x 1

BQ24745

45

PCIE x 1,USB x 1

Mini-Card

INPUTS OUTPUTS

SIM

WWAN

+DC_IN

+PWR_SRC

+PBATT

Left Side:

CRT Board
77

High Definition Audio SATA ports (6)

USB 2.0 x 4

26SYSTEM DC/DC

USB x 2

PCIE ports (8)

USB 2.0 x 1 76

Right Side: USB x 1

APL5930

51

4

INPUTS OUTPUTS

Bluetooth 73

USB2.0 x 4

LPC I/F

+3.3V_ALW

+1.8V_RUN

B

ACPI 1.1

+1.8V_RUN_VGA B

CAMERA 54

AZALIA

PCI/PCI BRIDGE
20,21,22,23,24,25,26,27,28

USB 2.0 x 1

CardReader
Realtek 78 RTS5138

SD/MMC+/MS/ MS Pro/xD

SYSTEM DC/DC

APL5930

90
3

2I6NPUTS

OUTPUTS

+1.5V_SUS +1.0V_RUN_VGA

Switches

INPUTS OUTPUTS

Internal Analog MIC

Azalia

SATA x 2

HP1 MIC IN
A
2CH SPEAKER

CODEC
IDT 92HD79B1
30

Flash ROM 4MB 62

LPC debug port
70

KBC

SPI

SMBus

NUVOTON

NPCE781BA0DX 37

HDD
59
ODD
59

<Core Design>

+1.5V_SUS +5V_ALW +3.3V_ALW

+1.5V_RUN +5V_RUN
+3.3V_RUN

PCB LAYER
L1:Top L2:VCC L3:Signal L4:Signal L5:GND L6:Bottom
A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Flash ROM 256kB 62

Touch PAD
68

Int. KB
68

Thermal
Main:G7922 Sec.EMC2102
2539

Fan
58

Title

Block Diagram

Size

Document Number

A3

Berry

Rev
X00

Date: W ednesday, October 14, 2009

Sheet 2

of

92

5

4

3

2

1

5

4

3

2

1

D
Adapter AO4407A
Battery

C
+15V_ALW

+3.3V_RTC_LDO +5V_ALW2

RT8208B

+VGA_CORE For Discrete

+PWR_SRC
Charger BQ24745 +PBATT

ISL62883
+VCC_CORE

TPS51218
+1.05V_VTT

RT8205B

+5V_ALW

+1.0V_RUN_VGA

APL5930KAI

D

TPS51116

TPS51611

+V_DDR_REF

+0.75V_DDR_VTT +1.5V_SUS

+CPU_GFX_CORE For UMA

AO4468

+3.3V_ALW

For Discrete

+1.5V_RUN +1.5V_RUN_CPU C

SI2301CDS

RT9715BGF

AO4468

RT9715BGF

AO4468

APL5930KAI

PA102FMG

+KBC_PWR

+5V_USB1 I/O Board USB Power

+5V_RUN

+5V_USB2 CRT Board USB Power

+3.3V_RUN

+3.3V_RUN_VGA For Discrete

+1.8V_RUN

+3.3V_LAN

RT9198-33PBG

APL5930KAI

SI3456BD

RTS5138

RTL8103T

B

B

+3.3V_CRT_LDO

+1.8V_RUN_VGA

+LCDVDD

+3.3V_RUN_CARD

+1.2V_LOM

For Discrete

A 5

Power Shape

Regulator

LDO

Switch

<Core Design>

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

Power Block Diagram

Size

Document Number

A3

Berry

Rev
X00

Date: Thursday, October 15, 2009

Sheet 3

of

92

4

3

2

1

A

B

C

D

E

PCH SMBus Block Diagram

+3.3V_ALW

+3.3V_RUN

KBC SMBus Block Diagram





+5V_RUN

+3.3V_RUN



SRN2K2J-1-GP



SRN2K2J-1-GP

1

SMBCLK SMBDATA

PCH_SMB_CLK
 PCH_SMB_DATA

+3.3V_ALW

PCH_SMBCLK
PCH_SMBDATA

DIMM
SCL
SDA

1

SMBus Address:A0

PSDAT1 TPDATA PSCLK1 TPCLK

SRN10KJ-5-GP



TPDATA TPCLK

TouchPad Conn.
TPDATA
TPCLK

1



2N7002SPT

+KBC_PWR

SRN2K2J-8-GP



SML1CLK SML1DATA

KBC_SCL1 KBC_SDA1

SML0CLK SML0_CLK SML0DATA SML0_DATA

To KBC
2N7002DW-1-GP
+3.3V_ALW


PCH_SMBCLK
PCH_SMBDATA

DIMM
SCL
SDA

2

SMBus Address:A4

SCL1 SDA1

BAT_SCL BAT_SDA

SRN4K7J-8-GP
SRN100J-3-GP PBAT_SMBCLK1 PBAT_SMBDAT1

Battery Conn.
CLK_SMB
DAT_SMB SMBus address:16

PCH

+3.3V_RUN

SRN2K2J-1-GP
UMA

SRN2K2J-1-GP
XDP

Clock

PCH_SMBCLK
PCH_SMBDATA

Generator
SCLK
SDATA

SMBus address:D2

KBC NPCE781BA0DX

BQ24745
SCL
SDA SMBus address:12
+3.3V_RUN

2

SDVO_CTRLCLK PCH_HDMI_CLK

Level

PCH_HDMI_CLK

SDVO_CTRLDATA PCH_HDMI_DATA

Shift

PCH_HDMI_DATA

Minicard

UMA
+3.3V_RUN


PCH_SMBCLK
PCH_SMBDATA

WLAN
SMB_CLK SMB_DATA



2

+3.3V_RUN


SRN4K7J-8-GP



THERM_SCL THERM_SDA

Thermal
SCL SMBus address:7A
SDA

L_DDC_CLK L_DDC_DATA

SRN2K2J-1-GP
UMA
LDDC_CLK_PCH LDDC_DATA_PCH

SRN0J-6-GP

PCH_SMBCLK PCH_SMBDATA

Minicard W-WAN
SMB_CLK
SMB_DATA

GPIO73/SCL2 GPIO74/SDA2

KBC_SCL1 KBC_SDA1

2N7002DW-1-GP

CRT_DDC_CLK CRT_DDC_DATA

PCH_CRT_DDCCLK PCH_CRT_DDCDATA

UMA
+3.3V_RUN_VGA


SRN2K2J-1-GP
DIS

3

DDC1CLK

DDC1DATA

LCD CONN

DDC2CLK DDC2DATA

VGA_CRT_DDCCLK VGA_CRT_DDCDATA

SRN0J-6-GP

VGA
+3.3V_RUN_VGA


SRN0J-6-GP

+3.3V_RUN

DIS



UMA

SRN2K2J-1-GP

+3.3V_RUN

UMA

+5V_RUN UMA


2N7002DW-1-GP

+5V_RUN

SRN2K2J-1-GP

CRT_DDCCLK_CON CRT_DDCDATA_CON

CRT CONN

+5V_RUN

SRN2K2J-1-GP

SRN2K2J-1-GP

4

DIS

IFPC_AUX_I2CW_SCL IFPC_AUX_I2C_SDA#

GPU_HDMI_CLK GPU_HDMI_DATA

TSCBTD3305CPWR

HDMI CONN

A

B

C

D

3

4

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

SMBUS Block Diagram

Size A2

Document Number
Berry

Rev
X00

Date: Wednesday, October 14, 2009 E

Sheet 4

of

92

A

B

C

D

E

Thermal Block Diagram
1

Audio Block Diagram
1

DP1 EMC2102_DP1

SC470P50V3JN-2GP

MMBT3904-3-GP

2

DN1 EMC2102_DN1

Thermal

Place near CPU PWM CORE

G7922R61U
DP2

VGA_THERMDA

DN2 VGA_THERMDC

THRMDA
VGA
THRMDC
Place near GPU(DISCRETE only).

MMBT3904-3-GP
3
System Sensor(UMA only)

DP3 EMC2102_DP3 DN3 EMC2102_DN3

SC470P50V3JN-2GP

MMBT3904-3-GP

Put under CPU(T8 HW shutdown)

4

SPKR_PORT_D_LSPKR_PORT_D_R+
Codec 92HD79B1
HP1_PORT_B_L HP1_PORT_B_R
HP0_PORT_A_L HP0_PORT_A_R VREFOUT_A_OR_F
DMIC_CLK/GPIO1 DMIC0/GPIO2
PORTC_L PORTC_R VREFOUT_C

A

B

C

D

SPEAKER

HP

OUT

2

MIC IN

3

Analog MIC

<Core Design>

4

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Thermal/Audio Block Diagram

Size

Document Number

Custom

Berry

Date: Wednesday, October 14, 2009

Sheet 5

of

E

Rev
X00
92

A

B

C

D

E

PCH Strapping

Calpella Schematic Checklist Rev.0_7

Name

Schematics Notes

SPKR

Reboot option at power-up

Default Mode: Internal weak Pull-down.

No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-k

4

- 10-k weak pull-up resistor.

INIT3_3V#

Weak internal pull-down. Do not pull high.

GNT3#/ GPIO55

Default Mode: Internal pull-up.
Low (0) = Top Block Swap Mode (Connect to ground with 4.7-k weak pull-down resistor).

INTVRMEN GNT0#, GNT1#/GPIO51
GNT2#/ GPIO53

High (1) = Integrated VRM is enabled Low (0) = Integrated VRM is disabled
Default (SPI): Left both GNT0# and GNT1# floating. No pull up required.
Boot from PCI: Connect GNT1# to ground with 1-k pull-down resistor. Leave GNT0# Floating.
Boot from LPC: Connect both GNT0# and GNT1# to ground with 1-k pull-down resistor.
Default - Internal pull-up. Low (0)= Configures DMI for ESI compatible operation (for servers only. Not for mobile/desktops).

GPIO33

Default: Do not pull low.

Disable ME in Manufacturing Mode: Connect to ground with 1-k

3

pull-down resistor.

SPI_MOSI

Enable iTPM: Connect to Vcc3_3 with 8.2-k weak pull-up resistor. Disable iTPM: Left floating, no pull-down required.

NV_ALE

Enable Danbury: Connect to Vcc3_3 with 8.2-k weak pull-up resistor.
Disable Danbury: Connect to ground with 4.7-k weak pull-down resistor.

NC_CLE

Weak internal pull-up. Do not pull low.

HAD_DOCK_EN# Low (0): Flash Descriptor Security will be overridden.

/GPIO[33]

High (1) : Flash Descriptor Security will be in effect.

HDA_SDO

Weak internal pull-down. Do not pull high.

HDA_SYNC

Weak internal pull-down. Do not pull high.

GPIO15

Weak internal pull-down. Do not pull high.

GPIO8

Weak internal pull-up. Do not pull low.

GPIO27

Default = Do not connect (floating)

High(1) = Enables the internal VccVRM to have a clean supply for

analog rails. No need to use on-board filter circuit.

Low (0) = Disables the VccVRM. Need to use on-board filter

2

circuits for analog rails.

Processor Strapping

Calpella Schematic Checklist Rev.0_7

Pin Name Strap Description Configuration (Default value for each bit is 1 unless specified otherwise)

Default Value

CFG[4]

Embedded

1: Disabled - No Physical Display Port attached to 1

DisplayPort Presence

Embedded DisplayPort. 0: Enabled - An external Display Port device is

4

connected to the Embedded Display Port.

CFG[3]

PCI-Express Static 1: Normal Operation.

1

Lane Reversal

0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

CFG[0] CFG[7]

PCI-Express Configuration Select
Reserved Temporarily used for early Clarksfield samples.

1: Single PCI-Express Graphics

1

0: Bifurcation enabled

Clarksfield (only for early samples pre-ES1) -

0

Connect to GND with 3.01K Ohm/5% resistor

Note: Only temporary for early CFD samples (rPGA/BGA) [For details please refer to the WW33 MoW and sighting report]. For a common motherboard design (for AUB and CFD), the pull-down resistor should be used. Does not impact AUB functionality.

3

2

PCIE Routing

USB Table

SATA Table

USB

SATA

LANE1 LANE2 LANE3 LANE4 LANE5

RESERVED MiniCard WLAN LAN W-WAN RESERVED

Pair 0 1 2 3 4 5 6

Device USB2 (CRT Board) USB3 (CRT Board) WLAN (I/O Board) RESERVED CARD READER BLUETOOTH
HM55 no support

Pair

Device

0 HDD 1 ODD 2 HM55 no support 3 HM55 no support 4 ESATA 5 RESERVED

LANE6 RESERVED

7

HM55 no support

1

LANE7 H55/HM55 no support

8 USB1 (I/O Board) 9 USB0 (I/O Board ESATA)

LANE8 H55/HM55 no support

10 RESERVED 11 W-WAN (I/O Board)

12 RESERVED

13 CAMERA

<Core Design>

1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

Table of Content

Size

Document Number

A3

Berry

Date: W ednesday, October 14, 2009

Sheet 6

of

Rev
X00
92

5

4

SSID = CLOCK

+3.3V_RUN

D

R701

1

2

+3.3V_RUN_SL585

1

C702 0R3J-0-U-GP

2

DY

1

DY C701

1

C703

1

C704

1

C705

1

1

C706

C707

3

2

+1.05V_VTT

R702

1

2

C708
DY

1

0R3J-0-U-GP

1

+1.05V_RUN_SL585_IO

1

1

C709

C710

C711

1 D

2

2

2

2

2

2

2

2

2

2

SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SC10U10V5ZY-1GP
SC1U10V2KX-1GP
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SC10U10V5ZY-1GP SC1U10V2KX-1GP

+3.3V_RUN_SL585

+1.05V_RUN_SL585_IO

+3.3V_RUN

R703

1

2

CPU_STOP#

C

2K2R2J-2-GP

C

U701

VDD_CPU 24 VDD_SRC 17 VDD_REF 29 VDD_DOT 1
VDD_27 5 VDD_SRC_IO 15 VDD_CPU_IO 18

SRN0J-6-GP

CLK_DREF# CLK_DREF

4 3

DOT_96# DOT_96

CLKIN_DMI# CLKIN_DMI
CLK_PCIE_SATA# CLK_PCIE_SATA

2 1
RN702

3

CLKIN_DMI#_C

4

CLKIN_DMI_C

SRN0J-6-GP

14 13

SRC_2# SRC_2

2 1

3 CLK_PCIE_SATA#_C 4 CLK_PCIE_SATA_C

11 10

SRC_1/SATA# SRC_1/SATA

CLK_CPU_BCLK# CLK_CPU_BCLK

RN703

22 23

CPU_0# CPU_0

19 20

CPU_1# CPU_1

27MHZ 27MHZ_SS

6 7

CLK_VGA_27M_NSS_R CLK_VGA_27M_SS_R

4 DIS 1 RN701

3

2 SRN33J-5-GP-U

CPU_STOP# CKPWRGD/PD# REF_0/CPU_SEL

16 25 30

XTAL_IN XTAL_OUT

28 27

SDA SCL

31 32

CPU_STOP# CK_PW RGD FSC
CLK_XTAL_IN CLK_XTAL_OUT

R704

2

1

33R2J-2-GP

CLK_PCH_14M

1

DY EC703

2

SC4D7P50V2CN-1GP

2

CLK_VGA_27M_SS

CLK_VGA_27M_NSS

1

1

DY EC701 SC4D7P50V2CN-1GP

DY EC702 SC4D7P50V2CN-1GP

2

33 GND 26 VSS_REF 21 VSS_CPU 12 VSS_SRC
2 VSS_DOT 8 VSS_27 9 VSS_SATA

PCH_SMBDATA PCH_SMBCLK

+3.3V_RUN_SL585

2

B

SLG8SP585VTR-GP

B

R705 10KR2J-3-GP

1

+1.05V_VTT

CK_PW RGD

FSC

0

1

133MHz

SPEED

100MHz

(Default)

CLK_XTAL_IN

X701

1

2

C712 SC12P50V2JN-3GP

1

X-14D31818M-37GP
82.30005.901

1

CLK_XTAL_OUT
C713 SC12P50V2JN-3GP

1

R706
DY 4K7R2J-2-GP
FSC

2

2

2

VR_CLKEN#

G

S

. . ...

Q701 2N7002E-1-GP

D

2

R707 10KR2J-3-GP

1

A

<Core Design>

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

Clock Generator SLG8SP585

Size

Document Number

Rev

Berry

X00

Date: Thursday, October 22, 2009

Sheet 7

of

92

5

4

3

2

1

SSID = CP5U
D C B A

4

3

2

1

DMI_PTX_CRXN0 DMI_PTX_CRXN1 DMI_PTX_CRXN2 DMI_PTX_CRXN3
DMI_PTX_CRXP0 DMI_PTX_CRXP1 DMI_PTX_CRXP2 DMI_PTX_CRXP3
DMI_CTX_PRXN0 DMI_CTX_PRXN1 DMI_CTX_PRXN2 DMI_CTX_PRXN3
DMI_CTX_PRXP0 DMI_CTX_PRXP1 DMI_CTX_PRXP2 DMI_CTX_PRXP3
FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7
FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7
FDI_FSYNC0 FDI_FSYNC1
FDI_INT
FDI_LSYNC0 FDI_LSYNC1
R804 1KR2J-1-GP
DIS

2

1

1

8

D

2

3

4

CPU1A

A24 C23 B22 A21

DMI_RX#0 DMI_RX#1 DMI_RX#2 DMI_RX#3

B24 D23 B23 A22

DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3

D24 G24 F23 H23

DMI_TX#0 DMI_TX#1 DMI_TX#2 DMI_TX#3

D25 F24 E23 G23

DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3

E22 D21 D19 D18 G21 E19 F21 G18

FDI_TX#0 FDI_TX#1 FDI_TX#2 FDI_TX#3 FDI_TX#4 FDI_TX#5 FDI_TX#6 FDI_TX#7

D22 C21 D20 C18 G22 E20 F20 G19

FDI_TX0 FDI_TX1 FDI_TX2 FDI_TX3 FDI_TX4 FDI_TX5 FDI_TX6 FDI_TX7

F17 E17

FDI_FSYNC0 FDI_FSYNC1

C17 FDI_INT

F18 D17

FDI_LSYNC0 FDI_LSYNC1

5

6

7

DIS RN801
SRN1KJ-4-GP

CLARKSFIELD

PCI EXPRESS -- GRAPHICS

DMI

Intel(R) FDI

1 OF 9

PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO
PEG_RBIAS

B26 PEG_IRCOMP_R

A26

B27

A25

EXP_RBIAS

PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8 PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15

K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31

PEG_RXN15 PEG_RXN14 PEG_RXN13 PEG_RXN12 PEG_RXN11 PEG_RXN10 PEG_RXN9 PEG_RXN8 PEG_RXN7 PEG_RXN6 PEG_RXN5 PEG_RXN4 PEG_RXN3 PEG_RXN2 PEG_RXN1 PEG_RXN0

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8 PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30

PEG_RXP15 PEG_RXP14 PEG_RXP13 PEG_RXP12 PEG_RXP11 PEG_RXP10 PEG_RXP9 PEG_RXP8 PEG_RXP7 PEG_RXP6 PEG_RXP5 PEG_RXP4 PEG_RXP3 PEG_RXP2 PEG_RXP1 PEG_RXP0

PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9 PEG_TX#10 PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15

L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26

PEG_C_TXN15 PEG_C_TXN14 PEG_C_TXN13 PEG_C_TXN12 PEG_C_TXN11 PEG_C_TXN10 PEG_C_TXN9 PEG_C_TXN8 PEG_C_TXN7 PEG_C_TXN6 PEG_C_TXN5 PEG_C_TXN4 PEG_C_TXN3 PEG_C_TXN2 PEG_C_TXN1 PEG_C_TXN0

PEG_TX0 PEG_TX1 PEG_TX2 PEG_TX3 PEG_TX4 PEG_TX5 PEG_TX6 PEG_TX7 PEG_TX8 PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25

PEG_C_TXP15 PEG_C_TXP14 PEG_C_TXP13 PEG_C_TXP12 PEG_C_TXP11 PEG_C_TXP10 PEG_C_TXP9 PEG_C_TXP8 PEG_C_TXP7 PEG_C_TXP6 PEG_C_TXP5 PEG_C_TXP4 PEG_C_TXP3 PEG_C_TXP2 PEG_C_TXP1 PEG_C_TXP0

CLARKU1NF
62.10055.341 SEC. 62.10053.561

R801 1 R802 1

2 49D9R2F-GP 2 750R2F-GP

PEG_RXN[0..15]

PEG_RXN[0..15]

PEG_RXP[0..15]

PEG_RXP[0..15]

C

PEG_TXN[0..15]

PEG_TXN[0..15]

DIS1

2 C816 SCD1U16V2KX-3GP

PEG_TXN15

DIS1

2 C815 SCD1U16V2KX-3GP

PEG_TXN14

DIS1

2 C814 SCD1U16V2KX-3GP

PEG_TXN13

DIS1

2 C813 SCD1U16V2KX-3GP

PEG_TXN12

DIS1

2 C812 SCD1U16V2KX-3GP

PEG_TXN11

DIS1

2 C811 SCD1U16V2KX-3GP

PEG_TXN10

DIS1

2 C810 SCD1U16V2KX-3GP

PEG_TXN9

DIS1

2 C809 SCD1U16V2KX-3GP

PEG_TXN8

DIS1

2 C808 SCD1U16V2KX-3GP

PEG_TXN7

DIS1

2 C807 SCD1U16V2KX-3GP

PEG_TXN6

DIS1

2 C806 SCD1U16V2KX-3GP

PEG_TXN5

DIS1

2 C805 SCD1U16V2KX-3GP

PEG_TXN4

DIS1

2 C804 SCD1U16V2KX-3GP

PEG_TXN3

DIS1

2 C803 SCD1U16V2KX-3GP

PEG_TXN2

DIS1 DIS1

2 C802 SCD1U16V2KX-3GP 2 C801 SCD1U16V2KX-3GP

PEG_TXN1 PEG_TXN0

B

PEG_TXP[0..15]

DIS1

2 C832 SCD1U16V2KX-3GP

PEG_TXP15

PEG_TXP[0..15]

DIS1

2 C831 SCD1U16V2KX-3GP

PEG_TXP14

DIS1

2 C830 SCD1U16V2KX-3GP

PEG_TXP13

DIS1

2 C829 SCD1U16V2KX-3GP

PEG_TXP12

DIS1

2 C828 SCD1U16V2KX-3GP

PEG_TXP11

DIS1

2 C827 SCD1U16V2KX-3GP

PEG_TXP10

DIS1

2 C826 SCD1U16V2KX-3GP

PEG_TXP9

DIS1

2 C825 SCD1U16V2KX-3GP

PEG_TXP8

DIS1

2 C824 SCD1U16V2KX-3GP

PEG_TXP7

DIS1

2 C823 SCD1U16V2KX-3GP

PEG_TXP6

DIS1

2 C822 SCD1U16V2KX-3GP

PEG_TXP5

DIS1

2 C821 SCD1U16V2KX-3GP

PEG_TXP4

DIS1

2 C820 SCD1U16V2KX-3GP

PEG_TXP3

DIS1

2 C819 SCD1U16V2KX-3GP

PEG_TXP2

DIS1

2 C818 SCD1U16V2KX-3GP

PEG_TXP1

DIS1

2 C817 SCD1U16V2KX-3GP

PEG_TXP0

<Core Design>

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (PCIE/DMI/FDI)

Size

Document Number

Berry

Date: Thursday, October 22, 2009

Sheet 8

of

Rev
X00
92

5

+1.05V_VTT

Processor Pullups

R901 1

2 49D9R2F-GP H_CATERR#

R907 1

2 68R2-GP

H_PROCHOT#

D

DY R906 1

2 68R2-GP

H_CPURST#

H_PECI

H_THERMTRIP#

H_PM_SYNC
C
H_PW RGD PM_DRAM_PW RGD
H_VTTPW RGD

4
Processor Compensation Signals

1 R902
1 R903
1 R904
1 R905
TPAD14-GP TP901

2

H_COMP3

20R2F-GP

2 20R2F-GP

H_COMP2

2

H_COMP1

49D9R2F-GP

2

H_COMP0

49D9R2F-GP

1

SKTOCC#_R

H_CATERR#

H_PROCHOT#

H_CPURST#

R910

1

2

VCCPW RGOOD

0R2J-2-GP

R912

1

2 VDDPWRGOOD_R

0R2J-2-GP

H_PW RGD_XDP

SSID = CP3U

2

CPU1B AT23 COMP3 AT24 COMP2 G16 COMP1 AT26 COMP0 AH24 SKTOCC# AK14 CATERR#
AT15 PECI
AN26 PROCHOT#
AK15 THERMTRIP#
AP26 RESET_OBS# AL15 PM_SYNC AN14 VCCPWRGOOD_1 AN27 VCCPWRGOOD_0 AK13 SM_DRAMPWROK AM15 VTTPWRGOOD AM26 TAPPWRGOOD

CLARKSFIELD

JTAG & BPM

DDR3 MISC

CLOCKS

MISC THERMAL

2 OF 9

RN901

BCLK BCLK#

A16 BCLK_CPU_C_P 1 B16 BCLK_CPU_C_N 2

4 3

BCLK_ITP BCLK_ITP#
PEG_CLK PEG_CLK#

AR30 AT30
E16 D16

BCLK_ITP_P SRN0J-6-GP

BCLK_ITP_N

RN902

CLK_EXP_C_P 1

4

CLK_EXP_C_N 2

3

DPLL_REF_SSCLK DPLL_REF_SSCLK#

A18 A17

SRN0J-6-GP

BCLK_CPU_P BCLK_CPU_N
CLK_EXP_P CLK_EXP_N

SM_DRAMRST#
SM_RCOMP0 SM_RCOMP1 SM_RCOMP2
PM_EXT_TS#0 PM_EXT_TS#1

F6
AL1 AM1 AN1
AN15 AP15

PRDY# PREQ#
TCK TMS TRST#
TDI TDO TDI_M TDO_M
DBR#

AT28 AP27
AN28 AP28 AT27
AT29 AR27 AR29 AP29
AN25

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23

SM_DRAMRST#
SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2
PM_EXTTS#0_C PM_EXTTS#1_C

PM_EXTTS#0_C

RN903

4

1

3

2

+1.05V_VTT

SRN10KJ-5-GP

1

4

2

3

RN904 SRN0J-6-GP

PM_EXTTS#0 PM_EXTTS#1

XDP_PRDY# XDP_PREQ#

XDP_TCLK XDP_TMS XDP_TRST#

XDP_TDI_R XDP_TDO_R XDP_TDI_M XDP_TDO_M
H_DBR#_R

R911

1

2 XDP_DBRESET#

XDP_OBS0 XDP_OBS1 XDP_OBS2 XDP_OBS3 XDP_OBS4 XDP_OBS5 XDP_OBS6 XDP_OBS7

0R2J-2-GP

1

+1.5V_RUN_CPU
R915
DY 1KR2J-1-GP

1
S3_RST_GATE#

+1.5V_SUS

1

R908

Q901

1KR2J-1-GP

BSS138-7F-GP

D

G

2

S

D

DDR3_DRAMRST#

1 R909

2 0R2J-2-GP

DDR3 Compensation Signals

SM_RCOMP_0 R913 1

2 100R2F-L1-GP-U

SM_RCOMP_1 R914 1

2 24D9R2F-L-GP

SM_RCOMP_2 R916 1

2 130R2F-1-GP

XDP_TMS XDP_TDI_R XDP_PREQ#
XDP_TCLK

+1.05V_VTT

C

1 R919
1 R920
1 R922

DY 2 51R2J-2-GP
DY 2 51R2J-2-GP
DY 2 51R2J-2-GP

DY 1
R923

2 51R2J-2-GP

PWR MANAGEMENT

2

For EMI
XDP_RST#_R VCCPW RGOOD VDDPW RGOOD_R H_VTTPW RGD PLT_RST#_R XDP_DBRESET#
EC906

EC905

PLT_RST#

1

2

R917 1K54R2F-GP

EC904 EC903

EC902

EC901

2

1

PLT_RST#_R AL14 RSTIN#

R918 750R2F-GP

CLARKU1NF

U901

+3.3V_RUN

1

SM_DRAMRST#
R921
DY 100KR2J-1-GP

2

2

2

2

2

2

2

1

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

1

1

1

DY

DY

DY DY

DY

DY

1

1

1

1.5CPU_1.05VTT_PW RGD

1 2 3

A B GND

VCC Y

5 4

VTT_PW RGD_C

B

NL17SZ08DFT2G-GP

DY R927

B

XDP1

1K54R2F-GP

XDP_TDI_R

DY 1
R928

2 0R2J-2-GP

XDP_TDI

NP1

XDP_TRST#

12

+1.5V_SUS

+1.5V_RUN_CPU

61

1

2

VDDPW RGOOD_R

XDP_TDO_M

DY 1
R929

2 0R2J-2-GP

XDP_TDO

1

1

62

1

XDP_PREQ#

3

4

1

XDP_PRDY#

5

6

DY R924
1K1R2F-GP

R925 1K1R2F-GP

XDP_OBS0

7 9

8 10

For S3 Reduction

R930
DY 750R2F-GP

R931 0R2J-2-GP

R932

2

51R2J-2-GP

2

2

XDP_OBS1

11

12

13

14

XDP_TDI_M

DY 1
R933

2 0R2J-2-GP

2

2

XDP_OBS2

15

16

VDDPW RGOOD_R

XDP_OBS3

17

18

XDP_TDO_R

1

2

19

20

R934

0R2J-2-GP

1

21

22

R926 3KR2F-GP

XDP_OBS4 XDP_OBS5

23

24

25

26

27 29

DY

28 30

+1.05V_VTT

Scan Chain (Default) CPU Only

Stuff --> R928, R931, R934 No Stuff --> R929, R933 Stuff --> R928, R929

JTAG MAPPING

2

31

32

1

+1.05V_VTT

XDP_OBS6

33

34

XDP_OBS7

35

36

37

38

C901
DY SCD1U16V2KX-3GP

1

2

H_PW RGD PM_PW RBTN#_R

R935 R937

1 1

DDYY

2

H_CPUPW RGD_XDP

2 1KR2J-1-GP PM_PW RBTN#_XDP

0R2J-2-GP

39 41 43

40 42 44

BCLK_ITP_P BCLK_ITP_N

R936 51R2J-2-GP

GMCH Only

No Stuff --> R931, R934, R933 Stuff --> R933, R934 No Stuff --> R928, R929, R931

A

DY H_PW RGD_XDP

1

R938

2

PCIE_CLK_XDP_P

0R2J-2-GP

45 47

46 48

DY XDP_RST#_R 1 R939

2H_CPURST# 1KR2J-1-GP

2

XDP_DBRESET#

<Core Design>

A

49

50

1

2

C902
DY SCD1U16V2KX-3GP

SML0_DATA SML0_CLK

51

52

53

54

55

56

XDP_TCLK

57

58

XDP_TRST# XDP_TDI XDP_TMS

XDP_TDO

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

59

60

63

Title

64

NP2

XDP_RST#_R

DY 1
R940

2 0R2J-2-GP

PLT_RST#

CPU (THERMAL/CLOCK/PM )

Size

Document Number

Rev

STC-CONN60A-GP-U1

Berry

X00

Date: Thursday, October 22, 2009

Sheet 9

of

92

5
SSID = CPU
CPU1C

M_A_DQ[63..0] D
C
B

M_A_DQ[63..0]
M_A_BS0 M_A_BS1 M_A_BS2 M_A_CAS# M_A_RAS# M_A_W E#

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

A10 C10
C7 A7 B10 D10 E10 A8 D8 F10 E6 F7 E9 B7 E7 C6 H10 G8 K7 J8 G7 G10 J7 J10 L7 M6 M8 L9 L6 K8 N8 P9 AH5 AF5 AK6 AK7 AF6 AG5 AJ7 AJ6 AJ10 AJ9 AL10 AK12 AK8 AL7 AK11 AL8 AN8 AM10 AR11 AL11 AM9 AN9 AT11 AP12 AM12 AN12 AM13 AT14 AT12 AL13 AR14 AP14

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

AC3 AB2
U7

SA_BS0 SA_BS1 SA_BS2

AE1 AB3 AE9

SA_CAS# SA_RAS# SA_WE#

CLARKU1NF A

5

DDR SYSTEM MEMORY A

CLARKSFIELD

4 3 OF 9

SA_CK0 SA_CK#0 SA_CKE0

AA6 AA7 P7

SA_CK1 SA_CK#1 SA_CKE1

Y6 Y5 P6

SA_CS#0 SA_CS#1

AE2 AE8

SA_ODT0 SA_ODT1

AD8 AF9

SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7

B9 D7 H7 M7 AG6 AM7 AN10 AN13

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7

C9 F8 J9 N9 AH7 AK9 AP11 AT13

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

C8 F9 H9 M9 AH8 AK10 AN11 AR13

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

3

2

CPU1D

M_CLK_DDR0 M_CLK_DDR#0 M_CKE0
M_CLK_DDR1 M_CLK_DDR#1 M_CKE1
M_CS#0 M_CS#1
M_ODT0 M_ODT1

M_B_DQ[63..0]

M_A_DM[7..0] M_A_DQS#[7..0]
M_A_DQS[7..0] M_A_A[15..0]

M_B_DQ[63..0]

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3 G4 H6 G2 J6 J3 G1 G5 J2 J1 J5 K2 L3 M1 K5 K4 M4 N5 AF3 AG1 AJ3 AK1 AG4 AG3 AJ4 AH4 AK3 AK4 AM6 AN2 AK5 AK2 AM4 AM3 AP3 AN5 AT4 AN6 AN4 AN3 AT5 AT6 AN7 AP6 AP8 AT9 AT7 AP9 AR10 AT10

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

M_B_BS0 M_B_BS1 M_B_BS2
M_B_CAS# M_B_RAS# M_B_W E#

AB1 W5 R7

SB_BS0 SB_BS1 SB_BS2

AC5 Y7
AC6

SB_CAS# SB_RAS# SB_WE#

CLARKU1NF

4

3

2

DDR SYSTEM MEMORY - B

CLARKSFIELD

1 4 OF 9

SB_CK0 SB_CK#0 SB_CKE0

W8 W9 M3

SB_CK1 SB_CK#1 SB_CKE1

V7 V6 M2

SB_CS#0 SB_CS#1

AB8 AD6

SB_ODT0 SB_ODT1

AC7 AD1

SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7

D4 E1 H3 K1 AH1 AL2 AR4 AT8

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7

D5 F4 J4 L4 AH2 AL4 AR5 AR8

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_CLK_DDR2 M_CLK_DDR#2 M_CKE2

M_CLK_DDR3

M_CLK_DDR#3

D

M_CKE3

M_CS#2 M_CS#3
M_ODT2 M_ODT3

M_B_DM[7..0] M_B_DQS#[7..0]

M_B_DQS[7..0]

M_B_A[15..0]

C

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7

C5 E3 H4 M5 AG2 AL5 AP5 AR7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

B

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

<Core Design>

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (DDR)

Size

Document Number

Berry

Date: Thursday, October 22, 2009

Sheet 10

of

1

Rev
X00
92

5

4

SSID = CPU

D

CFG0

1

R1101
DY 3KR2F-GP

PCI-Express Configuration Select

CFG0

1:Single PEG 0:Bifurcation enabled

2

CFG3

1

CFG3 - PCI-Express Static Lane Reversal

DIS

R1104 3KR2J-2-GP

1 :Normal Operation

CFG3 0 :Lane Numbers Reversed

C

2

15 -> 0, 14 -> 1, ...

CFG4

1

R1105
DY 3KR2F-GP

2

CFG4 - Display Port Presence

CFG4

1:Disabled; No Physical Display Port attached to Embedded Display Port 0:Enabled; An external Display Port device is connected to the Embedded Display Port

CFG7

CFG7(Reserved) - Temporarily used for early

1

B

R1106

Clarksfield samples.

DY 3KR2F-GP

CFG7 Clarksfield (only for early samples pre-ES1) -

2

Connect to GND with 3.01K Ohm/5% resistor.

Note: Only temporary for early CFD sample (rPGA/BGA) [For details please refer to the WW33 MoW and sighting report]. For a common M/B design (for AUB and CFD), the pull-down resistor shouble be used. Does not impact AUB functionality.

A

5

4

3

2

1

CLARKSFIELD

CPU1E

5 OF 9

RSVD#AJ13 RSVD#AJ12

AJ13 AJ12

D

AP25 AL25 AL24 AL22 AJ33 AG9 M27
L28 J17 H17 G25 G17 E31 E30

RSVD#AP25 RSVD#AL25 RSVD#AL24 RSVD#AL22 RSVD#AJ33 RSVD#AG9 RSVD#M27 RSVD#L28 SA_DIMM_VREF SB_DIMM_VREF RSVD#G25 RSVD#G17 RSVD#E31 RSVD#E30

RSVD#AH25 RSVD#AK26
RSVD#AL26 RSVD_NCTF_37
RSVD#AJ26 RSVD#AJ27

AH25 AK26
AL26 AR2
AJ26 AJ27

TPAD14-GP TP1101 TPAD14-GP TP1102 TPAD14-GP TP1103

TPAD14-GP TP1104 TPAD14-GP TP1105

TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP

TP1106 TP1107 TP1108 TP1109 TP1110 TP1111 TP1112 TP1113 TP1114 TP1115

CFG0
1 CFG1 1 CFG2 1 CFG3
CFG4
1 CFG5 1 CFG6
CFG7
1 CFG8 1 CFG9 1 CFG10 1 CFG11 1 CFG12 1 CFG13 1 CFG14 1 CFG15 1 CFG16 1 CFG17

AM30 AM28 AP31 AL32 AL30 AM31 AN29 AM32 AK32 AK31 AK28 AJ28 AN30 AN32 AJ32 AJ29 AJ30 AK30
H16

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 RSVD_TP_86

RESERVED

RSVD#AL28 RSVD#AL29 RSVD#AP30 RSVD#AP32 RSVD#AL27 RSVD#AT31 RSVD#AT32 RSVD#AP33 RSVD#AR33

AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33

RSVD#AR32 AR32

RSVD_TP#E15 RSVD_TP#F15
KEY RSVD#D15 RSVD#C15 RSVD#AJ15 RSVD#AH15

E15 F15 A2 D15 C15 AJ15 AH15

C

B19 A19

RSVD#B19 RSVD#A19

A20 B20

RSVD#A20 RSVD#B20

U9 T9

RSVD#U9 RSVD#T9

AC9 AB9

RSVD#AC9 RSVD#AB9

SA_CK2 SA_CK#2 SA_CKE2 SA_CS#2 SA_ODT2
SA_CK3 SA_CK#3 SA_CKE3 SA_CS#3 SA_ODT3

AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3

J29 J28

RSVD#J29 RSVD#J28

SB_CK2 SB_CK#2 SB_CKE2 SB_CS#2 SB_ODT2
SB_CK3 SB_CK#3 SB_CKE3 SB_CS#3 SB_ODT3

V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9

VSS (AP34) can be left NC is CRB implementation; EDS/DG recommendation to GND.

B

CLARKU1NF

VSS

AP34

RSVD_VSS 1

2

R1107 0R2J-2-GP

A <Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (RESERVED)

Size

Document Number

Rev

Berry

X00

Date: Wednesday, October 14, 2009

Sheet 11

of

92

3

2

1

5
SSID = CPU

4 CPU1F

+VCC_CORE
PROCESSOR CORE POWER

+VCC_CORE

D

1

C1201

1

C1205

1

C1206

C1207

1

DY

1

C1215

C1208

1

DY

48A

2

2

2

2

2

2

SC10U10V5KX-2GP SC10U10V5KX-2GP SC10U10V5KX-2GP SC10U10V5KX-2GP SC10U10V5KX-2GP SC10U10V5KX-2GP

SC10U10V5KX-2GP

SC10U10V5KX-2GP

SC10U10V5KX-2GP

SC10U10V5KX-2GP

SC22U6D3V5MX-2GP SC10U10V5KX-2GP

C1219 C1220

C1221

1

1

1

2

DY

2

2

DY

2

1

C1222

2

1

2

C1223

C1224

1

DY

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5MX-3GP

SC10U10V5KX-2GP SC10U10V5KX-2GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

1

1

C1226 C1225
DY

1

C1228

C1229

1

1

C1227

DY DY

1

C1230

C1231

C1232

1

1

DY DY

DY

2

2

2

2

2

2

2

2

C

1

C1235
DY

1

C1236

C1237

1

DY

1

C1238

C1239

1

DY

1

C1240 C1241

1

1

C1242

2

2

2

2

2

2

2

2

SC10U10V5KX-2GP

SC22U6D3V5MX-2GP SC10U10V5KX-2GP

SC10U6D3V5MX-3GP

SC10U10V5KX-2GP

SC10U10V5KX-2GP

1

C1243
DY

SC10U10V5KX-2GP
SC10U10V5KX-2GP SC22U6D3V5MX-2GP

2

B

AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26
Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

A CLARKU1NF

5

4

POWER
CPU VIDS

CLARKSFIELD

CPU CORE SUPPLY

SENSE LINES

1.1V RAIL POWER

3

2

1

6 OF 9

VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0

AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0

AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15

+1.05V_VTT

1

1

1

1

1

1

1

1

C1209
DYC1202

1

C1210

C1211

DY

C1212

C1203

C1204

C1213

C1214

DY DY DY

2

2

2

2

2

2

2

2

2

D

SC10U10V5ZY-1GP SC10U10V5ZY-1GP SC10U10V5ZY-1GP SC10U10V5KX-2GP SC10U10V5KX-2GP SC10U6D3V5KX-1GP SC10U10V5ZY-1GP SC10U10V5KX-2GP SC10U10V5ZY-1GP

1

2

2

+1.05V_VTT

C1216

1

C1217

C1218

1

DY

The decoupling capacitors, filter recommendations and sense resistors on the CPU/PCH Rails are specific to the CRB Implementation. Customers need to follow the recommendations in the Calpella Platform Design Guide.

2

SC10U6D3V5MX-3GP SC10U10V5KX-2GP SC10U10V5KX-2GP

+1.05V_VTT

C1233

C1234

1

C

2

DY

1

2

SC10U6D3V5MX-3GP SC10U10V5KX-2GP

Please note that the VTT Rail Values are Auburndale VTT=1.05V; Clarksfield VTT=1.1V

PSI# AN33

PSI#

H_VID[6..0]

VID VID VID VID VID VID VID PROC_DPRSLPVR

AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34

H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6

PM_DPRSLPVR

B

VTT_SELECT G15

H_VTTVID1

1

TP1201 TPAD14-GP

H_VTTVID1 = Low, 1.1V H_VTTVID1 = High, 1.05V

+VCC_CORE

1

ISENSE AN35

IMVP_IMON

VCC_SENSE VSS_SENSE

AJ34 AJ35

VTT_SENSE VSS_SENSE_VTT

B15 A15

TP_VSS_SENSE_VTT 1

VTT_SENSE TP1202 TPAD14-GP

1

2

R1201 100R2F-L1-GP-U
R1202 100R2F-L1-GP-U

VCC_SENSE VSS_SENSE

2

A <Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VCC_CORE)

Size

Document Number

Rev

Berry

X00

Date: Thursday, October 22, 2009

Sheet 12

of

92

3

2

1

5

4

SSID = CPU

+CPU_GFX_CORE

22A

CPU1G

D C

2

SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP

2

2

2

2

C1301

C1302

C1303

C1304

C1305

1

1

1

1

DY DY DY DY UMA

1

C1306
UMA

1

C1307
UMA

1

C1308
UMA

2

2

2

2

1

DIS R1302
0R3J-0-U-GP

Please note that the VTT Rail Values are: Auburndale VTT=1.05V
Clarksfield VTT=1.1V

1

AT21 AT19 AT18 AT16 AR21 AR19 AR18 AR16 AP21 AP19 AP18 AP16 AN21 AN19 AN18 AN16 AM21 AM19 AM18 AM16 AL21 AL19 AL18 AL16 AK21 AK19 AK18 AK16 AJ21 AJ19 AJ18 AJ16 AH21 AH19 AH18 AH16

VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG

+1.05V_VTT

1

1

C1316

C1317

J24 J23 H25

VTT1 VTT1 VTT1

SC10U10V5KX-2GP

2

SC10U10V5KX-2GP

2

+1.05V_VTT

18A

B

2

1

2

1

2

1

C1320

C1321

DY

C1322

C1323

2

1

K26 J27 J26 J25 H27 G28 G27 G26 F26 E26 E25

VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1

SC10U10V5KX-2GP

SC10U10V5KX-2GP

SC10U10V5KX-2GP

SC10U10V5KX-2GP

CLARKU1NF

GRAPHICS

POWER DDR3 - 1.5V RAILS

PEG & DMI

FDI

CLARKSFIELD SENSE
GRAPHICS VIDs LINES

1

1

2

2

3

2

1

7 OF 9

VAXG_SENSE VSSAXG_SENSE

AR22 AT22

VCC_AXG_SENSE VSS_AXG_SENSE

D

GFX_VID GFX_VID GFX_VID GFX_VID GFX_VID GFX_VID GFX_VID

AM22 AP22 AN22 AP23 AM23 AP24 AN24

GFX_VID0 GFX_VID1 GFX_VID2 GFX_VID3 GFX_VID4 GFX_VID5 GFX_VID6

GFX_VR_EN GFX_DPRSLPVR
GFX_IMON

AR25 AT25 AM24

R1305 2 UMA 1 4K7R2J-2-GP

GFX_IMON_C 1 DY 2

R1304

0R2J-2-GP

GFX_VR_EN
GFX_DPRSLPVR GFX_IMON

+1.5V_RUN_CPU

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1

2

1

DIS 1
R1303

2 1KR2J-1-GP

3A

1

1

1

1

1

1

1

C1309 C1310 C1311 C1312 C1313 C1314 C1315

TC1301

2

2

2

2

2

2

2

DY SE330U2D5VDM-2GP

+1.5V_SUS

S3 Reduction

C

1

1

1

1

C1331

C1332 C1333

C1334

DY DY DY DY

2

2

2

2

SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP
SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U6D3V2KX-GP

VTT0 VTT0 VTT0 VTT0

P10 N10 L10 K10

2.6A

+1.05V_VTT

1

1

C1318 SC10U10V5KX-2GP

C1319 SC10U10V5KX-2GP

2

2

VTT1 VTT1 VTT1 VTT1 VTT1 VTT1

J22 J20 J18 H21 H20 H19

+1.05V_VTT

B

1

1

VCCPLL VCCPLL VCCPLL

L26 L27 M26

C1324 SC10U10V5KX-2GP

2

C1325

DY

SC4D7U6D3V3KX-GP

2

1.35A +1.8V_RUN

1

1

1

2

2

C1326 SC1U6D3V2KX-GP

C1327

C1328

C1329

C1330 SC10U6D3V5MX-3GP

1.1V

1.8V

2

SC2D2U10V3KX-1GP SC4D7U6D3V3KX-GP
SC1U6D3V2KX-GP

A

<Core Design>

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VCC_GFXCORE)

Size

Document Number

Rev

Berry

X00

Date: Thursday, October 22, 2009

Sheet 13

of

92

5

4

3

2

1

5

4

3

2

1

SSID = CPU

CPU1H

8 OF 9

D C B

AT20 AT17 AR31 AR28 AR26 AR24 AR23 AR20 AR17 AR15 AR12 AR9 AR6 AR3 AP20 AP17 AP13 AP10
AP7 AP4 AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11 AM8 AM5 AM2 AL34 AL31 AL23 AL20 AL17 AL12 AL9 AL6 AL3 AK29 AK27 AK25 AK20 AK17 AJ31 AJ23 AJ20 AJ17 AJ14 AJ11 AJ8 AJ5 AJ2 AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13 AH9 AH6 AH3 AG10 AF8 AF4 AF2 AE35

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

CLARKSFIELD

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30

CPU1I

9 OF 9

K27 K9 K6 K3 J32 J30 J21 J19
H35 H32 H28 H26 H24 H22 H18 H15 H13 H11
H8 H5 H2 G34 G31 G20 G9 G6 G3 F30 F27 F25 F22 F19 F16 E35 E32 E29 E24 E21 E18 E13 E11 E8 E5 E2 D33 D30 D26 D9 D6 D3 C34 C32 C29 C28 C24 C22 C20 C19 C16 B31 B25 B21 B18 B17 B13 B11 B8 B6 B4 A29 A27 A23 A9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NCYF TEST PIN: A35,AT1,AT35,B1,A3,A33,A34, AP1,AP35,AR1,AR35,AT2,AT3, AT33,AT34,C1,C35,B35
NCTF

CLARKSFIELD

VSS

VSS_NCTF VSS_NCTF VSS_NCTF

AR34 B34 B2

VSS_NCTF#A35 VSS_NCTF#AT1 VSS_NCTF#AT35
VSS_NCTF#B1 RSVD_NCTF#A3 RSVD_NCTF#A33 RSVD_NCTF#A34 RSVD_NCTF#AP1 RSVD_NCTF#AP35 RSVD_NCTF#AR1 RSVD_NCTF#AR35 RSVD_NCTF#AT2 RSVD_NCTF#AT3 RSVD_NCTF#AT33 RSVD_NCTF#AT34 RSVD_NCTF#C1 RSVD_NCTF#C35 RSVD_NCTF#B35

A35 AT1 AT35 B1 A3 A33 A34 AP1 AP35 AR1 AR35 AT2 AT3 AT33 AT34 C1 C35 B35

TP_MCP_VSS_NCTF1 TP_MCP_VSS_NCTF2 TP_MCP_VSS_NCTF3 TP_MCP_VSS_NCTF4

1

TP1401

1

TP1402

1

TP1403

1

TP1404

D C B

CLARKU1NF

CLARKU1NF

A

<Core Design>

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU (VSS)

Size

Document Number

Rev

Berry

X00

Date: W ednesday, October 14, 2009

Sheet 14

of

92

5

4

3

2

1

2

C1819 SC1U10V2KX-1GP

2

5
SSID = MEMORY
D

C

+V_DDR_REF
C1811 SCD1U10V2KX-5GP

1

1

C1812
DY SC2D2U10V3KX-1GP

2

2

+0.75V_DDR_VTT

1

B

DY

C1818 SC10U6D3V5KX-1GP

2

+0.75V_DDR_VTT

Place these caps close to VTT1 and VTT2.

1

1

1

1

DY

DY

C1820 SC1U10V2KX-1GP

2

C1821 SC1U10V2KX-1GP

2

C1822 SC1U10V2KX-1GP

2

1

4

3

2

M_A_BS2
M_A_BS0 M_A_BS1 M_A_DQ[63..0]

C1813 SCD1U10V2KX-5GP

M_ODT0 M_ODT1

+V_DDR_REF

DDR3_DRAMRST# +0.75V_DDR_VTT

M_A_DM[7..0] M_A_DQS#[7..0]

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15
M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7
M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

DM1

98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78 79

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2

109 108

BA0 BA1

5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

10 27 45 62 135 152 169 186

DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#

12 29 47 64 137 154 171 188

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7

116 120

ODT0 ODT1

126 1

VREF_CA VREF_DQ

30 RESET#

203 204

VTT1 VTT2

NP1 NP2
RAS# WE# CAS#
CS0# CS1#
CKE0 CKE1
CK0 CK0#
CK1 CK1#
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7
SDA SCL
EVENT#
VDDSPD
SA0 SA1
NC#1 NC#2 NC#/TEST
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NP1 NP2
110 113 115
114 121
73 74
101 103
102 104
11 28 46 63 136 153 170 187
200 202
198
199
197 201
77 122 125
75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124
2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

H =4mm
DDR3-204P-47-GP

62.10017.P31

M_A_DQS[7..0] M_A_A[15..0]

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7
SA0_DIM0 SA1_DIM0
+1.5V_SUS

M_A_RAS# M_A_W E# M_A_CAS# M_CS#0 M_CS#1 M_CKE0 M_CKE1 M_CLK_DDR0 M_CLK_DDR#0 M_CLK_DDR1 M_CLK_DDR#1
PCH_SMBDATA PCH_SMBCLK
PM_EXTTS#0
C1801 SCD1U10V2KX-5GP

SEC. 62.10017.P11

2

1

SA0_DIM0 SA1_DIM0

1

Note: If SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30

1

R1803 10KR2J-3-GP

R1804 10KR2J-3-GP

If SA0 DIM0 = 1, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA2 SO-DIMMA TS Address is 0x32

2

2

+3.3V_RUN
DY C1802 SC2D2U10V3KX-1GP

1

2

+1.5V_SUS

SODIMM A DECOUPLING

2

1

TC1801 C1803
DY

2

1

C1804

2

1

2

1

C1805 C1806
DY

2

1

C1807

2

1

2

1

C1808 C1809 C1810
DY DY DY

2

1

2

1

SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP SC10U10V5ZY-1GP
SC10U10V5KX-2GP SC10U10V5KX-2GP SC10U10V5ZY-1GP SC10U6D3V5KX-1GP SC10U10V5KX-2GP SE330U2D5VDM-2GP

1

2

SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP

C1814
Layout Note: Place these Caps near SO-DIMMA.

2

1

C1815

2

1

C1816

2

1

C1817

2 S3 Power Reduction
+0.75V_DDR_VTT
R1806 22R2J-2-GP

1

2

DISCHARGE_0D75V

G D
S

PS_S3CNTRL

Q1801
. . ...
2N7002E-1-GP
84.2N702.D31

A

5

4

3

2

1 D

C

B

A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DDR3-SODIMM1

Size

Document Number

Berry

Date: Thursday, October 22, 2009 1

Sheet 18

of

Rev
X00
92

5

4

3

2

1

SSID = MEMORY

DM2

D C B

+V_DDR_REF
C1915 SCD1U10V2KX-5GP

2

1

2

1

C1916 SC2D2U10V3KX-1GP
DY

2

1

M_B_BS2
M_B_BS0 M_B_BS1 M_B_DQ[63..0]

C1917 SCD1U10V2KX-5GP

M_ODT2 M_ODT3

+0.75V_DDR_VTT

DDR3_DRAMRST#

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15
M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7
M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7
+V_DDR_REF

98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78 79

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2

109 108

BA0 BA1

5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

10 27 45 62 135 152 169 186

DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#

12 29 47 64 137 154 171 188

DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7

116 120

ODT0 ODT1

126 1

VREF_CA VREF_DQ

30 RESET#

203 204

VTT1 VTT2

NP1 NP2
RAS# WE# CAS#
CS0# CS1#
CKE0 CKE1
CK0 CK0#
CK1 CK1#
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7
SDA SCL
EVENT#
VDDSPD
SA0 SA1
NC#1 NC#2 NC#/TEST
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NP1 NP2
110 113 115
114 121
73 74
101 103
102 104
11 28 46 63 136 153 170 187
200 202
198
199
197 201
77 122 125
75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124
2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7
SA0_DIM1 SA1_DIM1
+1.5V_SUS

SCD1U16V2KX-3GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U16V2KX-3GP

M_B_RAS# M_B_W E# M_B_CAS#
M_CS#2 M_CS#3
M_CKE2 M_CKE3
M_CLK_DDR2 M_CLK_DDR#2
M_CLK_DDR3 M_CLK_DDR#3

M_B_DM[7..0] M_B_DQS#[7..0]
M_B_DQS[7..0] M_B_A[15..0]

PCH_SMBDATA PCH_SMBCLK PM_EXTTS#1
C1901 SCD1U10V2KX-5GP

1

1

+3.3V_RUN
DY C1902 SC2D2U10V3KX-1GP

+3.3V_RUN

1

SA1_DIM1 SA0_DIM1

2

1

R1903 10KR2J-3-GP

2

R1902 10KR2J-3-GP
Note: If SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30
If SA0 DIM0 = 1, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA2 SO-DIMMA TS Address is 0x32

2

2

+1.5V_SUS

SODIMM B DECOUPLING

2

1

C1903 C1904 C1905
DY DY

2

1

2

1

C1906

2

1

C1907

2

1

2

1

C1908 C1909
DY

1

C1910
DY

1

2

2

SC10U6D3V5KX-1GP

SC10U10V5KX-2GP

SC10U10V5ZY-1GP

SC10U10V5KX-2GP

SC10U10V5KX-2GP

SC10U10V5KX-2GP

SC10U10V5ZY-1GP

SC10U10V5ZY-1GP

1

Layout Note: Place these Caps near SO-DIMMB.

C1911

2

1

C1912

2

1

C1913

2

1

C1914

2

D C B

Place these caps

1

1

close to VTT1 and

VTT2.

DY

DY

2

2

2

1

2

1

H = 8mm DDR3-204P-55-GP 62.10017.Q31

C1921 SC1U10V2KX-1GP

C1920 SC1U10V2KX-1GP

C1919 SC1U10V2KX-1GP

C1918 SC1U10V2KX-1GP

SEC. 62.10017.N71

Note: SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34

SO-DIMMB is placed farther from the Processor than SO-DIMMA

A

A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

DDR3-SODIMM2

Size

Document Number

Rev

Berry

X00

Date: Thursday, October 22, 2009

Sheet 19

of

92

5

4

3

2

1

5

4

3

2

1

+3.3V_RUN

Digital Display Interface

U2001D

4 OF 10

3

4

D

GPU_LVDS_CLK GPU_LVDS_DATA

RN2001

1

4

2 UMA 3

SRN0J-6-GP

PCH_VGA_BLEN PCH_LCDVDD_EN
PCH_LBKLT_CTL

LDDC_CLK_PCH LDDC_DATA_PCH
LCTRL_CLK LCTRL_DATA

T48 T47
Y48
AB48 Y45
AB46 V48

L_BKLTEN L_VDD_EN
L_BKLTCTL
L_DDC_CLK L_DDC_DATA
L_CTRL_CLK L_CTRL_DATA

SDVO_TVCLKINN SDVO_TVCLKINP
SDVO_STALLN SDVO_STALLP
SDVO_INTN SDVO_INTP

BJ46 BG46
BJ48 BG48
BF45 BH45

1

2

RN2006
UMASRN2K2J-1-GP

D

4

3

2

1

R2002

DY 2

1 PCH_LCDVDD_EN

100KR2J-1-GP

+3.3V_RUN

Place near PCH UMA

2

1

TPAD14-GP
R2001 2K37R2F-GP

Impedance:85 ohm

TP2001 1LVDS_VBG

LIBG

AP39 AP41

RN2004

1

4 LVD_VREFH AT43

UMA 2

3 LVD_VREFL AT42

SRN0J-6-GP
PCH_LVDSA_TXC# PCH_LVDSA_TXC

AV53 AV51

PCH_LVDSA_TX0# PCH_LVDSA_TX1# PCH_LVDSA_TX2#

BB47 BA52 AY48 AV47

PCH_LVDSA_TX0 PCH_LVDSA_TX1 PCH_LVDSA_TX2

BB48 BA50 AY49 AV48

LVD_IBG LVD_VBG
LVD_VREFH LVD_VREFL
LVDSA_CLK# LVDSA_CLK
LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3
LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3

LVDS

SDVO_CTRLCLK SDVO_CTRLDATA

T51 T53

PCH_HDMI_CLK PCH_HDMI_DATA

DDPB_AUXN DDPB_AUXP
DDPB_HPD
DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

BG44 BJ44 AU38
BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38

HDMI_DATA2#_C HDMI_DATA2_C HDMI_DATA1#_C HDMI_DATA1_C HDMI_DATA0#_C HDMI_DATA0_C HDMI_CLK#_C HDMI_CLK_C

UMA1 UMA1 UMA1 UMA1 UMA1 UMA1 UMA1 UMA1

2 C2001 2 C2002 2 C2003 2 C2004 2 C2005 2 C2006 2 C2007 2 C2008

SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP

HDMI_PCH_DET
HDMI_PCH_DATA2# HDMI_PCH_DATA2 HDMI_PCH_DATA1# HDMI_PCH_DATA1 HDMI_PCH_DATA0# HDMI_PCH_DATA0 HDMI_PCH_CLK# HDMI_PCH_CLK

DDPC_CTRLCLK DDPC_CTRLDATA

Y49 AB49

Close to VGA

RN2002

C

UMA SRN2K2J-4-GP

PCH_LVDSB_TXC# PCH_LVDSB_TXC

AP48 AP47

LVDSB_CLK# LVDSB_CLK

8

7

6

5

LCTRL_DATA LCTRL_CLK LDDC_CLK_PCH LDDC_DATA_PCH

PCH_LVDSB_TX0# PCH_LVDSB_TX1# PCH_LVDSB_TX2#
PCH_LVDSB_TX0 PCH_LVDSB_TX1 PCH_LVDSB_TX2

AY53 AT49 AU52 AT53
AY51 AT48 AU50 AT51

LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3
LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3

Close to ball <600mil

DDPC_AUXN DDPC_AUXP
DDPC_HPD
DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

BE44 BD44 AV40
BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36

Impedance:85 ohm

Impedance:100 ohm

C

PCH_CRT_BLUE PCH_CRT_GREEN
PCH_CRT_RED
RN2005

5

6

7

8

Need Level Shift
PCH_CRT_DDCCLK PCH_CRT_DDCDATA

AA52 AB53 AD53

CRT_BLUE CRT_GREEN CRT_RED

V51 V53

CRT_DDC_CLK CRT_DDC_DATA

DDPD_CTRLCLK DDPD_CTRLDATA

U50 U52

DDPD_AUXN DDPD_AUXP
DDPD_HPD

BC46 BD46 AT38

B

UMA SRN150F-1-GP

4

3

2

1

PCH_CRT_HSYNC

Y53

PCH_CRT_VSYNC

Y51

2.5V Tolerance CRT_IREF AD48
AB51

1

R2007

CRT_HSYNC CRT_VSYNC
DAC_IREF CRT_IRTN

CRT

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36

B

IBEXPEAK-M-GP-NF

1KR2J-1-GP

2

20090918

<Core Design>

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (LVDS/CRT/DDI)

Size

Document Number

Berry

Date: Thursday, October 22, 2009

Sheet 20

of

Rev
X00
92

5

4

3

2

1

+3.3V_RUN

PCI_TRDY# PCI_DEVSEL# INT_PIRQA# PCI_IRDY#

5

RN2101

1

10

2

9

3

8

4

7

5

6

SRN8K2J-2-GP-U

PCI_FRAME# PCI_REQ2# INT_PIRQD# PCI_SERR#

+3.3V_RUN

4
SSID = PCH

D +3.3V_RUN

INT_PIRQH# INT_PIRQB# INT_PIRQF# PCI_REQ3#

RN2103

1

10

2

9

3

8

4

7

5

6

SRN8K2J-2-GP-U

PCI_REQ1# PCI_PLOCK# PCI_PERR# PCI_REQ0#

+3.3V_RUN

RN2102

1

8 PCI_STOP#

2

7 INT_PIRQE#

3

6 INT_PIRQC#

4

5 INT_PIRQG#

SRN8K2J-4-GP

+3.3V_RUN

PLT_RST#

BOOT BIOS Strap

PCI_GNT#1 PCI_GNT#0 BOOT BIOS Location

0

0

LPC

C

0

1

Reserved

1

0

PCI

1

1

SPI(Default)

+3.3V_ALW

USB_OC#2_3 SMC_W AKE_SCI#_R
USB_OC#6_7 USB_OC#0_1

RN2104
1 2 3 4 5

10 9 USB_OC#12_13 8 USB_OC#8_9 7 USB_OC#10_11 6 USB_OC#4_5

SRN8K2J-2-GP-U

+3.3V_ALW

PCI_GNT3#

R2105
1 DY 2
4K7R2J-2-GP

+3.3V_RUN

U2101

DY 5
4

VCC Y

A B GND

1 2 3

PCI_PLTRST#

NL17SZ08DFT2G-GP

1 R2101

2 0R2J-2-GP

1

DY C2101 SC220P50V2KX-3GP

2

TPAD14-GP TP2102 TPAD14-GP TP2103 TPAD14-GP TP2104
TPAD14-GP TP2110

B
A16 swap override Strap/Top-Block Swap Override jumper

PCI_GNT#3

Low = A16 swap override/Top-Block Swap Override enabled High = Default

PCLK_FW H CLK_PCI_FB PCLK_KBC

TPAD14-GP TP2115

1 R2107 1 R2108 1 R2109

2 2 22R2J-2-GP 2 22R2J-2-GP
22R2J-2-GP

2

EC2101
DY SC4D7P50V2CN-1GP

1

3

INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#
PCI_REQ0# PCI_REQ1# PCI_REQ2# PCI_REQ3#
1 PCI_GNT0# 1 PCI_GNT1# 1 PCI_GNT2#
PCI_GNT3#
INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH#
1 PCIRST#
PCI_SERR# PCI_PERR#

U2001E

H40 N34 C44 A38 C36 J34 A40 D45 E36 H48 E40 C40 M48 M45 F53 M40 M43 J36 K48 F40 C42 K46 M51 J52 K51 L34 F42 J40 G46 F44 M47 H36

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31

J50 G42 H47 G34

C/BE0# C/BE1# C/BE2# C/BE3#

G38 H51 B37 A44

PIRQA# PIRQB# PIRQC# PIRQD#

F51 A46 B45 M53

REQ0# REQ1#/GPIO50 REQ2#/GPIO52 REQ3#/GPIO54

F48 K45 F36 H53

GNT0# GNT1#/GPIO51 GNT2#/GPIO53 GNT3#/GPIO55

B41 K53 A36 A48

PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5

K6 PCIRST#

E44 E50

SERR# PERR#

PCI_IRDY#
PCI_DEVSEL# PCI_FRAME#
PCI_PLOCK#
PCI_STOP# PCI_TRDY#
1 PCH_PME#
PCI_PLTRST#
PCLK_FW H_R CLK_PCI_FB_R PCLK_KBC_R

A42 H44 F46 C46

IRDY# PAR DEVSEL# FRAME#

D49 PLOCK#

D41 C48

STOP# TRDY#

M7 PME#

D5 PLTRST#

N52 P53 P46 P51 P48

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

IBEXPEAK-M-GP-NF

KBC CLK EMI

A

5

4

3

PCI

USB

NVRAM

2

1

5 OF 10
NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3
NV_DQS0 NV_DQS1
NV_DQ0/NV_IO0 NV_DQ1/NV_IO1 NV_DQ2/NV_IO2 NV_DQ3/NV_IO3 NV_DQ4/NV_IO4 NV_DQ5/NV_IO5 NV_DQ6/NV_IO6 NV_DQ7/NV_IO7 NV_DQ8/NV_IO8 NV_DQ9/NV_IO9 NV_DQ10/NV_IO10 NV_DQ11/NV_IO11 NV_DQ12/NV_IO12 NV_DQ13/NV_IO13 NV_DQ14/NV_IO14 NV_DQ15/NV_IO15
NV_ALE NV_CLE

AY9 BD1 AP15 BD8
AV9 BG8
AP7 AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6 BD6 BB7 BC8 BJ8 BJ6 BG6
BD3 AY6

NV_ALE NV_CLE

DMI Termination Voltage
NV_CLE Set to Vss when low. Set to Vcc when high.

1

+V_NVRAM_VCCQ
R2102
DY1KR2J-1-GP

2

NV_CLE D

Danbury Technology: Disabled when Low. Enable when High.

1

+V_NVRAM_VCCQ
R2103
DY1KR2J-1-GP

2

NV_ALE

NV_RCOMP
NV_RB#
NV_WR#0_RE# NV_WR#1_RE#
NV_WE#_CK0 NV_WE#_CK1

AU2
AV7
AY8 AY5
AV11 BF5

NV_RCOMP 1

TP2105 TPAD14-GP

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

H18 J18 A18 C18 N20 P20 J20 L20 F20 G20 A20 C20 M22 N22 B21 D21 H22 J22 E22 F22 A22 C22 G24 H24 L24 M24 A24 C24

USB_PN0 USB_PP0 USB_PN1 USB_PP1 USB_PN2 USB_PP2
USB_PN4 USB_PP4 USB_PN5 USB_PP5
USB_PN8 USB_PP8 USB_PN9 USB_PP9
USB_PN11 USB_PP11
USB_PN13 USB_PP13

USBRBIAS# B25 USBRBIAS D25

USB_RBIAS_PN

1

2

R2106

22D6R2F-L1-GP

USB

Pair

Device

0 USB2 (CRT Board)

C

1 USB3 (CRT Board)

2 WLAN (I/O Board)

3X

4 CARD READER

5 BLUETOOTH

6X

7X

8 USB1 (I/O Board)

9 ESATA (I/O Board COMBO)

10 X

11 W-WAN (I/O Board)

12 X

13 CAMERA

B

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43
OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

N16 J16 F16 L16 E14 G16 F12 T15

USB_OC#0_1 USB_OC#2_3 USB_OC#4_5 USB_OC#6_7 USB_OC#8_9 USB_OC#10_11 USB_OC#12_13 SMC_W AKE_SCI#_R

USB_OC#0_1 USB_OC#8_9

<Core Design>

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (PCI/USB/NVRAM)

Size

Document Number

Rev

Berry

X00

Date: Thursday, October 22, 2009

Sheet 21

of

92

2

1

5

4

3

2

1

SSID = PCH

RN2201

FDI_PCH_TXP3 1

8

FDI_PCH_TXN3 2

7

FDI_TXP3 FDI_TXN3

D

+1.05V_VTT

DMI_CTX_PRXN0 DMI_CTX_PRXN1 DMI_CTX_PRXN2 DMI_CTX_PRXN3
DMI_CTX_PRXP0 DMI_CTX_PRXP1 DMI_CTX_PRXP2 DMI_CTX_PRXP3
DMI_PTX_CRXN0 DMI_PTX_CRXN1 DMI_PTX_CRXN2 DMI_PTX_CRXN3
DMI_PTX_CRXP0 DMI_PTX_CRXP1 DMI_PTX_CRXP2 DMI_PTX_CRXP3

R2202

1

2

49D9R2F-GP

DMI_IRCOMP_R

U2001C

BC24 BJ22 AW20 BJ20
BD24 BG22 BA20 BG20
BE22 BF21 BD20 BE18
BD22 BH21 BC20 BD18

DMI0RXN DMI1RXN DMI2RXN DMI3RXN
DMI0RXP DMI1RXP DMI2RXP DMI3RXP
DMI0TXN DMI1TXN DMI2TXN DMI3TXN
DMI0TXP DMI1TXP DMI2TXP DMI3TXP

BH25 BF25

DMI_ZCOMP DMI_IRCOMP

3 OF 10
FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7
FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1

BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12
BB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12
BJ14
BF13
BH13
BJ12
BG14

FDI_PCH_TXN0 FDI_PCH_TXN1 FDI_PCH_TXN2 FDI_PCH_TXN3 FDI_PCH_TXN4 FDI_PCH_TXN5 FDI_PCH_TXN6 FDI_PCH_TXN7
FDI_PCH_TXP0 FDI_PCH_TXP1 FDI_PCH_TXP2 FDI_PCH_TXP3 FDI_PCH_TXP4 FDI_PCH_TXP5 FDI_PCH_TXP6 FDI_PCH_TXP7
R2201
FDI_INT_C 1 UMA 2
0R2J-2-GP FDI_FSYNC0_C
FDI_FSYNC1_C
FDI_LSYNC0_C
FDI_LSYNC1_C

FDI_INT

FDI_PCH_TXN1 FDI_PCH_TXP1
FDI_PCH_TXN4 FDI_PCH_TXP4 FDI_PCH_TXP0 FDI_PCH_TXN0
FDI_PCH_TXP6 FDI_PCH_TXN6 FDI_PCH_TXN2 FDI_PCH_TXP2
FDI_PCH_TXN7 FDI_PCH_TXP7 FDI_PCH_TXP5 FDI_PCH_TXN5

3 4

UMA

6 5

SRN0J-7-GP

RN2202

1

8

2

7

3 4

UMA

6 5

SRN0J-7-GP

RN2203

1

8

2 3

UMA

7 6

4

5

SRN0J-7-GP

RN2204

1

8

2 3

UMA

7 6

4

5

SRN0J-7-GP

FDI_LSYNC1_C FDI_FSYNC1_C FDI_LSYNC0_C FDI_FSYNC0_C

RN2205

1

8

2 3

UMA

7 6

4

5

FDI_TXN1 FDI_TXP1
FDI_TXN4 FDI_TXP4 FDI_TXP0 FDI_TXN0
FDI_TXP6 FDI_TXN6 FDI_TXN2 FDI_TXP2
FDI_TXN7 FDI_TXP7 FDI_TXP5 FDI_TXN5
FDI_LSYNC1 FDI_FSYNC1 FDI_LSYNC0 FDI_FSYNC0

D

SRN0J-7-GP

System Power Management DMI FDI

C XDP_DBRESET#

T6 SYS_RESET#

WAKE# J12

PCIE_W AKE#

PM_PW ROK

PM_DRAM_PW RGD

PCH_RSMRST#

SUS_PW R_DN_ACK PM_PW RBTN#_R
PM_PW RBTN#

B

AC_PRESENT_EC

M6 SYS_PWROK

R2204 1

2 0R2J-2-GP PM_PW RGD

B17

RN2207

3

2

4

1

R2206

1

2 MEPW ROK K5

0R2J-2-GP

LAN_RST#1

A10

SRN10KJ-5-GP D9

PWROK MEPWROK LAN_RST# DRAMPWROK

1 R2213

2

PM_RSMRST#_R

0R2J-2-GP

1 R2215

2

SUS_PW R_ACK

0R2J-2-GP

1 R2218

2 0R2J-2-GP

PM_PW RBTN#_R

1 R2219

2

AC_PRESENT

0R2J-2-GP

PM_BATLOW #_R

C16 RSMRST# M1 SUS_PWR_DN_ACK/GPIO30 P5 PWRBTN# P7 ACPRESENT/GPIO31 A6 BATLOW#/GPIO72

CLKRUN#/GPIO32 Y1
SUS_STAT#/GPIO61 P8 SUSCLK/GPIO62 F3 SLP_S5#/GPIO63 E4 SLP_S4# H7 SLP_S3# P12 SLP_M# K8 TP23 N2 PMSYNCH BJ10

PM_CLKRUN#

PM_SUS_STAT# 1

PCH_SUSCLK

PCH_SLP_S5#

1

PM_SLP_S4#_R

PM_SLP_S3#_R

SIO_SLP_M#_R 1

PM_SLP_DSW# 1

H_PM_SYNC

TP2201 TPAD14-GP depend on Layout

1 R2209

2 0R2J-2-GP

1

2

R2211 10R2J-2-GP

TP2202

TPAD14-GP

1 R2214

2 0R2J-2-GP

PCH_SUSCLK_2102 PCH_SUSCLK_KBC
PM_SLP_S4#

1 R2216

2 0R2J-2-GP

PM_SLP_S3#

TP2203TPAD14-GP

TP2204TPAD14-GP

H_PM_SYNC

PM_RI#

F14 RI# IBEXPEAK-M-GP-NF

SLP_LAN#/GPIO29 F6

PM_SLP_LAN# 1

TP2205TPAD14-GP

C

+3.3V_ALW

PM_BATLOW #_R PM_RI# AC_PRESENT_EC SUS_PW R_ACK

RN2206

1

8

2

7

3

6

4

5

SRN10KJ-6-GP

PCIE_W AKE#

1 R2210

2 1KR2J-1-GP

PCH_RSMRST#

R2217

1

2

10KR2J-3-GP

B

PM_CLKRUN# 1

+3.3V_RUN 2

1

Option to " Disable " clkrun.

R2221 DY

Pulling it down will keep the clks running. 10KR2J-3-GP

R2220 10KR2J-3-GP

2

A

<Core Design>

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (DM I/FDI/PM)

Size

Document Number

Rev

Berry

X00

Date: Thursday, October 22, 2009

Sheet 22

of

92

5

4

3

2

1

5

4

3

2

1

SSID = PCH

+3.3V_ALW

U2001B

2 OF 10

+3.3V_ALW

2

1

D

PCIE_RXN2

PCIE_RXP2 PCIE_TXN2 PCIE_TXP2

C2301 SCD1U10V2KX-4GP 1 C2302 SCD1U10V2KX-4GP 1

2 PCIE_C_TXN2 2 PCIE_C_TXP2

PCIE_RXN3 PCIE_RXP3
PCIE_TXN3 PCIE_TXP3

C2303 SCD1U10V2KX-4GP 1 C2306 SCD1U10V2KX-4GP 1

2 PCIE_C_TXN3 2 PCIE_C_TXP3

PCIE_RXN4 PCIE_RXP4
PCIE_TXN4 PCIE_TXP4

C2304 SCD1U10V2KX-4GP 1 C2305 SCD1U10V2KX-4GP 1

2 PCIE_C_TXN4 2 PCIE_C_TXP4

C
PCIECLKRQ{0,3,4,5,6,7}# should have a 10K pull-up to +3.3V_ALW. PCIECLKRQ{1,2} should have a 10K pull-up to +3.3_RUN

BG30 BJ30 BF29 BH29
AW30 BA30 BC30 BD30
AU30 AT30 AU32 AV32
BA32 BB32 BD32 BE32
BF33 BH33 BG32 BJ32
BA34 AW34 BC34 BD34
AT34 AU34 AU36 AV36
BG34 BJ34 BG36 BJ36

PERN1 PERP1 PETN1 PETP1

PERN2 PERP2

WLAN

PETN2

PETP2

PERN3

PERP3 PETN3

LAN

PETP3

PERN4

PERP4 PETN4

W-WAN

PETP4

PERN5 PERP5 PETN5 PETP5

PERN6 PERP6 PETN6 PETP6

PERN7 PERP7 PETN7 PETP7

PERN8 PERP8 PETN8 PETP8

PCIE_CLK_RQ0#

AK48 AK47
P9

CLKOUT_PCIE0N CLKOUT_PCIE0P
PCIECLKRQ0#/GPIO73

PCIE_CLK_RQ1#

AM43 AM45
U4

CLKOUT_PCIE1N CLKOUT_PCIE1P
PCIECLKRQ1#/GPIO18

CLK_PCIE_W LAN# CLK_PCIE_W LAN
W LAN_CLKREQ#

AM47 AM48
N4

CLKOUT_PCIE2N CLKOUT_PCIE2P
PCIECLKRQ2#/GPIO20

From CLK BUFFER PEG

PCI-E*
Controller
Link

SMBus

SMBALERT#/GPIO11 B9 SMBCLK H14
SMBDATA C8

PCH_SMB_CLK PCH_SMB_DATA

SML0ALERT#/GPIO60 J14 SML0CLK C6
SML0DATA G8

TPM_ID1 SML0_CLK SML0_DATA

PCH_GPIO11
SML0_CLK SML0_DATA

TPM_ID1

2 R2305

LPD_SPI_INTR# 2 R2311

1 10KR2J-3-GP 1 10KR2J-3-GP

+3.3V_ALW

4

3

RN2302 SRN2K2J-1-GP
D PCH_SMB_CLK PCH_SMB_DATA

SML1ALERT#/GPIO74 M14 SML1CLK/GPIO58 E10
SML1DATA/GPIO75 G12

LPD_SPI_INTR# KBC_SCL1 KBC_SDA1

CL_CLK1 T13 CL_DATA1 T11 CL_RST1# T9

CL_CLK 1 CL_DATA 1 CL_RST# 1

TP2302 TPAD14-GP TP2303 TPAD14-GP TP2304 TPAD14-GP

DY

PEG_A_CLKRQ#/GPIO47

H1

PEG_CLKREQ#_C 1 R2310

2 0R2J-2-GP

KBC_SCL1 KBC_SDA1

RN2309 SRN2K2J-1-GP

SML0_DATA SML0_CLK
PEG_CLKREQ#

1

4

2

3

1

4

2

3

RN2301 SRN2K2J-1-GP
KBC_SCL1 KBC_SDA1

+3.3V_ALW
R2308
UMA 10KR2J-3-GP
PEG_CLKREQ#_C
R2309
DIS 10KR2J-3-GP

12

1

2

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

AD43 AD45

CLK_PCIE_VGA# CLK_PCIE_VGA

CLK_PCIE_VGA# CLK_PCIE_VGA

C

CLKOUT_DMI_N CLKOUT_DMI_P

AN4 AN2

CLK_EXP_N CLK_EXP_P

CLK_EXP_N CLK_EXP_P

+3.3V_RUN

RN2303

CLKOUT_DP_N/CLKOUT_BCLK1_N CLKOUT_DP_P/CLKOUT_BCLK1_P

AT1 AT3

2

3

1

4

SRN2K2J-1-GP

CLKIN_DMI_N CLKIN_DMI_P

AW24 CLKIN_DMI# BA24 CLKIN_DMI

CLKIN_BCLK_N CLKIN_BCLK_P

AP3 AP1

CLK_CPU_BCLK# CLK_CPU_BCLK

CLKIN_DMI# CLKIN_DMI
CLK_CPU_BCLK# CLK_CPU_BCLK

PCH_SMB_DATA

Q2301

6

1

5

2

PCH_SMBDATA

CLKIN_DOT_96N CLKIN_DOT_96P

F18 E18

CLKIN_SATA_N/CKSSCD_N CLKIN_SATA_P/CKSSCD_P

AH13 AH12

CLK_DREF# CLK_DREF
CLK_PCIE_SATA# CLK_PCIE_SATA

PCH_SMB_CLK

4

3

2N7002EDW -GP
84.27002.F3F

PCH_SMBCLK

CLK_PCIE_LAN# CLK_PCIE_LAN

AH42 AH41

CLKOUT_PCIE3N CLKOUT_PCIE3P

REFCLK14IN P41 CLK_PCH_14M

CLK_PCH_14M

B

2 R2304

1

PCIE_CLK_RQ3#

10KR2J-3-GP

A8 PCIECLKRQ3#/GPIO25

CLKIN_PCILOOPBACK J42

CLK_PCI_FB

CLK_PCI_FB

B

+3.3V_ALW

CLK_PCIE_W W AN# CLK_PCIE_W W AN
W W AN_CLKREQ#

RN2307

1

8

2

7

3

6

4

5

SRN10KJ-6-GP

W W AN_CLKREQ# PCIE_CLK_RQ0# PEG_B_CLKRQ# PCIE_CLK_RQ5#

PCIE_CLK_RQ5# PEG_B_CLKRQ#

AM51 AM53
M9

CLKOUT_PCIE4N CLKOUT_PCIE4P
PCIECLKRQ4#/GPIO26

AJ50 AJ52
H6

CLKOUT_PCIE5N CLKOUT_PCIE5P
PCIECLKRQ5#/GPIO44

AK53 AK51
P13

CLKOUT_PEG_B_N CLKOUT_PEG_B_P
PEG_B_CLKRQ#/GPIO56

IBEXPEAK-M-GP-NF

Clock Flex

XTAL25_IN XTAL25_OUT
XCLK_RCOMP

AH51 AH53
AF38

XTAL25_IN XTAL25_OUT
XCLK_RCOMP

R2306 1

2 90D9R2F-1-GP

CLKOUTFLEX0/GPIO64 T45 CLK_PCH_GPIO64 1

TP2301 TPAD14-GP

CLKOUTFLEX1/GPIO65 P43 CLK_PCI_LPC

1

TP2305 TPAD14-GP

CLKOUTFLEX2/GPIO66 T42 CLK_PCH_REF14 1

TP2306 TPAD14-GP

CLKOUTFLEX3/GPIO67 N50

CLK48_GPIO

2

R2307

1 33R2J-2-GP

+1.05V_VTT XTAL25_IN
UMA R2303 1M1R2J-GP XTAL25_OUT
CLK_48M_CARD

1

2

1

2

DIS uses 0ohm 63.R0034.1DL UMA uses 18pF 78.18034.1FL
C2308 2 CO1 LAY SC18P50V2JN-1-GP
X2301
UMA XTAL-25MHZ-102-GP
C2307
2 UM1 A
SC18P50V2JN-1-GP

2

For EMI

1

DY EC2301
SC22P50V2JN-4GP

A 5

+3.3V_RUN

RN2308

4

5

3

6

2

7

1

8

SRN10KJ-6-GP

XDP_DBRESET# W LAN_CLKREQ# INT_SERIRQ PCIE_CLK_RQ1#

XDP_DBRESET# INT_SERIRQ

4

3

<Core Design>

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (PCI-E/SMBUS/CLOCK/CL)

Size

Document Number

Rev

Berry

X00

Date: Thursday, October 22, 2009

Sheet 23

of

92

2

1

5

4

3

2

1

1 R2402

2 10MR2J-L-GP

PCH_RTCX1 PCH_RTCX2

X2401

1

4

+RTC_CELL

R2401

1

2

20KR2J-L2-GP

1

C2402 SC1U6D3V2KX-GP

INTVRMEN- Integrated SUS 1.1V VRM Enable High - Enable internal VRs

SSID = PCH

2

1

1

SC12P50V2JN-3GP

C2403

D

2

3

C2401

U2001A

1 OF 10

LPC_LAD[0..3]

LPC_LAD[0..3]

D

2

X-32D768KHZ-65-GP
82.30001.A41

2

SC12P50V2JN-3GP

+RTC_CELL

R2403

1

2

20KR2J-L2-GP C2404
SC1U6D3V2KX-GP

1

2

G2401 GAP-OPEN

R2407

2

1

1M1R2J-GP

PCH_RTCX1 PCH_RTCX2

B13 D13

RTCX1 RTCX2

PCH_RTCRST# SRTCRST# SM_INTRUDER#

C14 RTCRST# D17 SRTCRST# A16 INTRUDER#

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3
FWH4/LFRAME#
LDRQ0# LDRQ1#/GPIO23

D33 LPC_LAD0 B33 LPC_LAD1 C32 LPC_LAD2 A32 LPC_LAD3
C34
A34 F34

LPC_LFRAME#

RTC

2

1

+RTC_CELL

1 R2404

2

PCH_INTVRMEN

330KR2F-L-GP

A14 INTVRMEN

SERIRQ AB9

INT_SERIRQ

SATA LPC

PCH_AZ_CODEC_BITCLK PCH_AZ_CODEC_SYNC
ACZ_SPKR PCH_AZ_CODEC_RST#

C PCH_SDOUT_CODEC

+3.3V_RUN NO REBOOT STRAP

DY 1
R2410

2 ACZ_SPKR 1KR2J-1-GP

No Reboot Strap R23 Low = Default
HDA_SPKR High = No Reboot

For EMI

PCH_AZ_CODEC_BITCLK

B

PCH_AZ_CODEC_RST#

2

2

EC2402 SCD1U16V2KX-3GP

1

DY DY

1

EC2401 SC22P50V2JN-4GP

PCH_SPI_CLK PCH_SPI_CS0#
PCH_SPI_DO PCH_SPI_DI

R2405 1 R2406 1

R2408

1

2 33R2J-2-GP 2 33R2J-2-GP
2 33R2J-2-GP

ACZ_BIT_CLK ACZ_SYNC_R ACZ_SPKR ACZ_RST#_R

A30 HDA_BCLK D29 HDA_SYNC
P1 SPKR C30 HDA_RST#

PCH_SDIN_CODEC

G30 HDA_SDIN0 F30 HDA_SDIN1 E32 HDA_SDIN2 F32 HDA_SDIN3

IHDA

R2409

1

2 33R2J-2-GP

ACZ_SDATAOUT_R B29 HDA_SDO

ME_UNLOCK#

H32 HDA_DOCK_EN#/GPIO33 J30 HDA_DOCK_RST#/GPIO13

TPAD14-GP TP2404

1

TPAD14-GP TP2405

1

TPAD14-GP TP2406

1

TPAD14-GP TP2407

1

TPAD14-GP TP2408

1

PCH_JTAG_TCK PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_RST#

M3 JTAG_TCK K3 JTAG_TMS K1 JTAG_TDI J2 JTAG_TDO J4 TRST#

JTAG

PCH_SPI_CLK R2413 1

PCH_SPI_CS0# R2414 1

DY 1
R2415

PCH_SPI_DO

R2416 1

PCH_SPI_DI

2 15R2J-GP 2 15R2J-GP 2 0R2J-2-GP 2 15R2J-GP

SPI_CLK_R SPI_CS#0_R
SPI_CS1#
SPI_MOSI_R

BA2 SPI_CLK AV3 SPI_CS0# AY3 SPI_CS1#
AY1 SPI_MOSI AV1 SPI_MISO
IBEXPEAK-M-GP-NF

SPI

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

AK7 AK6 AK11 AK9

SATA_TXN0_C C2409 1 SATA_TXP0_C C2410 1

2 SCD01U50V2KX-1GP 2 SCD01U50V2KX-1GP

SATA1RXN SATA1RXP SATA1TXN SATA1TXP
SATA2RXN SATA2RXP SATA2TXN SATA2TXP
SATA3RXN SATA3RXP SATA3TXN SATA3TXP
SATA4RXN SATA4RXP SATA4TXN SATA4TXP
SATA5RXN SATA5RXP SATA5TXN SATA5TXP

AH6 AH5 AH9 AH8
AF11 AF9 AF7 AF6
AH3 AH1 AF3 AF1
AD9 AD8 AD6 AD5
AD3 AD1 AB3 AB1

SATA_TXN1_C C2405 1 SATA_TXP1_C C2406 1 SATA_TXN4_C C2407 1 SATA_TXP4_C C2408 1

2 SCD01U50V2KX-1GP 2 SCD01U50V2KX-1GP
2 SCD01U50V2KX-1GP 2 SCD01U50V2KX-1GP +1.05V_VTT

SATAICOMPO SATAICOMPI

AF16 AF15

R2412

SATAICOMP 1

2

37D4R2F-GP

+3.3V_RUN

SATA_RXN0_C SATA_RXP0_C SATA_TXN0 SATA_TXP0

HDD

SATA_RXN1_C SATA_RXP1_C SATA_TXN1 SATA_TXP1

ODD

C

SATA_RXN4_C SATA_RXP4_C SATA_TXN4 SATA_TXP4

ESATA

3

4

RN2401

SRN10KJ-5-GP

B

SATALED# T3

SATA_LED#

2

1

SATA0GP/GPIO21 Y9 SATA1GP/GPIO19 V1

SATA_DET#0_R SATA_DET#1_R

A

<Core Design>

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (SPI/RTC/LPC/SATA/IHDA)

Size

Document Number

Rev

Berry

X00

Date: Thursday, October 22, 2009

Sheet 24

of

92

5

4

3

2

1

5

4

3

2

1

SSID = PCH

U2001F

6 OF 10

SIO_EXT_SCI#

S_GPIO SIO_EXT_SCI#

Y3 BMBUSY#/GPIO0 C38 TACH1/GPIO1

CLKOUT_PCIE6N CLKOUT_PCIE6P

AH45 AH46

D SIO_EXT_W AKE#

PCH_GPIO6 SIO_EXT_W AKE#

D37 TACH2/GPIO6 J32 TACH3/GPIO7

CLKOUT_PCIE7N CLKOUT_PCIE7P

AF48 AF47

D

MISC

1

SIO_EXT_SMI#

SIO_EXT_SMI#

F10 GPIO8

DY C2501
SC47P50V2JN-3GP

2

PCH_GPIO12 HOST_ALTERT#1 DGPU_HOLD_RST# PCH_GPIO17

K9 LAN_PHY_PWR_CTRL/GPIO12 T7 GPIO15 AA2 SATA4GP/GPIO16 F38 TACH0/GPIO17

A20GATE U2

CLKOUT_BCLK0_N/CLKOUT_PCIE8N CLKOUT_BCLK0_P/CLKOUT_PCIE8P

AM3 AM1

BCLK_CPU_N BCLK_CPU_P

SIO_A20GATE +1.05V_VTT

2

PCH_GPIO22 PCH_GPIO37 PCH_GPIO36 PCH_GPIO48

RN2502
1 2 3 4 5

PCH_GPIO22

1

+3.3V_RUN

C2502 SC47P50V2JN-3GP

10

9

PCH_GPIO38

8 DGPU_HOLD_RST#

7

S_GPIO

6 PCH_TEMP_ALERT#_C

2

2

DY

TPAD14-GP TP2502

PCH_GPIO24 1 PCH_GPIO27
PCH_GPIO28 STP_PCI# CLK_SATA_OE# PCH_GPIO36

Y7 H10 AB12 V13 M11
V6 AB7

SCLOCK/GPIO22 GPIO24 GPIO27 GPIO28 STP_PCI#/GPIO34 SATACLKREQ#/GPIO35 SATA2GP/GPIO36

GPIO
CPU

PECI RCIN# PROCPWRGD THRMTRIP#

BG10 T1 BE10 BD10

TP1 BA22

H_PECI

SIO_RCIN#

H_PW RGD

PCH_THERMTRIP_R

1 R2506

R2504 56R2J-4-GP

1

2 54D9R2F-L1-GP

H_THERMTRIP#

Placed Within 2" from PCH

+3.3V_RUN

SRN10KJ-L3-GP

R2508 10KR2J-3-GP

PCH_GPIO37

AB13 SATA3GP/GPIO37

TP2 AW22

C

1

PCH_GPIO38

V3 SLOAD/GPIO38

TP3 BB22

C

PCH_GPIO39

P3 SDATAOUT0/GPIO39

TP4 AY45

PCH_GPIO45

H3 PCIECLKRQ6#/GPIO45

TP5 AY46

+3.3V_RUN

S3_RST_GATE#

1

2

C2503 SCD047U16V2KX-1-GP

PCH_GPIO48

F1 PCIECLKRQ7#/GPIO46 AB6 SDATAOUT1/GPIO48

TP6 AV43 TP7 AV45

PCH_GPIO39

4

STP_PCI#

3

SRN100KJ-6-GP

RN2503
1 2

PCH_TEMP_ALERT#

1 R2510

2 PCH_TEMP_ALERT#_C AA4

0R2J-2-GP

PCH_GPIO57

F8

SATA5GP/GPIO49 GPIO57

TP8 TP9 TP10

AF13 M18 N18

B

PCH_GPIO17 PCH_GPIO6 SIO_EXT_SCI# SIO_EXT_W AKE#

RN2504

1

8

2

7

3

6

4

5

SRN10KJ-6-GP

PCH_GPIO24

+3.3V_ALW

DY 2
R2515

1 100KR2J-1-GP

PCH_GPIO12 SIO_EXT_SMI# PCH_GPIO28 HOST_ALTERT#1

RN2501
1 2 3 4 5

10 9 S3_RST_GATE# 8 PCH_GPIO45 7 6 PCH_GPIO57

SRN10KJ-L3-GP

+3.3V_ALW

TPAD14-GP TP2503

1 PCH_NCTF_1

PCH_GPIO11

TPAD14-GP TP2504 TPAD14-GP TP2505

1 PCH_NCTF_2 1 PCH_NCTF_3

TPAD14-GP TP2507

1 PCH_NCTF_4

A4 A49
A5 A50 A52 A53
B2 B4 B52 B53 BE1 BE53 BF1 BF53 BH1 BH2 BH52 BH53 BJ1 BJ2 BJ4 BJ49 BJ5 BJ50 BJ52 BJ53 D1 D2 D53 E1 E53

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31

NCTF RSVD

TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 NC_1 NC_2 NC_3 NC_4 NC_5

AJ24 AK41 AK42 M32 N32 M30 N30 H12 AA23 AB45 AB38 AB42 AB41 T39

INIT3_3V# P6 TP24 C10

INIT3_3V#

1

TP2506TPAD14-GP

B

IBEXPEAK-M-GP-NF

A

<Core Design>

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (GPIO/CPU)

Size

Document Number

Rev

Berry

X00

Date: Thursday, October 22, 2009

Sheet 25

of

92

5

4

3

2

1

5

4

3

2

1

SSID = PCH

1 DIS 2
R2601 0R2J-2-GP

+3.3V_RUN

D

+1.05V_VTT
1.524A
C2602 SC10U6D3V5KX-1GP

2

1

2

1

C2601
DY SC1U10V2KX-1GP

+1.05V_VTT

U2001G

AB24 AB26 AB28 AD26 AD28 AF26 AF28 AF30 AF31 AH26 AH28 AH30 AH31 AJ30 AJ31

VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE

VCC CORE CRT

POWER

SC10U6D3V5MX-3GP SCD1U10V2KX-5GP SCD01U16V2KX-3GP

7 OF 10 VCCADAC VCCADAC VSSA_DAC VSSA_DAC

AE50 AE52 AF53 AF51

2

1

+VCCA_DAC_1_2 C2603
UMA

2

1

2

69mA

1

C2604

C2605

UMA

VCCALVDS VSSA_LVDS

AH38 AH39

+3VS_VCCA_LVD

D1IS 2
R2604 0R2J-2-GP

C2606
1 DY2

+3.3V_CRT_LDO

1 UMA 2

L2602

HCB1608KF-181-GP

1 UMA2
R2602 0R2J-2-GP

+3.3V_RUN

2 UMA1 300mA

R2603

0R3J-0-U-GP

+1.8V_RUN

D

AK24 VCCIO

TP2602

1 TPAD14-GP

VCCAPLLEXP

BJ24 VCCAPLLEXP

C

+1.05V_VTT
3.208A
C2614

1

1

1

C2615
UMA

C2616

C2617

UMA

C2618

1

1

2

2

2

2

2

SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP SC1U10V2KX-1GP
SC10U10V5KX-2GP

+3.3V_RUN
C2621 SCD1U10V2KX-4GP

1

AN20 AN22 AN23 AN24 AN26 AN28 BJ26 BJ28 AT26 AT28 AU26 AU28 AV26 AV28 AW26 AW28 BA26 BA28 BB26 BB28 BC26 BC28 BD26 BD28 BE26 BE28 BG26 BG28 BH27

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

2

AN30 AN31

VCCIO VCCIO

B

357mA AN35 VCC3_3

PCI E* DMI

HVCMOS LVDS

0R2J-2-GP

SCD01U16V2KX-3GP SCD01U16V2KX-3GP

VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS

AP43 AP45 AT46 AT45

SCD1U10V2KX-5GP +1.8VS_VCCTX_LVDS

1 UMA2 59mA

L2603

0R5J-5-GP

1

1

1

2

R2605

C2607

C2608

DIS

2

UMA

2

2

DY C2609 SC10U6D3V5MX-3GP
UMA

3.3V CRT LDO

1

2

VCC3_3 VCC3_3 VCC3_3

AB34 AB35 AD35

1

+3.3V_RUN
357mA
C2611 SCD1U10V2KX-5GP

+5V_RUN

U2601

+3.3V_CRT_LDO

DY 3
2 1

VIN GND EN

VOUT 4 NC#5 5

1

1

C2612 DY

RT9198-33PBG-GP

C2613 DY

C

SC1U10V2KX-1GP

SC1U10V2KX-1GP

2

2

Second 74.09091.H3F

VCCVRM AT24

35mA

+1.8V_RUN

VCCDMI VCCDMI

AT16 AU16

VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND

AM16 AK16 AK20 AK19 AK15 AK13 AM12 AM13 AM15

2

1

2

1

61mA +1.05VS_VCC_DMI R2606 0R2J-2-GP

1

2

C2619

SC1U6D3V2KX-GP
156mA

+V_NVRAM_VCCQ

C2620 SCD1U10V2KX-5GP

+1.05V_VTT

2

1

+1.8V_RUN
R2607 0R2J-2-GP

2

1

+3.3V_RUN
DY R2608 0R2J-2-GP

+3.3V_RUN

B

1

FDI NAND / SPI

+1.05V_VTT

TP2601

VCCAFDI_VRM 1 VCCFDIPLL TPAD14-GP

AT22 BJ18 AM23

VCCVRM[1] VCCFDIPLL VCCIO

IBEXPEAK-M-GP-NF

VCCME3_3 VCCME3_3 VCCME3_3 VCCME3_3

AM8 AM9 AP11 AP9

1

85mA
PCH_VCCME3_3 C2623 SCD1U10V2KX-5GP

2

R2609 0R2J-2-GP

2

A 5

VCCAFDI_VRM

0924 SA
R2610

1

2

0R2J-2-GP

+1.8V_RUN

4

3

<Core Design>

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (POWER1)

Size

Document Number

Rev

Berry

X00

Date: Thursday, October 22, 2009

Sheet 26

of

92

2

1

5

4

3

2

1

U2001J

POWER

10 OF 10

+1.05V_VTT

SSID = PCH

TP2701

1 VCCACLK TPAD14-GP

AP51 AP53

VCCACLK VCCACLK

AF23 VCCLAN AF24 VCCLAN D

DCPSUSBYP

Y20 DCPSUSBYP

1

C2703 SCD1U10V2KX-4GP

AD38 VCCME

2

AD39 VCCME

+1.05V_VTT
1.998A
C2707
SC10U10V5KX-2GP

1

1

C2704
DY

2

2

2

1

C2708

AD41 AF43 AF41 AF42
V39

VCCME VCCME VCCME VCCME VCCME

SC10U6D3V5MX-3GP

SC1U10V2KX-1GP

V41 VCCME

V42 VCCME

1

Y39 VCCME

+1.05V_VTT

L2702

DY C2710
SC1U10V2KX-1GP

Y41 VCCME

2

1

2

IND-10UH-218-GP

+1.05VS_VCCA_A_DPL

Y42 VCCME

1

1

C

C2712

2

DY C2711
SC10U6D3V5MX-3GP

SC1U10V2KX-1GP

2

+VCCRTCEXT

V9 DCPRTC

1

L2703

C2714 SCD1U10V2KX-4GP

+1.8V_RUN

2

1

2

+1.05VS_VCCA_B_DPL

IND-10UH-218-GP

1

1

C2717

DY C2716
SC10U6D3V5MX-3GP

SC1U10V2KX-1GP

72mA +1.05VS_VCCA_A_DPL

AU24 VCCVRM

BB51 BB53

VCCADPLLA VCCADPLLA

2

2

73mA +1.05VS_VCCA_B_DPL

BD51 BD53

VCCADPLLB VCCADPLLB

+1.05V_VTT

AH23 AJ35 AH35

VCCIO VCCIO VCCIO

1

1

1

2

C2720

C2721

C2722

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

2

2

AF34 AH34

VCCIO VCCIO

AF32 VCCIO

V12 DCPSST

+VCCSST B

1

C2725 SCD1U10V2KX-4GP

2

1

+1.05VALW _INT_VCCSUS
C2726 SCD1U10V2KX-4GP

Y22 DCPSUS

2

P18 VCCSUS3_3

+3.3V_ALW

163mA

U19 VCCSUS3_3 U20 VCCSUS3_3

1

C2728 SCD1U10V2KX-4GP

+3.3V_RUN

U22 VCCSUS3_3

2

+1.05V_VTT

1mA
C2730 SC10U6D3V5KX-1GP

1

C2729 SCD1U10V2KX-4GP

2

1

1

C2731

C2732

1

V15 VCC3_3 V16 VCC3_3 Y16 VCC3_3
AT18 V_CPU_IO AU18 V_CPU_IO

2

2

2

A

+RTC_CELL
2mA

1

1

C2734

C2735

A12 VCCRTC IBEXPEAK-M-GP-NF

RTC CPU HDA

PCI/GPIO/LPC SATA

Clock and Miscellaneous

PCI/GPIO/LPC

USB

VCCIO VCCIO VCCIO VCCIO

V24 V26 Y24 Y26

1

C2705
DYSC1U10V2KX-1GP

2

VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3

V28 U28 U26 U24 P28 P26 N28 N26 M28 M26 L28 L26 J28 J26 H28 H26 G28 G26 F28 F26 E28 E26 C28 C26 B27 A28 A26

2

1

+3.3V_ALW
C2706 SCD1U10V2KX-4GP

+3.3V_ALW

+3.3V_ALW

2

C2709 SCD1U10V2KX-4GP

D2701 CH751H-40PT-GP

1

2

+3.3V_RUN

D

2

1

VCCSUS3_3 U23

+1.05V_VTT

VCCIO V23 V5REF_SUS F24
V5REF K49 VCC3_3 J38 VCC3_3 L38

+5VALW _PCH_VCC5REFSUS
change 1uF
+5VS_PCH_VCC5REF

2

1

1 R2702 C2713 SC1U10V2KX-1GP
DG update 1.62

+3.3V_RUN

2

1

+5V_ALW 2 10R2J-2-GP
C2715 SC1U10V2KX-1GP

1

D2702 CH751H-40PT-GP
C

1 R2701

+5V_RUN 2 10R2J-2-GP

VCC3_3 M36

1

VCC3_3 N36

VCC3_3 P36 VCC3_3 U35

2

C2718 SCD1U10V2KX-4GP

C2719

1

2

+3.3V_RUN

VCC3_3 AD13

SCD1U10V2KX-4GP

VCCSATAPLL VCCSATAPLL

AK3 AK1

VCCSATAPLL

1

TPAD14-GP

TP2702

VCCIO AH22 VCCVRM AT20

+1.8V_RUN

VCCIO
VCCIO
VCCIO
VCCIO VCCIO VCCIO VCCIO
VCCIO VCCIO VCCIO VCCIO
VCCME VCCME VCCME VCCME
VCCSUSHDA

AH19
AD20
AF22
AD19 AF20 AF19 AH20
AB19 AB20 AB22 AD22
AA34 Y34 Y35 AA35
L30

R2703

+VCCSUSHDA 1

2

1

0R2J-2-GP
C2733 SC1U10V2KX-1GP

+1.05V_VTT

6mA

+3.3V_ALW

2

1

+1.05V_VTT

B

C2727 SC1U10V2KX-1GP

<Core Design>

A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

SCD1U16V2KX-3GP SCD1U10V2KX-4GP SCD1U16V2KX-3GP SCD1U10V2KX-4GP

2

Title

2

2

PCH (POWER2)

Size

Document Number

Rev

Berry

X00

Date: Thursday, October 22, 2009

Sheet 27

of

92

5

4

3

2

1

5

4

SSID = PCH

D

U2001H

8 OF 10

AB16 VSS

C B

AA19 AA20 AA22 AM19 AA24 AA26 AA28 AA30 AA31 AA32 AB11 AB15 AB23 AB30 AB31 AB32 AB39 AB43 AB47
AB5 AB8 AC2 AC52 AD11 AD12 AD16 AD23 AD30 AD31 AD32 AD34 AU22 AD42 AD46 AD49 AD7 AE2 AE4 AF12 Y13 AH49 AU4 AF35 AP13 AN34 AF45 AF46 AF49 AF5 AF8 AG2 AG52 AH11 AH15 AH16 AH24 AH32 AV18 AH43 AH47 AH7 AJ19 AJ2 AJ20 AJ22 AJ23 AJ26 AJ28 AJ32 AJ34 AT5 AJ4 AK12 AM41 AN19 AK26 AK22 AK23 AK28

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AK30 AK31 AK32 AK34 AK35 AK38 AK43 AK46 AK49 AK5 AK8 AL2 AL52 AM11 BB44 AD24 AM20 AM22 AM24 AM26 AM28 BA42 AM30 AM31 AM32 AM34 AM35 AM38 AM39 AM42 AU20 AM46 AV22 AM49 AM7 AA50 BB10 AN32 AN50 AN52 AP12 AP42 AP46 AP49 AP5 AP8 AR2 AR52 AT11 BA12 AH48 AT32 AT36 AT41 AT47 AT7 AV12 AV16 AV20 AV24 AV30 AV34 AV38 AV42 AV46 AV49 AV5 AV8 AW14 AW18 AW2 BF9 AW32 AW36 AW40 AW52 AY11 AY43 AY47

IBEXPEAK-M-GP-NF

A

5

4

3

U2001I

AY7 B11 B15 B19 B23 B31 B35 B39 B43 B47
B7 BG12 BB12 BB16 BB20 BB24 BB30 BB34 BB38 BB42 BB49
BB5 BC10 BC14 BC18
BC2 BC22 BC32 BC36 BC40 BC44 BC52
BH9 BD48 BD49
BD5 BE12 BE16 BE20 BE24 BE30 BE34 BE38 BE42 BE46 BE48 BE50
BE6 BE8 BF3 BF49 BF51 BG18 BG24 BG4 BG50 BH11 BH15 BH19 BH23 BH31 BH35 BH39 BH43 BH47 BH7 C12 C50 D51 E12 E16 E20 E24 E30 E34 E38 E42 E46 E48
E6 E8 F49 F5 G10 G14 G18 G2 G22 G32 G36 G40 G44 G52 AF39 H16 H20 H30 H34 H38 H42

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

IBEXPEAK-M-GP-NF

3

9 OF 10
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H49 H5 J24 K11 K43 K47 K7 L14 L18 L2 L22 L32 L36 L40 L52 M12 M16 M20 N38 M34 M38 M42 M46 M49 M5 M8 N24 P11 AD15 P22 P30 P32 P34 P42 P45 P47 R2 R52 T12 T41 T46 T49 T5 T8 U30 U31 U32 U34 P38 V11 P16 V19 V20 V22 V30 V31 V32 V34 V35 V38 V43 V45 V46 V47 V49 V5 V7 V8 W2 W52 Y11 Y12 Y15 Y19 Y23 Y28 Y30 Y31 Y32 Y38 Y43 Y46 P49 Y5 Y6 Y8 P24 T43 AD51 AT8 AD47 Y47 AT12 AM6 AT13 AM5 AK45 AK39 AV14

2

1

D

C

B

<Core Design>

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

PCH (VSS)

Size

Document Number

Rev

Berry

X00

Date: W ednesday, October 14, 2009

Sheet 28

of

92

2

1

5

4

3

2

1

SSID = AUDIO

C3005 SCD1U10V2KX-4GP

+AVDD

+5V_RUN

D

+3.3V_RUN

D

+3.3V_RUN

Close to codec

R3002

1

2

Close to codec

AUD_DVDDCORE

1

C3006

0R3J-0-U-GP

+PVDD

+5V_RUN

1

1

1

1

2

C3001 SC10U6D3V5MX-3GP

2

SC1U10V2KX-1GP

1

2

2

U3001

2

R3003 0R3J-0-U-GP

C3010 SC10U6D3V5MX-3GP

1

C3009 SC1U10V2KX-1GP

1

C3008 SCD1U10V2KX-4GP

C3004 SCD1U10V2KX-4GP

2

C3003 SC1U6D3V2KX-GP

2

C3002 SCD1U10V2KX-4GP

1

1

PCH_AZ_CODEC_BITCLK

1 DVDD_CORE 9 DVDD 3 DVDD_IO

AVDD AVDD

27 38

PVDD PVDD

39 45

AUD_AGND

2

2

2

1 R3004

2 0R3J-0-U-GP

1

2

DY C3007 SC4D7P50V2CN-1GP +3.3V_RUN

PCH_AZ_CODEC_BITCLK PCH_SDIN_CODEC PCH_SDOUT_CODEC
PCH_AZ_CODEC_SYNC PCH_AZ_CODEC_RST#

R3001 1

2 33R2J-2-GP

PCH_AZ_CODEC_BITCLK 6 HDA_BITCLK

PCH_SDIN_CODEC_C0

8 HDA_SDI

PCH_SDOUT_CODEC

5 HDA_SDO

PCH_AZ_CODEC_SYNC

10 HDA_SYNC

PCH_AZ_CODEC_RST#

11 HDA_RST#

SENSE_A SENSE_B

13 14

HP0_PORT_A_L HP0_PORT_A_R VREFOUT_A_OR_F

28 29 23

HP1_PORT_B_L HP1_PORT_B_R

31 32

AUD_SENSE_A AUD_SENSE_B

AUD_EXT_MIC_L AUD_EXT_MIC_R AUD_VREFOUT_B
AUD_HP1_JACK_L AUD_HP1_JACK_R

C3021 2 C3022 2

1SC1U10V2KX-1GP 1SC1U10V2KX-1GP

close to audio jack

R3005 1 R3006 1

2 60D4R2F-GP 2 60D4R2F-GP

AUD_AGND
MIC_IN_L MIC_IN_R
AUD_VREFOUT_B
AUD_HP1_JACK_L2 AUD_HP1_JACK_R2

R3008 10KR2J-3-GP
C AMP_MUTE#

2

1

TPAD14-GP TP3001

1

TPAD14-GP TP3002

1

AUD_DMIC_CLK AUD_DMIC_IN0

2 4
46
48

PORT_C_L

PORT_C_R

VREFOUT_C

DMIC_CLK/GPIO1

DMIC0/GPIO2

SPKR_PORT_D_L+

SPKR_PORT_D_L-

DMIC1/GPIO0/SPDIF_OUT_1

SPKR_PORT_D_R-

SPDIF_OUT_0

SPKR_PORT_D_R+

19 20 24
40 41
43 44

AUD_INT_MIC_R_L
AUD_VREFOUT_C
AUD_SPK_L+ AUD_SPK_L-
AUD_SPK_RAUD_SPK_R+

1 C3011
1 R3007

2 SC1U6D3V2KX-GP 2
4K7R2J-2-GP

AUD_SPK_L+ AUD_SPK_L-

AUD_SPK_RAUD_SPK_R+

INT_MIC_L_R

Check

R3009

C3012

120KR2J-L-GP

2

1 SCD1U10V2KX-4GP SB_SPKR_R 1

2

2

1 SCD1U10V2KX-4GP KBC_BEEP_R 1

2

R3010

From SB
ACZ_SPKR KBC_BEEP

C

2

AUD_VREFOUT_B

AMP_MUTE#

1

AMP_MUTE# PUMP_CAPN

47 EAPD 35 CAP-

PORT_E_L PORT_E_R

15 16

PORT_F_L PORT_F_R

17 18

AUD_PC_BEEP

C3013 G3001
DUMMY-C2

470KR2J-2-GP From EC

1

1

C3023 SC1U10V2KX-1GP

C3014 SC2D2U25V5KX-1GP

2

PUMP_CAPP

36 CAP+ 7 DVSS

PC_BEEP 12 MONO_OUT 25

AUD_PC_BEEP Trace width>15 mils

2

33 30 26

AVSS AVSS AVSS

CAP2 22 VREFFILT 21

AUD_CAP2 AUD_VREFFLT

Possible to remove for new IC

42 PVSS

V- 34

AUD_V_B

49 GND

VREG 37

AUD_VREG

92HD81B1A5NLGXUAX8-GP

C3017

C3016 SC1U6D3V2KX-GP

1

C3015 SC10U6D3V5MX-3GP

1

C3018 SC10U6D3V5MX-3GP

1

1

AUD_AGND

2

2

2

2

X01 will change to 92HD79B1

P/N:71.92H79.003

AUD_AGND AUD_AGND AUD_AGND AUD_AGND

Azalia I/F EMI
B PCH_SDOUT_CODEC

Close to codec B

1

SC4D7U6D3V3KX-GP PCH_AZ_CODEC_SDOUT1

2

1

2

R3015
DY 47R2J-2-GP
DY C3020 SCD1U10V2KX-4GP

1

+AVDD
R3018 2K49R2F-GP

R3016

20KR2F-L-GP

1

2

2

AUD_SENSE_A

1

C3019 SC1000P50V3JN-GP-U

R3022

39K2R2F-L-GP

2

1

2

AUD_AGND

Close to Pin13

AUD_HP1_JD# EXT_MIC_JD#

+AVDD

1

AUD_SENSE_B

12

R3019 2K49R2F-GP
R3021 20KR2F-L-GP

2

AUD_AGND
Close to Pin14

R3014

2

1

0R3J-0-U-GP

R3017

2

1

0R3J-0-U-GP

R3020

2

1

0R3J-0-U-GP

AUD_AGND

A

A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Audio Codec 92HD81B1

Size

Document Number

Rev

Custom Berry

X00

Date: Thursday, October 22, 2009

Sheet 30

of

92

5

4

3

2

1

5

4

3

2

1

+KBC_PW R

10 mW solution remove

R3701

2

1

0R2J-2-GP

2 L3701

1 0R3J-0-U-GP

+3.3V_RTC_LDO

1

1

1

1

1

1

1

DY

1

CAP close to VCC-GND pin pair
VBAT

+3.3V_RUN

1

1

C3702 SCD1U10V2KX-4GP

2

2

DY C3703 SC2D2U10V3KX-1GP THERM_SDA

+3.3V_RUN

Q2302

4

3

5

2

KBC_SDA1

1

SSID = KBC
+KBC_PW R
Madison
R3705 2K2R2J-2-GP

C3710 SCD1U10V2KX-4GP

AVCC 102 VDD 4
GPIO41 80

115 88 76 46 19

2

C3709 SC2D2U10V3KX-1GP

C3708 SCD1U10V2KX-4GP

C3707 SCD1U10V2KX-4GP

C3706 SCD1U10V2KX-4GP

C3705 SCD1U10V2KX-4GP

C3704 SCD1U10V2KX-4GP

2

2

2

2

2

2

C3701 SC2D2U10V3KX-1GP

2

D

U3701A

VCC VCC VCC VCC VCC

AD_IA

TP3704

1

THERMTRIP_VGA# PSID_EC

KBC_GPIO91
DISCRETE_ID KBC_THERMTRIP#

104 VREF

97 98 99 100 108 96

GPI90/AD0 GPI91/AD1 GPI92/AD2 GPI93/AD3 GPIO05 GPIO04

A/D

SUS_PW R_DN_ACK 3.3V_RUN_VGA_EN
PH for Discrete Internal PL for UMA

TP3703 PM_SLP_S3#

C

+KBC_PW R

R3715

LID_CLOSE#

2 DIS 1 2K2R2J-2-GP

1.0V_RUN_VGA_EN

PLTRST_DELAY#
3V_5V_POK PM_PW ROK EC_SPI_W P#_R

PW RLED# PW R_BTN_LED# W HITE_LED#_KBC
AD_OFF PCH_RSMRST#
PM_SLP_S4#

BLON_OUT IMVP_VR_ON PSID_DISABLE# GFX_CORE_EN ME_UNLOCK#

USB_PW R_EN#

1

KBC_GPIO96 PCB_VER2

101 105 106 107

GPI94 GPI95 GPI96 GPI97

D/A

KBC_PWRBTN_EC# AC_IN#_KBC PCB_VER0 KBC_BIOS_ID PCB_VER1
EC_ENABLE#

64 95 93 94 119
6 109 120
65 66 16 17 20 21 22 23 24 25 26 27 28 73 74 75 110

GPIO01/TB2 GPIO03 GPIO06 GPIO07 GPIO23 GPIO24 GPIO30 GPIO31 GPIO32/D_PWM GPIO33/H_PWM GPIO40/F_PWM GPIO42/TCK GPIO43/TMS GPIO44/TDI GPIO45/E_PWM GPIO46/TRST# GPIO47 GPIO50/TDO GPIO51 GPIO52/RDY# GPIO53 GPIO70 GPIO71 GPIO72 GPO82/TRIS#

GPIO

+3.3V_RUN

1 OF 2

LPC

GPIO10/LPCPD# LRESET# LCLK LFRAME# LAD0 LAD1 LAD2 LAD3 SERIRQ
GPIO11/CLKRUN# KBRST# GA20
ECSCI#/GPIO54 GPIO65/SMI#
GPIO67/PWUREQ#

124 7 2 3 126 127 128 1 125 8 122 121 29 9 123

SMB

GPIO74/SDA2 GPIO73/SCL2 GPIO22/SDA1 GPIO17/SCL1

68 67 69 70

SP

GPIO66/G_PWM 81

BAT_IN#

PLT_RST1#_1

PCH_TEMP_ALERT#

LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3

PCLK_KBC LPC_LFRAME#
LPC_LAD[0..3]

ECSCI#_KBC

INT_SERIRQ PM_CLKRUN# SIO_RCIN# SIO_A20GATE

ECSW I#_KBC

PANEL_BLEN

1 UMA 2

R3714

10KR2F-2-GP

KBC_SDA1 KBC_SCL1 BAT_SDA BAT_SCL

1.8V_VGA_RUN_EN

KBC_SCL1

6

1

2N7002EDW -GP
84.27002.F3F

+1.05V_VTT

THERM_SCL

2

DISCRETE_ID
For 512MB/1GB VRAM option
+3.3V_RUN

1

H_THERMTRIP# SIO_EXT_W AKE#

R3710 2K2R2J-2-GP

12

C3711

DY H_THERMTRIP_R# 2

1

SCD1U16V2KX-3GP

2

3 KBC_THERMTRIP#

Q3705

PMBS3904-1-GP

D3701 1
3
2

ECSW I#_KBC

E51_RxD

DY 1
R3711

2 10KR2J-3-GP

THERMTRIP_VGA# BAT_SCL BAT_SDA ECRST#
KB_DET# LCD_CBL_DET#

RN3701

5

4

6

3

7

2

8

1

SRN4K7J-10-GP

RN3703

3

2

4

1

+KBC_PW R
DY

2

1

SPI

GPIO77 GPIO76/SHBM
GPIO75 GPIO81

84 83 82 91

ECSMI#_KBC

BLUETOOTH_EN W IFI_RF_EN W W AN_RADIO_DIS#

SIO_EXT_SCI#

GPO83/SOUT_CR/BADDR1 GPIO87/SIN_CR GPO84/BADDR0

SER/IR

GPIO16 GPIO34 GPIO36

111

E51_TxD

113

E51_RxD

112

AC_PRESENT_EC

114

14 1.5CPU_1.05VTT_PWRGD_KBC 1

15

S5_ENABLE

R3723

2 0R2J-2-GP

VCORF 44

1

KBC_VCORF
C3712 SC1U6D3V2KX-GP

PM_LAN_ENABLE 1.5CPU_1.05VTT_PW RGD
SIO_EXT_SMI#

BAS16PT-GP

D3704 1
3

ECSCI#_KBC

2

BAS16PT-GP

D3705 1
3
2 BAS16PT-GP

ECSMI#_KBC

SRN100KJ-6-GP

KBC_THERMTRIP#

2

1

AC_IN#_KBC

R2516 2

1 100KR2J-1-GP

R2517

100KR2J-1-GP

X01 change location

BLUETOOTH_EN R3712 1

S5_ENABLE

R3713 1

IMVP_VR_ON

R3717 1

2 10KR2J-3-GP 2 10KR2J-3-GP 2 10KR2J-3-GP

EC3701 SCD1U16V2KX-3GP

20090702 Update 10mW circuit

1 R3703

DY
2 KBC_PWRBTN_EC# 0R2J-2-GP

KBC_PW RBTN#

KBC_PW RBTN#

3

D3702

BAT54C-U-GP

1

+KBC_PW R

R3704

2

1

100KR2J-1-GP

+3.3V_RTC_LDO

+3.3V_RTC_LDO

0707

2

R3706 10KR2J-3-GP

2

S

AC_IN#_KBC +KBC_PW R

R3708
1 DY 2
0R2J-2-GP

KBC_ON#

G

1

D3703 BAT54C-U-GP

1

D

Q3703

D

SI2301CDS-T1-GE3-GP

+KBC_PW R

20090714
EC_ENABLE#

3

2

Q3704 G
S

. . ...

D

KBC_ON#

AC_IN#

2N7002E-1-GP
84.2N702.D31

+KBC_PW R

2

PURE_HW _SHUTDOW N#

1

R3722 10KR2J-3-GP
+3.3V_RUN

SIO_A20GATE SIO_RCIN#

RN3702

2

3

1

4

SRN10KJ-5-GP

C

GND GND GND GND GND GND

2

NPCE781BA0DX-GP

Vendor recomment FW can do it

Vendor recomment can remove

103 AGND

116 89 78 45 18 5

1

1

1

10KR2J-3-GP R3729
10KR2J-3-GP R3728

R3727
DY 10KR2J-3-GP

DY

DY

MB VERSION ID

U3701B

2 OF 2

2

2

2

KCOL[0..16]

10KR2J-3-GP R3733
10KR2J-3-GP R3732

PCB_VER0 PCB_VER1 PCB_VER2
R3731 10KR2J-3-GP

1

1

1

X00 X01 X02 A00

VER2 VER1
00 00 01 01

VER0
0 1 0 1

2

2

2

B

VGA STRAP option

GPIO24 GPIO5

UMA

0

0

Madisan

1

1

Park

1

0

Reserved 0

1

For EMI

THERMTRIP_VGA_GATE

PCH_SUSCLK_KBC

77

+KBC_PW R

DY R3737 1
AMP_MUTE#

IMVP_PW RGD PM_PW RBTN#
LCD_TST_EN KBC_BEEP
AMBER_LED#_KBC
TP3705

2TOURBO_BOOST 79 10KR2J-3-GP 30

63

117

31

32

118

1BRIGHTNESS

62

KB_DET#

DIS

LCD_CBL_DET#

2

1

R3746

0R2J-2-GP

13

12

THERMTRIP_VGA_GATE_C

11

LCD_TST

10

TPDATA

71

TPCLK

72

EC_SPI_DI EC_SPI_DO EC_SPI_CS# EC_SPI_CLK

1 R3745
R3734 1

2 33R2J-2-GP
2 33R2J-2-GP

86 EC_SPI_DO_C 87
90 EC_SPI_CLK_C 92

32KX1/32KCLKIN

KBSOUT0/JENK#

KBSOUT1/TCK

KBSOUT2/TMS

KBSOUT3/TDI

32KX2

KBSOUT4/JEN0#

GPIO55/CLKOUT

KBSOUT5/TDO

KBSOUT6/RDY#

GPIO14/TB1 GPIO20/TA2

KBC

KBSOUT7 KBSOUT8

GPIO56/TA1

KBSOUT9

GPIO15/A_PWM

KBSOUT10

GPIO21/B_PWM

KBSOUT11

GPIO13/C_PWM

KBSOUT12/GPIO64

KBSOUT13/GPIO63

KBSOUT14/GPIO62

KBSOUT15/GPIO61/XOR_OUT

GPIO12/PSDAT3

GPIO60/KBSOUT16

GPIO25/PSCLK3

GPIO57/KBSOUT17

GPIO27/PSDAT2

GPIO26/PSCLK2

PS/2 GPIO35/PSDAT1
GPIO37/PSCLK1

KBSIN0 KBSIN1

KBSIN2

KBSIN3

KBSIN4

F_SDI

KBSIN5

F_SDO F_CS0#

FIU

KBSIN6 KBSIN7

F_SCK

53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33
54 55 56 57 58 59 60 61

KCOL0 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16 KCOL17 1
KROW 0 KROW 1 KROW 2 KROW 3 KROW 4 KROW 5 KROW 6 KROW 7

TP3708 TPAD14-GP
KROW [0..7]

B

VCC_POR# 85

ECRST#

2

PM_PW ROK

PCLK_KBC

1

1

EC3702

EC3703

DY DY SC470P50V2JN-GP

SC470P50V2JN-GP

2

PURE_HW _SHUTDOW N#

NPCE781BA0DX-GP

ECRST#

1

1
Q3701 PMBS3906-GP

3

2

2

DY C3716 SC1U6D3V2KX-GP

PLT_RST#

2 R3716

1 0R2J-2-GP

PLT_RST1#_1

1

C3714
DY SC470P50V2JN-GP

2

A

A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

KBC Nuvoton NPCE781BA0DX

Size

Document Number

Rev

A2

Berry

X00

Date: Thursday, October 22, 2009

Sheet 37

of

92

5

4

3

2

1

5

4

3

2

1

SSID = Thermal

+5V_RUN

+3.3V_RUN

1

1

1

C3902 SC10U6D3V5MX-3GP

C3901 SCD1U16V2KX-3GP

R3901 10KR2J-3-GP

2

2

2

1. Place near CPU PWM CORE and PCH.

+3.3V_RUN

EMC2102_FAN_TACH

EMC2102_FAN_TACH

D

Layout notice :

R3902

D

Both DN1 and DP1 routing 10 mil trace width and 10 mil spacing.

49D9R2F-GP

2

1 EMC2102_VDD_3D3

EMC2102_FAN_DRIVE

EMC2102_FAN_DRIVE

3

C3905 must be near Q3901

1

2

Q3901 PMBS3904-1-GP

2

C3904

1

DY SC470P50V2JN-GP

2

1

near EMC2102
C3905 SC470P50V2JN-GP

C3903 SCD1U16V2KX-3GP

1

2

THERM_SCL THERM_SDA

THERM_SCL THERM_SDA

RN3901

3

2

4

1

+3.3V_RUN

UMA

2

EMC2102_DN2_UMA

1

C3906

1

DY SC470P50V2JN-GP

U3901

GND 29 TACH 28 VDD_5Va 27 FANa 26 FANb 25 VDD_5Vb 24 SMCLK 23 SMDATA 22

THERM_POWER_OK# THERMTRIP#

SRN4K7J-8-GP

SRN10KJ-5-GP

3

2

4

1

RN3902

2

Q3902 PMBS3904-1-GP

3

EMC2102_DP2_UMA

2

1 VDD_3V

NC#21 21

0R2J-2-GP

2. System Sensor(UMA Only)

2

R3903
UMA

EMC2102_DN1

2 DN1

GND 20

0R2J-2-GP

R3904

Layout notice :

UMA

Both DN2 and DP2 routing 10 mil

1

EMC2102_DP1 EMC2102_DN2

3 DP1 4 DN2

EMC2102

ALERT# 19 CLK_IN 18

CLK_32K

+3.3V_RUN

C

trace width and 10 mil spacing.

1

C

Reserved DISCRETE

EMC2102_DP2

5 DP2

CLK_SEL 17 EMC2102_CLK_SEL

1 R3905

2 0R2J-2-GP

VGA_THERMDC

DIS

1

2

R3906 0R2J-2-GP

1

C3907 SC470P50V2JN-GP

EMC2102_DN3 EMC2102_DP3

6 DN3 7 DP3

RESET# 16 NC#15 15

EM2102_RESET# 1

TP3901

GND = Internal Oscillator Selected +3.3V = External 32.768kHz Clock Selected

8 NC#8 9 SHDN_SEL 10 FAN_MODE 11 TRIP_SET 12 SYS_SHDN# 13 THERMTRIP# 14 POWER_OK#

2

VGA_THERMDA

DIS

1

2

R3907 0R2J-2-GP

3.VGA Sensor(DISCRETE Only)
Layout notice : Both VGA_THERMDA and VGA_THERMDC routing 10 mil trace width and 10 mil spacing.

C3907 must be near Q3902

1

1

2

Q3903 PMBS3904-1-GP

2

C3908

1

DY SC470P50V2JN-GP

3

B

4.HW T8 sensor

2

C3909 SC470P50V2JN-GP
C63 must be near EMC2102

Layout notice : Both DN3 and DP3 routing 10 mil trace width and 10 mil spacing.

GND = Channel 1 OPEN = Channel 3 +3.3V = Disabled

R3908
2 DY 1

EMC2102_SHDN

10KR2J-3-GP

+3.3V_RUN

R3909
2 DY 1

EMC2102_FAN_mode

10KR2J-3-GP

R3911

1

2

0R2J-2-GP
GND = Fan is OFF OPEN = Fan is at 60% full-scale +3.3V = Fan is at 75% full-scale

THERM_SYS_SHDN#

Main G7922R61U for GMT P/N:74.07922.0B3 EMC2102-DZK-GP SEC. EMC2102 for SMSC P/N:74.02102.A73
THERM_POWER_OK# THERMTRIP#

+3.3V_RUN

Q3904 G

. . ...

D

S

2N7002E-1-GP
84.2N702.D31

PURE_HW_SHUTDOWN#

+3.3V_RUN

C3910 SCD1U16V2KX-3GP
V_DEGREE

2

1

2

1

B
R3913 10KR2F-2-GP
TRIP_SET Pin Voltage V_DEGREE=(((Degree-75)/21)

1

1

G D
S

PCH_SUSCLK_2102

. . ...

32K suspend clock output
Q3905 2N7002E-1-GP
84.2N702.D31

C3911 SCD1U16V2KX-3GP

2

2

R3914 2K37R2F-GP
T8 shutdown is set 88 deg-C.

RUN_ENABLE

CLK_32K_R

R3915

1

2

10R2J-2-GP

CLK_32K

1

A

DY C3913 SC4D7P50V2CN-1GP

2

5

4

3

<Core Design>

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Thermal/Fan Controllor EMC2102

Size

Document Number

Rev

Custom

Berry

X00

Date: Thursday, October 22, 2009

Sheet 39

of

92

2

1

5

4

3

2

1

SSID = Reset.Suspend

H_THERMTRIP#

E

H_PW RGD

R4201
1 DY 2

H_PW RGD_R

DY B Q4201

1

1KR2J-1-GP

C4202

DY SCD1U10V2KX-4GP BAS16PT-GP

C

CHT2222APT-GP

2

D

2

D

3V_5V_EN

1

DY

1 D4201 1
R4203

3 2
1KR2J-1-GP

PURE_HW _SHUTDOW N# S5_ENABLE

R4202 200KR2J-L1-GP

2

Run Power

+15V_ALW

AO4468 MAX 9A Rds(on) = 18.5mOhm

+5V_RUN

+5V_ALW

+5V_RUN

2

U4201

5D

G4

R4204

6D

S3

+5V_RUN Comsumption

C

100KR2J-1-GP

7D

S2

8D

S1

Peak current 7.73A

C

1

1

+3.3V_RTC_LDO

100KR2J-1-GP

R4207

1

2 PS_S3CNTRL

PS_S3CNTRL

2

R4205

1

2

10KR2J-3-GP

5V_RUN_ENABLE

SI4800BDY-T1-GP

1

C4201 84.04800.D37
SC6800P25V2KX-1GP

2

C4203 SC10U6D3V5KX-1GP

DGS

+3.3V_RUN

4

5

6

PM_SLP_S3# RUN_ENABLE

1

2

3

Q4202 2N7002EDW -GP
84.27002.F3F
SGD
RUN_ENABLE

2

R4211

1

2

AO4468 MAX 11.6A Rds(on) = 18.5mOhm

+3.3V_ALW

+3.3V_RUN

U4202

5D

G4

6D

S3

7D

S2

8D

S1

1

3.3V_RUN_ENABLE

SI4800BDY-T1-GP

C4205 SC10U6D3V5KX-1GP

+3.3V_RUN Comsumption Peak current 8.14A

1

B

10KR2J-3-GP

C4207 84.04800.D37

B

SCD01U50V2KX-1GP

2

2

+1.5V_RUN_CPU

S3 Power Reduction

1

R4213
DY 220R2J-L2-GP

2

+1.5V_SUS
R4214 1 0R5J-5-GP R4219 1 0R5J-5-GP

+1.5V_RUN

1

MAX Current 3000 mA Design Current 2100 mA

+1.5V_RUN_CPU

+1.5V_RUN

2

1 DY 2

R4215

0R5J-5-GP

2

DY 1
R4220

2 0R5J-5-GP

1.5V_RUN for VGA Comsumption Peak current 7.39A
+1.5V_RUN_CPU Comsumption Peak current 3A
+1.5V_RUN for Mini-Card Comsumption Peak current 1A
Total= 11.39A

DISCHARGE_1D5V_CPU_C

SIR460DP MAX 40A Rds(on) = 4.7mOHM

Rds(on) = 4.7mOhm

8

U4203 D

COSLA1 Y

S3 Power Reduction

7D

S2

6D

S3

1

5D

G4

A

.

Q4206

C4208

. ...

2N7002E-1-GP
84.2N702.D31

R4227

1

21.5V_RUN_ENABLE

SIR460DP-T1-GE3-GP

2

SC10U6D3V5KX-1GP

10KR2J-3-GP

G D
S

1

PS_S3CNTRL

C4210 SCD01U50V2KX-1GP

2

DIS uses 84.00460.037 SIR460DP Peak current=40A UMA uses 84.07686.037 SI7686DP Peak current=35A

5

4

3

<Core Design> A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

Power Plane Enable

Size

Document Number

A3

Berry

Date: Thursday, October 22, 2009

Sheet 42

of

Rev
X00
92

2

1

5

4

3

2

1

Batt Connecter

+VCHGR

1

1

PG4401

D

BATT_SENSE

2

1

PC4402 SCD1U50V3KX-GP

PC4401 SC2200P50V2KX-2GP

BATT1

D

2

2

GAP-CLOSE-PWR-3-GP

10

1

2

BAT_SCL BAT_SDA BAT_IN#

PR4401

R4401 1 R4402 1 R4403 1

2 100R2J-2-GP 2 100R2J-2-GP 2 100R2J-2-GP

PBAT_PRES1#

PBAT_SMBCLK1 PBAT_SMBDAT1

3 4 5 6

+KBC_PWR

2

1

AFTP4401

1BAT_ALERT

7

8

470KR2J-2-GP

9

11

ALP-CON9-2-GP
20.81316.009

C

For actual location, need to be swap all pin

C

Close to Batt Connector

BAT_SCL BAT_SDA BAT_IN#

AFTP4402

1 PBAT_PRES1#

PD4401

3

AFTP4403

1 PBAT_SMBDAT1

PD4402

PD4403

3

3

B

AFTP4404

1 PBAT_SMBCLK1

1

2

B

AFTP4405

1 +VCHGR

1

2

1

2

BAV99-8-GP

BAV99-8-GP

BAV99-8-GP

+KBC_PWR

<Core Design>

Wistron Corporation

A

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

A

Taipei Hsien 221, Taiwan, R.O.C.

Title

BATT CONN

Size Document Number

A4

Berry

Rev
X00

Date: Thursday, October 22, 2009

Sheet 44

of

92

5

4

3

2

1

5

4

3

2

1

SSID = Charger

modify +VCHGR

D +DC_IN_SS

PR4504

1

10KR2J-3-GP

+DC_IN_SS

2

PU4502

8D

S1

7D

S2

6D

S3

5D

G4

AO4407A-GP

Id=-12A Qg=-25nC

PR4513_03

2

Rdson=10~38mohm

2

1

PR4503 100KR2J-1-GP

+SDC_IN PR4502

1

2

D01R2512F-4-GP

+PWR_SRC

1

1

PG4502 GAP-CLOSE-PWR-3-GP

2 DY 1

2

PG4503 GAP-CLOSE-PWR-3-GP

2

2

2

2

+DC_IN_SS

PU4503 1S 2S 3S 4G

+VCHGR D8 D7 D6 D5

AO4407A-GP D

1

PR4506 470KR2J-2-GP

Id=-12A Qg=-25nC Rdson=10~38mohm

2

GAP-CLOSE-PWR-3-GP

PG4505

1

GAP-CLOSE-PWR-3-GP

PG4504

1

GAP-CLOSE-PWR-3-GP

PG4506

1

GAP-CLOSE-PWR-3-GP

PG4501

1

1 PR4533_02 2

PR4505 10KR2F-2-GP

1

PQ4502_05 PQ4502_03

PQ4501

3

4

1

PR4507 0R2J-2-GP PR4524_03

0R2J-2-GP

PR4510

PR4508

0R2J-2-GP

316KR3F-2-GP

1

PR4509

BQ24745_ACOK 2

5

2

2

EC4502 SCD1U25V2ZY-1GP

EC4501 SC2200P50V2KX-2GP

SCD1U50V3KX-GP

1

6

CHAGER_SRC

2

2

2

PC4509 SCD1U50V3KX-GP

SC10U25V6KX-1GP

PC4508

SC10U25V6KX-1GP

PC4507

PC4506 SC1U6D3V2KX-GP

ICREF 1

2N7002EDW-GP

84.27002.F3F
2 PR4511 1 PC4503

1

0R2J-2-GP

SCD1U50V3KX-GP

BQ24745_DCIN

2

CHG_AGND 22 DCIN

1

2

PC4502

SCD1U50V3KX-GP

CSSP 28

PC4505

BQ24745_CSSP1

2

DY

1

2

PC4504

1

1

1

CHAGER_SRC

1

1

1

DY DY

1

PU4504 SI4800BDY-T1-GP

D8

D7

D6

D5

33R3J-2-GP

PR4513

1

PR4516 2 10KR2F-12-GP

1

10KR2F-2-GP

PC4510 SCD01U50V2KX-1GP

1

PR4514 48K7R3F-1-GP

BQ24745_LDO BQ24745_REF +KBC_PWR

BQ24745_ACIN

2 ACIN 11 VDDSMB

1

PR4515

C
DY
ACAV_IN

2

2

2

1

2009/08/04

CHG_AGND

DY

PC4501

PR4512

SCD1U10V2KX-4GP 0R2J-2-GP

2

1

BQ24745_ACOK

2

CHG_AGND

BAT_SCL

2 PG4507

1

BAT_SCL_1

GAP-CLOSE-PWR-3-GP

13 ACOK 10 SCL

BAT_SDA

2 PG4508

1

BAT_SDA_1

GAP-CLOSE-PWR-3-GP

9 SDA

15K8R3F-GP

2

PR4520

AD_IA

PR4501

2

1

0R2J-2-GP

CHG_AGND

14 NC#14

CSSN ICOUT

27 26

BOOT VDDP

25 21

SCD1U50V3KX-GP BQ24745_CSSN

CHG_AGND

DY DY

2

BQ24745_ICOUT

2

PR4517 0R3J-0-U-GP

PD4501

CHG_AGND

BQ24745_BOOT1_1

2BQ24745_BST1 K

A

1

2

BQ24745_LDO

PC4511

SD103AWS-1-GP SCD1U50V3KX-GP

1S

2S

3S

4G

UGATE 24 PHASE 23 LGATE 20

BQ24745_CHARGER_UGATE

1

2

PC4512

1 0R3J-0-U-GP

2 PR4518

SCD1U50V3KX-GP

DY BQ24745_PHASE_GND

1

2

BQ24745_LGATE_1

PC4514

SC220P50V2JN-3GP

2

1

PC4513
DY SC3300P50V3KX-1GP BQ24745_LX1

D8

D7

D6

D5

PGND 19 CSOP 18

BQ24745_CSOP_1

2

2

PL4501

1

2

IND-5D6UH-43-GP

2009/06/24

2

PG4510

1

PG4509

1

2

2

Charger Current=1.4~3.6A C modify +VCHGR

+VCHGR1

PR4519

1

2

D01R2512F-3-GP

+VCHGR

K

2

2

PC4519

1

PC4518

1

PC4517

1

PC4516

1

PC4515

1

DY

DY

2

2

2

A

PD4502 1SMA18AT3G-GP

SCD1U50V3KX-GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP

GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR-3-GP

PU4505 SI4800BDY-T1-GP

2

SCD1U50V3KX-GP

2 PR4524 0R2J-2-GP

SCD1U50V3KX-GP

1BQ24745_FBO21PR4521 1 4K7R2J-2-GP

SC220P50V2JN-3GP

PR4522 200KR2F-L-GP

BQ24745_VICM BQ24745_FBO

8 VICM

CSON 17

PC4520

1

4G

3S

2S

1S

BQ24745_PR4505

8K45R2F-2-GP

PC4531 SCD1U50V3KX-GP

PR4530 1K8R6J-GP

PC4530 SCD1U10V2KX-4GP

1

2

1PR4525

B

2

DY

2

1PC4524

PC4526

1

PC4522 2SC2200P50V2KX-2GP

PR4526

2

1PR45226_071K5R2F-11-GP

PC4521 SC150P50V2JN-3GP

PC4525

1

2

1

DY

1

PC4527 SC56P50V2JN-2GP

DY

DY
PC4528

2

2

SCD01U50V2KX-1GP

2

1

6

BQ24745_EAI

5

BQ24745_EAO

4

BQ24745_REF

3

1

2 BQ24745_CE 7

PR4527

12

0R2J-2-GP

FBO EAI EAO VREF CE GND

1

DY

PU4501

BQ24745RHDR-GP

2

PC4529 SC1U6D3V2KX-GP

29 GND

NC#16 16 VFB 15

PR4529

2

1

0R2J-2-GP

PR4528

0R2J-2-GP

BAT_SENSE 2

1

1

1

DY

DY

PC4523

1

2

CHG_AGND BATT_SENSE

1 PR4523 2 0R2J-2-GP

BQ24745_CSOP BQ24745_CSON

1

21

DY

B

2

2

CHG_AGND

CHG_AGND

CHG_AGND

CHG_AGND

PC4532 SCD1U25V2ZY-1GP

SCD01U50V2KX-1GP

SCD1U50V3KX-GP 2

This Resistor must be 1% tolerance.

AC_IN#

1

2

DY PC4533

.

Q4502

2N7002E-1-GP

... .

S D
G

SCD1U25V2ZY-1GP

A

ACAV_IN

<Core Design>

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CHARGER BQ24745

Size

Document Number

Rev

Custom

Berry

X00

Date: Thursday, October 22, 2009

Sheet 45

of

92

5

4

3

2

1

A

B

C

D

E

1

+3.3V_ALW _2
PR4602 100KR2J-1-GP

51125_VCLK

1

1

1

PC4603 SCD1U25V3KX-GP

PC4604 SCD1U25V3KX-GP

3 PD3904_1 2

3 PD3903_1 2

2

2

PC4602 SC1KP50V2KX-1GP

51125_ENTRIP

G D
S

51125_ENTIP1

1

1

.
Q4601

SC18P50V2JN-1-GP

2N7002E-1-GP
.

...

PC4601 DY

2

PR4601 91KR2F-GP

6

5

4

PD4601 BAT54S-5-GP

PD4602 BAT54S-5-GP

4

84.2N702.D31

PQ4602

4

1

1

2

2

2N7002EDW -GP

+15V_ALW

+5V_PW R

84.27002.F3F

3

2

1

PG4605

3V_5V_EN

1

2

PD3903_2

PD3903_04 2

2

1

51125_ENTIP2
DY

1

PR4603 100KR2F-L1-GP

GAP-CLOSE-PW R-3-GP

2

1

PC4605 SC1U25V3KX-1-GP

1

2

PC4606 SCD1U25V3KX-GP
PC4608 SCD1U25V3KX-GP

1

2

2

TPS51125 PR4622 DY

RT8205B ASM

PC4607 SC18P50V2JN-1-GP

+PW R_SRC

+PW R_SRC

PR4622

+PW R_SRC

51125_EN 1

2

PC4612

1

1

1

1

1

SCD01U50V2KX-1GP SC10U25V6KX-1GP

820KR3J-GP

PC4613

PC4609 PC4610 PC4611

TPS51125

RT8205B

VIN 16

SCD01U50V2KX-1GP

SC10U25V6KX-1GP SC10U25V6KX-1GP

SC10U25V6KX-1GP SC10U25V6KX-1GP SCD01U50V2KX-1GP

2

2

DY
D

2

TPS51125 PR4604 0R3J

RT8205B 4R7

D8 D7 D6 D5

PU4602

DY

PR4605 0R3J

4R7

2

2

8

7

6

5

D

1

PC4614 PC4616

1

1

PC4617

D

D

D

D

PU4603

DY

+5V_PW R

+5V_ALW

PG4613

2

1

FDS8880-NL-GP

PU4601

FDS8880-NL-GP

2

2

2

GAP-CLOSE-PW R

PG4614

Design Current =9.07A 14.25A<OCP<16.84A
+3.3V_ALW

PL4601

PC4615

1S 2S 3S 4G

S

S

S

G

SCD1U25V3KX-GP

PR4604

PR4605

SCD1U25V3KX-GP

4D7R3J-L1-GP

4D7R3J-L1-GP

PC4618

S

G2

1 51125_VBST2_1 1

251125_VBST2 9 VBST2

VBST1 22 51125_VBST1 1

2 51125_VBST1_1 1

2

4

3

GS

2

1

51125_DRVH2 10 DRVH2

DRVH1 21 51125_DRVH1

PL4602

Design Current = 8.48A 13.32A<OCP< 15.75A
+5V_PW R

2

1

GAP-CLOSE-PW R

PG4615

2

1

GAP-CLOSE-PW R

3

1

2

IND-3D3UH-115-GP

51125_LL2 11 LL2

LL1 20 51125_LL1

1

2

IND-2D2UH-46-GP-U

PG4616

3

2

1

1

2

1

PC4619

2

1

PTC4601
DY

2

1

PTC4602

1

PG4624

PR4606 2D2R5F-2-GP

D DY

D8 D7 D6 D5

PU4604

51125_DRVL2 12 DRVL2

51125_VO2

7 VO2

DRVL1 19 51125_DRVL1 VO1 24 51125_VO1

1

PU4605 FDS6676AS-GP

5

6

D

7

D

8

D

D

D DYPR4607
2D2R5F-2-GP

1

PG4626

1

PC4620

PTC4603

1

1

PTC4604

GAP-CLOSE-PW R

PG4617

2

1

151125_LL21_R

151125_LL22_R

2

ST100U6D3VBM-5GP

ST220U6D3VDM-15GP SCD1U10V2KX-4GP

GAP-CLOSE-PWR-3-GP

FDS6676AS-GP
GAP-CLOSE-PWR-3-GP ST220U6D3VDM-15GP
ST100U6D3VBM-5GP SCD1U10V2KX-4GP

51125_FB2

5 VFB2

VFB1 2

51125_FB1

2

2

2

DY

GAP-CLOSE-PW R PG4618

PC4621

S

G

2

DY SC330P50V3KX-GP

1S 2S 3S 4G

DY 1
PR4608

2 51125_EN 13 820KR2F-GP

51125_ENTIP2 6 51125_VREF

3

EN0 ENTRIP2 VREF

PGOOD 23 ENTRIP1 1
GND 15

3V_5V_POK 51125_ENTIP1

4

3

2

1

GS
PC4622
DY SC560P50V-GP

2

G

S

S

S

2

2

1

GAP-CLOSE-PW R

PG4619

2

1

GAP-CLOSE-PW R

1

2

1

1

PC4623 SCD22U10V2KX-1GP

51125_TONSEL

4 TONSEL

GND 25

PR4611

1

PG4620

2

1

PR4609 6K65R2F-GP

PR4610 0R2J-2-GP
DY

51125_SKIPSEL 14 SKIPSEL

VCLK 18 51125_VCLK

0R2J-2-GP
DY

1

PR4612 33KR2F-GP

GAP-CLOSE-PW R

PG4621

2

1

12

17 VREG5

TPS51125RGER-GP

51125_FB1_R

GAP-CLOSE-PW R

12

2

2

51125_FB2_R
DY PC4625
SC18P50V2JN-1-GP

74.51125.073

+3.3V_ALW _2

PG4635

+5V_ALW 2

+3.3V_ALW

PC4624 DY
SC18P50V2JN-1-GP

2

2

1

1

PR4613 10KR2F-2-GP

2

1

51125_VREF +3.3V_ALW _2

PR4614

2

1

0R2J-2-GP

PR4617

DY 2

1

0R2J-2-GP

1

2

GAP-CLOSE-PW R-3-GP

Change to RT8205B 74.08205.B73

2

PR4615 100KR2J-1-GP
3V_5V_POK

2

PR4616 21K5R2F-GP
Close to VFB Pin (pin2)

1 3D3V_AUX_S5_5_51125 8 VREG3

SC22U6D3V5MX-2GP PC4628
SC10U10V5KX-2GP

51125_VREF

2

PR14618

0R2J-2-GP

PC4626

PC4627

1

2

Close to VFB Pin (pin5)

+3.3V_ALW _2

PR4619

DY 2

1

0R2J-2-GP

SC4D7U6D3V3KX-GP

2

2

DY

PR4620

DY 2

1

0R2J-2-GP

2

1

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L

Inductor: 2.2uH PCMC063T-2R2MN Cyntec 18mohm/20mohm Isat =14Arms 68.2R210.20B

2

O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L

O/P cap: 100U 6.3V TEPSLB20J107M(45)8R 45mOhm 1.374Arms NEC_TOKIN/77.C1071.081

H/S: FDS8880 9.6mohm/12mOhm@4.5Vgs/ 84.08880.037

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L

+3.3V_ALW _2

+3.3V_RTC_LDO

L/S: FDS6676AS 5.9mOhm/7.25mOhm@4.5Vgs/ 84.06676.A37

Inductor: 3.3UH PCMB104T-3R3MS Cyntec 10.8mohm/11.8mohm Isat =16Arms 68.3R310.20C O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L O/P cap: 100U 6.3V TEPSLB20J107M(45)8R 45mOhm 1.374Arms NEC_TOKIN/77.C1071.081 H/S: FDS8880 9.6mohm/12mOhm@4.5Vgs/ 84.08880.037

TPS51125 PR4614 DY PR4617 ASM

RT8205B ASM DY

PR4621

1

2

0R2J-2-GP

L/S: FDS6676AS 5.9mOhm/7.25mOhm@4.5Vgs/ 84.06676.A37

TPS51125:

TONSEL GND VREF VREG3 VREG5

CH1 200kHz 245kHz 300kHz 365kHz

CH2 265kHz 305kHz 375kHz 460kHz

SKIPSEL
Operating Mode

VREG3 or VREG5 VREF(2V) OOA Auto Skip Auto Skip

GND PWM only

EN0
Operating Mode

Open
enable both LDOs, VCLK on and ready to turn on switcher channels

820k to GND
enable both LDOs, VCLK off and ready to turn on switcher channels

GND
disable all circuit

1 A

RT8205B:
TONSEL GND VREF VREG3 VREG5

CH1 200kHz 300kHz 365kHz 365kHz

CH2 250kHz 375kHz 460kHz 460kHz

B

C

1

Bom

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

RT8205B_5V/3D3V

Size

Document Number

A2

Berry

Rev
X00

Date: Thursday, October 22, 2009

Sheet 46

of

92

D

E

5

4

3

2

1

+PW R_SRC

1

1

TC4702

TC4703

DY

DY

VR_CLKEN# +3.3V_RUN

PM_DPRSLPVR IMVP_VR_ON

H_VID[6..0]

PU4702

5 6 7 8

D

D

D

D

2

1

2

2

+PW R_SRC

1

1

1

PC4706

PC4703 PC4704
DY

PC4705

2

SCD1U50V3KX-GP

H_VID6 H_VID5 H_VID4 H_VID3 H_VID2 H_VID1 H_VID0

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SI7686DP-T1-GP

1

2

3

4

SE100U25VM-11GP

2

SE100U25VM-11GP

2

S

S

S

G

1 0R2J-2-GP
1 0R2J-2-GP
1 0R2J-2-GP
1 0R2J-2-GP
1 0R2J-2-GP
1 0R2J-2-GP
1 0R2J-2-GP
1 0R2J-2-GP
1 0R2J-2-GP
1 0R2J-2-GP

D
PR4745 1K91R2F-1-GP

1

2

2

2

2

2

2

2

2

UGATE1

PL4701

+VCC_CORE

D

PHASE1

1

2

IND-D36UH-9-GP

PR4775

1

1

1

8

7

6

5

D

D

D

PU4703

DY

D

PTC4703 PTC4702

SE220U2VDM-12GP

2

ST330U2VDM-4-GP

2

1

1

SC330P50V2KX-3GP 2D2R5J-1-GP

1SNUBB2ER_1

PR4766

PR4729

PR4762

PR4730

PR4746

PR4755

PR4718

PR4773

PR4749

PC4718

+VCC_CORE_PHASE1 2

2

1

2

3

4

62883_VID0

62883_VID1

62883_VID2

62883_VID3

62883_VID4

62883_VID5

62883_VID6

62883_VR_ON

62883_DPRSLPVR 2

PR4735

62883_CLK_EN# 2

2

PG4706 GAP-CLOSE-PWR-3-GP
PG4708 GAP-CLOSE-PWR-3-GP

SIR460DP-T1-GE3-GP

S

S

S

G

+3.3V_RUN

CLK_EN# 40 DPRSLPVR 39
VR_ON 38 VID6 37 VID5 36 VID4 35 VID3 34 VID2 33 VID1 32 VID0 31

1

PR4720 1K91R2F-1-GP

PU4701

IMVP_PW RGD PSI#

NTC 470K close to H/S MOSFET of Phase1

H_PROCHOT#

PR4771

1 DY 2 6266A_NTC_R1
PR4774

DY2 NTC-470K-1-GP

4K02R2F-GP

1 DY2
SCD01U25V2KX-3GP

PC4737

1

2

PR4726

8K06R2F-GP

1

2 62883_PGOOD 1

PR4704

0R2J-2-GP

1

2 62883_PSI# 2

PR4733

0R2J-2-GP

1

2 62883_RBIAS 3

PR4781

147KR2F-GP

1 DY 2H_PROCHOT#_R 4
PR4758

4K02R2F-GP 62883_NTC

5

62883_VW

6

62883_COMP 7

62883_FB

8

PGOOD PSI# RBIAS VR_TT# NTC VW COMP FB

2

ISL62883HRZ-T-GP

BOOT2 30 UGATE2 29 PHASE2 28
VSSP2 27 LGATE2 26
VCCP 25 PWM3/LGATE1# 24
LGATE1 23

BOOT2 UGATE2

PR4772

1

2 B00T2_R

2D2R3J-2-GP

PHASE2

1

2

PC4710

SCD22U16V3KX-1-GP

LGATE2

62883_VCCP

62883_PW M3

LGATE1

1

2

ISEN3

9 ISEN3/FB2

VSSP1 22

1

SCD22U10V2KX-1GP SCD22U10V2KX-1GP

C

PC4719 SC1KP50V2KX-1GP

PC4702 ISEN2 10 ISEN2

1

PC4707

2

PR4744
1 DY 2

1

2

PC4738

2

41 GND

0R2J-2-GP

SC33P50V2JN-3GP

ISEN3

DY

1

2

PC4735

SC22P50V2JN-4GP

1

262883_COMP_1R

2

PC4740

PR4752

SC150P50V2JN-3GP 324KR2F-GP

1

ISEN1 PC4736 SCD22U10V2KX-1GP

ISEN1 VSEN RTN ISUMISUM+ VDD VIN IMON BOOT1 UGATE1

2

PC4709 SCD22U16V3KX-1-GP

PHASE1 21

PHASE1 +1.05V_VTT

2

1

PR4786

UGATE1 PR4722

DY 100KR2F-L1-GP

BOOT1 1

2BOOT1_PHASE1

1

2D2R3J-2-GP

11 12 13 62883_ISUM- 14 15 62883_VDD 16 62883_VIN 17 18 19 20

VSUM-

PC4716

1

262883_FB_VSEN1

2

PR4714 562R2F-GP

PR4712

SC390P50V2KX-GP

1

2

2

2

1

PR4754 0R2J-2-GP

1

2 +PWR_SRC

1

2

PR4759

+5V_ALW

1

1R2F-GP

2 PC4729 SCD22U25V3KX-GP

6K98R2-GP

2

1

PR4776

1

IMVP_IMON
PC4730 SCD22U10V2KX-1GP

2

VSS_SENSE

2KR2F-3-GP

1

2

+5V_ALW

PR4770
1 DY 2
4K02R2F-GP

1

PR4751 0R3J-0-U-GP

2

PC4708 PC4732

1

1

2

2

SC1U10V2KX-1GP SC1U10V2KX-1GP

PR4723 0R2J-2-GP

+5V_ALW

PR4731

1

2

PC4734

1

2

0R2J-2-GP

SC1U10V2KX-1GP PR4734

BOOT3

1

2 6208_PHASE3

2

PU4706

2D2R3J-2-GP PC4723
SCD22U16V3KX-1-GP

1

VCC 5 BOOT 1

6208_PWM 6208_FCCM

PC4722 SC1U10V2KX-1GP

GND GND

1VSUM_R2R

2 VSUM_2RC

11KR2F-L-GP SCD01U16V2KX-3GP SCD33U16V3KX-1GP

PC4721 SC330P50V2KX-3GP

2

1

1

PR4725 82D5R2F-1-GP

1

2

PC4717

1

2

1

PC4741 PR4736

1

VSUM+
PR4750 2K61R2F-1-GP

2 PWM 6 FCCM

PHASE UGATE LGATE

7 8 4

PHASE3 UGATE3 LGATE3

VCC_SENSE

9 3

ISL6208CRZ-TGP-U

2

1

PC4711 SC330P50V2KX-3GP
VSS_SENSE B

2

Intel support POC (Power On Configuration).

PC4701 SC1KP50V2KX-1GP

1

2

1

PC4742 SCD01U25V2KX-3GP

PR4748

1

2

649R2F-GP

2

1

2

PR4721 NTC-10K-26-GP
VSUM-
NTC 10K close to Choke of Phase1
PC4731 SCD1U25V3KX-GP

+1.05V_VTT

PG4715

PR4737 PR4701 PR4709 PR4732 PR4713 PR4705 PR4769 PR4724 PR4753

1

2

GAP-CLOSE-PW R-3-GP

1

1

1

1

1

1

1

1

1

DY DY

DY

DY

1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP

2

2

2

2

2

2

2

2

2

H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6 PM_DPRSLPVR PSI#
PR4715 PR4702 PR4768 PR4743 PR4727 PR4710 PR4706 PR4703 PR4777

1

1

1

1

1

1

1

1

DY DY DY

DY

DY

1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP

2

2

2

2

2

2

2

2

A

2

1

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L Inductor: 0.36UH PCMC104T-R36MN1R05J Cyntec 1.05mohm/ 68.R3610.20C O/P cap: 330U 2V EEFSX0D221E7 6mOhm 3.0Arms Panasonic/79.33719.20L O/P cap: 220U 2V EEFSX0D331XE 7mOhm 3.4Arms Panasonic/79.22719.90L H/S: SI7686DP/ POWERPAK-8/11mOhm/14mOhm@4.5Vgs/ 84.07686.037 L/S: SiR460DP/ POWERPAK-8/ 4.9mOhm/6.1mohm@4.5Vgs/ 84.00460.037

5

4

3

DY
LGATE1

2

PHASE1_R

ISEN1 VSUM+ VSUMISEN2 ISEN3

1 PR4756
1 PR4767
1 PR4742
1 PR4716
1 PR4738

2 10KR2F-2-GP
2 3K65R3F-GP
2 1R2F-GP
2 10KR2F-2-GP
2 10KR2F-2-GP

+PW R_SRC

PU4704

5 6 7 8

D

D

D

D

2

1

2

2

PC4715

1

1

PC4713 PC4714
DY

1

PC4712

2

Design Current = 48A 52.8A<OCP<67.2A
C

SCD1U50V3KX-GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SI7686DP-T1-GP

S

S

S

G

1

2

3

4

UGATE2 PHASE2
PU4705

5

6

D

7

D

8

D

D

PL4702

1

2

IND-D36UH-9-GP

PR4728

1

DY

2

1

2

1

+VCC_CORE PTC4705 PTC4704

SE220U2VDM-12GP

ST330U2VDM-4-GP

1

1

SC330P50V2KX-3GP 2D2R5J-1-GP

1SNUBB2ER_2

PG4713 GAP-CLOSE-PWR-3-GP
PG4712 GAP-CLOSE-PWR-3-GP

SIR460DP-T1-GE3-GP

2

2

PC4733

S

S

S

G

1

2

3

4

LGATE2

DY

2

+VCC_CORE_PHASE2

PHASE2_R

ISEN2

1

2

PR4780

10KR2F-2-GP

VSUM+

1

2

PR4739

3K65R3F-GP

VSUM-

1

2

PR4708

1R2F-GP

ISEN1

1

2

PR4760

10KR2F-2-GP

ISEN3

1

2

PR4707

10KR2F-2-GP

+PW R_SRC

B

PU4707

5 6 7 8

D

D

D

D

2

1

2

2

PC4727

1

1

PC4725 PC4728
DY

1

PC4726

2

SCD1U50V3KX-GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SI7686DP-T1-GP

S

S

S

G

1

2

3

4

UGATE3 PHASE3
PU4708

5

6

D

7

D

8

D

D

PL4703

1

2

IND-D36UH-9-GP

PR4740

1

1

DY

2

SC330P50V2KX-3GP 2D2R5J-1-GP

1SNUBB2ER_3

SIR460DP-T1-GE3-GP

PC4739

S

S

S

G

1

2

3

4

+VCC_CORE_PHASE3

PHASE3_R

LGATE3
ISEN3 VSUM+ VSUMISEN1 ISEN2

DY

2

1 PR4763
1 PR4764
1 PR4747
1 PR4719
1 PR4765

2 10KR2F-2-GP
2 3K65R3F-GP
2 1R2F-GP
2 10KR2F-2-GP
2 10KR2F-2-GP

2

PG4714 GAP-CLOSE-PWR-3-GP
PG4701 GAP-CLOSE-PWR-3-GP

2

1

2

1

+VCC_CORE

1

PTC4706

PTC4707

ST330U2VDM-4-GP

2

ST330U2VDM-4-GP

A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

ISL62883_CPU_CORE

Size A2

Document Number
Berry

Date: Thursday, October 22, 2009 1

Sheet 47

of

Rev
X00
92

5

+PW R_SRC

+PW R_SRC_VTT

PG4901

1

2

GAP-CLOSE-PW R

PG4902

1

2

GAP-CLOSE-PW R

PG4903

1

2

GAP-CLOSE-PW R

D

PG4904

1

2

GAP-CLOSE-PW R

PG4907

1

2

GAP-CLOSE-PW R

RUNPW ROK

1.5CPU_1.05VTT_PW RGD

PR4901

1

2

80K6R2F-GP

1 PR4903

2 0R2J-2-GP

1

1

4
TPS51218 for +1.05V_VTT
+PW R_SRC_VTT

8

7

6

5

PU4902

D

D

D

D

SIS406DN-T1-GE3-GP

S

S

S

G

51218_VTT_TRIP 51218_VTT_EN 51218_VTT_VFB 51218_VTT_CCM
PR4904 470KR2F-GP

PU4901

1 2 3 4 5

PGOOD TRIP EN VFB CCM

GND VBST DRVH
SW V5IN DRVL

11 10 9 8 7 6

TPS51218DSCR-GP-U

2

PC4908

PR4902

SCD1U25V3KX-GP

2D2R3J-2-GP

51218_VBST_VTT 1

251218_VBST_VTT12

1

51218_DRVH_VTT

51218_SW _VTT

51218_DRVL_VTT

+5V_ALW

1

PC4909 SC1U10V2KX-1GP

5

4

6

3

7

2

8

1

PU4904

2

2

PC4901 SC1KP50V2KX-1GP

D

D

D

D

SIS402DN-T1-GE3-GP

S

S

S

G

1

2

3

4

+3.3V_RUN

+3.3V_ALW

1

C
PR4908 10KR2J-3-GP

1

PR4909 100KR2J-1-GP

2

PQ4901

2

1

6

1.5CPU_1.05VTT_PW RGD
PC4913 SCD1U25V3KX-GP

2

1

2

5

H_VTTPW RGD_R

3

4

2N7002EDW -GP
84.27002.F3F

1

+1.05V_VTT
PR4911 1KR2J-1-GP

2

H_VTTPW RGD

H_VTTPW RGD

4

5

4

5

G

3

6

3

6

D

G

D

2

7

2

7

S

D

S

D

1

8

1

8

S

D

S

D

S

D

S

D

PR4910

2

20KR2F-L-GP

3

2

PC4906
SCD1U25V2KX-GP PC4903
SC10U25V6KX-1GP PC4904
SC10U25V6KX-1GP PC4902
SC10U25V6KX-1GP

PU4903

1

2

1

2

1

2

1

2

DY
DIS(Arrandale 1.05V_VTT) Design Current = 20.57A 30.79A<OCP<36.39A

SIS406DN-T1-GE3-GP

1+1.05V_VTT_VOUT 2

151218_SW_GND_VTT 2

SE330U2VDM-L-GP SE330U2VDM-L-GP

SCD1U10V2KX-4GP

SC4D7U6D3V3KX-GP GAP-CLOSE-PWR-3-GP

PL4901

1

2

IND-D56UH-12-GP

1

DY PR4905

2D2R5J-1-GP

PU4905

1

PG4916

2

1

PC4910
DY

2

1

2

+1.05V_VTT

1

1

PC4911

PTC4901

PTC4902

2

SIS402DN-T1-GE3-GP

PC4912
DY

2

SC330P50V2KX-3GP

PR4907

1 DY 2
PR4906 10R2J-2-GP

VTT_SENSE

R1
Vout=0.704V*(R1+R2)/R2

10KR2F-2-GP

2

51218_VTT_VFB

1

R2

Frequency setting 470K -->290KHz 200K -->340KHz 100K -->380KHz
39K -->430KHz

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L Inductor: 0.56uH PCMC104T-R56MN Cyntec DCR:1.6mohm/1.8mohm Isat=25Arms 68.R5610.10D O/P cap: 330U 2.5V EEFSX0D331ER 9mOhm 3Arms PANASONIC/ 79.33719.L01 H/S: SiS406DN/ POWERPAK-8/ 11.5mOhm/14.5mOhm @4.5Vgs/ 84.00406.037 L/S: SiS402DN/ POWERPAK-8/ 6.4mOhm/8mohm@4.5Vgs/ 84.00402.037

B

1 D C B

A

A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

TPS51218_+1.05V_VTT

Size A2

Document Number
Berry

Rev
X00

Date: Thursday, October 22, 2009

Sheet 49

of

92

5

4

3

2

1

5

4

3

2

1

SSID = PWR.Plane.Regulator_1p5v0p75v

+5V_ALW

5 S3 Power Reduction

1

PR5001 5D1R3J-GP
+5V_ALW

+5V_ALW

PC5001 SC1U10V2KX-1GP

PR5002

2

1.5CPU_1.05VTT_PWRGD

Modified net name

1

2 TPS51116_VDD

10KR2F-2-GP

+5V_ALW

1

PS_S3CNTRL

1

D

D

1

2

PC5003

PR5016

SC1U10V2KX-1GP

100KR2J-1-GP

A

1

2

PC5002 +3.3V_RUN SC1KP50V2KX-1GP

2

PD5001

2

+PWR_SRC_1D5V

TPS51116_VDD_R

2

DY

RB551V-30-2GP

+1.5V_RUN_CPU

1.5V_RUN_CPU_EN#

PQ5002

6

5

4

PR5015 0R2J-2-GP

K

2

VDDP 14 VDDP 15

ILIM 16

PR5004 20KR2F-L-GP

1

RUNPWROK PR5006 1

DY 2 622KR2F-GP

13 TPS51116_NC#12 12
1D5V_EN 11 0D75V_EN 10

PGD NC#12 EN/PSV VTTEN

PU5001

BST DH

PR5005

22 TPS51116_VBST 1

2TPS51116_VBST1

0R3J-0-U-GP 21 TPS51116_UGT

LX 20 TPS51116_PHS

PR5017

2

11.5V_RUN_CPU_EN 1

4K7R2J-2-GP

3

PQ5001 PMBS3904-1-GP

2

1

2N7002EDW-GP
84.27002.F3F

3

2

PM_SLP_S3#

PR5003
1 DY 2
0R2J-2-GP

1

2

1

0D75V_EN
PC5004
DY SCD1U10V2KX-4GP

RT: Non_ASM

+1.5V_SUS

23 VTTIN

1

TI: ASM

+5V_ALW

PC5005 SC1U10V2KX-1GP

7 NC#7

DL 19 TPS51116_LGT

2

C

PR50081
+1.5V_SUS PR50091

DY 2 1M1R2J-GP
2 0R2J-2-GP

2

TPS51116_TON

TPS51116RGER-GP-U

1 PGND2 4 TON

PGND1 PGND1

18 17

VDDQS 8

TPS51116_VDDQSNS

+0D75V_DDR_P

PC5007
DY SC1KP50V2KX-1GP

1

24 VTT 2 VTTS

FB 9 VCCA 6

TPS51116_VDDQSET
+5V_ALW PR5010
1DY 2

+PWR_SRC

+PWR_SRC_1D5V

PM_SLP_S4#

PR5007 1

2 0R2J-2-GP

1D5V_EN

PG5002

2

1

C

1

DY PC5006 SCD1U10V2KX-4GP

GAP-CLOSE-PWR

PG5003

2

1

2

GAP-CLOSE-PWR

PG5004

2

1

0R2J-2-GP

+PWR_SRC_1D5V

25 GND 3 VSSA

GAP-CLOSE-PWR

1

+V_DDR_REF

DY PC5008 SC1U10V2KX-1GP

PG5006

2

1

2

1 PR5011 2 0R0603-PAD

2

2

2

2

DY

1

GAP-CLOSE-PWR

PC5014 SC4D7U25V5KX-GP

PC5013 SCD1U25V2KX-GP

PC5012 SC10U25V6KX-1GP

PC5011 SC10U25V6KX-1GP

PC5009 SC10U25V6KX-1GP

1TPS51116_REF 5 REF

8

7

6

5

PU5002

2

1

1

1

1

D

D

D

D

+0D75V_DDR_P Design Current = 0.7A

2

PC5010 SCD033U16V3KX-GP

Design Current = 14.45A 22.71A<OCP< 26.84A

SI7686DP-T1-GP

S

S

S

G

1

2

3

4

PC5018 SC10U6D3V5MX-3GP

PC5017 SC10U6D3V5MX-3GP

PC5016 SC10U6D3V5MX-3GP

PC5015 SCD1U10V2KX-4GP

+0D75V_DDR_P

+0.75V_DDR_VTT

PG5001

TPS51116_UGT

1

1

1

1

2

1

B

GAP-CLOSE-PWR

TPS51116_VBST1 1

2

2

2

2

2

PG5016

PC5019

2

1

SCD1U25V3KX-GP

GAP-CLOSE-PWR

State S3

S5 VDDR VTTREF

VTT

S0

Hi Hi

On

On

On

S3

Lo Hi

On

On

Off(Hi-Z)

S4/S5 Lo Lo

Off

Off Off

TPS51116_LGT

4

5

G

3

6

D

2

7

S

D

1

8

S

D

S

D

TPS51116_PHS

+1.5V_SUS

PL5001

1

2

B

IND-1D5UH-34-GP

PC5021 SCD1U10V2KX-4GP

1

PC5020 SC4D7U6D3V3KX-GP

2

8

7

6

5

GAP-CLOSE-PWR-3-GP

SE220U2VDM-8GP SE220U2VDM-8GP

SIR460DP-T1-GE3-GP

S

S

S

G

SIR460DP-T1-GE3-GP

PU5003

D

D

D

D

PU5004
DY

2

DY PR5012 2D2R5F-2-GP TPS51116_PHS_SET

1

PG5017

2

1

2

1

2

1

2

1

PTC5002 PTC5001
DY

1

1

2

3

4

DY PC5022
SC330P50V3KX-GP

2

TPS51116_VDDQSNS

1

1

PR5013 30KR2F-GP

DY

PC5023 SC18P50V2JN-1-GP

2

TPS51116_VDDQSET

12

VDDQSET GND
A
V5IN FB Resistors

VDDQ (V)

VTTREF and VTT

2.5

VVDDQSNS/2

1.8

VVDDQSNS/2

Adjustable

VVDDQSNS/2

NOTE DDR DDR2
1.5 V < VVDDQ < 3 V

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L Inductor: 0.56uH PCMC104T-R56MN Cyntec DCR:1.8mohm Isat=25Arms 68.R5610.10D O/P cap: 220U 2V EEFCX0D221ER 15mOhm 2.7Arms PANASONIC/ 79.22719.20L H/S: SI7686DP/ POWERPAK-8/11mOhm/14mOhm@4.5Vgs/ 84.07686.037 L/S: SiR460DP/ POWERPAK-8/ 4.9mOhm/6.1mohm@4.5Vgs/ 84.00460.037 Switching freq-->400KHz

5

4

3

PR5014 30KR2F-GP
2

2

Close to VFB Pin (pin5)

<Core Design>

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

TPS51116_+1.5V_SUS

Size

Document Number

Custom

Berry

Date: Thursday, October 22, 2009

Sheet 50

of

1

Rev
X00
92

5

4

3

2

SSID = PWR.Plane.Regulator_1p8v

D

APL5930 for +1.8V_RUN

+3.3V_ALW

+1.8V_RUN_VIN

+5V_ALW

+1.8V_RUN_VIN

1

1

1

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

PG5107

2

1

GAP-CLOSE-PW R

PG5106

2

1

GAP-CLOSE-PW R

PC5110 SC1U10V2KX-1GP
PU5101

2

2

PC5109

PC5113
DY

2

Design Current =1.23A

+1.8V_RUN_P

+1.8V_RUN

VCNTL 6

PM_SLP_S3#

RUNPW ROK 1
PR5109

1 PR5113

21.8V_RUN_POK 0R2J-2-GP

2 1D8V_RUN_EN 0R2J-2-GP

7 POK 8 EN

VIN#5 VIN#9

5 9

VOUT#3 VOUT#4

3 4

FB 2

1

+1.8V_RUN_P

1

1

1

PR5111 PC5108

PC5111

PC5112
DY

PG5105

1

2

GAP-CLOSE-PW R

PG5108

1

2

GAP-CLOSE-PW R

2

2

2

1 GND

16K5R2F-2-GP

2

C

APL5930KAI-TRG-GP

SO-8-P

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC68P50V2JN-1GP

5912_1.8V_RUN_FB

1

PC5114

2

DY
Vout=0.8V*(R1+R2)/R2
PR5110 13K3R2F-L1-GP

1

SC4700P50V2KX-1GP

2

B

1 D C B

A

<Core Design>

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

APL5930_+1.8V_RUN

Size

Document Number

A3

Berry

Rev
X00

Date: Thursday, October 22, 2009

Sheet 51

of

92

5

4

3

2

1

5

4

SSID = CPU.GFX.Regulator

GFX_VR_EN

UMA

1

2

PR5310

0R2J-2-GP

+3.3V_ALW

51611_VREFF

+5V_ALW

51611_VREFF

UMA

D

1

2

PR5311 124KR2F-GP

2 0R2J-2-GP
2 0R2J-2-GP
2 0R2J-2-GP
2 0R2J-2-GP 2 0R2J-2-GP 2 0R2J-2-GP

51611_VREFF

1

2

PC5313 SC2D2U10V3KX-1GP

UMA

1

2 PC5314

UMA

SC68P50V2JN-1GP

UMA

1

2

PR5312 1K69R2F-2-GP

1

UMA

PC5315 SCD22U10V2KX-1GP

1

PR5313

1

PR5314

PR5315

UMA UMA DY DY DY UMA

1 PR5316
1 PR5317
1 PR5318

PR5319
UMA DY

1

2

2

1

+3.3V_RUN

3

2

+PW R_SRC

+VGFXCORE_PW R_SRC

PG5301

1

2

GAP-CLOSE-PW R

PG5303

1

2

GAP-CLOSE-PW R

PG5305

1

2

GAP-CLOSE-PW R

PG5308

1

2

GAP-CLOSE-PW R

PG5311

1

2

GAP-CLOSE-PW R

+VGFXCORE_PW R_SRC

51611_VR_ON

51611_TRIPSEL 1

51611_TONSEL

51611_OSRSEL

PR5301 10KR2F-2-GP 0R2J-2-GP

51611_ISLEW

51611_VREFF 51611_DROOP

2

1

1

1

51611_CLKEN 51611_PGOOD

GND 33 VREF 32 DROOP 31 V5FILT 30 ISLEW 29 OSRSEL 28 TONSEL 27 TRIPSEL 26 VR_ON 25

PU5301

1 GND

CLKEN# 24

51611_CSP

2 CSP

PGOOD 23

51611_CSN

3 CSN

MODE 22

51611_GSNS

Close to VGA

51611_VSNS

DY

DY 1
PR5320

251611_THERM_R

1

2KR2F-3-GP

PR5321

2

51611_THERM

NTC-100K-10-GP

4 GNDSNS

UMA

V5IN 21

5 VSNS TPS51611RHBR-GP DRVL 20

6 THERM

LL 19

C

PM_EXTTS#0_C GFX_IMON

1

2

PR5322 DY 0R2J-2-GP

51611_VR_TT

7 VR_TT# 8 IMON

VBST 18 DRVH 17

+5V_ALW

PU5302 SI7686DP-T1-GP

PC5301

UM1A 2
SC2D2U10V3KX-1GP

51611_PHASE

2D2R3J-2-GP

PC5316

51611_BOOT

1

2 6236A_BOOT_C

PR5323 UMA
51611_UGATE

1

2

SCD22U16V3KX-2-GP

UMA

UMA

9 DPRSLP 10 VID6 11 VID5 12 VID4 13 VID3 14 VID2 15 VID1 16 VID0

2

1

1

PR5325 10KR2F-2-GP
DY

2

PC5317
DY
SC3300P50V2KX-1GP

74.51611.073

PU5303
UMA

5

4

5

G

6

3

6

D

G

D

7

2

7

S

D

S

D

8

1

8

S

D

S

D

S

D

S

D

DY PC5302

PC5303

UMA UMA

PC5304

SCD1U25V2KX-GP

2

2

2

SC10U25V6KX-1GP SC10U25V6KX-1GP

PU5304

D

D

D

DY

5

G

6

7

S

8

S

S

D

2D2R3J-2-GP

GAP-CLOSE-PWR-3-GP

1

PR5324
DY
PG5322

1

PL5301

1

2

IND-D56UH-12-GP

UMA

PG5323

2

2

51611_RF

1

DYPC5318

SC470P50V2KX-3GP

SIR460DP-T1-GE3-GP

SIR460DP-T1-GE3-GP

2

1

2

3

4

1

2

3

4

GFX_DPRSLPVR GFX_VID6 GFX_VID5 GFX_VID4
GFX_VID3 GFX_VID2 GFX_VID1 GFX_VID0
B

PRN5301

5

4

6

3

7 UMA 2

8

1

SRN0J-7-GP

PRN5302

5

4

6

3

7 UMA 2

8

1

SRN0J-7-GP

51611_DPRSLP_1 51611_VID6 51611_VID5 51611_VID4
51611_VID3 51611_VID2 51611_VID1 51611_VID0

51611_LGATE

51611_CSP

UMA

2

1

PR5327
1UMA 2
330R2F-GP
PC5320 SC33P50V2JN-3GP
UMA

1

Close to choke (L5301)
51611_CSP_R

2

PR5326
UMA NTC-100K-10-GP

1

PC5321 SCD022U50V3KX-GP

51611_CSP_CSN UMA

1

PR5328

1

2

UMA

24K9R2F-L-GP

PR5330 154KR2F-GP

51611_CSP_G

1

2

1

2

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L I0.56uH PCMC104T-R56MN Cyntec DCR:1.6mohm/1.8mohm Isat=25Arms 68.R5610.10D O/P cap: 330U 2.5V EEFSX0D331ER 9mOhm 3Arms PANASONIC/ 79.33719.L01 H/S: SI7686DP/ POWERPAK-8/11mOhm/14mOhm@4.5Vgs/ 84.07686.037 L/S: SiR460DP/ POWERPAK-8/ 4.9mOhm/6.1mohm@4.5Vgs/ 84.00460.037

UMA

PC5322 SC33P50V2JN-3GP

2

51611_CSN

PR5332

1

2

UMA

330R2F-GP

2

UMA

PR5331 43K2R2F-L-GP

X01-0713

51611_GSNS

UMAPC5323

2

1

SC1KP50V2KX-1GP

51611_CSN_R

1

UMA

1

2

PR5333

0R2J-2-GP

+VCC_CORE

2

PC5324
UMA SC1KP50V2KX-1GP

51611_VSNS

2

1

PR5334
UMA 100R2F-L1-GP-U

PG5324

PC5325

2

1

UMA

SC1KP50V2KX-1GP

VCC_AXG_SENSE

1

2

GAP-CLOSE-PW R-3-GP

PG5325

VSS_AXG_SENSE

1

2

2

GAP-CLOSE-PW R-3-GP A

PR5335
UMA 100R2F-L1-GP-U

1

5

4

3

2

2

1

GAP-CLOSE-PWR-3-GP

1 D

Design Current =17.6A 27.2<OCP<32.15A
+CPU_GFX_CORE

PTC5301

C

1

1

1

1

1

DY

2

DY

2

DY

2

2

2

UMA UMA SE330U2VDM-L-GP

SE330U2VDM-L-GP PTC5302
SC22U6D3V5MX-2GP PC5311
SC22U6D3V5MX-2GP PC5312
SC22U6D3V5MX-2GP PC5319

B

A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
TPS51611_+GFX_CORE(UMA)

Size A2

Document Number
Berry

Rev
X00

Date: Thursday, October 22, 2009 1

Sheet 53

of

92

SSID = VIDEO

+3.3V_RUN_VGA

+3.3V_RUN

LVDS CONNECTOR

3.3V_LCD_RUN

1 DY

R5404

2 0R2J-2-GP

+3.3V_RUN

1

GFX_PW R_SRC

1 R5407

2 0R2J-2-GP

DY R5401 10KR2J-3-GP

LCD1

48

100R2J-2-GP

2

R5402 1

2

41

50

1

+LCDVDD

LCD_BRIGHTNESS

2

C5401 SCD1U10V2KX-4GP

2

3

2

1

4

C5402

5

42

6

7

3.3V_LCD_RUN

8

LCD_BRIGHTNESS

9

BLON_OUT_C

10

LCD_CBL_DET#_C

11

LCD_TST_C

2

1

SC1U6D3V2KX-GP

1

DY R5405 100KR2J-1-GP

12

LVDSB_TX2

43

13

LVDSB_TX2#

14

LCD_DET_G

15

LVDSB_TX1

16

LVDSB_TX1#

17

18

19

44

20

LVDSB_TX0 LVDSB_TX0#

21

LVDSB_TXC

22

LVDSB_TXC#

23

1

2

R5408 100KR2J-1-GP

BLON_OUT_C

1

LCD_CBL_DET#_C 2

LCD_TST_C

3

LCD_DET_G

4

RN5401
8 7 6 5

SRN100J-4-GP

24

LVDSA_TXC

25

LVDSA_TXC#

26

R5409

1

2

45

27

28

29

LVDSA_TX2 LVDSA_TX2#

0R3J-0-U-GP

30

LVDSA_TX1

31

LVDSA_TX1#

32

4

3

33

46

34

35

36

37

38

39

LVDSA_TX0 LVDSA_TX0# GPU_LVDS_DATA GPU_LVDS_CLK

USB_CAMERA# USB_CAMERA

DY

L-112UH-1-GP-U TR5401

1

2

40

47

51

+3.3V_CAMERA

49 IPEX-CONN40-2R-GP-U
20.F1093.040

For Camera GND

R5411

1

2

0R3J-0-U-GP

LBKLT_CTL
BLON_OUT LCD_CBL_DET# LCD_TST
USB_PN13 USB_PP13

Camera Power

+3.3V_RUN

R5414

1

2

+3.3V_CAMERA

0R3J-0-U-GP

1

1

DY EC5405
SCD1U16V2KX-3GP

C5403 SC10U6D3V5MX-3GP

2

2

Close to LVDS connector

LVDSB_TXC#

LVDSB_TXC

LVDSA_TXC#

LVDSA_TXC

1

1

1

1

EC5406 EC5407 EC5408 EC5409

DY DY

DY DY

2

2

2

1

LCD_BRIGHTNESS LCD_TST_C
DY DY

2

1

EC5402 SC33P50V2JN-3GP

EC5401 SC33P50V2JN-3GP

SC5D6P50V2CN-1GP

SC5D6P50V2CN-1GP

SC5D6P50V2CN-1GP

SC5D6P50V2CN-1GP

2

2

For EMI request

SSID = Inverter
INVERTER POWER

GFX_PW R_SRC
C5406 SC1KP50V2KX-1GP

2

1

1

2

Change Poly-fuse

C5407 SCD1U50V3KX-GP

F5401

2

1

POLYSW -1D1A24V-GP

Main:69.50007.A41 Second:69.50007.A31

+PW R_SRC

SSID = VIDEO

LCD POWER
+15V_ALW
LCDVDD_EN D5401
BAT54C-U-GP LCD_TST_EN

2

1

+3.3V_RUN

Q5401
1D 2D 3G

D6 D5 S4

+LCDVDD

1

1 R5412
1 C5409

2 330KR2J-L1-GP 2 SCD1U25V2KX-GP

2 DY 1
100KR2J-1-GP R5406

FPVCC_CTL1

SI3456DDV-T1-GE3-GP

R5416 150R3J-L-GP

Q5402

4

3

LCDVDD_1

2

5

2

6

1

2N7002EDW -GP
84.27002.F3F

+5V_ALW Q5403

3 LCDVCC_EN

2 R1

IN

R2

1 R5415 3 OUT 1 GND

DDTC144EUA-7F-GP

<Core Design>

2 100KR2J-1-GP
FPVCC_CTL3

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

LCD/Inverter Connector

Size A3

Document Number
Berry

Date: Thursday, October 22, 2009

Sheet 54

of

Rev
X00
92

5
LVDS Channel A

PCH_LVDSA_TX2# PCH_LVDSA_TX2 PCH_LVDSA_TXC# PCH_LVDSA_TXC

RN5501

5

4

6

3

7

2

8

1

UMA SRN0J-7-GP

D

Impedance:85 ohm

RN5503

GPU_LVDSA_TX2# GPU_LVDSA_TX2 GPU_LVDSA_TXC# GPU_LVDSA_TXC

4

5

3

6

2

7

1

8

Impedance:100 ohm

DIS SRN0J-7-GP

PCH_LVDSA_TX0# PCH_LVDSA_TX0 PCH_LVDSA_TX1# PCH_LVDSA_TX1

RN5507

5

4

6

3

7

2

8

1

Impedance:85 ohm

UMASRN0J-7-GP

GPU_LVDSA_TX0# GPU_LVDSA_TX0 GPU_LVDSA_TX1# GPU_LVDSA_TX1

RN5508

4

5

3

6

2

7

1

8

Impedance:100 ohm

DISSRN0J-7-GP

C

LVDS Channel B

PCH_LVDSB_TXC# PCH_LVDSB_TXC PCH_LVDSB_TX0# PCH_LVDSB_TX0
Impedance:85 ohm

RN5505

5

4

6

3

7

2

8

1

UMA SRN0J-7-GP

GPU_LVDSB_TXC# GPU_LVDSB_TXC GPU_LVDSB_TX0# GPU_LVDSB_TX0

RN5510

4

5

3

6

2

7

1

8

B

Impedance:100 ohm

DISSRN0J-7-GP

PCH_LVDSB_TX1# PCH_LVDSB_TX1 PCH_LVDSB_TX2# PCH_LVDSB_TX2

RN5509

5

4

6

3

7

2

8

1

Impedance:85 ohm

UMASRN0J-7-GP

GPU_LVDSB_TX1# GPU_LVDSB_TX1 GPU_LVDSB_TX2# GPU_LVDSB_TX2
Impedance:100 ohm

RN5506

4

5

3

6

2

7

1

8

DIS SRN0J-7-GP

A

5

4
LVDSA_TX2# LVDSA_TX2 LVDSA_TXC# LVDSA_TXC
Impedance:90 ohm

LVDSA_TX0# LVDSA_TX0 LVDSA_TX1# LVDSA_TX1

Impedance:90 LVDSA_TX0# LVDSA_TX0 LVDSA_TX1# LVDSA_TX1

ohm

3

2

Panel BL brightness/Power En/BL En

PCH_VGA_BLEN PCH_LCDVDD_EN PCH_LBKLT_CTL
VGA_BLEN VGA_LBKLT_CTL VGA_LCDVDD_EN

RN5502

5

4

6

3

7 UMA 2

8

1

SRN0J-7-GP

RN5504

5

4

6

3

7 DIS 2

8

1

SRN0J-7-GP

PANEL_BLEN LCDVDD_EN LBKLT_CTL

1 D
C

LVDSB_TXC# LVDSB_TXC LVDSB_TX0# LVDSB_TX0
Impedance:90 ohm
LVDSB_TXC# LVDSB_TXC LVDSB_TX0# LVDSB_TX0
LVDSB_TX1# LVDSB_TX1 LVDSB_TX2# LVDSB_TX2
Impedance:90 ohm
LVDSB_TX1# LVDSB_TX1 LVDSB_TX2# LVDSB_TX2

4

3

B

<Core Design>

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

LVDS_Switch

Size

Document Number

Rev

Berry

X00

Date: Thursday, October 22, 2009

Sheet 55

of

92

2

1

5

4

SSID = VIDEO HDMI Level Shifter & CONNECTOR

+3.3V_RUN

1 1

+3.3V_RUN

R5702 DY
4K7R2J-2-GP

2 2

R5701 4K7R2J-2-GP
DY Impedance:100 ohm

1

1

1

1

1

C5717

C5716

C5715

C5714

C5701

UMA UMA UMA UMA UMA

D

HDMI_CCT2 HDMI_CCT1

SCD1U10V2KX-4GP

2

SCD1U10V2KX-4GP

2

SCD1U10V2KX-4GP

2

SCD1U10V2KX-4GP

2

SCD1U10V2KX-4GP

2

35 34

2 11 15 21 26 33 40 46

U5701

+3.3V_RUN

HDMI_PCH_CLK# HDMI_PCH_CLK
HDMI_PCH_DATA0# HDMI_PCH_DATA0
HDMI_PCH_DATA1# HDMI_PCH_DATA1
HDMI_PCH_DATA2# HDMI_PCH_DATA2

38 39

IN_D1IN_D1+

41 42

IN_D2IN_D2+

44 45

IN_D3IN_D3+

47 48

IN_D4IN_D4+

R5703 2 UMA 1 4K7R2J-2-GP

DY R5704 2

1 4K7R2J-2-GP

1

R5706
4K7R2J-2-GP UMA +3.3V_RUN

HDMI_PC0 3

HDMI_PC1

4

R5705

2 UMA 1 HDMI_REXT 6

499R2F-2-GP

10

HDMI_OE#

25

1 UMA 2 HDMI_DDC_EN

32

R5708

4K7R2J-2-GP

PC0 PC1
REXT RT_EN# OE# DDC_EN

VCC VCC VCC VCC VCC VCC VCC VCC

UMA

NC#35 NC#34

Close to HDMI Connector

OUT_D1OUT_D1+

23 22

OUT_D2OUT_D2+

20 19

OUT_D3OUT_D3+

17 16

OUT_D4OUT_D4+

14 13

HDMI_LS_TXC# HDMI_LS_TXC
HDMI_LS_TX0# HDMI_LS_TX0
HDMI_LS_TX1# HDMI_LS_TX1
HDMI_LS_TX2# HDMI_LS_TX2

SRN0J-6-GP 1
2 UMA
SRN0J-6-1GP
2 UMA
SRN0J-6-1GP
2 UMA
SRN0J-6-1GP
2 UMA

RN5703
4 3 RN5704
4 3 RN5706
4 3 RN5707
4 3

HDMI_CLK# HDMI_CLK
HDMI_DATA0# HDMI_DATA0
HDMI_DATA1# HDMI_DATA1
HDMI_DATA2# HDMI_DATA2

SDA SCL HPD

8 9 7

HPD_SINK SDA_SINK SCL_SINK

30 29 28

HPD_HDMI_CON DDC_DATA_HDMI DDC_CLK_HDMI

1

PCH_HDMI_DATA PCH_HDMI_CLK
HDMI_PCH_DET
DY R5707 20KR2J-L2-GP

2

GND GND GND GND GND GND GND GND GND GND GND

2

1 5 12 18 24 27 31 36 37 43 49

Change from 5.1K to 4.7K.

PS8101-GP

1st Parade 71.P8101.003

2nd Pericom 71.03411.B03

C
HDMI DISCRETE/ UMA Co-lay
Close to Level Shift Close to HDMI Connector

HDMI_PCH_CLK# HDMI_PCH_CLK HDMI_PCH_DATA0# HDMI_PCH_DATA0
HDMI_PCH_DATA1# HDMI_PCH_DATA1 HDMI_PCH_DATA2# HDMI_PCH_DATA2

RN5708 SRN0J-6-GP

2 1

DIS

3 4

2 1

DIS

3 4

RN5709 SRN0J-6-GP

RN5710 SRN0J-6-GP

2 1

DIS

3 4

2 1

DIS

3 4

RN5711 SRN0J-6-GP

HDMI_CLK#_R HDMI_CLK_R
HDMI_DATA0#_R HDMI_DATA0_R

C5706 C5707
C5708 C5709

1DIS 2 SCD1U16V2KX-3GP 1DIS 2 SCD1U16V2KX-3GP 1DIS 2 SCD1U16V2KX-3GP 1DIS 2 SCD1U16V2KX-3GP

HDMI_DATA1#_R HDMI_DATA1_R
HDMI_DATA2#_R HDMI_DATA2_R

C5713 C5710
C5711 C5712

1DIS 2 SCD1U16V2KX-3GP 1DIS 2 SCD1U16V2KX-3GP 1DIS 2 SCD1U16V2KX-3GP 1DIS 2 SCD1U16V2KX-3GP

Impedance:100 ohm

Impedance:100 ohm

Impedance:100 ohm
HDMI_CLK# HDMI_CLK
HDMI_DATA0# HDMI_DATA0
HDMI_DATA1# HDMI_DATA1
HDMI_DATA2# HDMI_DATA2

2DIS 1 499R2F-2-GP
2DIS 1 499R2F-2-GP
2DIS 1 499R2F-2-GP
2DIS 1 499R2F-2-GP
2DIS 1 499R2F-2-GP
2DIS 1 499R2F-2-GP
2DIS 1 499R2F-2-GP
2DIS 1 499R2F-2-GP

R5715 R5716 R5717 R5718 R5719 R5720 R5721 R5722

HDMI_PLL_GND

DIS .

Q5703

2N7002E-1-GP

B

. ... 84.2N702.D31

+5V_RUN

3

2

HDMI CONN

HDMI1 22 20 1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 23
SKT-HDMI19P-69-GP
22.10296.211

HDMI_DATA2
HDMI_DATA2# HDMI_DATA1 HDMI_DATA1# HDMI_DATA0 HDMI_DATA0#
HDMI_CLK HDMI_CLK#
DDC_CLK_HDMI DDC_DATA_HDMI

+3.3V_RUN

1

UMA

R5709 20KR2J-L2-GP

2

HDMI_OE#

D

+5V_RUN

UMA .
. ...

Q5701 2N7002E-1-GP
84.2N702.D31

S

G

HPD_HDMI_CON

1

C5705 SCD1U16V2KX-3GP

2

+3.3V_RUN_VGA

HPD_HDMI_CON

3

DIS

1

2HDMI_HPD_B 1

R5711

150KR2J-L1-GP DIS

Q5702 PMBS3904-1-GP

2

1

R5710
DY 200KR2J-L1-GP

2

R5712 DIS
10KR2J-3-GP

1

HDMI_HPD_DET

2

+3.3V_RUN_VGA

+5V_RUN

3

4

4

3

+3.3V_RUN_VGA
+5V_RUN 1 7 8 4

RN5702

SRN2K2J-1-GP

U5702

DY 1OE
2OE

1A 2A

2 5

VCC GND

1B 2B

3 6

2

1

RN5701
DYSRN1K5J-GP

TSCBTD3305CPW R-GP

1

2

5V Tolerance
GPU_HDMI_CLK GPU_HDMI_DATA
DDC_CLK_HDMI DDC_DATA_HDMI

GPU_HDMI_CLK GPU_HDMI_DATA

RN5705

2 1

DIS

3 4

SRN0J-6-GP

G D
S

1

DY R5714 100KR2J-1-GP

1 D C B

2

A

A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

HDMI Level Shifter/Connector

Size A2

Document Number
Berry

Rev
X00

Date: Thursday, October 22, 2009

Sheet 57

of

92

5

4

3

2

1

5

4

3

2

SSID = User.Interface

ITP Connector

H_CPURST# use pull-up Resistor close

D

ITP connector 500 mil ( max ),

others place near CPU side.

1 D

C
SSID = Thermal
B
A 5

CPU

ITP Connector

TCK(PIN AC5)

TCK(PIN 5)

FBO(PIN 11)
C

EMC2102_FAN_TACH EMC2102_FAN_DRIVE
4

Fan Connector
B

*Layout* 15 mil

AFTP5801

1

FAN1 5 3 2
1 4
FOX-CON3-6-GP-U

K

1

C5801 SC10U6D3V5MX-3GP

2

A

D5801 RB551V-30-2GP
20.D0210.103

3

31

AFTP5802 AFTP5803

1 EMC2102_FAN_TACH 1 EMC2102_FAN_DRIVE

<Core Design>

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

ITP/Fan Connector

Size

Document Number

A3

Berry

Rev
X00

Date: Thursday, October 22, 2009

Sheet 58

of

92

2

1

SSID = SATA

SATA HDD Connector

+3.3V_RUN

1

1

DY DY C5904
SC10U6D3V5MX-3GP

C5901 SCD1U16V2KX-3GP

2

2

+5V_RUN
C5905 SC10U6D3V5MX-3GP

1

1

C5906 SCD1U16V2KX-3GP

2

2

HDD1

P1 P2 P3

V33 V33 V33

P7 P8 P9

V5 V5 V5

P13 P14 P15

V12 V12 V12

SATA_TXP0 SATA_TXN0

SATA_RXP0_C SATA_RXN0_C

SCD01U50V2KX-1GP 1 SCD01U50V2KX-1GP 1

2 C5903 2 C5902

S2 S3

A+ A-

SATA_RXP0 SATA_RXN0

S6 S5

B+ B-

16 17 18

16 17 18

GND GND GND GND GND GND GND GND

S1 S4 S7 P4 P5 P6 P10 P12

DAS/DSS P11

SKT-SATA7P-15P-17-GP
62.10065.C71

ODD Connector

ODD1

8 NP1

S1

S2

S3

S4

S5

SATA_RX1-_C

S6

SATA_RX1+_C

S7

P1 P2 P3 P4 P5 P6 NP2 9

SKT-SATA7P+6P-42-GP
62.10065.581

SCD01U50V2KX-1GP 1 SCD01U50V2KX-1GP 1

2

2 C5907 2 C5908

SATA_TXP1 SATA_TXN1
SATA_RXN1_C SATA_RXP1_C

SATA_RX- and SATA_RX+ Trace Length match within 20 mil
+5V_RUN

1

1

C5909 SCD1U10V2KX-4GP

C5910 SC10U6D3V5MX-3GP

2

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

Size A3

Document Number
Berry

HDD/ODD

Date: Thursday, October 22, 2009

Sheet 59

of

Rev
X00
92

5

4

3

SSID = AUDIO

Speaker Connector
D

2

1

LINE1
OUT
D

5

AUD_SPK_LAUD_SPK_L+ AUD_SPK_RAUD_SPK_R+
C

EC6008 SCD1U16V2KX-3GP

EC6007 SCD1U16V2KX-3GP

EC6004 SC100P50V2JN-3GP

EC6003 SC100P50V2JN-3GP

EC6002 SC100P50V2JN-3GP

EC6001 SC100P50V2JN-3GP

2

1

2

1

DY DY DY DY

2

1

2

1

SPK1 FOX-CON4-19-GP
1

AUD_HP1_JD#

2 3

AUD_HP1_JACK_L2

4

AUD_HP1_JACK_R2

6

20.F0711.004
SEC. 20.F0693.004

AUD_HP1_JACK_L2 AUD_HP1_JACK_R2
EC6005 SC1KP50V2KX-1GP

1

1

BLM18BD601SN1D-GP

L6001

1

2

1

2

L6002 BLM18BD601SN1D-GP

EC6006 SC1KP50V2KX-1GP

1

AUD_HP1_JD# AUD_HP1_JACK_L1
AUD_HP1_JACK_R1

1

2

2

2

2

JACK_AGND JACK_AGND

JACK_AGND JACK_AGND

LINEOUT1 6 5 2
4 1 3 7 8
PHONE-JK383-GP

AFTP6001 AFTP6005 AFTP6007 AFTP6009

1 AUD_SPK_L1 AUD_SPK_L+ 1 AUD_SPK_R1 AUD_SPK_R+

1 AFTP6002

AFTP6003 AFTP6004 AFTP6008

1 AUD_HP1_JD# 1 AUD_HP1_JACK_L1 1 AUD_HP1_JACK_R1

600ohm 100MHz 200mA 0.5ohm DC

AFTP6006 1 22.10133.K31

C JACK_AGND

MIC IN

Internal

AUD_VREFOUT_B

Microphone

1

2

RN6001 SRN4K7J-8-GP

INT_MIC_L_R

MIC1 is in DIP

1

MIC1

MICROPHONE-40-GP-U1

2

1

4

3

B MIC_IN_L MIC_IN_R

MICIN1

EC6009

23.42143.001

8

SC1KP50V2KX-1GP

7

2

B

3

1

2

1

MIC_IN_L_C

4

R6001

0R3J-0-U-GP

2

5

1

2

MIC_IN_R_C

6

R6002

0R3J-0-U-GP

PHONE-JK383-GP

AFTP6011 AFTP6012 AFTP6013

1 MIC_IN_L_C 1 MIC_IN_R_C 1 EXT_MIC_JD#

EXT_MIC_JD#

EC6010 SC100P50V2JN-3GP

2

1

2

1

EC6011

22.10133.K31

1

AFTP6010

JACK_AGND

JACK_AGND

SC100P50V2JN-3GP

Close Jack
A

width 15mil

2 DY 1

R6004

0R2J-2-GP

1 R6003

2 0R3J-0-U-GP

AUD_AGND

JACK_AGND

5

4

3

<Core Design>

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

Audio Jack

Size

Document Number

A3

Berry

Rev
X00

Date: Thursday, October 22, 2009

Sheet 60

of

92

2

1

5
SSID = Flash.ROM
D

4

3

SPI FLASH ROM (4M byte) for PCH

+3.3V_RUN

1

5

6

7

8

RN6201 SRN4K7J-10-GP

C6201 DY
SC10U6D3V5MX-3GP

2

2

1

2
+3.3V_RUN C6202 SCD1U16V2KX-3GP

4

3

2

1

PCH_SPI_HOLD_0#

PCH_SPI_CS0# PCH_SPI_DI

PCH_SPI_CS0#

1

2

1

R6202 15R2J-GP
DY EC6202
SC4D7P50V2CN-1GP

2

U6201

PCH_SPI_DI_R PCH_SPI_W P#

1 2 3 4

CS# SO WP# GND

+3.3V_RUN

VCC NC#7
SCK SI

8 7 6 5

PCH_SPI_HOLD_0#

1

1

MX25L3205DM2I-12G-GP

DY DY EC6203

EC6204

SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

PCH_SPI_CLK PCH_SPI_DO

1 D

2

2

C

SPI FLASH ROM (256K byte) for KBC

+KBC_PW R

C +KBC_PW R

1

1

5

6

7

8

RN6202 SRN100KJ-5-GP

C6203
DY SC10U6D3V5MX-3GP

2

2

C6204 SCD1U16V2KX-3GP

4

3

2

1

EC_SPI_HOLD#

EC_SPI_CS# EC_SPI_DI EC_SPI_W P#_R

R6205 1 R6206 1

1

2 0R2J-2-GP 2 0R2J-2-GP

EC_SPI_DI_R EC_SPI_W P#

U6202

1 2 3 4

CS# SO WP# GND

VCC HOLD#
SCLK SI

8 7 6 5

+KBC_PW R EC_SPI_HOLD#

EC_SPI_CLK EC_SPI_DO

1

1

1

B

DY DY EC6201
SC4D7P50V2CN-1GP

R6208 100KR2J-1-GP

DY DY MX25L2005C-12G-GP EC6205

EC6206

B

2

SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP

2

2

2

SSID = RBATT

+3.3V_RTC_LDO

+RTC_CELL

U6203

2 +RTC_VCC

3

R6210

1

RTC_PWR 1

2

2

C6205

1KR2J-1-GP

SC1U6D3V2KX-GP

SDMG0340LC7F-GP-U

1

1 AFTP6203

A

Width=20mils

AFTP6202

1 +RTC_VCC

RTC1

1 2 NP1 NP2

PWR GND NP1 NP2

BAT-CON2-1-GP-U

62.70001.011

5

4

3

<Core Design>

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

Flash/RTC

Size

Document Number

A3

Berry

Rev
X00

Date: Thursday, October 22, 2009

Sheet 62

of

92

2

1

5

4

3

2

SSID = USB
IO Board USB Power

Close to I/O connector

D
Main RT9715BGF P/N:74.09715.B79
SEC G547F2P81U P/N: 74.00547.A79

+5V_ALW

1

C6301

DY

at least 80 mil
USB_PW R_EN#

Support 2A

U6301

1 2 3 4

GND VIN VIN EN#

VOUT VOUT VOUT FLG#

8 7 6 5

RT9715BGF-GP

at least 80 mil

+5V_USB1

1

C6302 SC1U10V2KX-1GP

2

2

USB_OC#8_9

SCD1U10V2KX-4GP

CRT Board USB Power
C

1

+5V_ALW
DY

at least 80 mil
USB_PW R_EN#

2

C6303 SCD1U10V2KX-4GP

Close to CRT Board connector

Support 2A

U6302

1 2 3 4

GND VIN VIN EN#

VOUT VOUT VOUT FLG#

8 7 6 5

RT9715BGF-GP

at least 80 mil

+5V_USB2

1

C6304 SC1U10V2KX-1GP

2

USB_OC#0_1

B

1 D C B

<Core Design>

A

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

USB Power SW

Size

Document Number

Berry

Date: Thursday, October 22, 2009

Sheet 63

of

Rev
X00
92

5

4

3

2

1

R1 R2
R1 R2
R1 R2
R1 R2
R1 R2

5

4

3

SSID = User.Interface

Power LED(White)

Q6602

+5V_ALW

E

PW RLED#_C

B

D

C

LED_PW R

1

2

PW R_LED_B

R6601

220R2J-L2-GP

1

W HITE_LED#_KBC SATA_LED#

RN6601

1

4 W HITE_LED_BAT#

2

3 SATA_LED#_C

EC6601

PDTA143ET-GP
84.00143.M11

2

DYSC220P50V2KX-3GP

1 R6603

2 POWER_SW_LED_B 100R2J-2-GP

SRN15KJ-3-GP

AMBER_LED#_KBC PW RLED#

RN6602

1

4 AMBER_LED_BAT#

2

3

PW RLED#_C

SATA HDD LED(White)

SRN15KJ-3-GP

+5V_RUN

Q6601

SATA_LED#_C

B

E

C

SATA_LED_R

R6604

2

1

330R2J-3-GP

1

PDTA143ET-GP
84.00143.M11

2

DY

EC6604 SC220P50V2KX-3GP

SATA_LED

C

Battery LED1(White)

Q6603

+5V_ALW

W HITE_LED_BAT#

B

E

C

W HITE_LED_BAT

R6602

2

1

BAT_W HITE

1

PDTA143ET-GP
84.00143.M11

2

DY

330R2J-3-GP EC6602 SC220P50V2KX-3GP

Battery LED2(Amber)

Q6604

+5V_ALW

AMBER_LED_BAT#

B

E

R6606

C

AMBER_LED_BAT

1

2

BAT_AMBER

PDTA143ET-GP

1

330R2J-3-GP

B

84.00143.M11

DY EC6603 SC220P50V2KX-3GP

2

PW R_LED_B
SATA_LED BAT_W HITE BAT_AMBER

LEDBD1 7
1
2 3 4 5 6
8
ACES-CON6-13-GP

1 D C B

2

Power button LED(White)

KBC_PW RBTN#

1 R6605

2 100R2J-2-GP

PW RBTN1 5

1

+5V_ALW

KBC_PW RBTN#_C

2

3

POW ER_SW _LED_B

4

Q6605 6

E

PW R_BTN_LED#

1

2 PWR_BTN_LED#_C

B

R6607

15KR2J-1-GP

C

POWER_SW_LED_R 1 DY 2 POWER_SW_LED_B

ACES-CON4-10-GP-U

A

R6608

100R2J-2-GP

20.K0320.004

<Core Design>

A

PDTA143ET-GP

84.00143.M11

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

LED Bard/Power Button

Size A3

Document Number
Berry

Rev
X00

Date: Thursday, October 22, 2009

Sheet 66

of

92

5

4

3

2

1

5

4

SSID = KBC

D

Internal KeyBoard Connector

KB1
31 1

1

AFTP6801

KB_DET#

2

KROW 7

1

3

KROW 6

1

AFTP6802

4

KROW 4

1

AFTP6803

5

KROW 2

1

AFTP6804

6

KROW 5

1

7

KROW 1

1

AFTP6805 AFTP6806

8

KROW 3

1

AFTP6807

9

KROW 0

1

AFTP6808

10

KCOL5

1

AFTP6809

11

KCOL4

1

12

KCOL7

1

13

KCOL6

1

AFTP6810 AFTP6811 AFTP6812

KROW [0..7]

14

KCOL8

1

AFTP6813

15

KCOL3

1

16

KCOL1

1

17

KCOL2

1

AFTP6814 AFTP6815 AFTP6816

KCOL[0..16]

18

KCOL0

1

AFTP6817

19

KCOL12

1

AFTP6818

C

20

KCOL16

1

AFTP6819

21

KCOL15

1

22

KCOL13

1

AFTP6821 AFTP6823

23

KCOL14

1

AFTP6822

24

KCOL9

1

AFTP6824

25

KCOL11

1

AFTP6825

26

KCOL10

1

27

AFTP6826 AFTP6827

28

29

30

1

32

AFTP6828

ACES-CON30-3-GP

20.K0421.030 Sec. 20.K0259.030

B

3

2

1

SSID = Touch.Pad

D
TouchPad Connector

+5V_RUN

+5V_RUN

C6801 SCD1U16V2KX-3GP

1

1

2

2

RN6801 SRN10KJ-5-GP

TPAD1 6

4

3

TPCLK TPDATA

4

3

2

C

1

1

C6802 DY DY C6803

SC33P50V2JN-3GP

SC33P50V2JN-3GP

2

2

1 AFTP6820

1 5 ACES-CON4-10-GP-U
20.K0320.004

AFTP6829 AFTP6830 AFTP6831

1 +5V_RUN 1 TPCLK 1 TPDATA

B

A

<Core Design>

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

Key Board/Touch Pad

Size A3

Document Number
Berry

Rev
X00

Date: Thursday, October 22, 2009

Sheet 68

of

92

5

4

3

2

1

5

4

3

2

AFTP6901 AFTP6902

1 +3.3V_ALW 1 LID_CLOSE#_1

D

LID_CLOSE#
C

+3.3V_ALW

1

2

+3.3V_ALW

1

DY DY

12

R6901 100KR2J-1-GP

LID_CLOSE#

2

R6902

C6902 SCD047U16V2KX-1-GP

C6903 SCD1U6D3V2KX-GP

2

1 0R2J-2-GP

LID_CLOSE#_1

HALLSW1

2 3

VDD OUT

VSS

1

S-5711ACDL-M3T1S-GP

AFTP6903

1

1 D
C

B

B

<Core Design>

Wistron Corporation

A

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

A

Taipei Hsien 221, Taiwan, R.O.C.

Title

Hall Sensor

Size Document Number

A4

Berry

Rev
X00

Date: Thursday, October 22, 2009

Sheet 69

of

92

5

4

3

2

1

5 D
C

4

3

+3.3V_RUN
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LPC_LFRAME# PLT_RST#
PCLK_FWH

DB1

1

2

3

4

5

6 7

DY

8

9

10

11

12

MLX-CON10-7-GP

20.D0183.110

B

A

5

4

3

2

1

D

C

B

<Core Design>

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

A

Taipei Hsien 221, Taiwan, R.O.C.

Title

Dubug connector

Size Document Number

A4

Berry

Date: Thursday, October 22, 2009
2

Sheet 70

of

1

Rev
X00
92

5

4

3

2

SSID = User.Interface

D

Bluetooth Module conn.

AFTP7301
AFTP7302
AFTP7304 AFTP7305 AFTP7314

1 BLUETOOTH_DET#
W LAN_ACT 1 BDC_ON
BLUETOOTH_EN 1 BT_LED 1 BLUETOOTH_GPIO3 1 BLUETOOTH_GPIO5

BT1

15 NP1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

NP2

16

HRS-CONN14D-GP

20.F0987.014

BT_ACT
USB_PP5 USB_PN5

1

AFTP7313

2

1

+3.3V_RUN
C7301 SC2D2U10V3KX-1GP

USB_PP5 USB_PN5
BT_ACT BLUETOOTH_EN
W LAN_ACT
C

BT_ACT BLUETOOTH_EN W LAN_ACT

AFTP7316 AFTP7317 AFTP7315 AFTP7318 AFTP7319 AFTP7320

1 WLAN_ACT 1 BLUETOOTH_EN 1 BT_ACT 1 +3.3V_RUN 1 USB_PP5 1 USB_PN5

1

EC7302

1

1

DY DY

R7304 10KR2J-3-GP

SC220P50V2KX-3GP

R7303 100KR2J-1-GP

2

2

2

B

1 D C B

A

<Core Design>

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

Bluetooth

Size

Document Number

A3

Berry

Rev
X00

Date: Thursday, October 22, 2009

Sheet 73

of

92

5

4

3

2

1

5

4

IO Board CONN 80 pin

D

USB(ESATA)

USB_PP9

USB_PN9

WWAN USB

USB_PP11 USB_PN11

USB1

USB_PN8 USB_PP8

WLAN USB

USB_PP2 USB_PN2

WWAN PCIE

E51_RXD E51_TXD
PCIE_RXP4 PCIE_RXN4

WWAN PCIE

PCIE_TXP4 PCIE_TXN4

WWAN/WLAN SMBUS

PCH_SMBDATA PCH_SMBCLK

+DC_IN_SS

C
W IFI_RF_EN W W AN_CLKREQ# W W AN_RADIO_DIS#
PSID_DISABLE#

LAN PCIE

PCIE_RXP3 PCIE_RXN3

LAN PCIE

PCIE_TXP3 PCIE_TXN3

B

3

2

IOBD1

85

NP1

86

84

2

1

4

3

6

5

8

7

10

9

12

11

14

13

16

15

18

17

20

19

22

21

24

23

26

25

28

27

30

29

32

31

34

33

36

35

38

37

40

39

42

41

44

43

46

45

48

47

50

49

52

51

54

53

56

55

58

57

60

59

62

61

64

63

66

65

68

67

70

69

72

71

74

73

76

75

78

77

80

79

83

81

82

NP2

ACES-CONN80D-GP

20.F1009.080

SATA_TXN4
SATA_TXP4
SATA_RXN4_C SATA_RXP4_C

SATA(ESATA) SATA(ESATA)

PCIE_TXP2 PCIE_TXN2
PCIE_RXP2 PCIE_RXN2

WLAN PCIE WLAN PCIE

CLK_PCIE_W LAN CLK_PCIE_W LAN#
CLK_PCIE_LAN CLK_PCIE_LAN#
CLK_PCIE_W W AN CLK_PCIE_W W AN#

WLAN CLK LAN CLK WWAN CLK

at least 80 mil
+5V_ALW +3.3V_RUN

+5V_USB1

+3.3V_ALW +1.5V_RUN
AD_OFF PM_LAN_ENABLE PLT_RST# W LAN_CLKREQ# PCIE_W AKE# BT_ACT
W LAN_ACT PSID_EC

1 D C B

A

<Core Design>

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

IO Board Connector

Size

Document Number

A3

Berry

Rev
X00

Date: Thursday, October 22, 2009

Sheet 76

of

92

5

4

3

2

1

5

4

3

2

CRT Board Connector

CRTBD1

21

1

at least 80 mil

2

+5V_USB2

3

4

+5V_RUN

5

6 7

USB_PN1 USB_PP1

USB3 PORT

8

9 10

USB_PN0 USB_PP0

USB2 PORT

11

D

12

CRT_RED

13 14

CRT_GREEN CRT_BLUE

CRT RGB

15 16

CRT_HSYNC_CON CRT_VSYNC_CON

CRT H/VSYNC

17 18

CRT_DDCCLK_CON CRT_DDCDATA_CON

CRT SMBUS

19

20

22

ACES-CON20-1-GP-U

20.F0772.020 SEC. 20.F1035.020

CRT RGB

CRT Hsync & Vsync level shift

Close to CRT Board CONN

Close to CRT Board CONN Filter design on CRT Board

VGA_CRT_RED VGA_CRT_GREEN VGA_CRT_BLUE

RN7701

1

8

2

7

3 4

DIS

6 5

SRN0J-7-GP

RN7702

1

8

C

PCH_CRT_RED PCH_CRT_GREEN PCH_CRT_BLUE

2

7

3 4

UMA

6 5

SRN0J-7-GP

CRT_RED CRT_GREEN CRT_BLUE

3.3V Tolerance
VGA_CRT_HSYNC VGA_CRT_VSYNC
PCH_CRT_HSYNC PCH_CRT_VSYNC
2.5V Tolerance?

RN7703

SRN0J-6-GP

1

4

2 DIS 3

2 1

UMA

3 4

RN7704 SRN0J-6-GP

CRT_HSYNC_IN CRT_VSYNC_IN
U7701

2 5

6 3

RN7706

2

3

1

4

SRN0J-6-GP
CRT_HSYNC_OUT CRT_VSYNC_OUT

RN7705

4

1

3 DY 2

SRN33J-5-GP-U

+5V_RUN

CRT_HSYNC_CON CRT_VSYNC_CON

1

DY

C7702 SCD1U16V2KX-3GP

2

VCC 8

Y1 Y2

A1 A2

TC7W T125FU-GP

DY

G1# G2#

CRT DDCDATA & DDCCLK level shift

4 GND

1 7

Need Level Shift
PCH_CRT_DDCDATA PCH_CRT_DDCCLK
5V Tolerance
VGA_CRT_DDCDATA VGA_CRT_DDCCLK

+3.3V_RUN
Pull High 5V Design on CRT Board

1

2

RN7707
UMASRN2K2J-1-GP

+3.3V_RUN

4

3

RN7709

2 1

DIS

3 4

SRN0J-6-GP

Q7701

4

3

U5MA 2

6

1

2N7002EDW -GP
84.27002.F3F

CRT_DDCDATA_CON CRT_DDCCLK_CON

B

1 D C B

A

A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

CRT Board Connector

Size A2

Document Number
Berry

Rev
X00

Date: Thursday, October 22, 2009

Sheet 77

of

92

5

4

3

2

1

5
SSID = SDIO
D

4

3

2

Card Reader connector

+3.3V_RUN

CARDBD1

7

C

1

CLK_48M_CARD
USB_PN4 USB_PP4

2 3 4 5 6
8

MLX-CON6-21-GP
20.F1035.006

B

1 D C B

<Core Design>

Wistron Corporation

A

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

A

Taipei Hsien 221, Taiwan, R.O.C.

Title

CARD Reader CONN

Size Document Number

A4

Berry

Rev
X00

Date: Thursday, October 22, 2009

Sheet 78

of

92

5

4

3

2

1

5

4

3

2

1

H1 HTE95BE95R29-R-5-GP

H2 HTE95BE95R29-R-5-GP

H3

H4

H5

H6

HTE95BE95R29-R-5-GP HTE95BE95R29-R-5-GP HTE95BE95R29-R-5-GP HTE95BE95R29-R-5-GP

H7 HTE95BE95R29-R-5-GP

H8 HTE95BE95R29-R-5-GP

H9 HTE95BE95R29-R-5-GP

D

D

1

1 1
1

1 1 1
1 1
1 1 1 1

1

H10 HOLE335R115-GP

CPU Thermal module hole

HTML1

HTML2

HTML3

HOLE197R166-GP HOLE197R166-GP HOLE197R166-GP

GPU Thermal module hole
HGPU1 STF237R117H83-1-GP

stand off
HBT1 STF237R115H123-GP

1

C

C

DY

DY

DY

EMI Reserve

+PWR_SRC

+VGFXCORE_PWR_SRC

+PWR_SRC_VTT

+PWR_SRC_1D5V

1

1

1

1

1

1

1

1

1

1

EC7901

EC7902

EC7904

EC7903

EC7905

EC7907

EC7909

EC7906

DY

2

2

2

DY DY DY DY

2

2

2

DY DY

2

B

EC7911

EC7916

2

DY

DY

2

DY

2

B

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

SCD1U25V2KX-GP

EMI Reserve
SPR1 SPRING-58-GP
DY
A

1

5

4

<Core Design>

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

A

Taipei Hsien 221, Taiwan, R.O.C.

Title

UNUSED PARTS/EMI Capacitors

Size Document Number

Rev

A4

Berry

X00

Date: Thursday, October 22, 2009

Sheet 79

of

92

3

2

1

5
PEG_TXP[0..15] PEG_TXN[0..15]

VGA1A

4

3

1 OF 8

PEG_RXP[0..15] PEG_RXN[0..15]

PEG_TXP0 PEG_TXN0

AA38 Y37

PCIE_RX0P PCIE_RX0N

PCIE_TX0P PCIE_TX0N

Y33 Y32

DIS

PEG_C_RXP0 C8001 1

2 SCD1U16V2KX-3GP PEG_RXP0

PEG_C_RXN0 C8002 1DIS 2 SCD1U16V2KX-3GP PEG_RXN0

DIS

D

PEG_TXP1 PEG_TXN1

Y35 W36

PCIE_RX1P PCIE_RX1N

PCIE_TX1P PCIE_TX1N

W33 W32

PEG_C_RXP1 C8003 1

2 SCD1U16V2KX-3GP PEG_RXP1

PEG_C_RXN1 C8004 1DIS 2 SCD1U16V2KX-3GP PEG_RXN1

PEG_TXP2 PEG_TXN2

W38 V37

PCIE_RX2P PCIE_RX2N

PCIE_TX2P PCIE_TX2N

U33 U32

DIS

PEG_C_RXP2 C8005 1

2 SCD1U16V2KX-3GP PEG_RXP2

PEG_C_RXN2 C8006 1DIS 2 SCD1U16V2KX-3GP PEG_RXN2

PEG_TXP3 PEG_TXN3

V35 U36

PCIE_RX3P PCIE_RX3N

PCIE_TX3P PCIE_TX3N

U30 U29

DIS

PEG_C_RXP3 C8008 1

2 SCD1U16V2KX-3GP PEG_RXP3

PEG_C_RXN3 C8007 1DIS 2 SCD1U16V2KX-3GP PEG_RXN3

PEG_TXP4 PEG_TXN4

U38 T37

PCIE_RX4P PCIE_RX4N

PCIE_TX4P PCIE_TX4N

T33 T32

DIS

PEG_C_RXP4 C8009 1

2 SCD1U16V2KX-3GP PEG_RXP4

PEG_C_RXN4 C8010 1DIS 2 SCD1U16V2KX-3GP PEG_RXN4

PEG_TXP5 PEG_TXN5

T35 R36

PCIE_RX5P PCIE_RX5N

PCIE_TX5P PCIE_TX5N

T30 T29

DIS

PEG_C_RXP5 C8011 1

2 SCD1U16V2KX-3GP PEG_RXP5

PEG_C_RXN5 C8012 1DIS 2 SCD1U16V2KX-3GP PEG_RXN5

PCI EXPRESS INTERFACE

PEG_TXP6 PEG_TXN6

R38 P37

PCIE_RX6P PCIE_RX6N

PCIE_TX6P PCIE_TX6N

P33 P32

DIS

PEG_C_RXP6 C8013 1

2 SCD1U16V2KX-3GP PEG_RXP6

PEG_C_RXN6 C8014 1DIS 2 SCD1U16V2KX-3GP PEG_RXN6

PEG_TXP7 PEG_TXN7

P35 N36

PCIE_RX7P PCIE_RX7N

PCIE_TX7P PCIE_TX7N

P30 P29

DIS

PEG_C_RXP7 C8016 1

2 SCD1U16V2KX-3GP PEG_RXP7

PEG_C_RXN7 C8015 1DIS 2 SCD1U16V2KX-3GP PEG_RXN7

DIS

C

PEG_TXP8 PEG_TXN8

N38 M37

PCIE_RX8P PCIE_RX8N

PCIE_TX8P PCIE_TX8N

N33 N32

PEG_C_RXP8 C8018 1

2 SCD1U16V2KX-3GP PEG_RXP8

PEG_C_RXN8 C8017 1DIS 2 SCD1U16V2KX-3GP PEG_RXN8

PEG_TXP9 PEG_TXN9

M35 L36

PCIE_RX9P PCIE_RX9N

PCIE_TX9P PCIE_TX9N

N30 N29

DIS

PEG_C_RXP9 C8020 1

2 SCD1U16V2KX-3GP PEG_RXP9

PEG_C_RXN9 C8019 1DIS 2 SCD1U16V2KX-3GP PEG_RXN9

PEG_TXP10 PEG_TXN10

L38 K37

PCIE_RX10P PCIE_RX10N

PCIE_TX10P PCIE_TX10N

L33 L32

DIS

PEG_C_RXP10 C8021 1

2 SCD1U16V2KX-3GP PEG_RXP10

PEG_C_RXN10 C8022 1DIS 2 SCD1U16V2KX-3GP PEG_RXN10

PEG_TXP11 PEG_TXN11

K35 J36

PCIE_RX11P PCIE_RX11N

PCIE_TX11P PCIE_TX11N

L30 L29

DIS

PEG_C_RXP11 C8023 1

2 SCD1U16V2KX-3GP PEG_RXP11

PEG_C_RXN11 C8024 1DIS 2 SCD1U16V2KX-3GP PEG_RXN11

PEG_TXP12 PEG_TXN12

J38 H37

PCIE_RX12P PCIE_RX12N

PCIE_TX12P PCIE_TX12N

K33 K32

DIS

PEG_C_RXP12 C8025 1

2 SCD1U16V2KX-3GP PEG_RXP12

PEG_C_RXN12 C8026 1DIS 2 SCD1U16V2KX-3GP PEG_RXN12

PEG_TXP13 PEG_TXN13

H35 G36

PCIE_RX13P PCIE_RX13N

PCIE_TX13P PCIE_TX13N

J33 J32

DIS

PEG_C_RXP13 C8028 1

2 SCD1U16V2KX-3GP PEG_RXP13

PEG_C_RXN13 C8027 1DIS 2 SCD1U16V2KX-3GP PEG_RXN13

PEG_TXP14 PEG_TXN14

G38 F37

PCIE_RX14P PCIE_RX14N

PCIE_TX14P PCIE_TX14N

K30 K29

DIS

PEG_C_RXP14 C8030 1

2 SCD1U16V2KX-3GP PEG_RXP14

PEG_C_RXN14 C8029 1DIS 2 SCD1U16V2KX-3GP PEG_RXN14

DIS

B

PEG_TXP15 PEG_TXN15

F35 E37

PCIE_RX15P PCIE_RX15N

PCIE_TX15P PCIE_TX15N

H33 H32

PEG_C_RXP15 C8032 1

2 SCD1U16V2KX-3GP PEG_RXP15

PEG_C_RXN15 C8031 1DIS 2 SCD1U16V2KX-3GP PEG_RXN15

CLK_PCIE_VGA CLK_PCIE_VGA#

AB35 AA36

CLOCK
PCIE_REFCLKP PCIE_REFCLKN

AJ21

DIS

AK21

1

2 PW RGOOD AH16

R8018

10KR2F-2-GP

NC#AJ21 NC#AK21 PWRGOOD

CALIBRATION PCIE_CALRP PCIE_CALRN

PLT_RST#

1 R8020 2VGA_RST# AA30
0R2J-2-GP DY

PERST#

PLTRST_DELAY#

1 DIS 2

R8021

0R2J-2-GP

MADISON-PRO-2-GP
DIS

Y30 PCIE_CALRP

R8017 DIS

1

2

1K27R2F-L-GP

Y29 PCIE_CALRN

1

R8019 DIS

+1.0V_RUN_VGA 2
2KR2F-3-GP

A

5

4

3

2

1

CONFIGURATION STRAPS
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET

RECOMMENDED SETTINGS 0= DO NOT INSTALL RESISTOR 1 = INSTALL 3K RESISTOR X = DESIGN DEPENDANT NA = NOT APPLICABLE

STRAPS

PIN

DESCRIPTION OF DEFAULT SETTINGS

PLATFORM RECOMMEND SETTING

TX_PWRS_ENB

GPIO0

Transmitter Power Savings Enable 0: 50% Tx output swing 1: Full Tx output swing

X

1

D

TX_DEEMPH_EN

GPIO1

PCIE TRANSMITTER DE-EMPHASIS ENABLED 0:Tx de-emphasis disabled 1:Tx de-emphasis enabled

X

1

0:Advertises the PCIe device as 2.5GT/s capable at power on.

BIF_GEN2_EN_A

GPIO2

1:Advertises the PCIe device as 5.0GT/s capable at power on.

0

0

GPIO5_AC_BATT

GPIO5

optional input allow the system to request a fast power reduction by setting GPIO5 to low.

?

0

RESERVED VGA_DIS
ROMIDCFG[2:0]

GPIO8

RESERVED

0

0:VGA Controller capacity enabled

GPIO9

1:The device won't be recognized as the system's VGA controller

0

GPIO[13:11]

BIOS_ROM_EN=1, Config[2:0] defines the ROM type BIOS_ROM_EN=0, Config[2:0] defines the primary memory aperture size

X XX

0
0 0 0 1 (256MB)

RESERVED

GPIO21

RESERVED

0

0

BIOS_ROM_EN GPIO_22_ROMCSB

0:Disable external BIOS ROM device 1:Enable external BIOS ROM device

X

0

VIP Device Strap Enable indicates to the software driver that it sense

VIP_DEVICE_STRAP_EN

V2SYNC

whether or not a VIP device is connected on the VIP Host interface.

X

0

RSVD

H2SYNC

RESERVED

C

0

0

RSVD

GENERICC

RESERVED

0

0

AUD[1] AUD[0]

HSYNC

X

1

AUD[1:0]:11-Audio for both DisplayPort and HDMI

VSYNC

X

1

TX_PW RS_ENB TX_DEEMPH_EN BIF_GEN2_EN_A
GPIO8_ROMSO VGA_DIS
CONFIG0 CONFIG1 CONFIG2 VGA_CRT_VSYNC VGA_CRT_HSYNC
VSYNC_DAC2 HSYNC_DAC2 BIOS_ROM_EN GPIO5_AC_BATT GPIO21_BB_EN

PIN STRAPS

+3.3V_RUN_VGA

DY R8001 1

2 3KR2J-2-GP

DY R8002 1

2 3KR2J-2-GP

DY R8003 1

2 10KR2J-3-GP

DY R8004 1

2 10KR2J-3-GP

DY R8005 1

2 10KR2J-3-GP

B

R8006 1 DIS 2

DY R8007 1

2

DY R8008 1

2

10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP

R8009 1 DIS 2 R8010 1 DIS 2

10KR2J-3-GP 10KR2J-3-GP

DY R8012 1

2

DY R8013 1

2

DY R8014 1

2

DY R8015 1

2

DY R8016 1

2

10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP

<Core Design>

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU_PCIE/STRAPPING(1/5)

Size

Document Number

A3

Berry

Rev
X00

Date: Thursday, October 22, 2009

Sheet 80

of

92

2

1

5

4

3

2

1

MDA[0..31]

VGA1C DDR2
GDDR3/GDDR5

3 OF 8 DDR2 GDDR5/GDDR3

MDB[0..31]

VGA1D DDR2
GDDR3/GDDR5

4 OF 8 DDR2 GDDR5/GDDR3

DDR3

DDR3

DDR3

DDR3

D MDA[32..63]
C

MDA0 MDA1 MDA2 MDA3 MDA4 MDA5 MDA6 MDA7 MDA8 MDA9 MDA10 MDA11 MDA12 MDA13 MDA14 MDA15 MDA16 MDA17 MDA18 MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43 MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63

C37 C35 A35 E34 G32 D33 F32 E32 D31 F30 C30 A30 F28 C28 A28 E28 D27 F26 C26 A26 F24 C24 A24 E24 C22 A22 F22 D21 A20 F20 D19 E18 C18 A18 F18 D17 A16 F16 D15 E14 F14 D13 F12 A12 D11 F10 A10 C10 G13 H13 J13 H11 G10 G8
K9 K10 G9
A8 C8 E8 A6 C6 E6 A5

DQA0_0/DQA_0 DQA0_1/DQA_1 DQA0_2/DQA_2 DQA0_3/DQA_3 DQA0_4/DQA_4 DQA0_5/DQA_5 DQA0_6/DQA_6 DQA0_7/DQA_7 DQA0_8/DQA_8 DQA0_9/DQA_9 DQA0_10/DQA_10 DQA0_11/DQA_11 DQA0_12/DQA_12 DQA0_13/DQA_13 DQA0_14/DQA_14 DQA0_15/DQA_15 DQA0_16/DQA_16 DQA0_17/DQA_17 DQA0_18/DQA_18 DQA0_19/DQA_19 DQA0_20/DQA_20 DQA0_21/DQA_21 DQA0_22/DQA_22 DQA0_23/DQA_23 DQA0_24/DQA_24 DQA0_25/DQA_25 DQA0_26/DQA_26 DQA0_27/DQA_27 DQA0_28/DQA_28 DQA0_29/DQA_29 DQA0_30/DQA_30 DQA0_31/DQA_31 DQA1_0/DQA_32 DQA1_1/DQA_33 DQA1_2/DQA_34 DQA1_3/DQA_35 DQA1_4/DQA_36 DQA1_5/DQA_37 DQA1_6/DQA_38 DQA1_7/DQA_39 DQA1_8/DQA_40 DQA1_9/DQA_41 DQA1_10/DQA_42 DQA1_11/DQA_43 DQA1_12/DQA_44 DQA1_13/DQA_45 DQA1_14/DQA_46 DQA1_15/DQA_47 DQA1_16/DQA_48 DQA1_17/DQA_49 DQA1_18/DQA_50 DQA1_19/DQA_51 DQA1_20/DQA_52 DQA1_21/DQA_53 DQA1_22/DQA_54 DQA1_23/DQA_55 DQA1_24/DQA_56 DQA1_25/DQA_57 DQA1_26/DQA_58 DQA1_27/DQA_59 DQA1_28/DQA_60 DQA1_29/DQA_61 DQA1_30/DQA_62 DQA1_31/DQA_63

MAA0_0/MAA_0 MAA0_1/MAA_1 MAA0_2/MAA_2 MAA0_3/MAA_3 MAA0_4/MAA_4 MAA0_5/MAA_5 MAA0_6/MAA_6 MAA0_7/MAA_7 MAA1_0/MAA_8 MAA1_1/MAA_9 MAA1_2/MAA_10 MAA1_3/MAA_11 MAA1_4/MAA_12 MAA1_5/MAA_13_BA2 MAA1_6/MAA_14_BA0 MAA1_7/MAA_A15_BA1

G24 J23 H24 J24 H26 J26 H21 G21 H19 H20 L13 G16 J16 H16 J17 H17

W CKA0_0/DQMA_0 W CKA0#_0/DQMA_1
W CKA0_1/DQMA_2 W CKA0#_1/DQMA_3
W CKA1_0/DQMA_4 W CKA1#_0/DQMA_5
W CKA1_1/DQMA_6 W CKA1#_1/DQMA_7

A32 C32 D23 E22 C14 A14 E10 D9

GDDR5/DDR2/GDDR3 EDCA0_0/QSA_0/RDQSA_0 EDCA0_1/QSA_1/RDQSA_1 EDCA0_2/QSA_2/RDQSA_2 EDCA0_3/QSA_3/RDQSA_3 EDCA1_0/QSA_4/RDQSA_4 EDCA1_1/QSA_5/RDQSA_5 EDCA1_2/QSA_6/RDQSA_6 EDCA1_3/QSA_7/RDQSA_7

C34 D29 D25 E20 E16 E12 J10 D7

DDBIA0_0/QSA_0#/W DQSA_0 DDBIA0_1/QSA_1#/W DQSA_1 DDBIA0_2/QSA_2#/W DQSA_2 DDBIA0_3/QSA_3#/W DQSA_3 DDBIA1_0/QSA_4#/W DQSA_4 DDBIA1_1/QSA_5#/W DQSA_5 DDBIA1_2/QSA_6#/W DQSA_6 DDBIA1_3/QSA_7#/W DQSA_7

A34 E30 E26 C20 C16 C12 J11 F8

ADBIA0/ODTA0 ADBIA1/ODTA1

J21 G19

CLKA0 CLKA0#

H27 G27

CLKA1 CLKA1#

J14 H14

RASA0# RASA1#

K23 K19

CASA0# CASA1#

K20 K17

CSA0#_0 CSA0#_1

K24 K27

CSA1#_0 CSA1#_1

M13 K16

MEMORY INTERFACE A MEMORY INTERFACE B

MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 A_BA2 A_BA0 A_BA1
DQMA0 DQMA1 DQMA2 DQMA3 DQMA4 DQMA5 DQMA6 DQMA7
QSAP_0 QSAP_1 QSAP_2 QSAP_3 QSAP_4 QSAP_5 QSAP_6 QSAP_7
QSAN_0 QSAN_1 QSAN_2 QSAN_3 QSAN_4 QSAN_5 QSAN_6 QSAN_7
ODTA0 ODTA1
CLKA0 CLKA0#
CLKA1 CLKA1#
RASA0# RASA1#
CASA0# CASA1#
CSA0#_0
CSA1#_0

MDB[32..63]
Reserved for JTAG
+3.3V_RUN_VGA

MDB0 MDB1 MDB2 MDB3 MDB4 MDB5 MDB6 MDB7 MDB8 MDB9 MDB10 MDB11 MDB12 MDB13 MDB14 MDB15 MDB16 MDB17 MDB18 MDB19 MDB20 MDB21 MDB22 MDB23 MDB24 MDB25 MDB26 MDB27 MDB28 MDB29 MDB30 MDB31 MDB32 MDB33 MDB34 MDB35 MDB36 MDB37 MDB38 MDB39 MDB40 MDB41 MDB42 MDB43 MDB44 MDB45 MDB46 MDB47 MDB48 MDB49 MDB50 MDB51 MDB52 MDB53 MDB54 MDB55 MDB56 MDB57 MDB58 MDB59 MDB60 MDB61 MDB62 MDB63

C5 C3 E3 E1 F1 F3 F5 G4 H5 H6 J4 K6 K5 L4 M6 M1 M3 M5 N4 P6 P5 R4 T6 T1 U4 V6 V1 V3 Y6 Y1 Y3 Y5 AA4 AB6 AB1 AB3 AD6 AD1 AD3 AD5 AF1 AF3 AF6 AG4 AH5 AH6 AJ4 AK3 AF8 AF9 AG8 AG7 AK9 AL7 AM8 AM7 AK1 AL4 AM6 AM1 AN4 AP3 AP1 AP5

DQB0_0/DQB_0 DQB0_1/DQB_1 DQB0_2/DQB_2 DQB0_3/DQB_3 DQB0_4/DQB_4 DQB0_5/DQB_5 DQB0_6/DQB_6 DQB0_7/DQB_7 DQB0_8/DQB_8 DQB0_9/DQB_9 DQB0_10/DQB_10 DQB0_11/DQB_11 DQB0_12/DQB_12 DQB0_13/DQB_13 DQB0_14/DQB_14 DQB0_15/DQB_15 DQB0_16/DQB_16 DQB0_17/DQB_17 DQB0_18/DQB_18 DQB0_19/DQB_19 DQB0_20/DQB_20 DQB0_21/DQB_21 DQB0_22/DQB_22 DQB0_23/DQB_23 DQB0_24/DQB_24 DQB0_25/DQB_25 DQB0_26/DQB_26 DQB0_27/DQB_27 DQB0_28/DQB_28 DQB0_29/DQB_29 DQB0_30/DQB_30 DQB0_31/DQB_31 DQB1_0/DQB_32 DQB1_1/DQB_33 DQB1_2/DQB_34 DQB1_3/DQB_35 DQB1_4/DQB_36 DQB1_5/DQB_37 DQB1_6/DQB_38 DQB1_7/DQB_39 DQB1_8/DQB_40 DQB1_9/DQB_41 DQB1_10/DQB_42 DQB1_11/DQB_43 DQB1_12/DQB_44 DQB1_13/DQB_45 DQB1_14/DQB_46 DQB1_15/DQB_47 DQB1_16/DQB_48 DQB1_17/DQB_49 DQB1_18/DQB_50 DQB1_19/DQB_51 DQB1_20/DQB_52 DQB1_21/DQB_53 DQB1_22/DQB_54 DQB1_23/DQB_55 DQB1_24/DQB_56 DQB1_25/DQB_57 DQB1_26/DQB_58 DQB1_27/DQB_59 DQB1_28/DQB_60 DQB1_29/DQB_61 DQB1_30/DQB_62 DQB1_31/DQB_63

MAB0_0/MAB_0 MAB0_1/MAB_1 MAB0_2/MAB_2 MAB0_3/MAB_3 MAB0_4/MAB_4 MAB0_5/MAB_5 MAB0_6/MAB_6 MAB0_7/MAB_7 MAB1_0/MAB_8 MAB1_1/MAB_9 MAB1_2/MAB_10 MAB1_3/MAB_11 MAB1_4/MAB_12
MAB1_5/BA2 MAB1_6/BA0 MAB1_7/BA1
W CKB0_0/DQMB_0 W CKB0#_0/DQMB_1
W CKB0_1/DQMB_2 W CKB0#_1/DQMB_3
W CKB1_0/DQMB_4 W CKB1#_0/DQMB_5
W CKB1_1/DQMB_6 W CKB1#_1/DQMB_7 GDDR5/DDR2/GDDR3 EDCB0_0/QSB_0/RDQSB_0 EDCB0_1/QSB_1/RDQSB_1 EDCB0_2/QSB_2/RDQSB_2 EDCB0_3/QSB_3/RDQSB_3 EDCB1_0/QSB_4/RDQSB_4 EDCB1_1/QSB_5/RDQSB_5 EDCB1_2/QSB_6/RDQSB_6 EDCB1_3/QSB_7/RDQSB_7
DDBIB0_0/QSB_0#/W DQSB_0 DDBIB0_1/QSB_1#/W DQSB_1 DDBIB0_2/QSB_2#/W DQSB_2 DDBIB0_3/QSB_3#/W DQSB_3 DDBIB1_0/QSB_4#/W DQSB_4 DDBIB1_1/QSB_5#/W DQSB_5 DDBIB1_2/QSB_6#/W DQSB_6 DDBIB1_3/QSB_7#/W DQSB_7
ADBIB0/ODTB0 ADBIB1/ODTB1
CLKB0 CLKB0#
CLKB1 CLKB1#
RASB0# RASB1#
CASB0# CASB1#
CSB0#_0 CSB0#_1
CSB1#_0 CSB1#_1

P8 T9 P9 N7 N8 N9 U9 U8 Y9 W9 AC8 AC9 AA7 AA8 Y8 AA9
H3 H1 T3 T5 AE4 AF5 AK6 AK5
F6 K3 P3 V5 AB5 AH1 AJ9 AM5
G7 K1 P1 W4 AC4 AH3 AJ8 AM3
T7 W7
L9 L8
AD8 AD7
T10 Y10
W 10 AA10
P10 L10
AD10 AC10

MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 B_BA2 B_BA0 B_BA1
DQMB0 DQMB1 DQMB2 DQMB3 DQMB4 DQMB5 DQMB6 DQMB7
QSBP_0 QSBP_1 QSBP_2 QSBP_3 QSBP_4 QSBP_5 QSBP_6 QSBP_7
QSBN_0 QSBN_1 QSBN_2 QSBN_3 QSBN_4 QSBN_5 QSBN_6 QSBN_7
ODTB0 ODTB1
CLKB0 CLKB0#
CLKB1 CLKB1#
RASB0# RASB1#
CASB0# CASB1#
CSB0#_0
CSB1#_0

D C

MVREFDA MVREFSA
MEM_CALRN0 MEM_CALRN1 MEM_CALRN2

L18 L20
L27 N12 AG12

MVREFDA MVREFSA
MEM_CALRN0 MEM_CALRN1 MEM_CALRN2

CKEA0 CKEA1

K21 J20

W EA0# W EA1#

K26 L15

CKEA0 CKEA1
WEA0# WEA1#

2

R8121
DIS 10KR2J-3-GP

MVREFDB MVREFSB

Y12 AA12

MVREFDB MVREFSB

CKEB0 CKEB1
W EB0# W EB1#

U10 AA11
N10 AB11

CKEB0 CKEB1
WEB0# WEB1#

1

+1.5V_RUN
R_MEM_3

21

+1.5V_RUN
DIS
1 243R2F-2-GP

MEM_CALRP1 MEM_CALRP0 MEM_CALRP2

M12 M27 AH12

MEM_CALRP1 MEM_CALRP0 MEM_CALRP2

2 MEM_CALRN0 R8104

GDDR5

MAA0_8 MAA1_8

H23 J19

MAA13

TP8101
R8122 DY TP8102
10KR2J-3-GP

TEST_EN

AD28

1

CLKTESTA AK10

TP1AD14-GP CLKTESTB AL10

TPAD14-GP

TESTEN
CLKTESTA CLKTESTB

GDDR5

MAB0_8 MAB1_8
DRAM_RST#

T8 W8
AH11

MAB13

R_MEM_2 DIS

DRAM_RST

1

2

R8103

680R2J-3-GP

1

R_MEM_1
R8105

1

DY

R8102 2K2R2J-2-GP

2

C_MEM

MEM_RST

1

DIS
1

2 MEM_CALRN1

10KR2J-3-GP DIS

DIS

C8103 SC68P50V2JN-1GP

2

243R2F-2-GP

R8106

DIS

B

1

2 MEM_CALRN2

243R2F-2-GP R8107

DIS

MADISON-PRO-2-GP

DIS

For new version

DIS MADISON-PRO-2-GP

2

B

R8110 1

2MEM_CALRP1

243R2F-2-GP

DIS
R8111 1 243R2F-2-GP
DIS
R8112 1 243R2F-2-GP

2MEM_CALRP0 2MEM_CALRP2

**This basic topology should be used for DRAM_RST for
DDR3/GDDR3/GDDR5.These Capacitors and Resistor values are an example only. The Series R and || Cap values will depend on the DRAM load and will have to be calculated for different Memory ,DRAM Load and board

to pass Reset Signal Spec.

PLACE MVREF DIVIDERS AND CAPS CLOSE TO ASIC

2

2

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

1

1

1

1

Ra R8113 Madi4s0oD2nR2F-GP
MVREFDA

Ra R8114
40D2R2F-GP
Madison

MVREFSA

12

12

1

1

R8117

Madison
C8104

2

Rb 100R2F-L1-GP-U

Madison

SCD1U10V2KX-4GP

Madison

R8118

C8105

2

Rb 100R2F-L1-GP-U

Madison

SCD1U10V2KX-4GP

R8115
Ra 40D2R2F-GP DIS

MVREFDB

R8116
Ra 40D2R2F-GP DIS

MVREFSB

12

12

1

1

C8106

R8119

SCD1U10V2KX-4GP

2

Rb 100R2F-L1-GP-U

DIS

DIS

R8120

DIS
C8107

2

Rb 100R2F-L1-GP-U

DIS

SCD1U10V2KX-4GP

2

2

Designator For M97-M2 For Mannhatton

R_MEM_1 R_MEM_2 R_MEM_3 C_MEM

10K 0R/Short DNI 2.2nF

10K 680R DNI 68pF

DDR3/GDDR3 Memory Stuff Option

A

GDDR5 GDDR3

DDR3

MVDDQ 1.5V 1.8V/1.5V 1.5V

Ra

40.2R 40.2R

40.2R

Rb

100R 100R

100R

5

4

3

A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU Memory(2/5)

Size

Document Number

C

Berry

Rev
X00

Date: Thursday, October 22, 2009

Sheet 81

of

92

2

1

5

4

3

2

1

VGA1B

2 OF 8

LVDS Interface

MEMORY ID Table
DVPDATA[0:3]

Description

MUTI GFX

TXCAP_DPA3P TXCAM_DPA3N

AU24 AV23

DPA

TX0P_DPA2P TX0M_DPA2N

AT25 AR24

HDMI_PCH_CLK HDMI_PCH_CLK#
HDMI_PCH_DATA0 HDMI_PCH_DATA0#

VGA1G

7 OF 8

RN8203

2

3

1 DIS 4

SRN10KJ-5-GP

1000

DDR3 Samsung-K4W1G1646E-HC12 (800MHz)

D

0000

DDR3 Hynix-H5TQ1G63BFR-12C (800MHz)

DVPDATA[0:3] Default:Pull down

THERMTRIP_VGA

MEM_ID Control

+1.8V_RUN_VGA

Hynix R8207 1

2 10KR2J-3-GP

DY R8209 1

2 10KR2J-3-GP 1

TP8222

1 TPAD14-GP

TP8223

TPAD14-GP

6 THERMTRIP_R

1

2N7002EDW -GP Q8203
84.27002.F3F

1

2

5

3

4

2

DY R8208
10KR2J-3-GP
DIS

THERMTRIP_VGA#

.

DIS
.

...

Q8202 2N7002E-1-GP
84.2N702.D31

G D
S

H_THERMTRIP# THERMTRIP_VGA_GATE

+3.3V_RUN_VGA

AR8

AU8

AP8

AW8

AR3

AR1 MEM_ID0 AU1

MEM_ID1 MEM_ID2 MEM_ID3

AU3 AW3 AP6

AW5

AU5

AR6

AW6

AU6

AT7

AV7

AN7

AV9

AT9

AR10

AW10

AU10

AP10

AV11

AT11

AR12

AW12

AU12

AP12

DVPCNTL_MVP_0 DVPCNTL_MVP_1 DVPCNTL_0 DVPCNTL_1 DVPCNTL_2 DVPCLK DVPDATA_0 DVPDATA_1 DVPDATA_2 DVPDATA_3 DVPDATA_4 DVPDATA_5 DVPDATA_6 DVPDATA_7 DVPDATA_8 DVPDATA_9 DVPDATA_10 DVPDATA_11 DVPDATA_12 DVPDATA_13 DVPDATA_14 DVPDATA_15 DVPDATA_16 DVPDATA_17 DVPDATA_18 DVPDATA_19 DVPDATA_20 DVPDATA_21 DVPDATA_22 DVPDATA_23

DPB DPC

1

2

R8201
DIS
10KR2J-3-GP

1

2

2

JTAG_TRST#_VGA
For new version
JTAG_TCK_VGA
DY R8203
10KR2J-3-GP

1

2

C
+3.3V_RUN_VGA
DIS R8205
10KR2J-3-GP JTAG_TMS_VGA

1

JTAG SIGNAL OPTION

Signal

Normal mode

TESTEN

"1"(PU)

JTAG_TRST# "0"(PD)

RN8201

DIS SRN4K7J-8-GP

DPD

I2C Bus for LVDS
Straps

GPU_LVDS_CLK GPU_LVDS_DATA

RN8202

4

1 GPU_LVDS_CLK_C AK26

DIS 3

2 GPU_LVDS_DATA_C AJ26

SRN0J-6-GP

Debug mode "1"(PU)
"1"(PU)

TX_PW RS_ENB TX_DEEMPH_EN BIF_GEN2_EN_A

GPIO5_AC_BATT
GPIO8_ROMSO VGA_DIS

TP8207

1 TPAD14-GP

VGA_BLEN

GPIO6_VGA

CONFIG0 CONFIG1 CONFIG2
GPIO21_BB_EN BIOS_ROM_EN
CLK_VGA_27M_SS
For new version

PW RCNTL_0 TP8203

1
TP8213 TP8209

PW RCNTL_1

PEG_CLKREQ#

R8204

TP8202

1 DIS 2

0R2J-2-GP
no 27M

TP8205 TP8206 TP8211 TP8218 TP8219 TP8212 TP8220 TP8221

1

VPIO14_VGA

TP8208 TPAD14-GP

TPAD14-GP

GPIO16_SSIN

1 TPAD14-GP

GPIO17_VGA

1 TPAD14-GP

GPIO18_VGA

THERMTRIP_VGA

1 TPAD14-GP
1 TPAD14-GP 1 TPAD14-GP 1 TPAD14-GP 1 TPAD14-GP 1 TPAD14-GP 1 TPAD14-GP 1 TPAD14-GP 1 TPAD14-GP

JTAG_TRST#_VGA JTAG_TDI_VGA JTAG_TCK_VGA
JTAG_TMS_VGA JTAG_TDO_VGA GEN_A GEN_B GENERICC GENERICD GENERICE_HPD4 GENERICF GENERICG

AH20 AH18 AN16 AH23 AJ23 AH17 AJ17 AK17 AJ13 AH15 AJ16 AK16 AL16 AM16 AM14 AM13 AK14 AG30 AN14 AM17 AL13 AJ14 AK13 AN13 AM23 AN23 AK23 AL24 AM24 AJ19 AK19 AJ20 AK20 AJ24 AH26 AH24

3

4

I2C

SCL SDA

GENERAL PURPOSE I/O

GPIO_0

GPIO_1

GPIO_2

GPIO_3_SMBDATA

GPIO_4_SMBCLK

GPIO_5_AC_BATT GPIO_6

DAC1

GPIO_7_BLON

GPIO_8_ROMSO

GPIO_9_ROMSI

GPIO_10_ROMSCK

GPIO_11

GPIO_12

GPIO_13

GPIO_14_HPD2

GPIO_15_PWRCNTL_0

GPIO_16_SSIN

GPIO_17_THERMAL_INT

GPIO_18_HPD3

GPIO_19_CTF

GPIO_20_PWRCNTL_1

GPIO_21_BB_EN

GPIO_22_ROMCS#

GPIO_23_CLKREQ#

JTAG_TRST#

JTAG_TDI

JTAG_TCK

JTAG_TMS

JTAG_TDO

GENERICA

GENERICB

GENERICC

GENERICD

GENERICE_HPD4 GENERICF

DAC2

GENERICG

TX1P_DPA1P TX1M_DPA1N
TX2P_DPA0P TX2M_DPA0N
TXCBP_DPB3P TXCBM_DPB3N
TX3P_DPB2P TX3M_DPB2N
TX4P_DPB1P TX4M_DPB1N
TX5P_DPB0P TX5M_DPB0N
TXCCP_DPC3P TXCCM_DPC3N
TX0P_DPC2P TX0M_DPC2N
TX1P_DPC1P TX1M_DPC1N
TX2P_DPC0P TX2M_DPC0N
TXCDP_DPD3P TXCDM_DPD3N
TX3P_DPD2P TX3M_DPD2N
TX4P_DPD1P TX4M_DPD1N
TX5P_DPD0P TX5M_DPD0N

AU26 AV25
AT27 AR26
AR30 AT29
AV31 AU30
AR32 AT31
AT33 AU32
AU14 AV13
AT15 AR14
AU16 AV15
AT17 AR16
AU20 AT19
AT21 AR20
AU22 AV21
AT23 AR22

R R#
G G#
B B#
HSYNC VSYNC

AD39 AD37
AE36 AD35
AF37 AE38
AC36 AC38

RSET
AVDD AVSSQ
VDD1DI VSS1DI

AB34
AD34 AE34
AC33 AC34

R2 R2#

AC30 AC31

G2 G2#

AD30 AD31

B2 B2#

AF30 AF31

C Y COMP

AC32 AD32 AF32

H2SYNC V2SYNC

AD29 AC29

HDMI_PCH_DATA1 HDMI_PCH_DATA1#
HDMI_PCH_DATA2 HDMI_PCH_DATA2#

R82012 DIS 210KR2J-3-GP

VGA_BLEN

LVDS CONTROL

VARY_BL DIGON

AK27 AJ27

TXCLK_UP_DPF3P TXCLK_UN_DPF3N
TXOUT_U0P_DPF2P TXOUT_U0N_DPF2N
TXOUT_U1P_DPF1P TXOUT_U1N_DPF1N
TXOUT_U2P_DPF0P TXOUT_U2N_DPF0N
TXOUT_U3P TXOUT_U3N

AK35 AL36
AJ38 AK37
AH35 AJ36
AG38 AH37
AF35 AG36

LVTMDP

TXCLK_LP_DPE3P TXCLK_LN_DPE3N
TXOUT_L0P_DPE2P TXOUT_L0N_DPE2N
TXOUT_L1P_DPE1P TXOUT_L1N_DPE1N
TXOUT_L2P_DPE0P TXOUT_L2N_DPE0N
TXOUT_L3P TXOUT_L3N

AP34 AR34
AW37 AU35
AR37 AU39
AP35 AR35
AN36 AP37

VGA_LBKLT_CTL VGA_LCDVDD_EN
GPU_LVDSB_TXC GPU_LVDSB_TXC# GPU_LVDSB_TX0 GPU_LVDSB_TX0# GPU_LVDSB_TX1 GPU_LVDSB_TX1# GPU_LVDSB_TX2 GPU_LVDSB_TX2#
GPU_LVDSA_TXC GPU_LVDSA_TXC# GPU_LVDSA_TX0 GPU_LVDSA_TX0# GPU_LVDSA_TX1 GPU_LVDSA_TX1# GPU_LVDSA_TX2 GPU_LVDSA_TX2#

VGA_CRT_RED

DIS MADISON-PRO-2-GP

VGA_CRT_GREEN

+3.3V tolerant

VGA_CRT_BLUE

RN8204

VGA_CRT_HSYNC VGA_CRT_VSYNC

VGA_CRT_BLUE 1 VGA_CRT_GREEN 2 VGA_CRT_RED 3

8

DIS

7 6

GPU_RSET

DIS

1

2

4

5

R8214

499R2F-2-GP

SRN150F-1-GP

AVDD

VDD1DI

+1.8V_RUN_VGA

AVDD

L8202 DIS

1

2

(1.8V@65mA AVDD)

BLM15BD121SS1D-GP

1

1

1

C8203

C8204

C8201 DIS
SC4D7U6D3V3KX-GP

DIS DIS
SC1U6D3V2KX-GP

2

2

SCD1U10V2KX-4GP

2

VDD1DI

L8203 DIS

1

2

(1.8V@100mA VDD1DI)

BLM15BD121SS1D-GP

1

1

1

C8206

C8207

C8202 DIS
SC4D7U6D3V3KX-GP

2

2

DIS

2

DIS
SCD1U10V2KX-4GP

SC1U6D3V2KX-GP

HSYNC_DAC2 VSYNC_DAC2

2

2

SCD1U10V2KX-4GP

(1.8V@50mA VDD2DI)

1

1

C8209

C8210

DY DY
SC1U6D3V2KX-GP

A2VDDQ

D C

SC1U6D3V2KX-GP

SCD1U10V2KX-4GP

JTAG_TCK JTAG_TMS

CLK "1"(PU)

"1"(PU) "1"(PU)

+1.8V_RUN_VGA

HDMI_HPD_DET

1

PLACE VREFG DIVIDER AND CAP CLOSE TO ASIC

DIS

R8216 499R2F-2-GP

AK24 HPD1

VDD2DI VSS2DI

AG31 AG32

A2VDD AG33

+1.8V_RUN_VGA +3.3V_RUN_VGA

A2VDDQ

L8205 DIS

(1.8V@1.5mA A2VDDQ)

1

2

BLM15BD121SS1D-GP

1

C8212

DIS

1

C8213
DIS

2

2

SC1U6D3V2KX-GP

SCD1U10V2KX-4GP

SC1U6D3V2KX-GP

B

+1.8V_RUN_VGA

DIS L8201 (1.8V@75mA DPLL_PVDD)

1

2

DPLL_PVDD

12

GPU_VREFG DPLL_PVDD

AH13 VREFG

A2VDDQ A2VSSQ

AD33 AF33

B

1

SCD1U10V2KX-4GP

BLM18PG471SN1D-GP
C8205 DY
SC4D7U6D3V3KX-GP

2

1

1

C8218
DIS

2

2

1

C8219
DIS

R8217
249R2F-GP DIS

2

2

C8217
DIS

AM32 AN32

DPLL_PVDD DPLL_PVSS

AN31 DPLL_VDDC

DIS

R2SET

AA29

R2SET 1 R8218

2 715R2F-GP

DDC/AUX

DDC1CLK DDC1DATA

AM26 AN26

VGA_CRT_DDCCLK VGA_CRT_DDCDATA

DDC1 channel for CRT

+3.3V_RUN_VGA

2

(3.3V@130mA A2VDD)

1

1

C8215
DY DY

C8216 SCD1U10V2KX-4GP

2

+1.0V_RUN_VGA

(1.0V@125mA DPLL_VDDC)

DPLL_VDDC

DIS

(1.1V@150mA DPLL_VDDC For M96/M92)

1

2

L8207 BLM18PG471SN1D-GP

1

C8220 DY
SC4D7U6D3V3KX-GP

C8221 C8222

DIS

DIS

1

1

CLK_VGA_27M_NSS

XTALIN AV33 XTALOUT AU34

XTALIN XTALOUT

PLL/CLOCK

AW34 AW35

XO_IN XO_IN2

AUX1P AUX1N
DDC2CLK DDC2DATA
AUX2P AUX2N

AM27 AL27
AM19 AL19
AN20 AM20

GPU_HDMI_CLK GPU_HDMI_DATA

DDC2 channel for HDMI

2

SCD1U10V2KX-4GP

2

SC1U6D3V2KX-GP

2

VGA_THERMDA

2

C8226

DDCCLK_AUX3P DDCDATA_AUX3N

AL30 AM30

DDC1/DDC2/DDC6 have 5V-tolerant

+1.8V_RUN_VGA

VGA_THERMDC

DY

1

SC470P50V2JN-GP AF29 AG29

DPLUS DMINUS

THERMAL

TP8214 TSVDD

1 TPAD14-GP

FAN_PW M

AK32 AL31

TS_FDO TS_A

DDCCLK_AUX4P DDCDATA_AUX4N
DDCCLK_AUX5P DDCDATA_AUX5N
DDC6CLK DDC6DATA

AL29 AM29
AN21 AM21
AJ30 AJ31

C8227

2

1

XTALIN

X8201

1

4

L8204 DIS

1

2

BLM15BD121SS1D-GP

(1.8V@20mA TSVDD)

AJ32 AJ33

TSVDD TSVSS

DDCCLK_AUX7P DDCDATA_AUX7N

AK30 AK29

DY

DY SC18P50V2JN-1-GP

2

3

XTALOUT

C8228

1

2

1

1

1

DIS

DIS

2

2

C8223 DY
SC4D7U6D3V3KX-GP

C8224

C8225

SC1U6D3V2KX-GP SCD1U10V2KX-4GP

2

DIS MADISON-PRO-2-GP

A

XTAL-27MHZ-85-GP

SC18P50V2JN-1-GP
DY

A

Clock Input Configuraiton -GDDR3/DDR3 a) 27MHz crystal connected to XTALIN or XTALOUT or b) 27MHz (1.8V) oscillator connected to XTALIN or c) 27MHz (3.3V) oscillator connected to XO_IN (Park, Madison, and Broadway only)

5

4

3

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
GPU_DP/LVDS/CRT/GPIO(3/5)

Size A2

Document Number
Berry

Rev
X00

Date: Thursday, October 22, 2009

Sheet 82

of

92

2

1

5

4

3

2

1

VGA1E

5 OF 8

+1.8V_RUN_VGA

+1.5V_RUN

For DDR3/GDDR5, MVDDQ = 1.5V

MEM I/O

PCIE

(1.8V@504mA PCIE_VDDR)

SC1U6D3V2KX-GP

1

1

1

SC1U6D3V2KX-GP

1

SC1U6D3V2KX-GP

1

SC1U6D3V2KX-GP SC1U10V2KX-1GP

SC1U6D3V2KX-GP SC1U10V2KX-1GP

SC1U10V2KX-1GP SC1U10V2KX-1GP

C8301
DIS

2

C8304
DIS

2

C8305
DIS

2

C8306
DIS

2

C8307
DIS

2

C8308
DIS

2

C8309
DIS

2

C8310
DIS

2

C8311
DIS

2

C8312
DIS

2

1

1

1

1

1

1

1

1

1

1

C8318
DIS

2

C8319
DIS

2

C8320
DIS

2

C8321
DIS

2

C8322
DIS

2

C8323
DY

2

C8324
DY

2

C8325
DY

2

C8326
DY

2

C8327
DY

2

D

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SCD1U10V2KX-4GP

SCD1U16V2KX-3GP

SCD1U10V2KX-4GP

1

1

C8303

C8335

2

DIS DIS

2

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

+1.8V_RUN_VGA

SC1U6D3V2KX-GP

SC4D7U6D3V3KX-GP

1 L8301

DIS

(1.8V@110mA VDD_CT) 2 BLM15BD121SS1D-GP
C8351
DIS

1

2

+3.3V_RUN_VGA

1

2

C8352
DIS

1

1

1

C8366
DIS

C8367

C8368

2

2

2

DIS DIS

C

SC1U6D3V2KX-GP

2

1

2

1

C8353
DIS
C8369
DIS

SCD1U10V2KX-4GP

2

1

C8354
DIS

SC1U6D3V2KX-GP

2

1

VDDC_CT
C8355
DIS

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC4D7U6D3V3KX-GP

2

1

C8374 SC1U6D3V2KX-GP
DIS

1

C8375 SCD1U10V2KX-4GP
DIS

2

SC1U6D3V2KX-GP

1

SC1U6D3V2KX-GP

1

SC1U6D3V2KX-GP

1

SC1U6D3V2KX-GP

1

1

AC7 AD11
AF7 AG10
AJ7 AK8 AL9 G11 G14 G17 G20 G23 G26 G29 H10
J7 J9 K11 K13 K8 L12 L16 L21 L23 L26 L7 M11 N11 P7 R11 U11 U7 Y11 Y7

VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1

AF26 AF27 AG26 AG27

LEVEL TRANSLATION
VDD_CT VDD_CT VDD_CT VDD_CT

AF23 AF24 AG23 AG24

I/O
VDDR3 VDDR3 VDDR3 VDDR3

AF13 AF15 AG13 AG15

VDDR4 VDDR4 VDDR4 VDDR4

AD12 AF11 AF12 AG11

VDDR4 VDDR4 VDDR4 VDDR4

M20 M21

NC_VDDRHA NC_VSSRHA

V12 U12

NC_VDDRHB NC_VSSRHB

1 L8302

DIS

(1.8V@40mA PCIE_PVDD)

2

BLM15BD121SS1D-GP

1

1

1

C8377

C8378

2

C8376 DIS

DIS

2

2

DIS

PCIE_PVDD

MPV18 SPV18

AB37
H7 H8

PLL PCIE_PVDD
MPV18 MPV18

PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR PCIE_VDDR

AA31 AA32 AA33 AA34 V28 W29 W30 Y31

PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC

G30 G31 H29 H30 J29 J30 L28 M28 N28 R28 T28 U28

CORE

VDDC VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

POWER

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC/BIF_VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC/BIF_VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

VDDC

AA15 AA17 AA20 AA22 AA24 AA27 AB16 AB18 AB21 AB23 AB26 AB28 AC17 AC20 AC22 AC24 AC27 AD18 AD21 AD23 AD26 AF17 AF20 AF22 AG16 AG18 AG21 AH22 AH27 AH28 M26 N24 N27 R18 R21 R23 R26 T17 T20 T22 T24 T27 U16 U18 U21 U23 U26 V17 V20 V22 V24 V27 Y16 Y18 Y21 Y23 Y26 Y28

SC1U6D3V2KX-GP

2

1

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SCD1U10V2KX-4GP

2

SC1U6D3V2KX-GP

1

SC1U6D3V2KX-GP

1

SC1U6D3V2KX-GP

1

1

1

C8313
DY

2

C8314
DIS

2

C8315
DY

2

C8316
DIS

2

C8317
DIS SC4D7U6D3V3KX-GP

(1.0V@1920mA PCIE_VDDC)

+1.0V_RUN_VGA

1

1

1

1

1

1

1

C8328

C8329

C8330

2

2

DIS DIS DIS

2

C8331
DIS

2

C8332
DIS

2

C8333
DIS

2

C8302

C8334

DIS SC4D7U6D3V3KX-GP

2

DIS

SC1U6D3V2KX-GP SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

+VGA_CORE For UMA +VGA_CORE connect to GND

1

1

1

1

1

1

1

1

1

1

C8336
DIS

2

C8337
DIS

2

C8338
DIS

2

C8339
DIS

2

C8340
DIS

2

C8341
DIS

2

C8342
DIS

2

C8343
DIS

2

C8344
DIS

2

C8345

SC1U6D3V2KX-GP

R8301

DIS

UMA 0R3J-0-U-GP

1

2

SC1U10V2KX-1GP SC1U10V2KX-1GP

2

SC1U6D3V2KX-GP

SC1U10V2KX-1GP

SC1U6D3V2KX-GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

1

1

1

1

1

C8346
DIS

C8347
DIS

C8348
DY

C8349

C8350

DIS DIS SC1U6D3V2KX-GP

2

2

2

2

2

SC1U6D3V2KX-GP SC1U6D3V2KX-GP

SCD1U16V2KX-3GP SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

1

1

1

1

1

1

1

1

1

1

2

SC1U6D3V2KX-GP

SCD1U16V2KX-3GP

SC1U6D3V2KX-GP SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SCD1U16V2KX-3GP SC1U6D3V2KX-GP

C8356
DIS

2

C8357
DIS

2

C8358
DIS

2

C8359
DIS

C8360
DY

2

2

C8361
DIS

2

C8362
DIS

2

C8363
DIS

2

C8364
DIS

2

C8365
COLAY

1

C8370
DIS

1

C8371
DIS

1

C8372
DY

1

C8373
DIS

2

2

2

2

SC10U10V5KX-2GP SC10U6D3V5KX-1GP SC10U10V5KX-2GP SC10U10V5KX-2GP

(GDDR3/DDR3 1.12V@4A VDDCI)

VDDCI and VDDC should have seperate regulators with a merge option on PCB For Madison and Park, VDDCI and VDDC can share one common regulator

D C

SC4D7U6D3V3KX-GP

SPV10

+VGA_CORE

SCD1U10V2KX-4GP

SC1U6D3V2KX-GP

B

SCD1U10V2KX-4GP

SC1U6D3V2KX-GP

+1.0V_RUN_VGA

L8303 1

DIS2

BLM18PG471SN1D-GP

(For M96 SPV10 = VDDC)

(For M97, Broadway, Madison and Park SPV10 = 1.0V)

C8379

1

(120mA SPV10)

1

C8380

DIS

DIS

2

2

SC4D7U6D3V3KX-GP

2

1

C8381
DIS

AM10 AN9
AN10

SPV18 SPV10 SPVSS

VOLTAGE SENESE

M97, Broadway, Madison and Park only M96 do not support core vsense feature

TP8301 TP8302

1FB_VDDC TPAD14-GP
1FB_VDDCI TPAD14-GP

AF28 FB_VDDC AG28 FB_VDDCI

TP8303

1FB_GND TPAD14-GP

AH29 FB_GND

VCORE_SEN/RTN and VDDCI_SEN/RTN route as differetial pair

ISOLATED CORE I/O

VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI

AA13 AB13 AC12 AC15 AD13 AD16 M15 M16 M18 M23 N13 N15 N17 N20 N22 R12 R13 R16 T12 T15 V15 Y13

SC1U6D3V2KX-GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP SCD1U10V2KX-4GP

(GDDR5 1.12V@16A VDDCI)

1

1

1

1

1

1

1

2

C8382
DY

2

C8383
DIS

2

C8384
DIS

2

C8385
DY

2

C8386
DIS

2

C8387 SC1U6D3V2KX-GP
DIS

2

C8388
DIS SC10U10V5KX-2GP

B

M97, Broadway, Madison and Park only

1 L8304

DIS

1

(1.8V@75mA SPV18) 2 BLM15BD121SS1D-GP
C8389 DIS

2

SC4D7U6D3V3KX-GP

2

1

SPV18
C8390
DIS DIS

2

1

C8391 SCD1U10V2KX-4GP

MADISON-PRO-2-GP

DIS

NOTE1:

Back Bias is not supported on M97, Broadway, Madison and Park

For the M96 Back Bias circuitry, refer to REF134

NOTE2: FB_VDDC, FB_VDDCI and FB_GND are not support on M96

SC1U6D3V2KX-GP

NOTE3:

M97 VDDC and VDDCI ball assignments are different from M96.

(M97, Broadway and Madison: 1.8V@150mA MPV18)

If M96 is populated on this design, VDDC and VDDCI will be shorted on the substrate.

(Park: 1.8V@75mA MPV18)

L8305 1

DIS2

BLM18PG471SN1D-GP

MPV18

NOTE4: For M2 design compatibility, refer to the document AN_M96_Ax and AN_M97_Ax

1

1

1

C8393

C8396

C8392 DIS

SCD1U10V2KX-4GP

A

SC4D7U6D3V3KX-GP

2

2

DIS

2

DIS

A

SC1U6D3V2KX-GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU_POWER(4/5)

Size A2

Document Number
Berry

Rev
X00

Date: Thursday, October 22, 2009

Sheet 83

of

92

5

4

3

2

1

5

4

3

2

1

VGA1F

6 OF 8

VGA1H

8 OF 8

D C B

AB39 E39 F34 F39 G33 G34 H31 H34 H39 J31 J34 K31 K34 K39 L31 L34 M34 M39 N31 N34 P31 P34 P39 R34 T31 T34 T39 U31 U34 V34 V39 W31 W34 Y34 Y39

PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS PCIE_VSS

F15 F17 F19 F21 F23 F25 F27 F29 F31 F33
F7 F9 G2 G6 H9 J2 J27 J6 J8 K14 K7 L11 L17 L2 L22 L24 L6 M17 M22 M24 N16 N18 N2 N21 N23 N26 N6 R15 R17 R2 R20 R22 R24 R27 R6 T11 T13 T16 T18 T21 T23 T26 U15 U17 U2 U20 U22 U24 U27 U6 V11 V16 V18 V21 V23 V26 W2 W6 Y15 Y17 Y20 Y22 Y24 Y27 U13 V13

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND GND GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND/PX_EN

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

A3 A37 AA16 AA18 AA2 AA21 AA23 AA26 AA28 AA6 AB12 AB15 AB17 AB20 AB22 AB24 AB27 AC11 AC13 AC16 AC18 AC2 AC21 AC23 AC26 AC28 AC6 AD15 AD17 AD20 AD22 AD24 AD27 AD9 AE2 AE6 AF10 AF16 AF18 AF21 AG17 AG2 AG20 AG22 AG6 AG9 AH21 AJ10 AJ11 AJ2 AJ28 AJ6 AK11 AK31 AK7 AL11 AL14 AL17 AL2 AL20 AL21 AL23 AL26 AL32 AL6 AL8 AM11 AM31 AM9 AN11 AN2 AN30 AN6 AN8 AP11 AP7 AP9 AR5 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B7 B9 C1 C39 E35 E5 F11 F13

VSS_MECH VSS_MECH VSS_MECH

A39 VSS_MECH1 AW1 VSS_MECH2 AW39VSS_MECH3

+1.0V_RUN_VGA (1.0V@110mA DPC_VDD10)
+1.0V_RUN_VGA (1.0V@110mA DPD_VDD10)

DPB_VDD18

DP C/D POWER

AP20 AP21

DPC_VDD18 DPC_VDD18

AP13 AT13

DPC_VDD10 DPC_VDD10

AN17 AP16 AP17 AW14 AW16
DPD_VDD18

DPC_VSSR DPC_VSSR DPC_VSSR DPC_VSSR DPC_VSSR

AP22 AP23

DPD_VDD18 DPD_VDD18

AP14 AP15

DPD_VDD10 DPD_VDD10

DP A/B POWER

DPA_VDD18 DPA_VDD18

AN24 AP24

DPA_VDD10 DPA_VDD10

AP31 AP32

DPA_VSSR DPA_VSSR DPA_VSSR DPA_VSSR DPA_VSSR

AN27 AP27 AP28 AW24 AW26

DPB_VDD18 DPB_VDD18

AP25 AP26

DPB_VDD10 DPB_VDD10

AN33 AP33

DPA_VDD18

+1.0V_RUN_VGA

DPA_VDD10

(1.0V@110mA DPA_VDD10)

L8403 1

DIS2

1

1

1

BLM15BD121SS1D-GP

C8402

C8403

C8405

2

DIS

2

DIS

2

DIS SC10U6D3V5KX-1GP

SC1U6D3V2KX-GP

SCD1U10V2KX-4GP

DPB_VDD18 +1.0V_RUN_VGA
(1.0V@110mA DPB_VDD10)

AN19 AP18 AP19 AW20 AW22

DPD_VSSR DPD_VSSR DPD_VSSR DPD_VSSR DPD_VSSR

DP mode (1.8V@130mA DPE_VDD18)

R8401 DIS

1

2DPCD_CALR AW18

+1.8V_RUN_VGA

150R2F-1-GP

LVDS mode

DPE_VDD18

DIS L8401

(1.8V@200mA DPE_VDD18)

1

2

AH34

BLM18PG471SN1D-GP

AJ34

2

1

1

C8401

C8418

LVDS mode

SC4D7U6D3V3KX-GP DIS

DIS DIS C8419
SCD1U10V2KX-4GP

1

2

2

(1.0V@120mA DPE_VDD10)

AL33

DP mode

DPE_VDD10

AM33

(1.0V@110mA DPE_VDD10)

DPCD_CALR
DP E/F POWER DPE_VDD18 DPE_VDD18
DPE_VDD10 DPE_VDD10

DPB_VSSR DPB_VSSR DPB_VSSR DPB_VSSR DPB_VSSR

AN29 AP29 AP30 AW30 AW32

R8404

DPAB_CALR

AW28DPAB_CALR1

2

150R2F-1-GP

DP PLL POWER
DPA_PVDD DPA_PVSS

AU28 AV27

DIS

DPB_PVDD DPB_PVSS

AV29 AR28

SCD1U10V2KX-4GP

+1.8V_RUN_VGA

DPA_PVDD

(1.8V@20mA DPA_PVDD)

L8404 1

DIS2

BLM15BD121SS1D-GP

1

1

C8412

1

C8413

2

DIS

2

2

DIS DIS C8414
SC4D7U6D3V3KX-GP

SC1U6D3V2KX-GP

(1.8V@20mA DPB_PVDD)

SC1U6D3V2KX-GP

+1.0V_RUN_VGA

L8408 1

DIS2

BLM15BD121SS1D-GP

C8404

SC4D7U6D3V3KX-GP

1

DIS

2

DP mode (1.8V@130mA DPF_VDD18) LVDS mode (1.8V@200mA DPF_VDD18)

+1.8V_RUN_VGA

L8405 DIS

1

2

BLM18PG471SN1D-GP

C8423

SC4D7U6D3V3KX-GP

1

DIS

2

LVDS mode (1.0V@120mA DPF_VDD10) DP mode (1.0V@110mA DPF_VDD10)

+1.0V_RUN_VGA

L8407 1

DIS2

BLM15BD121SS1D-GP

C8426

SC4D7U6D3V3KX-GP

1

DIS

2

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

2

1

1

1

2

C8424

C8425

DIS DISSCD1U10V2KX-4GP

2

DPF_VDD18

2

1

C8427 C8428
DIS DISSCD1U10V2KX-4GP
DPF_VDD10

1

1

C8433
DIS

2

C8434
DIS

2

AN34 AP39 AR39 AU37

DPE_VSSR DPE_VSSR DPE_VSSR DPE_VSSR

AF34 AG34

DPF_VDD18 DPF_VDD18

AK33 AK34

DPF_VDD10 DPF_VDD10

AF39 AH39 AK39 AL34 AM34

DPF_VSSR DPF_VSSR DPF_VSSR DPF_VSSR DPF_VSSR

2

DPC_PVDD DPC_PVSS

AU18 AV17

(1.8V@20mA DPC_PVDD)

DPD_PVDD DPD_PVSS
DPE_PVDD DPE_PVSS

AV19 AR18

(1.8V@20mA DPD_PVDD)

DPF_PVDD
(1.8V@20mA DPE_PVDD) AM37 AN38

DPF_PVDD DPF_PVSS

AL38 AM35

1

(1.8V@20mA DPF_PVDD)

L8406 1

DIS2

BLM15BD121SS1D-GP

1

1

C8429

C8430

DIS

DIS DIS C8416
SC4D7U6D3V3KX-GP

2

2

SC1U6D3V2KX-GP

SCD1U10V2KX-4GP

AM39 DPEF_CALR
MADISON-PRO-2-GP
DIS

2DPEF_CALR

R8406
DIS 150R2F-1-GP

SCD1U10V2KX-4GP

SC1U6D3V2KX-GP

1

TPAD14-GP1 TPAD14-GP1 TPAD14-GP1

TP8401 TP8402 TP8403

For M97/M96, DPF_VDD18 can be shared with DPE_VDD18 For M97/M96, DPF_VDD10 can be shared with DPE_VDD10
For dual link DVI using DPA AND DPB, DPA_VDDxx and DPB_VDDxx can be shared respectively For dual link DVI using DPC AND DPD, DPC_VDDxx and DPD_VDDxx can be shared respectively For dual link LVDS, DPE_VDDxx and DPF_VDDxx can be shared respectively

DNI for M96/M92

+1.8V_RUN_VGA

DPA_VDD18

SC1U6D3V2KX-GP

L8402 1

DIS2

(1.8V@130mA DPA_VDD18)

BLM15BD121SS1D-GP

1

1

C8407

C8406 DIS
SC4D7U6D3V3KX-GP

2

2

DIS DIS

1

2

C8408 SCD1U10V2KX-4GP

DPB_VDD18

DIS

(1.8V@130mA DPB_VDD18)

1

2

R8402

0R2J-2-GP

1

1

DY
C8409 SC4D7U6D3V3KX-GP

C8410
DY DIS

2

C8411 SCD1U10V2KX-4GP

1

2

SC1U6D3V2KX-GP

2

DPD_VDD18

DIS

1

2

(1.8V@130mA DPD_VDD18)

R8405

0R2J-2-GP

2

1

1

DY
C8415

C8421 Madison

SC4D7U6D3V3KX-GP

2

2

DY

1

C8422

SCD1U10V2KX-4GP

SC1U6D3V2KX-GP

D C B

MADISON-PRO-2-GP

DIS

A

A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
GPU_DPPWR/GND(5/5)

Size

Document Number

A2

Berry

Rev
X00

Date: Tuesday, October 20, 2009

Sheet 84

of

92

5

4

3

2

1

5

4

3

2

1

+1.5V_RUN

+1.5V_RUN

VRAM1

VRAM2

SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP
SC10U10V5KX-2GP SC10U6D3V5KX-1GP

D

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC1U10V2KX-1GP

SCD1U10V2KX-4GP

SC1U10V2KX-1GP

K8

1

1

SC1U6D3V2KX-GP

C8514

1

1

1

1

SC1U6D3V2KX-GP

K2

C8510

1

C8507

C8508

C8509 C8512 C8511

C8513

N1

1

R9

B2

2

2

2

2

2

2

2

2

MMadaidsiosnon MadisonMadisoMnadisoMnadisMoandisonMadison D9

G7

R1

N9

A8

A1

C8502

C8505

C1

1

1

C9

Madison Madison D2

2

2

E9

F1

H9

H2

VRAM1_VREF

H1

VRAM2_VREF

M8

1

2 VRAM_ZQ1 L8

R8503 Madison 243R2F-2-GP

VDD VDD VDD VDD VDD VDD VDD VDD VDD
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VREFDQ VREFCA ZQ

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

E3 F7 F2 F8 H3 H8 G2 H7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

D7 C3 C8 C2 A7 A2 B8 A3

DQSU DQSU#

C7 B7

DQSL DQSL#

F3 G3

MDA3 MDA7 MDA1 MDA6 MDA2 MDA4 MDA0 MDA5
MDA20 MDA19 MDA23 MDA18 MDA22 MDA16 MDA21 MDA17

MDA[0..31]
QSAP_2 QSAN_2 QSAP_0 QSAN_0

C8525

SCD1U16V2KX-3GP

2

1

C8524

DY
Madison

SC1U6D3V2KX-GP

2

1

C8516

SC1U6D3V2KX-GP

SC1U10V2KX-1GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SC1U10V2KX-1GP

K8

1

1

C8519

1

SC1U6D3V2KX-GP

K2

C8517

1

C8518

C8515

C8520

N1

1

1

R9

B2

2

2

2

2

2

2

MadisonMadison MadisoMnadisMonadison D9

Madison

G7 R1

N9

1

A8

A1

C8521

C8522

C1

1

C9

D2

2

MadisonMadison E9

F1

H9

H2

2

VRAM2_VREF

H1

VRAM1_VREF

M8

1

2VRAM_ZQ2 L8

R8504 Madison 243R2F-2-GP

VDD VDD VDD VDD VDD VDD VDD VDD VDD
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VREFDQ VREFCA ZQ

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

E3 F7 F2 F8 H3 H8 G2 H7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

D7 C3 C8 C2 A7 A2 B8 A3

DQSU DQSU#

C7 B7

DQSL DQSL#

F3 G3

MDA29 MDA24 MDA30 MDA26 MDA28 MDA27 MDA25 MDA31
MDA8 MDA14 MDA9 MDA10 MDA15 MDA12 MDA13 MDA11

MDA[0..31]
QSAP_1 QSAN_1 QSAP_3 QSAN_3

D

MAA0

MAA1

MAA2

MAA3

MAA4

MAA5

MAA6

MAA7

MAA8

MAA9

C

MAA10

MAA11

MAA12

MAA13

20090902
CLKA0 CLKA0#

1

R8508

R8507

56R2J-4-GP

Madison56R2J-4-GP

1

A_BA0 A_BA1 A_BA2
CKEA0
DQMA2
Madison DQMA0

2

2

1

GPU_CLKA0_T
C8503 Madison

WEA0# CASA0# RASA0#

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 NC#M7

M2 N8 M3

BA0 BA1 BA2

J7 K7

CK CK#

K9 CKE

D3 E7

DMU DML

L3 K3 J3

W E# CAS# RAS#

ODT K1

CS# RESET#

L2 T2

NC#T7 NC#L9 NC#L1 NC#J9 NC#J1

T7 L9 L1 J9 J1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

G1 F9 E8 E2 D8 D1 B9 B1 G9

ODTA0
CSA0#_0 MEM_RST

MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13
A_BA0 A_BA1 A_BA2
CLKA0 CLKA0#
CKEA0
DQMA1 DQMA3
WEA0# CASA0# RASA0#

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 NC#M7

M2 N8 M3

BA0 BA1 BA2

J7 K7

CK CK#

K9 CKE

D3 E7

DMU DML

L3 K3 J3

W E# CAS# RAS#

ODT K1

CS# RESET#

L2 T2

NC#T7 NC#L9 NC#L1 NC#J9 NC#J1

T7 L9 L1 J9 J1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

G1 F9 E8 E2 D8 D1 B9 B1 G9

ODTA0
CSA0#_0 MEM_RST

C

SCD01U50V2KX-1GP B

2

K4W1G1646E-HC12-GP
Madison
20090902
+1.5V_RUN

K4W1G1646E-HC12-GP

20090902

Madison

B

+1.5V_RUN

1

1

2

R8510 2K1R2F-GP
Madison
VRAM1_VREF

1

R8511 2K1R2F-GP
Madison

2

C8504
Madison
SCD1U16V2ZY-2GP

2

1

2

R8513 2K1R2F-GP
Madison
VRAM2_VREF

1

R8512 2K1R2F-GP
Madison

2

C8506
Madison
SCD1U16V2ZY-2GP

1

2

A

<Core Design>

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU-VRAM1,2 (1/4)

Size

Document Number

Rev

Custom Berry

X00

Date: Thursday, October 22, 2009

Sheet 85

of

92

5

4

3

2

1

5

4

3

2

1

+1.5V_RUN

VRAM3

+1.5V_RUN

VRAM4

D

C8602

SC1U6D3V2KX-GP

1

SC1U6D3V2KX-GP

C8613

1

SC1U6D3V2KX-GP

C8614

1

SC1U6D3V2KX-GP

C8611

1

SC1U6D3V2KX-GP

C8612

1

SC1U10V2KX-1GP

1

C8609

SC1U6D3V2KX-GP

C8610

1

SC1U10V2KX-1GP

1

C8607

K8 K2 N1 R9 B2
MadisoMnadisoMnadisoMnadisoMnadisoMnadisoMnadisoMnadison D9
G7 R1 N9

2

2

2

2

2

2

2

2

SC10U6D3V5KX-1GP

SC10U10V5KX-2GP

A8

A1

C8606

C1

1

1

C8608

C9

D2

2

2

Madison Madison E9

F1

H9

H2

VRAM3_VREF VRAM4_VREF

H1

M8

1

2VRAM_ZQ3 L8

R8603 Madison 243R2F-2-GP

VDD VDD VDD VDD VDD VDD VDD VDD VDD
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VREFDQ VREFCA ZQ

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

E3 F7 F2 F8 H3 H8 G2 H7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

D7 C3 C8 C2 A7 A2 B8 A3

DQSU DQSU#

C7 B7

DQSL DQSL#

F3 G3

MDA36 MDA38 MDA33 MDA39 MDA32 MDA34 MDA35 MDA37
MDA46 MDA43 MDA45 MDA40 MDA44 MDA41 MDA47 MDA42

MDA[32..63]
QSAP_5 QSAN_5 QSAP_4 QSAN_4

C8621

SCD1U16V2KX-3GP

2

1

SCD1U10V2KX-4GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

K8

1

SC1U6D3V2KX-GP

C8615

1

SC1U6D3V2KX-GP

C8616

1

C8624

1

C8625

1

SC1U10V2KX-1GP

C8622

1

SC1U6D3V2KX-GP

K2

C8623

1

C8618

N1

DY

R9 B2

2

2

2

MadisonMadisMonadisoMnadisonMadisonMadisMoandison

2

2

2

2

D9

G7

R1

N9

SC10U6D3V5KX-1GP

1

SC10U6D3V5KX-1GP

C8617
Madison

2

1

A8

A1

C8619

C1

C9

Madison D2

E9

F1

H9

H2

2

VRAM4_VREF VRAM3_VREF

H1

M8

1

2VRAM_ZQ4 L8

R8604 Madison 243R2F-2-GP

VDD VDD VDD VDD VDD VDD VDD VDD VDD
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VREFDQ VREFCA ZQ

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

E3 F7 F2 F8 H3 H8 G2 H7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

D7 C3 C8 C2 A7 A2 B8 A3

DQSU DQSU#

C7 B7

DQSL DQSL#

F3 G3

MDA61 MDA57 MDA63 MDA60 MDA59 MDA56 MDA62 MDA58
MDA50 MDA55 MDA49 MDA52 MDA48 MDA54 MDA51 MDA53

MDA[32..63]
QSAP_6 QSAN_6 QSAP_7 QSAN_7

D

MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13
C

A_BA0 A_BA1 A_BA2

CLKA1 CLKA1#

1

CKEA1

1

R8607 56R2J-4-GP
Madison

2

R8608 56R2J-4-GP
Madison

DQMA5 DQMA4

2

1

GPU_CLKA1_T
C8603 Madison

WEA1# CASA1# RASA1#

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 NC#M7

M2 N8 M3

BA0 BA1 BA2

J7 K7

CK CK#

K9 CKE

D3 E7

DMU DML

L3 K3 J3

W E# CAS# RAS#

ODT K1

CS# RESET#

L2 T2

NC#T7 NC#L9 NC#L1 NC#J9 NC#J1

T7 L9 L1 J9 J1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

G1 F9 E8 E2 D8 D1 B9 B1 G9

ODTA1 CSA1#_0 MEM_RST
CLKA1 CLKA1#

MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13
A_BA0 A_BA1 A_BA2
CKEA1
DQMA6 DQMA7
WEA1# CASA1# RASA1#

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 NC#M7

M2 N8 M3

BA0 BA1 BA2

J7 K7

CK CK#

K9 CKE

D3 E7

DMU DML

L3 K3 J3

W E# CAS# RAS#

ODT K1

CS# RESET#

L2 T2

NC#T7 NC#L9 NC#L1 NC#J9 NC#J1

T7 L9 L1 J9 J1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

G1 F9 E8 E2 D8 D1 B9 B1 G9

ODTA1
CSA1#_0 MEM_RST

C

SCD01U50V2KX-1GP

K4W1G1646E-HC12-GP

K4W1G1646E-HC12-GP

2

Madison

Madison

20090902

20090902

B

20090902

+1.5V_RUN

B

+1.5V_RUN

1

1

2

R8601 2K1R2F-GP
Madison

VRAM3_VREF

1

R8602 2K1R2F-GP
Madison

2

C8601
Madison
SCD1U16V2ZY-2GP

2

1

2

R8605 2K1R2F-GP
Madison

VRAM4_VREF

1

R8606 2K1R2F-GP
Madison

2

C8605
Madison
SCD1U16V2ZY-2GP

1

2

A

<Core Design>

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU-VRAM3,4 (2/4)

Size

Document Number

Custom

Berry

Rev
X00

Date: Thursday, October 22, 2009

Sheet 86

of

92

5

4

3

2

1

5

4

3

2

1

+1.5V_RUN

VRAM5

D

C8702 SC1U10V2KX-1GP
DI2S 1
C8707 SCD1U16V2KX-3GP
DI2S 1
C8710 SC1U6D3V2KX-GP
DI2S 1
C8709 SCD1U16V2KX-3GP
DI2S 1
C8711 SC1U10V2KX-1GP
DI2S 1
C8712 SC1U10V2KX-1GP
DI2S 1
C8713 SC1U10V2KX-1GP
DI2S 1
C8714 SC1U6D3V2KX-GP
DI2S 1

VRAM5_VREF VRAM6_VREF

SC10U10V5KX-2GP
DI2S 1
SC10U6D3V5KX-1GP
DI2S 1

C8706 1
R8704 DIS

C8708 2 VRAM_ZQ5
243R2F-2-GP

K8 K2 N1 R9 B2 D9 G7 R1 N9

VDD VDD VDD VDD VDD VDD VDD VDD VDD

A8 A1 C1 C9 D2 E9 F1 H9 H2

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

H1 M8 L8

VREFDQ VREFCA ZQ

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

E3 F7 F2 F8 H3 H8 G2 H7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

D7 C3 C8 C2 A7 A2 B8 A3

DQSU DQSU#

C7 B7

DQSL DQSL#

F3 G3

MDB14 MDB13 MDB12 MDB15 MDB11 MDB8 MDB9 MDB10
MDB26 MDB27 MDB30 MDB24 MDB31 MDB25 MDB29 MDB28

MAB0

MAB1

MAB2

MAB3

MAB4

MAB5

MAB6

MAB7

MAB8

MAB9

MAB10

MAB11

MAB12

C

MAB13

20090902

B_BA0 B_BA1 B_BA2

CLKB0 CLKB0#

1

R8707 56R2J-4-GP
DIS

R8708 56R2J-4-GP
DIS

2

GPU_CLKB0_T

1

C8703 DIS

2

1

CKEB0
DQMB3 DQMB1
W EB0# CASB0# RASB0#

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 NC#M7

M2 N8 M3

BA0 BA1 BA2

J7 K7

CK CK#

K9 CKE

D3 E7

DMU DML

L3 K3 J3

WE# CAS# RAS#

ODT K1

CS# RESET#

L2 T2

NC#T7 NC#L9 NC#L1 NC#J9 NC#J1

T7 L9 L1 J9 J1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

G1 F9 E8 E2 D8 D1 B9 B1 G9

SCD01U50V2KX-1GP

2

K4W 1G1646E-HC12-GP
DIS

B

20090902

+1.5V_RUN

MDB[0..31]
QSBP_3 QSBN_3 QSBP_1 QSBN_1 ODTB0 CSB0#_0 MEM_RST

C8717 SC1U6D3V2KX-GP
DI2S 1

C8715 SC1U6D3V2KX-GP
DI2S 1

C8720 SC1U6D3V2KX-GP
DI2S 1

+1.5V_RUN

VRAM6

C8721 SCD1U16V2KX-3GP
DI2S 1

DY
VRAM6_VREF VRAM5_VREF

C8723

SC1U6D3V2KX-GP

2

1

C8722 SC1U6D3V2KX-GP
DI2S 1

C8725 SCD1U10V2KX-4GP
DI2S 1

C8724 SC1U6D3V2KX-GP
DI2S 1

K8 K2 N1 R9 B2 D9 G7 R1 N9

SC10U6D3V5KX-1GP
DI2S 1
SC10U10V5KX-2GP
DI2S 1

A8

A1

C8718

C8719

C1

C9

D2

E9

F1

H9

H2

1
R8706 DIS

H1 M8 2 VRAM_ZQ6 L8 243R2F-2-GP

VDD VDD VDD VDD VDD VDD VDD VDD VDD
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VREFDQ VREFCA ZQ

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

E3 F7 F2 F8 H3 H8 G2 H7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

D7 C3 C8 C2 A7 A2 B8 A3

DQSU DQSU#

C7 B7

DQSL DQSL#

F3 G3

MDB16 MDB18 MDB20 MDB19 MDB22 MDB17 MDB23 MDB21
MDB1 MDB5 MDB2 MDB4 MDB3 MDB7 MDB0 MDB6

MDB[0..31]
QSBP_0 QSBN_0 QSBP_2 QSBN_2

D

CLKB0 CLKB0#

MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 MAB13
B_BA0 B_BA1 B_BA2
CKEB0
DQMB0 DQMB2
W EB0# CASB0# RASB0#

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 NC#M7

M2 N8 M3

BA0 BA1 BA2

J7 K7

CK CK#

K9 CKE

D3 E7

DMU DML

L3 K3 J3

WE# CAS# RAS#

ODT K1

CS# RESET#

L2 T2

NC#T7 NC#L9 NC#L1 NC#J9 NC#J1

T7 L9 L1 J9 J1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

G1 F9 E8 E2 D8 D1 B9 B1 G9

ODTB0 CSB0#_0 MEM_RST
C

K4W 1G1646E-HC12-GP
DIS

20090902

B

+1.5V_RUN

1

1

2

R8701 2K1R2F-GP
DIS
VRAM5_VREF

1

R8702 2K1R2F-GP

DIS

DIS

2

C8701 SCD1U16V2ZY-2GP

1

2

R8703 2K1R2F-GP
DIS
VRAM6_VREF

1

R8705 2K1R2F-GP

DIS

DIS

2

C8705 SCD1U16V2ZY-2GP

1

2

2

A

<Core Design>

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU-VRAM5,6 (3/4)

Size A3

Document Number
Berry

Rev
X00

Date: Thursday, October 22, 2009

Sheet 87

of

92

5

4

3

2

1

5

4

+1.5V_RUN

VRAM7

D

C8802 SC1U6D3V2KX-GP
DI2S 1

C8808 SC1U10V2KX-1GP
DI2S 1

C8809 SC1U10V2KX-1GP
DI2S 1

C8810 SC1U10V2KX-1GP
DI2S 1

VRAM7_VREF VRAM8_VREF

C8811 SCD1U10V2KX-4GP
DI2S 1

C8812 SCD1U16V2KX-3GP
DI2S 1
C8813 SC1U10V2KX-1GP
DI2S 1
C8814 SC1U6D3V2KX-GP
DI2S 1

K8 K2 N1 R9 B2 D9 G7 R1 N9

SC10U6D3V5KX-1GP

1

SC10U10V5KX-2GP

A8

A1

C8806

C8807

C1

1

C9

DIS DIS

D2

2

E9

F1

H9

H2

2

1
R8803 DIS

H1 M8 2 VRAM_ZQ7 L8 243R2F-2-GP

VDD VDD VDD VDD VDD VDD VDD VDD VDD
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VREFDQ VREFCA ZQ

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

E3 F7 F2 F8 H3 H8 G2 H7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

D7 C3 C8 C2 A7 A2 B8 A3

DQSU DQSU#

C7 B7

DQSL DQSL#

F3 G3

MDB40 MDB43 MDB47 MDB44 MDB41 MDB45 MDB42 MDB46
MDB36 MDB35 MDB39 MDB32 MDB37 MDB33 MDB38 MDB34

MAB0

MAB1

MAB2

MAB3

MAB4

MAB5

MAB6

MAB7

MAB8

MAB9

MAB10

C

MAB11

MAB12

MAB13

20090902

B_BA0 B_BA1 B_BA2

CLKB1 CLKB1#
R8807 56R2J-4-GP
DIS

2

1

R8808 56R2J-4-GP
DIS
GPU_CLKB1_T

1

C8803 DIS

2

1

CKEB1
DQMB4 DQMB5
W EB1# CASB1# RASB1#

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 NC#M7

M2 N8 M3

BA0 BA1 BA2

J7 K7

CK CK#

K9 CKE

D3 E7

DMU DML

L3 K3 J3

WE# CAS# RAS#

ODT K1

CS# RESET#

L2 T2

NC#T7 NC#L9 NC#L1 NC#J9 NC#J1

T7 L9 L1 J9 J1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

G1 F9 E8 E2 D8 D1 B9 B1 G9

SCD01U50V2KX-1GP

2

K4W 1G1646E-HC12-GP

B

DIS

20090902

+1.5V_RUN

1

2

R8801 2K1R2F-GP
DIS
VRAM7_VREF

1

R8802 2K1R2F-GP

DIS

DIS

2

C8801 SCD1U16V2ZY-2GP

1

2

A

5

4

3

2

1

MDB[32..63]
DY
QSBP_4 QSBN_4 QSBP_5 QSBN_5 ODTB1 CSB1#_0 MEM_RST
CLKB1 CLKB1#

C8816

SC1U6D3V2KX-GP

2

1

C8819 SC1U10V2KX-1GP
DI2S 1

C8820 SC1U10V2KX-1GP
DI2S 1

C8821 SCD1U16V2KX-3GP
DI2S 1

+1.5V_RUN

VRAM8

MDB[32..63]

C8822

SC1U6D3V2KX-GP

1

C8823

DY DY

2

2

SC10U6D3V5KX-1GP

1

C8817
DIS

2

VRAM8_VREF VRAM7_VREF

1 R8804

DIS

SC1U6D3V2KX-GP

1

C8824 SC1U6D3V2KX-GP
DI2S 1

SC10U6D3V5KX-1GP

2

1

C8825 SCD1U10V2KX-4GP
DI2S 1

C8818
DIS
2 VRAM_ZQ8 243R2F-2-GP

K8 K2 N1 R9 B2 D9 G7 R1 N9

VDD VDD VDD VDD VDD VDD VDD VDD VDD

A8 A1 C1 C9 D2 E9 F1 H9 H2

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

H1 M8 L8

VREFDQ VREFCA ZQ

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

E3 F7 F2 F8 H3 H8 G2 H7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

D7 C3 C8 C2 A7 A2 B8 A3

DQSU DQSU#

C7 B7

DQSL DQSL#

F3 G3

MDB53 MDB51 MDB55 MDB49 MDB54 MDB48 MDB52 MDB50
MDB61 MDB62 MDB58 MDB59 MDB63 MDB56 MDB57 MDB60

QSBP_7 QSBN_7
QSBP_6 QSBN_6

D

MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 MAB13
B_BA0 B_BA1 B_BA2
CKEB1
DQMB7 DQMB6
W EB1# CASB1# RASB1#

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 M7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 NC#M7

M2 N8 M3

BA0 BA1 BA2

J7 K7

CK CK#

K9 CKE

D3 E7

DMU DML

L3 K3 J3

WE# CAS# RAS#

ODT K1

CS# RESET#

L2 T2

NC#T7 NC#L9 NC#L1 NC#J9 NC#J1

T7 L9 L1 J9 J1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

G1 F9 E8 E2 D8 D1 B9 B1 G9

ODTB1 CSB1#_0 MEM_RST
C

K4W 1G1646E-HC12-GP

DIS

B

20090902

+1.5V_RUN

1

2

R8805 2K1R2F-GP
DIS
VRAM8_VREF

1

R8806 2K1R2F-GP

DIS

DIS

2

C8804 SCD1U16V2ZY-2GP

1

2

<Core Design>

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

GPU-VRAM7,8 (4/4)

Size A3

Document Number
Berry

Rev
X00

Date: Thursday, October 22, 2009

Sheet 88

of

92

3

2

1

5

4

3

2

1

SSID = Video.PWR.Regulator RT8208BGQW for +VGA_CORE

D

D

+PW R_SRC

PC8907 SC2200P50V2KX-2GP

1

PC8911 SCD1U25V2KX-GP

1

SC10U25V6KX-1GP PC8905

1

PC8903 SC10U25V6KX-1GP

1

PC8914 SC10U25V6KX-1GP

1

+5V_ALW

PU8902 SI7686DP-T1-GP

5

6

D

7

D

8

D

D

2

DIS DIS DIS

2

2

2

DY DY

2

Vout=0.75V*(R1+R2)/R2

1

PC8908
DIS
SC1U10V2KX-1GP

+GFX_CORE_TON

PR8910
1 DIS 2
249KR2F-GP

DIS

G

S

S

S

Design Current = 21.94A 24.14A<OCP< 28.53A

1

2

3

4

2

PU8901

PR8902

PC8906

PR8903
2 DIS 1
10R2F-L-GP

16 9

TON VDDP

+GFX_CORE_VDD 2 VDD

BOOT 13

UGATE PHASE LGATE

12 11 8

+GFX_CORE_BOO2T DIS 1+GFX_CORE_BOOT_1C DIS2
1R3J-L1-GP

+GFX_CORE_UGATE

SCD1U25V3KX-GP

+GFX_CORE_PHASE

+GFX_CORE_LGATE

1

PL8901

1

2

IND-D56UH-12-GP

DIS

C

RUNPW ROK

PC8904

1

DIS

DIS
1 PR8905

4 2+GFX_CORE_CS 10 6K34R2F-GP +GFX_CORE_EN_R 15

DIS PGOOD

G0

CS

FB

G1

D1

EM/DEM

D0

7 3 14 5 6

+GFX_CORE_FB
PW RCNTL_1# PW RCNTL_0#

PW RCNTL_0 PW RCNTL_1

SC1U10V2KX-1GP

2

17 GND

VOUT 1 +GFX_CORE_VOUT

PU8903

5

6

D

7

D

8

D

D

PU8904

8

7

6

5

D

D

D

D

DIS

DIS

DY PR8906
2D2R5F-2-GP

2

1

PC8915

SCD1U10V2KX-4GP

+VGA_CORE

1

1

1

1

PTC8901 PTC8902 PTC8903 C

2

2

DY DY

2

DIS DIS

2

PC8913 SC10P50V2JN-4GP

1

PC8917 SC10P50V2JN-4GP

PG8920 GAP-CLOSE-PWR-3-GP

1

1VGA_CORE_DIV 2

SIR460DP-T1-GE3-GP

SIR460DP-T1-GE3-GP

SE330U2VDM-L-GP SE330U2VDM-L-GP SE330U2VDM-L-GP

S

S

S

G

S

S

S

G

RT8208BGQW -GP
RT8208B:74.08208.A73

4

3

2

1

4

3

2

1

+GFX_CORE_VOUT

2

DY PC8910

PR8908 10KR2F-2-GP
DIS

1

2

DY DY

2

SC330P50V3KX-GP

2

GFX_CORE_EN PM_SLP_S3#

PR8921 1 DY 2 0R2J-2-GP

DIS PR8920 1

2 10KR2J-3-GP

+GFX_CORE_EN_R

1

PC8912 SCD1U6D3V2KX-GP

2

B

+GFX_CORE_FB

1

1

1

DIS

PR8909 150KR2F-L-GP

PR8911 49K9R2F-L-GP
DIS

PR8912 49K9R2F-L-GP
DIS

2

2

2

B

PWRCNTL_1#

PWRCNTL_0#

PWRCNTL_0 H L H L

PWRCNTL_1 H H L L

+VGA_CORE 0.9V 0.95V 1.05V 1.1V

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L

A

Inductor: 0.56uH PCMC104T-R56MN Cyntec DCR:1.6mohm/1.8mohm Isat=25Arms 68.R5610.10D

O/P cap: 330U 2.5V PSLV0E337M(15) 15mOhm 2.886Arms NEC_TOKIN/ 77.C3371.10L

H/S: SI7686DP/ POWERPAK-8/11mOhm/14mOhm@4.5Vgs/ 84.07686.037

L/S: SiR460DP/ POWERPAK-8/ 4.9mOhm/6.1mohm@4.5Vgs/ 84.00460.037

5

4

3

<Core Design>

A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

RT8208B_+VGA_CORE

Size

Document Number

A3

Arsenal DJ1 Discrete

Rev
X00

Date: Thursday, October 22, 2009

Sheet 89

of

92

2

1

5

4

3

2

APL5930 for +1.8V_RUN_VGA

+1.8V_RUN_VGA_P

+1.8V_RUN_VGA

PG9002

+3.3V_RUN

+1.8V_RUN_VGA_VIN

+5V_RUN

+1.8V_RUN_VGA_VIN

1

2

GAP-CLOSE-PWR

PG9003

2

2

2

SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP

D

PG9001

PC9002

1

1

1

PC9003

PC9004

1

2

2

1

DIS
SC1U10V2KX-1GP

DY

GAP-CLOSE-PWR

GAP-CLOSE-PWR PG9004

DIS

+5V_ALW

2

1

GAP-CLOSE-PWR

Design Current =1.13A

PU9001

VCNTL 6

2

DIS

R9006 100KR2J-1-GP

RUNPWROK

1.8V_VGA_RUN_EN

DIS 1

21.8V_VGA_RUN_EN_C

PR9002

0R2J-2-GP

Vo=0.8*(1+(R1/R2))

1

PC9001

DY

7 POK

VIN#5 VIN#9

5 9

DIS 8 EN

VOUT#3 VOUT#4

3 4

FB 2

1 GND

2

APL5930KAI-TRG-GP

SO-8-P

2

+1.8V_RUN_VGA_P

1

PR9003

1

PC9005

2

DIS DIS

2

1

PC9006

PC9007

1

DIS DY

2

5912_1.8V_DELAY_FB

SC4700P50V2KX-1GP

6 1.8V_DIS_GATE 1

SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP
SC68P50V2JN-1GP 16K5R2F-2-GP

4

5

DIS

1

2

3

PQ9001

+1.8V_RUN_VGA

2N7002EDW-GP

84.27002.F3F

DIS

1.8V_DIS 1

2

R9005

10R2J-2-GP

Vout=0.8V*(R1+R2)/R2

1

DIS

PR9006 13K3R2F-L1-GP

2

1.8V_VGA_RUN_EN C

+3.3V_RUN_VGA

+3.3V_RUN

1 DIS 2

R9001

0R2J-2-GP

Q9001

+3.3V_RUN_VGA

DY S

D

SI2301CDS-T1-GE3-GP

1

DY R9002
100KR2J-1-GP

G

Id: 2A Rds: 0.15ohm

2

3.3V_ALW_1

1

4

5

6

Q9002

2N7002EDW-GP
84.27002.F3F

DY

2

R9004
DY 100R2J-2-GP

3

2

1

B 3.3V_RUN_VGA_EN

3.3V_RUN_VGA_1

APL5930KAI for +1.0V_RUN_VGA

+5V_ALW

+1.5V_SUS

1

1

1

SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP

PC9008
DIS
SC1U10V2KX-1GP

2

2

PC9009
DIS

2

PC9010
DY

SCD01U16V2KX-3GP

SC4700P50V2KX-1GP

6 1.0V_DIS_GATE 1

+3.3V_ALW

2

DIS

R9007 100KR2J-1-GP

1.0V_RUN_VGA_EN

PU9002

RUNPWROK

DIS 1

21.0V_RUN_VGA_EN_C

PR9007

0R2J-2-GP

7 POK 8 EN

VIN#5 VIN#9

5 9

VOUT#3 VOUT#4

3 4

1

PC9011

DIS

DY

FB 2

1 GND

2

APL5930KAI-TRG-GP
SO-8-P

VCNTL 6

2

1

+1.0V_RUN_VGA Design Current: 1.51A
+1.0V_RUN_VGA

PR9009
DIS

2

1

2

PC9012
DIS

1

PC9013
DIS

1

PC9014
DY

2

SC10U6D3V3MX-GP SC10U6D3V3MX-GP
12KR2F-L-GP

4

5

DIS

1

2

3

PQ9002 2N7002EDW-GP
84.27002.F3F

+1.0V_RUN_VGA

DIS

1.0V_DIS 1

2

R9010

10R2J-2-GP

1.0V_RUN_VGA_EN

5930_1.0VRUN_FB

1

Vout=0.8V*(R1+R2)/R2

PR9011

DIS 32K4R2F-1-GP

2

1 D C B

A

A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
DISCRETE VGA POWER

Size

Document Number

C

Berry

Rev
X00

Date: Thursday, October 22, 2009

Sheet 90

of

92

5

4

3

2

1

5

4

D15 Intel-Power Up Sequence

(AC mode)

red word: KBC GPIO

+RTC_VCC T1
PCH_RTCRST#

+PWR_SRC T2

+3.3V_RTC_LDO T3

D

S5_ENABLE

T4

+5V_ALW T5

+3.3V_ALW T6

+5VALW_PCH_VCC5REFSUS

KBC GPIO36 control

+15V_ALW 3V_5V_POK SUS_PWR_DN_ACK PCH_RSMRST#(EC Delay 40ms) PCH_SUSCLK_KBC AC_PRESENT_EC

T7 T8
T9 T10
>10ms T11
T12 <200ms

TPS51125 to KBC GPIO46 PCH to KBC GPI94
KBC GPIO43 to PCH PCH to KBC GPIO00

AC KBC_PWRBTN_EC# AC PM_PWRBTN#

Press Power button 3V_5V_POK
T13

KBC_PWRBTN_EC# GPIO3 KBC GPO84 to PCH

AC PM_PWRBTN# T14

PM_SLP_S4# T15

PM_SLP_S3#

>30us

T16

C

PM_LAN_ENABLE T17

+3.3V_LAN

KBC GPO16 to LAN

+1.5V_SUS

T18

+V_DDR_REF(0.9V) +5V_RUN

T19 T20

+5V_RUN & +3.3V_RUN need meet 0.7V difference

+3.3V_RUN +5VS_PCH_VCC5REF

T21 T22

+1.5V_RUN

T23

+1.8V_RUN

T24

GFX_CORE_EN(Discrete only)

+VGA_CORE(Discrete only)

1.0V_RUN_VGA_EN(Discrete only)

+1.0V_RUN_VGA(Discrete only)

1.8V_VGA_RUN_EN(Discrete only)

+1.8V_RUN_VGA(Discrete only)

+3.3V_RUN_VGA_EN(Discrete only)-->DY reserved

+3.3V_RUN_VGA(Discrete only) -->Reserved for sequence

H_PWRGD T25 >1ms
T26 T27 T28

KBC GPIO71 to RT8208B KBC GPIO30 to APL5930

T29 T30

KBC GPIO66 to APL5930

T31 T32
T33

KBC GPI95

RUNPWROK

T34

T35

+1.05V_VTT

B

T36

TPS51218 to KBC GPI34

1.5CPU_1.05VTT_PWRGD(after delay 1ms GPI96-VDDPWRGOOD_EC output for s3 reduction)

T37 +0.75V_DDR_VTT

H_VTTPWRGD

T38

+1.05V_VTT

T39

GFX_VR_EN(UMA only)

+CPU_GFX_CORE(UMA only)

T40

CPU to TPS51611

UMA GFX CORE Power

1.5CPU_1.05VTT_PWRGD IMVP_VR_ON +VCC_CORE

T41 ( >99ms )

T42 <3m s

KBC GPO53 to ISL62883

CPU CORE Power

CLK_CPU_BCLK

CLKIN_BCLK(from CK505) stable

43 >1ms

ISL62883 to CLOCKGEN

CK_PWRGD IMVP_PWRGD

T44 >1ms T45

ISL62884 to KBC GPO14

1.5CPU_1.05VTT_PWRGD

Delay 10ms T46 >5ms

KBC GPIO47 to PCH

PM_PWROK

3ms< T47 <20ms

+1.5V_RUN_CPU

T49 >100ns

T48 >1ms

A

PM_DRAM_PWRGD (for S3 Reduction)

H_PWRGD PLT_RST# PLTRST_DELAY# H_CPURST#

H_VTTPWRGD PM_PWROK +VCC_CORE

T50 >1ms T51 >1ms 0.05ms< T52 <650ms

T53 >1m s

KBC LRESET#

T54

KBC GPIO45

T55

5

4

3

2

(DC mode)

red word: KBC GPIO

+RTC_VCC T1
PCH_RTCRST# +PWR_SRC
T2 +3.3V_RTC_LDO
KBC_PWRBTN_EC#
+KBC_PWR S5_ENABLE +5V_ALW +3.3V_ALW +5VALW_PCH_VCC5REFSUS +15V_ALW 3V_5V_POK PM_PWRBTN# SUS_PWR_DN_ACK PCH_RSMRST# PCH_SUSCLK_KBC

Press Power button

KBC_PWRBTN_EC# GPIO3

T3 T4
T5

EC_ENABLE# (GPIO51) keep low KBC GPIO36 control

T6 +5V_ALW & +3.3V_ALW need meet 0.7V difference

T7 +5V_ALW & +3.3V_ALW need meet 0.7V difference

T8 T9

TPS51125 to KBC GPIO46

T10

KBC GPO84 to PCH

PCH to KBC GPI94 T11
KBC GPIO43 to PCH T12 >10ms
T13 PCH to KBC GPIO01

DC PCH_SUSCLK_KBC T14

PM_SLP_S4# PM_SLP_S3# PM_LAN_ENABLE +3.3V_LAN

T15 >30us
T16
T17

+1.5V_SUS

T18

+V_DDR_REF(0.9V)

T19

+5V_RUN

T20

+3.3V_RUN

T21

+5VS_PCH_VCC5REF

+1.5V_RUN

T23

+1.8V_RUN

T24

GFX_CORE_EN(Discrete only)

+VGA_CORE(Discrete only)

1.0V_RUN_VGA_EN(Discrete only)

+1.0V_RUN_VGA(Discrete only)

1.8V_VGA_RUN_EN(Discrete only)

+1.8V_RUN_VGA(Discrete only)

+3.3V_RUN_VGA_EN(Discrete only)-->DY reserved

+3.3V_RUN_VGA(Discrete only) -->Reserved for sequence

KBC GPO16 to LAN

+5V_RUN & +3.3V_RUN need meet 0.7V difference

T22 T26

H_PWRGD T25 >1ms
T27 T28
T29 T30
T31 T32 T33

KBC GPIO71 to RT8208B KBC GPIO30 to APL5930 KBC GPIO66 to APL5930 KBC GPI95

RUNPWROK +1.05V_VTT 1.5CPU_1.05VTT_PWRGD(after delay 1ms GPI96-VDDPWRGOOD_EC output for s3 reduction) +0.75V_DDR_VTT H_VTTPWRGD

T34

T35

T36

TPS51218 to KBC GPI34

T37

T38

+1.05V_VTT

T39

GFX_VR_EN(UMA only)

+CPU_GFX_CORE(UMA only)

T40

CPU to TPS51611

UMA GFX CORE Power

1.5CPU_1.05VTT_PWRGD
IMVP_VR_ON +VCC_CORE CLK_CPU_BCLK

T41 ( >99ms )

CK_PWRGD IMVP_PWRGD

PM_PWROK PM_DRAM_PWRGD (for S3 Reduction)

H_PWRGD PLT_RST# PLTRST_DELAY# H_CPURST#

T42 <3m s

KBC GPO53 to ISL62883

CPU CORE Power

CLKIN_BCLK(from CK505) stable 43 >1ms

1.5CPU_1.05VTT_PWRGD

T44 >1ms T46 >5ms

T45 Delay 10ms

+1.5V_RUN_CPU

3ms< T47 <20ms T49 >100ns

T48 >1ms

ISL62883 to CLOCKGEN ISL62884 to KBC GPO14
KBC GPIO47 to PCH

H_VTTPWRGD PM_PWROK +VCC_CORE

T50 >1ms T51 >1ms 0.05ms< T52 <650ms

T53 >1m s

KBC LRESET#

T54

KBC GPIO45

T55

3

2

1 D

C

B

A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Power Sequence

Size A1

Document Number
Berry

Date: Tuesday, October 20, 2009 1

Sheet 91

of

Rev
X00
92

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