Reference manual The i.MX 8QuadMax Applications Processor Reference Manual (IMX8QMRM) contains a comprehensive description of the structure and function (oper ation) of the QuadPlus SoC. Data sheet This data sheet includes electrical characteristics and signal connections.
MIMX8QP5AVUFFAB Datasheet PDF - NXP
NXP Semiconductors Data Sheet: Technical Data IMX8QPAEC Rev. 2, 05/2021 MIMX8QPnAVUxxAx i.MX 8QuadPlus Automotive and Infotainment Applications Processors Package Information 29 x 29 mm package case outline Ordering Information See Table 2 on page 5 1 Introduction The i.MX 8 Family consists of two processors: i.MX 8QuadMax and 8QuadPlus. This data sheet covers the i.MX 8QuadPlus processor, which is composed of seven cores (one Arm® Cortex®-A72, four Arm Cortex®-A53, and two Arm Cortex®-M4F), dual 32-bit GPU subsystems, 4K H.265 capable VPU, and dual failover-ready display controllers. This processor supports a single 4K display (with multiple display output options, including MIPI-DSI, HDMI, eDP/DP, and LVDS), or multiple smaller displays. Memory interfaces supporting LPDDR4, Quad SPI/Octal SPI (FlexSPI), eMMC 5.1, RAW NAND, SD 3.0, and a wide range of peripheral I/Os such as PCIe 3.0, provide wide flexibility. Advanced multicore audio processing is supported by the Arm cores and a high performance Tensilica® HiFi 4 DSP for pre- and post-audio processing as well as voice recognition. 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 System Controller Firmware (SCFW) Requirements5 1.3 Related resources . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 Special Signal Considerations. . . . . . . . . . . . . . . . 13 3.2 Recommended Connections for Unused Interfaces13 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 Power supplies requirements and restrictions. . . . 26 4.3 PLL electrical characteristics . . . . . . . . . . . . . . . . . 29 4.4 On-chip oscillators. . . . . . . . . . . . . . . . . . . . . . . . . 33 4.5 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 36 4.6 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 42 4.7 Output Buffer Impedance Parameters. . . . . . . . . . 45 4.8 System Modules Timing . . . . . . . . . . . . . . . . . . . . 49 4.9 General-Purpose Media Interface (GPMI) Timing . 53 4.10 External Peripheral Interface Parameters . . . . . . . 62 4.11 Analog-to-digital converter (ADC) . . . . . . . . . . . . 111 5 Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 115 5.1 Boot mode configuration inputs. . . . . . . . . . . . . . 115 5.2 Boot devices interfaces allocation . . . . . . . . . . . . 115 6 Package information and contact assignments . . . . . . 117 6.1 FCPBGA, 29 x 29 mm, 0.75 mm pitch . . . . . . . . 117 7 Release Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2018-2021 NXP B.V. Introduction The i.MX 8QuadPlus processor offers numerous advanced features as shown in this table. Table 1. i.MX 8QuadPlus advanced features Function Feature Multicore architecture provides 4× Cortex-A53, 1× Cortex-A72 cores, and 2× Cortex-M4F cores Graphics Processing Unit (GPU) Video Processing Unit (VPU) Tensilica HiFi 4 DSP for pre- and post-processing Memory AArch64 for 64-bit support and new architectural features AArch32 for full backward compatibility with ARMv7 Cortex-A72 and Cortex-A53 cores support ARM virtualization extensions. sMMU provides address virtualization to all subsystems. Cortex-M4F cores for real-time applications 16× Vec4 shaders with 64 execution units. Split GPU architecture allows for dual independent 8-Vec4 shader GPUs or a combined 16-Vec4 shader GPU. Supports OpenGL 3.0, 2.1,; OpenGL ES 3.2, 3.1 (with AEP), 3.0, 2.0, and 1.1; OpenCL 1.2 Full Profile and 1.1; OpenVG 1.1; and Vulkan High-performance 2D Blit Engine H.265 decode (4Kp60) H.264 decode (4Kp30) WMV9/VC-1 imple decode MPEG 1 and 2 decode AVS decode MPEG4.2 ASP, H.263, Sorenson Spark decode Divx 3.11 including GMC decode ON2/Google VP6/VP8 decode RealVideo 8/9/10 decode JPEG and MJPEG decode H.264 encode (1080p30) 666 MHz Fixed-point and vector-floating-point support 32 KB instruction cache, 48 KB data cache, 512 KB SRAM (448 KB of OCRAM and 64 KB of TCM) 64-bit LPDDR4 @1600 MHz 1× Quad SPI which can be used to connect to an FPGA 2× Quad SPI or 1× Octal SPI (FlexSPI) for fast boot from SPI NOR flash 2× SD 3.0 card interfaces 1× eMMC5.1/SD3.0 RAW NAND (62-bit ECC support via BCH-62 module) i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 2 NXP Semiconductors Function Display Controller Display I/O Camera I/O and video Security System Control Introduction Table 1. i.MX 8QuadPlus advanced features (continued) Feature Supports single UltraHD 4Kp60 display or up to 4 independent FullHD 1080p60 displays Up to 18-layer composition Complementary 2D blitting engines and online warping functionality Integrated Failover Path (SafeAssure) to ensure display content stays valid even in event of a software failure 2× MIPI-DSI with 4 lanes each 1× HDMI-TX/DisplayPort compliant with: · HDMI · eDP 1.4 · DP 1.3 This high performance serializer supports a pair of LVDS displays with 8 lanes each. Each port can be configured for 2x Tx with 4 lanes each. 2× MIPI-CSI with 4-lanes each Advanced High Assurance Boot (AHAB) secure & encrypted boot Random Number Generator with a high-quality entropy source generator and Hash_DRBG (based on hash functions) RSA up to 4096, Elliptic Curve up to 1023 AES-128/192/256, DES, 3DES, MD5, SHA-1, SHA-224/256/384/512 Dedicated Security Controller for Flashless SHE and HSM support, Trustzone Built-in ECDSA/DSA protocol support See the security reference manual for this chip for a full list of security features. · 2× I2C tightly coupled with Cortex-M4 cores (1× per Cortex M4F core) · The tightly coupled M4 I2C ports cannot be used for general-purpose use · System Control Unit (SCU): · Power control, clocks, reset · Boot ROMs · PMIC interface · Resource Domain Controller i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 3 Introduction Function I/O Packaging Table 1. i.MX 8QuadPlus advanced features (continued) Feature 1× PCIe 3.0 (2-lanes). Can be used as two PCIe 3.0 controllers with one-lane, independent operation. PCIe 1.0 and 2.0 compliant. PCIe 3.0 capable, contact your NXP representative. 1× USB 3.0 with PHY 2× USB 2.0 (1 with PHY, 1 with HSIC) 1× SATA 3.0 can be used as PCIe one-lane. This is in addition to the standard PCIe controller. PCIe 1.0 and 2.0 compliant. PCIe 3.0 capable, contact your NXP representative. 2× 1Gb Ethernet with AVB (can be used as 10/100 Mbps ENET with AVB) 3× CAN/CAN-FD 8× UARTs: · 5× UARTs (2× with hardware flow control) · 2× UARTs tightly coupled with Cortex-M4F cores (1× per Cortex-M4F core) · 1× UART tightly coupled with SCU 18× I2C: · 5× General-Purpose I2C (full-speed with DMA support) · Low-speed I2C without DMA support: · 2× master I2C in MIPI-DSI (1× per instance) · 4× master I2C in LVDS (2× per instance) · 2× master I2C in HDMI-TX · 2× master I2C in MIPI-CSI (1× per instance) Note: Although low-speed I2Cs can be made available for general purpose use which requires the associated PHY (for example, MIPI) to be powered on, it is not recommended. Note: I/O muxing constraints prevent using all I2Cs simultaneously. · 2x I2C tightly coupled with Cortex-M4 cores (1x per Cortex M4F core) Note: The tightly coupled M4 I2C ports cannot be used for general purpose use. · 1× I2C tightly coupled with SCU for communication with the PMIC. Not general purpose and not available for non-PMIC uses. 4× SAI (SAI0 and SAI1 are transmit/receive; SAI2 and SAI3 are receive only) 2× Enhanced Serial Audio Interface (ESAI) × ASRC (Asynchronous Sample Rate Converter) (note: no I/O signals are directly connected to this module) 1× SPDIF (Tx and Rx) 2× 4-channel ADC converters 3.3 V/1.8 V GPIO 4× PWM channels 1× 6×8 KPP (Key Pad Port) 1× MQS (Medium Quality Sound) 4× SPI Case FCPBGA 29 x 29 mm, 0.75 mm pitch i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 4 NXP Semiconductors 1.1 Ordering Information The following table provides the ordering information. Architectural Overview Table 2. i.MX 8QuadPlus Orderable part numbers Part Number MIMX8QP5AVUFFAB MIMX8QP6AVUFFAB Options Cortex-A72 Cortex-A53 Cortex-M4F GPU Qualification Tier Package 1 x VPU 1 x VPU 1 x DSP One @ 1.6 GHz Four @ 1.2 GHz Two @ 264 MHz Two @ Automotive 625 MHz AEC-Q100 29 mm × 29 mm 0.75 mm pitch FCPBGA (lidded) 1.2 System Controller Firmware (SCFW) Requirements The i.MX 8 and 8X families require a minimum SCFW release version for correct operation and to prevent potential reliability issues. The SCFW is released as part of a Board Support Package (e.g. Linux, Android) which may vary in version number for a specific BSP. For example, 5.4.70_2.3.0 GA contains SCFW version 1.7.1. Whereas 5.10.0_1.0.0 GA contains SCFW version 1.8.0. The released SCFW version associated within each BSP is the minimum version required to correctly support the wider BSP functionality. Customers should always check that they are using the specific SCFW binary delivered within their chosen BSP release. Customers should not mix newer BSP versions with older revisions of the SCFW. 1.3 Related resources Table 3. Related resources Type Reference manual Data sheet Chip Errata Package drawing Hardware guide Description The i.MX 8QuadMax Applications Processor Reference Manual (IMX8QMRM) contains a comprehensive description of the structure and function (operation) of the QuadPlus SoC. This data sheet includes electrical characteristics and signal connections. The chip mask set errata provides additional and/or corrective information for a particular device mask set. Package dimensions are provided in Section 6, "Package information and contact assignments"." The i.MX 8QuadMax/8QuadPlus Hardware Developer's Guide (IMX8HWDG) provides system design guidelines. 2 Architectural Overview The following subsections provide an architectural overview of the i.MX 8QuadPlus processor system. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 5 Architectural Overview 2.1 Block Diagram The following figure shows the functional modules in the processor system. 1x UART (each) 1x I2C (each) 1x GPIO (each) 2x User CM4 Complexes M4 Platform M4 CPU nvic fpu mpu MMCAU MCM 16KB code$ 16KB system$ 256KB TCM w/ ECC LPIT LPUART INTs LPI2C WDOG RGPIO PWM 2x MU CPU1 Platform 4x ARM Cortex-A53 NEON VFP 32KB I$ 32KB D$ 1MB L2 w/ ECC CPU2 Platform 1x ARM Cortex-A72 NEON VFP 48KB I$ 32KB D$ 1MB L2 w/ optional ECC Cache Coherent Interconnect (CCI-400) I2C w/ DMA UART (5 Mb/s) CAN / CAN-FD ADC (4 channels each) SPDIF TX / RX ESAI TX / RX 2x SAI TX / RX 2x SAI RX RAW / ONFI 3.2 NAND Flash 1x eMMC 5.1 / SD 3.0 2x SD 3.0 (UHS-I) 1x USB 3.0 PHY 1x USB 2.0 Host / HSIC 1x USB 2.0 OTG, PHY 10/100/1000M Ethernet + AVB 24M and 32k XTALOSC Sources 2x ADC DMA Subsystem 2x eDMA 5x LPUART 2x EVM SIM 3x FlexCAN 4x LPSPI 5x LPI2C 2x FTM 2x ASRC 2x ESAI 8x SAI Audio Subsystem SPDIF HDMI TX SAI MQS 6x GPT Audio Mixer ACM 2x eDMA Connectivity Subsystem NAND 3x uSDHC USB3 2x USB2 2x ENET VPU Subsystem Video Processing Unit VPU DSP Core HIFI4 DSP 32KB I$ 48KB D$ 448KB OCRAM 64KB TCM System Control Unit SCU CM4 Complex M4 Platform M4 CPU nvic fpu mpu MMCAU MCM 16KB code$ 16KB system$ 256KB TCM w/ ECC LPIT LPUART INTs LPI2C WDOG RGPIO PWM 2x MU SJC Debug DAP, CTI, etc Boot ROM HAB PMIC I/F IOMUX Clock, Reset Power Mgmt RDC Tempmon Security SNVS SECO OTP ADM CAAM Security Controller (M0+) External Memory Interface PG PG BN PG PG DDR Controller SSI Bus High Speed I/O 2x PCIe SATA Imaging MJPEG MJPEG ISI DEC ENC 2x LVDS TX LPI2C Display Controllers 2x DPU (4x LCD) Graphics Processing Unit 2x GPU Internal Memory OCRAM (256KB) LPI2C 2x MIPI CSI2 LPI2C 2x MIPI DSI LPI2C LPI2C HDMI PHY PHY 64-bit LPDDR4 @1600 MHz x1 PCIe 2 lanes / x2 PCIe 1 lane each 1x SATA 3.0 / 1x PCIe (1 lane) 1/2 LVDS TX (4 lanes each) 1x I2C 1x I2C 2x MIPI CSI2 (4-lanes) 1x I2C MIPI Display (4-lanes) 1x I2C 1x I2C HDMI Tx 2.0a (eDP 1.4 DisplayPort 1.3) Low Speed I/O (LSIO) Subsystem IEE 14x MU 2x FlexSPI 4x PWM 5x GPT KPP 8x GPIO 6x8 Keypad 32-bit GPIO 2x Quad SPI / 1x Octal SPI NOR Flash 1x UART 1x I2C 1x GPIO Dedicated RNG Tamper Detection Secure RTC Secure JTAG Ciphers (ECC, RSA) 64k Secure RAM Mult-format Decode H.265 Dec (4k60) H.264 Dec (1080p60) H.264 Enc (1080p30) Dual Core, 16 shaders Vulkan, OGLES 3.2 w/ AEP, OCL 2.0, VG 1.1 2D Blit Engine Figure 1. i.MX 8QuadPlus System Block Diagram i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 6 NXP Semiconductors Modules List 3 Modules List The i.MX 8QuadPlus processors contain a variety of digital and analog modules. This table describes the processor modules in alphabetical order. Table 4. i.MX 8QuadPlus modules list Block Mnemonic ADC APBH-DMA A53 A72 ASRC BCH-62 CAAM CTI CTM DAP DC DDR Controller Block Name Brief Description Analog-to-Digital Converter The analog-to-digital converter (ADC) is a successive approximation ADC designed for operation within a SoC. NAND Flash and BCH ECC DMA Controller The AHB-to-APBH bridge provides the chip with a peripheral attachment bus running on the AHB's HCLK, which includes the AHB-to-APB PIO bridge for a memory-mapped I/O to the APB devices, as well as a central DMA facility for devices on this bus and a vectored interrupt controller for the Arm core. Arm (CPU1) CPU cluster embedding 4x Cortex-A53 CPUs with a 32KB L1 instruction cache and a 32KB data cache. The CPUs share a 1 MB L2 cache. Arm (CPU2) CPU cluster embedding 1x Cortex-A72 CPU with a 48 KB L1 instruction cache and 32 KB data cache. The CPU has a 1MB L2 cache. Asynchronous Sample Rate Converter The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of a signal associated to an input clock into a signal associated to a different output clock. The ASRC supports concurrent sample rate conversion of up to 10 channels of about -120dB THD+N. The sample rate conversion of each channel is associated to a pair of incoming and outgoing sampling rates. The ASRC supports up to three sampling rate pairs. Binary-BCH ECC Processor The BCH62 module provides up to 62-bit ECC for NAND Flash controller (GPMI2) Cryptographic Accelerator and Assurance Module CAAM is a cryptographic accelerator and assurance module. CAAM implements several encryption and hashing functions, a run-time integrity checker, and a Pseudo Random Number Generator (PRNG). CAAM also implements a Secure Memory mechanism. In this device the security memory provided is 64 KB. Cross Trigger Interface CTI sends signals across the chip indicating that debug events have occurred. It is used by features of the Coresight infrastructure. Cross Trigger Matrix Cross Trigger Matrix IP is used to route triggering events between CTIs. Debug Access Port The DAP provides real-time access for the debugger without halting the core to: · System memory and peripheral registers · All debug configuration registers The DAP also provides debugger access to JTAG scan chains. Display Controller Dual display controller DRAM Controller · Memory types: LPDDR4 · Two channels of 32-bit memory: · LPDDR4 up to 1.6 GHz i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 7 Modules List Block Mnemonic DPR eDMA ENET ESAI FTM FlexCAN Table 4. i.MX 8QuadPlus modules list (continued) Block Name Brief Description Display/Prefetch/ Resolve The DPR prefetches data from memory and converts the data to raster format for display output. Raster source buffers can also be prefetched unconverted. The resolve process supports graphics and video formatted tile frame buffers and converts them to raster format. Embedded display memory is used as temporary storage for data which is sourced by the display controller to drive the display. Enhanced Direct Memory Access · 4× eDMA with a total of 128 channels (note: all channels are not assigned; see the product reference manual for more information): · 4× instances with 32 channels each · Programmable source, destination addresses, transfer size, plus support for enhanced addressing modes · Internal data buffer, used as temporary storage to support 64-byte burst transfers, one outstanding transaction per DMA controller. · Transfer control descriptor organized to support two-deep, nested transfer operations · Channel service request via one of three methods: · Explicit software initiation · Initiation via a channel-to-channel linking mechanism for continuous transfers · Peripheral-paced hardware requests (one per channel) · Support for fixed-priority and round-robin channel arbitration · Channel completion reported via interrupt requests · Support for scatter/gather DMA processing · Support for complex data structures via transfer descriptors · Support to cancel transfers via software or hardware · Each eDMA instance can be uniquely assigned to a different resource domain, security (TZ) state, and virtual machine · In scatter-gather mode, each transfer descriptor's buffers can be assigned to different SMMU translation Ethernet Controller 2× 1 Gbps Ethernet controllers supporting RGMII + AVB (Audio Video Bridging, IEEE 802.1Qav) Enhanced Serial Audio Interface The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port for serial communication with a variety of serial devices, including industry-standard codecs, SPDIF transceivers, and other processors. The ESAI consists of independent transmitter and receiver sections, each section with its own clock generator. All serial transfers are synchronized to a clock. Additional synchronization signals are used to delineate the word frames. The normal mode of operation is used to transfer data at a periodic rate, one word per period. The network mode is also intended for periodic transfers; however, it supports up to 32 words (time slots) per period. This mode can be used to build time division multiplexed (TDM) networks. In contrast, the on-demand mode is intended for non-periodic transfers of data and to transfer data serially at high speed when the data becomes available. The ESAI has 12 pins for data and clocking connection to external devices. FlexTimer Provides input signal capture and PWM support Flexible Controller Area Communication controller implementing the CAN with Flexible Data rate (CAN FD) Network protocol and the CAN protocol according to the CAN 2.0B protocol specification. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 8 NXP Semiconductors Block Mnemonic FlexSpi (Quad SPI/Octal SPI) GIC GPIO GPMI GPT GPU HDMI Tx/ DP/eDP HiFi 4 DSP I2C IEE Table 4. i.MX 8QuadPlus modules list (continued) Modules List Block Name Brief Description Flexible Serial Peripheral Interface · Flexible sequence engine to support various flash vendor devices, including HyperBusTM devices: · Support for FPGA interface · Single, dual, quad, and octal mode of operation. · DDR/DTR mode wherein the data is generated on every edge of the serial flash clock. · Support for flash data strobe signal for data sampling in DDR and SDR mode. · Two identical serial flash devices can be connected and accessed in parallel for data read operations, forming one (virtual) flash memory with doubled readout bandwidth. Generic Interrupt Controller The GIC-500 handles all interrupts from the various subsystems and is ready for virtualization. General Purpose I/O Modules Used for general purpose input/output to external devices. Each GPIO module supports 32 bits of I/O. General Purpose Media The GPMI module supports up to 8× NAND devices. 62-bit ECC (BCH) Interface encryption/decryption for NAND Flash controller (GPMI). The GPMI supports separate DMA channels per NAND device. General Purpose Timer Each GPT is a 32-bit "free-running" or "set and forget" mode timer with programmable prescaler and compare and capture register. A timer counter value can be captured using an external event and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse. When the timer is configured to operate in "set and forget" mode, it is capable of providing precise interrupts at regular intervals with minimal processor intervention. The counter has output compare logic to provide the status and interrupt at comparison. This timer can be configured to run either on an external clock or on an internal clock. Graphics Processing 2× GC7000XSVX GPUs with 8 shaders each that can run either independently or in "dual-mode" with 16 shaders. HDMI Tx interface HDMI transmitter, Display Port 1.3 and embedded Display Port 1.4 Audio Processor I2C Interface A highly optimized audio processor geared for efficient execution of audio and voice codecs and pre- and post-processing modules to offload the Arm core. I2C provides serial interface for external devices. · Supports direct encryption and decryption of FlexSPI memory type · Provides decryption services (lower performance) for DRAM traffic · Supports I/O direct encrypted storage and retrieval · Support for a number of cryptographic standards: · 128/256-bit AES Encryption (AES-CTR, AES-XTS mode options) · Multiple keys supported: · Loaded via secure key channel from security block · Key selection is per access and based on source of transaction IOMUXC JPEG/dec IOMUX Control MJPEG engine for decode This module enables flexible I/O multiplexing. Each I/O pad has default and several alternate functions. The alternate functions are software configurable. Provides up to 4-stream decoding in parallel. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 9 Modules List Block Mnemonic JPEG/enc KPP LPIT-1 LPIT-2 LPSPI 03 LVDS M4F MIPI CSI-2 MIPI-DSI MQS OCOTP_CTRL Table 4. i.MX 8QuadPlus modules list (continued) Block Name Brief Description MJPEG engine for encode Provides up to 4-stream encoding in parallel. Key Pad Port The Keypad Port (KPP) is a 16-bit peripheral that can be used as a 6 x 8 keypad matrix interface or as general purpose input/output (I/O). Low-Power Periodic Interrupt Timer Each LPIT is a 32-bit "set and forget" timer that starts counting after the LPIT is enabled by software. It is capable of providing precise interrupts at regular intervals with minimal processor intervention. It has a 12-bit prescaler for division of input clock frequency to get the required time setting for the interrupts to occur, and counter value can be programmed on the fly. Configurable SPI Full-duplex enhanced Synchronous Serial Interface. It is configurable to support Master/Slave modes, four chip selects to support multiple peripherals. LVDS Display Bridge This high performance serializer supports a pair of LVDS displays with 8 lanes each. Each port can be configured for 2x Tx with 4 lanes each. Arm (CPU3) · Cortex-M4F core · AHB LMEM (Local Memory Controller) including controllers for TCM and cache memories · 256 KB embedded tightly coupled memory(TCM) (128 KB TCMU, 128 KB TCML) · 16 KB Code Bus Cache · 16 KB System Bus Cache · ECC for TCM memories and parity for code and system caches · Integrated Nested Vector Interrupt Controller (NVIC) · Wakeup Interrupt Controller (WIC) · FPU (Floating Point Unit) · Core MPU (Memory Protection Unit) · Support for exclusive access on the system bus · MMCAU (Crypto Acceleration Unit) · MCM (Miscellaneous Control Module) MIPI CSI-2 Interface The MIPI CSI-2 IP provides MIPI CSI-2 standard camera interface ports. The MIPI CSI-2 interface supports up to 1.5 Gbps for up to 4 data lanes MIPI DSI interface The MIPI DSI IP provides DSI standard display serial interface. The DSI interface supports 80 Mbps to 1.5 Gbps speed per data lane. Medium Quality Sound Medium Quality Sound (MQS) is used to generate 2-channel medium quality PWM-like audio via two standard digital GPIO pins. OTP Controller The On-Chip OTP controller (OCOTP_CTRL) provides an interface for reading, programming, and/or overriding identification and control information stored in on-chip fuse elements. The module supports electrically-programmable poly fuses (eFUSEs). The OCOTP_CTRL also provides a set of volatile software-accessible signals that can be used for software control of hardware elements, not requiring non-volatility. The OCOTP_CTRL provides the primary user-visible mechanism for interfacing with on-chip fuse elements. Among the uses for the fuses are unique chip identifiers, mask revision numbers, cryptographic keys, JTAG secure mode, boot characteristics, and various control signals requiring permanent nonvolatility. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 10 NXP Semiconductors Block Mnemonic OCRAM PCIe PRG PWM RAM 64 KB Secure RAM RAM 256 KB RNG SAI SECO SJC sMMU SNVS SPDIF Table 4. i.MX 8QuadPlus modules list (continued) Modules List Block Name Brief Description On-Chip Memory Controller The On-Chip Memory controller (OCRAM) module is designed as an interface between the system's AXI bus and the internal (on-chip) SRAM memory module. The OCRAM is used for controlling the 256 KB multimedia RAM through a 64-bit AXI bus. PCI Express 3.0 PCIe 1.0 and 2.0 compliant. PCIe 3.0 capable; contact your NXP representative. Prefetch/Resolve Gasket The PRG is a gasket which translates system memory accesses to local display RTRAM accesses for display refresh. It works with the DPR to complete the prefetch and resolving operations needed to drive the display. Pulse Width Modulation The pulse-width modulator (PWM) has a 16-bit counter and is optimized to generate sound from stored sample audio images and it can also generate tones. It uses 16-bit resolution and a 4×16 data FIFO to generate square waveforms. Secure/non-secure RAM Secure/non-secure Internal RAM, interfaced through the CAAM. Internal RAM Internal RAM, which is accessed through OCRAM memory controllers. Random Number Generator The purpose of the RNG is to generate cryptographically strong random data. It uses a true random number generator (TRNG) and a pseudo-random number generator (PRNG) to achieve true randomness and cryptographic strength. The RNG generates random numbers for secret keys, per message secrets, random challenges, and other similar quantities used in cryptographic algorithms. I2S/SSI/AC97 Interface The SAI module provides a synchronous audio interface that supports full duplex serial interfaces with frame synchronization, such as I2S, AC97, TDM, and codec/DSP interfaces. Security Controller Core and associated memory and hardware responsible for key management. Secure JTAG Controller The SJC provides the JTAG interface, which is compatible with JTAG TAP standards, to internal logic. This device uses JTAG port for production, testing, and system debugging. Additionally, the SJC provides BSR (Boundary Scan Register) standard support, which is compatible with IEEE1149.1 and IEEE1149.6 standards. The JTAG port must be accessible during platform initial laboratory bring-up, for manufacturing tests and troubleshooting, as well as for software debugging by authorized entities. The SJC incorporates three security modes for protecting against unauthorized accesses. Modes are selected through eFUSE configuration. System MMU The System MMU is an MMU-500 from Arm. It supports two-stage address translation and multiple translation contexts. Secure Non-Volatile Storage Secure Non-Volatile Storage, including Secure Real Time Clock, Security State Machine, Master Key Control. Sony Philips Digital Interconnect Format The Sony/Philips Digital Interface (SPDIF) audio block is a stereo transceiver that allows the processor to receive and transmit digital audio. The SPDIF transceiver allows the handling of both SPDIF channel status (CS) and User (U) data and includes a frequency measurement block that allows the precise measurement of an incoming sampling frequency. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 11 Modules List Block Mnemonic TEMPMON UART USB3/USB2 USBOH Table 4. i.MX 8QuadPlus modules list (continued) Block Name Temperature Monitor UART Interface Brief Description The temperature monitor/sensor IP module for detecting high temperature conditions. The temperature read out does not reflect case or ambient temperature. It reflects the temperature in proximity of the sensor location on the die. Temperature distribution may not be uniformly distributed; therefore, the read-out value may not be the reflection of the temperature value for the entire die. · High-speed TIA/EIA-232-F compatible, up to 5.0 Mbps · Serial IR interface low-speed, IrDA-compatible (up to 115.2 Kbit/s) · 9-bit or Multidrop mode (RS-485) support (automatic slave address detection) · 7, 8, 9, or 10-bit data characters (7-bits only with parity) · 1 or 2 stop bits · Programmable parity (even, odd, and no parity) · Hardware flow control support for request to send (RTS_B) and clear to send (CTS_B) signals The USB3/USB2 OTG module has been specified to perform USB 3.0 dual role and USB 2.0 On-The-Go (OTG) compatible with the USB 3.0, and USB 2.0 specification with OTG supplementary specifications. This controller supports twoindependent USB cores (1× USB3.0 dual-role, 1× USB2.0 OTG) and includes the PHY and I/O interfaces to support this operation. The full pinout of the USB 3.0 controller includes the signaling for both USB 3.0 and USB 2.0. This does not mean there is a separate USB 2.0 controller that can be used independently and simultaneously with USB 3.0. This device has an additional separate, independent USB 2.0 OTG controller which can be used simultaneously with this USB 3.0. Specific features requested for this updated module: · Super Speed (5 Gbps), High Speed (480 Mbps), full speed (12 Mbps) and low speed (1.5 Mbps) · Fully compatible with the USB 3.0 specification (backward compatible with USB 2.0) · Fully compatible with the USB On-The-Go supplement to the USB 2.0 specification · Hardware support for OTG signaling · Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) implemented in hardware, which can also be controlled by software The USBOH module has been specified which performs USB 2.0 On-The-Go (OTG) and USB 2.0 Host functionality compatible with the USB 2.0 with OTG supplement and HS IC-USB specification. This controller supports two independent USB cores (1× USB2.0 OTG, 1× USB2.0 Host) and includes the PHY and I/O interfaces to support this operation. Key features: · One USB2.0 OTG controller · High Speed (480 Mbps), full speed (12 Mbps) and low speed (1.5 Mbps) · Fully compatible with the USB 2.0 specification · Fully compatible with the USB On-The-Go supplement to the USB 2.0 specification · Hardware support for OTG signaling · Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) implemented in hardware, which can also be controlled by software · USB2.0 Host with HS IC-USB specification · HS IC-USB transceiver-less downstream support (Host only). i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 12 NXP Semiconductors Modules List Table 4. i.MX 8QuadPlus modules list (continued) Block Mnemonic uSDHC VPU WDOG XTAL OSC24M XTAL OSC32K Block Name Brief Description SD/eMMC and SDXC Enhanced Multi-Media Card / Secure Digital Host Controller i.MX 8 Family SoC-specific characteristics: All three MMC/SD/SDIO controller IPs are identical and are based on the uSDHC IP. The uSDHC is a host controller used to communicate with external low cost data storage and communication media. It supports the previous versions of the MultiMediaCard (MMC) and Secure Digital Card (SD) standards. Specifically, the uSDHC supports: · SD Host Controller Standard Specification v3.0 with the exception that all the registers do not match the standards address mapping. · SD Physical Layer Specification v3.0 UHS-I (SDR104/DDR50) · SDIO specification v3.0 · eMMC System Specification v5.1 Video Processing Unit See the device reference manual for the complete list of the VPU's decoding/encoding capabilities. Watchdog The Watchdog Timer supports two comparison points during each counting period. Each of the comparison points is configurable to evoke an interrupt to the Arm core, and a second point evokes an external event on the WDOG line. The 24 MHz clock source is an external crystal that acts as the main system clock. The OSC24M is used as the source clock for subsystem PLLs. OSC24M can be turned off by the System Control Unit (SCU) during sleep mode. The 32.768 kHz clock source is an external crystal. The OSC32K is intended to be always on and is distributed by the SCU to modules in the chip. 3.1 Special Signal Considerations Special signal considerations can be found in the Hardware Developer's Guide for this device in the Design Checklist section. 3.2 Recommended Connections for Unused Interfaces The recommended connections for unused analog interfaces can be found in the section, "Unused Input/Output Terminations," in the Hardware Developer's Guide for this device. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 13 Electrical characteristics 4 Electrical characteristics This section provides the device and module-level electrical characteristics for these processors. 4.1 Chip-level conditions This section provides the device-level electrical characteristics for the SoC. See the following table for a quick reference to the individual tables and sections. Table 5. Chip-level conditions For these characteristics, ... Absolute maximum ratings FCPBGA package thermal resistance data Operating ranges External Input Clock Frequency Maximum supply currents Standby use cases USB 2.0 PHY typical current consumption in Power-Down Mode USB 3.0 PHY typical current consumption in Power-Down Mode Typical current consumption in Power-Down mode for USB 2.0 PHY embedded in USB 3.0 PHY Topic appears ... on page 15 on page 17 on page 17 on page 21 on page 21 on page 48 on page 25 on page 25 on page 25 4.1.1 Absolute Maximum Ratings CAUTION Stresses beyond those listed under Table 6 may affect reliability or cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated in the "Operating ranges" or other parameter tables is not implied. Exposure to absolute-maximum-rated conditions for extended periods will affect device reliability. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 14 NXP Semiconductors Parameter Description Core Supplies Input Voltage DDR PHY supplies 1.0V IO supplies IO Supply for GPIO Type 1.8V IO Single supply IO Supply for GPIO Type 1.8 / 2.5 / 3.3V IO Tri-voltage Supply Table 6. Absolute maximum ratings Symbol Min VDD_A72 -0.3 VDD_A53 VDD_GPU0 VDD_GPU1 VDD_MAIN VDD_MEMC VDD_DDR_VDDQ -0.3 VDD_MIPI_1P0 -0.3 VDD_USB_OTG_1P0 VDD_ADC_1P8 -0.5 VDD_ADC_DIG_1P8 VDD_ANA0_1P8 (IO, analog,OSC SCU) VDD_ANA1_1P8 (IO, analog,OSC SCU) VDD_DDR_PLL_1P8 (memory PLLs) VDD_MIPI_1P8 (PHY, GPIO) VDD_MIPI_CSI_DIG_1P8 (PHY, GPIO) VDD_PCIE_1P8 (PHY) VDD_USB_1P8 (PHY, GPIO) VDD_ENET1_1P8_2P5_3P3 -0.3 VDD_ENET0_1P8_3P3 Electrical characteristics Max Units 1.2 V 1.75 V 1.2 V 2.1 V 3.8 V i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 15 Electrical characteristics Table 6. Absolute maximum ratings (continued) Parameter Description Symbol IO Supply for GPIO Type 1.8 / 3.3V IO Dual Voltage Supply VDD_CAN_UART_1P8_3P3 VDD_CSI_1P8_3P3 VDD_EMMC0_1P8_3P3 VDD_EMMC0_VSELECT_1P8_3P3 VDD_ENET_MDIO_1P8_3P3 VDD_MIPI_DSI_DIG_1P8_3P3 VDD_PCIE_DIG_1P8_3P3 VDD_QSPI0A_1P8_3P3 VDD_QSPI0B_1P8_3P3 VDD_SPI_MCLK_UART_1P8_3P3 VDD_SPI_SAI_1P8_3P3 VDD_TMPR_CSI_1P8_3P3 VDD_USB_3P3 (PHY & GPIO) VDD_USDHC1_1P8_3P3 VDD_USDHC1_VSELECT_1P8_3P3 SNVS Coin Cell VDD_SNVS_4P2 USB VBUS (OTG2) USB_OTG2_VBUS USB VBUS (OTG1) USB_OTG1_VBUS I/O Voltage for USB Drivers USB_OTG1_DP/USB_OTG1_DN USB_OTG2_DP/USB_OTG2_DN I/O Voltage for ADC ADC_INx Vin/Vout input/output voltage range (GPIO Vin/Vout Type Pins) Vin/Vout input/output voltage range (DDR Vin/Vout pins) ESD immunity (HBM). Vesd_HBMX ESD immunity (CDM). Vesd_CDM Storage temperature range Tstorage Min Max -0.3 3.8 -0.3 4.3 -0.3 3.63 -0.3 5.5 -0.3 3.63 -0.1 2.1 See Section 4.6.1 See Section 4.6.1 -- 1000 -- 250 -40 150 NOTE HDMI CEC is 3.3V tolerant. HDMI DDC signals and HPD are 5V tolerant. Refer to the Hardware Developer's Guide for proper terminations. Units V V V V V V V V V V °C i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 16 NXP Semiconductors 4.1.2 Thermal resistance 4.1.2.1 FCPBGA package thermal resistance This table provides the FCPBGA package thermal resistance data. Electrical characteristics Table 7. FCPBGA package thermal resistance data Rating Board Type1 Symbol 29x29 mm package Unit Junction to Ambient Thermal Resistance2 JESD51-9, 2s2p RJA 12.9 °C/W Junction to Package Top Thermal Resistance2 JESD51-9, 2s2p JT 0.1 °C/W Junction to Case Thermal Resistance3 JESD51-9, 1s RJC 0.3 °C/W 1 Thermal test board meets JEDEC specification for this package (JESD51-9). 2 Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is solely for a thermal performance comparison of one package to another in a standardized specified environment. It is not meant to predict the performance of a package in an application-specific environment. 3 Junction-to-Case thermal resistance determined using an isothermal cold plate. Case temperature refers to the mold surface temperature at the package top side dead center. 4.1.3 Operating Ranges The following table provides the operating ranges of these processors. VDD_A722 Symbol VDD_A532 VDD_GPU0 VDD_GPU1 VDD_MEMC Table 8. Operating ranges1 Description Mode Min Typ Max Unit Comments Power supply Overdrive 1.05 1.10 1.15 V Min frequency = 208.5 MHz of Cortex-A72 Max frequency = 1.6 GHz cluster Nominal 0.95 1.00 1.10 V Max frequency = 1.06 GHz Power supply Overdrive 1.05 1.10 1.15 V Min frequency = 208.5 MHz of Cortex-A53 Max frequency = 1.2 GHz cluster Nominal 0.95 1.00 1.10 V Max frequency = 900 MHz Power supply of first GPU instance Nominal 0.95 1.00 1.10 V Max frequencies: Shaders = 625 MHz; Core = 625 MHz Power supply of second GPU instance Nominal 0.95 1.00 1.10 V Max frequencies.: Shaders = 625 MHz; Core = 625 MHz Power supply of memory controller N/A 1.05 1.10 1.15 V -- i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 17 Electrical characteristics Table 8. Operating ranges1 (continued) Symbol VDD_MAIN3 Description Power supply of remaining core logic VDD_DDR_CH0_VDDQ, VDD_DDR_CH0_VDDQ_CKE, VDD_DDR_CH1_VDDQ, VDD_DDR_CH1_VDDQ_CKE, Power supplies of memory I/Os VDD_DDR_CH0_VDDA_PLL_1P8, VDD_DDR_CH1_VDDA_PLL_1P8 Power supplies of memory PLLs VDD_MIPI_CSI0_1P0, VDD_MIPI_CSI1_1P0, VDD_MIPI_DSI0_1P0, VDD_MIPI_DSI0_PLL_1P0, VDD_MIPI_DSI1_1P0, VDD_MIPI_DSI1_PLL_1P0, VDD_LVDS0_1P0, VDD_LVDS1_1P0 Power supplies of PHYs (1.0 V part) VDD_ANA1_1P8, VDD_ANA2_1P8, VDD_ANA3_1P8, VDD_CP_1P8, VDD_SCU_1P8, VDD_SCU_ANA_1P8, VDD_SCU_XTAL_1P8 Power supplies of I/Os, analog and oscillator of the SCU VDD_PCIE_IOB_1P8, VDD_ADC_1P8, VDD_ADC_DIG_1P8, VDD_HDMI_RX0_1P84, VDD_HDMI_TX0_1P8, VDD_LVDS0_1P8, VDD_LVDS1_1P8, VDD_MIPI_CSI0_1P8, VDD_MIPI_CSI1_1P8, VDD_MIPI_DSI0_1P8, VDD_MIPI_DSI1_1P8, VDD_MLB_1P85, VDD_PCIE_LDO_1P8, VDD_PCIE_SATA0_PLL_1P84, VDD_PCIE0_PLL_1P8, VDD_PCIE1_PLL_1P8, VDD_USB_HSIC0_1P8, VDD_ANA0_1P8, VDD_MIPI_CSI_DIG_1P8 Power supplies of PHYs (1.8 V part) and GPIO operating at 1.8 V only. Mode Min Typ Max Unit Comments N/A 0.95 1.00 1.10 V Max frequencies: HiFi4 DSP = 666 MHz M4 = 264 MHz VPU = 600 MHz LPDDR4 1.06 1.10 1.17 V Max frequency = 1.6 GHz Supports LPDDR4-3200 N/A 1.65 1.80 1.95 V PLL supply can be merged with other 1.8V supplies with proper on board decoupling. N/A 0.95 1.00 1.10 V These balls shall be connected to the same power supply as VDD_MAIN. It shall be a star connection from the power supply. Each VDD power supply ball shall have its own dedicated decoupling caps. N/A 1.65 1.70 1.75 V These balls shall be powered by a dedicated supply. Note: The disconnect between the ball naming, implying a 1.8 V supply, and the actual required operating voltage of 1.7 V is known and correct as shown. N/A 1.65 1.80 1.95 V -- i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 18 NXP Semiconductors Electrical characteristics Table 8. Operating ranges1 (continued) Symbol Description VDD_HDMI_RX0_VH_RX_3P34, VDD_HDMI_TX0_DIG_3P3, VDD_USB_OTG1_3P3, VDD_USB_OTG2_3P3, VDD_USB_SS3_TC_3P3 Power supplies of PHYs (3.3 V part) and GPIO operating at 3.3 V only VDD_PCIE_DIG_1P8_3P3, Power VDD_ENET0_1P8_3P3, supplies of VDD_ENET_MDIO_1P8_3P3, GPIO VDD_EMMC0_1P8_3P3, supporting VDD_USDHC1_1P8_3P3, both 1.8 V or VDD_USDHC2_1P8_3P3, 3.3 V VDD_USDHC_VSELECT_1P8_3P3, VDD_SIM0_1P8_3P3, VDD_ESAI0_MCLK_1P8_3P3, VDD_ESAI1_SPDIF_SPI_1P8_3P3, VDD_FLEXCAN_1P8_3P3, VDD_LVDS_DIG_1P8_3P3, VDD_M4_GPT_UART_1P8_3P3, VDD_MIPI_DSI_DIG_1P8_3P3, VDD_MLB_DIG_1P8_3P36, VDD_QSPI0_1P8_3P3, VDD_QSPI1A_1P8_3P3, VDD_SPI_SAI_1P8_3P3 VDD_ENET1_1P8_2P5_3P3 Power supplies of ethernet I/Os VDD_USB_HSIC0_1P2 VDD_SNVS_4P2 Power supply of USB-HSIC I/Os Power supply of SNVS Mode N/A Min Typ Max Unit 3.00 3.30 3.60 V Comments -- 1.8 V 3.3 V 1.65 1.80 1.95 V When VDD_USDHC1_1P8_3P3 3.00 3.30 3.60 V or VDD_USDHC2_1P8_3P3 is used to support an SD card then it shall be on a dedicated 1.8V/3.3V regulator. When VDD_SIM0_1P8_3P3 is used to support a SIM card, it shall be on a dedicated 1.8V/3.3V regulator. VDDs of this list targeting 1.8V can share 1.8V regulator of 1.8V only VDDs VDDs of this list targeting 3.3V can share 3.3V regulator of 3.3V only VDDs 1.8 V 1.65 1.80 1.95 V -- 2.5 V 2.38 2.50 2.63 V -- 3.3 V 3.00 3.30 3.60 V -- N/A 1.1 1.2 1.3 V -- N/A 2.80 3.30 4.20 V It can be supplied by a backup battery: a coin cell or a super cap. Output of embedded LDOs and negative charge pump VDD_USB_SS3_LDO_1P0_CAP, 1.0 V output of N/A -- 1.00 -- V -- VDD_HDMI_RX0_LDO0_1P0_CAP4 embedded , LDOs VDD_HDMI_RX0_LDO1_1P0_CAP4 , VDD_HDMI_TX0_LDO_1P0_CAP, VDD_PCIE_LDO_1P0_CAP VDD_SNVS_LDO_1P8_CAP 1.8 V output of N/A -- 1.80 -- V -- SNVS embedded LDO i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 19 Electrical characteristics Table 8. Operating ranges1 (continued) Symbol Description Mode Min Typ Max Unit Comments VDD_M1P8 _CAP -1.8 V output N/A -- -1.80 -- V -- of embedded charge pump Power supplies that shall be connected to output of an embedded LDO VDD_HDMI_TX0_1P0 -- VDD_PCIE_SATA0_1P04, -- VDD_PCIE0_1P0, VDD_PCIE1_1P0 VDD_USB_OTG1_1P0, -- VDD_USB_OTG2_1P0 N/A -- 1.00 -- V Shall be externally connected to VDD_HDMI_TX0_LDO_1P0_CA P N/A -- 1.00 -- V Shall be externally connected to VDD_PCIE_LDO_1P0_CAP N/A -- 1.00 -- V Shall be externally connected to VDD_USB_SS3_LDO_1P0_CA P Junction temperature Junction temperature -- -- -40 125 °C -- 1 Voltage ranges are defined to group as many supplies as possible. Individual supplies may have a wider range than listed here. 2 These are the supported frequencies included in the Linux, Android, and all other operating systems using the SCU defined DVFS (Dynamic Voltage and Frequency Scaling) set points. An additional Overdrive set point is included to provide a more balanced power-versus-performance trade-off, where the A72 runs at 1.3 GHz and the A53 runs at 1.1 GHz. Likewise, an additional Nominal set point is included where both the A72 and A53 run at 600 MHz. 3 During low power state, this voltage can be dropped to 0.8 V +/- 3% for retention. 4 HDMI-RX is not currently supported, the related power and signal connections are provided for future use when it is expected HDMI-RX support will be enabled. 5 MLB is not supported on this product. This MLB power rail may be tied to the power supply voltage indicated or may be terminated, per the Hardware Developer's Guide power supplies of unused functions. 6 MLB is not supported on this product. The MLB power rail must be tied to the power supply voltage indicated if other I/O functions are used, as determined by IOMUX selection. Alternately, terminate the MLB supply per the Hardware Developer's Guide power supplies of unused functions. 4.1.4 External clock sources Each processor has two external input system clocks: a low frequency (RTC_XTALI) and a high frequency (XTALI). The RTC_XTALI is used for real time functions. It supplies the clock for real time clock operation and for slow-system and watchdog counters. The clock input can be connected to either an external oscillator or a crystal using the internal oscillator amplifier. The system clock input XTALI is used to generate the main system clock. It supplies the PLLs and other peripherals. The system clock input requires a crystal using the internal oscillator amplifier. The PCIe oscillator can be sourced internally or input to the chip. In both cases, it is a 100 MHz nominal clock using HCSL signaling to provide the PCIe reference clock. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 20 NXP Semiconductors The following table shows the interface frequency requirements. Electrical characteristics Table 9. External Input Clock Frequency Parameter Description Symbol Min Typ Max Unit RTC_XTALI Oscillator1,2 XTALI Oscillator4,2 PCIe oscillator5 fckil -- fxtal -- f100M -- 32.7683/32.0 24 100 -- kHz -- MHz -- MHz Frequency accuracy -- -- -- ±300 ppm 1 External oscillator or a crystal with internal oscillator amplifier. 2 The required frequency stability of this clock source is application dependent. For recommendations, see the hardware development guide for this device. 3 Recommended nominal frequency 32.768 kHz. 4 Fundamental frequency crystal with internal oscillator amplifier. 5 If using an external clock instead of the internal clock source, an HCSL-compatible clock is required. Concerning EMI/EMC, note that internal source is not spread-spectrum capable. The typical values shown in Table 9 are required for use with NXP board support packages (BSPs) to ensure precise time keeping and USB and HDMI operations. 4.1.5 Maximum Supply Currents NOTE Some of the numbers shown in this table are based on the companion regulator limits and not actual use cases. Current-drain application note AN13249 is also available for reference. This document contains measured results for i.MX 8QuadMax and should be used as a guideline for i.MX 8QuadPlus. Symbol VDD_A72 VDD_A53 VDD_GPU0 VDD_GPU1 VDD_MAIN VDD_MEMC VDD_DDR_CH0_VDDQ VDD_DDR_CH0_VDDQ_CKE VDD_DDR_CH0_VDDA_PLL_1P8 Table 10. Maximum supply currents Value Unit Comments 3500 2500 3500 3500 5000 3200 800 200 20 mA Value based on max current delivered by PMIC mA Value based on max current delivered by PMIC mA Value based on max current delivered by PMIC mA Value based on max current delivered by PMIC mA Value based on max current delivered by PMIC mA Value based on max current delivered by PMIC mA Does not include current used by external memory. mA Does not include current used by external memory. mA i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 21 Electrical characteristics Table 10. Maximum supply currents (continued) Symbol VDD_DDR_CH1_VDDQ VDD_DDR_CH1_VDDQ_CKE VDD_DDR_CH1_VDDA_PLL_1P8 VDD_SCU_ANA_1P8 VDD_SCU_1P8 VDD_CP_1P8 VDD_SCU_XTAL_1P8 VDD_ANA0_1P8 VDD_ANA1_1P8 VDD_ANA2_1P8 VDD_ANA3_1P8 VDD_SIM0_1P8_3P3 VDD_M4_GPT_UART_1P8_3P3 VDD_ESAI1_SPDIF_SPI_1P8_3P3 VDD_ESAI0_MCLK_1P8_3P3 VDD_SPI_SAI_1P8_3P3 VDD_FLEXCAN_1P8_3P3 VDD_QSPI1A_1P8_3P3 VDD_QSPI0_1P8_3P3 VDD_EMMC0_1P8_3P3 VDD_USDHC_VSELECT_1P8_3P3 VDD_USDHC1_1P8_3P3 VDD_USDHC2_1P8_3P3 VDD_ENET_MDIO_1P8_3P3 VDD_ENET0_1P8_3P3 VDD_ENET1_1P8_2P5_3P3 VDD_LVDS_DIG_1P8_3P3 VDD_LVDSx_1P8 VDD_LVDSx_1P0 VDD_MIPI_DSI_DIG_1P8_3P3 VDD_MIPI_DSIx_1P8 VDD_MIPI_DSIx_1P0 VDD_MIPI_DSIx_PLL_1P0 Value Unit Comments 800 mA Does not include current used by external memory. 200 mA Does not include current used by external memory. 20 mA 5 mA 20 mA Digital I/Os of SCU 60 ma There is a peak current of 60mA over 140 s. 10 mA Supply of crystal oscillator and integrated 200 MHz oscillator 175 mA 45 mA 140 mA 110 mA 15 mA 45 mA 40 mA 25 mA 35 mA 15 mA 20 mA 35 mA 55 mA 5 mA 55 mA 35 mA 15 mA 25 mA 25 mA 25 mA 100 mA x is 0 or 1 5 mA x is 0 or 1 20 mA 5 mA x is 0 or 1 35 mA x is 0 or 1 5 mA x is 0 or 1 i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 22 NXP Semiconductors Electrical characteristics Table 10. Maximum supply currents (continued) Symbol Value Unit Comments VDD_MIPI_CSI_DIG_1P8 20 mA VDD_MIPI_CSIx_1P8 5 mA x is 0 or 1 VDD_MIPI_CSIx_1P0 20 mA x is 0 or 1 VDD_HDMI_TX0_DIG_3P3 5 mA VDD_HDMI_TX0_1P8 80 mA VDD_HDMI_TX0_1P0 80 mA Shall be externally connected to VDD_HDMI_TX0_LDO_1P0_CAP VDD_ADC_1P8 5 mA VDD_ADC_DIG_1P8 VDD_MLB_DIG_1P8_3P31 VDD_MLB_1P82 1 mA 10 mA 50 mA VDD_USB_OTG1_1P0 1 mA Shall be externally connected to VDD_USB_SS3_LDO_1P0_CAP VDD_USB_OTG1_3P3 30 mA VDD_USB_OTG2_1P0 35 mA Shall be externally connected to VDD_USB_SS3_LDO_1P0_CAP VDD_USB_OTG2_3P3 10 mA VDD_USB_SS3_TC_3P3 10 mA VDD_USB_HSIC0_1P2 10 mA VDD_USB_HSIC0_1P8 5 mA VDD_PCIE_DIG_1P8_3P3 5 mA VDD_PCIE_IOB_1P8 45 mA VDD_PCIE_LDO_1P8 190 mA VDD_PCIE_SATA0_PLL_1P8 20 mA VDD_PCIE0_PLL_1P8 20 mA VDD_PCIE1_PLL_1P8 20 mA VDD_PCIE_SATA0_1P0 65 mA Shall be externally connected to VDD_PCIE_LDO_1P0_CAP VDD_PCIE0_1P0 65 mA Shall be externally connected to VDD_PCIE_LDO_1P0_CAP VDD_PCIE1_1P0 60 mA Shall be externally connected to VDD_PCIE_LDO_1P0_CAP VDD_SNVS_4P23 5 mA Start-up current 1 MLB is not supported on this product. This MLB power rail must be tied to the voltage specified in Table 8 if other I/O functions are used, as determined by IOMUX selection. Alternately, terminate the MLB supply per the Hardware Developer's Guide power supplies of unused functions. 2 MLB is not supported on this product. The MLB power rail must be tied to the voltage specified in Table 8 or may be terminated, per the Hardware Developer's Guide power supplies of unused tables. 3 Under normal operating conditions, the maximum current on VDD_SNVS_4P2 is shown Table 11. During initial power on, VDD_SNVS_4P2 can draw up to 5 mA if the supply is capable of sourcing that current. If less than 5 mA is available, the VDD_SNVS_LDO_1P8_CAP charge time will increase. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 23 Electrical characteristics 4.1.6 Low power mode supply currents The following table shows the current core consumption (not including I/O) in selected low power modes. Table 11. i.MX 8QuadPlus Key State (KSx) power consumption Mode Test conditions Supply KS0 KS11 SNVS only, all other supplies OFF. RTC running, tamper not active, external 32K crystal. RAM and IO state retained. DRAM in self-refresh, associated I/O's OFF. 32K running, 24M, PLLs and ring oscillators OFF PHYs are in idle state. MEMC, A53, A72, and GPU supplies OFF. MAIN2 dropped to 0.8 V. KS43 Leakage test, not intended as a customer use case. Overdrive conditions set, memories active, all sub-systems powered ON. Active power minimized. VDD_SNVS_4P2 (4.2 V) VDD_ANAx_1P8, VDD_SCUx_1P8, VDD_CP_1P8 (1.7V) VDD_A53 (OFF) VDD_A72 (OFF) VDD_GPU0 (OFF) VDD_GPU1 (OFF) VDD_MEMC (OFF) VDD_DDR_CHx_VDDQ (1.1V) VDD_MAIN (0.8V) Total VDD_A53 (1.1V) VDD_A72 (1.1V) VDD_GPU0 (1.0V) VDD_GPU1 (1.0V) VDD_MEMC (1.1V) VDD_MAIN (1.0V) Total 1 Maximum values are for 25 °C Tambient . 2 0.8 V nominal--voltage specification under this case is ± 3%. 3 Maximum values are for 125 °C Tjunction . Stated supply voltages do not exceed +2% during test. 4 Unavailable at time of publication. Max Unit 50 A 6 mA -- mA -- mA -- mA -- mA -- mA 1.4 mA 12 mA 21.94 mW 1066 mA 2000 mA See mA footnote4 See mA footnote4 1800 mA 1500 mA mW i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 24 NXP Semiconductors Electrical characteristics 4.1.7 USB 2.0 PHY typical current consumption in Power-Down mode In power down mode, everything is powered down, including the VBUS valid detectors, typical condition. The following table shows the USB interface typical current consumption in Power-Down mode. Table 12. USB 2.0 PHY typical current consumption in Power-Down Mode Current VDD_USB_OTG1_3P3 (3.3 V) 1 A VDD_ANA0_1P8 (1.8 V) 0.06 A VDD_USB_OTG1_1P0 (1.0 V) 0.5 A 4.1.8 USB 3.0 PHY typical current consumption in Power-Down mode In power down mode, everything is powered down, including the VBUS valid detectors, typical condition. The following table shows the USB interface typical current consumption in Power-Down mode. Table 13. USB 3.0 PHY typical current consumption in Power-Down Mode Current -- VDD_ANA0_1P8 (1.8 V) VDD_USB_OTG2_1P0 (1.0 V) -- 10 A 70 A The following table shows the current consumption for the USB 2.0 PHY embedded in the USB 3.0 PHY. Table 14. Typical current consumption in Power-Down mode for USB 2.0 PHY embedded in USB 3.0 PHY Current--Host mode Current--Device mode VDD_USB_OTG2_3P3 (3.3 V) 22.6 A 12.6 VDD_ANA0_1P8 (1.8 V) 12.7 85.7 VDD_USB_OTG2_1P0 (1.0 V) 81.5 78.5 i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 25 Electrical characteristics 4.2 Power supplies requirements and restrictions The system design must comply with power-up sequence, power-down sequence, and steady state guidelines as described in this section to ensure the reliable operation of the device. Any deviation from these sequences may result in the following situations: · Excessive current during power-up phase · Prevention of the device from booting · Irreversible damage to the processor 4.2.1 Power-up sequence The device has the following power-up sequence requirements: · Supply group 0 (SNVS) must be powered first. It is expected that group 0 will typically remain always on after the first power-on. · Supply group 1 (MAIN and SCU) and group 0 must both be powered to their nominal values prior to boot. They must power up after or simultaneously with group 0. · Supply group 2 (I/O's and DDR interface) consists of those modules required to start the boot process by accessing external storage devices. These must be fully powered prior to POR release if booting from one of these supplies interfaces. They must power up after or simultaneously with group 1. · Supply group 3 consists of the remaining portions of the SoC. This includes nonboot I/O voltages and supplies for the major computational units. These can be sequenced in any order and as required to perform the desired functions for the intended application. They must power up after or simultaneously with group 2. NOTE The definition of "power-up" refers to a stable voltage operating within the range defined in Table 8. This should be taken into consideration, along with the different capacitive loading on each rail, if considering simultaneous switch-on of the different supply groups. 4.2.2 Power-down sequence The device processor has the following power-down sequence requirements: · Supply group 0 must be turned off last, after all other supplies. · Supply group 1 can be turned off just prior to group 0. All remaining supplies can be turned off prior to group 1. NOTE When switching off supply group 0 (SNVS), VDD_SNVS_LDO_1P8_CAP must be fully discharged to 0 V before starting the next power-up sequence to ensure correct operation. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 26 NXP Semiconductors 4.2.3 Power Supplies Usage The following table shows the power supplies usage by group. Electrical characteristics i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 27 Electrical characteristics 28 Table 15. Power supplies usage i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 Supply Groups Voltage Group 0 2.4 - 4.2v VDD_SNVS_4P2 Group 1 1.0v 1.8v VDD_MAIN VDD_ANA1_1P8 VDD_LVDSx_1P0 VDD_ANA2_1P8 VDD_MIPI_CSIx_1P0 VDD_ANA3_1P8 VDD_MIPI_DSIx_1P0 VDD_CP_1P8 VDD_MIPI_DSIx_PLL_1P0 VDD_SCU_1P8 VDD_SCU_x_1P8 Group 2 1.1V 1.8v 1.8v or 3.3v 1.8v or 3.3v switchable 3.3v VDD_MEMC VDD_ADC_DIG_1P8 VDD_EMMC0_1P8_3P3 VDD_USDHCx_1P8_3P3 VDD_HDMI_RX0_VH_RX_3P3 VDD_DDR_CHx_VDDQ VDD_ADC_1P8 VDD_ESAI0_MCLK_1P8_3P3 VDD_SIM0_1P8_3P3 VDD_HDMI_TX0_DIG_3P3 VDD_DDR_CHx_VDDQ_CKE VDD_ANA0_1P8 VDD_ESAI1_SPDIF_SPI_1P8_3P3 VDD_USB_OTGx_3P3 VDD_DDR_CHx_VDDA_PLL_1P8 VDD_FLEXCAN_1P8_3P3 VDD_USB_SS3_TC_3P3 VDD_HDMI_x_1P8 VDD_LVDS_DIG_1P8_3P3 VDD_LVDSx_1P8 VDD_M4_GPT_UART_1P8_3P3 VDD_MIPI_CSI_DIG_1P8 VDD_MIPI_x_1P8 VDD_MLB_1P82 VDD_MIPI_DSI_DIG_1P8_3P3 VDD_MLB_DIG_1P8_3P31 VDD_PCIE_DIG_1P8_3P3 VDD_PCIE_SATA0_PLL_1P8 VDD_QSPIx_1P8_3P3 VDD_PCIE_x_1P8 VDD_SPI_SAI_1P8_3P3 VDD_PCIEx_PLL_1P8 VDD_USDHC_VSELECT_1P8_3P3 VDD_USB_HSIC0_1P8 Group 3 1.1 - 1.1v 1.0v internal LDO's 1.2v 1.8v or 2.5v or 3.3v VDD_A53 VDD_HDMI_TX0_1P0 VDD_USB_HSIC0_1P2 VDD_ENET_MDIO_1P8_3P3 VDD_A72 VDD_PCIE_SATA0_1P0 VDD_ENET0_1P8_3P3 VDD_ENET1_1P8_2P5_3P3 VDD_GPUx VDD_PCIEx_1P0 VDD_USB_OTGx_1P0 1 MLB is not supported on this product. This MLB power rail must be tied to the voltage specified in Table 8 if other I/O functions are used as determined by IOMUX selection. Alternately, terminate the MLB supply, per the Hardware Developer's Guide power supplies usage of unused features. 2 MLB is not supported on this product. The MLB power rail must be tied to the voltage specified in Table 8 or may be terminated, per the Hardware Developer's Guide power supplies of unused functions. NXP Semiconductors 4.3 PLL electrical characteristics Electrical characteristics 4.3.1 PLLs of subsystems i.MX 8QuadPlus embeds a large number of PLLs to address clocking requirements of the various subsystems. These PLLs are controlled through the SCU and not directly by Cortex-A or Cortex-M4F processors. A software API shall be used by those processors to access the PLL settings. Additional PLLs are specific to high-performance interfaces. These are described in the following sections. This table summarizes the PLLs controlled by the SCU. Table 16. PLLs controlled by SCU Subsystem PLL usage Cortex-A532 Cortex-A723 Subsystem Subsystem CCI GPU Subsystem PLL #0: subsystem PLL #1: shaders DRC (DRAM Controller) Subsystem DB (DRAM Block) Subsystem DBLog Subsystem Display Controller 0 PLL #0: subsystem PLL #1: display clock #0 PLL #2: display clock #1 Display Controller 1 PLL #0: subsystem PLL #1: display clock #0 PLL #2: display clock #1 Imaging Subsystem Audio PLL #0: subsystem PLL #1: audio PLL #0 PLL #2: audio PLL #1 Connectivity Subsystem Source clock 24 24 24 24 24 24 Locking range1 Min freq. Max freq. 1250 2500 1250 2500 650 1250 1300 2500 1250 2500 1250 2500 Lock freq. · Overdrive: 2400 · Nominal: 1800 · Overdrive: 1600 · Nominal: 2120 1000 · Nominal: 2500 · Underdrive: 16004 · Nominal: 2500 · Underdrive: 16004 · LPDDR4: 1600 Unit MHz MHz MHz MHz MHz MHz 24 650 1300 750 MHz 24 650 1300 800 MHz 24 650 1300 800 MHz 24 650 1300 User-configurable MHz 24 650 1300 User-configurable MHz 24 650 1300 800 MHz 24 650 1300 User-configurable MHz 24 650 1300 User-configurable MHz 24 650 1300 1200 MHz 24 650 1300 700 MHz 24 650 1300 User-configurable MHz 24 650 1300 User-configurable MHz 24 650 1300 792 MHz i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 29 Electrical characteristics Table 16. PLLs controlled by SCU (continued) Subsystem PLL usage Locking range1 Source clock Lock freq. Unit Min freq. Max freq. HSIO (High-speed Subsystem I/O) 24 650 1300 800 MHz LSIO (Low-speed I/O) Subsystem 24 650 1300 800 MHz Cortex-M4 Subsystem 24 650 1300 792 MHz VPU PLL #0: subsystem 24 650 1300 1200 MHz PLL #1: Audio DSP (HiFi 4) 24 650 1300 666 MHz HDMI-TX / eDP Subsystem 24 650 1300 User-configurable MHz MIPI-DSI Subsystem 24 650 1300 864 MHz MIPI-CSI Subsystem 24 650 1300 720 MHz DMA Subsystem 24 650 1300 960 MHz SCU (System Controller Unit) Subsystem 24 650 1300 1056 MHz 1 Operating frequencies are limited to only those supported by the SCFW. 2 2400 MHz is used to generate the 1200 MHz maximum and 600 MHz slow operating points; 1800 MHz is used to generate the 900 MHz typical operating point. See Table 8 to get associated voltages. 3 1600 MHz is used for max operating point, 2120 MHz is used to generate 1060 MHz for typical operating point, and 2400 MHz is used to generate the 600 MHz slow operating point. See Table 8 to get associated voltages. 4 2500 MHz is used to generate 625 MHz for the max operating point, 1600 MHz is used to generate 400 MHz for the slow operating point. See Table 8 to get associated voltages. 4.3.2 PLLs dedicated to specific interfaces The following sections cover PLLs used for specific interfaces. Clock output frequency and clock output range refer to the output of the PLL. Additional clock dividers may be on the output path to divide the output frequency down to the targeted frequency. See the related sections in the reference manual for settings of these clock dividers. 4.3.2.1 Ethernet PLL This PLL is controlled by the SCU. Reference clock Clock output frequency Parameter Table 17. Ethernet PLL Value 24 1 Unit MHz GHz i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 30 NXP Semiconductors Electrical characteristics 4.3.2.2 USB 3.0 PLLs USB 3.0 has two PLLs. One is embedded in Super-Speed PHY. The other one is embedded in the USB 2.0 OTG PHY that is part of the USB 3.0 interface. The table below describes the PLL embedded in the Super-Speed PHY. Table 18. USB 3.0 PLL embedded in Super Speed PHY Reference clock Clock output frequency Parameter Value 24 5 Unit MHz GHz The table below describes the PLL embedded in the USBOTG PHY. Table 19. USB 3.0 PLL embedded in USBOTG PHY Reference clock Clock output frequency Parameter Value 24 480 Unit MHz MHz 4.3.2.3 USB 2.0 OTG and USB-HSIC PLLs This PLL is embedded in the USB 2.0 OTG PHY (the one which is not part of the USB 3.0 feature). It is also used to supply the 480 MHz clock to the HSIC interface. Reference clock Clock output frequency Table 20. USB 2.0 OTG and USB-HSIC PLLs Parameter Value 24 480 Unit MHz MHz 4.3.2.4 PCIe PLLs The PCIe interface has seven PLLs: · One is used to generate the single, common 100 MHz reference clock to each lane · One Transmit and one Receive PLL per lane (three lanes) i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 31 Electrical characteristics The table below shows the characteristics for the reference clock PLL. Parameter Reference clock Clock output frequency Table 21. PCIe reference clock PLLs Value 24 100 Unit Comments MHz -- MHz Used to generate internal 100 MHz reference clock to PCIe lanes The table below shows characteristics of the TX and RX PLLs used in each lane. Table 22. PCIe Transmit and Receive PLLs1 Parameter Value Unit Comments Reference clock 100 MHz From differential input clock pads or from internal PLL Clock output range 6 ~ 10 GHz PCIe gen3: 8GHz to get 8GHz baud clock PCIe gen2: 10GHz to get 5GHz baud clock PCIe gen1: 10GHz to get 2.5GHz baud clock 1 PCIe 1.0 and 2.0 compliant. PCIe 3.0 capable, contact your NXP representative. 4.3.2.5 HDMI-TX / DP PLLs The HDMI-TX interface uses two PLLs. One is used to generate the reference clock when using the HDMI PHY itself in HDMI mode. In DP mode, this PLL is bypassed and only the PLL embedded in the PHY is used. The table below shows characteristics of the reference clock PLL for HDMI. Parameter Reference clock Clock output range Table 23. HDMI reference clock PLL Value 24 1.25 ~ 2.5 Unit Comments MHz -- GHz Refer to HDMI / DP section of reference manual The table below shows characteristics of the PLL embedded in HDMI/DP PHY. Parameter Reference clock Clock output range Table 24. PLL embedded in HDMI/DP PHY Value 24MHz / derived from HDMI-TX PLL 5.4 Unit Comments MHz 24MHz: when in DP mode derived from HDMI-TX PLL: when in HDMI mode GHz Dependent on targeted display configuration i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 32 NXP Semiconductors Electrical characteristics 4.3.2.6 MIPI-DSI PLL The table below shows characteristics of the PLL embedded in the MIPI-DSI PHY. Parameter Reference clock Clock output range Table 25. MIPI-DSIPHY PLL Value 24 0.75 ~ 1.5 Unit Comments MHz -- GHz Dependent on targeted display configuration 4.3.2.7 LVDS PLL The table below shows characteristics of the PLL embedded in LVDS PHY. Parameter Reference clock Data rate range Table 26. LVDS PHY PLL Value 25 ~ 160 175 ~ 1120 Unit Comments MHz -- Mbps Dependent on targeted display configuration 4.4 On-chip oscillators 4.4.1 OSC24M This block integrates trimmable internal loading capacitors and driving circuitry. When combined with a suitable 24 MHz external quartz element, it can generate a low-jitter clock. The oscillator is powered from VDD_SCU_XTAL_1P8. The internal loading capacitors are trimmable to provide fine adjustment of the 24 MHz oscillation frequency. It is expected that customers burn appropriate trim values for the selected crystal and board parasitics. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 33 Electrical characteristics Figure 2. Normal Crystal Oscillation mode Table 27. Crystal specifications Parameter description Min Typ Max Unit Frequency1 Cload2 -- 24 -- MHz -- 18 -- pF Maximum drive level 200 -- -- W ESR -- -- 60 1 The required frequency accuracy is set by the serial interfaces utilized for a specific application and is detailed in the respective standard documents. 2 Cload is the specification of the quartz element, not for the capacitors coupled to the quartz element. 4.4.2 OSC32K This block implements an internal amplifier, trimmable load capacitors and a bias network that when combined with a suitable quartz crystal implements a low power oscillator. Additionally, if the clock monitor determines that the 32KHz oscillation is not present, then the source of the 32 KHz clock will automatically switch to the internal relaxation oscillator of lesser frequency accuracy. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 34 NXP Semiconductors Electrical characteristics CAUTION The internal ring oscillator is not meant to be used in customer applications, due to gross frequency variation over wafer processing, temperature, and supply voltage. These variations will cause timing issues to many different circuits that use the internal ring oscillator for reference; and, if this timing is critical, application issues will occur. To prevent application issues, it is recommended to only use an external crystal or an accurate external clock. If this recommendation is not followed, NXP cannot guarantee full compliance of any circuit using this clock. The OSC32K runs from VDD_SNVS_LDO_1P8_CAP, which is regulated from VDD_SNVS. The target battery/voltage range is 2.8 to 4.2 V for VDD_SNVS, with a regulated output of approximately 1.75 V. Table 28. OSC32K main characteristics Parameter Min Typ Max Comments Fosc -- 32.768 kHz -- This frequency is nominal and determined mainly by the crystal selected. 32.0 KHz is also supported. Current -- · xtal oscillator mode: 5 A -- These values are for typical process and room consumption · 32K internal oscillator mode: 10 A temperature. Values will be updated after silicon characterization. Bias resistor -- 200 M -- This the integrated bias resistor that sets the amplifier into a high gain state. Any leakage through the ESD network, external board leakage, or even a scope probe that is significant relative to this value will debias the amplifier. The debiasing will result in low gain, and will impact the circuit's ability to start up and maintain oscillations. Target Crystal Properties Cload -- 10 pF -- Usually crystals can be purchased tuned for different Cloads. This Cload value is typically 1/2 of the capacitances realized on the PCB on either side of the quartz. A higher Cload will decrease oscillation margin, but increases current oscillating through the crystal. ESR -- 50 k 100 k Equivalent series resistance of the crystal. Choosing a crystal with a higher value will decrease the oscillating margin. Frequency VPP RTC_XTALI Rise/fall time Table 29. External input clock for OSC32K Min Typ -- 32.768 or 32 700 -- -- -- Max -- VDD_SNVS_LDO_1P8_CAP -- Unit kHz mV ns Notes -- 1,2,3 4 i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 35 Electrical characteristics 1 The external clock is fed into the chip from the RTC_XTALI pin; the RTC_XTALO pin should be left floating. 2 The parameter specified here is a peak-to-peak value and VIH/VIL specifications do not apply. 3 The voltage applied on RTC_XTALI must be within the range of VSS to VDD_SNVS_LDO_1P8_CAP. 4 The rise/fall time of the applied clock are not strictly confined. 4.5 I/O DC Parameters This section includes the DC parameters of the following I/O types: · XTALI and RTC_XTALI (clock inputs) DC parameters · General Purpose I/O (GPIO) DC parameters NOTE The term `OVDD' in this section refers to the associated supply rail of an input or output. 1 or pdat 0 Predriver ovdd pmos (Rpu) pad Voh min Vol max nmos (Rpd) ovss Figure 3. Circuit for Parameters Voh and Vol for I/O Cells 4.5.1 XTALI and RTC_XTALI (Clock Inputs) DC Parameters For RTC_XTALI, VIH/VIL specifications do not apply. The high and low levels of the applied clock on this pin are not strictly defined, as long as the input's peak-to-peak amplitude meet the requirements and the input's voltage value does not exceed the limits. 4.5.2 General-purpose I/O (GPIO) DC parameters NOTE The term "OVDD" in this section refers to the associated supply rail of an input or output. The association is shown in Table 127. 4.5.2.1 Tri-voltage GPIO DC parameters The following tables show tri-voltage 1.8V, 2.5 V, and 3.3 V DC parameters, respectively, for GPIO pads. These parameters are guaranteed per the operating ranges in Table 8, unless otherwise noted. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 36 NXP Semiconductors Electrical characteristics Table 30. Tri-voltage 1.8 V GPIO DC parameters1 Parameter Symbol Test Conditions Min Max Units High-level output voltage2,3 VOH IOH= 0.1mA PDRV=1 0.8 × OVDD -- V Low-level output voltage2,3 VOL IOH= 2mA PDRV=0 IOL= -0.1mA PDRV=1 -- 0.125 × OVDD V High-Level input voltage2,4 VIH Low-Level input voltage VIL Pull-up resistance RPU IOL= -2mA PDRV=0 -- -- VIN=0V (Pullup Resistor) PUN = "L", PDN = "H" 0.625 × OVDD OVDD V 0 0.25 × OVDD V 15 50 k Pull-down resistance RDOWN VIN=OVDD( Pulldown Resistor) 15 PUN = "H", PDN = "L" 50 k Input current (no PU/PD) IIN VI = 0, VI = OVDD -1 1 A PUN = "H", PDN = "H" 1 For tri-voltage I/O, the associated IOMUXD compensation control register PSW_OVR and COMP bits must be set correctly. For 1.8 or 3.3 V operation, the SCFW API must be used to set PSW_OVR = 0b0 and COMP=0b000. For 2.5 V operation, PSW_OVR = 0b1 and COMP = 0b010. 2 Refer to Section 4.6.1 for undershoot and overshoot specifications. 3 As programmed in the associated IOMUX (PDRV field) register. High Drive mode is recommended for 3v3 and 2v5 modes. Low Drive mode is recommended for 1v8 mode. 4 Refer to Section 4.6.2 for monotonic requirements. Parameter High-level output voltage2,3 Low-level output voltage2,3 High-Level input voltage2,4 Low-Level input voltage Pull-up resistance Table 31. Tri-voltage 2.5 V GPIO DC parameters1 Symbol V OH V OL V IH VIL RPU Test Conditions IOH= 2mA PDRV=0 IOL= -2mA PDRV=0 -- -- VIN=0V (Pullup Resistor) PUN = "L", PDN = "H" Min 0.8 × OVDD -- 0.625 × OVDD 0 10 Max -- 0.125 × OVDD OVDD 0.25 × OVDD 100 Units V V V V k i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 37 Electrical characteristics Table 31. Tri-voltage 2.5 V GPIO DC parameters1 (continued) Parameter Symbol Test Conditions Min Max Units Pull-down resistance RDOWN VIN=OVDD( Pulldown 10 Resistor) PUN = "H", PDN = "L" 100 k Input current (no PU/PD) IIN VI = 0, VI = OVDD -1 PUN = "H", PDN = "H" 1 A 1 For tri-voltage I/O, the associated IOMUXD compensation control register PSW_OVR and COMP bits must be set correctly. For 1.8 or 3.3 V operation, the SCFW API must be used to set PSW_OVR = 0b0 and COMP=0b000. For 2.5 V operation, PSW_OVR = 0b1 and COMP = 0b010. 2 Refer to Section 4.6.1 for undershoot and overshoot specifications. 3 As programmed in the associated IOMUX (PDRV field) register. High Drive mode is recommended for 3v3 and 2v5 modes. Low Drive mode is recommended for 1v8 mode. 4 Refer to Section 4.6.2 for monotonic requirements. Table 32. Tri-voltage 3.3 V GPIO DC parameters1 Parameter Symbol Test Conditions Min Max Units High-level output voltage2,3 VOH IOH= 0.1mA 0.8 × OVDD V PDRV=1 Low-level output voltage2,3 V OL IOH= 2mA PDRV=0 IOPLD=R-0V.31=m1A -- 0.125 × OVDD V High-Level input voltage2,4,3 Low-Level input voltage Pull-up resistance V IH VIL RPU IOL= -2mA PDRV=0 -- -- VIN=0V (Pullup Resistor) PUN = "L", PDN = "H" 0.725 × OVDD OVDD V 0 0.25 × OVDD V 10 100 k Pull-down resistance RDOWN VIN=OVDD( Pulldown Resistor) 10 PUN = "H", PDN = "L" 100 k Input current (no PU/PD) IIN VI = 0, VI = OVDD -2 2 A PUN = "H", PDN = "H" 1 For tri-voltage I/O, the associated IOMUXD compensation control register PSW_OVR and COMP bits must be set correctly. For 1.8 or 3.3 V operation, the SCFW API must be used to set PSW_OVR = 0b0 and COMP=0b000. For 2.5 V operation, PSW_OVR = 0b1 and COMP = 0b010. 2 Refer to Section 4.6.1 for undershoot and overshoot specifications. 3 As programmed in the associated IOMUX (PDRV field) register. High Drive mode recommended for 3v3 and 2v5 modes. Low Drive mode is recommended for 1v8 mode. 4 Refer to Section 4.6.2 for monotonic requirements. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 38 NXP Semiconductors Electrical characteristics 4.5.2.2 Dual-voltage GPIO DC parameters The following two tables show dual-voltage 1.8 V and 3.3 V DC parameters, respectively, for GPIO pads. These parameters are guaranteed per the operating ranges in Table 8, unless otherwise noted. Table 33. Dual-voltage 1.8 V GPIO DC parameters Parameter Symbol Test Conditions Min Max Units High-level output voltage1,2 VOH Ioh= 0.1mA PDRV=1 0.8 × OVDD -- V Low-level output voltage1,2 Ioh= 2mA PDRV=0 VOL Iol= -0.1mA PDRV=1 -- 0.125 × OVD V D High-Level input voltage1,3 Iol= -2mA PDRV=0 VIH -- 0.625 × OVD OVDD V D Low-Level input voltage Pull-up resistance VIL -- RPU Vin=0 V (Pullup Resistor) PUN = "L", PDN = "H" 0 0.25 × OVDD V 15 50 k Pull-down resistance Rdown Vin=OVDD( Pulldown Resistor) 15 PUN = "H", PDN = "L" 50 k Input current (no PU/PD) IIN VI = 0, VI = OVDD PUN = "H", PDN = "H" -1 1 A 1 Refer to Section 4.6.1 for undershoot and overshoot specifications. 2 As programmed in the associated IOMUX (PDRV field) register. High Drive mode is recommended for SD standard (3v3 mode) and MMC standard (1v8/3v3 modes). Low Drive mode is recommended for SD standard (1v8 mode). 3 Refer to Section 4.6.2 for monotonic requirements. Parameter High-level output voltage1,2 Low-level output voltage1,2 High-Level input voltage1,3 Low-Level input voltage Table 34. Dual-voltage 3.3 V GPIO DC parameters Symbol VOH VOL VIH VIL Test Conditions Ioh= 0.1mA PDRV=1 Ioh= 2mA PDRV=0 Iol= -0.1mA PDRV=1 Iol= -2mA PDRV=0 -- -- Min 0.8 × OVDD Max Units -- V -- 0.125 × OVDD V 0.725 × OVDD OVDD V 0 0.25 × OVDD V i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 39 Electrical characteristics Table 34. Dual-voltage 3.3 V GPIO DC parameters (continued) Parameter Symbol Test Conditions Min Max Units Pull-upresistance RPU Vin=0V (Pullup Resistor) 10 100 k PUN = "L", PDN = "H" Pull-down resistance Rdown Vin=OVDD( Pulldown Resistor) 10 PUN = "H", PDN = "L" 100 k Input current (no PU/PD) IIN VI = 0, VI = OVDD -2 2 A PUN = "H", PDN = "H" 1 Refer to Section 4.6.1 for undershoot and overshoot specifications. 2 As programmed in the associated IOMUX (PDRV field) register. High Drive mode is recommended for SD standard (3v3 mode) and MMC standard (1v8/3v3 modes). Low Drive mode is recommended for SD standard (1v8 mode). 3 Refer to Section 4.6.2 for monotonic requirements. 4.5.2.3 Single-voltage GPIO DC parameters Table 35 and Table 36 show single-voltage 1.8 V and 3.3 V DC parameters, respectively, for GPIO pads. These parameters are guaranteed per the operating ranges in Table 8 unless otherwise noted. Parameter High-level output voltage1,2 Low-level output voltage1,2 High-Level input voltage2,3 Low-Level input voltage2,3 Pull-up resistance Pull-down resistance Input current (no PU/PD) Keeper Circuit Resistance Table 35. Single-voltage 1.8 V GPIO DC parameters Symbol VOH VOL VIH VIL RPU Rdown IIN R_Keeper Test Conditions IOH= 0.1mA DSE = 000 or 001 IOH= 2mA DSE = 010 or 011 IOH= 4mA DSE = 100 to 110 IOL= -0.1mA DSE = 000 or 001 IOL= -2mA DSE = 010 or 011 IOL= -4mA DSE = 100 to 110 -- -- Vin=0V (Pullup Resistor) PUN = "L", PDN = "H" Vin=OVDD( Pulldown Resistor) PUN = "H", PDN = "L" VI = 0, VI = OVDD PUN = "H", PDN = "H" VI =.3xOVDD, VI = .7x OVDD PUN = "L", PDN = "L" Min OVDD × 0.8 Max Units -- V -- OVDD × 0.2 V 0.65 × OVDD OVDD V 0 0.35 × OVDD V 20 90 k 20 90 k -5 5 A 20 90 k i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 40 NXP Semiconductors 1 As programmed in the associated IOMUX (DSE field) register. 2 Refer to Section 4.6.1 for undershoot and overshoot specifications. 3 Refer to Section 4.6.2 for monotonic requirements. Electrical characteristics Table 36. Single-voltage 3.3 V GPIO DC parameters Parameter Symbol Test Conditions High-level output voltage1,2 VOH IOH = 0.1mA DSE = 00 or 01 Low-level output voltage1,2 VOL IOH= 2mA DSE = 10 or 11 IOL= -0.1mA DSE = 00 or 01 High-Level input voltage2,3 VIH Low-Level input voltage2,3 VIL Pull-upresistance RPU IOL = -2mA DSE = 10 or 11 -- -- Vin=0 V (Pullup Resistor) PUN = "L", PDN = "H" Pull-down resistance Rdown Vin=OVDD( Pulldown Resistor) PUN = "H", PDN = "L" Input current (no PU/PD) IIN VI = 0, VI = OVDD PUN = "H", PDN = "H" Keeper Circuit Resistance R_Keeper VI =.3xOVDD, VI = .7x OVDD PUN = "L", PDN = "L" 1 As programmed in the associated IOMUX (DSE field) register. 2 Refer to Section 4.6.1 for undershoot and overshoot specifications. 3 Refer to Section 4.6.2 for monotonic requirements. Min 0.8 × OVDD -- 0.75 × OVDD 0 20 20 -5 20 Max Units -- V 0.2 × OVDD V OVDD V 0.25 × OVDD V 90 k 90 k 5 A 90 k 4.5.3 HDMI control signals parameters The following table shows HDMI control signals DC parameters. These parameters are guaranteed per the operating ranges in Table 8, unless otherwise noted. Parameter High-level input voltage Low-level input voltage Table 37. HDMI DDC and HPD DC parameters Symbol Test Conditions Min VIH -- 2 VIL -- 0 Max Units 5.3 V 0.8 V i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 41 Electrical characteristics 4.5.4 DDR I/O DC parameters 4.5.4.1 LPDDR4 mode I/O DC parameters These parameters are guaranteed per the operating ranges in Table 8 unless otherwise noted. Table 38. LPDDR4 DC parameters Parameter Symbol Test Conditions High-level output voltage1 Low-level output voltage1 VOH Output Drive = All settings (40,48,60,80,120,240) unterminated outputs VOL Output Drive = All settings (40,48,60,80,120,240) unterminated outputs Input current (no ODT) IIN VI = VSSQ, VI = VDDQ DC High-Level input voltage VIH_DC -- DC Low-Level input voltage VIL_DC -- 1 Refer to Section 4.6.1 for undershoot and overshoot specifications. Min 0.9 × VDDQ -- -2 VREF + 0.1 VSSQ Max Units -- V 0.1 × VDDQ V 2 A VDDQ V VREF 0.1 V 4.6 I/O AC Parameters The GPIO and DDR I/O load circuit and output transition time waveforms are shown in Figure 4 and Figure 5. From Output Under Test Test Point CL CL includes package, probe and fixture capacitance Figure 4. Load Circuit for Output Output (at pad) 80% 20% tr tf Figure 5. Output Transition Time Waveform OVDD 80% 20% 0V 4.6.1 I/O Overshoot and Undershoot Parameters For all inputs/outputs, maximum peak amplitude allowed for overshoot and undershoot is specified in Table 39. OVDD is the I/O Supply. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 42 NXP Semiconductors Electrical characteristics NOTE If a signal edge produces more than one overshoot/undershoot event, the sum of all areas following the transition must be less than the area specified. Table 39. Overshoot and Undershoot Parameters Parameter Amplitude above OVDD or below GND Area above OVDD or below GND (A + B) Symbol Min VPeak -- VArea -- Max Units 0.35 V 0.8 V-ns Overshoot/undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, and other methods. Noncompliance to this specification may affect device reliability or cause permanent damage to the device. VPeak A B Figure 6. Undershoot Waveform Example 4.6.2 Input Signal Monotonic Requirements Processor input signal monotonic requirements are illustrated in the following figure. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 43 Electrical characteristics Figure 7. Input Waveform Monotonic Requirement VIH_min and VIL_max are the guaranteed minimum logic-high and maximum logic-low voltage specifications, respectively. NXP devices are typically better than guaranteed specifications; these values are shown in the diagram as "typ". Nominally, lower voltages than the guaranteed specification are accepted by the device as logic high and higher voltages than the guaranteed specification are accepted as logic low. 4.6.3 General Purpose I/O (GPIO) AC Parameters Table 40. General Purpose I/O AC Parameters1 Symbol Parameter fmax Maximum frequency tr Rise time tf Fall time fmax Maximum frequency Test Condition Min Typ 1.8 V application2 Load = 21 pF (PDRV = L, high -- -- drive, 33 Load = 15 pF (PDRV = H, low drive, 50 Measured between VOL and 0.4 -- VOH Measured between VOH and 0.4 -- VOL Driver 3.3 V application3 Load = 30 pF -- -- Max 208 1.32 1.32 52 Unit MHz ns ns MHz i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 44 NXP Semiconductors Electrical characteristics Table 40. General Purpose I/O AC Parameters1 (continued) Symbol Parameter Test Condition Min Typ Max Unit tr Rise time Measured between -- -- 3 ns VOL and VOH tf Fall time Measured between -- -- 3 ns VOH and VOL 1 All output I/O specifications are guaranteed for Accurate mode of the compensation cell operation. This is applicable for both DC and AC specifications. 2 All timing specifications in 1.8 V application are valid for High Drive mode (PDRV = L). In Low Drive mode (PDRV = H), the driver is functional. 3 All timing specifications in 3.3 V application are valid for Low Drive only. For High Drive setting, the driver is functional. Table 41. Dynamic input characteristics Symbol Parameter Condition1,2 Min Dynamic Input Characteristics for 3.3 V Application fop Input frequency of operation INPSL Slope of input signal at I/O -- -- Measured between 10% to 90% of the I/O swing -- Dynamic Input Characteristics for 1.8 V Application fop Input frequency of operation -- -- INPSL Slope of input signal at I/O Measured between 10% to 90% of the I/O swing -- 1 For all supply ranges of operation. 2 The dynamic input characteristic specifications are applicable for the digital bidirectional cells. Max Unit 52 MHz 3.5 ns 208 MHz 1.5 ns 4.7 Output Buffer Impedance Parameters This section defines the I/O impedance parameters for the following I/O types: · General Purpose I/O (GPIO) output buffer impedance · Double Data Rate I/O (DDR) output buffer impedance for LPDDR4 NOTE GPIO and DDR I/O output driver impedance is measured with "long" transmission line of impedance Ztl attached to I/O pad and incident wave launched into transmission line. Rpu/Rpd and Ztl form a voltage divider that defines specific voltage of incident wave relative to OVDD. Output driver impedance is calculated from this voltage divider (see Figure 8). i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 45 Electrical characteristics ipp_do predriver U,(V) VDD OVDD PMOS (Rpu) pad Ztl , L = 20 inches NMOS (Rpd) OVSS Vin (do) Cload = 1p 0 U,(V) OVDD Vref Vref1 Vref2 t,(ns) Vout (pad) 0 Vovdd Vref1 Rpu = × Ztl Vref1 t,(ns) Rpd = Vref2 × Ztl Vovdd Vref2 Figure 8. Impedance Matching Load for Measurement 4.7.1 GPIO output buffer impedance 4.7.1.1 Tri-voltage GPIO output buffer impedance Parameter Output impedance Output impedance Table 42. Tri-voltage 1.8 V GPIO output impedance DC parameters Symbol ZO ZO Test conditions 1DSE=0 1DSE=1 Typical 33 50 Units i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 46 NXP Semiconductors 1 As programmed in the associated IOMUX (PDRV field) register. Electrical characteristics Table 43. Tri-voltage 2.5 V GPIO output impedance DC parameters Parameter Symbol Test conditions Output impedance ZO 1DSE=0 Output impedance ZO 1DSE=1 1 As programmed in the associated IOMUX (PDRV field) register. Typical 25 33 Units Table 44. Tri-voltage 3.3 V GPIO output impedance DC parameters Parameter Symbol Test conditions Output impedance ZO 1DSE=0 Output impedance ZO 1DSE=1 1 As programmed in the associated IOMUX (PDRV field) register. Typical 25 37 4.7.1.2 Dual-voltage GPIO output buffer impedance Table 45. Dual-voltage 1.8 V GPIO output impedance DC parameters Parameter Symbol Test conditions Output impedance ZO 1DSE=0 Output impedance ZO 1DSE=1 1 `As programmed in the associated IOMUX (PDRV field) register. Typical 33 50 Units Units Table 46. Dual-voltage 3.3 V GPIO output impedance DC parameters Parameter Symbol Test conditions Output impedance ZO 1DSE=0 Output impedance ZO 1DSE=1 1 As programmed in the associated IOMUX (PDRV field) register. Typical 25 37 Units i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 47 Electrical characteristics 4.7.1.3 Single-voltage 1.8 V GPIO output buffer drive strength The following table shows the GPIO output buffer drive strength (OVDD 1.8 V). Table 47. Single-voltage GPIO 1.8 V output impedance DC parameters Parameter Symbol Test conditions 1DSE=000 1DSE=001 1DSE=010 Output impedance ZO 1DSE=011 1DSE=100 1DSE=101 1DSE=110 1DSE=111 1 As programmed in the associated IOMUX (DSE field) register. Typical 200 100 55 40 30 24 20 18 4.7.1.4 Single-voltage 3.3 V GPIO output buffer drive strength The following table shows the GPIO output buffer drive strength (OVDD 3.3 V). Units Table 48. Single-voltage GPIO 3.3 V output impedance DC parameters Parameter Symbol Test conditions Output impedance ZO 1DSE=00 1DSE=01 1DSE=10 1DSE=11 1 As programmed in the associated IOMUX (DSE field) register. Typical 400 200 100 50 Units i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 48 NXP Semiconductors Electrical characteristics 4.7.2 DDR I/O output buffer impedance The following tables show LPDDR4 I/O output buffer impedance of the device. The ZQ Calibration cell uses a single register (ZQnPR0) to determine the target output buffer impedances of the pull-up driver and the pull-down driver, as well as the target on-die termination impedance. The resulting calibration setting is then applied to all DDR pads within the PHY complex. Table 49 shows the recommended ZQnPR0 field settings for the LPDDR4 I/Os to achieve the desired output buffer impedances. Parameter Recommended combinations for DQ /CA pins Table 49. LPDDR4 I/O output buffer impedance Typical ZQnPR0 ZPROG_ASYM_PU_DRV 5 7 9 11 Impedance 80 60 48 40 ZQnPR0 ZPROG_ASYM_PD_DRV 3 5 7 9 Impedance 120 80 60 48 Table 50. LPDDR4 I/O on-die termination impedance Parameter Typical Impedance Recommended combinations for DQ/CA pins 120.0 80.0 60.0 48.0 40.0 ZQnPR0. ZPROG_HOST_ODT 3 5 7 9 11 4.8 System Modules Timing This section contains the timing and electrical parameters for the modules in each processor. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 49 Electrical characteristics 4.8.1 Reset Timing Parameters The following figure shows the reset timing and Table 51 lists the timing parameters. POR_B (Input) CC1 Figure 9. Reset timing diagram Table 51. Reset timing parameters ID CC1 Parameter Duration of SRC_POR_B to be qualified as valid Min Max Unit 1 -- XTALOSC_RTC_ XTALI cycle 4.8.2 WDOG reset timing parameters The following figure shows the WDOG reset timing and Table 52 lists the timing parameters. Figure 10. SCU_WDOG_OUT timing diagram Table 52. WDOG1_B timing parameters ID Parameter CC3 Duration of SCU_WDOG_OUT assertion Min Max 1 -- Unit XTALOSC_RTC_ XTALI cycle NOTE XTALOSC_RTC_XTALI is approximately 32 kHz. XTALOSC_RTC_XTALI cycle is one period or approximately 30 s. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 50 NXP Semiconductors Electrical characteristics 4.8.3 DDR SDRAMspecific parameters (LPDDR4) The i.MX 8 Family of processors have been designed and tested to work with JEDEC JESD209-4A compliant LPDDR4 memory . Timing diagrams and tolerances required to work with these memories are specified in the respective documents and are not reprinted here. Meeting the necessary timing requirements for a DDR memory system is highly dependent on the components chosen and the design layout of the system as a whole. NXP cannot cover in this document all the requirements needed to achieve a design that meets full system performance over temperature, voltage, and part variation; PCB trace routing, PCB dielectric material, number of routing layers used, placement of bulk/decoupling capacitors on critical power rails, VIA placement, GND and Supply planes layout, and DDR controller/PHY register settings all are factors affecting the performance of the memory system. Consult the hardware user guide for this device and NXP validated design layouts for information on how to properly design a PCB for best DDR performance. NXP strongly recommends duplicating an NXP validated design as much as possible in the design of critical power rails, placement of bulk/decoupling capacitors and DDR trace routing between the processor and the selected DDR memory. All supporting material is readily available on the device web page on https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applicatio ns-processors/i.mx-8-processors:IMX8-SERIES . Processors that demonstrate full DDR performance on NXP validated designs, but do not function on customer designs, are not considered marginal parts. A report detailing how the returned part behaved on an NXP validated system will be provided to the customer as closure to a customer's reported DDR issue. Customers bear the responsibility of properly designing the Printed Circuit Board, correctly simulating and modeling the designed DDR system, and validating the system under all expected operating conditions (temperatures, voltages) prior to releasing their product to market. Table 53. i.MX 8 Family DRAM controller supported SDRAM configurations Parameter Number of Controllers Number of Channels Number of Chip Selects Bus Width Number of Address Rows Maximum Clock Frequency 1 Only 16-bit external memory configurations are supported. LPDDR4 2 2 per controller 2 per channel 16 bit per channel1 16 (R0-R15) 1600 MHz 4.8.3.1 Clock/data/command/address pin allocations These processors uses generic names for clock, data and command address bus (DCF--DRAM controller functions); the following table provides mapping of clock, data and command address signals for LPDDR4 modes. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 51 Electrical characteristics Table 54. Clock, data, and command address signals for LPDDR4 modes DDR_CH[1:0].CK0_P DDR_CH[1:0].CK0_N DDR_CH[1:0].CK1_P DDR_CH[1:0].CK1_N DDR_CH[1:0].DQ_[15:0] DDR_CH[1:0].DQ_[31:16] DDR_CH[1:0].DQS_N_[3:0] DDR_CH[1:0].DQS_P_[3:0] DDR_CH[1:0].DM_[3:0] DDR_CH[1:0].DCF00 DDR_CH[1:0].DCF01 DDR_CH[1:0].DCF02 DDR_CH[1:0].DCF03 DDR_CH[1:0].DCF04 DDR_CH[1:0].DCF05 DDR_CH[1:0].DCF06 DDR_CH[1:0].DCF07 DDR_CH[1:0].DCF08 DDR_CH[1:0].DCF09 DDR_CH[1:0].DCF10 DDR_CH[1:0].DCF11 DDR_CH[1:0].DCF12 DDR_CH[1:0].DCF13 DDR_CH[1:0].DCF14 DDR_CH[1:0].DCF15 DDR_CH[1:0].DCF16 DDR_CH[1:0].DCF17 DDR_CH[1:0].DCF18 DDR_CH[1:0].DCF19 DDR_CH[1:0].DCF20 DDR_CH[1:0].DCF21 DDR_CH[1:0].DCF22 Signal name LPDDR4 CK_t_A CK_c_A CK_t_B CK_c_B DQ[15:0]_A DQ[15:0]_B DQS_N_[3:0] DQS_P_[3:0] DM_[3:0] CA2_A CA4_A CA5_A CA3_A ODT_CA_A CS0_A CA0_A CS1_A CKE0_A CKE1_A CA1_A CA4_B RESET_N CA5_B i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 52 NXP Semiconductors Electrical characteristics Table 54. Clock, data, and command address signals for LPDDR4 modes (continued) DDR_CH[1:0].DCF23 DDR_CH[1:0].DCF24 DDR_CH[1:0].DCF25 DDR_CH[1:0].DCF26 DDR_CH[1:0].DCF27 DDR_CH[1:0].DCF28 DDR_CH[1:0].DCF29 DDR_CH[1:0].DCF30 DDR_CH[1:0].DCF31 DDR_CH[1:0].DCF32 DDR_CH[1:0].DCF33 Signal name LPDDR4 ODT_CA_B CA3_B CA0_B CS0_B CS1_B CKE0_B CKE1_B CA1_B CA2_B 4.9 General-Purpose Media Interface (GPMI) Timing The GPMI controller is a flexible interface NAND Flash controller with 8-bit data width, up to 400 MB/s I/O speed, and individual chip select. It supports Asynchronous Timing mode, Source Synchronous Timing mode, and Toggle Timing mode, as described in the following subsections. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 53 Electrical characteristics 4.9.1 GPMI Asynchronous mode AC timing (ONFI 1.0 compatible) Asynchronous mode AC timings are provided as multiplications of the clock cycle and fixed delay. The Maximum I/O speed of GPMI in Asynchronous mode is about 50 MB/s. Figure 11 through Figure 14 depict the relative timing between GPMI signals at the module level for different operations under Asynchronous mode. Table 55 describes the timing parameters (NF1NF17) that are shown in the figures. .!.$?#,% .!.$?#%?" NF1 NF3 NF2 NF4 .!.$?7%?" NF5 .!.$?!,% .!.$?$!4!XX NF6 NF7 NF8 NF9 Command Figure 11. Command Latch Cycle Timing Diagram .!.$?#,% .!.$?#%?" .!.$?7%?" NF1 NF3 NF10 NF5 NF11 .!.$?!,% NAND_DATAxx NF6 NF8 Address NF7 NF9 Figure 12. Address Latch Cycle Timing Diagram .!.$?#,% .!.$?#%?" .!.$?7%?" NF1 NF3 NF10 NF5 NF11 .!.$?!,% NF6 NF7 .!.$?$!4!XX NF8 NF9 Data to NF Figure 13. Write Data Latch Cycle Timing Diagram i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 54 NXP Semiconductors Electrical characteristics .!.$?#,% .!.$?#%?" .!.$?2%?" NF14 NF13 NF15 .!.$?2%!$9?" NF12 NF16 NF17 .!.$?$!4!XX Data from NF Figure 14. Read Data Latch Cycle Timing Diagram (Non-EDO Mode) .!.$?#,% .!.$?#%?" .!.$?2%?" NF14 NF13 NF15 .!.$?2%!$9?" NF12 NAND_DATAxx NF16 NF17 Data from NF Figure 15. Read Data Latch Cycle Timing Diagram (EDO Mode) Table 55. Asynchronous Mode Timing Parameters1 Timing ID Parameter Symbol T = GPMI Clock Cycle Unit Min Max NF1 NAND_CLE setup time tCLS (AS + DS) × T - 0.12 [see 2,3] ns NF2 NAND_CLE hold time tCLH DH × T - 0.72 [see 2] ns NF3 NAND_CEx_B setup time tCS (AS + DS + 1) × T [see 3,2] ns NF4 NAND_CEx_B hold time tCH (DH+1) × T - 1 [see 2] ns NF5 NAND_WE_B pulse width tWP DS × T [see 2] ns NF6 NAND_ALE setup time tALS (AS + DS) × T - 0.49 [see 3,2] ns NF7 NAND_ALE hold time tALH (DH × T - 0.42 [see 2] ns NF8 Data setup time tDS DS × T - 0.26 [see 2] ns NF9 Data hold time tDH DH × T - 1.37 [see 2] ns NF10 Write cycle time tWC (DS + DH) × T [see 2] ns NF11 NAND_WE_B hold time tWH DH × T [see 2] ns NF12 Ready to NAND_RE_B low tRR4 (AS + 2) × T [see 3,2] -- ns NF13 NAND_RE_B pulse width tRP DS × T [see 2] ns NF14 READ cycle time tRC (DS + DH) × T [see 2] ns NF15 NAND_RE_B high hold time tREH DH × T [see 2] ns i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 55 Electrical characteristics Table 55. Asynchronous Mode Timing Parameters1 (continued) Timing ID Parameter Symbol T = GPMI Clock Cycle Unit Min Max NF16 Data setup on read NF17 Data hold on read tDSR tDHR -- 0.82/11.83 [see 5,6] (DS × T -0.67)/18.38 [see 5,6] ns -- ns 1 The GPMI asynchronous mode output timing can be controlled by the module's internal registers HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD. This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings. 2 AS minimum value can be 0, while DS/DH minimum value is 1. 3 T = GPMI clock period -0.075ns (half of maximum p-p jitter). 4 NF12 is met automatically by the design. 5 Non-EDO mode. 6 EDO mode, GPMI clock 100 MHz (AS=DS=DH=1, GPMI_CTL1 [RDN_DELAY] = 8, GPMI_CTL1 [HALF_PERIOD] = 0). In EDO mode (Figure 15), NF16/NF17 are different from the definition in non-EDO mode (Figure 14). They are called tREA/tRHOH (NAND_RE_B access time/NAND_RE_B HIGH to output hold). The typical value for them are 16 ns (max for tREA)/15 ns (min for tRHOH) at 50 MB/s EDO mode. In EDO mode, GPMI will sample NAND_DATAxx at rising edge of delayed NAND_RE_B provided by an internal DPLL. The delay value can be controlled by GPMI_CTRL1.RDN_DELAY (see the GPMI chapter of the device reference manual. The typical value of this control register is 0x8 at 50 MT/s EDO mode. However, if the board delay is large enough and cannot be ignored, the delay value should be made larger to compensate the board delay. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 56 NXP Semiconductors Electrical characteristics 4.9.2 GPMI Source Synchronous mode AC timing (ONFI 2.x compatible) The following figure shows the write and read timing of Source Synchronous mode. NF18 NF19 .!.$?#%?" NAND_CLE NAND_ALE NAND_WE/RE_B NAND_CLK NF23 NF25 NF26 NF25 NF26 NF22 NF24 NAND_DQS NAND_DQS Output enable NAND_DATA[7:0] NF20 NF21 CMD NF20 NF21 ADD NAND_DATA[7:0] Output enable Figure 16. Source Synchronous Mode Command and Address Timing Diagram i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 57 Electrical characteristics .!.$?#%?" NF18 .!.$?#,% .!.$?!,% NF23 NF23 NF25 NF25 NF26 NF26 NF24 NF24 NF19 NAND_WE/RE_B .!.$?#,+ .!.$?$13 NF27 NF22 NF27 .!.$?$13 Output enable NF29 NF29 .!.$?$1;= .!.$?$1;= Output enable NF28 NF28 Figure 17. Source Synchronous Mode Data Write Timing Diagram NF18 .!.$?#%?" NF19 .!.$?#,% NF23 NF25 NF26 NF24 NAND_ALE NF23 NF25 NF26 NF24 .!.$?7%2% NF25 NF22 .!.$?#,+ NF26 NF25 .!.$?$13 .!.$?$13 /UTPUTENABLE .!.$?$!4!;= .!.$?$!4!;= /UTPUTENABLE Figure 18. Source Synchronous Mode Data Read Timing Diagram i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 58 NXP Semiconductors Electrical characteristics .!.$?$13 NF30 .!.$?$!4!;= D0 D1 D2 D3 NF30 NF31 NF31 Figure 19. NAND_DQS/NAND_DQ Read Valid Window Table 56. Source Synchronous Mode Timing Parameters1 Timing ID Parameter Symbol T = GPMI Clock Cycle Unit Min Max NF18 NAND_CEx_B access time NF19 NAND_CEx_B hold time tCE CE_DELAY × T - 0.79 [see 2] ns tCH 0.5 × tCK - 0.63 [see 2] ns NF20 Command/address NAND_DATAxx setup time tCAS 0.5 × tCK - 0.05 ns NF21 Command/address NAND_DATAxx hold time tCAH 0.5 × tCK - 1.23 ns NF22 clock period NF23 preamble delay NF24 postamble delay tCK -- ns tPRE PRE_DELAY × T - 0.29 [see 2] ns tPOST POST_DELAY × T - 0.78 [see 2] ns NF25 NAND_CLE and NAND_ALE setup time tCALS 0.5 × tCK - 0.86 ns NF26 NAND_CLE and NAND_ALE hold time tCALH 0.5 × tCK - 0.37 ns NF27 NAND_CLK to first NAND_DQS latching transition tDQSS T - 0.41 [see 2] ns NF28 Data write setup tDS 0.25 × tCK - 0.35 ns NF29 Data write hold tDH 0.25 × tCK - 0.85 ns NF30 NAND_DQS/NAND_DQ read setup skew tDQSQ -- 2.06 -- NF31 NAND_DQS/NAND_DQ read hold skew tQHS -- 1.95 -- 1 The GPMI source synchronous mode output timing can be controlled by the module's internal registers GPMI_TIMING2_CE_DELAY, GPMI_TIMING_PREAMBLE_DELAY, GPMI_TIMING2_POST_DELAY. This AC timing depends on these registers settings. In the table, CE_DELAY/PRE_DELAY/POST_DELAY represents each of these settings. 2 T = tCK (GPMI clock period) -0.075ns (half of maximum p-p jitter). Figure 19 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid window. For Source Synchronous mode, the typical value of tDQSQ is 0.85 ns (max) and 1 ns (max) for tQHS at 200 MB/s. GPMI will sample NAND_DATA[7:0] at both rising and falling edge of a delayed NAND_DQS signal, which can be provided by an internal DPLL. The delay value can be controlled by GPMI register GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the device reference manual. Generally, the typical delay value of this register is equal to 0x7 which means 1/4 clock cycle delay expected. However, if the board delay is large enough and cannot be ignored, the delay value should be made larger to compensate the board delay. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 59 Electrical characteristics 4.9.3 ONFI NV-DDR2 mode (ONFI 3.2 compatible) 4.9.3.1 Command and address timing ONFI 3.2 mode command and address timing is the same as ONFI 1.0 compatible Async mode AC timing. See Section 4.9.1, "GPMI Asynchronous mode AC timing (ONFI 1.0 compatible)"," for details. 4.9.3.2 Read and write timing ONFI 3.2 mode read and write timing is the same as Toggle mode AC timing. See Section 4.9.4, "Toggle mode AC Timing"," for details. 4.9.4 Toggle mode AC Timing 4.9.4.1 Command and address timing NOTE Toggle mode command and address timing is the same as ONFI 1.0 compatible Asynchronous mode AC timing. See Section 4.9.1, "GPMI Asynchronous mode AC timing (ONFI 1.0 compatible)"," for details. 4.9.4.2 Read and write timing Figure 20. Toggle mode data write timing i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 60 NXP Semiconductors DEV?CLK .!.$?#%X?" .!.$?#,% .& .!.$?!,% .!.$?7%?" .!.$?2%?" .!.$?$13 .!.$?$!4!;= T#+ .& T#+ T#+ Electrical characteristics .& T#+ T#+ Figure 21. Toggle mode data read timing Table 57. Toggle mode timing parameters1 Timing ID Parameter Symbol T = GPMI Clock Cycle Min. Max. NF1 NAND_CLE setup time NF2 NAND_CLE hold time NF3 NAND_CE0_B setup time NF4 NAND_CE0_B hold time NF5 NAND_WE_B pulse width NF6 NAND_ALE setup time NF7 NAND_ALE hold time NF8 Command/address NAND_DATAxx setup time NF9 Command/address NAND_DATAxx hold time NF18 NAND_CEx_B access time tCLS tCLH tCS tCH tWP tALS tALH tCAS tCAH tCE (AS + DS) × T - 0.12 [see note2s,3] DH × T - 0.72 [see note2] (AS + DS) × T - 0.58 [see notes,2] DH × T - 1 [see note2] DS × T [see note2] (AS + DS) × T - 0.49 [see notes,2] DH × T - 0.42 [see note2] DS × T - 0.26 [see note2] DH × T - 1.37 [see note2] CE_DELAY × T [see notes4,2] -- NF22 clock period NF23 preamble delay tCK -- -- tPRE PRE_DELAY × T [see notes5,2] -- NF24 postamble delay tPOST POST_DELAY × T +0.43 [see -- note2] i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors Unit ns ns ns ns 61 Electrical characteristics Table 57. Toggle mode timing parameters1 (continued) Timing ID Parameter Symbol T = GPMI Clock Cycle Unit Min. Max. NF28 Data write setup NF29 Data write hold NF30 NAND_DQS/NAND_DQ read setup skew NF31 NAND_DQS/NAND_DQ read hold skew tDS6 tDH6 tDQSQ7 tQHS7 0.25 × tCK - 0.32 0.25 × tCK - 0.79 -- -- -- ns -- ns 3.18 3.27 1 The GPMI toggle mode output timing can be controlled by the module's internal registers HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD. This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings. 2 AS minimum value can be 0, while DS/DH minimum value is 1. 3 T = tCK (GPMI clock period) -0.075 ns (half of maximum p-p jitter). 4 CE_DELAY represents HW_GPMI_TIMING2[CE_DELAY]. NF18 is guaranteed by the design. Read/Write operation is started with enough time of ALE/CLE assertion to low level. 5 PRE_DELAY+1) (AS+DS) 6 Shown in Figure 20. 7 Shown in Figure 21. For DDR Toggle mode, Figure 21 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid window. The typical value of tDQSQ is 1.4 ns (max) and 1.4 ns (max) for tQHS at 133 MB/s. GPMI will sample NAND_DATA[7:0] at both rising and falling edge of an delayed NAND_DQS signal, which is provided by an internal DPLL. The delay value of this register can be controlled by GPMI register GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the device reference manual. Generally, the typical delay value is equal to 0x7 which means 1/4 clock cycle delay expected. But if the board delay is big enough and cannot be ignored, the delay value should be made larger to compensate the board delay. 4.10 External Peripheral Interface Parameters The following subsections provide information on external peripheral interfaces. 4.10.1 LPSPI timing parameters All LPSPI interfaces do not have the same maximum serial clock frequency. There are two groups. LPSPI interfaces which can operate at 60 MHz in Master mode and 40 MHz in Slave mode and the other group where interfaces operate at 40 MHz in Master mode and 20 MHz in Slave mode. The same performance is achieved at 1.8 V and 3.3 V unless otherwise stated. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 62 NXP Semiconductors Below are the LPSPI interfaces and their respective chip selects: Electrical characteristics Table 58. LPSPI interfaces and chip selects LPSPI interface Chip select Comment 60 MHz in Master mode and 40 MHz in Slave mode 40 MHz in Master mode and 20 MHz in Slave mode SPI0, SPI1, SPI2, SPI3 (primary mode) SPI3b (behind UART1) SPI1 is muxed behind ADC pins so it operates at 1.8 V only. -- 4.10.1.1 LPSPI Master mode Waveform is assuming LPSPI is configured in mode 0, i.e. TCR.CPOL=0b0 and TCR.CPHA=0b0. Timing parameters are valid for all modes using appropriate edge of the clock. Figure 22. LPSPI Master mode Table 59. LPSPI timings--Master mode at 60 MHz ID Parameter -- SPIx_SCLK Cycle frequency t1 SPIx_SCLK High or Low TimeRead SPIx_SCLK High or Low TimeWrite t2 SPIx_CSy pulse width t3 SPIx_CSy Lead Time(1) t4 SPIx_CSy Lag Time(3) Min -- 7.5 7.5 FCLK_PERIOD(2) x (PCSSCK + 1) / 2PRESCALE - 3 FCLK_PERIOD(2) x (SCKPCS + 1) / 2PRESCALE + 3 Max Unit 60 MHz -- ns -- ns -- ns -- ns i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 63 Electrical characteristics Table 59. LPSPI timings--Master mode at 60 MHz (continued) ID Parameter Min Max Unit t5 SPIx_SDO output Delay (CLOAD = 20 pF) -- 3 ns t6 SPIx_SDI Setup Time 2 -- ns t7 SPIx_SDI Hold Time 2 -- ns 1 This timing is controllable through CCR.PCSSCK and TCR.PRESCALE registers. 2 FCLK_PERIOD is the period of the functional clock provided to LPSPI module. Maximum allowed frequency is 240 MHz. 3 This timing is controllable through CCR.SCKPCS and TCR.PRESCALE registers. Table 60. LPSPI timings--Master mode at 40 MHz ID Parameter Min Max Unit -- SPIx_SCLK Cycle frequency -- 40 MHz t1 SPIx_SCLK High or Low TimeRead SPIx_SCLK High or Low TimeWrite 11 -- ns t2 SPIx_CSy pulse width t3 SPIx_CSy Lead Time(1) t4 SPIx_CSy Lag Time(3) 11 FCLK_PERIOD(2) x (PCSSCK + 1) / 2PRESCALE + 3 FCLK_PERIOD(2) x (SCKPCS + 1) / 2PRESCALE + 3 -- ns -- ns -- ns t5 SPIx_SDO output Delay (CLOAD = 20 pF) -- 5 ns t6 SPIx_SDI Setup Time 5 -- ns t7 SPIx_SDI Hold Time 4 -- ns 1 This timing is controllable through CCR.PCSSCK and TCR.PRESCALE registers. 2 FCLK_PERIOD is the period of the functional clock provided to LPSPI module. Maximum allowed frequency is 240 MHz. 3 This timing is controllable through CCR.SCKPCS and TCR.PRESCALE registers. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 64 NXP Semiconductors Electrical characteristics Figure 23. LPSPI Slave mode Table 61. LPSPI timings--Slave mode at 40 MHz ID Parameter -- SPIx_SCLK Cycle frequency t1 SPIx_SCLK High or Low TimeRead SPIx_SCLK High or Low TimeWrite t2 SPIx_CSy pulse width t3 SPIx_CSy Lead Time (CS setup time) t4 SPIx_CSy Lag Time (CS hold time) t5 SPIx_SDO output Delay (CLOAD = 20 pF) t6 SPIx_SDI Setup Time t7 SPIx_SDI Hold Time Min Max Unit -- 40 MHz 11 -- ns 11 -- ns 4 -- ns 2 -- ns -- 5 ns 2 -- ns 2 -- ns Table 62. LPSPI timings--Slave mode at 20 MHz ID Parameter -- SPIx_SCLK Cycle frequency t1 SPIx_SCLK High or Low TimeRead SPIx_SCLK High or Low TimeWrite t2 SPIx_CSy pulse width t3 SPIx_CSy Lead Time (CS setup time) Min Max Unit -- 20 MHz 22 -- ns 22 -- ns 4 -- ns i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 65 Electrical characteristics Table 62. LPSPI timings--Slave mode at 20 MHz (continued) ID Parameter t4 SPIx_CSy Lag Time (CS hold time) t5 SPIx_SDO output Delay (CLOAD = 20 pF) t6 SPIx_SDI Setup Time t7 SPIx_SDI Hold Time Min Max Unit 2 -- ns -- 18 ns 2 -- ns 2 -- ns 4.10.2 Serial audio interface (SAI) timing parameters The timings and figures in this section are valid for noninverted clock polarity (I2S_TCR2.BCP = 0b0, I2S_RCR2.BCP = 0b0) and non-inverted frame sync polarity (I2S_TCR4.FSP = 0b0, I2S_RCR4.FSP = 0b0). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (SAI_TXC / SAI_RXC) and/or the frame sync (SAI_TXFS / SAI_RXFS) shown in the figures below. The same performance is achieved at both 1.8 V and 3.3 V unless otherwise stated. NOTE SAI0 and SAI1 are transmit/receive capable. SAI2 and SAI3 are receive only. 4.10.2.1 SAI Master Synchronous mode In this mode, transmitter clock and frame sync are used by both transmitter and receiver (I2S_TCR2.SYNC=0b00, I2S_RCR2.SYNC=0b01). In that case, SAI interface requires only 4 signals to be routed: SAI_TXC, SAI_TXFS, SAI_TXD and SAI_RXD. SAI_RXC and SAI_RXFS can be left unconnected. I2S_RCR2.BCI shall be set to 0b1 to get setup and hold times provided in Table 63. Figure 24. SAI Master Synchronous mode i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 66 NXP Semiconductors Electrical characteristics Table 63. SAI timings--Master Synchronous mode ID Parameters -- SAI TXC clock frequency t1 SAI TXC pulse width low / high t2 SAI TXFS output valid t3 SAI TXD output valid t4 SAI RXD input setup t5 SAI RXD input hold Min -- 45% -- -- 1 4 Max 49.152 55% 2 2 -- -- Unit MHz SAI_TXC period ns ns ns ns 4.10.2.2 SAI Master mode In this mode, transmitter and/or receiver part are set to bring out transmit and/or receive clock. Frame sync can be either input or output. Figure 25. SAI Master mode Table 64. SAI timings--Master mode ID Parameters -- SAI TXC / RXC clock frequency1 t1 SAI TXC / RXC pulse width low / high t2 SAI TXFS / RXFS output valid Min -- 45% -- Max 49.152 55% 2 Unit MHz TXC/RXC period ns i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 67 Electrical characteristics Table 64. SAI timings--Master mode (continued) ID Parameters Min Max Unit t3 SAI TXD output valid -- 2 ns t4 SAI RXD/RXFS/TXFS input setup 6 -- ns t5 SAI RXD/RXFS/TXFS input hold 0 -- ns 1 Given the high setup time requirement on inputs, receiver and transmitter, when using frame sync in input, are likely to run at a lower frequency. This frequency will be driven by characteristics of the external component connected to the interface. 4.10.2.3 SAI Slave mode In this mode, transmitter and/or receiver parts are set to receive transmit and/or receive clock from external world. Frame sync can be either input or output. Figure 26. SAI Slave mode Table 65. SAI timings--Slave mode ID Parameters -- SAI TXC/RXC clock frequency t11 SAI TXC/RXC pulse width low/high t12 SAI TXFS/RXFS output valid t13 SAI TXD output valid t14 SAI RXD/RXFS/TXFS input setup t15 SAI RXD/RXFS/TXFS input hold Min -- 45% -- -- 1 4 Max 24.576 55% 13 13 -- -- Unit MHz TXC/RXC period ns ns ns ns i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 68 NXP Semiconductors Electrical characteristics 4.10.3 Enhanced serial audio interface (ESAI) The same performance is achieved at both 1.8 V and 3.3 V unless otherwise stated. SCKT (Input / Output) FST (bit) out FST (word) out Data Out FST (bit) in FST (word) in Flags Out t1 t1 2t 2t 2t t3 t4 t5 t6 First bit 4t t5 t6 t7 Figure 27. ESAI Transmit timing 2t Last bit t3 i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 69 Electrical characteristics Figure 28. ESAI Receive timing The following table shows the interface timing values. The ID field in the table refers to timing signals found in Figure 27 and Figure 28. Table 66. Enhanced Serial Audio Interface (ESAI) Timing ID Parameters Min Max Condition1 Unit -- Clock frequency -- 24.576 -- t1 SCKT / SCKT pulse width high / low 45% 55% -- t2 FST output delay -- 10 x ck 2 i ck t3 TX data - high impedance / valid data -- 9 x ck 1 i ck t4 TX data output delay -- 10 x ck 2 i ck t5 FST - setup requirement -- 2 x ck 10 i ck t6 FST - hold requirement -- 2 x ck 0 i ck t7 Flag output delay 10 x ck 2 i ck MHz SCKT / SCKR period ns ns ns ns ns ns i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 70 NXP Semiconductors Electrical characteristics Table 66. Enhanced Serial Audio Interface (ESAI) Timing (continued) ID Parameters Min Max Condition1 Unit t8 FSR output delay 7 x ck ns 4 i ck a t9 RX data pins - setup requirement 2 -- x ck ns 10 i ck t10 RX data pins - hold requirement 2 -- x ck ns 0 i ck t11 FSR - setup requirement 2 -- x ck ns 10 i ck a t12 FSR - hold requirement 2 -- x ck ns 0 i ck a t13 Flags - setup requirement 2 -- x ck ns 10 i ck s t14 Flags - hold requirement 2 -- x ck ns 0 i ck s -- RX_HF_CLK / TX_HX_CLK clock cycle 20 -- -- ns -- TX_HF_CLK input to SCKT 10 -- ns -- RX_HF_CLK input to SCKR 10 -- ns 1 i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode (SCKT and SCKR are two different clocks) i ck s = internal clock, synchronous mode (SCKT and SCKR are the same clock) 4.10.4 Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC) AC Timing This section describes the electrical information of the uSDHC, including: · SD3.1/eMMC5.1 High-Speed mode AC Timing · eMMC5.1 DDR 52 mode/SD3.1 DDR 50 mode timing · HS400 AC timing--eMMC 5.1 only · HS200 Mode Timing · SDR50/SDR104 AC Timing i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 71 Electrical characteristics 4.10.4.1 SD3.1/eMMC5.1 High-Speed mode AC Timing The following figure depicts the timing of SD3.1/eMMC5.1 High-Speed mode, and Table 67 lists the timing characteristics. SD4 SD2 SD1 SD5 SDx_CLK SD3 SD6 Output from uSDHC to card SDx_DATA[7:0] SD7 SD8 Input from card to uSDHC SDx_DATA[7:0] Figure 29. SD3.1/eMMC5.1 High-Speed mode Timing Table 67. SD3.1/eMMC5.1 High-Speed mode interface timing specification ID Parameter Symbols Min Max Unit Card Input Clock SD1 Clock Frequency (Low Speed) Clock Frequency (SD/SDIO Full Speed/High Speed) Clock Frequency (MMC Full Speed/High Speed) Clock Frequency (Identification Mode) SD2 Clock Low Time SD3 Clock High Time SD4 Clock Rise Time SD5 Clock Fall Time fPP1 0 400 fPP2 0 25/50 fPP3 0 20/52 fOD 100 400 tWL 7 -- tWH 7 -- tTLH -- 3 tTHL -- 3 eSDHC Output/Card Inputs SD_CMD, SD_DATA (Reference to SD_CLK) kHz MHz MHz kHz ns ns ns ns SD6 eSDHC Output Delay tOD 6.6 3.6 ns eSDHC Input/Card Outputs SD_CMD, SD_DATA (Reference to SD_CLK) SD7 eSDHC Input Setup Time tISU 2.5 -- ns SD8 eSDHC Input Hold Time4 tIH 1.5 -- ns 1 In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V. 2 In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 025 MHz. In high-speed mode, clock frequency can be any value between 050 MHz. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 72 NXP Semiconductors Electrical characteristics 3 In normal (full) speed mode for MMC card, clock frequency can be any value between 020 MHz. In high-speed mode, clock frequency can be any value between 052 MHz. 4 To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns. 4.10.4.2 eMMC5.1 DDR 52 mode/SD3.1 DDR 50 mode timing The following figure depicts the timing of eMMC5.1 DDR 52 mode/SD3.1 DDR 50 mode, and Table 68 lists the timing characteristics. Be aware that only SDx_DATA is sampled on both edges of the clock (not applicable to SD_CMD). SD1 SDx_CLK SD2 SD2 Output from eSDHCv3 to card SDx_DATA[7:0] ...... SD3 SD4 Input from card to eSDHCv3 SDx_DATA[7:0] ...... Figure 30. eMMC 5.1 timing Figure 31. eMMC5.1 DDR 52 mode/SD3.1 DDR 50 mode interface timing Table 68. eMMC5.1 DDR 52 mode/SD3.150 mode interface timing specification ID Parameter Symbols Min Max Card Input Clock1 SD1 Clock Frequency (eMMC5.1 DDR) SD1 Clock Frequency (SD3.1 DDR) fPP 0 52 fPP 0 50 uSDHC Output / Card Inputs SD_CMD, SDx_DATAx (Reference to CLK) SD2 uSDHC Output Delay tOD 2.8 6.8 uSDHC Input / Card Outputs SD_CMD, SDx_DATAx (Reference to CLK) SD3 uSDHC Input Setup Time SD4 uSDHC Input Hold Time 1 Clock duty cycle will be in the range of 47% to 53%. tISU 1.7 -- tIH 1.5 -- Unit MHz MHz ns ns ns 4.10.4.3 HS400 AC timing--eMMC 5.1 only Figure 32 depicts the timing of HS400. Table 69 lists the HS400 timing characteristics. Be aware that only data is sampled on both edges of the clock (not applicable to CMD). The CMD input/output timing for i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 73 Electrical characteristics HS400 mode is the same as CMD input/output timing for SDR104 mode. Check SD5, SD6 and SD7 parameters in Table 71 SDR50/SDR104 Interface Timing Specification for CMD input/output timing for HS400 mode. Figure 32. HS400 timing Table 69. HS400 interface timing specifications ID Parameter Symbols Min Max Unit Card Input clock SD1 Clock Frequency fPP 0 200 Mhz SD2 Clock Low Time SD3 Clock High Time tCL 0.46 × tCLK 0.54 × tCLK ns tCH 0.46 × tCLK 0.54 × tCLK ns uSDHC Output/Card inputs DAT (Reference to SCK) SD4 Output Skew from Data of tOSkew1 0.45 -- ns Edge of SCK SD5 Output Skew from Edge of tOSkew2 0.45 -- ns SCK to Data uSDHC input/Card Outputs DAT (Reference to Strobe) SD6 uSDHC input skew SD7 uSDHC hold skew tRQ -- 0.45 ns tRQH -- 0.45 ns i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 74 NXP Semiconductors Electrical characteristics 4.10.4.4 HS200 Mode Timing The following figure depicts the timing of HS200 mode, and Table 70 lists the HS200 timing characteristics. SCK SD1 SD2 SD3 SD4/SD5 8-bit output from uSDHC to eMMC 8-bit input from eMMC to uSDHC SD6 SD7 SD8 Figure 33. HS200 Mode Timing Table 70. HS200 Interface Timing Specification ID Parameter Symbols Min Max Card Input Clock SD1 Clock Frequency Period SD2 Clock Low Time SD2 Clock High Time tCLK tCL tCH 5.0 0.46 × tCLK 0.46 × tCLK -- 0.54 × tCLK 0.54 × tCLK uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK) SD5 uSDHC Output Delay tOD 1.6 1 uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)1 SD8 Card Output Data Window 1HS200 is for 8 bits while SDR104 is for 4 bits. tODW 0.5*tCLK -- Unit ns ns ns ns ns i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 75 Electrical characteristics 4.10.4.5 SDR50/SDR104 AC Timing The following figure depicts the timing of SDR50/SDR104, and Table 71 lists the SDR50/SDR104 timing characteristics. SCK Output from uSDHC to card SD1 SD2 SD3 SD5 SD4 SD6 SD7 Input from card to uSDHC SD8 Figure 34. SDR50/SDR104 timing Table 71. SDR50/SDR104 Interface Timing Specification ID Parameter Symbols Min Max Unit Card Input Clock SD1 SD2 SD3 Clock Frequency Period Clock Low Time Clock High Time tCLK 4.8 -- ns tCL 0.46 × tCLK 0.54 × tCLK ns tCH 0.46 × tCLK 0.54 × tCLK ns uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to SDx_CLK) SD4 uSDHC Output Delay tOD 3 1 ns uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to SDx_CLK) SD5 uSDHC Output Delay tOD 1.6 1 ns uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to SDx_CLK) SD6 uSDHC Input Setup Time tISU 2.5 -- ns SD7 uSDHC Input Hold Time tIH 1.5 -- ns uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to SDx_CLK)1 SD8 Card Output Data Window tODW 0.5 × tCLK -- ns 1Data window in SDR100 mode is variable. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 76 NXP Semiconductors Electrical characteristics 4.10.4.6 Bus Operation Condition for 3.3 V and 1.8 V Signaling Signaling level of SD/eMMC 5.1 and eMMC 5.1 modes is 3.3 V. Signaling level of SDR104/SDR50 mode is 1.8 V. The DC parameters for the NVCC_SD1, NVCC_SD2, and NVCC_SD3 supplies are identical to those shown in "," and Table 33, "Dual-voltage 1.8 V GPIO DC parameters," on page 39Table 34, "Dual-voltage 3.3 V GPIO DC parameters," on page 39. 4.10.5 Ethernet Controller (ENET) AC Electrical Specifications ENET interface supporting RGMII protocol in delay and non-delay mode. RGMII is used to support up to 1000 Mbps Ethernet as well as RMII protocol. RMII is used to support up to 100 Mbps Ethernet. NOTE ENET1 supports RGMII at 1.8 V and 2.5 V, and RMII at 3.3 V. ENET0 supports RGMII at 1.8 V only and RMII at 3.3 V. Pin name1 ENETx_RGMII_TXC Table 72. RGMII/RMII pin mapping RGMII RGMII_TXC RMII RCLK50M ENETx_RGMII_TX_CTL ENETx_RGMII_TXD0 ENETx_RGMII_TXD1 ENETx_RGMII_TXD2 ENETx_RGMII_TXD3 ENETx_RGMII_RXC ENETx_RGMII_RX_CTL ENETx_RGMII_RXD0 ENETx_RGMII_RXD1 ENETx_RGMII_RXD2 RGMII_TX_CTL RGMII_TXD0 RGMII_TXD1 RGMII_TXD2 RGMII_TXD3 RGMII_RXC RGMII_RX_CTL RGMII_RXD0 RGMII_RXD1 RGMII_RXD2 ENETx_RGMII_RXD3 RGMII_RXD3 ENETx_REFCLK_125M_25M RGMII_REF_CLK RMII_TXEN RMII_TXD0 RMII_TXD1 N/A N/A N/A RMII_CRS_DV RMII_RXD0 RMII_RXD1 RMII_RXER N/A N/A ENETx_MDIO ENETx_MDC 1 x can be 0 or 1. RGMII_MDIO RGMII_MDC RMII_MDIO RMII_MDC Comment2 RCLK50M can be an input or an output. It's using different Alternate pin muxing modes. Refer to pin muxing for details. -- -- -- -- -- -- -- -- -- RMII_RXER is mapped on ALT1 mode of pin muxing. -- RGMII_REF_CLK is optional for RGMII operation and dependent on the intended clock configuration. -- -- i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 77 Electrical characteristics 2 Except for RCLK50M and RMII_RXER, all other RMII functions are using the same pin muxing mode as RGMII. 4.10.5.1 RGMII 4.10.5.1.1 No-Internal-Delay mode This mode corresponds to the RGMIIv1.3 specification. Figure 35. RGMII timing diagram--No-Internal-Delay mode Table 73. RGMII timings--No-Internal-Delay mode ID Parameter Min Typ Max Unit TXC / RXC frequency -- 125 -- MHz t1 Clock cycle 7.2 8 8.8 ns t2 Data to clock output skew -500 -- 500 ps t3 Data to clock input skew1(1) 1 -- 2.6 ns 1 This implies that PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns and less than 2.0 ns is added to the associated clock signal. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 78 NXP Semiconductors Electrical characteristics 4.10.5.1.2 Internal-delay mode This mode corresponds to RGMIIv2.0 specification. The interface is still operating at 2.5 V. 1.5 V is not supported. Figure 36. RGMII timing diagram--Internal-Delay mode Table 74. RGMII timing--Internal-Delay mode ID Parameter TXC / RXC frequency t1 Clock cycle t2 TXD setup time t3 TXD hold time t4 RXD setup time t5 RXD hold time Min Typ Max -- 125 -- 7.2 8 8.8 1.2 -- -- 1.2 -- -- 0 -- -- 2.5 -- -- Unit MHz ns ns ns ns ns i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 79 Electrical characteristics 4.10.5.2 RMII RMII interface is matching RMII v1.2 specification. In RMII mode, the reference clock can be generated internally and provided to the PHY through RCLK50M_OUT. Or, it come from and external 50MHz clock generator which is connected to the PHY and to i.MX8 through RCLK50M_IN pin. Figure 37. RMII timing diagram Timings in table below are covering both cases: reference clock generated internally or externally. Table 75. RMII timing ID Parameter t1 Reference clock Reference clock accuracy Reference clock duty-cycle t2 RMII_TXEN, RMII_TXD output delay t3 RMII_CRS_DV, RMII_RXD setup time t4 RMII_CRS_DV, RMII_RXD hold time Min Typ Max Unit -- 50 -- MHz -- -- 50 ppm 35 -- 65 % 2 -- 12 ns 4 -- -- ns 2 -- -- ns 4.10.5.3 MDIO MDIO is the control link used to configure Ethernet PHY connected to i.MX8 device. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 80 NXP Semiconductors Electrical characteristics Figure 38. MDIO timing diagram Table 76. MDIO timing ID Parameter MDC frequency t1 MDC high / low pulse width t2 MDIO output delay t3 MDIO setup time t4 MDIO hold time Min Typ Max Unit -- 2.5 -- MHz 180 -- -- % 0 -- 20 ns 10 -- -- ns 10 -- -- ns 4.10.6 CAN network AC Electrical Specifications The Flexible Controller Area Network (FlexCAN) module is a communication controller implementing the CAN protocol according to the CAN with Flexible Data rate (CAN FD) protocol and the CAN 2.0B protocol specification. The processor has three CAN modules available for systems design. Tx and Rx ports for both modules are multiplexed with other I/O pins. See the IOMUXC chapter of the device reference manual to see which pins expose Tx and Rx pins; these ports are named FLEXCAN_TX and FLEXCAN_RX, respectively. 4.10.7 HDMI Tx module timing parameters See the following specifications: · DisplayPort 1.3 standard (VESA.org) · Embedded DisplayPort 1.4 standard (VESA.org) i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 81 Electrical characteristics The DDC link requires external pull-up resistors to be connected to a 5 V supply. The following table provides the range for those pull-ups. Table 77. HDMI--Pull-up resistors for DDC link Ball name HDMI_TX0_DDC_SCL HDMI_TX0_DDC_SDA Min Typ Max Unit 1.5 -- 1.5 -- 2 k 2 k 4.10.8 HDMI Tx and Rx REXT reference resistor connection Table 78. HDMI_REXT reference resistor connection Name Min Typ Max Unit Descriptions REXT 497.50 500 502.50 REXT resistor is 500 ± 0.5%. It shall be connected to ground. 4.10.9 I2C Module Timing Parameters This section describes the timing parameters of the I2C module. The following figure depicts the timing of the I2C module, and Table 79 lists the I2C module timing characteristics. I2Cx_SDA IC10 IC11 IC2 I2Cx_SCL START IC8 IC4 IC7 IC10b IC6 IC5 IC1 IC11b START Figure 39. I2C bus timing IC9 IC3 STOP START Table 79. I2C Module Timing Parameters ID Parameter IC1 I2Cx_SCL cycle time IC2 Hold time (repeated) START condition IC3 Set-up time for STOP condition IC4 Data hold time Standard Mode Min Max 10 -- 4.0 -- 4.0 -- 01 3.452 Fast Mode Unit Min Max 2.5 -- µs 0.6 -- µs 0.6 -- µs 01 0.92 µs i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 82 NXP Semiconductors Electrical characteristics Table 79. I2C Module Timing Parameters (continued) Standard Mode Fast Mode ID Parameter Unit Min Max Min Max IC5 HIGH Period of I2Cx_SCL Clock 4.0 -- 0.6 -- µs IC6 LOW Period of the I2Cx_SCL Clock 4.7 -- 1.3 -- µs IC7 Set-up time for a repeated START condition 4.7 -- 0.6 -- µs IC8 Data set-up time 250 -- 1003 -- ns IC9 Bus free time between a STOP and START condition 4.7 -- 1.3 -- µs IC10/IC10b Rise time of both I2Cx_SDA and I2Cx_SCL signals IC11/IC11b Fall time of both I2Cx_SDA and I2Cx_SCL signals -- 1000 20 + 0.1Cb4 300 ns -- 300 20 + 0.1Cb4 300 ns IC12 Capacitive load for each bus line (Cb) -- 400 -- 400 pF 1 A device must internally provide a hold time of at least 300 ns for I2Cx_SDA signal in order to bridge the undefined region of the falling edge of I2Cx_SCL. 2 The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2Cx_SCL signal. 3 A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7) of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2Cx_SCL signal. If such a device does stretch the LOW period of the I2Cx_SCL signal, it must output the next data bit to the I2Cx_SDA line max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the I2Cx_SCL line is released. 4 Cb = total capacitance of one bus line in pF. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 83 Electrical characteristics Table 80. I2C timing Fast Mode Plus ID Parameter Min Max IC1 SCL clock frequency -- 1 IC2 Hold time (repeated) START condition 260 -- IC3 Set-up time for STOP condition 260 -- IC4 Data hold time 0 -- IC5 HIGH Period of I2Cx_SCL Clock 260 -- IC6 LOW Period of the I2Cx_SCL Clock 500 -- IC7 Set-up time for a repeated START condition 260 -- IC8 Data set-up time 50 -- IC9 Bus free time between a STOP and START condition 500 -- IC10 Rise time of I2Cx_SDA signals -- 120 IC11 Fall time of I2Cx_SDA signals 12 (@3.3 V) 120 6.5 (@1.8 V) IC10b Rise time of I2Cx_SCL signals -- 120 IC11b Fall time of I2Cx_SCL signals 12 (@3.3 V) 120 6.5 (@1.8 V) IC12 Capacitive load for each bus line (Cb) -- 550 1 High-speed mode is only available for I2C modules in DMA, SCU and Cortex-M4 subsystems. 4.10.10 LVDS and MIPI-DSI display output specifications 4.10.10.1 LVDS display bridge module parameters Maximum frequency support for dedicated LVDS channels on this device: High Speed1 Unit Min Max -- 3.4 MHz 160 -- ns 160 -- ns 0 70 ns 60 -- ns 160 -- ns 160 -- ns 10 -- ns 150 -- ns 10 80 ns 10 80 ns 10 40 ns 10 40 ns -- 100 pF Table 81. LVDS pins Function1 Channel A Channel B Single channel 4 pairs LVDS up to 1.12 Gbps per pair 4 pairs LVDS up to 1.12 Gbps per pair Dual channel 8 pairs LVDS up to 595 Mbps per pair 1 In single channel operation the maximum clock speed is 160 MHz; in dual channel operation with a single synchronized clock the maximum clock speed is 85 MHz. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 84 NXP Semiconductors 4.10.10.2 MIPI-DSI display bridge module parameters Maximum frequency support for dedicated MIPI-DSI channels on this device: Electrical characteristics Table 82. MIPI-DSI pins Function1 Channel A DSI DSI up to 1.5 Gb/per lane 1 Maximum clock speed is 1.5 GHz. 4.10.10.3 LVDS display bridge (LDB) module electrical specifications The LVDS interface is compatible with TIA/EIA 644-A standard. For more details, see TIA/EIA STANDARD 644-A, "Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits." Table 83. LVDS Display Bridge (LDB) Electrical Specifications Parameter Differential Voltage Output Voltage Output Voltage High Output Voltage Low Offset Static Voltage VOS Differential Output short-circuited to GND Output short current Symbol VOD Voh Vol VOS VOSDIFF ISA ISB ISAB Test Condition Min 100 Differential load 100 differential load (0 V Diff--Output High Voltage static) 100 differential load (0 V Diff--Output Low Voltage static) Two 49.9 resistors in series between N-P terminal, with output in either Zero or One state, the voltage measured between the 2 resistors. Difference in VOS between a One and a Zero state With the output common shorted to GND 0.25 -- 0.925 1.125 -- -- -- Max 0.4 1.475 Units V V -- V 1.275 V -- mV 40 mA 12 mA 4.10.10.4 MIPI-DSI HS-TX specifications Symbol VCMTX1 |VCMTX|(1,0) |VOD|1 |VOD| Table 84. MIPI high-speed transmitter DC specifications Parameter High Speed Transmit Static Common Mode Voltage VCMTX mismatch when Output is Differential-1 or Differential-0 High Speed Transmit Differential Voltage VOD mismatch when Output is Differential-1 or Differential-0 Min Typ Max Unit 150 200 250 mV -- -- 5 mV 140 200 270 mV -- -- 10 mV i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 85 Electrical characteristics Table 84. MIPI high-speed transmitter DC specifications (continued) Symbol Parameter VOHHS1 High Speed Output High Voltage ZOS Single Ended Output Impedance ZOS Single Ended Output Impedance Mismatch 1 Value when driving into load impedance anywhere in the ZID range. Min Typ Max Unit -- -- 360 mV 40 50 62.5 -- -- 10 % Table 85. MIPI high-speed transmitter AC specifications Symbol Parameter VCMTX(HF) Common-level variations above 450 MHz VCMTX(LF) Common-level variation between 50-450 MHz tR and tF1 Rise Time and Fall Time (20% to 80%) 1 UI is the long-term average unit interval. Min Typ ---- ---- 100 -- Max 15 25 0.35 UI Unit mVRMS mVPEAK ps 4.10.10.5 MIPI-DSI LP-TX specifications Table 86. MIPI low-power transmitter DC specifications Symbol Parameter Min Typ Max Unit VOH1 Thevenin Output High Level 1.1 1.2 1.3 V VOL Thevenin Output Low Level 50 -- 50 mV ZOLP2 Output Impedance of Low Power Transmitter 110 -- -- 1 This specification can only be met when limiting the core supply variation from 1.1 V till 1.3 V. 2 Although there is no specified maximum for ZOLP, the LP transmitter output impedance ensures the TRLP/TFLP specification is met. Table 87. MIPI low-power transmitter AC specifications Symbol Parameter Min Typ Max Unit TRLP/TFLP1 15% to 85% Rise Time and Fall Time -- -- 25 ns TREOT1,2,3 30% to 85% Rise Time and Fall Time -- -- 35 ns TLP-PULSE-TX4 Pulse width of the LP exclusive-OR clock: First LP exclusive-OR clock pulse after Stop 40 -- -- ns state or last pulse before Stop state Pulse width of the LP exclusive-OR clock: All other pulses 20 -- -- ns TLP-PER-TX Period of the LP exclusive-OR clock 90 -- -- ns i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 86 NXP Semiconductors Electrical characteristics Table 87. MIPI low-power transmitter AC specifications (continued) Symbol Parameter Min Typ Max Unit V/tSR1,5,6,7 Slew Rate @ CLOAD= 0 pF Slew Rate @ CLOAD= 5 pF 30 -- 500 mV/ns 30 -- 200 mV/ns Slew Rate @ CLOAD= 20 pF 30 -- 150 mV/ns Slew Rate @ CLOAD= 70 pF 30 -- 100 mV/ns CLOAD Load Capacitance 0 -- 70 pF 1 CLOAD includes the low equivalent transmission line capacitance. The capacitance of TX and RX are assumed to always be < 10 pF. The distributed line capacitance can be up to 50 pF for a transmission line with 2 ns delay. 2 The rise-time of TREOT starts from the HS common-level at the moment of the differential amplitude drops below 70 mV, due to stopping the differential drive. 3 With an additional load capacitance CCM between 0 to 60 pF on the termination center tap at RX side of the lane. 4 This parameter value can be lower then TLPX due to differences in rise vs. fall signal slopes and trip levels and mismatches between Dp and Dn LP transmitters. Any LP exclusive-OR pulse observed during HS EoT (transition from HS level to LP-11) is glitch behavior as described in Low-Power Receiver section. 5 When the output voltage is between 15% and below 85% of the fully settled LP signal levels. 6 Measured as average across any 50 mV segment of the output signal transition. 7 This value represents a corner point in a piecewise linear curve. 4.10.10.6 MIPI-DSI LP-RX specifications Table 88. MIPI low power receiver DC specifications Symbol VIH VIL VIL-ULPS VHYST Parameter Logic 1 input voltage Logic 0 input voltage, not in ULP state Logic 0 input voltage, ULP state Input hysteresis Min Typ Max Unit 880 -- 1.3 mV -- -- 550 mV -- -- 300 mV 25 -- -- mV Table 89. MIPI low power receiver AC specifications Symbol Parameter Min Typ Max Unit eSPIKE1,2 TMIN-RX3 Input pulse rejection Minimum pulse width response -- -- 20 -- VINT Peak Interference amplitude -- -- fINT Interference frequency 450 -- 1 Time-voltage integration of a spike above VIL when in LP-0 state or below VIH when in LP-1 state. 2 An impulse below this value will not change the receiver state. 3 An input pulse greater than this value shall toggle the output. 300 V.ps -- ns 200 mV -- MHz i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 87 Electrical characteristics 4.10.10.7 MIPI-DSI LP-CD specifications Table 90. MIPI contention detector DC specifications Symbol VIHCD VILCD Parameter Logic 1 contention threshold Logic 0 contention threshold Min Typ Max Unit 450 -- -- mV -- -- 200 mV 4.10.10.8 MIPI-DSI DC specifications Table 91. MIPI input characteristics DC specifications Symbol Parameter Min Typ Max Unit VPIN ILEAK1 Pad signal voltage range Pin leakage current 50 -- 1350 mV 10 -- 10 A VGNDSH Ground shift 50 -- 50 mV VPIN(absmax)2 Maximum pin voltage level 0.15 -- 1.45 V TVPIN(absmax)3 Maximum transient time above VPIN(max) or below VPIN(min) -- -- 20 ns 1 When the pad voltage is within the signal voltage range between VGNDSH(min) to VOH + VGNDSH(max) and the Lane Module is in LP receive mode. 2 This value includes ground shift. 3 The voltage overshoot and undershoot beyond the VPIN is only allowed during a single 20 ns window after any LP-0 to LP-1 transition or vice versa. For all other situations it must stay within the VPIN range. 4.10.11 PCIe PHY Parameters The TX and RX eye diagrams specifications are per the template shown in the following figure. The summary of specifications is shown in Table 92 and Table 93. Note that the time closure (1A OPENING) in the eye templates needs not match jitter specifications in the Standards Specifications, as there are such discrepancies in some Standards Specifications. The design meets the tightest of specifications in case of discrepancy. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 88 NXP Semiconductors Electrical characteristics Figure 40. TX and RX eye diagram template Table 92. PCIe transmitter eye specifications for example standards UI AOPENING BOPENING AOPENING BOPENING VDIFFp-pmin VDIFFp-pmax ps UI ps mV PCI Express Gen 1 Transition Bit 400 0.75 0 300 0 800 12001 PCI ExpressGen 1 De-emphasized Bit 400 0.75 0 300 0 PCI Express Gen 2 Transition Bit 200 0.75 0 150 0 PCI Express Gen 2 De-emphasized Bit 200 0.75 0 150 0 1 VDIFFp-p eye opening is limited to VDDIO under matched termination conditions. 505 757 800 12001 379 850 Table 93. PCIe receiver eye specifications for example standards PCI Express Gen 1 Transition Bit PCI Express Gen 2 Transition Bit1 PCI Express Gen 3 Virtual EYE2 UI AOPENING BOPENING AOPENING BOPENING VDIFFp-pmin VDIFFp-pmax ps UI ps mV 400 0.4 0 160 0 175 1200 200 0.32 0 64 0 100 1200 125 0.3 0 38 0 25 1300 i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 89 Electrical characteristics 1 For a lossy channel, the default DFE setting may not work for PCIe Gen1 -3.5dB TX de-emphasis. It is recommended to use a higher DFE setting (reg241[7]=A1_force=1 and reg241[5:0]=A1_init) in this case. 2 PCIE 3.0 8 GT/s measured using PCIE reference equalizer + CDR per PCIE specification.PCIe 1.0 and 2.0 compliant. PCIe 3.0 capable, contact your NXP representative. Table 94. PCIe differential output driver characteristics (including board and load) Parameter Min Typ Max Units Notes Output Rise and fall time TR, TF Output Rise/Fall matching 175 -- 350 ps 1 -- -- 20 % 1, 2 Output skewTOSKEW Initialization time from assertion of TXOE -- -- 50 ps -- 100 -- -- ns -- Initialization time from assertion of TXENA -- 10 -- s -- Transmission line characteristic impedance (ZO) -- Driver output impedance, single ended (small signal @ -- Vout=Vcm) 50 1000 -- -- -- -- Output single ended voltage (RS= 33, RT= 50 ) VOH IOH@ 6 * IR VOL 0.65 -13 -0.20 0.71 -14.2 0.00 0.85 -17 0.05 V 3, 4 mA V 3 Output common mode voltage (RS = 33, RT= 50 ) |VOCM| VOCM (DC) VOCM (AC) Buffer induced deterministic jitter (absolute, pk-pk) 0.25 -0.015 -0.050 -- 0.375 -- 0.55 0.015 0.050 4 V 5 6 ps 7,8 Reference Buffer Dynamic Power (Digital) -- 0.015 0.66 A 9 Reference Buffer Dynamic Power (Analog) -- 2.8 3.14 mA 9 Output Buffer Dynamic Power (Digital) -- 0.035 1.8 A 9 Output Buffer Dynamic Power (Analog) -- 18.9 22.11 mA 9 1 When the output is transitioning between logic 0 and logic 1, or logic 1 and logic 0, and driving a terminated transmission line, the outputs monotonically transition between VOL and VOH, VOH, and VOL respectively. Target rise and fall times observed at the receiver and are primarily set by board trace impedance and Load capacitance. Rise and fall times are defined by 25% and 75% crossing points. 2 Calculated as: 2 × (TRTF) / (TR+ TF) 3 IR is proportional to the reference current. Measured across RT. The primary contributor to output voltage spread is VDD spread, and so a VDD tighter than ±10% may be required to achieve this spread. 4 Higher output voltages may occur depending on load, power supply, and selected output drive. Higher output voltages may transiently occur during initialization period following TXENA assertion. 5 Peak change in output differential voltage when driving a logic 0 and when driving a logic 1 under DC conditions. 6 Peak change in output differential voltage when driving a logic 0 and when driving a logic 1 under AC conditions. 7 Measured under "clean power supply and ground" conditions, and after de-embedding the jitter of the input, measured over a time span of 1000 cycles 8 Power supply induced jitter is included under this category, and the power supply variation is to be less than 8mVpp. Note that customer has to be uncommonly careful with power supply fidelity due to the small jitter numbers. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 90 NXP Semiconductors 9 Power consumption is simulated under the following conditions: Typ: TT, VDD=1.0 V, VD18=1.8 V, 25 °C Max: FF, VDD=1.1 V, VD18=1.98 V, 125 °C Dynamic: TXENA=1, TXOE=1 Static: TXENA=0, TXOE=1 4.10.11.1 PCIE_REXT reference resistor connection The following figure shows the PCIE_REXT reference resistor connection. Electrical characteristics Figure 41. PCIE_REXT reference resistor connection 4.10.11.2 PCIE_REF_CLK Contact an NXP representative to obtain the hardware development guide for this device, which contains details on the PCIe reference clock requirements. 4.10.12 Pulse Width Modulator (PWM) Timing Parameters This section describes the electrical information of the PWM. The PWM can be programmed to select one of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before being input to the counter. The output is available at the pulse-width modulator output (PWMO) external pin. The following figure depicts the timing of the PWM, and Table 95 lists the PWM timing parameters. PWMn_OUT Figure 42. PWM Timing i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 91 Electrical characteristics Table 95. PWM Output Timing Parameters ID Parameter -- PWM Module Clock Frequency P1 PWM output pulse width high P2 PWM output pulse width low Min Max 0 ipg_clk 15 -- 15 -- Unit MHz ns ns 4.10.13 FlexSPI (Quad SPI/Octal SPI) timing parameters The FlexSPI interface can work in SDR or DDR modes. It can operate up to 60 MHz at 3.3 V, 166 MHz at 1.8 V SDR mode or 200 MHz at 1.8 V DDR mode. It supports single-ended and differential DQS signaling. FlexSPI supports the following clocking scheme for a read data path: · Dummy read strobe generated by FlexSPI controller and looped back internally (FlexSPIn_MCR0[RXCLKSRC] = 0x0) · Dummy read strobe generated by FlexSPI controller and looped back through the DQS pad (FlexSPIn_MCR0[RXCLKSRC] = 0x1). It means the I/O cannot be used for another feature. · Read strobe provided by memory device and input from DQS pad (FlexSPIn_MCR0[RXCLKSRC] = 0x3) 4.10.13.1 SDR mode 4.10.13.1.1 SDR mode timing diagrams The following write timing diagram is valid for any FlexSPIn_MCR0[RXCLKSRC] value. Figure 43. FlexSPI write timing diagram (SDR mode) i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 92 NXP Semiconductors Electrical characteristics The following read timing diagram is valid for FlexSPIn_MCR0[RXCLKSRC] = 0x0 or 0x1. Figure 44. FlexSPI read timing diagram (SDR mode) The following read timing diagram is valid for FlexSPIn_MCR0[RXCLKSRC] = 0x3. Figure 45. FlexSPI read with DQS timing diagram (SDR mode) 4.10.13.1.2 SDR mode timing parameter tables Table 96. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x0 (SDR mode) ID Parameter -- QSPIx[A/B]_SCLK Cycle frequency t1 QSPIx[A/B]_SCLK High or Low Time t2 QSPIx[A/B]_SSy_B pulse width t3 QSPIx[A/B]_SSy_B Lead Time1 t4 QSPIx[A/B]_SSy_B Lag Time1 t5 QSPIx[A/B]_DATAy output Delay t6 QSPIx[A/B]_DATAy Setup Time t7 QSPIx[A/B]_DATAy Hold Time 1 Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2). Min Max -- 60 7.5 -- 1 -- TCSS+0.5 -- TCSH -- -- 1 6 -- 0 -- Unit MHz ns SCLK SCLK SCLK ns ns ns i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 93 Electrical characteristics Table 97. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x1 (SDR mode) ID Parameter -- QSPIx[A/B]_SCLK Cycle frequency t1 QSPIx[A/B]_SCLK High or Low Time t2 QSPIx[A/B]_SSy_B pulse width t3 QSPIx[A/B]_SSy_B Lead Time1 t4 QSPIx[A/B]_SSy_B Lag Time1 t5 QSPIx[A/B]_DATAy output Delay t6 QSPIx[A/B]_DATAy Setup Time t7 QSPIx[A/B]_DATAy Hold Time 1 Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2). Min Max -- 166 2.7 -- 1 -- TCSS+0.5 -- TCSH -- -- 1 1 -- 2 -- Unit MHz ns SCLK SCLK SCLK ns ns ns Table 98. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x3 (SDR mode) ID Parameter -- QSPIx[A/B]_DQS Cycle frequency t1 QSPIx[A/B]_SCLK High or Low Time t2 QSPIx[A/B]_SSy_B pulse width1 t3 QSPIx[A/B]_SSy_B Lead Time2 t4 QSPIx[A/B]_SSy_B Lag Time2 t5 QSPIx[A/B]_DATAy output Delay t8 QSPIx[A/B]_DQS / QSPIx[A/B]_DATAy delta 1 Minimum is 2 SCLK cycles even if CSINTERVAL value is less than 2. 2 Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2). Min Max -- 200 2.25 -- CSINTERVAL -- TCSS+0.5 -- TCSH -- -- 1 -0.65 0.65 Unit MHz ns SCLK SCLK SCLK ns ns i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 94 NXP Semiconductors 4.10.13.2 DDR mode 4.10.13.2.1 DDR mode timing diagrams Electrical characteristics Figure 46. FlexSPI write timing diagram (DDR mode) Figure 47. FlexSPI read timing diagram (DDR mode) QSPIx[A/B]_DQS QSPIx[A/B]_DATAy t9 t10 Figure 48. FlexSPI read with DQS timing diagram (DDR mode) Table 99. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x0 (DDR mode) ID Parameter -- QSPIx[A/B]_SCLK Cycle frequency t1 QSPIx[A/B]_SCLK High or Low Time Min Max Unit -- 30 MHz 15 -- ns i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 95 Electrical characteristics Table 99. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x0 (DDR mode) (continued) ID Parameter t2 QSPIx[A/B]_SSy_B pulse width t3 QSPIx[A/B]_SSy_B Lead Time1 t4 QSPIx[A/B]_SSy_B Lag Time1 t5 QSPIx[A/B]_DATAy output valid time t6 QSPIx[A/B]_DATAy output hold time t7 QSPIx[A/B]_DATAy Setup Time t8 QSPIx[A/B]_DATAy Hold Time 1 Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2). Min Max Unit 1 -- SCLK (TCSS+0.5)/2 -- SCLK TCSH/2 -- SCLK 6.5 -- ns 6.5 -- ns 6 -- ns 0 -- ns Table 100. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x1 (DDR mode) ID Parameter -- QSPIx[A/B]_SCLK Cycle frequency t1 QSPIx[A/B]_SCLK High or Low Time t2 QSPIx[A/B]_SSy_B pulse width t3 QSPIx[A/B]_SSy_B Lead Time1 t4 QSPIx[A/B]_SSy_B Lag Time1 t5 QSPIx[A/B]_DATAy output valid time t6 QSPIx[A/B]_DATAy output hold time t7 QSPIx[A/B]_DATAy Setup Time t8 QSPIx[A/B]_DATAy Hold Time 1 Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2). Min Max -- 83 5.4 -- 1 -- (TCSS+0.5)/2 -- TCSH/2 -- 2 -- 2 -- 1 -- 1 -- Unit MHz ns SCLK SCLK SCLK ns ns ns ns Table 101. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x3 (DDR mode) ID Parameter -- QSPIx[A/B]_SCLK Cycle frequency t1 QSPIx[A/B]_SCLK High or Low Time t2 QSPIx[A/B]_SSy_B pulse width t3 QSPIx[A/B]_SSy_B Lead Time1 t4 QSPIx[A/B]_SSy_B Lag Time1 t5 QSPIx[A/B]_DATAy output valid time t6 QSPIx[A/B]_DATAy output hold time Min Max -- 200 2.25 -- 1 -- (TCSS+0.5)/2 -- TCSH/2 -- 0.65 -- 0.65 -- Unit MHz ns SCLK SCLK SCLK ns ns i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 96 NXP Semiconductors Electrical characteristics Table 101. FlexSPI timings with FlexSPIn_MCR0[RXCLKSRC] = 0x3 (DDR mode) (continued) ID Parameter t9 QSPIx[A/B]_DATAy Setup Skew t10 QSPIx[A/B]_DATAy Hold Skew 1 Timing is controlled from FLSHxCR1 register (x=A1, A2, B1, or B2). Min Max Unit -- 0.65 ns -- 0.65 ns 4.10.14 Secure JTAG controller (SJC) 4.10.14.1 Internal pull-up/pull-down configuration The following table describes the default configuration of internal pull-ups and pull-downs of the JTAG interface. External pull-ups and pull-downs are needed when this interface is routed to a connector. Table 102. JTAG default configuration for internal pull-up/pull-down Ball name Internal pull setting1 Typical pull value Unit JTAG_TMS JTAG_TCK JTAG_TDI JTAG_TRST_B TEST_MODE_SELECT 1 PU = pull-up; PD = pull-down PU 50 K PD PU PU PD 4.10.14.2 JTAG timing parameters Figure 49 depicts the SJC test clock input timing. Figure 50 depicts the SJC boundary scan timing. Figure 51 depicts the SJC test access port. Figure 52 depicts the JTAG_TRST_B timing. Signal parameters are listed in Table 103. JTAG_TCK (Input) VIH SJ3 SJ2 VM VIL SJ1 SJ2 VM SJ3 Figure 49. Test Clock Input Timing Diagram i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 97 Electrical characteristics JTAG_TCK (Input) Data Inputs Data Outputs Data Outputs Data Outputs JTAG_TCK (Input) JTAG_TDI JTAG_TMS (Input) JTAG_TDO (Output) JTAG_TDO (Output) JTAG_TDO (Output) VIL SJ6 SJ7 VIH SJ4 SJ5 Input Data Valid Output Data Valid SJ6 Output Data Valid Figure 50. Boundary system (JTAG) timing diagram VIL SJ10 SJ11 VIH SJ8 SJ9 Input Data Valid Output Data Valid SJ10 Output Data Valid Figure 51. Test Access Port Timing Diagram i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 98 NXP Semiconductors Electrical characteristics JTAG_TCK (Input) JTAG_TRST_B (Input) SJ13 SJ12 Figure 52. JTAG_TRST_B Timing Diagram Table 103. JTAG Timing ID Parameter1,2 SJ0 JTAG_TCK frequency of operation 1/(3xTDC)1 SJ1 JTAG_TCK cycle time in crystal mode SJ2 JTAG_TCK clock pulse width measured at VM2 SJ3 JTAG_TCK rise and fall times SJ4 Boundary scan input data set-up time SJ5 Boundary scan input data hold time SJ6 JTAG_TCK low to output data valid SJ7 JTAG_TCK low to output high impedance SJ8 JTAG_TMS, JTAG_TDI data set-up time SJ9 JTAG_TMS, JTAG_TDI data hold time SJ10 JTAG_TCK low to JTAG_TDO data valid SJ11 JTAG_TCK low to JTAG_TDO high impedance SJ12 JTAG_TRST_B assert time SJ13 JTAG_TRST_B set-up time to JTAG_TCK low 1 TDC = target frequency of SJC 2 VM = mid-point voltage All Frequencies Min Max 0.001 22 45 -- 22.5 -- -- 3 5 -- 24 -- -- 40 -- 40 5 -- 25 -- -- 44 -- 44 100 -- 40 -- Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns 4.10.15 SPDIF Timing Parameters The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal. Table 104, Figure 53, and Figure 54 show SPDIF timing parameters for the Sony/Philips Digital Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 99 Electrical characteristics Table 104. SPDIF Timing Parameters Parameter SPDIF_IN Skew: asynchronous inputs, no specs apply SPDIF_OUT output (Load = 50pf) · Skew · Transition rising · Transition falling SPDIF_OUT output (Load = 30pf) · Skew · Transition rising · Transition falling Modulating Rx clock (SPDIF_SR_CLK) period SPDIF_SR_CLK high period SPDIF_SR_CLK low period Modulating Tx clock (SPDIF_ST_CLK) period SPDIF_ST_CLK high period SPDIF_ST_CLK low period Timing Parameter Range Symbol Unit Min Max -- -- 0.7 ns -- -- -- -- -- -- 1.5 ns 24.2 31.3 -- -- -- srckp srckph srckpl stclkp stclkph stclkpl -- -- -- 40.0 16.0 16.0 40.0 16.0 16.0 1.5 ns 13.6 18.0 -- ns -- ns -- ns -- ns -- ns -- ns SPDIF_SR_CLK (Output) srckpl VM srckp srckph VM Figure 53. SPDIF_SR_CLK Timing Diagram SPDIF_ST_CLK (Input) stclkpl VM stclkp stclkph VM Figure 54. SPDIF_ST_CLK Timing Diagram i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 100 NXP Semiconductors 4.10.16 UART I/O configuration and timing parameters Electrical characteristics 4.10.16.0.1 UART Transmitter The following figure depicts the transmit timing of UART in the RS-232 serial mode, with 8 data bit/1 stop bit format. Table 105 lists the UART RS-232 serial mode transmit timing characteristics. UARTx_TX_DATA (output) UA1 Start Bit Bit 0 UA1 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 POSSIBLE PARITY BIT Par Bit STOP BIT UA1 UA1 Figure 55. UART RS-232 Serial Mode Transmit Timing Diagram NEXT START BIT Table 105. UART RS-232 Serial Mode Transmit Timing Parameters ID Parameter Symbol Min Max Unit UA1 Transmit Bit Time tTbit 1/Fbaud_rate1 Tref_clk2 1/Fbaud_rate + Tref_clk -- 1 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (LPUART_clk frequency)/(SBR[12:0] × (OSR+1)). 2 Tref_clk: The period of UART reference clock ref_clk (LPUART_clk after SBR divider). 4.10.16.0.2 UART Receiver The following figure depicts the RS-232 serial mode receive timing with 8 data bit/1 stop bit format. Table 106 lists serial mode receive timing characteristics. UARTx_RX_DATA (input) UA2 UA2 POSSIBLE PARITY BIT Start Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Par Bit STOP BIT UA2 UA2 Figure 56. UART RS-232 Serial Mode Receive Timing Diagram NEXT START BIT Table 106. RS-232 Serial Mode Receive Timing Parameters ID Parameter Symbol Min Max Unit UA2 Receive Bit Time1 tRbit 1/Fbaud_rate2 1/(16 × Fbaud_rate) 1/Fbaud_rate + -- 1/(16 × Fbaud_rate) 1 The UART receiver can tolerate 1/((OSR+1) × Fbaud_rate) tolerance in each bit, but accumulation tolerance in one frame must not exceed 3/((OSR+1) × Fbaud_rate). 2 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (LPUART_clk frequency)/(SBR[12:0] × (OSR+1)). i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 101 Electrical characteristics 4.10.16.0.3 UART IrDA Mode Timing The following subsections give the UART transmit and receive timings in IrDA mode. UART IrDA Mode Transmitter The following figure depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. Table 107 lists the transmit timing characteristics. UA3 UA3 UA4 UA3 UA3 UARTx_TX_DATA (output) Start Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Figure 57. UART IrDA Mode Transmit Timing Diagram POSSIBLE PARITY BIT STOP BIT Table 107. IrDA Mode Transmit Timing Parameters ID Parameter Symbol Min Max Unit UA3 Transmit Bit Time in IrDA mode tTIRbit 1/Fbaud_rate1 Tref_clk2 1/Fbaud_rate + Tref_clk -- UA4 Transmit IR Pulse Duration tTIRpulse (TNP+1)/(OSR+1) × (1/Fbaud_rat (TNP+1)/(OSR+1) × (1/Fbaud_rat -- e) Tref_clk e) + Tref_clk 1 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (LPUART_clk frequency)/(SBR[12:0] × (OSR+1)). 2 Tref_clk: The period of UART reference clock ref_clk (LPUART_clk after SBR divider). UART IrDA Mode Receiver The following figure depicts the UART IrDA mode receive timing, with 8 data bit/1 stop bit format. Table 108 lists the receive timing characteristics. UA5 UA5 UA6 UA5 UA5 UARTx_RX_DATA (input) Start Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Figure 58. UART IrDA Mode Receive Timing Diagram POSSIBLE PARITY BIT STOP BIT Table 108. IrDA Mode Receive Timing Parameters ID Parameter Symbol Min Max Unit UA5 Receive Bit Time1 in IrDA mode tRIRbit 1/Fbaud_rate2 1/(16 × Fbaud_rate) 1/Fbaud_rate + -- 1/(16 × Fbaud_rate) UA6 Receive IR Pulse Duration tRIRpulse 1.41 s (5/16) × (1/Fbaud_rate) -- 1 The UART receiver can tolerate 1/((OSR+1) × Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not exceed 3/((OSR+1) × Fbaud_rate). i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 102 NXP Semiconductors Electrical characteristics 2 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (LPUART_clk frequency)/(SBR[12:0] × (OSR+1)). 4.10.17 USB HSIC Timings This section describes the electrical information of the USB HSIC port. NOTE HSIC is a DDR signal. The following timing specification is for both rising and falling edges. 4.10.17.1 USB HSIC Transmit Timing USB_H_STROBE USB_H_DATA Tstrobe Todelay Todelay Figure 59. USB HSIC Transmit Waveform Table 109. USB HSIC Transmit Parameters Name Parameter Tstrobe Todelay Tslew strobe period data output delay time strobe/data rising/falling time Min 4.165 550 0.7 Max 4.168 1350 2 Unit ns ps V/ns Comment -- Measured at 50% point Averaged from 30% 70% points 4.10.17.2 USB HSIC Receive Timing USB_H_STROBE USB_H_DATA Tstrobe Thold Tsetup Figure 60. USB HSIC Receive Waveform Table 110. USB HSIC Receive Parameters1 Name Parameter Tstrobe Thold strobe period data hold time Min 4.165 300 Max 4.168 -- Unit Comment ns -- ps Measured at 50% point i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 103 Electrical characteristics Table 110. USB HSIC Receive Parameters1 (continued) Name Parameter Min Max Tsetup data setup time 300 -- Tslew strobe/data rising/falling time 0.7 2 1 The timings in the table are guaranteed when: --AC I/O voltage is between 0.9× to 1× the I/O supply --DDR_SEL configuration bits of the I/O are set to (10)b Unit ps V/ns Comment Measured at 50% point Averaged from 30% 70% points 4.10.18 USB 2.0 PHY Parameters 4.10.18.1 USB 2.0 PHY Transmitter specifications This section describes the transmitter specifications for USB2.0 PHY. 4.10.18.1.1 USB 2.0 PHY full-speed/low-speed transmitter specifications The following table lists the full-speed/low-speed (FS/LS) transmitter specifications for USB2.0 PHY. Table 111. USB 2.0 PHY FS/LS transmitter specifications Symbol Description VOL Output Voltage Low VOH Output Voltage High (Driven) VOSE1 Single Ended One (SE1) VCRS Output Signal Cross Over Voltage TFR Driver Rise Time - FS TLR Driver Rise Time - LS TFF Driver Fall Time - FS TLF Driver Fall Time - LS TFRFM Differential Rise and Fall Time Matching - FS TLRFM Differential Rise and Fall Time Matching - LS ZHSDRV Driver Output Resistance (Also serves as HS Termination) TDJ1 Source Jitter (Next Transition) - FS TDJ2 Source Jitter (Paired Transition) - FS TFDEOP Source Jitter (Differential to SE0 transition) - FS TFEOPT Source SE0 interval of EOP - FS TDDJ1 Source Jitter in downstream direction (Next Transition) - LS TDDJ2 Source Jitter in downstream direction (Paired Transition) - LS TUDJ1 Source Jitter in upstream direction (Next Transition) - LS Min Typ Max Units 0 -- 0.3 V 2.8 -- 3.6 V 0.8 -- -- V 1.3 -- 2.0 V 4-- 20 ns 75 -- 300 ns 4-- 20 ns 75 -- 300 ns 90 -- 111.11 % 80 -- 125 % 40.5 -- 49.5 -3.5 -- 3.5 ns -4 -- 4 ns -2 -- 5 ns 160 -- 175 ns -25 -- 25 ns -14 -- 14 ns -95 -- 95 ns i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 104 NXP Semiconductors Electrical characteristics Table 111. USB 2.0 PHY FS/LS transmitter specifications (continued) Symbol Description TUDJ2 Source Jitter in upstream direction (Paired Transition) - LS TLDEOP Source Jitter in upstream direction (Differential to SE0 transition) - LS TLEOPT Source SE0 interval of EOP - LS Min Typ -150 -- -40 -- 1.25 -- Max 150 100 1.5 Units ns ns s 4.10.18.2 USB 2.0 PHY high-speed transmitter specifications The following table lists the high-speed (HS) transmitter specifications for USB 2.0 PHY. Table 112. USB 2.0 PHY HS transmitter specifications Symbol/Parameter HSOI VHSTERM VHSOL VCHIRPJ VCHIRPK ZHSDRV THSR THSF HS Eye Opening: Template 1 HS Eye Opening: Template 2 HS Jitter: Template 1 HS Jitter: Template 2 Description Min Typ Max Units High Speed Idle Level -10 -- 10 mV Termination Voltage in High Speed -10 -- 10 mV High Speed Data Signaling Low -10 -- 10 mV Chirp J (Differential Voltage) 700 -- 1100 mV Chirp K (Differential Voltage) -900 -- -500 mV Driver Output Resistance 40.5 -- 49.5 Rise Time (10% to 90%) 100 -- -- ps Fall Time (10% to 90%) 100 -- -- ps Differential eye opening at 37.5% US and 62.5% UI for a -300 -- 300 mV hub measured at TP2 and for a device without a captive cable measured at TP3. Differential eye opening at 37.5% US and 62.5% UI for a -175 -- 175 mV device with a captive cable measured at TP2. Peak-Peak Jitter at Zero crossing for a hub measured at TP2 and for a device without captive cable measured at TP3. ---- 15 %UI -- -- 312.5 ps Peak-Peak Jitter at Zero crossing for a device with captive -- cable measured at TP2. -- -- 25 %UI -- 520.83 ps 4.10.18.3 USB 2.0 PHY receiver specifications This section describes the receiver specifications implemented in USB 2.0 PHY. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 105 Electrical characteristics 4.10.18.3.1 USB 2.0 PHY full-speed/low-speed (FS/LS) receiver specifications Table 113. USB 2.0 PHY FS/LS receiver specifications Symbol VIH VIHZ VIL VTH VCM TJR1 TJR2 TFEOPR TUJR1 TUJR2 TDJR1 TDJR2 TLEOPR Description Input Voltage Level - High (Driven) Input Voltage Level - High (Floating) Input Voltage Level - Low Switching Threshold Common Mode Range Receiver Jitter Budget (Next Transition) - FS Receiver Jitter Budget (Paired Transition) - FS Receiver EOP Interval of EOP - FS US Port Differential Receiver Jitter (Next Transition) - LS US Port Differential Receiver Jitter (Paired Transition) - LS DS Port Differential Receiver Jitter (Next Transition) - LS DS Port Differential Receiver Jitter (Paired Transition) - LS Receiver EOP Interval of EOP - LS Min Typ Max Units 2 ---- V 2.7 -- 3.6 V -- -- 0.8 V 0.8 -- 2.0 V 0.8 -- 2.5 V -18.5 -- 18.5 ns -9 -- 9 ns 82 ---- ns -152 -- 152 ns -200 -- 200 ns -75 -- 75 ns -45 -- 45 ns 670 -- -- ns 4.10.18.3.2 USB 2.0 PHY high-speed receiver specifications The following table lists the high-speed (HS) receiver specifications for USB 2.0 PHY. Table 114. USB 2.0 PHY HS receiver specifications Symbol/Parameter Description Min Typ Max Units VHSCM HS RX input common mode voltage range. -50 -- 500 mV ZHSDRV HS RX input termination (Same as Driver output resistance). 40.5 -- 49.5 HSRX Jitter: Template 3 HS RX Peak-Peak Jitter specification at differential zero crossing for a -- device with captive cable when signal applied at TP2. -- -- 20 %UI -- 416.66 ps HSRX Jitter: Template 4 HS RX Peak-Peak Jitter specification at differential zero crossing for a -- -- 30 %UI device without captive cable at TP3 and for a hub at TP2. -- -- 625 ps HSRX Input Eye Opening: HS RX differential sensitivity specification at 40% and 60% UI for a -275 -- 275 mV Template 3 device with captive cable when signal is applied at TP2. HSRX Input Eye Opening: HS RX differential sensitivity specification at 35% and 65% UI for a -150 -- 150 mV Template 4 device without captive cable when signal is applied at TP3 and for a hub when a signal is applied at TP2. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 106 NXP Semiconductors Electrical characteristics 4.10.18.3.3 USB 2.0 PHY high-speed envelope detector specifications The following table lists the high-speed (HS) Envelope Detector Specifications of USB 2.0 PHY. Table 115. USB 2.0 PHY HS envelope detector specifications Symbol VHSSQ VHSDSC Description HS Squelch Detection threshold (differential signal amplitude) HS Disconnect Detection threshold (differential signal amplitude) Min Typ Max Units 100 -- 150 mV 525 -- 625 mV 4.10.18.4 USB 2.0 PHY full-speed/high-speed terminations specification The following table lists the full-speed/low-speed (FS/LS) Terminations Specification of USB 2.0 PHY. Table 116. USB 2.0 PHY FS/LS terminations specification Symbol RPU RPD VTERM Description Bus Pull-Up resistor on US Port in IDLE State Bus Pull-Up resistor on US Port in ACTIVE State Bus Pull-Down resistor on DS Port Termination Voltage for US Port Pull-Up (RPU) Min Typ 900 -- 1425 -- 14.25 -- 3.0 -- Max 1575 3090 24.8 3.6 Units K V 4.10.18.5 Voltage threshold specification The following table lists the OTG Comparator Specifications of USB2.0 PHY. Table 117. USB 2.0 PHY OTG comparator specifications Symbol sessvld vbusvalid Description B-Device Session Valid threshold VBUS Valid threshold Min Typ Max 0.8 -- 4.0 4.4 -- 4.75 4.10.19 USB 3.0 PHY parameters The following content is from the USB 3.0 PHY specifications. Units V V i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 107 Electrical characteristics 4.10.19.1 USB 3.0 PHY external component Table 118. USB 3.0 PHY external component specifications Name Min Typ Max Units Descriptions rext 497.5 500 502.5 There needs to be an external resistor component connected at rext ball while the internal resistor or current is getting calibrated. Package routing from rext ball to its respective bump should not contribute more than 0.05 . 4.10.19.2 USB 3.0 PHY transmitter module Table 119. USB 3.0 PHY transmitter module electrical specifications Symbol Description Min Typ Max Unit VTX-DIFFp VTX-DIFFp-p VTX-DIFFp-p-LOW1 ITX-SHORT RLTX-DIFF RLTX-CM ZTX-DIFF-DC UI TTX-MAX-JITTER TTX-RJ-PLL-sigma LTLAT-10 Voltage/current parameters Programmable output voltage 50 -- 500 mV swing (single-ended) Programmable differential 100 -- 1000 mV peak-to-peak output voltage Low power differential p-p TX 400 -- 1200 mV voltage swing Transmit lane short-circuit current ---- 100 mA Transmitter differential return loss ---- 0 < -20dB < 100Mhz Db 100Mhz < -18dB < 300Mhz 300Mhz < -16dB < 600Mhz 600Mhz < -10dB < 2500Mhz 2500Mhz < -9dB < 4875Mhz 4875Mhz < -8dB < 11200Mhz 11200Mhz < -5dB < 16800Mhz and -3dB beyond that Transmitter common mode return ---- 50Hz < -8dB < 15000Mhz dB loss DC differential TX impedance 80 100 120 Unit Interval 199.94 -- 200.06 ps Transmitter total jitter ---- 0.4 UI (peak-to-peak) (Tj) After application of TX jitter transfer -- -- 2.42 ps function Transmitter data latency ---- 210 UI i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 108 NXP Semiconductors Electrical characteristics Table 119. USB 3.0 PHY transmitter module electrical specifications (continued) Symbol Description Min Typ Max Unit Voltage parameters VTX-CM-DC-ACTIVE-IDLE-DELTA Absolute Delta of DC Common Mode Voltage during L0 and Electrical Idle. 0-- VTX-IDLE-DIFF-AC-p Electrical Idle Differential Peak Output Voltage 0-- VTX-CM-DC-LINE-DELTA Absolute Delta of DC Common 0-- Mode Voltage between D+ and D- VTX-RCV-DETECT The amount of voltage change 0-- allowed during Receiver Detection TTX-IDLE-SET-TO-IDLE Maximum time to transition to a ---- valid Electrical Idle after sending an EIOS TTX-IDLE-TO-DIFF-DATA Maximum time to transition to valid -- -- diff signaling after leaving Electrical Idle VTX-CM-AC-PP Tx AC peak-peak common mode voltage (5.0 GT/s) 20 -- TEIExit Time to exit Electrical Idle (L0s) state and to enter L0 ---- Tx signal characteristics ftol TX Frequency Long Term Accuracy -300 -- fSSC Spread-Spectrum Modulation Frequency t20-80TX TX Rise/Fall Time tskewTX TX Differential Skew 1 For USB 3.0, no EQ is required 30 -- 0.2 -- ---- 100 mV 20 mV 25 mV 600 mV 8 ns 8 ns 150 mVpp 5 Txsysclk 300 ppm of Fbaud 33 kHz 0.41 UI 20 ps 4.10.19.3 USB 3.0 PHY receiver module Symbol VRX-DIFF(p-p) Table 120. USB 3.0 PHY receiver module electrical specifications Description Min Typ Max Unit Comments Voltage Parameters Differential input voltage 100 -- 1200 mV -- (peak-to-peak) (that is, receiver eye voltage opening) i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 109 Electrical characteristics Table 120. USB 3.0 PHY receiver module electrical specifications (continued) Symbol Description Min Typ Max Unit Comments VRX-IDLE-DET-DIFF(p-p Differential input threshold voltage 100 -- 300 mV USB3 LFPS ) (peak-to-peak) to detect idle (LFPS) Vcm, acRX VRX-CM-AC RX AC Common Mode Voltage Receiver common-mode voltage for AC coupling -- -- 100 mVp-p Simulated at 250 MHz -- 0 150 mV -- ZRX-DIFF-DC RLRX-DIFF Differential input impedance (DC) 80 100 120 Receiver differential return loss Same as -- -- TX RL W 100 ± 10% dB -- Jitter Parameters TRX-MAX-JITTER Receiver total jitter tolerance 0 -- 0.66 UI Incoming Jitter: USB3 = 0.43UI DJ + 0.23UI RJ USB3 numbers are with REFC-TLE Table 121. PLL module electrical specifications Parameter Symbol Description Min Typ Max Units Input Reference Clock REF CLK Frequency REF CLK Duty Cycle REF CLK Frequency REF CLK RJ Tolerance REF CLK Duty Cycle Divided Reference Frequency REF CLK -- REF CLK -- -- -- -- 19.2 19.2/24/25/26/38.4 38.4 MHz -- 47 -- 53 MHz -- 40 40/48/50/52/100 100 MHz Integrated jitter from 10 kHz to 16 MHz -- after applying appropriate PLL ref clock transfer function and the protocol JTF -- 37 -- 0.5 ps -- 63 % -- 19.2 -- 38.4 MHz Dividers Input division IPDIV<7:0> -- Feedback division pll_fbdiv_high<9:0> -- pll_fbdiv_low<9:0> -- Feedback fractional -- -- division range 1 -- 255 Counts 2 -- 1025 Counts 2 -- 1025 Counts >-2 -- <2 Counts i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 110 NXP Semiconductors Parameter Number of fractional bits Clock frequency VCO frequency Output clock frequency tolerance SSC modulation rate Output clock RJ sigma for TX Output clock RJ sigma for RX Electrical characteristics Table 121. PLL module electrical specifications (continued) Symbol -- Description This includes one bit for sign Min Typ Max Units -- 27 -- Bits VCO -- Output full rate clocks -- VCO oscillation frequency -- This includes SSC deviation -- -- -5300 5000 5000 -- -- MHz -- MHz 300 ppm -- As applicable for USB3.0 30 -- After application of TX jitter transfer -- function -- After application of RX jitter transfer -- function -- 33 kHz -- 2.42 ps -- 1.40 ps 4.11 Analog-to-digital converter (ADC) The following table shows the ADC electrical specifications for VREFH=VDD_ADC_1P8. Symbol VADIN CADIN RADIN RAS fADCK Csample Ccompare Cconversion DNL INL ENOB SINAD Table 122. ADC electrical specifications (VREFH=VDD_ADC_1P8) Description Min Typ1 Max Input Voltage Input capacitance Input Resistance Analog Source Resistance ADC Conversion Clock Frequency Sample cycles Fixed compare cycles Conversion cycles Differential Non-Linearity Integral Non-Linearity Effective Number of Bits Avg = 1 Avg = 2 Avg = 16 Signal to Noise plus Distortion VREFL -- VREFH -- 4.5 -- -- 500 -- -- -- 5 -- 24 -- 3.5 -- 131.5 -- 17.5 -- Cconversion = Csample + Ccompare -- ± 0.6 -0.5 to +1.1 -- ± 0.9 ±1.1 -- -- -- 10.1 10.4 -- 10.5 10.7 -- 11.1 11.3 -- SINAD=6.02 x ENOB + 1.76 Unit V pF k MHz -- cycles cycles LSB LSB -- Bits Bits Bits dB Notes -- -- -- 2 -- 3 -- -- 4 4 5,6,7 -- i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 111 Electrical characteristics Table 122. ADC electrical specifications (VREFH=VDD_ADC_1P8) (continued) Symbol Description Min Typ1 Max Unit Notes EG EO IVDDA18 Gain error Offset error Supply Current -- -0.29 -- %FSV 8 -- 0.01 -- %FSV 9 -- 480 -- A 10 Iin,ext,leak External Channel Leakage Current -- 30 500 nA -- EIL Input leakage error RAS * Iin mV -- 1 Typical values assume VDD_ADC_1P8 = 1.8 V, Temp = 25 °C, fACLK = Max, unless otherwise stated. Typical values are for reference only. All values, including Min and Max, are derived from lab characterization and are not tested in production. 2 This resistance is external to the input pad. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 15 analog source resistance. The RAS/CAS (analog source capacitance) time constant should be kept to < 1 ns. 3 See Figure 61. 4 ADC conversion clock at max frequency and using linear histogram. 5 Input data used for test was 1 kHz sine wave. 6 Measured at VREFH = 1.8 V and pwrsel = 2. 7 ENOB can be lower than shown, if an ADC channel corrupts other ADC channels through capacitive coupling. This coupling may be dominated by board parasitics. Care must be taken not to corrupt the desired channel being measured. This coupling becomes worse at higher analog frequencies and with switching waveforms due to the harmonic content. 8 Error measured at fullscale at 1.8 V. 9 Error measured at zero scale at 0 V. 10 Power Configuration Select, PWRSEL, is set to 10 binary. The following table shows the ADC electrical specifications for 1VVREFH<VDD_ADC_1P8. Symbol VADIN CADIN RADIN RAS fADCK Csample Ccompare Cconversion DNL INL Table 123. ADC electrical specifications (1VVREFH<VDD_ADC_1P8) Description Min Typ1 Max Input Voltage VREFL -- VREFH Input capacitance -- 4.5 -- Input Resistance -- 500 -- Analog Source Resistance -- -- 5 ADC Conversion Clock Frequency -- 24 -- Sample cycles 3.5 -- 131.5 Fixed compare cycles -- 17.5 -- Conversion cycles Differential Non-Linearity Cconversion = Csample + Ccompare -- ± 0.6 -0.5 to +1.1 Integral Non-Linearity -- ± 0.9 ±1.1 Unit V pF k MHz -- cycles cycles LSB LSB Notes -- -- -- 2 -- 3 -- -- 4 4 i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 112 NXP Semiconductors Electrical characteristics Table 123. ADC electrical specifications (1VVREFH<VDD_ADC_1P8) (continued) Symbol Description Min Typ1 Max Unit Notes ENOB Effective Number of Bits -- -- -- -- 5,6,7 Avg = 1 9.5 9.7 -- Bits Avg = 2 9.9 10.1 -- Bits Avg = 16 10.8 11 -- Bits SINAD Signal to Noise plus Distortion SINAD=6.02 x ENOB + 1.76 dB -- EG EO IVDDA18 Gain error Offset error Supply Current -- 0.29 -- 0.01 -- 480 -- %FSV 8 -- %FSV 9 -- A 10 Iin,ext,leak External Channel Leakage Current -- 30 500 nA -- EIL Input leakage error RAS * Iin mV -- 1 Typical values assume VDD_ANA_1P8 = 1.8 V, Temp = 25 °C, fACLK = Max, unless otherwise stated. Typical values are for reference only. All values, including Min and Max, are derived from lab characterization and are not tested in production. 2 This resistance is external to the input pad. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 15 analog source resistance. The RAS/CAS (analog source capacitance) time constant should be kept to < 1 ns. 3 See Figure 61. 4 ADC conversion clock at max frequency and using linear histogram. 5 Input data used for test was 1 kHz sine wave. 6 Measured at VREFH = 1 V and pwrsel = 2. 7 ENOB can be lower than shown, if an ADC channel corrupts other ADC channels through capacitive coupling. This coupling may be dominated by board parasitics. Care must be taken not to corrupt the desired channel being measured. This coupling becomes worse at higher analog frequencies and with switching waveforms due to the harmonic content. 8 Error measured at fullscale at 1.0 V. 9 Error measured at zero scale at 0 V. 10 Power Configuration Select, PWRSEL, is set to 10 binary. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 113 Electrical characteristics The following figure shows a plot of the ADC sample time versus RAS. Figure 61. Sample time vs. RAS i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 114 NXP Semiconductors Boot mode configuration 5 Boot mode configuration This section provides information on boot mode configuration pins allocation and boot devices interfaces allocation. 5.1 Boot mode configuration inputs The following table lists boot option dedicated inputs. These inputs are sampled at reset and can be used to override fuse values, depending on the value of FORCE_BOOT_FROM_FUSE. After this fuse is blown, the Boot mode inputs are ignored by ROM; ROM receives 'boot mode' from the BT_MODE_FUSES fuse. The boot option inputs are in effect when BT_FUSE_SEL fuse is `0' (cleared, which is the case for an unblown fuse). For detailed boot mode options configured by the Boot mode pins, see the "System Boot, Fusemap, and eFuse" chapter of the device reference manual. Interface BOOT_MODE[0] BOOT_MODE[1] BOOT_MODE[2] BOOT_MODE[3] BOOT_MODE[4] BOOT_MODE[5] Table 124. Boot options and associated inputs used for Boot IP Instance Input Input Input Input Input Input Allocated Pads During Boot SCU_BOOT_MODE0 SCU_BOOT_MODE1 SCU_BOOT_MODE2 SCU_BOOT_MODE3 SCU_BOOT_MODE4 SCU_BOOT_MODE5 Comment Boot mode selection 5.2 Boot devices interfaces allocation The following table lists the interfaces that can be used by the boot process in accordance with the specific Boot mode configuration. The table also describes the interface's specific modes and IOMUXC allocation, which are configured during boot when appropriate. Interface MMC SD/MMC Table 125. Interface allocation during boot IP Instance Allocated Pads During Boot USDHC-0 USDHC-1 EMMC0_CLK, EMMC0_CMD, EMMC0_DATA0, EMMC0_DATA1, EMMC0_DATA2, EMMC0_DATA3, EMMC0_DATA4, EMMC0_DATA5, EMMC0_DATA6, EMMC0_DATA7, EMMC0_RESET_B 4 or 8 bit USDHC1_CLK, USDHC1_CMD, USDHC1_DATA0, USDHC1_DATA1, USDHC1_DATA2, USDHC1_DATA3, USDHC1_DATA4, USDHC1_DATA5, USDHC1_DATA6, USDHC1_DATA7, USDHC1_VSELECT, USDHC1_RESET_B 4 or 8 bit Comment i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 115 Boot mode configuration Table 125. Interface allocation during boot (continued) Interface SD QSPI NAND USB IP Instance Allocated Pads During Boot Comment USDHC-2 QSPI0 GPMI USB-OTG PHY USDHC2_CLK, USDHC2_CMD, 4 bit USDHC2_DATA0, USDHC2_DATA1, USDHC2_DATA2, USDHC2_DATA3, USDHC2_RESET_B, USDHC2_VSELECT, USDHC2_CD_B QSPI0A_DATA0, QSPI0A_DATA1, QSPI0A_DATA2, QSPI0A_DATA3, QSPI0A_DQS, QSPI0A_SS0_B, QSPI0A_SS1_B, QSPI0A_SCLK, QSPI0B_SCLK, QSPI0B_DATA0, QSPI0B_DATA1, QSPI0B_DATA2, QSPI0B_DATA3, QSPI0B_DQS, QSPI0B_SS0_B, QSPI0B_SS1_B 4, dual-4, or 8 bit During boot, QSPI0B can only be used in combination with QSPI0A, i.e. booting with 4-bit QSPI0B is not supported. EMMC0_CLK, EMMC0_CMD, EMMC0_DATA0, EMMC0_DATA1, EMMC0_DATA2, EMMC0_DATA3, EMMC0_DATA4, EMMC0_DATA5, EMMC0_DATA6, EMMC0_DATA7, EMMC0_STROBE, EMMC0_RESET_B,, USDHC1_DATA0, USDHC1_DATA1 USDHC1_DATA2, USDHC1_DATA3, USDHC1_DATA4, USDHC1_DATA5 USDHC1_DATA6, USDHC1_DATA7 USDHC1_STROBE 8 bit Boot from CS0 only, but will drive CS1to high when booting if specified in fuse, this is for Multi-CS NAND chip. · Single-ended DQS--use EMMC0_CMD · Single-ended RE--use USDHC1_DATA5 · Differential DQS-- · _N use USDHC1_DATA2 · _P use USDHC1_DATA3 · Differential RE-- · _N use USDHC1_DATA0 · _P use USDHC1_DATA1 USB_OTG1_VBUS, USB_OTG1_DP, -- USB_OTG1_DN, USB_OTG2_VBUS, USB_OTG2_DP, USB_OTG2_DN i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 116 NXP Semiconductors Package information and contact assignments 6 Package information and contact assignments This section contains package information and contact assignments for the following package(s): · FCPBGA, 29 x 29 mm, 0.75 mm pitch 6.1 FCPBGA, 29 x 29 mm, 0.75 mm pitch This section includes the following information for the 29 x 29 mm, 0.75 mm pitch package: · Mechanical package drawing · Ball map · Contact assignments i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 117 Package information and contact assignments 6.1.1 29 x 29 mm package case outline The following figure shows the top, bottom, and side views of the 29 × 29 mm package. Figure 62. 29 x 29 mm Package Top, Bottom, and Side Views i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 118 NXP Semiconductors Package information and contact assignments The notes in the following figure pertain to the preceding figure., "29 x 29 mm Package Top, Bottom, and Side Views." Figure 63. Notes on 29 x 29 mm Package Top, Bottom, and Side Views i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 119 Package information and contact assignments 6.1.2 29 x 29 mm, 0.75 mm pitch ball map The following page shows the 29 x 29 mm, 0.75 mm pitch ball map. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 120 NXP Semiconductors 29 x 29 mm, 0.75 pitch ballmap 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 A VSS_MAI N USDHC1_ RESET_B USDHC2_ VSELECT ENET0_MD C ENET1_RE FCLK_125 M_25M ENET1_MD C PCIE_CTR L0_WAKE _B PCIE_CTR L0_CLKRE Q_B PCIE_SAT A0_RX0_P PCIE1_RX 0_P VSS_MAI N PCIE_CTR L1_CLKRE Q_B PCIE_CTR L1_WAKE _B PCIE0_RX 0_P VSS_MAI N USB_SS3 _TX_P USB_OTG 2_VBUS USB_OTG 1_ID USB_OTG 1_VBUS ENET0_RG MII_TXC ENET0_RG MII_TXD0 ENET0_RG MII_TXD2 ENET0_RG MII_RXD0 ENET1_RG MII_TXD0 VSS_MAI N B USDHC1_ VSELECT VSS_MAI N USDHC2_ CD_B ENET0_RE FCLK_125 M_25M VSS_MAI N VSS_MAI N PCIE_SAT A0_TX0_P VSS_MAI N PCIE_SAT A0_RX0_ N PCIE1_RX 0_N PCIE1_TX0 _P PCIE0_TX0 _P VSS_MAI N PCIE0_RX 0_N USB_SS3 _TX_N USB_SS3 _RX_N VSS_MAI N USB_OTG 2_DP USB_OTG 1_DP ENET0_RG MII_TXD1 ENET0_RG MII_RXC VSS_MAI N ENET1_RG MII_TX_CT L ENET1_RG MII_RXC C VSS_MAI N FLEXCAN 2_RX FLEXCAN 0_RX USDHC2_ RESET_B VSS_MAI N VSS_MAI N ENET1_MD IO VSS_MAI N PCIE_SAT A0_TX0_N VSS_MAI N VSS_MAI N VSS_MAI N PCIE1_TX0 _N PCIE0_TX0 _N VSS_MAI N VSS_MAI N VSS_MAI N USB_SS3 _RX_P USB_OTG 2_DN USB_OTG 1_DN VSS_MAI N VSS_MAI N ENET0_RG MII_RXD2 ENET1_RG MII_TXD1 VSS_MAI N ENET1_RG MII_RXD1 VSS_MAI N D MLB_CLK VSS_MAI N USDHC2_ WP ENET0_MD IO QSPI1A_D ATA0 QSPI1A_D ATA1 VSS_MAI N VSS_MAI N PCIE_CTR L0_PERST _B PCIE_REX T VSS_MAI N VSS_MAI N VSS_MAI N MLB_SIG_ P MLB_CLK _P VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N ENET0_RG MII_TXD3 ENET0_RG MII_RXD1 ENET1_RG MII_TXC ENET1_RG MII_TXD3 ENET1_RG MII_RXD2 E MLB_SIG MLB_DAT A FLEXCAN 1_RX FLEXCAN 2_TX VSS_MAI N QSPI1A_D ATA3 QSPI1A_D ATA2 QSPI0A_S S0_B QSPI0A_S CLK VSS_MAI N VSS_MAI N PCIE_REF_ QR PCIE_SAT A_REFCL K100M_N USB_SS3 _REXT USB_OTG 2_REXT MLB_SIG_ N MLB_CLK _N MLB_DAT A_N USDHC1_ DATA0 USDHC1_ DATA2 ENET0_RG MII_TX_CT L ENET0_RG MII_RX_CT L ENET0_RG MII_RXD3 VSS_MAI N ENET1_RG MII_RX_CT L ENET1_RG MII_RXD0 ENET1_RG MII_RXD3 F VSS_MAI N VSS_MAI N USB_SS3 _TC2 QSPI1A_S CLK VSS_MAI N QSPI0A_D ATA1 QSPI0A_S S1_B QSPI0B_S CLK QSPI0B_D ATA3 QSPI0B_S S0_B VSS_MAI N PCIE_SAT A_REFCL K100M_P USB_HSIC 0_STROB E USB_OTG 2_ID VSS_MAI N MLB_DAT A_P VSS_MAI N USDHC1_ DATA1 USDHC1_ DATA3 USDHC1_ DATA6 VSS_MAI N USDHC2_ CLK VSS_MAI N VSS_MAI N G DDR_CH1 _DQ05 DDR_CH1 _DQ06 VSS_MAI N FLEXCAN 1_TX VSS_MAI N QSPI1A_S S1_B QSPI0A_D ATA0 VSS_MAI N QSPI0A_D QS QSPI0B_D ATA2 VSS_MAI N VSS_MAI N PCIE_CTR L1_PERST _B VSS_MAI N EMMC0_D ATA0 EMMC0_D ATA2 VSS_MAI N EMMC0_D ATA7 EMMC0_S TROBE VSS_MAI N USDHC1_ CMD USDHC1_ DATA5 USDHC2_ DATA1 ENET1_RG MII_TXD2 VSS_MAI N DDR_CH0 _DQ06 DDR_CH0 _DQ05 H DDR_CH1 _DM0 DDR_CH1 _DQ04 FLEXCAN 0_TX USB_SS3 _TC3 QSPI1A_D QS QSPI0A_D ATA2 QSPI0A_D ATA3 QSPI0B_D ATA0 QSPI0B_D ATA1 QSPI0B_D QS QSPI0B_S S1_B USB_HSIC 0_DATA EMMC0_C LK EMMC0_D ATA1 EMMC0_D ATA3 EMMC0_D ATA5 EMMC0_D ATA6 EMMC0_R ESET_B USDHC1_ DATA4 USDHC1_ DATA7 USDHC2_ CMD USDHC2_ DATA0 DDR_CH0 _DQ04 DDR_CH0 _DM0 J VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N USB_SS3 _TC0 QSPI1A_S S0_B VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N EMMC0_C MD VSS_MAI N VSS_MAI N EMMC0_D ATA4 VSS_MAI N VSS_MAI N USDHC1_ CLK VSS_MAI N USDHC1_ STROBE USDHC2_ DATA3 VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N K DDR_CH1 _DQS0_P DDR_CH1 _DQ09 DDR_CH1 _DQ03 VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N DDR_CH0 _DQ03 DDR_CH0 _DQ09 DDR_CH0 _DQS0_P L DDR_CH1 _DQS0_N DDR_CH1 _DQ11 DDR_CH1 _DQ08 DDR_CH1 _DQ02 USB_SS3 _TC1 VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N USDHC2_ DATA2 DDR_CH0 _DQ02 DDR_CH0 _DQ08 DDR_CH0 _DQ11 DDR_CH0 _DQS0_N M VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N N DDR_CH1 _DQS1_P DDR_CH1 _DQ10 DDR_CH1 _DQ13 DDR_CH1 _DM1 DDR_CH1 _DQ01 DDR_CH1 _DQ07 VSS_MAI N VDD_MLB _DIG_1P8 _3P3 VDD_FLE XCAN_1P 8_3P3 VDD_USB _SS3_TC_ 3P3 VDD_QSPI 1A_1P8_3 P3 VDD_ENE T_MDIO_1 P8_2P5_3 P3 VDD_QSPI 0_1P8_3P 3 PCIE_SAT A0_PHY_ PLL_REF_ RETURN VDD_PCIE _SATA0_ PLL_1P8 VDD_PCIE 1_PLL_1P 8 VDD_PCIE _SATA0_ 1P0 PCIE1_PH Y_PLL_RE F_RETURN VDD_PCIE 1_1P0 VDD_PCIE 0_1P0 VDD_PCIE 0_PLL_1P 8 PCIE0_PH Y_PLL_RE F_RETURN VDD_USB _SS3_LD O_1P0_C AP VDD_PCIE _LDO_1P0 _CAP VDD_USB _OTG1_1P 0 VDD_USB _OTG2_3P 3 VDD_USD HC1_1P8_ 3P3 VDD_USD HC2_1P8_ 3P3 VDD_USB _OTG2_1P 0 VDD_USB _OTG1_3P 3 VDD_EMM C0_1P8_3 P3 VDD_USD HC1_1P8_ 3P3 VDD_ENE T0_1P8_3 P3 VDD_ENE T0_1P8_3 P3 VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N DDR_CH0 _DQ07 DDR_CH0 _DQ01 DDR_CH0 _DM1 DDR_CH0 _DQ13 DDR_CH0 _DQ10 DDR_CH0 _DQS1_P P DDR_CH1 _DQS1_N DDR_CH1 _DQ14 DDR_CH1 _DQ15 DDR_CH1 _DQ12 DDR_CH1 _DQ00 VSS_MAI N VSS_MAI N DDR_CH0 _DQ00 DDR_CH0 _DQ12 DDR_CH0 _DQ15 DDR_CH0 _DQ14 DDR_CH0 _DQS1_N R VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N T DDR_CH1 _DCF09 DDR_CH1 _DCF10 DDR_CH1 _DCF08 DDR_CH1 _DCF13 DDR_CH1 _DTO1 VSS_MAI N U DDR_CH1 _DCF16 DDR_CH1 _DCF11 DDR_CH1 _DCF12 DDR_CH1 _DCF00 DDR_CH1 _DTO0 DDR_CH1 _VREF V VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N W DDR_CH1 _DCF14 DDR_CH1 _DCF07 DDR_CH1 _CK0_P DDR_CH1 _DCF01 DDR_CH1 _DCF06 DDR_CH1 _DCF04 Y DDR_CH1 _DCF15 DDR_CH1 _CK0_N DDR_CH1 _DCF02 DDR_CH1 _DCF03 DDR_CH1 _DCF05 VSS_MAI N AA VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N AB DDR_CH1 _DCF31 DDR_CH1 _CK1_N DDR_CH1 _DCF18 DDR_CH1 _DCF19 DDR_CH1 _DCF24 VSS_MAI N AC DDR_CH1 _DCF30 DDR_CH1 _DCF22 DDR_CH1 _CK1_P DDR_CH1 _DCF17 DDR_CH1 _DCF23 DDR_CH1 _DCF20 VSS_MAI N AD VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N AE DDR_CH1 _DCF32 DDR_CH1 _DCF27 DDR_CH1 _DCF29 DDR_CH1 _DCF26 DDR_CH1 _DCF21 VDD_DDR _CH1_VD DA_PLL_1 P8 VSS_MAI N AF DDR_CH1 _DCF25 DDR_CH1 _DCF28 DDR_CH1 _DCF33 DDR_CH1 _ATO DDR_CH1 _ZQ VSS_MAI N AG VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N AH DDR_CH1 _DQS2_N DDR_CH1 _DQ23 DDR_CH1 _DQ22 DDR_CH1 _DQ21 DDR_CH1 _DQ25 VSS_MAI N AJ DDR_CH1 _DQS2_P DDR_CH1 _DQ19 DDR_CH1 _DQ20 DDR_CH1 _DM2 DDR_CH1 _DQ24 DDR_CH1 _DQ30 VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VDD_DDR _CH1_VD DQ VSS_MAI N VDD_USD HC_VSEL ECT_1P8_ 3P3 VDD_MAI N VSS_MAI N VSS_MAI N VDD_PCIE _DIG_1P8 VDD_MAI N VSS_MAI N VDD_PCIE _IOB_1P8 VSS_MAI N VDD_MLB _1P8 VSS_MAI N VDD_ANA 1_1P8 VDD_PCIE _LDO_1P8 VDD_ANA 0_1P8 VDD_ANA 0_1P8 VSS_MAI N VDD_MAI N VSS_MAI N VDD_GPU 1 VSS_MAI N VDD_ENE T1_1P8_2 P5_3P3 VDD_DDR _CH0_VD DQ VDD_DDR _CH1_VD DQ VSS_MAI N VDD_GPU 0 VSS_MAI N VDD_MAI N VDD_USB _HSIC0_1 P2 VDD_USB _HSIC0_1 P8 VSS_MAI N VDD_MAI N VSS_MAI N VDD_GPU 1 VDD_DDR _CH0_VD DQ VDD_DDR _CH1_VD DQ VDD_MEM C VSS_MAI N VDD_GPU 0 VSS_MAI N VDD_MAI N VSS_MAI N VDD_MAI N VSS_MAI N VDD_GPU 1 VSS_MAI N VDD_MEM C VDD_DDR _CH0_VD DQ VDD_DDR _CH1_VD DQ VDD_GPU 0 VSS_MAI N VDD_GPU 0 VSS_MAI N VDD_MAI N VSS_MAI N VDD_MAI N VSS_MAI N VDD_GPU 1 VSS_MAI N VDD_DDR _CH0_VD DQ VDD_DDR _CH1_VD DQ VSS_MAI N VDD_GPU 0 VSS_MAI N VDD_MAI N VSS_MAI N VDD_MAI N VSS_MAI N VDD_MAI N VSS_MAI N VDD_GPU 1 VSS_MAI N VDD_DDR _CH0_VD DQ VDD_DDR _CH1_VD DQ_CKE VSS_MAI N VDD_GPU 0 VSS_MAI N VDD_MAI N VSS_MAI N VDD_MAI N VSS_MAI N VDD_GPU 1 VSS_MAI N VDD_GPU 1 VDD_DDR _CH0_VD DQ_CKE VDD_DDR _CH1_VD DQ_CKE VDD_MEM C VSS_MAI N VDD_GPU 0 VSS_MAI N VDD_MAI N VSS_MAI N VDD_MAI N VSS_MAI N VDD_GPU 1 VSS_MAI N VDD_MEM C VDD_DDR _CH0_VD DQ_CKE VDD_DDR _CH1_VD DQ_CKE VDD_GPU 0 VSS_MAI N VDD_GPU 0 VSS_MAI N VDD_MAI N VSS_MAI N VDD_MAI N VSS_MAI N VDD_GPU 1 VSS_MAI N VDD_DDR _CH0_VD DQ_CKE VDD_DDR _CH1_VD DQ VSS_MAI N VDD_GPU 0 VSS_MAI N VDD_MAI N VSS_MAI N VDD_MAI N VSS_MAI N VDD_MAI N VSS_MAI N VDD_GPU 1 VSS_MAI N VDD_DDR _CH0_VD DQ VDD_DDR _CH1_VD DQ VSS_MAI N VDD_MAI N VSS_MAI N VDD_MAI N VSS_MAI N VDD_MAI N VSS_MAI N VDD_MAI N VSS_MAI N VDD_MAI N VDD_DDR _CH0_VD DQ VDD_DDR _CH1_VD DQ VDD_MEM C VSS_MAI N VDD_MAI N VSS_MAI N VDD_MEM C VSS_MAI N VDD_MEM C VSS_MAI N VDD_MAI N VSS_MAI N VDD_MEM C VDD_DDR _CH0_VD DQ VDD_DDR _CH1_VD DQ VDD_MAI N VSS_MAI N VDD_MEM C VSS_MAI N VDD_MEM C VSS_MAI N VDD_MEM C VSS_MAI N VDD_MAI N VSS_MAI N VDD_DDR _CH0_VD DQ VDD_DDR _CH1_VD DQ VSS_MAI N VDD_MAI N VSS_MAI N VDD_MEM C VSS_MAI N VDD_MEM C VSS_MAI N VDD_MAI N VSS_MAI N VDD_ANA 2_1P8 VSS_MAI N VDD_DDR _CH0_VD DQ VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N DDR_CH0 _DTO1 DDR_CH0 _DCF13 DDR_CH0 _DCF08 DDR_CH0 _DCF10 DDR_CH0 _DCF09 DDR_CH0 _VREF DDR_CH0 _DTO0 DDR_CH0 _DCF00 DDR_CH0 _DCF12 DDR_CH0 _DCF11 DDR_CH0 _DCF16 VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N DDR_CH0 _DCF04 DDR_CH0 _DCF06 DDR_CH0 _DCF01 DDR_CH0 _CK0_P DDR_CH0 _DCF07 DDR_CH0 _DCF14 VSS_MAI N DDR_CH0 _DCF05 DDR_CH0 _DCF03 DDR_CH0 _DCF02 DDR_CH0 _CK0_N DDR_CH0 _DCF15 VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N DDR_CH0 _DCF24 DDR_CH0 _DCF19 DDR_CH0 _DCF18 DDR_CH0 _CK1_N DDR_CH0 _DCF31 VSS_MAI N DDR_CH0 _DCF20 DDR_CH0 _DCF23 DDR_CH0 _DCF17 DDR_CH0 _CK1_P DDR_CH0 _DCF22 DDR_CH0 _DCF30 VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VDD_DDR _CH0_VD DA_PLL_1 P8 DDR_CH0 _DCF21 DDR_CH0 _DCF26 DDR_CH0 _DCF29 DDR_CH0 _DCF27 DDR_CH0 _DCF32 VSS_MAI N DDR_CH0 _ZQ DDR_CH0 _ATO DDR_CH0 _DCF33 DDR_CH0 _DCF28 DDR_CH0 _DCF25 VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N DDR_CH0 _DQ25 DDR_CH0 _DQ21 DDR_CH0 _DQ22 DDR_CH0 _DQ23 DDR_CH0 _DQS2_N VSS_MAI N DDR_CH0 _DQ30 DDR_CH0 _DQ24 DDR_CH0 _DM2 DDR_CH0 _DQ20 DDR_CH0 _DQ19 DDR_CH0 _DQS2_P AK VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N AL DDR_CH1 _DQS3_N DDR_CH1 _DQ18 DDR_CH1 _DQ17 DDR_CH1 _DQ27 ADC_IN6 VREFH_A DC VSS_MAI N AM DDR_CH1 _DQS3_P DDR_CH1 _DQ16 DDR_CH1 _DQ26 VSS_MAI N VREFL_A DC VSS_MAI N AN VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N ADC_IN4 ADC_IN1 VSS_MAI N AP DDR_CH1 _DM3 DDR_CH1 _DQ29 ADC_IN7 ADC_IN2 ADC_IN0 VSS_MAI N AR DDR_CH1 _DQ28 DDR_CH1 _DQ31 VSS_MAI N ADC_IN5 ADC_IN3 VSS_MAI N VDD_ADC _DIG_1P8 VSS_MAI N VDD_ANA 3_1P8 VSS_MAI N VDD_MEM C VSS_MAI N VDD_MEM C VSS_MAI N VDD_MAI N VSS_MAI N VDD_MAI N VSS_MAI N VDD_ADC _1P8 VDD_MAI N VDD_SPI_ SAI_1P8_ 3P3 VDD_SPI_ SAI_1P8_ 3P3 VSS_MAI N VDD_MAI N VSS_MAI N VDD_MAI N VSS_MAI N VDD_MAI N VDD_A53 VSS_MAI N VSS_MAI N VDD_A53 VSS_MAI N VDD_MAI N VDD_A53 VSS_MAI N VSS_MAI N VDD_A72 VSS_MAI N VDD_A72 VSS_MAI N VDD_A72 VSS_MAI N VDD_A72 VSS_MAI N VDD_A72 VSS_MAI N VDD_A72 VSS_MAI N VDD_A72 VSS_MAI N VDD_MAI N VDD_M4_ GPT_UAR T_1P8_3P 3 VDD_M4_ GPT_UAR T_1P8_3P 3 VDD_CP_ 1P8 VDD_SCU _1P8 VDD_ESAI 0_MCLK_1 P8_3P3 VSS_MAI N VDD_MAI N VSS_MAI N VDD_A53 VSS_MAI N VDD_A72 VSS_MAI N VDD_A72 VSS_MAI N VDD_MAI N VDD_SCU _1P8 VDD_ESAI 0_MCLK_1 P8_3P3 VDD_MAI N VSS_MAI N VDD_A53 VSS_MAI N VDD_A53 VSS_MAI N VDD_A72 VSS_MAI N VDD_A72 VSS_MAI N VDD_MAI N VDD_SCU _ANA_1P 8 VDD_SIM0 _1P8_3P3 VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N SIM0_PD SIM0_CLK DDR_CH0 _DQ27 DDR_CH0 _DQ17 DDR_CH0 _DQ18 DDR_CH0 _DQS3_N VSS_MAI N M40_I2C0 _SCL VSS_MAI N DDR_CH0 _DQ26 DDR_CH0 _DQ16 DDR_CH0 _DQS3_P VSS_MAI N VSS_MAI N SIM0_IO VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VDD_M1P 8_CAP M41_GPIO 0_00 SIM0_GPI O0_00 SIM0_RST DDR_CH0 _DQ29 DDR_CH0 _DM3 UART1_R TS_B M41_I2C0 _SCL M40_GPIO 0_00 VSS_MAI N DDR_CH0 _DQ31 DDR_CH0 _DQ28 AT VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N ESAI1_TX 5_RX0 VSS_MAI N AU SAI1_TXD SAI1_RXF S SAI1_TXC ESAI0_TX 5_RX0 ESAI0_TX 2_RX3 ESAI1_TX 2_RX3 AV SAI1_TXF S SAI1_RXD SAI1_RXC ESAI0_TX 4_RX1 ESAI1_TX 3_RX2 VSS_MAI N AW SPI2_CS0 VSS_MAI N SPI2_SCK VSS_MAI N ESAI0_FS R VSS_MAI N VSS_MAI N VDD_MAI N VSS_MAI N VDD_A53 VSS_MAI N VDD_MAI N VSS_MAI N VDD_MAI N VSS_MAI N VDD_A72 VSS_MAI N VDD_SNV S_4P2 VDD_ESAI 1_SPDIF_ SPI_1P8_3 P3 VSS_MAI N VDD_HDMI _TX0_1P0 VDD_HDMI _RX0_LD O0_1P0_C AP VDD_HDMI _RX0_LD O1_1P0_C AP VDD_MIPI_ CSI1_1P8 VSS_MAI N VDD_HDMI _RX0_1P8 VDD_HDMI _RX0_VH _RX_3P3 VDD_MIPI_ CSI_DIG_1 P8 VDD_MIPI_ CSI0_1P8 VDD_MIPI_ DSI_DIG_1 P8_3P3 VDD_MIPI_ DSI0_1P0 VSS_MAI N VDD_MIPI_ CSI0_1P0 VDD_MIPI_ DSI1_1P0 VDD_MIPI_ DSI1_1P8 VSS_MAI N VDD_LVD S_DIG_1P 8_3P3 VDD_LVD S0_1P8 VDD_MAI N VDD_LVD S0_1P0 VSS_MAI N VSS_MAI N VDD_SCU _XTAL_1P 8 VDD_HDMI _TX0_LDO _1P0_CAP VDD_HDMI _TX0_1P8 VSS_MAI N VDD_HDMI _TX0_DIG _3P3 VSS_MAI N VDD_MIPI_ CSI1_1P0 VDD_MIPI_ DSI1_PLL_ 1P0 VDD_MIPI_ DSI0_PLL_ 1P0 VDD_MIPI_ DSI0_1P8 VDD_LVD S1_1P8 VDD_LVD S1_1P0 VSS_MAI N VDD_SNV S_LDO_1P 8_CAP VSS_MAI N UART1_R X VSS_MAI N SIM0_PO WER_EN VSS_MAI N VSS_MAI N SCU_GPIO 0_00 UART0_R TS_B M41_GPIO 0_01 M41_I2C0 _SDA M40_I2C0 _SDA M40_GPIO 0_01 VSS_MAI N SCU_GPIO 0_01 UART1_C TS_B UART0_T X UART0_R X GPT0_CA PTURE VSS_MAI N SCU_GPIO 0_02 VSS_MAI N UART0_C TS_B VSS_MAI N GPT0_CO MPARE AY SPI2_CS1 SPI2_SDI SPI0_SDO ESAI0_SC KT ESAI1_SC KT ESAI1_TX 4_RX1 SCU_BOO T_MODE4 SCU_GPIO 0_05 PMIC_I2C_ SCL UART1_T X GPT1_CA PTURE GPT0_CLK BA SPI2_SDO SPI0_CS1 SPI0_SDI ESAI0_TX 1 ESAI0_TX 0 ESAI1_TX 1 VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N SCU_BOO T_MODE3 VSS_MAI N SCU_PMIC _STANDB Y JTAG_TM S GPT1_CO MPARE GPT1_CLK BB VSS_MAI N SPI0_SCK VSS_MAI N ESAI0_SC KR VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N SCU_BOO T_MODE0 SCU_GPIO 0_03 VSS_MAI N SCU_WDO G_OUT VSS_MAI N BC SPI0_CS0 MCLK_IN0 ESAI0_TX 3_RX2 SPDIF0_R X SPDIF0_T X VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N SCU_BOO T_MODE1 SCU_GPIO 0_04 TEST_MO DE_SELEC T JTAG_TC K SCU_PMIC _MEMC_O N BD ANA_TES T_OUT1_N MCLK_OU T0 SPDIF0_E XT_CLK SPI3_CS1 ESAI1_SC KR VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N MIPI_DSI0_ GPIO0_01 MIPI_DSI0_ GPIO0_00 LVDS1_I2 C1_SCL LVDS1_G PIO00 LVDS0_I2 C0_SDA LVDS0_I2 C0_SCL LVDS0_G PIO01 SNVS_TA MPER_OU T1 SNVS_TA MPER_OU T0 VSS_MAI N VSS_MAI N JTAG_TD O BE ANA_TES T_OUT1_P VSS_MAI N SPI3_SDI VSS_MAI N VSS_MAI N ESAI1_FS R HDMI_RX0 _DDC_SD A MIPI_CSI1_ I2C0_SDA MIPI_CSI0_ DATA3_N MIPI_CSI0_ DATA1_N MIPI_CSI0_ CLK_N MIPI_CSI0_ DATA0_N MIPI_CSI0_ DATA2_N MIPI_DSI1_ I2C0_SCL MIPI_DSI0_ I2C0_SCL MIPI_DSI0_ I2C0_SDA LVDS1_I2 C0_SDA LVDS0_I2 C1_SDA LVDS0_I2 C1_SCL LVDS0_G PIO00 SNVS_TA MPER_IN0 SNVS_TA MPER_IN1 VSS_MAI N ON_OFF_ BUTTON POR_B JTAG_TDI JTAG_TR ST_B BF SPI3_SDO VSS_MAI N SPI3_SCK ESAI1_TX 0 ESAI1_FS T HDMI_RX0 _HPD MIPI_CSI0_ DATA3_P MIPI_CSI0_ DATA1_P MIPI_CSI0_ CLK_P MIPI_CSI0_ DATA0_P MIPI_CSI0_ DATA2_P VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N SCU_GPIO 0_07 PMIC_EAR LY_WARN ING VSS_MAI N HDMI_TX0 BG _DDC_SC L HDMI_TX0 _AUX_N SPI3_CS0 VSS_MAI N ESAI0_FS T VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N MIPI_DSI1_ I2C0_SDA MIPI_DSI1_ DATA3_P MIPI_DSI1_ DATA1_P MIPI_DSI1_ CLK_P MIPI_DSI1_ DATA0_P MIPI_DSI1_ DATA2_P LVDS0_C H1_TX3_N LVDS0_C H1_TX2_N LVDS0_C H1_TX1_N LVDS0_C H1_TX0_N LVDS0_C H1_CLK_N VSS_MAI N SCU_GPIO 0_06 PMIC_I2C_ SDA ANA_TES T_OUT0_P BH HDMI_TX0 _AUX_P VSS_MAI N HDMI_TX0 _HPD HDMI_RX0 _DDC_SC L MIPI_CSI1_ DATA3_N MIPI_CSI1_ DATA1_N MIPI_CSI1_ CLK_N MIPI_CSI1_ DATA0_N MIPI_CSI1_ DATA2_N VSS_MAI N MIPI_CSI0_ I2C0_SCL MIPI_DSI1_ DATA3_N MIPI_DSI1_ DATA1_N MIPI_DSI1_ CLK_N MIPI_DSI1_ DATA0_N MIPI_DSI1_ DATA2_N LVDS1_G PIO01 LVDS0_C H1_TX3_P LVDS0_C H1_TX2_P LVDS0_C H1_TX1_P LVDS0_C H1_TX0_P LVDS0_C H1_CLK_P PMIC_INT_ B ANA_TES T_OUT0_N BJ HDMI_TX0 _CEC VSS_MAI N VSS_MAI N HDMI_TX0 _REXT HDMI_RX0 _CEC HDMI_RX0 _REXT MIPI_CSI1_ DATA3_P MIPI_CSI1_ DATA1_P MIPI_CSI1_ CLK_P MIPI_CSI1_ DATA0_P MIPI_CSI1_ DATA2_P MIPI_CSI0_ MCLK_OU T VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N SCU_BOO T_MODE2 HDMI_TX0 BK _CLK_EDP 3_N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N VSS_MAI N MIPI_DSI1_ GPIO0_01 MIPI_DSI0_ DATA1_P MIPI_DSI0_ DATA0_P LVDS1_C H1_TX3_N LVDS1_C H1_TX1_N LVDS1_C H1_CLK_N LVDS1_C H0_CLK_N LVDS1_C H0_TX1_N LVDS1_C H0_TX3_N LVDS0_C H0_TX0_N LVDS0_C H0_TX2_N VSS_MAI N VSS_SCU _XTAL SCU_BOO T_MODE5 BL VSS_MAI N HDMI_TX0 _CLK_EDP 3_P HDMI_TX0 _DATA0_ EDP2_P HDMI_TX0 _DATA1_ EDP1_P HDMI_TX0 _DATA2_ EDP0_P HDMI_RX0 _CLK_N HDMI_RX0 _ARC_N HDMI_RX0 _DATA0_ N HDMI_RX0 _DATA1_ N HDMI_RX0 _DATA2_ N VSS_MAI N MIPI_CSI0_ GPIO0_00 MIPI_DSI0_ DATA3_P MIPI_DSI0_ CLK_P MIPI_DSI0_ DATA2_P LVDS1_C H1_TX2_N LVDS1_C H1_TX0_N LVDS1_I2 C0_SCL LVDS1_C H0_TX0_N LVDS1_C H0_TX2_N LVDS0_C H0_CLK_N LVDS0_C H0_TX1_N LVDS0_C H0_TX3_N RTC_XTA LO XTALO PMIC_ON_ REQ VSS_MAI N BM HDMI_TX0 _DATA0_ EDP2_N HDMI_TX0 _DATA1_ EDP1_N HDMI_TX0 _DATA2_ EDP0_N VSS_MAI N HDMI_RX0 _CLK_P HDMI_RX0 _ARC_P HDMI_RX0 _DATA0_ P HDMI_RX0 _DATA1_ P HDMI_RX0 _DATA2_ P MIPI_CSI0_ GPIO0_01 MIPI_DSI1_ GPIO0_00 MIPI_DSI0_ DATA1_N MIPI_DSI0_ DATA0_N LVDS1_C H1_TX3_P LVDS1_C H1_TX1_P LVDS1_C H1_CLK_P LVDS1_C H0_CLK_P LVDS1_C H0_TX1_P LVDS1_C H0_TX3_P LVDS0_C H0_TX0_P LVDS0_C H0_TX2_P VSS_MAI N VSS_SCU _XTAL VSS_SCU _XTAL BN VSS_MAI N HDMI_TX0 _DDC_SD A HDMI_TX0 _TS_SDA HDMI_TX0 _TS_SCL HDMI_RX0 _MON_5V MIPI_CSI1_ GPIO0_01 MIPI_CSI1_ GPIO0_00 MIPI_CSI1_ I2C0_SCL MIPI_CSI0_ I2C0_SDA VSS_MAI N MIPI_CSI1_ MCLK_OU T MIPI_DSI0_ DATA3_N MIPI_DSI0_ CLK_N MIPI_DSI0_ DATA2_N LVDS1_C H1_TX2_P LVDS1_C H1_TX0_P LVDS1_I2 C1_SDA LVDS1_C H0_TX0_P LVDS1_C H0_TX2_P LVDS0_C H0_CLK_P LVDS0_C H0_TX1_P LVDS0_C H0_TX3_P RTC_XTA LI XTALI VSS_SCU _XTAL i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 121 Package information and contact assignments 6.1.3 29 x 29 mm power supplies and functional contact assignments The following table shows power supplies contact assignments for the 29 × 29 mm package. Table 126. 29 x 29 mm power supplies contact assignments Power rail VDD_A53 VDD_A72 VDD_ADC_1P8 VDD_ADC_DIG_1P8 VDD_ANA0_1P8 VDD_ANA1_1P8 VDD_ANA2_1P8 VDD_ANA3_1P8 VDD_CP_1P8 VDD_DDR_CH0_VDDA_PLL_1P8 VDD_DDR_CH0_VDDQ VDD_DDR_CH0_VDDQ_CKE VDD_DDR_CH1_VDDA_PLL_1P8 VDD_DDR_CH1_VDDQ VDD_DDR_CH1_VDDQ_CKE VDD_EMMC0_1P8_3P3 VDD_ENET_MDIO_1P8_3P3 VDD_ENET0_1P8_3P3 VDD_ENET1_1P8_2P5_3P3 VDD_ESAI0_MCLK_1P8_3P3 VDD_ESAI1_SPDIF_SPI_1P8_3P3 VDD_FLEXCAN_1P8_3P3 VDD_GPU0 VDD_GPU1 VDD_HDMI_RX0_LDO0_1P0_CAP1 VDD_HDMI_RX0_LDO1_1P0_CAP1 VDD_HDMI_RX0_VH_RX_3P31 VDD_HDMI_TX0_1P0 VDD_HDMI_TX0_1P8 Ball reference AM22, AM26, AN23, AP24, AR21, AR25, AT22 AL29, AL33, AM30, AM34, AN27, AN31, AN35, AP28, AP32, AR29, AR33, AT34 AL15 AK16 U29, U31 U25 AJ35 AK20 AN37 AE43 AA39, AE39, AF38, AG39, AH38, AJ39, U39, V38, W39, Y38 AB38, AC39, AD38 AE11 AA15, AE15, AF16, AG15, AH16, AJ15, U15, V16, W15, Y16 AB16, AC15, AD16 N35 N17 M40, N39 T38 AP16, AR15 AU15 N15 AA19, AB20, AC21, AD18, AD22, AE19, V20, W21, Y18, Y22 AA35, AB32, AB36, AC33, AD34, AE35, U35, V36, W33, Y34 AU19 AU21 AV20 AV16 AW17 i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 122 NXP Semiconductors Package information and contact assignments Table 126. 29 x 29 mm power supplies contact assignments (continued) Power rail VDD_HDMI_TX0_DIG_3P3 VDD_HDMI_TX0_LDO_1P0_CAP VDD_LVDS_DIG_1P8_3P3 VDD_LVDS0_1P0 VDD_LVDS0_1P8 VDD_LVDS1_1P0 VDD_LVDS1_1P8 VDD_M1P8_CAP VDD_M4_GPT_UART_1P8_3P3 VDD_MAIN VDD_MEMC VDD_MIPI_CSI_DIG_1P8 VDD_MIPI_CSI0_1P0 VDD_MIPI_CSI0_1P8 VDD_MIPI_CSI1_1P0 VDD_MIPI_CSI1_1P8 VDD_MIPI_DSI_DIG_1P8_3P3 VDD_MIPI_DSI0_1P0 VDD_MIPI_DSI0_1P8 VDD_MIPI_DSI0_PLL_1P0 VDD_MIPI_DSI1_1P0 VDD_MIPI_DSI1_1P8 VDD_MIPI_DSI1_PLL_1P0 VDD_MLB_1P82 VDD_MLB_DIG_1P8_3P33 VDD_PCIE_DIG_1P8_3P3 VDD_PCIE_IOB_1P8 VDD_PCIE_LDO_1P0_CAP VDD_PCIE_LDO_1P8 VDD_PCIE_SATA0_1P01 Ball reference AW21 AW15 AV32 AV36 AV34 AW35 AW33 AP42 AL39, AM38 AA23, AA27, AA31, AB24, AB28, AC25, AC29, AD26, AD30, AE23, AE27, AE31, AF20, AF24, AF28, AF32, AF36, AG21, AG33, AH18, AH34, AJ19, AJ31, AK32, AK36, AL17, AL21, AL25, AL37, AM18, AN19, AP20, AP36, AR17, AR37, AT18, AT26, AT30, AU35, T34, U19, U23, V24, V32, W25, W29, Y26, Y30 AC17, AC37, AG17, AG25, AG29, AG37, AH22, AH26, AH30, AJ23, AJ27, AK24, AK28, W17, W37 AV22 AV26 AV24 AW25 AU23 AU27 AU29 AW31 AW29 AV28 AV30 AW27 T30 M14 T22 T26 N29 U27 M24 i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 123 Package information and contact assignments Table 126. 29 x 29 mm power supplies contact assignments (continued) Power rail VDD_PCIE_SATA0_PLL_1P81 VDD_PCIE0_1P0 VDD_PCIE0_PLL_1P8 VDD_PCIE1_1P0 VDD_PCIE1_PLL_1P8 VDD_QSPI0_1P8_3P3 VDD_QSPI1A_1P8_3P3 VDD_SCU_1P8 VDD_SCU_ANA_1P8 VDD_SCU_XTAL_1P8 VDD_SIM0_1P8_3P3 VDD_SNVS_4P2 VDD_SNVS_LDO_1P8_CAP VDD_SPI_SAI_1P8_3P3 VDD_USB_HSIC0_1P2 VDD_USB_HSIC0_1P8 VDD_USB_OTG1_1P0 VDD_USB_OTG1_3P3 VDD_USB_OTG2_1P0 VDD_USB_OTG2_3P3 VDD_USB_SS3_LDO_1P0_CAP VDD_USB_SS3_TC_3P3 VDD_USDHC_VSELECT_1P8_3P3 VDD_USDHC1_1P8_3P3 VDD_USDHC2_1P8_3P3 VREFH_ADC VREFL_ADC Ball reference N21 M26 N27 N25 M22 N19 M18 AN39, AP38 AR39 AU39 AK42 AT38 AW39 AM16, AN15 V26 V28 M32 N33 N31 M34 M30 M16 T18 M36, N37 M38 AL11 AM10 i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 124 NXP Semiconductors Package information and contact assignments Table 126. 29 x 29 mm power supplies contact assignments (continued) Power rail Ball reference VSS_MAIN A23, A3, A31, A51, AA1, AA11, AA13, AA17, AA21, AA25, AA29, AA3, AA33, AA37, AA41, AA43, AA45, AA47, AA49, AA5, AA51, AA53, AA7, AA9, AB12, AB18, AB22, AB26, AB30, AB34, AB42, AC13, AC19, AC23, AC27, AC31, AC35, AC41, AD10, AD12, AD2, AD20, AD24, AD28, AD32, AD36, AD4, AD42, AD44, AD46, AD48, AD50, AD52, AD6, AD8, AE13, AE17, AE21, AE25, AE29, AE33, AE37, AE41, AF12, AF18, AF22, AF26, AF30, AF34, AF42, AG1, AG11, AG13, AG19, AG23, AG27, AG3, AG31, AG35, AG41, AG43, AG45, AG47, AG49, AG5, AG51, AG53, AG7, AG9, AH12, AH20, AH24, AH28, AH32, AH36, AH42, AJ13, AJ17, AJ21, AJ25, AJ29, AJ33, AJ37, AJ41, AK10, AK12, AK18, AK2, AK22, AK26, AK30, AK34, AK38, AK4, AK44, AK46, AK48, AK50, AK52, AK6, AK8, AL13, AL19, AL23, AL27, AL31, AL35, AL41, AM12, AM20, AM24, AM28, AM32, AM36, AM42, AM46, AM8, AN1, AN13, AN17, AN21, AN25, AN29, AN3, AN33, AN41, AN43, AN47, AN49, AN5, AN51, AN53, AN7, AP12, AP18, AP22, AP26, AP30, AP34, AR11, AR19, AR23, AR27, AR31, AR35, AR49, AR5, AT12, AT16, AT2, AT20, AT24, AT28, AT32, AT36, AT4, AT42, AT46, AT50, AT52, AT6, AT8, AU17, AU25, AU31, AU33, AU37, AV12, AV38, AV42, AW11, AW19, AW23, AW3, AW37, AW43, AW47, AW51, AW7, B12, B14, B18, B28, B36, B46, B6, BA13, BA15, BA17, BA19, BA21, BA23, BA25, BA27, BA29, BA31, BA33, BA35, BA37, BA39, BA41, BA45, BB10, BB14, BB16, BB18, BB2, BB20, BB22, BB24, BB26, BB28, BB30, BB32, BB34, BB36, BB38, BB40, BB48, BB52, BB6, BC11, BC13, BC15, BC17, BC19, BC21, BC23, BC25, BC27, BC29, BC31, BC33, BC35, BC37, BC39, BC41, BC43, BD14, BD16, BD18, BD20, BD22, BD24, BD26, BD48, BD50, BE3, BE45, BE7, BE9, BF26, BF28, BF30, BF32, BF34, BF36, BF38, BF4, BF40, BF42, BF44, BF52, BG11, BG13, BG15, BG17, BG19, BG21, BG23, BG47, BG7, BH22, BH4, BJ25, BJ27, BJ29, BJ3, BJ31, BJ33, BJ35, BJ37, BJ39, BJ41, BJ43, BJ45, BJ47, BJ49, BJ5, BJ51, BK10, BK12, BK14, BK16, BK18, BK20, BK22, BK46, BK6, BK8, BL1, BL21, BL53, BM10, BM46, BN21, BN3, C1, C11, C15, C19, C21, C23, C29, C31, C33, C41, C43, C49, C53, C9, D16, D18, D24, D26, D28, D34, D36, D38, D40, D6, E19, E21, E47, E9, F12, F2, F24, F32, F36, F4, F44, F50, F52, G15, G21, G23, G27, G33, G39, G49, G5, G9, J1, J13, J15, J17, J19, J21, J23, J25, J29, J3, J31, J35, J37, J41, J47, J49, J5, J51, J53, J7, K12, K14, K16, K18, K20, K22, K24, K26, K28, K30, K32, K34, K36, K38, K40, K42, K46, K8, L11, L13, L15, L17, L19, L21, L23, L25, L27, L29, L31, L33, L35, L37, L39, L41, L43, M10, M2, M4, M44, M46, M48, M50, M52, M6, M8, N13, N41, P12, P42, R1, R11, R15, R17, R19, R21, R23, R25, R27, R29, R3, R31, R33, R35, R37, R39, R43, R45, R47, R49, R5, R51, R53, R7, R9, T12, T16, T20, T24, T28, T32, T36, T42, U17, U21, U33, U37, V10, V12, V18, V2, V22, V30, V34, V4, V42, V44, V46, V48, V50, V52, V6, V8, W19, W23, W27, W31, W35, Y12, Y20, Y24, Y28, Y32, Y36, Y42 VSS_SCU_XTAL BK48, BM48, BM50, BN51 1 HDMI-RX is not currently supported, the related power and signal connections are provided for future use when it is expected HDMI-RX support will be enabled. 2 MLB is not supported on this product. The MLB power rail must be tied to the voltage specified in Table 8 or may be terminated, per the Hardware Developer's Guide power supplies of unused functions. 3 MLB is not supported on this product. This MLB power rail must be tied to the voltage specified in Table 8 if other I/O functions are used, as determined by IOMUX selection. Alternately, terminate the MLB supply, per the Hardware Developer's Guide power supplies of unused functions. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 125 Package information and contact assignments The following table shows functional contact assignments for the 29 × 29 mm package. Ball AP10 AN11 AP8 AR9 AN9 AR7 AL9 AP6 BH52 BG53 BD2 BE1 H28 J27 G29 H30 G31 H32 J33 H34 H36 G35 H38 G37 A9 D10 B10 E43 B44 A47 Table 127. 29 × 29 mm functional contact assignments Ball Name ADC_IN0 ADC_IN1 ADC_IN2 ADC_IN3 ADC_IN4 ADC_IN5 ADC_IN6 ADC_IN7 ANA_TEST_OUT0_N ANA_TEST_OUT0_P ANA_TEST_OUT1_N ANA_TEST_OUT1_P EMMC0_CLK EMMC0_CMD EMMC0_DATA0 EMMC0_DATA1 EMMC0_DATA2 EMMC0_DATA3 EMMC0_DATA4 EMMC0_DATA5 EMMC0_DATA6 EMMC0_DATA7 EMMC0_RESET_B EMMC0_STROBE ENET0_MDC ENET0_MDIO ENET0_REFCLK_125M_25M ENET0_RGMII_RX_CTL ENET0_RGMII_RXC ENET0_RGMII_RXD0 Power Domain VDD_ADC_3P3 VDD_SCU_ANA_1P8 VDD_SCU_ANA_1P8 Ball Type1 Default mode GPIO ALT0 ANA Reset Condition Default function ADC_IN0 ADC_IN1 ADC_IN2 ADC_IN3 ADC_IN4 ADC_IN5 ADC_IN6 ADC_IN7 NXP Internal Use Only (Leave Unconnected) VDD_EMMC0_1P8_3P3 VDD_ENET_MDIO_1P8_3P3 VDD_ENET0_1P8_3P3 FASTD ALT1 ALT0 GPIO ALT3 FASTD ALT0 GPIO ALT3 ALT0 ALT3 FASTD ALT0 NAND_READY_B EMMC0_CMD EMMC0_DATA0 EMMC0_DATA1 EMMC0_DATA2 EMMC0_DATA3 EMMC0_DATA4 EMMC0_DATA5 EMMC0_DATA6 EMMC0_DATA7 LSIO.GPIO5.IO13 EMMC0_STROBE LSIO.GPIO4.IO14 ENET0_MDIO LSIO.GPIO4.IO15 ENET0_RGMII_RX_CTL ENET0_RGMII_RXC ENET0_RGMII_RXD0 State2 PD PU PD PU PD PD PU PD PD i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 126 NXP Semiconductors Ball D44 C45 E45 E41 A41 A43 B42 A45 D42 A13 C13 A11 E49 B50 E51 C51 D52 E53 B48 D46 A49 C47 G47 D48 AW9 BG9 BB8 AY8 BA9 BA7 AU9 BC5 Package information and contact assignments Table 127. 29 × 29 mm functional contact assignments (continued) Ball Name ENET0_RGMII_RXD1 ENET0_RGMII_RXD2 ENET0_RGMII_RXD3 ENET0_RGMII_TX_CTL ENET0_RGMII_TXC ENET0_RGMII_TXD0 ENET0_RGMII_TXD1 ENET0_RGMII_TXD2 ENET0_RGMII_TXD3 ENET1_MDC ENET1_MDIO ENET1_REFCLK_125M_25M ENET1_RGMII_RX_CTL ENET1_RGMII_RXC ENET1_RGMII_RXD0 ENET1_RGMII_RXD1 ENET1_RGMII_RXD2 ENET1_RGMII_RXD3 ENET1_RGMII_TX_CTL ENET1_RGMII_TXC ENET1_RGMII_TXD0 ENET1_RGMII_TXD1 ENET1_RGMII_TXD2 ENET1_RGMII_TXD3 ESAI0_FSR ESAI0_FST ESAI0_SCKR ESAI0_SCKT ESAI0_TX0 ESAI0_TX1 ESAI0_TX2_RX3 ESAI0_TX3_RX2 Power Domain VDD_ENET0_1P8_3P3 VDD_ENET_MDIO_1P8_3P3 VDD_ENET1_1P8_2P5_3P3 VDD_ESAI0_MCLK_1P8_3P3 Ball Type1 Default mode FASTD ALT0 ALT3 GPIO ALT3 ALT0 ALT3 FASTD ALT0 ALT3 GPIO ALT0 Reset Condition Default function ENET0_RGMII_RXD1 ENET0_RGMII_RXD2 ENET0_RGMII_RXD3 LSIO.GPIO5.IO31 LSIO.GPIO5.IO30 LSIO.GPIO6.IO00 LSIO.GPIO6.IO01 LSIO.GPIO6.IO02 LSIO.GPIO6.IO03 LSIO.GPIO4.IO18 ENET1_MDIO LSIO.GPIO4.IO16 ENET1_RGMII_RX_CTL ENET1_RGMII_RXC ENET1_RGMII_RXD0 ENET1_RGMII_RXD1 ENET1_RGMII_RXD2 ENET1_RGMII_RXD3 LSIO.GPIO6.IO11 LSIO.GPIO6.IO10 LSIO.GPIO6.IO12 LSIO.GPIO6.IO13 LSIO.GPIO6.IO14 LSIO.GPIO6.IO15 ESAI0_FSR ESAI0_FST ESAI0_SCKR ESAI0_SCKT ESAI0_TX0 ESAI0_TX1 ESAI0_TX2_RX3 ESAI0_TX3_RX2 State2 PD PD PD PU PD PD PD PD i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 127 Package information and contact assignments Table 127. 29 × 29 mm functional contact assignments (continued) Ball AV8 AU7 BE11 BF12 BD12 AY10 BF10 BA11 AU11 AV10 AY12 AT10 C5 H6 E5 G7 C3 E7 AV52 AY52 AW53 AY50 BA53 BA51 BL13 BM14 BJ9 BL11 BM12 BL15 BM16 BL17 BM18 Ball Name ESAI0_TX4_RX1 ESAI0_TX5_RX0 ESAI1_FSR ESAI1_FST ESAI1_SCKR ESAI1_SCKT ESAI1_TX0 ESAI1_TX1 ESAI1_TX2_RX3 ESAI1_TX3_RX2 ESAI1_TX4_RX1 ESAI1_TX5_RX0 FLEXCAN0_RX FLEXCAN0_TX FLEXCAN1_RX FLEXCAN1_TX FLEXCAN2_RX FLEXCAN2_TX GPT0_CAPTURE GPT0_CLK GPT0_COMPARE GPT1_CAPTURE GPT1_CLK GPT1_COMPARE HDMI_RX0_ARC_N3 HDMI_RX0_ARC_P3 HDMI_RX0_CEC3 HDMI_RX0_CLK_N3 HDMI_RX0_CLK_P3 HDMI_RX0_DATA0_N3 HDMI_RX0_DATA0_P3 HDMI_RX0_DATA1_N3 HDMI_RX0_DATA1_P3 Power Domain VDD_ESAI0_MCLK_1P8_3P3 Ball Type1 Default mode GPIO ALT0 VDD_ESAI1_SPDIF_SPI_1P8_3P3 GPIO ALT0 VDD_FLEXCAN_1P8_3P3 VDD_M4_GPT_UART_1P8_3P3 GPIO GPIO ALT0 ALT3 ALT0 ALT3 ALT0 ALT3 ALT0 VDD_HDMI_RX0_1P8 HDMI Reset Condition Default function ESAI0_TX4_RX1 ESAI0_TX5_RX0 ESAI1_FSR ESAI1_FST ESAI1_SCKR ESAI1_SCKT ESAI1_TX0 ESAI1_TX1 ESAI1_TX2_RX3 ESAI1_TX3_RX2 ESAI1_TX4_RX1 ESAI1_TX5_RX0 FLEXCAN0_RX LSIO.GPIO3.IO30 FLEXCAN1_RX LSIO.GPIO4.IO00 FLEXCAN2_RX LSIO.GPIO4.IO02 GPT0_CAPTURE GPT0_CLK GPT0_COMPARE GPT1_CAPTURE GPT1_CLK GPT1_COMPARE Not muxed State2 PD PD PD PD PD PD PD PD PD i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 128 NXP Semiconductors Ball BL19 BM20 BH10 BE13 BF14 BN11 BJ11 BG3 BH2 BJ1 BK2 BL3 BM4 BL5 BM6 BL7 BM8 BL9 BG1 BN5 BH8 BJ7 BN9 BN7 BC51 BE51 BD52 BA49 BE53 Package information and contact assignments Table 127. 29 × 29 mm functional contact assignments (continued) Ball Name HDMI_RX0_DATA2_N3 HDMI_RX0_DATA2_P3 HDMI_RX0_DDC_SCL3 HDMI_RX0_DDC_SDA3 HDMI_RX0_HPD3 HDMI_RX0_MON_5V3 HDMI_RX0_REXT3 HDMI_TX0_AUX_N HDMI_TX0_AUX_P HDMI_TX0_CEC HDMI_TX0_CLK_EDP3_N HDMI_TX0_CLK_EDP3_P HDMI_TX0_DATA0_EDP2_N HDMI_TX0_DATA0_EDP2_P HDMI_TX0_DATA1_EDP1_N HDMI_TX0_DATA1_EDP1_P HDMI_TX0_DATA2_EDP0_N HDMI_TX0_DATA2_EDP0_P HDMI_TX0_DDC_SCL HDMI_TX0_DDC_SDA HDMI_TX0_HPD HDMI_TX0_REXT HDMI_TX0_TS_SCL HDMI_TX0_TS_SDA JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_B Power Domain VDD_HDMI_RX0_1P8 Ball Type1 Default mode HDMI Reset Condition Default function Not muxed State2 VDD_HDMI_TX0_1P8 HDMI Not muxed VDD_HDMI_TX0_DIG_3P3 GPIO ALT0 VDD_SCU_1P8 TEST HDMI_TX0_TS_SCL HDMI_TX0_TS_SDA Not muxed PU PD PU Drive0 PU i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 129 Package information and contact assignments Table 127. 29 × 29 mm functional contact assignments (continued) Ball BL41 BN41 BK42 BM42 BL43 BN43 BK44 BM44 BL45 BN45 BG45 BH46 BG43 BH44 BG41 BH42 BG39 BH40 BG37 BH38 BE39 BD40 BD38 BD36 BE37 BE35 Ball Name LVDS0_CH0_CLK_N LVDS0_CH0_CLK_P LVDS0_CH0_TX0_N LVDS0_CH0_TX0_P LVDS0_CH0_TX1_N LVDS0_CH0_TX1_P LVDS0_CH0_TX2_N LVDS0_CH0_TX2_P LVDS0_CH0_TX3_N LVDS0_CH0_TX3_P LVDS0_CH1_CLK_N LVDS0_CH1_CLK_P LVDS0_CH1_TX0_N LVDS0_CH1_TX0_P LVDS0_CH1_TX1_N LVDS0_CH1_TX1_P LVDS0_CH1_TX2_N LVDS0_CH1_TX2_P LVDS0_CH1_TX3_N LVDS0_CH1_TX3_P LVDS0_GPIO00 LVDS0_GPIO01 LVDS0_I2C0_SCL LVDS0_I2C0_SDA LVDS0_I2C1_SCL LVDS0_I2C1_SDA Power Domain VDD_LVDS0_1P8 Ball Type1 Default mode LVDS Reset Condition Default function Not muxed VDD_LVDS0_1P8 LVDS Not muxed VDD_LVDS_DIG_1P8_3P3 GPIO ALT0 LVDS0_GPIO00 LVDS0_GPIO01 LVDS0_I2C0_SCL LVDS0_I2C0_SDA LVDS0_I2C1_SCL LVDS0_I2C1_SDA State2 PD PU i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 130 NXP Semiconductors Ball BK36 BM36 BL37 BN37 BK38 BM38 BL39 BN39 BK40 BM40 BK34 BM34 BL33 BN33 BK32 BM32 BL31 BN31 BK30 BM30 BD34 BH36 BL35 BE33 BD32 BN35 Package information and contact assignments Table 127. 29 × 29 mm functional contact assignments (continued) Ball Name LVDS1_CH0_CLK_N LVDS1_CH0_CLK_P LVDS1_CH0_TX0_N LVDS1_CH0_TX0_P LVDS1_CH0_TX1_N LVDS1_CH0_TX1_P LVDS1_CH0_TX2_N LVDS1_CH0_TX2_P LVDS1_CH0_TX3_N LVDS1_CH0_TX3_P LVDS1_CH1_CLK_N LVDS1_CH1_CLK_P LVDS1_CH1_TX0_N LVDS1_CH1_TX0_P LVDS1_CH1_TX1_N LVDS1_CH1_TX1_P LVDS1_CH1_TX2_N LVDS1_CH1_TX2_P LVDS1_CH1_TX3_N LVDS1_CH1_TX3_P LVDS1_GPIO00 LVDS1_GPIO01 LVDS1_I2C0_SCL LVDS1_I2C0_SDA LVDS1_I2C1_SCL LVDS1_I2C1_SDA Power Domain VDD_LVDS1_1P8 Ball Type1 Default mode LVDS Reset Condition Default function Not muxed State2 VDD_LVDS1_1P8 LVDS Not muxed VDD_LVDS_DIG_1P8_3P3 GPIO ALT0 LVDS1_GPIO00 PD LVDS1_GPIO01 LVDS1_I2C0_SCL PU LVDS1_I2C0_SDA LVDS1_I2C1_SCL LVDS1_I2C1_SDA i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 131 Package information and contact assignments Table 127. 29 × 29 mm functional contact assignments (continued) Ball AR47 AU53 AM44 AU51 AP44 AU47 AR45 AU49 BC3 BD4 BE21 BF20 BE23 BF22 BE19 BF18 BE25 BF24 BE17 BF16 BL23 BM22 BH24 BN19 BJ23 Ball Name M40_GPIO0_00 M40_GPIO0_01 M40_I2C0_SCL M40_I2C0_SDA M41_GPIO0_00 M41_GPIO0_01 M41_I2C0_SCL M41_I2C0_SDA MCLK_IN0 MCLK_OUT0 MIPI_CSI0_CLK_N MIPI_CSI0_CLK_P MIPI_CSI0_DATA0_N MIPI_CSI0_DATA0_P MIPI_CSI0_DATA1_N MIPI_CSI0_DATA1_P MIPI_CSI0_DATA2_N MIPI_CSI0_DATA2_P MIPI_CSI0_DATA3_N MIPI_CSI0_DATA3_P MIPI_CSI0_GPIO0_00 MIPI_CSI0_GPIO0_01 MIPI_CSI0_I2C0_SCL MIPI_CSI0_I2C0_SDA MIPI_CSI0_MCLK_OUT Power Domain VDD_M4_GPT_UART_1P8_3P3 Ball Type1 Default mode GPIO ALT0 VDD_ESAI0_MCLK_1P8_3P3 VDD_MIPI_CSI0_1P8 GPIO CSI ALT0 ALT3 Reset Condition Default function M40_GPIO0_00 M40_GPIO0_01 M40_I2C0_SCL M40_I2C0_SDA M41_GPIO0_00 M41_GPIO0_01 M41_I2C0_SCL M41_I2C0_SDA MCLK_IN0 LSIO.GPIO3.IO01 Not muxed VDD_MIPI_CSI0_1P8 VDD_MIPI_CSI_DIG CSI Not muxed GPIO ALT0 ALT3 MIPI_CSI0_GPIO0_00 MIPI_CSI0_GPIO0_01 MIPI_CSI0_I2C0_SCL MIPI_CSI0_I2C0_SDA LSIO.GPIO1.IO29 State2 PD PU PD PU PD PD PD PU PD i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 132 NXP Semiconductors Ball BH16 BJ17 BH18 BJ19 BH14 BJ15 BH20 BJ21 BH12 BJ13 BN15 BN13 BN17 BE15 BN23 BN27 BL27 BM28 BK28 BM26 BK26 BN29 BL29 BN25 BL25 BD30 BD28 BE29 BE31 Package information and contact assignments Table 127. 29 × 29 mm functional contact assignments (continued) Ball Name MIPI_CSI1_CLK_N MIPI_CSI1_CLK_P MIPI_CSI1_DATA0_N MIPI_CSI1_DATA0_P MIPI_CSI1_DATA1_N MIPI_CSI1_DATA1_P MIPI_CSI1_DATA2_N MIPI_CSI1_DATA2_P MIPI_CSI1_DATA3_N MIPI_CSI1_DATA3_P MIPI_CSI1_GPIO0_00 MIPI_CSI1_GPIO0_01 MIPI_CSI1_I2C0_SCL MIPI_CSI1_I2C0_SDA MIPI_CSI1_MCLK_OUT MIPI_DSI0_CLK_N MIPI_DSI0_CLK_P MIPI_DSI0_DATA0_N MIPI_DSI0_DATA0_P MIPI_DSI0_DATA1_N MIPI_DSI0_DATA1_P MIPI_DSI0_DATA2_N MIPI_DSI0_DATA2_P MIPI_DSI0_DATA3_N MIPI_DSI0_DATA3_P MIPI_DSI0_GPIO0_00 MIPI_DSI0_GPIO0_01 MIPI_DSI0_I2C0_SCL MIPI_DSI0_I2C0_SDA Power Domain VDD_MIPI_CSI1_1P8 Ball Type1 Default mode CSI Reset Condition Default function Not muxed State2 VDD_MIPI_CSI_DIG VDD_MIPI_DSI0_1P8 GPIO ALT0 MIPI_CSI1_GPIO0_00 PD MIPI_CSI1_GPIO0_01 MIPI_CSI1_I2C0_SCL PU MIPI_CSI1_I2C0_SDA ALT3 LSIO.GPIO1.IO29 PD DSI Not muxed VDD_MIPI_DSI_DIG_1P8_3P3 GPIO ALT0 MIPI_DSI0_GPIO0_00 PD VDD_MIPI_DSI_DIG_1P8_3P3 GPIO ALT0 MIPI_DSI0_GPIO0_01 PD MIPI_DSI0_I2C0_SCL PU MIPI_DSI0_I2C0_SDA i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 133 Package information and contact assignments Table 127. 29 × 29 mm functional contact assignments (continued) Ball BH30 BG31 BH32 BG33 BH28 BG29 BH34 BG35 BH26 BG27 BM24 BK24 BE27 BG25 D2 E3 E1 E33 D32 E35 F34 E31 D30 BE47 A17 D20 A15 A25 G25 A27 Ball Name MIPI_DSI1_CLK_N MIPI_DSI1_CLK_P MIPI_DSI1_DATA0_N MIPI_DSI1_DATA0_P MIPI_DSI1_DATA1_N MIPI_DSI1_DATA1_P MIPI_DSI1_DATA2_N MIPI_DSI1_DATA2_P MIPI_DSI1_DATA3_N MIPI_DSI1_DATA3_P MIPI_DSI1_GPIO0_00 MIPI_DSI1_GPIO0_01 MIPI_DSI1_I2C0_SCL MIPI_DSI1_I2C0_SDA MLB_CLK4 MLB_DATA4 MLB_SIG4 MLB_CLK_N5 MLB_CLK_P5 MLB_DATA_N5 MLB_DATA_P5 MLB_SIG_N5 MLB_SIG_P5 ON_OFF_BUTTON PCIE_CTRL0_CLKREQ_B PCIE_CTRL0_PERST_B PCIE_CTRL0_WAKE_B PCIE_CTRL1_CLKREQ_B PCIE_CTRL1_PERST_B PCIE_CTRL1_WAKE_B Power Domain VDD_MIPI_DSI1_1P8 Ball Type1 Default mode DSI Reset Condition Default function Not muxed State2 VDD_MIPI_DSI_DIG_1P8_3P3 GPIO ALT0 MIPI_DSI1_GPIO0_00 PD MIPI_DSI1_GPIO0_01 MIPI_DSI1_I2C0_SCL PU MIPI_DSI1_I2C0_SDA VDD_MLB_DIG_1P8_3P3 GPIO ALT0 MLB_CLK PD MLB_DATA MLB_SIG VDD_MLB_1P8 MLB Not muxed PD VDD_SNVS_LDO_1P8_CAP VDD_PCIE_DIG_1P8_3P3 ANA Not muxed PU GPIO ALT0 PCIE_CTRL0_CLKREQ_B PD PCIE_CTRL0_PERST_B PCIE_CTRL0_WAKE_B PU PCIE_CTRL1_CLKREQ_B PD PCIE_CTRL1_PERST_B PCIE_CTRL1_WAKE_B PU i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 134 NXP Semiconductors Package information and contact assignments Table 127. 29 × 29 mm functional contact assignments (continued) Ball Ball Name E23 PCIE_REF_QR D22 PCIE_REXT M20 PCIE_SATA0_PHY_PLL_REF_RETURN3 M28 PCIE0_PHY_PLL_REF_RETURN N23 PCIE1_PHY_PLL_REF_RETURN E25 PCIE_SATA_REFCLK100M_N3 F26 PCIE_SATA_REFCLK100M_P3 B20 PCIE_SATA0_RX0_N3 A19 PCIE_SATA0_RX0_P3 C17 PCIE_SATA0_TX0_N3 B16 PCIE_SATA0_TX0_P3 B30 PCIE0_RX0_N A29 PCIE0_RX0_P C27 PCIE0_TX0_N B26 PCIE0_TX0_P B22 PCIE1_RX0_N A21 PCIE1_RX0_P C25 PCIE1_TX0_N B24 PCIE1_TX0_P BF50 PMIC_EARLY_WARNING AY46 PMIC_I2C_SCL BG51 PMIC_I2C_SDA BH50 PMIC_INT_B BL51 PMIC_ON_REQ BE49 POR_B Power Domain VDD_PCIE_LDO_1P8 VDD_PCIE_LDO_1P0_CAP VDD_SCU_1P8 VDD_SNVS_LDO_1P8_CAP VDD_SCU_1P8 Ball Type1 Default mode PCIE Reset Condition Default function Not muxed State2 PCIE HCSL compatiable clock Not muxed Not muxed SCU ALT0 ANA SCU PMIC_EARLY_WARNING PMIC_I2C_SCL PMIC_I2C_SDA PMIC_INT_B Not muxed PD PU Drive1 PU i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 135 Package information and contact assignments Table 127. 29 × 29 mm functional contact assignments (continued) Ball G13 F14 H14 H16 G17 E17 E15 F16 H18 H20 G19 F20 H22 F18 F22 H24 D12 D14 E13 E11 H12 F10 J11 G11 BN47 BL47 AV6 AV4 AU3 AU5 AU1 AV2 Ball Name QSPI0A_DATA0 QSPI0A_DATA1 QSPI0A_DATA2 QSPI0A_DATA3 QSPI0A_DQS QSPI0A_SCLK QSPI0A_SS0_B QSPI0A_SS1_B QSPI0B_DATA0 QSPI0B_DATA1 QSPI0B_DATA2 QSPI0B_DATA3 QSPI0B_DQS QSPI0B_SCLK QSPI0B_SS0_B QSPI0B_SS1_B QSPI1A_DATA0 QSPI1A_DATA1 QSPI1A_DATA2 QSPI1A_DATA3 QSPI1A_DQS QSPI1A_SCLK QSPI1A_SS0_B QSPI1A_SS1_B RTC_XTALI RTC_XTALO SAI1_RXC SAI1_RXD SAI1_RXFS SAI1_TXC SAI1_TXD SAI1_TXFS Power Domain VDD_QSPI0_1P8_3P3 Ball Type1 Default mode FASTD ALT0 VDD_QSPI0_1P8_3P3 FASTD ALT0 VDD_QSPI1A_1P8_3P3 FASTD ALT0 VDD_SNVS_LDO_1P8_CAP ANA Reset Condition Default function QSPI0A_DATA0 QSPI0A_DATA1 QSPI0A_DATA2 QSPI0A_DATA3 QSPI0A_DQS QSPI0A_SCLK QSPI0A_SS0_B QSPI0A_SS1_B QSPI0B_DATA0 QSPI0B_DATA1 QSPI0B_DATA2 QSPI0B_DATA3 QSPI0B_DQS QSPI0B_SCLK QSPI0B_SS0_B QSPI0B_SS1_B QSPI1A_DATA0 QSPI1A_DATA1 QSPI1A_DATA2 QSPI1A_DATA3 QSPI1A_DQS QSPI1A_SCLK QSPI1A_SS0_B QSPI1A_SS1_B Not muxed VDD_SPI_SAI_1P8_3P3 GPIO ALT0 SAI1_RXC SAI1_RXD SAI1_RXFS SAI1_TXC SAI1_TXD SAI1_TXFS State2 PD PD PU PD PU PD i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 136 NXP Semiconductors Ball BB44 BC45 BJ53 BA43 AY42 BK52 AU43 AV44 AW45 BB46 BC47 AY44 BG49 BF48 BC53 BA47 BB50 AL45 AP46 AN45 AL43 AT48 AP48 BE41 BE43 BD46 BD42 BD6 BC7 BC9 Package information and contact assignments Table 127. 29 × 29 mm functional contact assignments (continued) Ball Name SCU_BOOT_MODE0 SCU_BOOT_MODE1 SCU_BOOT_MODE2 SCU_BOOT_MODE3 SCU_BOOT_MODE4 SCU_BOOT_MODE5 SCU_GPIO0_00 SCU_GPIO0_01 SCU_GPIO0_02 SCU_GPIO0_03 SCU_GPIO0_04 SCU_GPIO0_05 SCU_GPIO0_06 SCU_GPIO0_07 SCU_PMIC_MEMC_ON SCU_PMIC_STANDBY SCU_WDOG_OUT SIM0_CLK SIM0_GPIO0_00 SIM0_IO SIM0_PD SIM0_POWER_EN SIM0_RST SNVS_TAMPER_IN0 SNVS_TAMPER_IN1 SNVS_TAMPER_OUT0 SNVS_TAMPER_OUT1 SPDIF0_EXT_CLK SPDIF0_RX SPDIF0_TX Power Domain VDD_SCU_1P8 Ball Type1 Default mode SCU Reset Condition Default function Not muxed State2 PD VDD_SCU_1P8 ALT0 GPIO ALT0 VDD_SCU_1P8 GPIO ALT0 VDD_SCU_1P8 SCU VDD_SIM0_1P8_3P3 GPIO ALT3 VDD_SNVS_LDO_1P8_CAP ANA SCU_BOOT_MODE4 SCU_BOOT_MODE5 SCU_GPIO0_00 SCU_GPIO0_01 SCU_GPIO0_02 SCU_GPIO0_03 SCU_GPIO0_04 SCU_GPIO0_05 SCU_GPIO0_06 SCU_GPIO0_07 Not muxed LSIO.GPIO0.IO00 LSIO.GPIO0.IO05 LSIO.GPIO0.IO02 SIM0_PD LSIO.GPIO0.IO04 SIM0_RST Not muxed PD PU PD PD PD Drive- 0 PD PD PD Hi-Z VDD_ESAI1_SPDIF_SPI_1P8_3P3 GPIO ALT0 SPDIF0_EXT_CLK PD SPDIF0_RX ALT3 LSIO.GPIO2.IO15 PD i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 137 Package information and contact assignments Table 127. 29 × 29 mm functional contact assignments (continued) Ball BC1 BA3 BB4 BA5 AY6 AW1 AY2 AW5 AY4 BA1 BG5 BD8 BF6 BE5 BF2 BC49 AW49 AU45 AV50 AV48 AV46 AR43 AT44 AY48 H26 F28 C39 B40 A37 A39 Ball Name SPI0_CS0 SPI0_CS1 SPI0_SCK SPI0_SDI SPI0_SDO SPI2_CS0 SPI2_CS1 SPI2_SCK SPI2_SDI SPI2_SDO SPI3_CS0 SPI3_CS1 SPI3_SCK SPI3_SDI SPI3_SDO TEST_MODE_SELECT UART0_CTS_B UART0_RTS_B UART0_RX UART0_TX UART1_CTS_B UART1_RTS_B UART1_RX UART1_TX USB_HSIC0_DATA USB_HSIC0_STROBE USB_OTG1_DN USB_OTG1_DP USB_OTG1_ID USB_OTG1_VBUS Power Domain VDD_SPI_SAI_1P8_3P3 Ball Type1 Default mode GPIO ALT0 ALT3 ALT0 VDD_ESAI1_SPDIF_SPI_1P8_3P3 GPIO ALT3 ALT0 VDD_ESAI1_SPDIF_SPI_1P8_3P3 GPIO ALT0 VDD_SCU_1P8 VDD_M4_GPT_UART_1P8_3P3 VDD_USB_HSIC0_1P2 ALT3 SCU GPIO ALT0 ALT3 ALT0 ALT3 ALT0 ALT3 ALT0 ALT3 FASTD ALT0 VDD_USB_OTG1_3P3 OTG Reset Condition Default function SPI0_CS0 SPI0_CS1 SPI0_SCK SPI0_SDI LSIO.GPIO3.IO03 SPI2_CS0 SPI2_CS1 SPI2_SCK SPI2_SDI LSIO.GPIO3.IO08 SPI3_CS0 SPI3_CS1 SPI3_SCK SPI3_SDI LSIO.GPIO2.IO18 Not muxed UART0_CTS_B LSIO.GPIO0.IO22 UART0_RX LSIO.GPIO0.IO21 UART1_CTS_B LSIO.GPIO0.IO26 UART1_RX LSIO.GPIO0.IO24 USB_HSIC0_DATA USB_HSIC0_STROBE Not muxed State2 PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD Hi-Z i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 138 NXP Semiconductors Ball C37 B38 F30 E29 A35 E27 B34 C35 B32 A33 J9 L9 F8 H10 J39 G41 E37 F38 E39 F40 H40 G43 F42 H42 J43 A5 B4 B8 Package information and contact assignments Table 127. 29 × 29 mm functional contact assignments (continued) Ball Name USB_OTG2_DN USB_OTG2_DP USB_OTG2_ID USB_OTG2_REXT USB_OTG2_VBUS USB_SS3_REXT USB_SS3_RX_N USB_SS3_RX_P USB_SS3_TX_N USB_SS3_TX_P USB_SS3_TC0 USB_SS3_TC1 USB_SS3_TC2 USB_SS3_TC3 USDHC1_CLK USDHC1_CMD USDHC1_DATA0 USDHC1_DATA1 USDHC1_DATA2 USDHC1_DATA3 USDHC1_DATA4 USDHC1_DATA5 USDHC1_DATA6 USDHC1_DATA7 USDHC1_STROBE USDHC1_RESET_B USDHC1_VSELECT USDHC2_CD_B Power Domain VDD_USB_OTG2_3P3 Ball Type1 Default mode OTG Reset Condition Default function Not muxed State2 VDD_USB_SS3_LDO_1P0_CAP USB3 Not muxed VDD_USB_SS3_TC_3P3 GPIO ALT0 VDD_USDHC1_1P8_3P3 VDD_USDHC1_1P8_3P3 FASTD ALT0 FASTD ALT0 VDD_USDHC_VSELECT_1P8_3P3 GPIO ALT3 ALT0 USB_SS3_TC0 USB_SS3_TC1 USB_SS3_TC2 USB_SS3_TC3 USDHC1_CLK USDHC1_CMD USDHC1_DATA0 USDHC1_DATA1 USDHC1_DATA2 USDHC1_DATA3 USDHC1_DATA4 USDHC1_DATA5 USDHC1_DATA6 USDHC1_DATA7 USDHC1_STROBE LSIO.GPIO4.IO07 LSIO.GPIO4.IO07 USDHC2_CD_B PU Drive0 PD PU PU PU i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 139 Package information and contact assignments Table 127. 29 × 29 mm functional contact assignments (continued) Ball Ball Name Power Domain Ball Type1 Default mode Reset Condition Default function State2 F46 USDHC2_CLK VDD_USDHC2_1P8_3P3 FASTD ALT3 LSIO.GPIO5.IO24 PD H44 USDHC2_CMD ALT0 USDHC2_CMD PD H48 USDHC2_DATA0 USDHC2_DATA0 PU G45 USDHC2_DATA1 USDHC2_DATA1 L45 USDHC2_DATA2 USDHC2_DATA2 J45 USDHC2_DATA3 USDHC2_DATA3 C7 USDHC2_RESET_B VDD_USDHC_VSELECT_1P8_3P3 GPIO ALT3 LSIO.GPIO4.IO09 PU A7 USDHC2_VSELECT LSIO.GPIO4.IO10 D8 USDHC2_WP ALT0 USDHC2_WP PD BN49 XTALI VDD_SCU_XTAL_1P8 ANA Not muxed BL49 XTALO 1 FASTD are GPIO balls configured for high speed operation using the FASTFRZ control. 2 Reset condition shown is before boot code execution. For pad changes after boot code execution, see the "System Boot" chapter of the device reference manual, 3 HDMI-RX is not currently supported, the related power and signal connections are provided for future use when it is expected HDMI-RX support will be enabled. 4 MLB is not supported on this device. Users may choose alternate functions as determined by the IOMUX. 5 MLB is not supported on this device. Terminate these outputs per the Hardware Developer's Guide for unused I/O signals. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 140 NXP Semiconductors Package information and contact assignments The following table shows the DRAM pin function for the 29 x 29 mm package. Ball Name DDR_CHx_ATO DDR_CHx_CK0_N DDR_CHx_CK0_P DDR_CHx_CK1_N DDR_CHx_CK1_P DDR_CHx_DCF00 DDR_CHx_DCF01 DDR_CHx_DCF02 DDR_CHx_DCF03 DDR_CHx_DCF04 DDR_CHx_DCF05 DDR_CHx_DCF06 DDR_CHx_DCF07 DDR_CHx_DCF08 DDR_CHx_DCF09 DDR_CHx_DCF10 DDR_CHx_DCF11 DDR_CHx_DCF12 DDR_CHx_DCF13 DDR_CHx_DCF14 DDR_CHx_DCF15 DDR_CHx_DCF16 DDR_CHx_DCF17 DDR_CHx_DCF18 DDR_CHx_DCF19 DDR_CHx_DCF20 DDR_CHx_DCF21 DDR_CHx_DCF22 DDR_CHx_DCF23 DDR_CHx_DCF24 Table 128. 29 x 29 mm DRAM pin function x=0 x=1 AF46 AF8 Y50 Y4 W49 W5 AB50 AB4 AC49 AC5 U47 U7 W47 W7 Y48 Y6 Y46 Y8 W43 W11 Y44 Y10 W45 W9 W51 W3 T48 T6 T52 T2 T50 T4 U51 U3 U49 U5 T46 T8 W53 W1 Y52 Y2 U53 U1 AC47 AC7 AB48 AB6 AB46 AB8 AC43 AC11 AE45 AE9 AC51 AC3 AC45 AC9 AB44 AB10 LPDDR4 Function -- CK_c_A CK_t_A CK_c_B CK_t_B CA2_A CA4_A -- CA5_A -- -- -- -- CA3_A -- CS0_A CA0_A CS1_A -- CKE0_A CKE1_A CA1_A CA4_B RESET_N CA5_B -- -- -- -- -- Notes NXP Internal Use Only (Leave Unconnected) The exact clock and control line connections will be dependent on the memory configuration in use. Refer to the Hardware Developers Guide (HDG) for further details. i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 141 Package information and contact assignments Table 128. 29 x 29 mm DRAM pin function (continued) Ball Name DDR_CHx_DCF25 DDR_CHx_DCF26 DDR_CHx_DCF27 DDR_CHx_DCF28 DDR_CHx_DCF29 DDR_CHx_DCF30 DDR_CHx_DCF31 DDR_CHx_DCF32 DDR_CHx_DCF33 DDR_CHx_DM0 DDR_CHx_DM1 DDR_CHx_DM2 DDR_CHx_DM3 DDR_CHx_DQ00 DDR_CHx_DQ01 DDR_CHx_DQ02 DDR_CHx_DQ03 DDR_CHx_DQ04 DDR_CHx_DQ05 DDR_CHx_DQ06 DDR_CHx_DQ07 DDR_CHx_DQ08 DDR_CHx_DQ09 DDR_CHx_DQ10 DDR_CHx_DQ11 DDR_CHx_DQ12 DDR_CHx_DQ13 DDR_CHx_DQ14 DDR_CHx_DQ15 DDR_CHx_DQ16 DDR_CHx_DQ17 DDR_CHx_DQ18 DDR_CHx_DQ19 x=0 x=1 AF52 AF2 AE47 AE7 AE51 AE3 AF50 AF4 AE49 AE5 AC53 AC1 AB52 AB2 AE53 AE1 AF48 AF6 H52 H2 N47 N7 AJ47 AJ7 AP52 AP2 P44 P10 N45 N9 L47 L7 K48 K6 H50 H4 G53 G1 G51 G3 N43 N11 L49 L5 K50 K4 N51 N3 L51 L3 P46 P8 N49 N5 P50 P4 P48 P6 AM50 AM4 AL49 AL5 AL51 AL3 AJ51 AJ3 LPDDR4 Function -- CA3_B CA0_B CS0_B CS1_B CKE0_B CKE1_B CA1_B CA2_B DMI[3..0] DQ[31..0] Notes The exact clock and control line connections will be dependent on the memory configuration in use. Refer to the Hardware Developers Guide (HDG) for further details. The exact mask, strobe and data connections to memory are flexible as long as the correct byte mapping is used, there is no restriction on the bit connections within each byte. DM0 -> DQS0(_N/P) -> DQ[7..0] DM1 -> DQS1(_N/P) -> DQ[15..8] DM2 -> DQS2(_N/P) -> DQ[23..16] DM3 -> DQS3(_N/P) -> DQ[31..24] i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 142 NXP Semiconductors Package information and contact assignments Table 128. 29 x 29 mm DRAM pin function (continued) Ball Name x=0 x=1 LPDDR4 Function Notes DDR_CHx_DQ20 DDR_CHx_DQ21 DDR_CHx_DQ22 DDR_CHx_DQ23 DDR_CHx_DQ24 DDR_CHx_DQ25 DDR_CHx_DQ26 DDR_CHx_DQ27 DDR_CHx_DQ28 DDR_CHx_DQ29 DDR_CHx_DQ30 DDR_CHx_DQ31 DDR_CHx_DQS0_N DDR_CHx_DQS0_P DDR_CHx_DQS1_N DDR_CHx_DQS1_P DDR_CHx_DQS2_N DDR_CHx_DQS2_P DDR_CHx_DQS3_N DDR_CHx_DQS3_P DDR_CHx_DTO0 DDR_CHx_DTO1 DDR_CHx_VREF DDR_CHx_ZQ AJ49 AJ5 AH46 AH8 AH48 AH6 DQ[31..0] The exact mask, strobe and data connections to memory are flexible as long as the correct byte mapping is used, there is no restriction on the bit connections within each byte. AH50 AH4 AJ45 AJ9 AH44 AH10 DM0 -> DQS0(_N/P) -> DQ[7..0] DM1 -> DQS1(_N/P) -> DQ[15..8] DM2 -> DQS2(_N/P) -> DQ[23..16] DM3 -> DQS3(_N/P) -> DQ[31..24] AM48 AM6 AL47 AL7 AR53 AR1 AP50 AP4 AJ43 AJ11 AR51 AR3 L53 L1 DQS[3..0]_c maps to _N K52 K2 DQS[3..0]_t maps to _P P52 P2 N53 N1 AH52 AH2 AJ53 AJ1 AL53 AL1 AM52 AM2 U45 U9 -- NXP Internal Use Only (Leave Unconnected) T44 T10 -- U43 U11 -- -- AF44 AF10 -- -- i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 NXP Semiconductors 143 Release Notes 7 Release Notes This table provides release notes for the data sheet. Table 129. Data sheet release notes Rev. Number Date Substantive Change(s) 2 05/2021 · Clarified LVDS Tx port information in Table 1, "i.MX 8QuadPlus advanced features" under Display I/O. · Updated Table 2, "i.MX 8QuadPlus Orderable part numbers" information. · Updated the example in Section 1.2, "System Controller Firmware (SCFW) Requirements". · Corrected document IDs in Table 3, "Related resources". · Updated LVDS information and clarified KHz for XTAL OSC32K in Table 4, "i.MX 8QuadPlus modules list". · In Table 8, "Operating ranges", added min frequency for VDD_A72 and VDD_A53. · Updated note in Section 4.1.5, "Maximum Supply Currents". · Updated the value ranges in Table 26, "LVDS PHY PLL". · Updated footnotes pointing to Section 4.6.2, "Input Signal Monotonic Requirements" in Table 30, Table 31, Table 32, Table 33, Table 34, Table 35, and Table 36. · Corrected test conditions in Table 38, "LPDDR4 DC parameters". · Added Section 4.6.2, "Input Signal Monotonic Requirements". · Corrected maximum frequency test conditions and footnotes 2 and 3 in Table 40, "General Purpose I/O AC Parameters". · In Table 81, "LVDS pins", updated single channel values. · Updated PCI Express Gen 2 values for AOPENING and added footnote to Table 93, "PCIe receiver eye specifications for example standards". · Rewrote introductory paragraph for Section 5.1, "Boot mode configuration inputs". · Clarified QSPI information in Table 125, "Interface allocation during boot". · Corrected default function for Ball AP46 in Table 127, "29 × 29 mm functional contact assignments". · Corrected x=0 column value for DDR_CHx_DTO1 in Table 128, "29 x 29 mm DRAM pin function". i.MX 8QuadPlus Automotive and Infotainment Applications Processors, Rev. 2, 05/2021 144 NXP Semiconductors How To Reach Us Home Page: nxp.com Web Support: nxp.com/support Limited warranty and liability -- Information in this document is believed to be accurate and reliable. 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For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 05/2021 Document identifier: IMX8QPAECAcrobat Distiller 21.0 (Windows)