Index of /documentation/apple3/service reference manual/
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
É
Apple /// Computer Information
Apple ///
Servîce Reference Manual
Theory of Operation Servicing Information
Written by Apple Computer 1982
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
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APPLE III SERVICE REFERENCE
MANUAL
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
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To the Reader,
This manual was developed for all the A/// Service Technicians at our
I/I. Level It Regional Service Center. The intent of this book is to help
you understand and repair the Apple
The book is partitioned into
two sections: Theory of Operation and Servicing Information. There is
sufficient information in this manual so that an inexperienced technician
I/I. can be productive in a short time. This manual should help you understand
and appreciate the Apple
In Appreciation:
Although many people have helped me with this manual I wish to particularly thank the following people for their contribution to this manual:
Bill Holman Wendell Sanders Mike Fallon Rick Hoiberg Ed Goodwin Sandy Sanford Peter Quinn
Thanks!
Bob Cummings
Apple Computer Inc · 1982
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Apple Computer Inc · 1982
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APPLE I I I REFERENCE MANUAL
1f you are interested in how the Apple I/I works, or if you want to trouble
shoot your machine, you should have this manual. As you can see from the
I/I. table of contents (shown below), this comprehensive manual covers virtually
every facet of the Apple
Like new condition, binder, 17 chapters,
460 pages (8-1/2 x 11), two diagnostic diskettes
$150.
TARIE OF COI1TENTS
ThEORY OF OPERATION
INTRODUCTEON
Cenerai De.cription Sispilfied Punctionsi Description The Mein Logic Board
The Memory Board The Keyboard FCB The Disk Drive The AppLe I/I Power Supply
K5ORY & MENORY ADDRESSING
introduction En the Appia /1/ Memory Simplified Mesozy Login Memory Addressiug Block Flow The Pronessor Memory Address )twltipiemer
RAS/CAS Decode
Alternate Stack Memory & hesory Addresaing Appendices
TM! VERSATILE I RTERFACE ADAPTER
General VIA 6522 Fis Dencriptlnna Vus Functional Description loterrupt Operation 6522 VIA iovirnnnant as Control VIA (FFDX) VIA (FrEE) VIA Appendices
THE AdA
The 6551 Asynnhomous Conicatione Interfsce Adapter
Status Register Coma.nd Register Control Register Simple Serial Port
SISTiM CLOCKS k TIMING Main Clock ClAM
Frequency Divider Q Timing RVE° Freeze Ao, PRE1K, b CiM RAS (Row Address StrobotSelect)) Video Horizontal b Vtrtical State Counters Horizontal Section Vertical Section
VIDEO SISPLAY LOGIC DISP1OY Iodes
Inc roduct Ion
40 Ciaractor Apple j) 40 Choracter Apple /1/ BO Choracter Black & Ahite Apple I/I Black h White Hiree Modica Resolution 16 Color Graphics Apple I/I Super Hire. Apple I/I Apple /1/ Rires Super Hires Apple I/I Video Appendin
iNPUT/OUTPUT
Descrtpt ion interface Control lignais Interrupts Addressing the I/O The Input Operation The Output Operation System Timiog the A//I Joystick
TRE KEYBOARD
The Keyboard Reading the Keyboard Keyhoard Codez The Apple [ Emulation Mode
Electronic Circuit De.crtptioo The Repeat Function The Reset Function
Keyboard Light
POWER SUPPLY
The A le7/I Power Supply The Bacic Switching Fouet Supply Bow it s.orbii Detailed Hardware Description
SPcahretms aLtiicst
Component Layout
Alt EISULATIOB
A)) Emulation Restrictiçoa The Color Video Connector The High-Resolution Crophics (Hi-Ken) Mode The Speaker The Cassette Sntertsce Input/Output Special brat ions A/D Selection Analog Inputs Strobe Output
Autoetart ROM/Monitor ROM
The System Monitor Built-In I/O Locations Peripheral I/O The Joystick Ports Peripheral Connector Pinout Peripheral Connector Signal DvocriptlnR ROM ListinHe
SCHEMATIC DIAGRAMS
Annotated Schesatic Diagrams
DISK SUBSYSTEM
Theory 0f Ope tattoo Disk Conditioning Circuit Analog Card
SERVICING INFORMATION
TESTDHC b TROUBLESHOOTING
Apple III
16 Sector
Final Sink
Test Procedure I/I Final Test (bOOT)
Apple /1/ Troubleshooting (Mrdule Lanci)
S Volt Mrmury Board Ram Troubleshooting Procedure
The Apple /1/ TroubleshoOting Flowchart (Component)
pe iii tcriW tit ion PARTS LAYOUT AND PARTS LOST Apple /1/ Indented Bill nf Macerlain
WIRE LIST
Wire List
MODULE REPLACEMENT PROCEDURES b ASSEMBLY DRAWINGS
Apple III Module Replacemant Procedures Apple I/I Dealer Sernice Diagnoatics Reference Apple I/I Asaembly Drawings
CENtRAL APPENDIX
Apple /1/ System Overview Apple I/I System Monitor Apple III Logic Signai Source Main Logic Board Circuit Function Areas How to Read Pros (Boa) Logic Empressions
Prom (ROM) Logic Empressions Ascii Conversion Tables
TABLES & ILLUSTRATIONS
hIEl System BSock Diagtam (Illustration) AISE Systo. Block Diagram - Detailed (Illustration) Syste. Functional Block Diagram The 12 Volt Memory Board (126K Configuration) The S Volt Memory Board (128E Configuration) The Apple /11 Main Logic Board (Module) The Apple 1ff Detabied System Functional Block Diagram The Apple I/I Memory flap Simplified Mesory Address Block Diagram Block Diagrss Memory Address Logic RAS/CAS Decode Logic Block Diagram indirect Addressing (Listing) Memory & Memory Addressing Appendis
Apple i/I Memory Map Memory Map Space Allocations Address Logic Truth Table The Apple III Memory Board (12W) The Apple /1/ Memory Board (5V) The 5 Volt Memory Board (2S() How to READ PROM (ROM) Logic Empressions RASI Logic ispreasios MPS Registers Block biagra. of Ehe 6522 VIA
Addressing 6522 VIA Iterual Register VEA PRIE Internal Register Summary VIA FlEX Internal Regioter Summary
VIA Appendices The ACEA Block Diagram ACEA Cootroi Register ACtA Command Register ACIA Statue ReRleter ACIA Pin Configuration Main Clock 14Mhz CIrcuit Freqoescy Divider Circuit A//I Systes Timing Diagrams S to 2 11hz Gearshift Video State Counter Video Scan Decode ROM Video Appendis
Apple /// Video Logic Bloch Diagram HArca Mode Luge 1, B/U, 280 X 192 Hires Mode Page 2, B/U, 280 X 192 280 E 192 Color Hires Mode Page 1 280 X 192 Coiot Bites Mode Page 2 Duper Hires Mode Page I Super Rires lode Page 2 Ahite. Test Page
¡cIID MORt!
Page 0004 of 0730
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
TABLE OF CONTENTS
SECTION I. CHAPTER 1. CHAPTER 2
CHAPTER 3
CHAPTER 4 CHAPTER 5
THEORY OF OPERATION
INTRODUCTION
Genera]. Description
Simplified Functional Description
The Main Logic Board
The Memory Board
The Keyboard PCB
I/I The Disk Drive
The Apple
Power Supply
I/I MEMORY & MEMORY ADDRESSING Introduction to the Apple
Memory
Simplified Memory Logic
Memory Addressing: Block Flow
The Processor
Memory Address Multiplexer
RAS/CAS Decode
Alternate Stack
Memory & Memory Addressing Appendices
THE VERSATILE INTERFACE ADAPTER nera1
VIA 6522 Pin Descriptions VIA Functional Description
Interrupt Operation
6522 VIA Environment and Control
VIA (FFDX)
VIA (FFEX) VIA Appendices
THE ACtA ie 6551 Asynchonous Communications Interface Adapter
Status Register Command Register Control Register Simple Serial Port
SYSTEM CLOCKS & TIMING Main Clock CI4M Frequency Divider
"Q" Timing HPE* Freeze
Ax, PREIM, & C1M RAS (Row Address Strobe[Select]) Video Horizontal & Vertical State Counters Horizontal Section Vertical Section
PAGE
1.l 1.4 1.4 1.6 1.7 1.7 1.7
2.1 2.1 2.4 2.4
2.6
2. 6
2.10 2.12
3.1 3.1
3.6
3.8
3.10 3.12
3.15 3.18
4.1 4.3
4.4 4.5
4. 6
5.1.
5.1.
5.1
5.5
5. 5
5.5 5.7
5.7 5.10
iii
L
Apple Computer Inc · 1982
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" - I Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
CHAPTER 6
VIDEO DISPLAY LOGIC
Display Nodes
6.1
mt roduct tori
6.2
40 Character Apple ]
6.2
I/I 40 Character Apple
6.3
I/I 80 Character Black & White Apple
6.3
Black & White Hires
6.4
Medium Resolution 16 Color Graphics Apple /1/
6.4
I/I Super Hires Apple
I/i Apple
Hires
6. 5
6.5
I/I Super Hires Apple
6.7
Video Appendix
6.9
CHAPTER 7
INPUT/OUTPUT
Description
7.1
Interface Control Signals
7.1
Interrupts
7.2
Addressing the I/O
7.2
The Input Operation
7.3
The Output Operation
7.3
System Timing
7.3
the A//I Joystick
7.5
CHAPTER 8 CHAPTER 9 CHAPTER 10
THE KEYBOARD he Keyboard
Reading the Keyboard Keyboard Codes The Apple j f Emulation Mode Electronic Circuit Description The Repeat Function The Reset Function Keyboard Light
POWER SUPPLY
i/I The Apple
Power Supply
The Basic Switching Power Supply
How it works!
Detailed Hardware Description
Schematic
Parts List
Component Layout
AJ[ EMULATION
A] [ Emulation Restrictions The Color Video Connector
The High-Resolution Graphics (Ej-Res) Mode The Speaker The Cassette Interface Input/Output Special Locations AID Selection Analog Inputs Strobe Output
Autostart ROM/Monitor ROM
a.i 8.1 8. 8.? 8.7 8.8 8.8 8.8
9.].
9.1
9.3
9.6
9.9 9.10 9.13
10.1 10.2
10.3 10.3 10.3 10.4 10.4 10.5 10.5 10.5
Apple Computer Inc · 1982
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CHAPTER 11 CHAPTER 12
The System Monitor Built-In I/O Locations Peripheral I/O The Joystick Ports Peripheral Connector Pinout Peripheral Connector Signal Description ROM Listings
SCHEMATIC DIAGRAMS Annotated Schematic Diagrams
DISK SUBSYSTEM iory Of Operation Disk Conditioning Circuit
Analog Card
lO. 6
10.8 10.10 10.11
10.14 10.15 10.18
111
12.]. 12.]. 12 4
SECTION II.
SERVICING INFORMATION
CHAPTER 13
CHAPTER 14 CHAPTER 15 CHAPTER 16 CHAPTER 17
TESTING & TROUBLESHOOTING
Apple /1/ Final Test Procedure
I/I 16 Sector Disk
Final Test (1000T)
I/I Apple
Troubleshooting (Module Level)
13.1 13.9 13.11
5 Volt Memory Board Rain Troubleshooting Procedure 13.16
The Apple /1/ Troubleshooting Flowchart (Component) 13.28
PARTS LAYOUT AND PARTS LIST
I/I Apple 1/I IC Parts by Ltion
Apple
Indented Bill of Materials
14.1
14.4
WIRE LIST Wire List
15.1
MODULE REPLACEMENT PROCEDURES & ASSEMBLY DRAWINGS
I/I Apple
Module Replacement Procedures
I/I Apple
Dealer Service Diagnostics Reference
I/I Apple
Assembly Drawings
16.1 16.25 16.32
GENERAL APPENDIX
I/I Apple I/f Apple I/I Apple
System Overview System Monitor Logic Signal Source
Main Logic Board Circuit Function Areas
How to Read Prom (Rom) Logic Expressions
Prom (ROM) Logic Expressions
Ascii Conversion Tables
17 1
17.3 17.5 17.9 17.10
17.11
17.19
V
Apple Computer Inc · 1982
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- comput
LIST OF TABLES & ILLUSTRATIONS
AhI System Block Diagram (Illustration)
1.2
kill System Block Diagram - Detailed (Illustration) 1.3
System Functional Block Diagram
1.5
The 12 Volt Memory Board (128K Configuration)
1.6
The 5 Volt Memory Board (128K Configuration)
1.7
I/I The Apple I/I The Apple
Main Logic Board (Nodule)
1.8
Detailed System Functional Block Diag rami .9
I/I The Apple
Memory Map
2.2
Simplified Memory Address Block Diagram
2.3
Block Diagram Memory Address Logic
2.5
RAS/CAS Decode Logic Block Diagram
2.7
Indirect Addressing (Listing)
2.8
Memory & Memory Addressing Appendix
I/I Apple
Memory Map
2.12 2.13
Memory Map Space Allocations
2.17
Address Logic Truth Table
I/I The Apple
Memory Board (12V)
I/f The Apple
Memory Board (5V)
2.18 2.19 2.20
The 5 Volt Memory Board (25()
2.21
How to READ PROM (ROM) Logic Expressions
2.22
RAM Logic Expression
2.2 3-2.28
MPU Registers
2.29
Block Diagram of the 6522 VIA
3.2
Addressing 6522 VIA Internal Register
3.2
VIA FFDX Internal Register Summary
3.11
VIA FFEX Internal Register Summary
3.14
VIA Appendices
3.18
The ACIA Block Diagram
4.2
ACIA Control Register
4.11
ACIA Command Register
4.11
ACIA Status Register
4.12
ACIA Pin Configuration
4.12
Main Clock 14Mhz Circuit
5.2
Frequency Divider Circuit
5.2
A//I System Timing Diagrams
5.3-5.6
1 to 2 Mhz Gearshift
5.8
Video State Counter
5.8
Video Scan Decode ROM
5.9
Video Appendix
Apple /1/ Video Logic Block Diagram
6.9 6.10
Rires Mode Page 1, B/W, 280 X 192
6.11
Hires Mode Page 2, B/W, 280 X 192
6.12
280 X 1.92 Color Hires Mode Page 1
6.13
280 X 1.92 Color Hires Mode Page 2
6.14
Super Hires Mode Page 1
6.15
Super Hires Mode Page 2
6.16
Ahires Test Page 1.
6.17
vii
Apple Computer Inc · 1982
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Ahites Test Page 2 Color Bar & Gray Scale Test
6.18
6.19
Apple JI Text Mode Page 1
Apple ][ Text Mode Page 2
6.20 6.21
Sara 40 Column Text Mode Test
6.22
Sara 80 Column Text Mode Test
6.23
Video Mode Truth Tables
6.24
Video Circuit Schematic Video Output types
6.25 6.26
Video Output Type (Circuit diagrams)
6.27
Video ROM Logic Expressions
6.29
Video ROM Circuit truth table representation Color Video Connector Description
6.30
6.31
I/O System Timing Diagram
7.4
Peripheral Connector Pinout
7.7
Peripheral Connector Signal Description
7.8
Pin Signal Assignment Keys & Associated ASCII Codes
8.9
8.10
Keyboard Circuit Schematic Reset Circuit Schematic
8.12
8.13
A//I Power Supply Parts Layout
9.2
Switching Power Supply Block Diagram
9.4
Switching Power Supply Circuit Block Diagram
9.5
A/II Power Supply Schematic Diagram
9.8
A/// Power Supply Parts List
9.10
A//f Power Supply Parts Layout
9.13
A/// Schematic Diagrams
11.1-11.12
Disk Conditioning Circuit Schematic
12.2
Analog Card A//f Circuit Schematic
12.5
A/If Internal Disk Assembly Drawing
12.8
Install Disk Drive Illustration
Apple III Disk Enables
12.9 12.10
Main Logic Board IC Designators
14.3
Apple I/f Logic Signal Source
17.5
Main Logic Board Circuit Function Areas How to Read Prom (Rom) Logic Expressions Prom (ROM) Logic Expressions Ascii Conversion Tables
17.9
17.10 17.11
17.19
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
g
Apple /// Computer Information
Apple ///
Service Reference Manual
Section I of II . Theory of Operation Chapter i Introduction
Written by Apple Computer . 1982
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
t
a computar
INTRODUCTION
GENERAL DESCRIPTION
I/I The Apple
is a personal computer for the professional. It has the
capabilities to run very involved programs since it can have up to 256K of
RAM. The overall unit has been designed to incorporate the best features and
options that make it a complete personal computer. The Apple ][ emulation mode allows users to run most Apple ][ software. However, minor modifications
may be required for some Apple ][ programs or other peripheral devices.
The base system has a full ASCII keyboard which includes a 13-key numeric key pad with two special function keys. There are four cursor control keys. The A//I has two special repeat features: 1) each key repeats when held depressed, and 2) a high-speed repeat is activated with the Solid Apple key. It's typewriter style keyboard is sculptured for maximum typing speed and accuracy.
I/I The Apple
has a built-in disk drive (140K bytes) and controller whIch is
capable of supporting three additional external drives vithout additional
interfacing. One interesting feature is that the two drives may be o at the
I/Isame time. This increases the disk-to-disk transfer effectiveness. The Apple can also be used with "Profile"- Apple's 5 Megabyte hard disk for mass
data storage.
A built-in RS-232 port, located on the back panel, allows you to connect the
Apple /1/ to letter quality printers, high-speed data collection devices,
modems, and other serial input/output devices using RS-232-C protrocol. The A//f has two joystick ports for games, sophisticated cursor contrl, or silentype operation.
The Apple /1/ has 8 different modes of video operation. 81W Text in AO and 80
column, a 40 column 16 color text mode (where the foreground and background of each character can be defined). The Apple ][ graphics rodes are dupllcate1 and there are three more graphics modes: a super black and white Hi-Res, 16 color Hi-Res, and 16 color medium resolution graphics. The eigth mode is actually a utilizatin of the color text mode where the user defInes the character image and builds video images with these "character sets". Since the video character generator is RAN, not ROM, as in the :\pple ][, it provides the user with the capability of defining character sets to display whatver the user wants. Three video outputs are provided at the hack panel; these are black and white, NTSC color composite, and ROH video icr axceptional color purity and resolution.
The Apple ///'s Central Processing Unit (CPU) can be "interrupted" hy
peripheral devices whenever they require CPU control. Alternativel;r the CPU can poll the devices to determine which needs attention, therebi iiImizing tne software required for peripheral control.
I/I There are more features in the Arole
such as, a built-in c]ock/calender, a
hardware beeper to simplify programming, a six-level D/A corIvrter for nor
1.1
Apple Computer Inc · 1982
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I
-'Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
A III SYSTEM BLOCILDIAGRAN
r
MEMORY
POWER
SUPPLY
MAIN LOGIC BOARD
PERIPHERAL SLOTS
Y B O A R D
L
DISK
EXT DISK
i
JOYSTICK 0
JOYSTICK i
AUDIO
RS232
VIDEO
J
EXT
DISK
2
EXT
DISK
3
1.2
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual A III SYSTEJI BLOCLDIAGRAN
r
-I
MEMORY-
POWER SUPPLY
N
KM S EA W YT
I
B R &T
01 C AX H
R
E
_D
S
MAIN LOGIC BOARD
MPU ROM VIA'S CLOCK A/D SOUND TIMERS RAIl ADDRESS ACIA VIDEO GEN DISK CONTROLLER
PERIPHERAL SLOTS
JOYSTICK 0 JOYSTICK i AUDIO RS232 VIDEO
s-
'lb.
DISK
L
INTERNAL
-J
EXT DISK
i
EXT DISK
2
EXT DISK
D EF IN IT IONS
- MP
RO
-
MICROPROCESSOR READ ONLY MEMORY
FIG 1.1
VERSATILE INTERFACE ADAPTER: A SPECIAL PURPOSE PROCESSOR
ASYNCHRONOUS COMMUNICATIONS INTERFA ADAPTER PROVIDES
A/D -
RS232 COMMUNICATIONS CAPABILITY, ANALOG TO DIGITAL CONVERTER
1.3
Apple Computer Inc · 1982
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complex tone generation, and the duplication of the speaker function of the Apple ][.
As you can see there are many onboard features that would fully load an Apple
I/I ][, yet the Apple
has four expansion slots for additional user
interfacing. As you read this document and learn how it works, you will.
appreciate its capabilities, design, and usefulness.
SIMPLIFIED FUNCTIONAL DESCRIPTION
The Apple /1/ is not an easy machine to understand. It has been designed to
emulate the Apple ][ and has done many operations in a different manner, while adding many enhancements which contribute to its complexity. To understand the system structure it is best to start building functional blocks and gain an understanding of each separately, and then comprehensively.
I/f. There are five major parts (modules) to the Apple
These parts are:
Main Logic PCB - this board functions primarily as a processor and device controller. Many functions are integrated into the board, including the disk controller.
Memory PCB - this board stores data/programs temporarily (until power is removed).
Keyboard PCB - this is the primary input device provided to the user.
Disk Drive - Mass storage device for storing data.
Power Supply - provides the voltages and regulation required to keep everything else working.
THE MAIN LOGIC BOARD
The Main Logic Board is easily identified by its large size and mass quantities of integrated circuits (IC's).
Referring to the block diagram of Figure 1.1 ve encounter the microprocessor (MPU), Boot/Monitor ROM, address decode/select circuitry, the Versatile Interface (VIA) containing the bank switch register and the sound register, the VIA containing the environmental and zero page registers, the Asynchronous Communications Interf ace Adapter (AdA), analog to digital circuit (joystick inputs), the expansion I/O slots, disk controller, keyboard encoder, video generator, RAN, RAN address circuits, and the system and video timing circuits. Wh000, now you see why it's so big!
I/I Figure 1.1 shows the Apple
in it's simplest form and presents its expanded
I/O capability. On the other hand, the System Functional Block Diagram
displays the system in more detail and presents a sophisticated system using
some highly unique designs. Some definitions have been provided for some of
the terms used in the block diagram.
Apple Computer Inc · 1982
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B
u F F
E R
ZERO PAGE REG.
ROIl 4k
Afl-A7 Ilpu
A8-A1 5
6502
flux
FFDX
ZERO PAGE
VIA
6522
ADfSS
FF
VIA
6522
ACIA
6551
a
'J
A
F
flUX
F
E
BYT
R
A T
DATA BUS
J /0
lEYBOARD
Dish CONTROL
L,5138 (DECODE)
I/ujT
DATA TO RAM LONNECTORS
INTERNAL DATA BUS
j CLOCK
L__j I CALI
1.5
FIG 1.2
Apple Computer Inc · 1982
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pp-u
It is best to think of the Apple ¡/1 processor as more than just the MPU chip.
The processor/controller is actually comprised of many components. The most significant of these are the MPIJ and the two VIA's. Because of the system's complexity and memory size, the MPU must have extended addressing. Extended
addressing is accomplished thru bank switches, environmental register, and a
zero page register.
I/I The Apple
system is interrupt driven. In order to efficienctly use
processing time, only those devices that allow programs access to the
processor are serviced. In fact the processor can even totally mask. (disable)
the reset key.
THE MEMORY BOARD
I/I The other PCB in the Apple
is the memory board. It is mounted on the Main
Logic Board by two rows of pin connectors. There are two distinct types of
memory boards. The early memory board version is commonly refered to as the
12V Memory Board. Below is an illustration of this board.
THE 12 VOLT MEMORY BOARD (128K CONFIGURATION)
f-LE
J
o
i
=
= = =
=
= ==
= = =
C
C
=
=== ==
= = = {C O C
J
C
C
o
With the correct Main Logic Board configuration, this board can have up to 128K RAM (without modification). The board uses 16K and 32K RAM chips.
The latest memory board version is called the 5 Volt Memory Board. This board, illustrated in the accompanying pages, can be configured for 128K or 256K RAM. The 5 Volt Memory Board, however, requires the correct Main Logic Board configuration.
1.6
Apple Computer Inc · 1982
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THE 5 VOLT MEMORY BOARD (128K CONFIGURATION)
EJ
-5 w w w
w D- - D
OIILE1
:i tELI
THE KEYBOARD PCB
This has to be one of the nicest keyboards around. The sculptured keys are a
delight to touch. The Apple /1/ does not have an on board keyboard encoder -
the keyboard encoder is on the Main Logic Board. The keyboard is basically a matrix of switches. The keyboard is connected by means of a 26 pin ribbon cable to the Main Logic Board.
THE DISK DRIVE
I/I The disk drive is similiar to the Disk
Disk ][ and the Apple /1/ drive are the
](. The major difference between the door, the bezel, and the Analog Card.
Disk switch detection circuitry has been added to the Disk
Analog Card.
Through daiseychainirtg you can have up to three (3) external disk drives.
THE APPLE /1/ POWER SUPPLY The power supply, accessible from the bottom of the Apple 1/I, is housed in
the casting. It is a "switching type" power supply that supplies the following voltages:
o +5.0 VDC o +11.8 VDC
o 5.0 VDC
o 12.0 VDC
yet, it consumes less power than a 100 Watt light bulb. The power supply also has several protection features, le. overvoltage protection.
1.7
Apple Computer Inc · 1982
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a compu i
I/I Nov that we have taken a tour of the contents of the Apple
let us begin to
learn the inner workings.
-
N Ii
=
H
LJ
o
I LL[
-;, i_I I
o ___ RJo0
Iu - _uft,
nu
- ilL
-j
O
o
o
o
DL
o
I
I
a
o
THE APPLE /// MAIN LOGIC BOARD (MODULE) 1.8
Apple Computer Inc · 1982
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j j
-4-J
loin
çt0110 Too!
1101001
n-Io¡:liOixi.sIll-i-l
-4.-0x0;
4,041
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Apple Computer Inc · 1982
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i Apple /// Computer Information · Apple /// Level 2 Service Reference Manual Apple /// Computer Information Apple ///
Service Reference Manual
Section I of II s Theory of Operation Chapter 2 Memory & Memory Addressing
Written by Apple Computer . 1982
Apple Computer Inc · 1982
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MEMORY & MEMORY ADDRESSING
INTRODUCTION TO THE APPLE /1/ MEMORY
I/I In looking at the Apple
and its memory we are immediately posed with the
I/I problem of how the 6502 processor can handle 128K of RAM, 4K of ROM, and a
heavy array of internal and external I/O devices. The Apple
does indeed
do just that, and, further, has the hardware capability of controlling an
additional 128K of memory (for a total of 256K).
This "magic" is accomplished by Bank Switching technology. At any one time, the processor can directly address 65K locations. With the addition of the Bank Switch Register, an extended addressing register, the program can call up different banks of 32K RAM apace. With other software switches, ROM and all I/O locations can be replaced with RAM. [See Figure 2.1]
The first 8K of memory, from locations 0000 to 11FF, are fixed. The 32K
memory from locations locations 2000 to 91FF are electrically switchable. The
f/I Apple
can choose any of 15 banks to place in this area at any one time.
I/I, The maximum amount of storage on the Apple
therefore, is equal to 15
Banks x 32K per bank + 32K fixed storage. By comparison, a 128K system would
have three banks, a 256K system would have seven, etc.
In addition, the area in the fixed bank from location C000 to CFFF can be
switched from RAM memory to I/O space for the slots. The area from 1000 to FlIP is also switchab].e. When the machine is turned on, this area is ROM containing the startup program. This program runs a quick system check then loads SOS in from the internal drive. SOS then switches this area back to RAM.
The extended addressing mode allows any two adjacent banks, N and N+1, to be addressed as a contiguous 64K RAM space. Addresses 0000 to 7FFF are mapped Into bank N while addresses 8000 to 11FF are mapped into bank N+1.
I/I The Apple
has the capability for variable Zero Page locations and
I/I Alternate Stack locations. All these features give the Apple
great
flexibility. They also provide means for very large application programs, or
applications that need large amounts of RAM space for data crunching.
SIMPLIFIED MEMORY LOGIC
If we simplify the memory and memory address logic we get three basic
elements:
o the processor o the RAM address circuits
o the RAM array
2.1
Apple Computer Inc · 1982
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amp
$0000 $1000
RAM (8K)
0000 i FFF
Memory Map
128 K
BANK 0,
BANK i
BANK 2
$4000 $5000 $6000 $7000 $8000
RAM (32K)
Bank 0
R A M (32K)
Bank i
R A M (32K)
Bank 2
9FFF SA000
sc000
RAM (24K)
c000
I / 0 (4K)
CFFF
F000
ROM(4K)
FFFF
FFFF
I
2.2
FIG 2.1
Apple Computer Inc · 1982
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SIUFIED 1E?W' ADDtSS BlOCK DIN3RNI
VIDEO STATE COUNTER
ADDRESS
ADM DU
S S
ARX BUS
s, CAS
DECODE
CASØ-CAS7
LOGIC
BC AO
I, RAS
RAS-RAS7
DECODE
LOGIC
R O C E S S O R
MPU
& VIA'S
LANK SWITCH
'
R
O
L
DATA BUS
DA BUS
RAM
G R O U P "B"
JuAsE AcE T
DB BUS
Page 0023 of 0730
FIG 2.2
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
I-
,pIa comptar L
In this discussion, ti-' processor is more than just the microprocessor chip; it also contains various external registers and control ROMs which enabl.e the extended addressing and bank switch modes. [Refer to Figure 2.2.1
Very simply, the processor presents an address for memory cycle, which is multtplexed into the address bus, ARX, and is decoded to develop the RAS (Row Address Strobe) and CAS (Column Address Strobe) to the RAM array (RAM group A & B). The direction of the data is controlled by Read/Write*. The selection of which RAIl group is being gated to the data bus is controlled by the CAS
decode circul.ts.
The display is memory mapped, the Screen timeshares the RAM on the opposite
phase of the processor clock. Both the screen and the processor are running
I/I at a 1MHz rate, which means that the RAM is running at a 2MHz rate. One new
feature of the Apple
is that the processor is able to make use of the
other "phase while the screen is off. In other words, any time the screen Is
off, the processor may run at a full 2MHz rate.
MEMORY ADDRESSING: BLOCK FLOJ
As more detail is added, it is possible to see the basic elements of the complete memory system (For now, we are not considering any to the hardware or
I/O).
o In the memory addressing logic of Figure 2.3, the processor nov shows the MPU and the two registers for expanded addressing capacity:
- the bank address register
- zero page register
o The address circuit Is comprised of two sections:
- the address multiplexer
- the RAS/CAS decoder
o The RAM array is expanded to show the eight RAMs.
It should be noted that this diagram depicts a 128K system (with a 12V Memory board), and that each of the RAMs shown actually represents eight RAM chips, one for each bit. Each RAM contains 16K bytes. The dotted lines indicate the row of chips that contain the 32K RAM chips. These are actually two 16K RAMs which reside on the one IC package.
THE PROCESSOR
The MPU is isolated from the rest of the memory by various buffers, muxes1 and r.gIsters. The mux switches in the Zero Page register whenever the MFU is attemptfng to reference the zero page.
2.4
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BLOCK DIAGRAM MEMORY ADDRESS LOGIC
AU-A1
AO-Â6
IO HØ
D ¡J 3-H
EN -Vl4 OT
E
R
D
DM
RU
EX
S
AY AY
AÏ
A2
30M
L_IuiiuCAS AROM ,JND
CASi
CL
AS2
AA CAS 3 ST .-.cAS46
C CAS?
H USELB
II
RANi 4Sl,L' Cpi:
1RAM3 I
-
A8-A1 S
T ROM 3399
PA8 _RAS 6,7
- RAS 4,5 12
1RAMS J C4S7
1Is!ÒfRAe4MsvJb41
ç-n
ML
¿UL
RAM?
IRAM6
J
U
ADDRESS
F
llßOICfUfl
F
MPU
1BKi-I
¡JA
XT
C
Jk'2
k 4A1
PA8
Dø- DT
M
U ¡)B0-flW(
g,
q4 ii
F
X
M
U
R
DAO-DT
A
PAGE
FIG 2.3
Page 0025 of 0730
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
ppIaconU
o The register may contain the true zero nage or may be set to any of 255 other values, under program control.
o The zero page register resides in the VIA and is accessed at FFDO. (On the Main Logic Board this is the VIA at location B6.)
o The Bank Register is located in the other VIA and is accessed at FFEF (at location B5). Zero page selection is independent of bank selection.
MEMORY ADDRESS MULTIPLEXER
The Memory Address Mux provides the four sets of addresses to the RAM array. They are:
o MPU RAS
o Video RAS
o MPU CAS
o Video CAS
These are time multiplexed by the four states determined by AX* line which is held at a steady state, allowing the processor full access to the RAN.
The Video addresses are much the same as In the Apple ](. There is a minor
III, difference in the Summing Circuit, but the technique of condensing undisplayed
addresses is the same. There is an additional consideration in the Apple which has a feature requiring additional control of the Video lines. This new feature is called slow scrolling of the screen.
Slow scrolling is accomplished in the Video Mux ROM by the arithmetic offset
of the VA, VB, and VC lines.
This offset causes characters to be fetched from
memory In advance of where the screen actually thinks it is. The character
array on the screen shifts up the number of dots determined by the binary
weight of the VBX lines. The processor, by monitoring the Vertical Blanking,
can then step the VBX lines and scroll the screen by moving in new lines at
the bottom, removing the top line, and placing lt at the bottom, thus rolling
the display.
RAS/CAS DECODE The RAS/CAS decode circuit Is made from four ROMs, a latch, and a latching mux. The basic inputs to the circuit are:
o the Address Bus o the Bank Switches o the Zero Page Select
2.6
Apple Computer Inc · 1982
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N
AAl/tf-V--, CAS
7'&A4S
AY
mees -
_4s -
O-3
-4S3 Er/ç qS7e4ASCeSA-r4S.'a"7
4;
LIStt3
AO
A,f-4f5 >
tt42-
Sc
--
XI4S
DA4
t;-
> '4
s
?4S0,3
R,s t,7
e94/aei.8¿V'4' ",4E
cippkz compuLxu'1inC
102ó0 Band ley Drive Cupertino. California 95014
7?14S/124S bEC9b L11C
Loe* 64A1 2.9
Page 0027 of 0730
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
INDIRECT ADDRESSING
Lt(ZPAGE)JY
YREG=ø
LDA (Z PIE), Y OP CODE ZPP43E ADDRESS
(iST1 8BIT BYTE) )
) PUT TOGETHER TO GET IIRECT ADDRESS
(au 8B!T BYTE) J LCD PCCIf4JLATOR FF] AB(])
NEXT OP CODE
FIG 2.5
2.8
Apple Computer Inc · 1982
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IF ZP/.V3E
18-1F (1F zo pi3E FLS BEThEEN ThE RANGE OF 184F)
B1
1805CD
16-BIT READ 1806 AB
LDA ZPEI Y OP CE
ZPÊGE AIRESS
LLD NXIIIJLA1DR
NEXOPC3E
FLG 1=(TENDa INDIRECT
OLINDIREC
AB
ABK1 DED AUJ RESS
2.9
Apple Computer Inc · 1982
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(Refer to Figure 2.41
Normal or Direct Addressing looks at the address and current bank selection, and enables the appropriate array of 64K RAil. This Direct Addressing always uses RAN O and RAN 3. Bank switches determine which of the RAN pairs is used for the other 32K of RAM.
It should be noted that on any read cycle, one RAS line and two CAS lines are selected. In this way, two bytes are always presented to the video circuits and the data selector. During a write cycle only one of each is selected.
The dual byte read usually provides only the information for the new video modes, but there is a new special memory fetch cycle built into the hardware. It is a special extended Indirect Addressing scheme which places the entire memory in virtual access.
By using Indirect Addressing through the zero page containing the 16 bit address, an instruction can address any of the 64K bytes contained in the bank pair. Thus any of the 32K byte RAM banks can be paired with any of their neighbors to form a 64K byte virtual address space.
If, during a zero page reference the zero page register has a value between $18 and $1F ($ means hexadecimal), a special Indirect Mode is called up. This mode looks at the sister fetched data byte on the RAN address bus and also looks at the high order bit. See Figures 2.5 and 2.6.
This special Indirect Mode is determined by the zero page register (X page Z page EOR $OC) If the bit is zero, the mode is not actualized and the ref erence continues in a normal manner in the presently selected bank arrangement. But if the High Order Bit (DA7) is high, the bank control mux latch switches to the state determined by the state of the DAODA2 lines. This allows the program to have access to another array of special zero pages.
When the system is in this special extended Indirect Mode, the I/O and LSI are totally disabled and the RAN is enabled to the data bus.
ALTERNATE STACK
I/I, Alternate Stack, the new feature of the Apple
is not shown in the block
diagrams. One of the bits of the Environmental Register (from one of the
VIAs) is the Alternate Stack Switch. If the Alternate Stack Switch is
selected, the stack associated with that zero page is either the one after the
zero page, if the zero page reference is even, or the one previous if the
reference is odd (i.e., if zero page is 2B then the stack is located in 2C; if
the zero page is 31 then the stack is in 30).
OTHER BANK SWITCHING
Earlier it was mentioned that the processor can access RAN associated with the addresses that are normally with I/O, ROM, and other circuits. Looking again at the Environmental Register, there are several switches that enable or disable I/O, ROM, and other circuit address decoding. If these switches are
2.10
Apple Computer Inc · 1982
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selected to disable their aesociatd function, the control ROM, which develops the enable for the RAN data selector, senses the fact that no hardware is being selected and allows RAN data to be read on the bus. No other special enables are needed since RAM is always read for every address presented. It should be noted that a special RAN write enable is used to prevent inadvertant writing into the RAN space associated with the hardware while the hardware is enabled.
2.11
/
Apple Computer Inc · 1982
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MEMORY & MEMORY ADDRESSING APPENDIX
The attached figures and illustrations are provided for your reference. Little or no explanation has been provided.
This Appendix contains:
o
I/I THE APPLE
MEMORY MAP
o
MEMORY MAP SPACE ALLOCATIONS
o ADDRESS LOGIC TRUTH TABLE
o
128K 12V MEMORY BOARD: PHYSICAL MEMORY
o
THE 5V MEMORY BOARD: PHYSICAL MEMORY
o ADDRESSING LOGIC EXPRESSIONS
o MPU REGISTERS
2.12
/
Apple Computer Inc · 1982
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0 APPLE 1/1 MEMORY MAP
SOS MEMORY ALLOCATION Location
Assignment
0000-1FFF 2000-9FFF 2000-9FFF 2000-9FFF A000-BPFF C000-CFFF D000-EFFF F000-FFFF
SOS and Interpreter Workspace Bank O Graphics Page 1 and 2 Bank i Program Bank 2 Driver and Interprter Interpreter I/O or SOS Kernal (Bank switchable to RAM) SOS Kerual Boot ROM OR SOS Kernal
ADDRESS ASSIGN4ENT
ADDRESS (REX)
0000-00FF 0100-01FF 0200-02FF 0300-03FF 0400-07FF 0800-OBFF OCOO-OFFF 1000-1FFF 2000-3FFF 4 000-5FFF 6000-7FFF 8000-9FFF A000-BFFF C000-CO7F c000 C001-0007 C008 C009-COOP COlO C01l-0O2F
CO 30
CO3l-CO3F C040-0040 CO4E
CO 4F co 50
COSi CO52
CO 53
CO54
AS S IGNMENT
(FUNCTION)
Zero Page
S tack
Input Buffer Open Lo-Res Display (Primary) and text
Lo-Res Di8play (Secondary) and text
Open-Reserved for system space Open Ri-Rea P8]. (Primary) switchable to RAM Ri-Rea Pgl (Secondary) switchable to RAM Ui-Res Pg2 (Primary) switchabie to RAM Wi-Rca Pg2 (Secondary) switchable to RAM Open System I/O Keyboard "A" bus data Same as 0000 but not used Keyboard "B" bus data Same as C008 but not used Keyboard reset Not used in Apple III Toggle the speaker like ici A-11 Same as CO30 but not used Sound hardware beeper Character Ram Disable Character Rae Enable Clear Text Mode Set Text Mode Clear Mix Mode Set Mix Mode Clear PG2 Mode
2.13 4/
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pp-N
CO5 5
CO56
CO 57
CO58 CO59 CO SA CO5B
CO SC
CO5D
CO 5E
CO5F
C060 , C068 C061, C069
C062,CO6A C063,CO6B COÔ4,CO6C C065,CO6D C066,CO6E C067,CO6F C070 C071-CO7F
C 080-COFF CO8F CO9X COAX
CO EX
COCX CODO COD1 COD2
C 0D3
CODA COD5 COD6 COD7 COD8 COD9 CODA CODE CODC CODD
CODE CODF COEO
COEJ.
COE2 COE3 COE4 COE5 COE6 COE7
C 0E8 C OEA
COES
Set PG2 Mode
Clear HIRES 1ode Set HIRES Mode Clear EMSOT PDL.O SET ENSOT PDLO Clear PDL2 (AID Addr 2) Set PDL2 Clear PDLEN (A/D Ramp Start) Set PDLEN Clear AXCO (AID Addr 1) Set AXCO Read SWO
Read SW1/MGSW
Read SW2 Read SW3/SCO Read IRQ3 Read IRQ4 Read PDLOT (A/D R.amp Stop) Read MUXI (PRAS Control) Access Real Time Clock Saines as C070 but not used I/O Scot Device Enable
NDevice Select 1
NDevice Select 2
NDevice Select 3
NDevice Select 4
Clear DS AO AO,Al.O,0'no select
Set DS AO
l,OEna 1 Exit
Clear DS Al
O,lEna 2 Exit
Set DS AI
1,lxEna 3 Exit
Clear Enable 3. tnt
Set Enable 1 tnt
Clear Side 2
Set Side 2
Clear SCR
Set SCR Clear ENCWRT
Set ENCWRT
Clear ENSEL Set ENSEL.
Clear ENSIC
Set ENSIO Clear DPHO (also VAL)
Set DPHO
Clear DPH1 (also VBI)
Set DPH1
Clear DPH2 (also VCI)
Set DPH2 Clear DPH3
Set DP{3
Disable Motor Drive (strt 2 sec to) COE9 Enable Motor Drive
Enable Ext
Enable tnt
2.14
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COEC COED COEE COEF COFOr COPOw COF1r
CO F 1w
COF2r /w6551 COF3r/w6551.
C IX.X
C100-C7FF
C 100
C1FF C2XX C200-C2FF C3XX C300-C3FF C3FF
CI4XX
C400-C4FF C500-C7FF C800-CFFF D000-DFFF E000 FFCX FFDO FFD1 FFD2 FFD3 FFD4 FFD5 FFD6 FFD7 FFD8 FFD9 FFDA FFDB FFDC
F'FDD
FFDE FFDF FFEO
F FE1
P FEZ
FFE3 FFE4 FFE5 FFE6 FFE7 FFE8 FFE9
F FEA
F FEB
Clear Q6 Note:Q6,Q7 control read Set Q6 write, and sense write Clear Ql protect
Set Ql 6551 Rec Data Reg 6551 Xmit Data Reg 6551 Status Reg 6551 Program reset Command Reg Control Reg NIO Select 1 I/O Slot individual ROM Space Slot 1 Firmware
NIO Select 2 Slot 2 Firmware NIO Select 3 Slot 3 Firmware
NIO Select 4 Slot 4 Firmware Run Space only Expansion Rom Firmware Open (system software) Bank switchable between Rom and Ram Always Ram Port B VIA-73 "Zero Page Reg" Port A VIA-73 DDR B VIA-73 DDR A VIA-73 Timer 1 low Latch (w)/Counter (r) Timer i High Counter Timer 1 Low Latches Timer 1 High Latches Timer 2 Low Latch (w)/Counter (r) Timer 2 High Counter Shift Register (serial print) Aux Control Reg VIA-73 Peripheral Control Register Interrupt Flag Register (73) Interrupt Enable Register (73) ORA/IRA With no handshake Port B (97) (sound and slot NMI) Port A (97) Banksw and IRQ's DDR B (97) DDR A (97) Timer i Low Latch/Counter Timer I. High Counter Timer i Low Latches Timer i High Latches Timer 2 Low Latch/Counter Timer 2 High Counter Shift Register (97) Aux Control Register (97)
2.15 1
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FFEC
FFED FFEE FFEF FFEO FFFL FFF2 FFF3 FFF4 FFF5 FFF6 FFF7 FFFF
Peripheral Control Register (97) Interrupt Flag Register (97) Interrupt Enable Register (97) ORA/IRA with no handshake Ram/Rom Bank E/o Bank Switch 2 MRz/MHZ Mode Switch Ihres Bank Switch Screen Enable Display Modes Zero Page RegIster Interrupt Control
2.16
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0000 0100
0200
MEMORY MAP SPACE ALLOCATIONS
PRIMARY ZP. PRIMARY STACK
O kOO
0600
TEXT
D I SPLAY
1000 1800 1FFF
IMAGE PAGES
SPECIAL ZERO PAGES
2000 9FFF
BANK O (HIRES)
rAM B
BANK i
RAIl 6
2-6
BANK 7
RAM
D-k
RAM I
A000
C 000
C 500
c800 0000 F000 FFFF
/
I/O DEy SLOT i SLOT 2 SLOT 3
SLOT k
SHARED
I/fl
C000
Cl 00
C200
C 300
C400
C4 F F
C Boo
I CFFF
[ROM1
ROM2
t
J
-* FFCX, FFDX, FFEX ARE ENVIRONMENT ADDRESSES 2.17 ,/
Apple Computer Inc · 1982
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Wf0 A-)
,pp
__meL/ (ss) 'iEoI,J
Vt.4sVIIfJ4EOp Çpa-)
fnf/ E/)
ri-is 'ion.
PiIAXY,O&
ST,TrE.
,(O6,c 7em 734LE
VY1AX 3 L 12
M
I
Az.
Pt
141
V t Vt VS
oo
Öl
I O M>
//
Apple Computer Inc · 1982
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Apple Computer Inc · 1982
380$
c7W ,Woh'3,' N/Yh' /11 37ddv
A 5u$
==r========
=g
V
8/
Dc
II II II
II
2000.3FFF - 8K
8000.9FFp - 8K
r
- 1111111 II Il
HlREs IVI'
CAS 1
I RAflS 1i ,2
D
0800.OFFF 1800.1FFF
-
2K
fi
21C(Special
fZle1r1o 1Pa1ges)1J
C000.C7FF - 2K
D000.D7FF - 2k E000.FFFF -8K
t_J ILJJ IL_il
c
cc
lI 16K CAS 3
RAIS,0,3
I.
lu -W-i
- 'I J-J
16K
2000.5FFF - 16K
BANK i CAS 'e,6
=---- -L- liii till il
2000.SFFF - 16KJ
1111111 IRAI,
LJAINlLK_2i
16K
CAS 4,6
RAS 6,7
-ri--
Ii 'JI si Iv! El 2! II ci
V. 1I u. r. j-
4000.SFFF - 8K
6000.7FFF - 8K
li 1-I- II II'?
, THH
BauAiNnKreøt'l
16K
CAS 2
RAS 1,2
111111 I liii
n,, nur ..,
0000.07FF = 2K
1000.17pF = 2K
A000.BFFF 8K
C800.CFFF - 2K I
I L_1 D800.DFFF = 2K
I1
16K
16K CAS I
RAS 0 3
6000.gppp- 16K
liii 1111111
6000.9 FFF- 16K
¡III
BANK1
ii. II BAi4K 2
16k
CAS 5,7 RAS 4,5
I liii
16K
CAS 5,7 RAS 6,7
SL
f .9
,
=== o =====
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
f
i
LOW ADDRESS
(20XX - 3FXX)
and HIGH ADDRESS
(80XX - 9FXX)
RANGES
1817161514131211109 8 7 6 5 4 3 2 1
MIDDLE ADDRESS
(4OXX - 7FXX)
RANGE
Apple Computer Inc · 1982
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11h11!
.1
-
IL1I!UT1iI Ipz_I
-
_____1
:tnwxxY IZZZ1
-R cti
FAI
ffli= :ñ JLELI l
Am
_- _¿
;
,i*
rf
1V)
riznJlnlztii!u1ngfJijliUtmWiuJi':
o
W
r-1
!(D
U
(WLJUZ1IWg' tX1fZ*&n
''
I
,f
-_LIRX1 f TL'21j.IE
r'
Vrw? g_B.aIw! iil 11u..a I
,4flilW I
o
r
2.21.
Apple Computer Inc · 1982
Page 0041 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
HOW TO READ PROM (ROM) LOGIC EXPRESSIONS
X' - The single quote at the end of an expression means that the state of the signal is true when low, or it may represent the inversion of the state of the signal.
* - Defines a logic AND operation. The expressions on either side of the asterisk is ANDad.
+ - Defines a logic OR operation. The expression on either side of the
asterisk is OR'd.
() - Defines the boundaries of a logic expression. A new expression is defined by what ever is inside of the brackets.
RULES FOR INTERPRETATION
Always interpret (transform) the expression within the brackets first. Interpret AND (*) logic operations before OR (+) operations.
EXAMPLE:
Given: INPUTS: AIISW'
MIX VBL
HIRES V2
TEXT V4
OUTPUT: DRIRES - (AIISW*HIRES*ÇrEXT+MIX*V2*V4) '+AIISW'*HIRES)*VBL'
LOGIC REPRESENTATION:
MIX E1»
TEXT
All SW HI RES
DuRES
VBL
2.22
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
A-All 8-A13
CA14
D-A15 E-R/WN
F- DHIR.E S
G-AY' H-ABK2 t-PItAS1,2
J-PR.ASO, 3
DO-PCASO' D 1-PUSELE D2-PCAS3 D3-PCAS3'
PCASO'-(PRASO, 3 * (DILIRES' *Ay' +AY* (A15'* A14' * A13' *All' *R/jN' + A15' *A14' *A13'* R/WN+A15*A14'*A13' *AJt)))
PUSELB-PRASO, 3 * (A15' *A14' *A]3' *Al1 +A15 *A14 *A13' *Al1' +A15 *A1 *A13) +PBASO, 3 *PR1, 2 *(AJ5' *A14' *AJ3+A15* A14' *AJ3') +PRASO, 3 *pp,AS, '*(AlS' *AJ4' *A13+5' *Aj4 *A13') +PRASO, 3 '* PR.AS1, 2
* (A14' *A13' +A14 *A13) +PRASO1, 3 ' *pp, 2 ' *A14'
PCAS3-PRASO, 3 * (DEIRES ' *Ay ' + AY' (A15' *A14' *A13' *Al1 + A15 *A14 A13' *A1l' +A15 *A14 *A13))
PCAS3'-(PRASO,3 * (DRIRES ' *Ay' +AY* (A15' *A14' *A13' *All+A15 *A14 *A13' *Al1' +A15* A14* k13)))'
314
14
PR 112_.L A APZ _LL A? 12
D,
R D HIRES_L A,
M-
AIS i A
..L P.14
AZ
A13..í.*s
AIL.L
G,f
t2.
D3
2.23 -I
Apple Computer Inc · 1982
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's
A-A13 BsA11 C-A15 D-PR.ASO,3 E-DRIRES
F- ARK i
G-ABK2 H-ABK3 I'Ai4 J-AY'
DO-PCAS4 , 7'
D1-PCAS5,6' D2-PCASL' D3"PCAS2
PCAS47'- (AY*PRAS0, 3 * (ARKI*ASK2*ABK3'+ABK3* (ABKI' + ABK2'))* (A15' *A14) +AY* FRASO,) '* (ABK1' *AßK2*ARK3'*A14+ARKj*ABK2*A3K3'+K2 *ARI(3+ARK1' *K2*ABgj*A15') *(A14' *A13+A14*A13))'
PCAS5,6'. (AY8PRAs0,3 *(K1*ARK2*ARK3' +ABK3* (ABKL' +ARK2'))* (A15'*A14' *A13+A15*A14' *A14'*A13') +AY*PR.ASO, /3 '*(ABK1'*ARK2*ARK3' *A15+ ABK1*A3K2*ABK3*'+ARK2'*ABK3+ABK1l*Kj*ARK3*A15?) *(A14' *A13'A14* A13))'
PCASI' - (DRIRES *Ay'+Ay*pO 3 * (ABK3' * (ABKI'+ABKZ') +ABKI*ARK2*ABK3) * (A15'* A14' *A13+A15*A14' *A13') +AY*PR.ASO, 3 '*(2' *I3'+ARK1' *K2*ARK3'*Aj5') * (A14'* A13'+A14*A13))'
PCAS2' - (muREs *Ay' +AY*PRASO,3 *(K3'* (ABRi' +ABK2') +ARKI*ABK2*ABK3) *A15'* A14+AY*PRASO,3 '*(AB'*ABK3'+ABKi'*ABK2*ARK3P*Ai5) *(A14'
Av
*14 l A8)3 A8PZ
A8PU q DI4WIE.5
AIS
All
A13
Dø
*i C13
A
Dl
AS
M
M DZ
M
N
D3
£
2.24
Apple Computer Inc · 1982
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4acompr
RAS 258
A-ABK1 B-ABK2 C-ABK3 D-PA15 E-AY' F-PA8 G-ZPACE' }I-DHIRES t-RFSt J-ABK4 DO-PRASO, 3 D1-PRAS1,2 D2-PRAS4,5 D3-PR.AS6,7
PRASO,3 - AY'* (DRIRES' +RFSII) + ((ABK4* (zPAGE*PA8')'Y+ABK4* (zPAGE*PA8)' *AEK1* ABK2*ABK3)*AY FRASi ,2-AY'+AY PRAS4,5_AY'+AY*(ABK4* (ZPAGE*
PA8')')'*(AßK1*A3K2*ABK3'+ABK1'*ABK2*ABK3' *pA15+JK1'* A3K2'*PA15' +AZK1*ABK2*ABK3) PR.A56 7 +AY'*DHIRES'+AY* (K4*(zpAcE*pA8' )')'* (ABKI* (ABK2' +ABK.3')) +AY*AZKA* (ZPAGE*PA8')'* (p5'*K1* (ABK2' +ABK3') .FpM5*Ki'* (Ax32' + ABK3'))
4I
ftF5
RDHR
ZPAG PAB AY
PM54
7
2.25
Apple Computer Inc · 1982
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corn* r
RAS.2.TEXT
A-ABK1
BA3K2
C-ABK3 D-PA14 5 E-AY' F-PA8 GaZPAGE }L-DHIRES
I-RI S H
J-A8K4 DO-PRASO, 3 D1-PR.AS1,2 D2-PRAS4, 5 D3=PRAS6, 7
PRASO, 3 'AY" (DHIRES'+RFSH) + ((ABK4* (ZPAGE*PA8')') ' +ABK1*ABK2*ABK3) *Ay
PRASI,2 AY'* (DHIRES+RFsH) AY* (ABKI'* AKB2'*ABK3'* (ABK4* (zPAGE*PA8') '**pA15)'+Kj*A3K2*3) +AY*ARK3'* (ABKI'* AK2* ABK4* (ZPAGE* PA8') '*pA15+K1*K2*(A3K4* (ZPAGE*PA&') *pA15)')
PRAS4, 5 RFSH*AY'+AY*ABK2' *ABK3' * (ABK1 '*ABK4* (ZPAGE*PA8') 'PA15+ABK1* (ABK4* (zPAGE*PA8') '*pA15)')
PRAS6,7 RFSH*AY'+AY*ABK3'* (ABK1*?BK2'*ABK4* (ZPACE*PA8') '*pA15+.3Kj '* ABK2* (AK4* (zPACE*PA8') '*pA15)')
¡IBM
ABK.
-- 3q)-oGq.
AK4J A RF5IrJ.A,
RDHIRE..!L
¿PAGE....LA
PAS ..LA
DDØ1413
02(-z
7 c,i 'A$ D3-
2.26
Apple Computer Inc · 1982
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mp*' uc.
B-Al 2 C-Al 3
D-A14 E-IOSYNC F-SEL2M'
GABK4
}I-PA8
I-15 K-PAGE' DO-S399 Dl-PRDY' D2-LND'
S399ZPAGE*PA8' *A15' *A14' *A13' *AJ2* All
PRDY'-IOSYNC *Jj4 *ABK4
'Y IND'- (ABK4* (ZPAGE* PA8')
PAGE
MS
PAB
AB4
5 EL M EO5YJC
A 14
A%3
A a
34)-9Ø43
A9 AS A7
A5 A4 A3 AZ Al
5399
1MO NC.
2.27
Apple Computer Inc · 1982
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U175 1. TEXT
A-VA B-VS C-VC D-VAl E-VBI
F-VC]. G-DH IRES
HSCR
I-WE2114' J-VBL DO-MUXI D1-MUX2 D2-MUX3 D3-ENHREG'
MUX1-(DHIRES' +SCR * (vA* VAl' 1-VA' *VAI) + SCR' *VA) * (VBL' + WE2114) +VBL * WE2114'
MUX2=DHIRES* (sCR* (VA* VA1* (VB* VB!' +VB'* vsi) '+ (VA* VA1Y* (VB* VSI' +vB * VBI) ) +VB* SCV)
MUX3-DHIRES * (SCR* ((vA* VA1* (VB+ VSi) +VB* VB! )
* (vc* VC1'+VC'* VC!)
'+(VA* VA1* (vs+ VSi) 1-VB * VB!) '*(vc * vci) ) +VC* SCR')
ENHREG'-DHIRZS' *JE2 114'
3LItØØ,:
'I BL
WE2.I14
5CR tT
D HI RES
VC
VP"-
VC -
VB
VP'
2.28
'-I
Apple Computer Inc · 1982
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Apple Computer Inc · 1982
(p.i) (ANI< REGISTER -
IRQ
_] Iii ENVIRONMENT RE&ISTEJI
REETE#1 4
PRIfr1 STACKIL
FFEF
o
FFFbF
"ç
I
PCH
'5.
t
I0000
FFOO-J
2P1
000/
SOUND REG. I r o
FFEO
roN/Ir
NPL/ REGISTERS
A
f - ACCUIIULATOR
a
y
I -INDEX REGrSTER V
D
X
I -INDEX REc3rsrER)(
o
PCI-.
I -PROGRAII COLJNTEÑ
a
I-ZERO PAGE PEG.
o
s
(-STACIZ POINTER
L f $1D1T14c I - PROCEÇSOR TATVS REG. CARRY 2ERO
1RO DISABLE
> DECl/IAL 1100E BRK C0IIIIAND
) OVERFLOW
>NEGATIVE (S'ti)
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Apple Computer Inc · 1982
I/O DEVI STIBES
OX Ix 2X 3X zX 5X 6X
iX
8x 9X
AX BX Cx DX EX FX CoXX
KEYBOARD READ RESET KEYBAORD N.0 Speake Toggle Beeper Display Regiater Switch Register Real Time Clock N.C.
Slot 114 DEVSEL
I/O CONTROL REGISTER DISK REGISTER ACIA
EEYBL14JJ flTA
O
ASCI IO
i
ASCI II
2
ASCI 12
3
ASC1 13
4
ASC1 iI4
5
ASC1 15
6
ASC1 16
7
KBO FLAG
C000
JEYBOARO STAÌ1JS
O i 2 3
4
5 6
cOo 8
ANY KEY DOWN SHIFT CONTROL
CAPS LOC K
APPLE I APPLE II KEYBOARD PRESENT ASCI17
CAl
CA2
CB i
CB2
L
FFDX
SLOT INI. SWI/MARGIN INi') SERVICE CLOCK ILENTYPE SERVICE DATE/PDL
VIA
CAl CA2
CB i
CB2 FFEX
Rl CLOCK INT. KEYBOARD UNIT VERTICAL BLANKING VERTICAL BLANKING
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Apple Computer Inc · 1982
BANK PAGE REGISTER
O
L
2 3
14
SLOT i INI.
5
SLOT 2 INI.
6
7.
FFEF
SOUND REGISTER
O
i
2 3 4
7
FFEØ
SO
Si SOUND DAC
S2
S3
51;
S5
DISPLAY REGISTER
o - CO5 1/IO
DSPO
3/2 1 - DSP1
5/te
2 ......PAGE 2
7/6
3 - DSP3
9/8
4
EN SERCTRL
B/A 5 - ZEROSCO/PDL2
D/C 6 - POI ENBL
F/E
7
SER CTRL/PDL1
CØ5X
DISK REGISTER
COE 1/O 'DPHO/SCRO
3/2
i
DPH 1/S CR1
5/14
2 - DPH2/S CR2
7/6 3 DPH3
9/8 4 MOTOR TIMER
B/A
5 - INTIEXT SEL
DIC
6 - DISK CTRL 1
FIE
7 DISK CTRL 2
CØEX
I/O CONTROL REGISTER
COD 1/10 0 - EXT SELO
3/2
5/4
- EXT SELl INI SEL
7/6
- SIDE
9/8
eNBL SCROLL
B/A
ENBL CHAR WRT.
0/C
SER CIK OUT/k
F/E
7SER DATA OUT/IN
CØDX
SWITCH REGISTER
O
SWO
I. - SW1/MRGN SW
2 -. SW2
- 3
SW3/SER CLK
- 4
SLOT 3 INI
5 - SLOT 14 tNT
6 PDL TIMEOUT
7
C06x
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
É
Apple /// Computer Information
Apple ///
Service Reference Manual
Section I of II . Theory of Operation Chapter 3 The Versatile Interface Adapter (VIA)
Written by Apple Computer. 1982
Apple Computer Inc · 1982
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THE VERSATILE INTERFACE ADAPTER
OENERAL
I/I, The Versatile Interface Adapter (VIA), as used in the Apple
is a very
flexible I/O control device which minimizes the discrete control circuitry on
the Main Logic Board. There are two VIA. used in the system.
Each VIA contains two 8-bit I/O ports, a serial port, and two 16-bit interval
timers, as shown in the VIA Block Diagram. Each of the sections is very
III, flexible and can be utilized in many operating modes. In the Apple
however,some of these modes cannot be used because of certain hardware design
considerations.
Control of peripheral devices is handled primarily through two 8-bit bi-directional ports. Each line can be programmed as either an Input or an output. Several peripheral E/O lines can be controlled directly from the interval timers for generating programmable frequency square waves, or for counting externally generated pulses. To facilitate control of the many powerful features of this chip, an interrupt flag register) an interrupt
enable register, and a pair of function control registers are provided.
Before we get into a functional description of how the VIA is used in the
Apple ¡/1, lets first go through a pin description of the it.
VIA (6522] PIN DESCRIPTIONS
RES* (Reset) (34)
The Reset input clears al]. internal registers to logic O (except Ti and T2 latches and counters, and the shift register). This places all peripheral interface lines in the input state, disables the timers, shift register, etc., and disables interrupting from the chip. On both VIA. this pin (34) is connected to the RESET* of the system. The system generates the reset at power on, or at depression of the Reset switch in conjunction with the Control key. (Note the latter may be disabled.)
02 (Input Clock) (25)
The Input Clock i the system PREDI (PRE-i MHZ) clock which operates at 1MHZ and is used to trigger all data transfers between the system processor and the VIA. The PREDI, developed in the system timing circuits, is used within the device to clock the various functions of the registers and timers.
3.1
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comptarmc
Oat.
Oat.
Sta
5.4
attifa'
de Cs, ------
RSO
as,
052 053
Ch.Ø
Acciai Cøt.o1
iliamie, Cont.oI Fissi licol
UERI
Funcbo,. Conatol
Th? t
Laici.
latch
+ mL-Ht
Cairn..
mt-u
Ccwn..
(TIC-Ht
mc-u
Tim.. 2
fLatch 1T2L-LI
Catitis.
112C-HI
IT2C-Ll
Port A Maglia'
Unici Latch
Ociptil 10MAI
Oat. 0*. DOMAI
I
NondVtaks Co.,t.ol
Pat A
Pitt S
Si..tt M.g.it.,
(SRI
P.t a
tipi? Latch
Oulpil
10001
Osti Oir
boast
Block Diagram of the 6522 Versatile Interface Adapter
Stiff.,,
IPAI
Stiff...,
(P01
Po.tA
CAl CA2
C52
po..? s
Addressing 6522 VIA Internal Registers
Select Lin..
RI
Addrus.d Location
0EV DEV+1 DEV+2 0EV+3 DEV+4
DEV+5
DEV+6 DEV+7 DEV+8
°
DEV+9
DEV+A DEV+B DEV+C OEV+D DEV+E DEV+F
0 0 0 0 Output register lcr I/O Port B
O O O i Output register for I/O Port A. with handshaking
O Q 1 0 /0 Port B Dala Direction register
O O i i I/O Port A Dala Direction register
O i Q O Reed Timer I Counter low-order byte Write lo Timer i Latch low-order byte
O i O I Read Timer i Counter high-order byte Write to Timer t Latch high-order byte and initiate count
O i i O Access Timer i Latch loworder byte
O i i i Access Timer 1 Latch high-order byte i O O Q Read low-order byte of Timer 2 end reset
Counter interrupt Write to low-order byte of Timer 2 bui do not reset interrupt I O O i Access high-order byte of Timer 2. reset
Counter interrupt on write
i O i O Serial I/O Shift register
i O i i Auxiliary Control register
i i O O Peripheral Control register i i Q i Interrupt Flag register
i 1 i O Interrupt Enable register i 1 1 i Output register for I/O Port A. without handshaking
3.2
I
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ad/Write) (22)
The direction of the data transfers between the 6522 and the system processor i. controlled by the R/W5 line, which is driven by the Internal Read/Write, t R/W*, signal generated by the processor.
If pin 22 is low, data will, be transferred Out of the processor into the selected VIA register as in a write operation.
If R1W is high, data will be transferred out of the selected 6522 register, as in a read operation.
D3O-DB7 (Data Bus) (33-26)
The eight bi-directional data bus lines (in the Internal Data Bus) are used to transfer data between the VIA and the system processor.
o During read cycles, the contents of the selected register are placed on the data bus lines and transferred into the processor.
o During the write operation, these lines are high-impedance inputs and data is transferred from the processor into the selected register.
o When the 6522 is unselected, the data bus lines are at high-impedance. These lines are connected to the Internal Data Bus and are not accessable from the outside world.
CS1, CS25 (Chip Selects) (24,23)
These two chip select lines are connected to direct decodes of the processors address bus.
o CS.1 on both VIA. is controlled by the signal CS6522, a signal which is qualified by other system consideration.
o CS2 is driven by the signal FFDX for IC at location B5, and FFEX for 1C9 at location B6. The selected VIA register will be accessed when CS]. is high and CS2 is low.
RSO-RS3 (Register Selects) (38-35)
The four Register Select inputs permit the system processor to select one of the 16 internal registers, each of which performs a specific function, of the VIA as shown in the accompanying table.
IRQ (Interrupt Request) (21)
The Interrupt Request output goes low whenever an internal (to the VIA) flag is set and the corresponding interrupt enable bit is at 1. Thu output is
3.3
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- I Apple /// Computer Information · Apple /// Level 2 Service Reference Manual open-drain" to allow the interrupt request stgnl to be wired-ORED" with other equivalent signals in the system.
PAO-PA7 (Peripheral A Port) (2-10)
The PA port consists of 8 lines which can be individually programmed to act as inputs or outputs under control of a data direction register.
The output is controlled by an output register. Input data may be latched into an internal register under control of the CAl line. All of these modes of operation are controlled by the system processor through the internal control registers.
On standard TTh load, these lines are present in the input mode. Conversely, on standard TTh load, they will drive in the output mode.
CAl, CA2 (Peripheral A Control Lines) (40,39)
I/I) The tuo PA control lines can act as interrupt inputs (as used in the Apple or as handshake outputs. Each line controls an internal interrupt flag with a corresponding interrupt enable bit.
PBO-PB7 (Peripheral B Port) (11-17)
The PB port consists of 8 bi-directiona]. lines which are controlled by an output register and a data direction register in much the same manner as the PA port.
The polarity of the P87 output signal can be controlled by one of the interval timers, while the second timer can be programmed to count pulses on the PB6 pin.
Peripheral B lines represent one TTh load in the input mode and drive one standard load in the output mode.
CB1, CB2 (Peripheral B Control Lines) (18-19)
The PB control lines act as interrupt inputs or as handshake outputs. As with the CA lines, each line controls an interrupt flag.
These lines also act as a serial port under control of the Shift Register. They have loading and driving characteristics identical to the CA control
lines.
3.4
Apple Computer Inc · 1982
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ADDRESS BUS
B
U /4
F F E R
ZERO PAG E REG.
ROM
4k
AO-
MPU
A8-A1 5 6502
/1--J
4
flUX Ni
PAGE
FFDX
VIA
6522
FF
VIA
6522
ACIA
6551
B
4
U F
MUX
F
8
E
R
A T
DATA BUS
.1/O
IÇEYBOARD
DisK CONTROL LS138 (DECODE) WRjT DATA TO RAM 1/u (SONNECTORS
INTERNAL DATA BUS
L__i I CALS I
3.5
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é3pkzII
VIA FUNCTIONAL DESCRIPTION
Port A and Port B Operation
Each 8-bit peripheral port has a Data Direction Register for specifying whether the Peripheral pins are to act as inputs or outputs.
o A O in a bit of the DDR causes the corresponding peripheral pin to act as an input.
o A "i" causes the pin to act as an output.
Each peripheral pin is also controlled by a bit in the Output Register and a bit in the Input Register. When the pin is programmed as an output, the voltage on the pin is controlled by the corresponding bit of the output Register. A one in the ORX causes the output to go high; a zero causes the Output to go low.
Data may be written into OPI bits corresponding to pins which are programmed as inputs. In this case, however, the outpút signal is unaffected.
The IRB Register operation is similar to that of the IRA. For pins programmed as outputs, however, there is a difference. When reading the IRB, it is the bit stored in the ORB that is sensed. That means the buffering and gating on the two ports differ in respect to pins programmed as outputs.
See the figures below detailing the data bytes programmed into the DDRs and the two control registers for each of the VIAs. Compare these with the environments of each device.
Timer Operation
Interval Timer TI consists of two 8-bit latches and a 16 bit counter. The latches are used to store data which is to be loaded into the counter. After loading, the counter decrements at the rate of PRE1M.
Upon reaching zero, an interrupt flag will be set; if the interrupt is enabled, the IRQ* will go low. The timer will then disable any further interrupts, or vili automatically transfer the contents of the latches into the counter and vili continue to decrement.
In addition, the timer may be programmed to invert the output signal on a peripheral pin each tine it "times out." Each of these modes is discussed
below.
Timer i One-Shot Mode
The interval timer one-shot mode allows generation of a single interrupt for each timer load operation. As with any interval timer, the delay between the write Tic-H (FFD5, FFE5) operation and generation of the processor interrupt
3.6
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is e i..
u unction of the data loaded into the timer.
In the une-shot mode, writing into the high order latch has no effect on the operation of Timer 1. Rowever, it is necessary to assure that the low order
latch contains the proper data before initiating the count-down with a "write T1C-W operation.
When the processor writes into the high order counter o the Ti interrupt flag is cleared; o the contents of the low order latch are transferred into the low order Counter;
o the timer again begins to decrement at the PREIM rate.
After the timer reaches its time out, it continueu to decrement until it is
reset with the proper write operation.
The processor may read the current count of the timer to determine how long it hae been since the interrupt has been set. Reading the counter does not reset the interrupt flag or the timer.
Timer i Free-Run Mode
The most important advantage associated with the latches in Ti is the ability to produce a continuous series of evenly spaced interrupts. These interrupts are accomplished in the "f ree'-running node."
In the free-running mode, the interrupt flag is set each time the counter reaches zero. Rowever, instead of continuing to decrement from zero, the timer automatically reloads the contents of the high and low latches, and continues to decrement from there. In this mode, the interrupt flag can be cleared by writing TiC-H, or reading Tic-L., or by writing directly to the interrupt flag.
It is not necessary to rewrite the timer to enable setting the interrupt flag on the next time-out. All of the interval timers are retriggerable." Rewriting the counter will always re-initialize the time-out period.
Timer 2 Operation
Timer 2 operates as an interval timer in the one-shot mode only, or as a
counter of negative pulses on the PB6 peripheral pin. A single bit in the ACR is provided for this mode selection.
Timer 2 is comprised of a write-only low order latch, a read-only low order counter, and a read/write high order counter.
Timer 2 One Shot-Mode
3.7 4,
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" an 'rval timer, T2 operates very much like TI in the one-shot node. netting of the interrupt flag, however, will be disabled after the first time out, and it will flot be set again until the write T2C-H operation.
The flag can be reset by reading T2C-L, or by writing T2C-H.
Timer 2 Pulse Counting Mode
In the pulse counting mode, T2 serves primarily to count a predetermined number of negative-going pulses on the P6 pin. This is accomplished by first loading a number into T2, which clears the interrupt flag and allows the counter to be decreinented by the pulses on PB6. The interrupt flag will be set when T2 is decremented to zero. The counter will continue to decrement.
Note that it is necessary to rewrite the timer to re-enable the subsequent interrupt flags.
Shift Register Operation
The Shift Register performs serial data transfers into and out of the CB2 pin
under control of an internal modulo-8 counter. Shift pulses can be applied to the CBI pin from an external source or, with the proper mode selection, shift pulses generated internally will appear on the CB]. pin for controlling external devices.
The control bits which set the various register modes are located in the ACR. In total, there are eight modes for this register. The primary use of the shift register is control of the serial printer port.
In the FFEX VIA, the shift register can be activated to 'count 8 VBL (Vertical Blanking) pulses. The shift register sets its interrupt flag each
time it completes 8 shifts.
Refer to the figure below for descriptions of the various modes of the shift register.
Interrupt Operation Controlling interrupts within the VIA involves three principal operations. These are:
o flagging the interrupts o enabling the interrupts o signalling the processor that an interrupt conditton has occurred. Interrupt flags are set by interrupting conditions which exist within the chip, or on inputs to the chip. These flags normally remain set until the
3.8
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interrujt has been serviced by the processor. To determine the source of an interrupt, the processor must examine these flags in order from highest to lowest priority.
Procedure:
i. Read the flag register into the accumulator.
Shift it right or left.
Use conditional branch instructions to detect an active interrupt.
Associated with each flag bit is an enable bit. This can be set or cleared by the processor to enable or disable the flag respectively. If a flag bit is enabled and set, it will cause the IRQ* output to go low, thus sending a direct request to the processor. In addition, bit 7 of the flag register is set to allow quick determination of which chip contains an interrupt condition.
The 1FR may be read directly by the processor. In addition, Individual flag bite may be cleared by writing a 1 into the appropriate bit of the 1FR. When the proper chip select and register controls are applied to the chip, the contents of the 1FR are placed on the Data Bus. Bit 7 indicates the condition of the IRQ output, however it cannot be directly cleared; all other bits must be cleared in order for this bit to become inactive.
For each interrupt flag in the 1FR there is a corresponding bit In the
Interrupt Enable Register. This is accomplished by writing to the IRR. There are two steps to consider: the enabling write cycle and the disabling write cycle. The cycle is determined by the logic state of bit 7:
o If bit 7 and the corresponding O-6 bits are at "1", the O-6 bits enable their matching flag.
o If bit 7 is a O, then the O-6 bits containing a "1" disable the matching flag.
Refer to the figures to see the data byte configuration and device.
3.9
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PPOflL
6522 VIA
,iLd Control
The description so far has been very general and has not completely detailed
I/I. the functions of the two VIAs within the Apple
However, one must be
familiar with the many registers and modes to understand how the VIA i.
utilized and how it can be configured for various operations.
The following figures and tables detail the environment and address locations of each of the registers and I/O pins for the two chips. (Many of the signal.
are common controls or busses; their descriptions relate to both devices.)
IDO-1D7
The data bus pins of the VEA are connected to the associated pins of the Internal Data bus. When the chip is properly addressed and selected, each of the various registers may be accessed for reading or writing data, control bytes, status or timer states. It is this bus through which all data passes to the system and/or processor.
Reset
The RES pin is connected to the RESET line. The system generates the reset at Power On or when the Reset switch is depressed with the Control key. (Note: the Control key may be software disabled.)
I R/W*
The R/W* pin is connected directly to the processors internal Read/Write line. This signal cannot be accessed from the outside world. It is obviously used to control the direction of the data to or from the device.
PRE1 M
The 02 clock pin i driven by the PRE1M signal developed in the system timing circuits. It is used within the device to clock the various functions of the registers and timers.
CS6522 This signal is developed under Rom decode of various address states or ranges and other mode selections, and drives the CSI line of both VIA..
AO-A3 The processors address lines directly drive the Register Select input lines.
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_kI il
Ç
-s
roi
3Z
y02
3
f*
,
pa, pa
4_- Res,L2tv,AWV.
I
,
t-'vV\- I
7,
BS
ro
4-Az
' o, *a
.4A3
2
1R/
-*j
CFbSFt2.,____ cSi
2
- ._3L4
ftf1
w- i pç
,t
.j_2_-4*,WtraSECe*M
I
P$
-LI
-z.
H
-ç
' , 's
p,'
i'VY
Aø
At
> 'V,RC'AJHE,ttr4 L
ZEqo P4G (Ps /8 _,',c)
sER;
FPDfi
pFf)!
FPD2
Registi, Numbe,
O
I
2
3
4
PD5 5
6
PP2)7 7
1C1C 8 8
Ffj 9
FFDA / 10
11
FIDC 12
FFDJ) 13
C 14
15
RS3
O O
0 0 0 0 0 0
1 1 1 1 1
I
1 1
RS Coding RS2 RS1
O
O
O
O
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Regine,
RSO
Desig.
O ORB/IRS
i ORA/IRA
0 DORS
1
DORA
0 TiC-L
1 TiC-H
0 Ti L-L
1 IlL-H
0 T2C-L
1
T2C-H
0 SR
1
ACR
0 PCR
1
1FR
0 tER
1 ORA/IRA
Writ.
Description
Read
Output Register "B"
Input Register "B"
Output Register "A"
Input Register "A"
Data Direction Register "B"
Data Direction Register "A"
Ti Low-Order Latch.. j Ti Low-Order Counter
Ti High-Order Counter
TI Low-Order Latches
TI High-Order Latches
T? Low-Order Latches T2 Low-Order Counter
12 High-Order Counter
Shift Register
Auxiliary Control Register
Peripheral Control Register
Interrupt Flag Register
Interrupt Enable Register
Same as Reg I Except No "Handshake"
SV6522 Internal Register Summary
3.11
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pconiputarr
These four addresses, along with the two chip select lines, activate the chip for access to and from the data bus. You can see that the decimal equivalent of the address (Register Select) lines equals the register number, as detailed in the port address tables.
To determine the complete I/O location:
o Express the AO-Al bits in Hex
o Substitute the Hex expression for the "f in the signal name applied to the CS2 input.
IRQ*
The Interrupt Request line is a wire ORED bué, shared with the other LSI devices within the system which directly interrupt the processor. The VIA can generate an interrupt due to internal status and can be configured to interrupt on various input conditions. Each VIA provides indirect interrupts to the processor for the other devices in the system, including the slot interrupts. By polling the VIAs, the processor can quickly determine which device or group of devices needs servicing.
VIA (FFDX)
This VIA has the following responsibilities:
o Environmental Register
o Zero Page Register
o
obal Interrupt Request
o Serial Data Port Interrupt & Clocking (Silentype)
The signals of the IC at location B6 which are not common to both 6522s are either the port I/Os or the chip select line, CS2.
FFDX
This signal comes from the Device Select logic, and is true for the 16 address states, FFDO through FFDF.
The table below shows how the signal FFDX (CS2) and the Address Lines on the Register Select Inputs access each of the 16 registers within the VIA.
3.12
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r
Port A Description
The ORA for this device is also called the "Environmental Register" by the system. It is programmed to all outputs, and contains various control mode States which may be software modified.
PAO and PAl are used as software switches to control which set of Roms are to be used by the system, and also to indicate there is an expanded set of Rom in the system.
I/I PA2 provides the software switch that enables the Apple
to switch between
two memory stacks.
PA3 is a software switch which will enable or disable the system for writing into the Ram. It can be set for entire banks or it can be set at will to disallow writing into memory.
PA4 is a software switch which will cause the function of the Reset switch to be ignored, and will simultaneously disable the Non-Maskable Interrupts from the I/O slots.
PA5 contains the switch "Scm" (Screen) which is used to modify the Blanking signal.
Global IRQ
The CAl line is connected to "OR' function of the slot IRQs. If any slot is requesting an interrupt, this line will toggle. The VIA then generates an IRQ and sets the associated Interrupt flag.
Swl/Mgnaw
This line connected to the CA2 line can be programmed to cause an interrupt on either edge of transition. It could be used to have a Function Only run while the switch is depressed, or vice versa.
SCO/ SER
These two signals form a very elementary serial data port. They are usually programmed as data, and strobe to a serial RO printer.
The port may also be configured as a serial input register or simply as interrupts for the two external lines. SCO/SER are connected to CB1 and CB2 respectively.
ZO-Z7 (Zero Page Register)
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700
ro'
Uro,
105
¡C'.
107
A.
r
FFEX
. ZR q
;f, JJ
UD e
3*
Mt
85 s
27.04
Z?. 75¿ r
Z
2. ,,, i,
.3' ;33_
12
3
?b3 *3
22
fled
25:
$
az
Fe "
s.e-e- *7 L
'4NK
*,aI.
. 6cu,3 J
>AIlRlQs"3
IR
TClt4&
SOc/,t'D 75G/LS rE1
RET
VL YER77.4. t4N/c%4'&
f Registe,
o
P'E /
2
FFE3 3 PFE4 4 FPE5 5
8
,CES
7
8
1F,EE?'4 io
E/EPEECB
11 12
FicEZ 13
frFEE 14
15
RS Coding
RS3 P52 RS1
o
o
o
o
o
o
o
o
i
o
o
I
o
i
o
o
I
o
o
I
i
o
I
i
I
o
Q
i
o
o
io i
I
o
I
i
o
I
o
ii i
Ii i
Register
RSO
Cesig.
o OR 3/IR B
i O RA/I RA
o DORS
D D RA
o Ti C-L
Ti C-H
o T1L-L
i IlL-H
o T2C-L
i T2C-H
o SR
I ACR
o PCA
1FR
o
ER
i ORA/IRA
3.1.4
Description
Writs
Read
Output Register .-B
Input Register "8"
Ouut Register A
Input Register A
Data Direction Register "r
Data Drection Register A
Ti Low-Order latches TI Low-Order Counter Ti High-Order Counter
Ti Low-Order Latches
Ti Htgh-Order Latches
T2 Low-Order Latches
12 High-Order Counter
9ift Register
12 Low-Order Counter
Auxiliary Control Register
Peripheral Control Register
Interrupt Flag Register
Interrupt Enable Register
Sai-ne as Reg i Except No Handthae'
-j
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pa - m
The PB port is referred to as the Zero Page Register. In other words, its primary function is to store the current "Zero Pa3e" of the memory. The Apple
11/ is capable of moving the Zero Page, a feature which greatly enhances the
flexibility of the system.
The PB port baa a secondary function; it also serves as the address register for the Real Time Clock. The RTC muet have the addresses stable for an extended period of time, so instead of adding another latch in the hardware, the designers use this port for control.
Note that each time the port is used for the RTC function it i.ust be restored to the current Zero Page setting.
VIA (FFEX)
This VIA aids in providing the following:
o Bank Switching
o Sound Register
o Interrupt Recognition-clock, keyboard
The signals connected to the VIA located at 85 which are not common to both VIAs are:
o the A and B port I/Os, o the port control lines, and o the CS2 line.
FFEX
This signal corresponds to VFDX in that it is true for a group of 16 addresses. See the corresponding table fer the complete detail of the
register access locations.
Port A Description
The PAO-PA2 lines are configured as outputs and contain the software switches for the Rae banks. Currently, the system segregates the 128K memory into three banks. The decimal decode of the binary bit weight reveals the bank.
The PA4-PA7 lines are configured as inputs. Slot 1 and 2 tRQs, the Solid Apple switch, and the IRQ line itself form the respective inputs.
If its interrupted, the processor will poll the VIAs first to get a quick look at most of the system. It can then identify and service the requesting device faster, since it doegnt need to poll each individual device.
3.15
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ppIacomp*ari
The processor can, at certain times) read this port for the status of the special Apple switch on the keyboard without disturbing the keyboard circuit.
The IRQ* signal is wrapped around to the PAl line for special diagnostic purposes.
CLK IRQ*
The Real Time Clocks interrupt is connected to the CAl line, which is programmed to be a negative edge active input. When the clock generates an interrupt, it will set the IRA flag in the 1FR. The PA port is conditioned for non-latching, however, resulting in a basically independent interrupt for
the clock.
Keyboard Interrupt
The keyboards interrupt is connected to the CA2 input, which is programmed to be an independent negative edge interrupt. It will set Bit O in the 1FR and cause the IRQ* line to go low.
Note: The keyboard can, for the most part) be disabled by disabling the interrupt flag for the CA2 line.
VBL (Vertical Blanking)
This input can perform two functions, depending on how the CB1, CB2, and Shift Register are programmed.
o The system may want to be interrupted at each vertical blanking cycle. 1f so, you would program the CB2 line to be an independent interrupt OR let it strobe the IPS and set the corresponding bit flag.
o The system may want to synchronize an operation to the display, but may not want to be interrupted at each VBL. If this is the case, the system can configure the Shift Register to count 8 occurrences of the VBL signal. An interrupt will then occur after each set of 8 Vertical Blanking cycles (about once every second), in sync with the display scan.
PB Port Description
The first 6 lines of the B port are configured to be outputs. They are inputs to the Sound Generator.
o The tone generated at the speaker can be varied by changing the bit values of these lines.
o There are 127 possible tone combinations; the missing one turns the tone off completely.
3.16 4,
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r pI con* vi
PB6 La connected to the I/O Count line. Depending on the device in the slots, the VIA may be programmed to count a certain number of pulses generated or to determine that only one pulse occurred. Either way, the VIA will generate an IRQ and set the appropriate bit flag.
The last bit is uaed to monitor the !*iI (Non Maskable Interrupt) line
generated by the device, in the I/O slots.
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VA APPENDiCES
FFDØ/EØ REG O - ORB/lAB JJoJ L_
'Si
PU2
PS3 OUTPUT REGISTER °p° ORSI
'54
OR
INPUT REGISTER "5° ¿ORS)
Pli
'IS
's,
Ono. O...no..n
WRITE
READ
DORS. .....(OSJTPUTI
DORS. "L"IIPdPSJT) /1 no..i I.tc0.. dUbNdI
OORB 0' IIPOPUTI
lop., tolnh ...bIpd(
UPU.ItpoOVIp,.IL,.0. UPU,.. o.Ip(nI..*i..bn
10051
0 ORI P.n (no.) .. no (Ion.
UPU *,,Ipoo,,.ORIN,.t UPU lOodS,nP,.lIno.4.nPS
I,. If Ion o. ,.nI...I, 001,1 ØlR.
DORS tI..n,.d
UPU 'nod, IRS b.,. 00,CI, 1
W. no.1.1 It. P5
IP,o
lllOo OlINO l0ll CIT odo.
Figure 9. Output Register 8 (ORB), Input Register B (IRS)
REG 12PERIPHERAL CONTROL REGISTER
CR2 CONTLOL
7 0 S OPI LATION 0 0.0 INPUT NEGATIVI ACTIVE LDGI 0 01 I INDEPENDENT INTERRUPT
O 1 0 yNPU0 POSITIVE ACTIVI £061
o lIOEND(NTIl0T(RRUPT
I
INPUT P00 (DGL
I 00 II*I*OSI*AIE OUTPUT
i !0T PULLI OUTPUT
i 1 O LOWOUTPUT
11111 I.IIGIIOUTPUT
CII INTIOOUPT CONTROL
0. '.(CATIVE ACTO.II (DGL - 'OSITIVE OCTIVI L DGl
CA! INTLIRUPT CONTIOL
O. NEGATIVI ACTIVE (DGL O POSITIVI ACTIVE SOGE
CA2 CONTROL
7 IT OPERATION O S T INPUT NEGATIVE ACTIVE EDGE
o 0 1 INOEPINOENT INTERRUPT
INPUT NED EDGO S S L INPUT POSITIVE ACTIVE EDGE o I I I001PIP,OIPIT INTEROLIPT
INPUT POS IDOl 1 0 0 IANOSII*0E OUTPUT
I O i PULSI OUTPUT
1 1 0 LOW OUTPUT 5 1 1 111GO OUTPUT
Figure 14. CAL CA2, CB1. CB2 Control
REG 10 SHIFT REGISTER PFE,4'4
L 1716151413 121u101
REG 1 ORAfl.
FrE1/Di
lIAI
PAT
PA? OUTPUT REGISTER A° (ORAl
144[
ON
INPUT 010ISTIR "A lIRAI
PAS
PAS PA7
Dot. D,,.cuon S.I.t1 not
DORA "I (OUTPUT) II...,, (nl,h.., d,,.bl.dI DORA "I IOUTPUTI IInp*I I,,IIo.nR ....o4.d)
RRIT(
UPU flI0S O.'.o.ot Ln.I (DRA)
0(AD
UPE) ..d IeooI on PA p.o.
UPU .od, IRA t SIlO (pool & IP,. PA p.. oS tIp. 10lO& II,. I.. CAS poS,..
DORA '0" (INPUT) Inp5 I.IeIVt., d-..bI.dI
DORA 0 (INPUTI lInp*t 10.011.0, .0*bIndI
UPU nol,0 n! ORA b,00 UPU ,.00, (p.0. onPA p.ot. no HIPO pfl p'. .pnI, OlIVI ODRA thl,lptd
UPU If101 IRA 0* 0100.111 III. 10001 .f SI.. PA p.. ot II,. 1110*0110. Int CAO .ct,n.
Figure 10. Output Register A (ORA) Input Register A (IRA)
REG 2 (DDRB) AND REG 3 (DORA)
FFD2 I 1III 1211101
L___ P.o/PAIr
Pli/FAI
P12/PA2 P53/FA3 PS I/FAI
DATA DIRECTION REGISTER
"I OR "A DOMI/DONAI
PLO/PAL
'BIPAS
PS 7/PA 7
0' ASSOCIATED PS,A FINIS AN INPUT IHIGH IMPEDANCE)
"i ASSOCIATED PI/PA PIN IS AN OUTPUT.
WHOSE (EVIL IS DETERMINEDLY ORI/ORA REGISTER SIT.
REG 11 - AUXILIARY CONTROL REGISTER
i6$/Eß
171h1514l3l2lh101 I I,
SHIFT REGISTER BITS
NOTES. T WHEN SHIFTING our BIT 7(5 THE FIRST BIT
OUT AND SIMUILONEOUSLY IS ROTATED LACK INTO LIT Q. 2 WHEN SHIFTING I'4 BITS INITIALLY ENTER LITO ANO ARE SHIFTED TOWARDS LII 7.
LSHIFT REGISTER MODE CONTROL
43 2
oO O
oo i
OTO
Ot1
iOO
101 I IQ
i ii
OPERATION DISABLED SHlFTINUNOERCONTROL0PT SHIFT IN UNDER CONTROL OP 'I
SHIFTIP4UNO(RCONTROLOFEXTCLK SHIFT OUT FREE RUNNING AT ¡2 RATE SHIFT OUT UNDER COT,TROL OF T2 SHlFT0UT1jNDERCO.'TROLOP,., SHIFTOUTUND(PCOT.TROLOFEXTCLK
Figure 22. SR and ACR Control Bits
3.18
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Two bits are provided in the Auxiliary Control Register (bits 6 and 7) to allow selection of ho Ti oper-
ating modes. The four possible modes are depicted in Figure 17.
REG 4 TIM!R I LOW-ORDER COUNTER
L 1' 1s1413121u101
47
REG 5TIMER i HIGH-ORDER COUNTER
I'I'I111I1J1 t'ZS,/46
512 1024
COUNT VALUE 1$
33
.4
2043
40.4 uSE
COUNT VALUE
327
WRITE - S SITS LOADED INTO TI LOW-ORDER LATCHES. LATCH CONTENTS ARE TRANSFERRED INTO LOW-ORDER COUNTER AT THE TIME THE HIGH. ORDER COUNTER IS LOADED IREG St.
READ SlITS PROM TI LOW-ORDER COUNTER TRANSEERREDTOMPU. IN ADDITION. TI INTERRUPT FLAG IS RESET SITS IN INTERRUPT FLAG 5501511Ml.
WRIT! - S SITS LOADED INTO TI HIGH-ORDER LATCHES. ALSO. AT THIS TIME SOIN HIGH AND LOW-ORDER LATCHES TRANSFERRED INTO TI COUNTER. TI INTERRUPT FLAG ALSO IS RESET.
READ - S BITS P110W TI HIGH-ORDER COUNTER TRANSFERRED TO U.
Figure 15. 11 Counter Registers
REG 6 - TIMER i LOW-ORDER LATCHES
7/E 7
REG 7TIMER I HIGH-ORDER LATCHES
4c',1Ec.
1101
1h1h14131211101
4
S
COUNT
IS VALUE
32
.4
132
25S
512
1024
2045 - COUNT 4040 VALUE
5112
.3.4
32755
WRITE S BITS LOADED INTO TI LOW-ORDER LATCHES. THIS OPERATION 5MO DIFFERENT THAT A WRITE INTO REOS.
READ - S BITS FROM 11 LOW-ORDER LATCHES TRANSFERRED TO NPU. UNLIKE REGS OPERATION. THIS 00ES NOT CAUSE RESET OPTI INTERRUPT FLAG.
WRIT! - S BITS LOADED INTO TI HIGH-ORDER LATCHES. UNLIKE REGS OPERATION NO LATCH-TGCOIJNTER TRANSFERS TAKE PLACL
MEAD - I BITS FROM TI HIGH-ORDER LATCHES TRANSFERRED TO MPU.
Figure 16. Ti Latch Registers
FPDC /E
REG 11 - AUXILIARV CONTROL REGISTER
TI TIMER CONTROt
7 S OPERATION
O O TIMED INTERRUPT EACH TIME il IS LOADED
0 1 CONTINUOUS INTERRUPTS
I Q TIMED INTERRUPT EACH TIME Tl II L DA DI D
1 I CONTINUOUS INTERRUPTS
PS?
DISASLED
ONE-SHOT OUTPUT SOIJARE WAVE OUTPUT
T2 TIMSR CONTROL
S OPERATION O TIMED INTERRUPT
COUNT DOWN WITH PULItI ON PSI
PA LATCH ENASLE/DISASLE
P,
O DISASLE
I EMASLE LATCHING
SHIFT REGISTER CONTROl.
4 2 OPERATION
O o 011a IL S D
o
SHIFT IN UNDER CONTROl. OP TI
o o SHIFT IN UNDER CONT SOL OF 03
o
SHIFT IN UNDER CONTROl. OF EST. CLK
o o II-lIFT OUT FREE-RUNNING AT T2 RATE
o SHIFT OUT UNDER CONTROL OF TI
o 5HIPT OUT UNDER CONTROL OF 02
SHIFT OUT UNDER CONTROL OF IST CLE.
Figure 17. Auxiliary Control Register
4ote: The processor does noi write directly into the low order counter (TiC-L), Instead, this half of the Counter is loaded auto. matcally from the low order latch when the processor writes into the high order counter. In fact, it may not be necessary to write to the low order counter in sonic applications since the timing operation is triggered by writing to the high order cOunter.
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Ft s/t- REG 8- TIMER 2 LOW-ORDER COUNTER
5J
IJ lJ L_1-
Z
4
U
COUNT
VALUE
is
2$ sa 125
WRITE - I DITS LOADED INTO T? LOWOROER LATCHES.
READ - t litt FROM T2 I.OWOROER COUNTER TRANSFERREOTOMPU. T2IMTERRUPT FLAG IS RESET.
FO4D REG 13- INTERRUPT FLAG REGISTER
I ziilof
171615141
SET BY
CLEARED BY
r.,
-Cli
-TIMER 2
TIMER I
-1RO
CAl-
REG
CA2 ACTIVE EDGE READ OR WRITE REG i IORAI
CAt ACTIVE LOGE READ OR WRITE
REG 1 CORAl
COMPLETE S SHIFTS READ OR WRITE
SHIFT REG
C82 ACTIVE EDGE READ OR WRITE ORB
CB1 ACTIVE EDGE READ OR WRITE ORB
TIME.OUT OF T?
READ T2 LOW OR
WRITE T2 HIGH
TIME.OUT OF TI
READ Ti LOW OR
WRITE Ti HIGH
ANY ENABLEO INTERRUPT
CLEAR ALL INTERRUPTS
IF THE CA2/C82 CONTROL IN THE PCR IS SELECTED AS
INDEPENDENT INTERRUPT INPUT. THEN READING OR WRITING THE OUTPUT REGISTER ORAIORB WILL NOT CLEAR THE FLAG BIT INSTEAD. THE BIT MUST BU CLEARED BY WRITING INTO THE 1FR. AS DESCRIBED FRL VIOUS&Y.
Figure 25. Interrupt Flag Register (1FR)
REG 14 - INTERRUPT ENABLE REGISTER
171615141312 IiIc;I
CA2
Cal
SHIFT REG
C82
0-INTERRUPT DISABLED
Cli
t INTERRUPT ENABLED
TIMER 2
TIMER i
SET/CLEAR
NOTES:
i IF BIT 7 IS A 0. 'THEN EACH 1 IN B1TSO- 6 DISABLES THE CORREONOING INTERRUPT.
2 IF BIT 7 ISA ...... THEN EACH 1 IN BITS 0-6 ENABLES THE
COPREO4MDING INTERRUPT.
3. IF A READ OF THIS REGISTER IS DONE, BIT 7 WILL BE '0" AND ALL OTHER BITS WILL REFLECT THEIR ENABLE/DISABLE STATE.
REG 9-TIMER 2 HIGH-ORDER COUNTER
/c 9/Er
5I2
1024 204* 4055
SIM 153M
ml?
couNt
VALUE
WRITE - Slits LOADED iNTO Y? HIGH.OROER COUNTER ALSO. LOW-ORDER LATCHES TRANSFERRED TO LOW-ORDER COUNTER IN AOOIYIOF& YZ INTERRUPT FLAG IS RESET.
READ - SlITS FROM T? HIGH-ORDER COUNTER TRANSFERRED TO MFU.
PIN CONFIGURATION
V5$ a
40 CAl
FAO I 2 Pat a 3
.3' R CA?
35 RIO
FAa I 4 'AS a S
.37 u R$I
21 Ria
'M u s
.
u Ria
FAS e 7
PA' I $
.34 u
33 00
- PA? u S
32 Di
. PIO u 10 SYU$22 Si 02
il . PII u
30 03
Pl? . 12
25 Da
Pia u 13 Psa e 14
2$ a 0$ 27 u Os
pIO a IS 1$ a IS P', a 17
2$ R 07
2 25 u
24 u cii
Cul e 5
cia I 11
I 20
23 u
22 u
21 u Iã
3.20
Apple Computer Inc · 1982
Page 0072 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple ,/// Computer Information
Apple ///
Service Reference Manual
Section I of Il . Theory of Operation Chapter4 . TheACIA
Written by Apple Computer 1982
Apple Computer Inc · 1982
Page 0073 of 0730
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ep - u
THE 6551 ASYNCHRONOUS COMMUNICATIONS INTERFACE ADAPTER
I/I As you know, the Apple /1/ can be used to communicate to all devices that use
the RS-232-C standard communications format. This means the Apple
can
i/I communicate with letter-quality printers, modems, high speed data collection
devices, and other computers. The Apple
has a built in Asynchronous
Communications Interface Adapter (AdA). It is located at addresses COPO
through COP'3. This device is solely for use as a serial port input/output
controller. This RS-232-'C protocol, specified by the Electrical Industries
Association (EIA), is provided at port C connector through two buffer devices
as shown below.
BUFFER
PORT C
The 6551 contains seven registers and five control circuits dealing with the control, timing, and interrupt logic of transmitting amd receiving data through the serial EtA port. A block diagram of the 6551 ACTA is shown in Figure 1.
Before using the 6551, the system (or programmer) must initialize it for the I/O mode. Once initialized it will be set to transmit and/or receive data within the parameters set in the control bytes.
The Apple /1/ I/O addresses for data and control are presented in the following
discussions. The function of the data byte (depending on location) will also be shown. The characters in parentheses next to each register represent the function of the associated pin of the ACTA (i.e. R'Read,W-Write).
RECEIVE DATA REGISTER (RxD)
The Receive Data Register is accessed with I/O location COFO (r). The contents of the Receive Data Register will be the data bits of the completely received serial input character. This register is used as temporary data storage for the 6551 receive circuit. The first data bit received will be the LSB of the data byte (Bit O).
COFO (R) RECEIVE DATA REGISTER
4.].
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Apple Computer Inc · 1982
.3iCAJRIW
da' cs,
;
4OaS. ,4f RS
SELECT ANO
CONTROL LOGIC
Dß,L
DATA BUI
SUFFERS
V
ecco (&)
TRANIT
DATA REGISTER
STATUS REGISTER
CONTROL REGISTER
RECEIVE DATA
REGISTER
COMMAND REGISTER
IRANSHIT CONTROL
TRANSUIT SHIFT
REGISTER
INTERRUPT LOGIC
SAUD RATE GENERATOR
RECEIVE
hIlFT
REGISTER
RECEIVE CONTROL
T.D
RxC
XTAU
XTALS A//c
hiD
FIG1
THE ACIA BLOCK DIAGRAM
t
I
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
ep - ,
TRANSMIT DATA REGISTER (TxD) To load a byte to be transmitted out the serial RIA port, I/O location COFO (w) must be accessed. The LSB will be the first data bit transmitted.
COFO (w) TRANSMIT DATA REGISTER (w)
STATUS REGISTER
The 6551 continually monitors the condition of the registers and the quality of the incoming data. When I/O location COF1 (R) is accessed the contents of the Status Register is placed on the data bus. The meanings of the eight bits of the status byte are detailed following the illustration.
COF1 (R) STATUS REGISTER
IRQ--Bit 7 indicates that the 6551 generated an IRQ to the system f or one of the folllowing conditions:
1. Change of status of the DCD line. 2.. Change of status of the DSR line.
The Transmit Register has emptied. The Receive Register has filled with a new incoming character.
(Note: the third and fourth conditions are program controlled as to whether or not they inititate an IRQ).
DSR---Bit 6 indicated the status of the DSR line from the interface. 0-DSR is low and ready. 1-DSR is high and not ready.
DCD---Bit 5 shows the condition of the Data Carrier Detect line from the interface. 0-DCD is low and the carrier is detected. 1DCD is high and not ready.
TDRO--Blt 4 informs the host that the Transmit Data Register has transferred its contents to the outputs shift register and now ready to accept another character (byte). 0-not empty, 1-empty.
RDR.F1-Bit 3 indicates that the Received Data Register has been filled with a character from the line. 0-not full1, 1-full.
OVERR-Bit 2 shows that there has been an overrun error, that is, a new character has been transferred to the Received Data Register before the previous received character was taken
by the program and the RDR.F1 flag reset. This error will
not generate an IRQ but should be checked by the program so that tht lost data can be recovered. 0-no overrun, 1overrun has occurred.
4.3
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FRMERR-Bit i informs the program that the incuLng data did not conform co the parameters set in the Control Register. That mans usually that when the 6551 checked for the position and number of stop bits if found a descrepency. This error most often happens when the remote device is transmitting at a different baud rate. O-no framing error, 1-f raming error detected. This error does not generate an IRQ.
PARERR--Bit O indicates that there has been a parity error in the incoming data. This error does not cause an IRQ to be generated. O-no parity error,1-parity error detected.
PROGRAMMED RESET
By accessing COFI (w) the Status Register will be reset to all 0's. The data byte on the bus at that cycle does not have to be any particular structure.
COF1 (w) PROGRAMIIED RESET (w)
COMMAND REGISTER
To access the Command Register to initialize or modify the Command byte a COF2 (w) must be executed with the data byte configured for the desired effect. To inspect the contents (or current command structure) a COF2 (R) will cause the 6551 to place the contents of the Command Register on the data bus. The meaning of each bit is explained below.
COF2 (r/w) COMMAND REGISTER (r/w)
Parity ck ctrlsBits 7 through 5 command the 6551 in regard to parity checking. Bit 5 is parity enable. Bit 7 determines whether the parity bit position will have odd/even or fixed one/zero function. Bit 6, depending on the condition of Bit 7 selects either odd or even parity, or fixed mark (one) or fixed zero (space). Table - below clearly shows the conditions of these bits.
ECHOBit 4 determines whether the 6551 will echo (transmit a duplicate image of what is received) the received data to the remote device. O-no echo, 1-echo data.
TRANS CTRLSBits 3 and 2 control the 6551 in three (3) functions. They are Transmit Interrupt, the state of the RTS Line, and the Transmit BRK (break, a continuous space on the line for approximately 200 milliseconds). Table -- shows which state controls which function.
INT--Bjt t command the 6551 to either enable or disable interrupt on Received Data Register full (bit 3 of the status byte). O-IRQ on RDRF1, 1-no interrupt.
4.4
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I
IDTR--Bit O enable the 6551 to transmit and receive or not. It also
changes the state of the DTR output to match the condition of the 6551. 0-disable xmit/rcv (DTR high), 1-enable Xznit/Rcv (DTR low).
CONTROL REGISTER
The final 1/O loc*tion on the 6551 is the Control Register. By writing to CPF3 (w) with a properly structured date byte four functions are controlled. They are Number of Stop bits appended to outgoing data byte (and checked for on the incoming date byte), the source of the receiver clock, and the baud rate selection. By reading location COF3 (x) the current control configuration can be seen on the data bus.
COF3 (R/w) CONTROL REGISTER (P.1W)
STOPBBit 7 controls the number of stop bits that will be added to the transmitted data word. 0-istop bit, and depending on the word length selection 1-2 stop bits or 1 bit if word length is 8 and parity is selected, or 1/2 bits if word length is 5 and no parity is selected.
WORD LEN--Bits 6 and 5 determine the number of data bits that will be transmitted or received in the data word. The values (6,5) are as follows: 0,1-7 bits; 1,0-6 bits; 1,1-5 bits.
'XCLK--Bit 4 indicates the source of the receiver clock. 0-external clock source, 1-baud rate generator (internal). When the internal selection is made the ExC pin becomes an output.
BAUD RATE--Bits 3 through O select the baud rate at which the 6551 will operate. Table -- details the various selections available based on a standard 1.8432 MHZ clock input. It should be noted that 0,0,0,0 selects the external clock as the baud rate source but the clock rate is actually dividied by 16 so the external clock should be 16x the desired baud rate.
4.5
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pcompm
i
SIMPLE SERIAL PORT
1/I Incorporated into the A
port. Its main purpose
is
logic design is a provision for to support a Silentype printer.
a simple However,
serial it is
I/I Anjjoooyytssttaiiccdikkess.d.filcoFatotTrehrdeemaopulaosltreytraipshnpiatlnseicncetdahetieditoofnospsrht,aiaroeno"sngeoaftmjheohesya"svstiapinmlcgeakytceihorsne.nmeSTocihrtleeoernjttowhyyiapstnethieoconrknoeuawgooshfuelcsdoitnnhdbceee
more for applications like cursor control.
the used
The serial port is actually derived from a feature of the VIA. Two of the aasTp(pehUoptse1re7itnt7mV)dopIc.ilAoceenenitsaasTr)beho.lrpeleiryaoltlgciIhronnenpaetsomtprrmhoo(teerlPdt3(s.t1siyh,enseettPTeedBhCrmi2ehnr)seaceeleclrcstsytaeiwancoiittntnboiceohoodneftceshotodenenaafrrrtimVeagisIunoAfaref'onetsuddiwntaadtcarnoledifonbuccrenkoecnaaatttdniorosootthnalhhi.nelefdretdsfaprrdseeodwcgmriietsstschthsheeeaeerbst,lbeomiauhnlrsedatnt.tchcbeehe
The signal ENSIO when high enables data from the VIA to the port, when low it aueoillplsenfiosgannolebte.olhewteewn)osha,cibtdlcllhaoheoetcswakcr,ateefnhnmrheaooibbtmgeleAheXtusdCheseOenetvadhispbecioltegreo.nptsaonlroctTttlohiotetfcotokyhretestfhmuVhreIopeoAtpmp.elporytrodhtcete,TevhhsieVetscIhoecsAirlisgotmoncocafakayltnsthpEooeubNmteSetpEhsuoLetsrr.aeteVtdqdIu(ueAsiait.fsreberiaammtneiEsdsnNnetSeooElsnLnem.lcuttythtwheuheioaefrldn"lisPayrhwDceiiLkacgt2nghtcorihweo"-end
4.6
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
s 'c
=r
eL:O *Ö'3L
k F OLZ.-
T. t 4TP%A I_o.
rw
O OFTh
. VÇ
« 'fvTh
Ñ
StcSbv
U) J\LCC!Çr L
\Ç
-
Vv\\
4.7
Apple Computer Inc · 1982
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onut m
PINOUT OF TRE RS-232-C SERIAL INTERFACE (PORT C)
PIN
NANE
i
SGND
2
3
RCD
4
RIS
5
CTS
6
DSR
7
GND
8
DCD
9-19
20
DTR
DESCRIPTION
Shield GrouND.
Transmitted Data; serial data output from the Apple.
ReCieved Data; serial input to the Apple.
Request To Send output; this indicates that the Apple is ready to transmit data. This line is active whenever the Serial Card emulation is used.
Clear To Send input; this acknowledges that the Apple may begin transmission. This Une is ignored by the Serial Card emulation.
Data Set Ready input; this acknowledges that the remote device is operational. The Serial Card emulation checks this line and will not send characters if this line is held inactive. This can be used to prevent the Apple from overflowing a printer input buffer.
Signal GrouND.
Data Carrier Detect; this acknowledges that the remote device is ready to transmit data. The Serial Card emulation checks this line and will not send characters if this line is held inactive, This line can be used to prevent the Apple from overflowing a printer input buffer.
No connect.
Data Terminal Ready output; this indicates that the Apple is on and operational. This line will be active anytime the Serial Card emulation is used.
4.8 4,
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:
ACtA
The Apple /1/ has a built-in 6551 ACtA (Asynchronous
Communication Interface Adapter). It is located at addresses SCOPO thru $COF3 (decimal -16144 to -16141). Th. ACtA has five registers: transmit data1 receive data, status, command, and control.
The transmit register ($COFO) is used to send data out the Apple
/1/ to an external device, such as a modem or a printer. A byte is
transmitted by setting the control and command registers appropriately and then polling the status register. When bit 4 of this register La one the ACIA is ready to shift the next byte out. Often bits 5 and 6 are tested for zero to assure the Data Carrier Detect and Data Set Ready ara valid as some printers use these lines as handshake signals.
Care imist be taken when writing to the transmit data register as it is at the same address as the receive data register. The 6502 will do false reads when certain address modes are used, thus discarding whatever was in the receive data register.
The receive data register ($COFO) contains the last byte received from an external source, such as a modem. Bit 3 of the status register is one whenever this register is full.
The status register ($C0P1) indicates the states of Data Set Ready, Data Carrier Detect, whether the transmit and receive registers are full, and whether a framing, overrun or parity error has occured on input.
The command register ($COF2) sets the parity, echo mode, transmit and receive enables, and BRIC transmission.
The control register ($C0P3) sets the number of stop bits, data word length, receiver clock source, and baud rate.
PRYSICAL PINOUT OF TRE RS-23 2-C SERIAL INTERFACE
13
12
11
10
9
8
7
6
5
4
3
2
1
25 24 23 22 21 20 19 18 17 16 15 14
4.9
I
Apple Computer Inc · 1982
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RS232 CONNECTOR USAGE (PORT C)
Thi Apple /1/ 1g classified as Data Terminal Equipment (DTE)
under the EtA RS-232-C interface specification. It can be directly connected to a piece of Data Communications Equipment (DcE), such as a modeis. To connect the Apple to another piece of Data Terminal Equipment (such as a printer)1 you must use a modem eliminator.
All output levels are minimum +6 volts when logic O and maximum -6 volts when logic 1, measured into a 3T.L ohm load.
All.iuputs bave a turn-on positive going thresholl of +1.25 volts and a turn-off negative going theshold of +.8 volts, typical. All inputs sink a IO mA current, maximum.
4.10
Apple Computer Inc · 1982
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CONTROL" ISTER
The Control
ter i use to s4lect the desired mod.
for the SY6Ò Thci word length, number of stop bits
and clock controls are all determined by the Control
Register, whish is depicted in Figure 8.
CONTROl. REGISTER
1718151413 [21 ii BI
STOP SITZ
O-1 SNp Sit I 2 Suop liii
t Slap Sit if Wwd Lu. 1$.tsan4Po,Ny
1% Sp SEw if Wurd I.i.iØ,
-S Riti w Ns Pwii.
WORD LENGTh
BIT DATA WORD
LENGTH
00 S
li0Ioi
T S
R
RECEIVER CLOCK SOURCE
o - Ezt.r,Ew Rsc.i.ur Oo t - Riud Rats Gat.at
I i...._L
III I
o o oo
oBOO lOO
ooii
o too
o 10 1
0 1 10
oi it i ooo
1 0 0 '1
I O t0
ioti
i i OO
i I OI
1
1
tO
1
1
1
1
SAUD RATE GENERATOR is EXTERNAL CLOCK 50 BAUD 75
icen
i3i.sa
ISO
uco 1200 1500 2400 3400 4100 7100 9000 19200
This 110*1 f S-bit
71543210 IS Ewts biti plus p0*y).
HAROWARE RESET PROGRAM RESET
010101010 o o
Figure 6. Control Register Format
COMMAND REGISTER
The Command Register is used to control Specific Transmit/Receive functions and is shown in Figure 7.
COMMAND REGISTER I IS 5 4 3 2
PARITY CHECK CSMTROLS
785 SIT
-- O
OPERATION
PurityOiIsdNoParitySis
No Parity Bit Rus.it
O O 1 CHdPwityR.cuivuraidTmnwiiitt
i o
i Lom Pity Ruusiow aa
Tr.uu,iiter
t O t NsrI Purity Sit T,attsnittsd,
P*EIy O, DEwbI
i1
1
Purity Bit Trwrnfl
Purity Oit Oia.ø4
NORMAIJECHO NODE FOR RECEIVER
O No,ii,l
1-Eo
DATA TERMINAL READY
Di. RacS,srITrow,oitw
(OIR hiWI)
i - EaaUI. Rts.,r/Trusw,iittsq (DIR IowI
RECEIVER INTERRUPT ENABLE
0 (RO Inturnapt En11Iud from BEI O of StaSis R.qistw
i - ¡ kutanupt OisI.d
BIT
32
oo
OI tO tI
TRANSMIT INTERRUPT
DiiabI En.bi DsubI.d Diiabl
TRANSMITTER CONTROLS
Th LEVEL
Hifi
Low Low Low
OTHER
---
Tr*wnt BRK
7 S S 4 32 10
HARDWARE RESET o o o o
o
o
I PROGRAM RESET
o oo
o
Figure 7. Command Ragister Format
4.11
Apple Computer Inc · 1982
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STATUS REGISTER ¿26/cf
The Status Register is used to indicate to the processor the status of various SY6551 functions and is outlined in Figure 8.
STATUS REGISTER
Ie 5 4J3J2
IDI
1__ Parity
O No Parity Erro, 1 Parity Erro, D.tsct,d
Frimutg Erro,
O - No Framing Errar - Framing Error Datortud
O No Ovamun 1 Owo,run H Occurrad
R.c,.vo, Ost. R.gutto, Full O Not Full
- Full
Trinimitter Data R.gust Empty Io- Not Empty
1 Empty
Osta Co,rio, D.tart CbI
O 5Iow(Ostac()
OCO hiwi INot D.torwd(
Dula Sit MIadY ()
O ! low (Ready( - OSA hiØt (Not Raady(
Intsrrupt (lAG) O - No Intarrupt Plo intarnipt act,I for th.. conditi0nL I Intarrupt Hat Occwtsd
7es 43210
iI:I:J1J:Ej HARDWARE RESET
PROGRAM RESET
Figure 8. Status Register Format
PIN CONFIGURATION
ONO ca0 2
3 RES 4 RaC 5 XTAL1 e XTAL2 7
e CTS s
1*0 10 DIR 11
RaD 12
R; '3
4
25 Am
27 2e lAO 25 0ß7 24 OB, 23
22 Del 21 083 20 093 19 Del le 093
17 DSR
le Dc0
15 Vec
PIIDN NNOT. 1. -
4.12
Apple Computer Inc · 1982
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Service Reference Manual
Section I of Il . Theory of Operation Chapter . System Clocks & Timing
Written by Apple Computer. 1982
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e',p - u'
SYSTEM CLOCKS & TIMING
MAIN CLOCK (C14M)
The Apple /1/ has as its master clock a 14 megahertz crystal controlled
oscillator, The active components of the clock circuitry are QiO, Qil, and Yl. The exact frequency of the oscillator is 14.318 MHz. The slight increase over 14 MHz is compensated for in other logic. Device 813 provides buffering and power amplification to drive all the other loads on the C14M and C14M* lines.
FREQtENCY DIVIDER
The next circuit in the system clock section is the frequency divider formed by device Bl2 and 813. This develops both the C7M* and the C3.5M*.
The C7M signal is developed by clocking the Q* output into the data input of a Dtype latch. This results in a dividebytwo function of the clock frequency.
The C3.5M clock is developed in the same manner. However, the data input to the latch is an ExclusiveOr function of dM and C3.5M at B13. This accomplishes two functions:
o it divides the C14M clock by 4, and
o it gives a definite phase relationship of C7M to C3.5M clocks.
Looking at the timing diagram below we see that the D2 input of 812 is high if either the C7M or the C3.5 clock is high but not when both are high. This function is effectively at 3.5 MHz which toggles on the positive edge of the 7MHz clock. The true C3.5M signal toggles on the negative edge of the C7M clock.
C7fl
C3$
¿'z
/4/S
_j
"Q TIMING
i/I The Q clocks are a series of 2 MHz clocks which are out of phase with one another
by one clock time (refer to the Apple
Timing diagrams). The rest of the
system timing depends on the states of the "Q" outputs. They provide the basis
5.1 4,
Apple Computer Inc · 1982
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2 j21 I
,4EQc/ÇAJ,. V 2v ViS(.
TJLéD
MA
S!D
A'
s MC _T biSK
OIØ s,
SgcTWA)
X
I, 3
cm
clM __! 9,3
s
A
3at-
CI'i
C7M
C 3.M C LÇM
72g-3
VA', r (MV
TFSr
5.2
/
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
L
VA't' l.'**' NEV'
Apple Computer Inc · 1982
:
I
-
+
I1 W.WL'
IHii
A
'1
HlID ANGLI PNOJICIION DO PIfl ICALI DIAWING
+
/
j- - i'iJa.? v.av,
TO&1NANCIS
QIV PAlI IIUMIEI
DSIY
DAlI
DSC%IPIION
I t - DECIMAU
lxliit* - AMOLli INI I
t - VIA 11011%
CNI(IIIt
AVPIDID IT IILI*UDIT
t II *L*II11%
MATIIIAL
DM1 DATI
TITLF
DM1
DIAWING MONIlI
NtAT AUV flNI%tI
SHIFT
2
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
APPLE III TIMING
1PAS
PHASEN PiiØ
}SPAL.L
IuJ (wif
Apple Computer Inc · 1982
Page 0090 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
for processor and RAM address timing.
The Q clocks are initialized with each Load Parallel'o Serial pulse (LDPS), which changes the mode of the LS195 (Dio) from a shift' register to a parallel loaded register when low. At each load, all of the bits are set high. When LDPS5 returns high the next clock will shift the zero of Q35 across the register. This means that QO will stay high for one clock cycle. Ql will stay high for 2 clocks, etc. When the Q3* goes high at the forth clock edge after LDPS the J1( input will now see a "i". Subsequent clocks will start shifting that one across the register. When Ql. goes high again, LDPS* will be enabled low and another
load will be accomplished at the next clock edge. The waveforms ars assyminetrical.
Each of QOQ2 are up for three clocks and down for four. Q3 is up for four and down for three.
This type of cycling will continue for 128 cycles. Then the Horizontal Phase Disable (HPE*) "freeze" will occur.
HPE* FREEZE
The HPE* signal will cause the Q states to extend their next cycle by two clock times. The purpose of the shift is to shift the phase of the color reference signals to the data in the video generator. A detailed discussion of this phenomenon is described in the video generator section. How this shift occurs is discussed below.
Looking at the gate array of C9 and Bit we see that since HPE* is normally high, the output of C9 is normally low. This dcgates the And mut shared with QO, and allows LDPS to function as usual. But when HPE* goes low, which will always coincide with C14M going low, the And gate shared with QO will become enabled
and cause the extension of the LDPS* for two extra clock cycles. This state will exist until C3.5M returns high and relieves LDPS*. The next clock will change
the state of QO and that will not be able to "disrupt" the clocks until the next HPE pulse.
AX, PRE1M, & C1M
The AX, RAM address (the signal used to select which addressing source [row or column] is presented to the RAMs: see RAM Address Logic) is another 2 Mhz signal which lags Ql by one half clock cycles. It is developed at Ail pin 9.
PRE1M can toggle at each positive edge of AX, if the data input to the latch is at the opposite state. Looking at Dil (C1M*) ve will be abLe to see just that.
If PRE1M has just toggled low, one half clock cycle later dM5 will toggle high
which forma the data input to the PRE1M FlipFlop. But remember, the clock to the flipflop is AX, a 2 MHz signal. Dli pin 5 acts much like B12 pin 2 in that the data is always opposite to the "Q" output of the latch at the time of the clock edge, therefore we have a "clock divided by 2 function, of a 1 MHZ output.
RAS (Row Address Strobe)
5.5
J
Apple Computer Inc · 1982
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Apple Computer Inc · 1982
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I'
The RAS 51gHl , QO dalayed by one clock and inverted. This 5 acccornplished
at DIO pin. 15 & 14. (Note: the inversion is done by calling t' Q output the active low signal RAS*, clever huh?) RAS is used in the RAM ad"ess logic to develop the "row select" signals for the BANs.
VIDEO HORIZONTAL & VERTICAL STATE )L1TERS
This circuit i. nade up of four 4bit binary counters (710, F11, Cli, G12), which develop the essential signal, for partitioning the screen and addressing the RAM for ail th. video data.
Basically, there are two sections of the circuit:
i - horizontal postion counter
2 vertical position counter
These two counters form the X and Y coordinates of each addressable byte on the screen. Each byte contains 7 bits or dots in 40 character modes.
Fron the various discussions about the Apple i/i, we have learned that in the 40 character mode there are 280 dots across the horizontal line that can be
defined, and 192 of these horizontal line (280 X 192). In the Apple /1/ modes
there are 560 dots in the horizontal line, however, there are still only 192 horizontal lines (560 X 192).
The Video Counter works identically in either of these modes. It provides the resolution of 40 by 192 matrix. Each one of the 40 horizontal positions defines either 7 or 14 dots (40 or 80 character modes, respective].y)a These dots are actually bits of data bytes in memory that are parallel loadedd into a shift register and shifted out serially to the video monitor. In the 60 character modes the system loads the shift register at a 1 MHz rate and shifts at a 7 MHz rate. In the 80 character modes it loads at a 2 MHz rate and shifts at a 14 Mhz rate. It is interesting to note that in either mode the state counter increments at a 1 Mhz rate.
The system provides two complete accesses for the video output per increment of the state counter, but in the 40 character modes one of these are masked out.
HORIZONTAL SECTION
The Horizontal section of the state counter uses 7 of the counter stages and develops the HO through 05 and the HPE* signals. The remaining 9 stages of the counter develop the Vertical states VA, VB, VC, and VO through V5.
The Horizontal section provides the capability of a 128 state counter, however, it only provides 65 states. This is due to the action of the most significant stage, HPE*. The counter actually Counts from 64 to 128 then resets to count 64. Simply, HPE* starts high and when the counter increments HPE* low after 64 counts i is then reset to state 64 after the next clock input, this yields
5.7
/
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Apple Computer Inc · 1982
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p Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
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Apple Computer Inc · 1982
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65 states all together.
Looking at Fil we see that the tIPE5 output is connected to the "load" input of F10 and Fil. At the next clock input these two devices will be loaded with the state determined by what is on the data inputs. All inputs except pin 5 of Fil are tied low (disregard the input to pin 6 of Fil at this time). This binary state equals 64. So rather than starting back at "zero" the counter jumps to 64.
For real time considerations of the monitor, it takes 25 states or 25 microseconds for the sweep to return from the right hand side to the left side. So the system ignores the first 25 states and blanks the video output and the returning trace is not shown. The boolean expression for the horizontal blanking would be
e xpre es ed:
(R45 and R5*) or (H4 and H35)
This logical function is done within the G9 Control ROM. Refer to page 10 of 10 of the schematic diagram.
In suary, the horizontal counter provides the address necessary for the display. It divides the horizontal line into forty (40) sections, and yields the timing for horizontal blanking. The tIPE5 signal is used to momentarily "freeze" some of the system timing.
VERTICAL SECTION
The Vertical State Counter provides the Yaxis of the display matrix. The nine stages, if left alone to count, would provide 51.2 states. As in the horizontal counter, it is preset to count higher than zero eadch time it reaches the "termina], count". Also, some of the states are used to blank the video while the trace returns from the bottom of the screen to the top (VBL).
The vertical counter effectively counts the number of HPE55 that have occurred, or simply, the number of horizontal lines that have been generated in this scan.
At this time the counter is reset to count 250. Look at the timing diagram of the vertical counter. One can see that all vertical signals would normally go low, but instead the counter is loaded with the data inputs. VA will not be affected by the teminal count/load and will continue as discussed before. VB will be loaded to the present state of "comp" (or VA) which is high. VC and V5 will be loaded to a low and the rest of the bit states vil be loaded to "1... This will decode to decimal 250.
Six counts later VA through V4 will toggle low and V5 will toggle high. This is the point where the logic assumes to be at scan line "zero". It will now take 256 counts to reach the terminal count sequence and start again. Using some math we see that the counter defines 262 states (256+6 . 262).
Vertical blanking takes 70 of the 262 states developed by the counter. The boolean expressalon for the vertical blanking signal would be:
(V3 and V4)
5.10
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This si&nal is developed at F8 pin 6 and is used in the system to indicate that a complete scan of the current display page has occurred. It is also an input to the Control Rois, G9, and therefore is a modifier to its outputs. We vere looking for the isajic number of 192. Well, if youve been keeping track, its simply the difference of 272-70.
5.11
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Page 0098 of 0730
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
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Apple /// Computer Information
Apple ///
Service Reference Manual
Section I of II Theory of Operation Chapter 6 Video Display Logic
Written by Apple Computer 1982.
Apple Computer Inc · 1982
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CXi
DISPLAY MODES
O 40 CHARACTER APPL Ii : 40x24 CHARACTER B/W TEXT (2K BYTES AM)
o 40 CHARACTER APPLE /1/: 40x24 CHARACTER COLOR
TEXT - 16 BACKGROUNDJ 16 IExT COLORS
o 8i) CHARACTER BLACK & WHITE APPLE I/I: 80x24 CHARACTER B/W TEXT
o BLACK & WHITE HIRES: 280x192 B/W HIRES (8K RAH)
o ¡'lEDIUM RESOLUTION 16 COLOR GRAPHICS APPLE /1/: 280x192 16 COLOR HIREs IITH 40x192 BACKGROUND! I-OR:GROUND RESLUTION
o SUPER HIRES AP?LE 11/: 56Bx192 B/W HIRES o APPLE//I fIRES: 140x192 16-COLOR HIRES o RAM CHARACTER GENERATOR {128 CHARACTER)
Apple Computer Inc · 1982
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I/I APPLE
VIDEO
INTROD T.ET ION
I/I The Apple
has 11 defined video modes of operation. There are 5 Apple J[
f/f modes and 6 new Apple
modes. There are now 3 text modes and 8 graphics
modes. Though the Apple 11/ can emulate all of the Apple J[ video modes,
there are many differences in
Apple /1/, including:
the video
hardware between the
Apple
](
and
o 80 column text with full upper and louer case character capability
o New color text mode
o Super high resolution black and white graphics
o 2 new color hires modes
AND
o A modifiable character Bet
I/I. The modifiable character set is a major new feature of the Apple
You can
now change the character set by changing the pattEtrn in the character
generator. This is possible because of a ram, instead of a fixed rom
configuration.
There are also improved video outputs. An NTSC (National Television Standards Committee) composite Black and White and color composite, plus the primary video signals, are available at the back panel for mixing into the input of a high quality RBG monitor.
I/I, The Apple ]( emulation mode has the very same video modes as the Apple ][.
The Apple
while in its native mode, can have the following modes.
40 Character Apple J[ This mode is equivalent to the Apple J[ text mode. The only difference is it
has upper and lover characters.
o The screen is divided into 40 horizontal columns and 24 vertical lines.
o The characters are usually white dots on a black background.
o This mode has inverse video and flashing characteristics.
o This mode has no color.
V
6.2
1
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o This mcde has to screen pages mapped into memory:
- Page 1 is located at 0400-07FF
- Page 2 is located at 0800-OBFF.
I/I 40 Character Apple
This second 40 character text mode is the most interesting and, in a way, the most powerful. This is the only color text mode. It has the same screen
resolution as the Apple ](, and the same video attributes. BTJI it also has
the ability to select both the color of the foreground (dots) and the color of the background. Sixteen (16) colors are available as in the Apple ]( Lores Graphics.
o The color resolution can be selected for each character and can change for each character.
o It is interesting to note that by down loading a character set, a new low resolution graphies mode can be manufactured from a text node.
The page mode is different for this mode since both pages are used at once. Why? Because the first page contains the character data and the second page contains the color information. The page 2 mode reverses the mapping, that is, the characters in page 2 are stored where the color was stored in page i, and vice versa.
In the color byte, bits 4-7 set the foreground color and bits 0-3 set the background color. The mapping between color and character is 1:1. That is, a character located in 0409, for example, has its foreground color determined by the byte in location 0809.
In the page 1 mode the mapping is as follows:
0400-07FF contain the characters
0800-OBFF contain the color information.
In the page 2 mode:
0800-OBFF contain the characters.
0400-07FF contains the color.
I/I 80 Character Black & White Apple
This new text mode is the same as the 40 column mode with the obvious exception that it has 80 columns instead of 40. This 80 column display has
full upper and lover case, and inverse video.
Unlike the 40 character mode, it does not have 2 distinct pages. It uses both
6.3 /
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çpmp
pages to hold the characters. The memory happing for Page 1 utilizes:
0400-07FF for the primary fetch
0800-OBFF for the secondary.
In this mode, location 0400 contains the first character and 0800 contains the second. The third and the fourth characters come from locations 0401 and 0801
respectively.
In the Page 2 mode the primary fetch is from 0800-OBFF and the secondary from
0400-07FF. Therefore, the first and third characters come from 0800 and 0801 and the second and fourth come from 0400 and 0401.
Black & White Hires This is a new graphics mode that has a 280 by 192 resolution in Black and White only. It has two distinct pages:
Page 1 is located at 2000-3FFF
Page 2 is located at 4000-5FFF.
Medium Resolution 16 Color &aphics Apple /1/
I/I. This is a new graphics mode for the Apple
It has the same dot resolution
as the Apple J[ Hires (280 by 192), but it has an expanded color capability of 16 background colore. The B/W Output will yield 16 levels of grey scale.
The screen is divided into a 40 vide by 192 high matrix. That is, the color
selection for foreground and 16 background can change for each 7 dot [0000000]
pixel segment. You can think of each segment as a one-bit-high slice across a character space, as illustrated below.
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6.4
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- r
The memory mapping is as follows: Page 1: 2000-3FF? each byte represent. 7 pixels in the segment
4000-5FF? each byte represents the foreground and background colors for the corresponding 2000-3FF? byte.
Page 2; 2000-3FF? each byte represents the color. 4000-5FF? each byte represent. 7 pixels.
I/I Super Hires Apple
I/I This i. the Apple
Rires equivalent of 80 character mode. It is a Black
and White mode which has the dot resolution of 560 Horizontal by 192 vertical
spaces.
There are two distinct screen page., each with a primary and secondary page. Because it is like the 80 character modes, this mode draws it. information from alternating ram. Each memory byte contributes 7 pixels. In Page 1 mode, the primary contains the odd dot groups and the secondary contains the even dot groups. The primary (first 7 pixels) is located at 2000-3FFF, and the secondary (second 7 pixels) is found at 4000-5FFF. In Page 2 the primary is at 6000-7FFF, and the secondary i 8000-9FYF.
In each byte the Most Significant Bit (MSB) is ignored and the data is displayed with the Least Significant Bit (LSB) first from left to right.
I/I Apple
Hires
This i. the third new graphics mode. It has 140 by 192 pixel resolution, and i of 16 color selection per pixel. In this mode the pixel is formed by a group of four dota of the same color.
There are two distinct screen pagea in this mode but the mapping of the
individual pages is, at first encounter, a bit difficult to master.
od
luck!
o The display dot represents a sequence of 4 data bits in the RAM display area.
o Two rama are used starting at 2000 and 4000 respectively and alternate bytes are fetched from each ram area.
6.5
I
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o In any video mode only 7 of the 8 bite of each byte are displayed.
With this information in ,aind...and remembering that each pixel in this mode is made from 4 bits...you can see that you need 4 bytes of information to get 7 pixels. The way in which these bytes map into picture elements is shown below.
2000- 3FFF
2001
4000-SFFF
A
2000
11
I
ASH
Pl
tI I
I
P2
4 BYTES
4000
2001
i I II I I
fi i I
iI
t
P3
P4
I
P5
4001
I I 1.1 1
P6
P7
6.6
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4000-5FFF each byte represents 7 pixels.
Super Hires Apple /1/
f/I This is the Apple
Hires equivalent of 80 character mode. It is a Black and
White mode which has the dot resolution of 560 Horizontal by 192 vertical
spaces.
There are two distinct screen pages, each with a primary and secondary page.
Because it is like the 80 character modes, this mode draws its information from alternating raw. Each memory byte contributes 7 pixels. In Page 1 mode, the primary contains the odd dot groups and the secondary contains the even dot groups. The primary (first 7 pixels) is located at 2000-3FFF, and the secondary (second 7 pixels) is found at 4000-5FF?. In Page 2 the primary is at 6000-7FFF, and the secondary is 8000-9FF?.
In each byte the Most Significant Bit (MSB) is ignored and the data is displayed with the Least Significant Bit (LSB) first from left to right.
I/I Apple
Hires
This is the third new graphics mode. It has 140 by 192 pixel resolution, and i of 16 color selection per pixel. In this mode the pixel is formed by a group of four dots of the same color.
There are two distinct screen pages in this mode but the mapping of the individual pages is, at first encounter, a bit difficult to master. Good luck!
o The display dot represents a sequence of 4 data bits in the ram display area.
o Two rams are used starting at 2000 and 4000 respectively and alternate bytes are fetched from each rem area.
o In any video mode only 7 of the 8 bits of each byte are displayed.
With this information in mind...and remembering that each pixel in this mode is made from 4 bits...you can see that you need 4 bytes of information
to get 7 pixels. The way in,which these bytes map into picture elements is shown below.
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lt is apparent, from the diagram, that picture elements overlap the byte boundaries for 7 picture elements and 4 bytes. The basic pattern then
repeats.
I/I The four bytes are shifted out te a fashion similar to the other Apple
modes:
o The first byte comes from the primary and the second byte comes from the secondary.
o The first byte contains the first pixel and the second byte comes from the secondary.
o The first byte contains the first pixel and 3 bits of the second pixel.
o The second byte contains the fourth bit of the second pixel, the third pixel, and the first two bits of the fourth pixel.
o The third byte contains the last two bits of the fourth pixel, the fifth pixel, and the first bit of the sixth pixel.
o The fourth byte contains the last three bits of the sixth pixel and the entire seventh pixel.
We hope the preceding diagram will help you picture what has already been
described.
For this mode, Page 1. is mapped with the primary fetch in 2000-3FFF, and the secondary in 4000-5FFF. In Page 2 the primary is in 6000-7FFF, and the secondary is in 8000-7FFF.
6.8
I
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APPENDIX (VIDEO)
o Apple /1/ Video Logic Block Diagram
o Video Logic Diagrame for:
Rires Mode Page i, 3/W 280 X 192 Hires Mode Page 2, B/W 280 X 192 Color Hires Mode Page 1., 280 X 192 Color Hires Mode Page 2, 280 X 192 Super Hires Mode Page 1, 560 X 192 Super Hires Mode Page 2, 560 X 192 Ahires Test Page 1, 140 X 192 Ahires Test Page 2, 140 X 192 Color Bar & key Scale Test los Apple II Text Mode Page 1, B & W, 40 Column Apple II Test Mode Page 2, B & W, 40 Column Sara 40 Column Text Mode Test, 16 Colors Sara 80 Column Text Mode Test, B & W
o
Apple /1/ Video Modes Truth Tables
o
Video Prom Listing
o
Video Prom Equivalent Logic
6.9
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F R O
RAM
CIM
FIJCMÀ
R4M__-_.
APPLE III VIDEO LOGIC BLOCK DIAGRAM
ENRREG
C H8O
C7M
CLKEN 8o
LDPS
VDL
I AA
DTT EAC
OH
CM
DL. AA TT AC
M
RA
APCT
HM
I
CA
C 114 M C
VIDEO DATA
SERIALIE
> CHARACTER
GENERATOR
-
VC
VC,---
VB
VA
INVERSE LOGIC
-,-
BIT
T R AI N
MUX
c1 SEL 371+
0E 3714
J COLOR
F-f
REGISTER
DiM
C1I4M
VIDEO CONTROL ROM
GE 2-
RES
DRIRES r jAil LORES
E3714 :1-
'XT
SEL3T4
-
P02
if V D M
I A D T E A
O
VIDEO ROB 8 ROB 14
ROB 2 ROB i
114M or
BACKGROUND 3.M (AHIRES)
1ULTIPLEER
6.10
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual A//f VIDEO LOGIC DIAGRAM
ENHREG
FRRAM0MB-BUS
R0 RAM
ABUS
2000.3FFF
L S
8K
F2 8 4
fl uf
CDt B EN
il
L
s
3
7E2 8 4
A1
L S
E3
ill
Ql
C14M 76
6
RESE1' ç____
RAMS
VC>2114
VBi
VA_._ E5 & E4
10'
1'DH RES
WE2114 INVERS
LOG IC
H7
s-
All RES LO1ES 11 LS3
JI
1\r\ CM A EN
CDt
D4.13
SEL37k
OE37
COLOR LATCH
1C LS374
1i_5Th
4
3 12 -0032
IDEO CONTL
z- PAGE ROM / -+IIRES
.Q_- MIX TEXTE
OH IRE
t 11CR
0E37
C NaO AH IRE tO LR KL
5EL374
Pill i lip
PULL DOWN
L
Si
9
G3
lHIRES
C14M
it L
S .2.-RGB
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9 4--RGB1
g A
11 1S3
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1/
11 LS7I.
u ii8
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4M or 3.5M (AHIRES)
1. HIRESMODEPAGE1-B&W-280X192
2000S3FFF (3K)
6.11
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A/II VIDEO LOGIC DIAGRAM
FROM3 BUS
L s
3F2 8
4
Iii i
ÏBEN
D14
4000.5FFF
R0
RAM.
L
8K
BUS> 7E2 .
4
ENHR1
CLKEN 80
A1
L S
-> E3 8
Ql
16 A15
C14M
7
RESET -ç
7
4
i II
136 6'
LSO4
6
8
RAMS
2114
vC VB
vA_. E5 & E4
DH RES
WE2114 INVERSI
LOG IC
H7
All IRES LORE
11 LS3
ic
C1M-2-1 ULf
3
SEL374
0E374
\8
COLOR LATCH 1c L5374
F3
4
Ci 4M
17 1/
LS37
62
11
LS 374
62
342-0032
IDEO
n CONTL RAG E ROM vi IRES
MIX TEX
0H IRE
I ILOR OE3 7
cl18o
AH IRE
COLRKL
SEL374
P1111 lip
isAD
-L Si
PULL
DOWN
9
G3
1HIRES
L .2.-RGB S .L_....RGB 3 9 44-'-RGBl g
F1
14M or
3.5M (AHIRES)
2 HIRESMODEPAGE2B&W-280X192
O0OI5FFF (8K)
6.12
Apple Computer Inc · 1982
Page 0111 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
A//I VIDEO LOGIC DIAGRAM
F ROM
ii
?r_
L1z3-/\J
BUS
2000. 3FFF
L
S
8K
F2 8
4
'Iii î
CI M IB EN
4000.5FFF
L
s
8K
3
7E2 8
4
E NH RU
L
L
S
E3
4
dM2) D
Ji i
C1M ÌEN
3
SEL374
COLOR LATCH
0E374
1C LS374
F
DiM
4
4
C HB O
7W
j::
Cl1+M
7>
RESET-1.
LSOL+
6
7
vC1
VB....... VA_.
RAMS
2114
E5 & E4
1'DH RES
WE2114
NVERS LOGIC H7
C 14M
s
1
5i
J3
All IRES LORES
LSd
1-
li LS
62 q
I i,LS
l'o 11 LS 374
G2 if
342-0032
D- PAGE IRES MIX TEXT
IDEO CONTL
ROM
OH IRE
I ILOR
0E37 CH80
AH IRE
cOLRKL
SEL374 -Fur
put I tIP
PULL DOWN
-
15ADBL
L
s 1
9
G3
IiHIRES
L 2_.. RG B
S 7 RGB 3 1-0-..-RGBZ 9 3--'-RG BI g
14M or 3.511 (AHIRES)
3. 280 X 192 COLOR HIRES MODE PAGE 1 ( FGD/BKGD HIRES) 2000.5FFF (16K)
6.13
Apple Computer Inc · 1982
Page 0112 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
A/II VIDEO LOGIC DIAGRAM
E NH R E G
dUcEN 80
F ROM
j
RAM-
dM
->
8000. 9FFF
L
S
8K
F2 8
4
III
CIM
11 600I0B .7ENFF?
8K
»A BUS
8
5EL37k
Iii Ui
dM AEN
3
\8
0E374
COLOR LATCH 1C LS374
L S
E3 8 4 111
Ql
DIM
6 A15
7 4
ELI
C14M
76
RESET ç
L SO k
6
RAMS
VCLi-'
2114
VB
VA__L E5 & ELI
10(1?
DH RES
WE211k
NVERS LOGIC
H7
'4
S i 5 i
J3
11
11
All
I
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LE
S
1
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LL53
r G2
17
11 LS q
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Il> LS
l'o Il LS 374
G2
31+2-0032
IDEO
n'j CONTL PAd E ROM IRES
jo MIX TEXT
DHIRE
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0E37
CH8O AH IRE
COLRKL
SEL3714
pm, lIP
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L s
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DOWN G3
'HIRES
1J
L .2__,.. RG B
RG B
3
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9
9
14M or 3.5M (ANtRES)
LI. 280 X 192 COLOR HIRES MODE PAGE 2 (FGB/BKGD HIRES)
6000 I9FFF (16K)
6.14
Apple Computer Inc · 1982
Page 0113 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
A//I VIDEO LOGIC DIAGRAM
ENHRE
A1
2000. 3FFF
L
s
r> E3
L
S
8K
FROM ß BUS> F2 8
Q.'
4
Iii ut
C1M
1C1IM400.80E.5NFF?
RAM_..._A BUS
s
L
s
3
7E2
4
CHSO 7W
8
LSOB
2
1'-CLKEN 80
13
16 i15
7 4
F'4
C.'kM
76
RESET i
LSOk 6
RAMS 2114
E5 & ELI
101
WE21 iLe
TDH
NV E RSI
LOGIC
H7
11 LS3
G2 "k
C1M
2
SEL374
COLOR LATCH
0E374
1c LS374
DiM
1
31+2-0032
PAGE
/ -Hi RES
L- MIX
O-TEX
IDEO CONTL
ROM
OH IRE
I ILOR
7
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CH80
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COLRKL r,'
M SEL371+
Pill i lip
-j
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L
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1
9
G3
HIRES
C1LeM
11
L 2RGB
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3 -I-Q_I-RGBZ 9 35-'-RGBl 9
A
f9 1kM or 3.5M (MURES)
I 1LSZJ4
u',
lL> LS 37k G2
5 SUPER HIRES MODE PAGE 1 - B & W - 560XL92 2000a5FFF (16K)
6.15
Apple Computer Inc · 1982
Page 0114 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
AI/I VIDEO LOGIC DIAGRAM
FROM
RAM
_- B
BUS'
8000.9FFF
L
S
8K
F2 8
4
CIM
C1M B EN
1 6000. 7FFF
RO DAM A BUS
L
S
8K
3
7E2 8
4
ENH REG
A1
L
s
E3
I
Ql
5EL37L4
CIM AEN
3
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COLOR LATCH
OE37k
c LS374
F
01M
1
CHSO 7R
8
2
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13
C14M RESET
CLKEN 80
6 l5 7 4
Fq 76
LS Q
6
RAMS
VC>2114
VB
E5 & E
DH
WE2i1
NVERSL
LOG IC
H7
11 LS G2
17 1/
11 LS37 G2
ci 4M
1f
li LS 37k
G2
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VA PAG E
pl I RES
MIX
T EXT
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PULL DOWN
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9 G3
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s
RGB
3 .1üR G B2 9 4-5.-RGB 1
9
I.l
14M or 3.5M (AHIRES)
6. SUPER HIRES MODE PAGE 2 - B & W - 560 X 192 6000,9FFF (16K)
6.16
Apple Computer Inc · 1982
Page 0115 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
5EL3714
2000. 3FFF
A/II ViDEO LOGIC DIAGRAM
E NH R EG
'L
s E3
4 11
Ql
1CLKEN 80
CHSO
k l5
7
Cl 4M _____
RESET
'
8
7
VC VB VA
RAMS
2114
ES & E4
101
? DM RES
WE21IL4
NV E RS
LOGIC H7
S
1
J3
1? I9AII IRES LORES
i LS3 G2
j
_i- G2 iuLis 3
0E374
COLOR LATCH 1c LS374
F
4
Cl 4M
l_ LS 374
342-0032
2.i- PAGE f-fflRES
L MIX
IL. TEX
IDEO
C O NT L
ROM
'J DM IRE 14
I ILORS 0E374
C H80 P2
'J All IRE 'J CO LR KL
ri 5EL374 14
Pill I lIP
DOWN
isAD
L
si
9
G3 uM IRES
L 2._. RGB
s 1_.RG8
3 -l-O--RGB2
9 9
14M or
3.5M (AMIRES)
7. AHIRES TEST PAGE 1 - 140X192
2000.5FFF (16K)
6.17
Apple Computer Inc · 1982
Page 0116 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
AI/I VIDEO LOGIC DIAGRAM
- FROH RAM
B BUS
8000. 9FFF
L
S
8K
F2 8
4
C1M
RO RAM
ABUS
B EN
6000.7FFF
L
S
8K
3
7E2 8
4
dM
SEL374
) D4
11
CDt IAEN
3
\8
0E374
COLOR LATCH
C L5374
F3
z'
ENHREG
L
s E3 8
4
1
11
Ql
CLKEN 80 LS 08
fa) CHBO 6
-
7
4
F4
cl4M
6
RESET -_
LSO14 6
7
VCT1
RAMS
2114
E5 & E4
by
WE21I14 NVERS LOGIC
5
RES
1? IAII
I11 IRES LORE
L LS
17 1/
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t
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11,.LS,14 15
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62 if
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'ai OH IRE
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ra PAd E ROM ri IRES
'1 CH8D o
AH IRE
ri MIX
COLRKL ra
ri TEXTE
a SEL37 ra
t4
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1
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G3
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L lø-RGB
S .Z__.RGB
5-ci 3 1'RGB2
9
9
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14M or 3.5M (AHIRLS)
8. AHIRES TEST PAGE 2 - 140X192 6003,9FFF (16K)
6.18
Apple Computer Inc · 1982
Page 0117 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
AI/I VIDEO LOGIC DIAGRAM
CLKEN 80
FROM RAM
C1M
DAM
B BUS A BUS
2000. 3FFF
L S
F2 8
4
lily'
CIII IB EN
11 4000.5:FF
L
s
8K
E2
4
ENHRE
tI1
L s
E3
iI
Ql
t5P
6 Jl5
7 4
F14
CI4M
76
RESET i
LSO4 6
8
RAMS
7
2114
VC 7
VB
VA__. E5 &
'10?
E4
DH RES
WEll
NVERS
LOGIC
H7
S
i S i
J3
AI I
IRES LORE
1- LS G2
CIII 2
SEL37'4
,l 1
CIII
3
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8
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COLOR tATCH
1C 13374 F3
£4
342-0032
f I DEC CO MTL
PACE ROM IRES MIX -
TEXr
DHIRE I ILOR 0E37
CH8O A14 IRE COLRKL
SEL374
pill i lip 15DBL
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-DOWN
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RGB
2-.--I.-RGB
3
LD_I._RGB2
g 44-..-si
9
A
14M or
3.5M (AHIRES)
g, COLOR BAR & GRAY SCALE TEST
2000.5FFF (15K)
6.19
Apple Computer Inc · 1982
Page 0118 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
AI/I VIDEO LOGIC DIAGRAM
C HE O
t7R
LS 08
CLKEN 80
.6 «l5
FROM RA
L S
F2
4
ii uf
1) CiM B EN
13)
110400.O7FF
L
ROM PriM A BUS
S
1K
3
7 E2
4
VC VB VA
O'
WE21 i
8fDHIRES
NV E RS LOGIC
H7
LS3 G2
C1M SEL37i
A EN
3
OE37
COLOR LATCH
1C
LS 3 74
L1__5i
312- 00 32
PAG E
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MIX TEXT
IDEO
CO NT L
ROM
DHIRE 111CR 0E37
Ch80
AH IRE CU IR KL
SEL371i
PUI I LIP
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PULL
DOWN
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9
G3 1HIRES
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lt
L S
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B B
3
B 2
9
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g
A
4M or 3.5M (AHIRES)
10. APPLE II TEXT MODE PAGE 1 - B W - 40 COLUMN 0400.07FF (1K)
i /
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¿7p
J1
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6.20
LSO4 ES
Apple Computer Inc · 1982
Page 0119 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
A//I VIDEO LOGIC DIAGRAM
0800. OBFF
ENHREG
ji-
L
S
E3
4
1K
FROM
B BUS ¡
F2
Ql
RAM
4
13 RO
BUS
11 C1M
B EN
L
s
3 7 E2 8
4
CIM
2 SEL371i
Iii?i
Clii IA EN
3
0E374
COLOR LATCH 1c LS374
4
CLKEN 80
-C ClZ.M
RESET
6 A15
7
4
i Ii
6''
6
LSOI
RAMS
i 2114
VC
VB VA
i E5 &
E4
DH RES
WE21 i L4
NV E RS
LOGIC H7
Si
S
i
J3
11
19A1 IRES LO
I
LS3
C114M
LS3
i4
G2
Ii S
1/b li LS37
62
3k2-0032
IDEO CO NTL
i-PAGE ROM
IRES MIX -,
O TEXT
ri DHIRE
l'lo rei
'j 0E3 'j C H80
AH IRE roi
COLRKL
SE 1374
PU! L JP
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DOWN
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L
Si
9
63
1HIRES
L 2.-RGB
S 2_...RGB
3
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9 35-.-RGBI
9
I4 A
1LIM or
3.5M (AHIRES)
11. APPLE II TEST MODE PAGÉ 2 - B 8 W - 40 COLUrIN 0800-OBFF (1K)
6.21
Apple Computer Inc · 1982
Page 0120 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
A/II VIDEO LOGIC DIAGRAM
FROM RkM
0800 .OBFF
L
S
1K
F2 8
4
'Z-i--.
u131
RA...A BUS1
(il
Ci M
B EN
0400.07FF
L
S
3
7E2 4
ENHR1
Al
L
S
E3
¶11
Ql
dM ) SEL374
0E374
8
COLOR LATCH 1C LS374
F3
k
CH8O
t7W
LS 08 12
)i
I3IES
eCLKEN 80 6 tIl5
7 4
Fq
CikM
6
RESET -C______
LSO14
RAMS
VC 7
2114
VB
VA__L E5 & EL
i0j)
DH RES
WE2114
NVERS LOGIC
H7
All IRES L0
11 LS4 G2
17 11 LS37
> G2
Iit. LS7
ci 4M
ií8
LS374 G2
342-0032
IDEO
PAGE
I RES
CONTL ROM
O MIX
/ TEXT
OH IRE ri
I ILOR
0E37
CH8O AH IRE
N'j
N
'1 COL RKL
SEL374 ri
P1111 lIP
DOWN
i5ADBL L S
i
9
G3
'HIRES
1$
L S 7 -RGB 3 9 45-.-RGB1 g
A
¡9
1kM or 3.5M (AHIRES)
12 SARA LO COLUfIN TEXT MODE TEST- 16 COLORS 0400 SOBFF (2K)
6.22
Apple Computer Inc · 1982
Page 0121 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
A//I VIDEO LOGIC DIAGRAM
L
s
E3
0800 .OBFF
4
L
s
1K
ti
FROM
B BUS
F2
Ql
RAM-
4
13/ RAM
C1M B EN
0400.07FF
L
S
1K
3
7 E2
4
dM
SEL3714
0E3714
\8
COLOR LATCH 1C LS374
14
CHO
7W
S 08
12
13E8
IC1L4M
'-CLKEN 80
.E5
6 il5
7 4 i Di 6 6
LSO14
9-
14
RAMS
2114
VC
VB
VA
E5 & E1
10
DRIRES
E WEZI i
NV E RS
LOGIC
H7
11 LSS
62
17
1h LS37
62
L.i.1
ci 4M
i /
11 LS3714
62 I1
3442-0032
PAGE O -HIRES
/ MIX
O-TEXT
IDEO CONTL
ROM
OH IRE
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0E3
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N CH8O I;'
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FY
P1111 LIP
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L S
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9
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HIRES
L
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S
RG B
3
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9 4-5-.--RGB1
9
or 3.5K (AHIRES)
13. SARA 80 0LUMN TEXT 1100E TEST - B & W
O4OOSOBF (21()
6.23
Apple Computer Inc · 1982
Page 0122 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple Computer Inc · 1982
PDF compression, OCR, web optimization using a watermarked evaluation copy of CVISION PDFCompressor
VIDEO
MODES
A ri
() ()
( 1N P
Pr pw6
ROM & ROM &5 ROM & ROM &ç
pvti fi23
PACTE i
10 0 s
I
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0
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
LSO6
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6.25
Apple Computer Inc · 1982
Page 0124 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
VIDEO OUTPUTS o NTSC COLOR COMPOSITE VIDEO o NTSC B/W COMPOSITE VIDEO o SYNC o FOUR PRIMARY INDEPENDENT VIDEO LINES o MIX TO FORM RGB APPLE COLORS
THREE LINES CAN DRIVE TTL RB MONITOR
6.26
I,
Apple Computer Inc · 1982
Page 0125 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
VIDEO OUTPUTS
S(NC£H 4A'.. RP3
I I
Pk8 ca'I P4rSCt1
LI RaIl. 3 C,01/
I
75
RIZ.
47
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B&W VIDEO
RPT7 -
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Pú52.
XSZ.) 35-9
RGB
5'ftJCH
9 6.27
Apple Computer Inc · 1982
Page 0126 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
acomp*m
6.28
Apple Computer Inc · 1982
Page 0127 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
ucomp%tm
ROM 341-0032
A.A B-B C-S4
D-VBL.
E-PAGE2 F-AtISW' G-HI RES H-MIX I-rExT J-V2 X-V4 DC-PC2 D1-SEL374 D2-COLRKL'
D 3-ARI RES D4-C}f80
D5-0E374 D6-AIILORES D7-DHIRZS
-3
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6.29
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AIISW'
MIX
MIX TE
HIRES
AIIgw*
PG2
PAGE2
$4
VBL
HIRES
MIX TEXT
AIISW*
AHIR.ES
V4 V2 MIX TEXT
HIRES
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AIILORES
0E 3 7 4
6.30
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THE COLR .::E L:;:;Ec
Name Descriprion
1
SG
Shield Ground.
2
XRGS4 One of four CR2 outputs. this (and pins 5, 9,
and 10) is i tTh output with instantaneous color
information. A linear weighted sum of these four
signals vili form a true 16-color RG3 video signai.
3
SYN Composite synchronization signal with negative
going tips.
4
PDI
Not used.
5
flGßl Ses pin 2.
6
GND
Power and signal ground.
7
-5v
-5 volt power supply. A device na draw up to
200 ma through this pin.
8
+12v +12 volt power supply. A device may draw up to
500 ma through this pin.
9
XRGB2 See pin 2.
10
G38 See pin 2.
11
BWV
Black and white composite video. This is an NTSC
composite video signal with, negative-going synch
tips, I volt peak-to peak into a 73 ohm load. Colbr information is encoded as a Unear grey scale.
12
NTSC. Color composite video. This is an NTSC-compatible
video signal with negative-going sych tips, 1 volt
peak-to-peak into a 75 ohm load.
13
GND
Power and signal ground.
14
-12V -12 volt power supply. A device may dray up to
200 ma through this pin.
15
+5V
+3 volt supply. A device may draw up to t amp
through this pin.
This connector supplies 7 different video signals and 4 power supply voltages. Through this connector you can hook up the Apple to any NTSC color or black and white video monitor. With an additional circuit you can hook up the Apple to a studio-quality RG3 color monitor.
All power supply current ratings assume that no peripheral cards are installed in the system. If there are cards in the system, be sure to account for the current drawn by those cards.
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Í Apple /// Computer Information · Apple /// Level 2 Service Reference Manual Apple/// Computer Information Apple ///
Service Reference Manual
Section I of II Theory of Operation
Chapter7 Input/Output
Written by Apple Computer. 1982
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qumpm
INPUT/OUTPUT (r/o)
DESCRIPTION
In Apple computers I/o devices are treated very much like memory locations.
Most of the system's I/O fonctions are mapped into the address range C000 to
CFFF.
The I/O space is enabled by a bit in the Environmental Register.
Addresses CCXX control the onboard I/O. Mdresses Clxx, C2XX, C3XX, and C4XX
are reserved for the exclusive use of the four I/O slots. The I/O expansion
space from C800 to CFFF is switched between the I/O slots. Addresses C500 to C7FF are always Ram, regardless of the setting of the I/O enable bit.
I/O ADDRESS SPACE
oo
R AM
Normal
C4FF C800
CFFF
I/O Space
I/O Expansion
Space
I/O Enabled
INTERFACE CONTROL SIGNALS
For every I/O slot, the Apple 1/I provides 16 locations that set the Device
Select* signal and 256 locations that set the I/O Select* signal.
The Device Select* signal is a signal specific to each slot. It is active for for a 16address block. This signal is ususally used as an enable signal.
The I/O Select* signal can be used to control a page of memory (256 addresses) which could be placed in ROM, in the interface circuitry, for executing "driver routines". The I/O Select* signal could also be used in circumstances where a small amount of read/write memory for temporary storage is needed. Each I/O slot has its own I/O Select* signal, and each signal is active when a specific page of memory is addressed.
The 1/O Strobe La common to all I/O slots. This signal will be low (true) when an address location within the range of C800 to CFFF (2K of memory).
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INTERRUPTS
Interface cards that are capable of generating interrupts MUST latch the interrupt output until it is reset by the software. In addition, they MUST include the ability to mask and unmask their interrupt through software, and MUST default to the masked state when the system is reset.
C09 X
Clxx
COAX C2XX
COBX C3XX
COCx C4XX
Slot i Device Select Slot 1 I/O Select
Slot 2 Device Select Slot 2 i/o Select
Slot 3 Device Select Slot 3 I/O Select
Slot 4 Device Select Slot 4 I/O Select
The method of accomplishing this transmission between the interface and the
I/I, computer is called handshaking. In the Apple
the handshaking is normally
accomplished through the exchange of Device Select*, I/O Select*, IRQ*, and
RIW*. The R/W* control signal is used to synchronize the flow of data to and
from I/O devices. When the Read/Write* signal is a logic one, the processor is reading information from the data bus. Conversely, when R/W* is low, we
are performing a write to the data bus.
As you can see, the handshaking between the Apple 1/I and the interface is
dependent upon the software. Let us again emphasize the role of addressing
plays in the I/O process.
ADDRESSING THE I/O
There are certaLn addresses that you can write to or read from to control the operation of the interface card. Where "n" is the number of the slot where the interface is installed, these hardware addresses are in the range:
C080 + nO to C087 + nO
For example, if you install an interface in slot 2, you should write to the addresses from COAO through COA7.
The operations that the interface card performs are initiated by the read or write operations presented on these hardware addresses.
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cornptaru
THE INPUT OPERATION
In the input operation, whenever the correct address Is presented to the interface card, the data Is present on the data lines D7-DO. For example, If the location C083 + nO corresponds in the software to an input, the data presented on Dl-DO is accepted by the computer. If the interface card contains a control ROM, the code in ROM is being addressed whenever the I/O Select line is low; that is when the address on the address lines is between CnOO and CeFF). Recall that "n" is the slot number.
Device Select Address Bus
Data Bus
TYPICAL INTERFACE
THE OUTPUT OPERATION
In the output operation,
IF the address Co81 + nO represents an output operation In the software
AND the Read/Write* signal is low,
THEN the data is presented on the data bus and latched into the interface whenever the address C081 + nO is presented.
Device Select
Address Bus
Data Busj
TYPICAL INTERFACE
SYSTEM TIMING
A system timing diagram is provided. This diagram shows the timing of some signals at the I/O slots in the 1. MHz and 2 MHz frequency modes.
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I/O TIMING DIAGRAMS
VO Dr
X
19 4
Ñami CM
PH
CIM
:::Dj
2.17
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42.42 37
1. 2C 41
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19 PliC
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36 C
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7.4
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con* .f
TRE A//i JOYSTICK
The A//I has two ports designated for joystick (X and y axis paddles) each with two switches. However, unlike the Apple II the ports do not have "annunicator" outputs. One of the switches is a momentary contact and the other is a toggle.
The Analog X and Y inputs are read through a ramp type Analog to Digital converter (A/D). These values derived must be interpreted by the program. The switches are read to the data bus directly through a mulitplexor.
The 9708 has multiplexed inputs. To select which input channel is to be read the proper address must be set in an addressable latch and must be held during the PDLEN (ramp start) low cycle.
The I/O address for the setting and clearing of the A/D addresses and the ramp start is as shown in the following table:
I/o Address
AID Function
Signal Name
CO58 CO59 CO5A CO5B CO5C CO5D CO5E CO5F
AO Clear
AO Set
A2 Clear
A2 Set
Ramp Start Clear
"
"
Set
Al Clear
Al Set
POLO PDL2 PDLEN AXCO
To read the various signals associated with the joysticks the following addresses should be read:
I/O Address
Function
CO6O8
C061 9 C062,A C063,B CO66,E
Switch O Switch 1/Margin Switch Switch 2 Switch 3/Serial Clock AID ramp stop (PDLOT)
Note: The joystick port at J3 (Port A) can be configured to be a serial port to support a device like-the Sileatype. Care must be taken to insure that the port has been configured for the proper device or signal contention will occur and give erroneous resulte.
The sequence of operation for the A/D would be as follows:
1) set the desired channel address nto A/D O through AID 2.
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2) start the A/D by cycling the PDLEN signal low for 40 micro seconds then back high set up one of the timers to count. test for rasp stop read the counter compute the value of the channel input.
7.6
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öPkZ mixítú
Peripheral Connector Pinout
GND
DMAOK DMAI IONiC
lORES
12v
-5v SYNC C7N Q3
IOCL& C1M
DEVSEL
D7 D6 D5 D4 D3 D2 Dl DO +12V
26
25
+5V
27
24
NOT USED
28
23
NOT USED
29
22
TSADE (Open collector)
30
21
RDT (Open collector)
31
20
I/O STROBE
32
19
PKO
33
18
34
17
AlS
35
16
*24
36
13
*13
37
14
*12
38
13
All
39
12
AlO
40
11
A9
41
10
A8
42
9
*7
43
8
*6
44
7
*5
A//I Peripheral Connector Slot
TOP VIEW 1401 OP PC. 104*0
0kO 2$
0MAO 2?
z,
I P.&.1 21
I5I S 3310
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32
-12V 33
-5V 34
SmC 33
010M3 33?$
___ 31 01M 40 bEVIC& SELLO? 4$
0? ¿2
O0S54443
04 45 03 41 02 4? 01 41 00 41
.12V 50
23 .5V
24 NOT USSO
7333 TI1
21 OT
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P140
Is F«
17 AIS
IS A14
IS £13
14 412
12 AlI
¶3 AlO
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3 £1
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45
6
*4
46
5
*3
F*ON7 0F PC. ICARO
47
4
*2
48
3
Al
49
2
AO
50
1
1/0 SELECT
7.7
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Table 33: Peripheral Connector Signal Description
Pin:
2-17
18 19
20 21
22
23 24 25 26 27
Nane:
Xb Description:
I/O SELECT
O This line, normally high, will become low when the
microprocessor references page $Cn, where n is the individual slot nunber. This signal become active during PMO (nominally 500ns) and will drive 12 LSTTL loads.
AL-Al5
,O The buffered address bus. The address on these lines
becomes valid within 300ns after the beginning of
E1M and remains valid through PMO. These libes will each drive 8 LSTTL loads.
C Buffered Read/Write signal. - This becomes valid
at the same tine the address bus does, and goes high during a read cycle and low during a write. This, line can drive up to 10 LSTTL loads.
PMO
O A 1 z- signal which is identical to dM. This
line will drive 5 LSTTL inputs.
ITO STROBE' O
This line will go low, during CLM when the address bus contains an address between $C000 and $CFFF. This line will drive 12 LSTTL loads.
RDY
Z The 6502's RDY input. This line should change
only during CIM, and when low will halt the
microprocessor on the next read cycle. This ilne
has a 1K ohm pullup to +3V. This line should be
driven fron an open collector output.
TSADB
A low on this line from the peripheral will cause the address bus to tn-state for Direct Memory Access (DMA) applications. This has a i K ohm resistor pullup to +5v. This should be driven from an open collector output.
'M Not used in axt Apple
i/I. Not used in an Apple
+3V
Positive 5-volt supply, 2.0 amps total for all
peripheral boards together (but note a limit of
1.3 Watts per board).
GND DMAO
N'4' System circuit ground. O volt line from power supply. Do not use for shield ground.
t
Acknowledge signal to the peripheral following
7.8
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its request for the special Direct Memory Access
(DMA) mode. Informs the peripheral that the DMA can now proceed.
28
DMAI
Z Direct Memory Accesa (DMA) interrupt. Requests the A
I/f Apple
DMA mode. Baa a 1 K ohm pullup to +5.
This should be driven from an open collector output.
29
tONNI
Z
Input/Output Non-Maskable Interrupt. This is
114f J$Z O5
equivalent to the lORES (pin 31) line as it will
,t execute the same code in the Autostart ROM. This
line should be driven by an open colleccor
1jl%4j
30
X
This line is ignored in Apple H emulation node.
It should be driven by a TTL output.
31
LORES
O
Input/Output Reset signal used to reset che peripheral
devices. Pulled low by a power on or RESET key. This
line will drive 12 LSTTLJ loads.
32
1.
Inhibit line. When a device pulls this line low, all
system memory is disabled. This line has a I K ohm
puilup resistor to +5v and should be driven form an
open collector output.
33
-12V
0
Negative 12 volt supply, 200mA total for .aU.. peripheral
boards together.
34
-5v
0
Negative 5 volt supply, 200mA total for l...periperal
boards together.
35
SYNC
O
The 6502 opcode synchronization signal. Can be
used for external bus control signals. Will
drive 10 LSTTL loads.
36
dM
D
Seven MHz high frequency clock. Will drive LO
LSTTL loads.
37
Q3
o
A 2}ffiz (nonsymetrical) general purpose timing signal.
Will drive 10 LSTTL inputs.
38
0
Complement of CIM clock. This will, drive 12 LSTTL
loads.
39
IOCL&
Provides the $C800 space disable function directly
without address decoding ($CFPF is used for Apple )[ peripherals. It is addressed from $CO2x. This line vili, drive 12 LSTTL loads.
40
0
Phase C1M clock. This is the same as the
microprocessor's i MHz clock. This will drive 12 LSITL loads.
41
DEVICE SELECT This line becomes acive (low) on each peripheral
7.9
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42-49 Dl-DO
50
+12V
connector when the address bus is holding address
between $COnO and $COnF where n is the slot nunber
plus $8. This line will drive 12 LSTTL loads.
Zo The 8-bit system data bus. During a write cycle, data is set up by the 6502 less than 300ns after
the beginning of CTiÏ. During a read cycle the 6502 expects data to b. ready no less than iCOna
before the end of dM. These lines will drive 8 LSTTL inputs. 0 Pocitive 12 volt suppl 3COA total for alj peripheral
board. together.
Nr7 7br,1L /4I.L Ze.#w
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4çc3it, i' /S(
7.10
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amput
The Real Time Clock/Calendar
I/I A real time clock has been incorporated into the A
using 58167 CMOS
Clock/Calendar chip. This chip has the resolution to count to thousandths of
a second. The clock circuitry can be set to cause an interrupt at intervals
from a tenth of a second to interrupts every month.
Since the clock is a CMOS circuit it consumes about lOua in the standby (power
I/I) off in the Apple
mode. This is about the sane as a normal LCD watch.
Three "AA" alkaline batteries are mounted in a battery pack that clips to the
casting near the internal speaker. Wires attached to the battery holder
connect to a 2 pin molex connector at location G13.
This clock chip is not a member of the 6500 family and is not directly compatible. Special considerations have been incorporated into the logic design
to allow the Apple III to accesa and control of the clock chip.
The timing requirements for the clock chip require that the address lines be
latched for much longer than the processor can accomplish in normal operations, so the clock is addressed with the "Zero Page Register" (the B port of VIA B6). The operating system will temporarily store the current zero page address at another location then write the desired clock address into the zpage register. The processor clock, PRO, is extended to usec by the action of the prom 180 and associated circuit. The clock chip also requires a separate read and write strobe so appropriate logic was designed to split the R/V signal into a read and write strobe.
When the processor has completed its access to the clock it will return the proper zero page address to the VIA and PRO will return to its normal operation.
Please refer to the specification sheet in the Appendices for complete details of the clock.
I/I The transistor array performs two functions. One it supplies Vcc from the power
supply when the Apple
is "on", and develops a power down strobe to the clock
chip to set its standby mode just before the supply fully decays.
The clock may be programmed that while it is in the standby mode to provide a PDINT to an external device which may restore power to the Apple to service a particular device. This feature would be very useful in communications networks that poil at specific times in offhours. However, at the time of this printing no such remote device has been specified.
The clock runs on a 32KHZ crystal may be adjusted to an operating tolerance of 5 minutes a month. There are two methods used, on is a vertifications of operation using software, this however has the accuracy of approximately 5
minutes a month, which for many applications and users is close enough, but for those users who demand a closer setting a method of setting the clock using an accoustic probe and frequently meter is available. The only problem with this is the cost of the calibration equipment (nearly $1000 per station). Level II centers will most likely be equipped with these devices.
It should be noted that there is a slight shift if frequently between power on
7.11.
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placomput
and standy modes. Depending on the actual usage of power on and off the clock may vary perceptibly over the course of a month. So it is best to describe the entire function as a clock, not a chronograph.
7.12
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i Apple /// Computer Information · Apple /// Level 2 Service Reference Manual Apple 1/! Computer Information Apple ///
Service Reference Manual
Section lof Il . Theory of Operation
Chapter 8 The l<eyboard
Written by Apple Computer. 1982
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öppIa - u
THE KEYBOARD
I/I The Apple
has a built-tn 74 key typewriter-like keyboard which includes
full alpha/numertcs, four cursor control keys, two special function keys, and
a numeric keypad. It h88 full upper and lower case ASCII code generation
capability as well as full incorporation of Apple J( functions.
The drawing on the previous page shows the standard keyboard legend and details the keystation number. Note that ta addition to the 74 keys there is a recessed Reset key. Every key on the keyboard can be observed individually by the soft- ware. The Control and Shift keys modify the key codes when presented to the system.
The keyboard is electrically connected to the main circuit board by a 26 conductor ribbon cable. The cable plugs into a socket on the keyboard and the main circuit board. The signal assignment is shown on the Pin Signal Assignment table.
Repeat Functions
Any key held down for re tim 1/2 second is automatically activated to repeat
at a iO PS rate. A high speed (30 CPS) repeat function is activated by
holding down the closed Apple key (Key #68) after depressing and holding the
I/I key to be repeated. An idiosy-ncracy of the Apple
is that if the closed
Apple key is depressed before another key, it is displayed as only one charac-
ter. If it is depressed after another key, the high speed repeat is
activated.
The four cursor contiol keys (63, 70, 71, 72) are two-contact keys. This means that as the key is partially depressed, it makes its first contact generating a signal code. When it is fully depressed, it will make a second contact, automatically activating a high speed repeat of that key.
READING THE KEYBOARD
The keyboard can be thought of as two hardware ports (busses) that can provide two distinct types of data. The first type is ASCII, which is addres8ed by Memory Address C000; we will call this the KA port. The KA port always con-
tains the lower 7 bits of the ASCII code and, like the Apple JE, uses the MSB
as a keyboard data ready' flag. The second type of data is addressud by Memory Address C008; we call this the KB port. The KB port looks at the
direct connect" keys and at the eighth bit of the key code. A summary of the bit meanings for these two types of data is shown in the table at the top of
the following page.
8.1
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Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
KEYBOARD
KEYBOARD ENCODER MATRIX VERTICAL Y
KEY PAD
YO
A
Z
ESC
TAB
Yl
i
Q
s
x
Y2
2
W
D
C
Y3
3
E
F
V
SPACE
Y4
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+-
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NONE
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NONE NONE NONE
NONE
KEYBOARD HORIZONTAL X
KEY PAD
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2
3
4
5
6
7
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Xi
TAB
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- ENTER
8.4
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MEMORY ADDRESS REFERENCE
LA PORT (C000)
Bit O
Bit 1.
Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
ASCII Bit O
ASCII Bit i ASCII Bit 2 ASCII Bit 3 ASCII Bit 4 ASCII Bit 5 ASCII Bit 6
l'-"data ready flag"
KA PORT (C008)
* Bit O
* Bit i * Bit 2 * Bit 3 * Bit 4
* Bit 5 * Bit 6 * Bit 7
"l-"any key down"
"O"'-"shift depressed" 'O".'control depressed" 'O"'"alpha lock set" "0'&'Apple i switch depressed" "0'."Apple 2 switch depressed" "l"-"start up uncommitted mode" ASCII Bit 7
The KA data is used exactly like that in the Apple ] ( keyboard. The KB data
is provided for function expansion. The KB ports i to 5 are direct mechanical
connections to defined function switches. Bit O is an output f rois the encoder
I/I circuity and bit 7 is the eighth bit of the key code. Bit 6 Is a special bit,
a flag used during turn-on to show that the operational mode (Apple
or
Apple ][) has not yet been determined..
It should be noted that the Reset key cannot act on its own but has to be
depressed with another key. This is a safety feature to prevent blowing away
a good nights programming effort. Now isnt that nifty!? A CONTROL- RESET
will give a true system reset. However, it cannot be used for recovery from
f/f Apple ]( mode. The CONTROL-RESET will also give the system an NMI (Non-
Maskable Interrupt). This provides Apple
with two levels of "reset."
8.5
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KEYBOARD CODES
A complete list of the codes generated by the encoder circuitry is presented is the following table:
Table: Apple /1/ KEYBOARD CODES (HEX)
Key # Key Name US SH cr SU-CT
Key # Key Name US SH CT SU-CT
1*
2
3 4
6 7 8 9
10
11 12 13
14 15* 16* 17* 18* 19 20 21 22 23 24 25 26 27 28 29 30 31 32* 33* 34*
35 36 37 38
ESCAPE
9B 9B 98 98
1
31 21 31 31
2
32 40 32 00
3
33 23 33 23
4
34 24 34 24
5
35 25 35 25
6
36 5E 36 53
7
37 26 37 26
8
38 ZA 38 ZA
9
39 28 39 28
0
30 29 30 29
-
2D 5F 2D iF
-
3D 2E 3D 2B
BkCKLASH 5C 7C 7F IC
7
B7 B7 B7 B7
8
38 38 B8 B8
9
89 B9 B9 B9
TAB
89 89 89 89
Q
51 51 11 ii
W
57 57 17 17
E
45 45 05 05
R
52 52 12 12
T
54 54 14 14
Y
59 59 19 19
U
55 55 15 15
I
49 49 09 09
0
4F 4F 0F OF
P
50 50 10 10
RT-BRACK 5B 7B lB IB
LT-BRACK 5D 7D in in
LT-BRACI( 60 7E 60 7E
4
B4 84 B4 84
5
B5 B5 B5 B5
6
86 36 B6 86
CONTROL
KB-2
A
41 41 01 01
S
53 53 13 13
D
44 44 04 04
39 40
41 42 43 44 45 46 47 48* 49* 50*
51 52 53 54 55 56
57 58 59 60 61 62 63* 64* 65* 66 67 68 69* 70* 71* 72* 73* 74*
F
46 46 04 04
G
47 47 07 07
H
48 48 08 08
J
4A 4A OA OA
K
4B 4B OB OB
L
4C 4C OC OC
3B 3A 3E 3A
-
27 22 27 22
RETURN
OD OD OD OD
1
BI Bi Bi Bi
2
B2 82 32 82
3
SHIFT
83 B3 83 B3 KB-I
Z
5A 5A lA lA
X
58 58 18 18
C
43 43 03 03
V
56 56 16 16
8
42 42 02 02
N
4E 4E 0E 0E
M
4D 4D OD OD
,
2C 3C 2C 3C
2E 3E 2E 3E
/
SHIFT
2F 3F 2F 3F KB-1
IP-CURSOR 8B 8B 8B 88
0
BO BO BO BO
.
ALPHA-LK
AE AB AE AB KB-3
APPLE I
KB-4
APPLE 2
KB-5
SPACE
AO AO AO AO
LT-CURSOR 88 8B 88 88 RT-CURSOR 95 95 95 95
DN-CURSOR 8A 8A 8A 8A
-
AD AD AD AD
ENTER
8D 8D 8D 8D
* Bit 7 (MSB) on these keys appears on bit 7 of KB port, on the KA port. Note: the keys on the numeric keypad have only one code. Shift and Control
8.6
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have no effect on these keys.
THE APPLE II EMt1LATION MODE
I/I In this mode the Apple
special functions are locked out, making the
keyboard look exactly like the Apple JE. Thus, the Apple ]( software does not
look at the KB port and muet get all the Apple J [ codes for the KA port. This
I/I is the reason for coding and bit arrangements. However, the Apple
functions are not really locked out and could be read by an enterprising
programmer, if desired.
Some of the keyboard codinge which should be noted because of the Apple II emulation mode are:
It, "wtit is a coottoj- (Contro1-ShLf t-2). With the Apple
the
"NUL" is a Control-Shift-p.
"RS", record separator, is a control-Shif t-6, which corresponds to control-Shift-n in the Apple ](.
The Shif t-m, for a left square bracket in the japple J[, is not
available in the emulation mode since the character is represented
on the keyboard. The "", group separator, is a Control-left bracket rather than the Control-Shift-rn.
"BS, backspace, has been retained for the left arrow and "NAK",
negative acknowledgment, for the right arrow for both the Apple
I/I JE and Apple
modes.
"VT", vertical tab, and "LF, line feed, were chosen for the up and down cursor keys. In the Apple ][ mode these will not give a cursor movement (unless the operating system is changed) but will give the Control-k and Control-j codes. This could cause some slight confusion for those Apple J [ programs that use those codes (...now be tells me!).
The autorepeat and high speed repeat functions will work for the
I/I Apple ]( just like they do in the Apple
mode. Nice!
ELECTRONIC CIRCUIT DESCRIPTION
Please refer to sheet 9 of 10 of the Schematic (Drawing Number 050-0039) for the following Keyboard Logic circuit description.
I/I The Apple
keyboard is simply an 8 by 10 X,Y matrix which is scanned by the
encoder circuit [keyboard encoder rom }fl4] on the main logic board. All keys are scanned with the eceptionof five keys [shift, control, capsiock, Applel,
Apple2] that are direct connected. The second contacts of the cursor keys
(high speed repeat function are ORd wired into the Apple2 switch line on
KB-5.
8.7
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ippIa «pitar ri
On the main board the encoder scans the keyboard matrix and provides the correct code outputs plus a strobe and an "any key down" signal. A diagram for the key matrix shows the key locations, and their ASCII character representations are shown on the following page. The special function keys can be detected separately from the standard control keys by observing that the MSS of the KB port is set high.
The Ai signal to the Tn-state data selectors (LS257's) selects whether the output of the LS257 will be a KA or KB port. If A3 is high, selected by memory address C008, the KB port is selected. The KBD line enable the reading of data off the keyboard.
The Repeat Function: The normal repeat function (LO cps) that occurs when a key is held down is the result of clocking and resetting the flip-flop Hil (feeding into 812). This is accomplished by the AK (any key) and DTRDY (data ready) setting, 811 then having CLRSTB (clear strobe) resetting the flip-flop. The Apple2 key, when depressed after a character key, engages the high-speed repeat function. The combination of the Apple2 key signal clocking the edge triggered flip-flop (Ru), and pulse change to the inputs of the 556 (Lb) dual timers speeds up the timing.
The Reset Function: The power on reset is provided by the one shot (AS). Depressing the reset key results in a soft reset. This causes the KRESET line to go low and enable the tS139 (flu). If the Control key and the Reset key are both depressed, a hard reset results. This hard reset can be foiled through sophisticated programming. The R.ESETLK (reset lock signal) provided from the Environmental Register [6522 - B6], can disable the Reset and NMI. (Try it!)
Keyboard Light: The keyboard light indicates the VCC is provided to the keyboard. If no light is observed, check Q9 [MPV 511.
8.8
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7'/Ñ
Pin -
i
3 4 5
7
O 10 li 12 13
IS
I,
'escription
(n
vi
Poker Light
'(2
pnle 2 (high speed repeat)
':3
Apple L
'/4
Alpha Lock (alternate action) Y5 Control
Sinal (round
XC Reset X2
20
x3
'1
22
'(0
23
(6
24
Shift (both keys)
(7
26
/4'
'J
8
J t,
7 2&'.
7
u
.77
89
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- w,et&wrs /f'Lf > AMC/H9L
Table 2: Keys and their Associated ASCII Codes (Bit 7 always set)
Key
Alone CONTROL SHIFT Both
<space> ESCAPE
1!
2@ 3D
4$ 5Z 6 76 8*
9( O) -
\I
TAB
$AO $93 $31 $32 $B3
$34 $35 $B6 $37 $53 $89 $80 $AD $BD $DC $89 $DB $DD
RETUR1
s> 1?
<left arrow> <right arrow>
<up arrow) <down arrow>
ENTER
k
B C D E F G H I J
K
L M N O P Q R
S T
$8D $AC $AE 5k?
$88 $95 $8B 58k 5kB 5kO $80 5Cl $C2 $C3 $C4 $C5 $C6 5Cl $C8 $C9 $CA $CB 5CC $CD SC! $CF $DO $01 $02 $03 $04
SAO $9B $31 $B2 $33
$34 $B5 $36 $B7 $53 $89 $50 SAD $BD $9C $89 $93 $9D $A7. $8D $AC $AE $AF
$88 $95 $85 $8k 5kB $AD $80 $81 $82 $83 $84 $85 $86 $87 $88 $89 $8k $83 $8C $8D $8E $8F $90 $91 $92 $93 $94
SAO $93 $A1
$CO
$A3
$A4 $A5
$DE
$A6 $AA $A8 $A9 $DF 5kB $FC $89 5FB $FD $A1 $8D $BC $BE $5F
$88 $95 $85 $8k 5kB SAD $80 5Cl $C2
$C3 $C4 $C5 $C6 $C7 $C8 $C9 SCA $CB $CC $CD $CE $CF $00 $01 $D2 $D3 $04
$AD $93
58G $A3 $A4 $A5 $9E $A6
$A8 $A9 $9F $AB $FP $89 $93 $9D $A2 $8D $BC $BE $BF $88 $95 $85 $8A $AE SAD $8D $81 $82 $83 $84 $85 $86 $87 $88 $89 $8k $85 $8C $8D 58E $8F
$91 $92 $93 $94
8.10
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U
$D5
$95
$D5
$95
V
$D6
$96
$D6
$96
W
$D7
$97
$D7
$97
X
$D8
$98
$fl8
$98
Y
$D9
$99
$D9
$99
Z
$DA
$9A
$DA
$9k
8.11
Apple Computer Inc · 1982
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Apple Computer Inc · 1982
n'
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
I3I2C3sS- 31 JCJ
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Apple Computer Inc · 1982
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i Apple /// Computer Information · Apple /// Level 2 Service Reference Manual Apple /// Computer Information Apple ///
Service Reference Manual
Section I of Il . Theory of Operation
Chapter 9 Power Supply
Written by Apple Computer . 1982.
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I/I THE APPLE
POWER SUPPLY
The Apple ¡/1 power supply converts power from the AC line to DC. This is
a constant voltage power supply. This means:
The output voltage is maintained constant regardless of changes in the load, line, or temperature.
The Apple /1/ power supply is a free running f lyback type, off line
switching power supply.
- It can accept either 1ISVAC or Z3OVAC (jumper selectable) and
delivers 4 regulated DC outputs at a total of 55 watts.
- It supplies +5, -5, +11.8, and -12VDC.
- It is called a f lyback type power supply becau8e energy is transf erred from the primary of the transformer to the secondary when the switching transistor switches off (during f lyback).
The following paragraphs will describe the switching power supply in more detail.
THE BASIC SWITCEING POWER SUPPLY
The regulating element of the switching power supply consists of a transistor that acts as a rapidly opened and closed switch. The AC input Is rectified to unregulated DC, then "chopped" by the switching element components at a fast rate, approximately 25kHz. The resultant is transformer-coupled to an output network which provides the finsi rectification and filtering. Regulation is accomplished through control circuits that vary the on-off periods (duty cycles) of the switching components.
Advent ages
Greater Efficiency
- Lower power i. dissipated because of the on/off role of the regulator. The switching transistors dissipate very little power when either saturated (on) or cutof f (off). With less wasted power, the switching power supply runs at cooler temperatures and costs less to operate.
Size and Weight
- Because components such as capacitors, transformers, and inductors operate at high switching rates they can be smaller and weigh less than those that operate at power line frequencies.
Operating Conditions
- The switching power supply can operate under low AC conditions and can sustain (holdup) its output if input power is momen-
9.1
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i
r
ThE APPLE I/I FG[R SUPPLY
PARTS LAYOUT
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tarily lost. This is because the AC input is rectified and the filter capacitors charge to peak voltages on the AC line.
Disadvantage.
Transient Recovery Time
- The dynamic loading regulation is slower than that of the series regulated supply. The recovery is limited mostly by the inductance of the output filter network.
EMI (Electro-Magnetic Interference)
- This is a natural byproduct of this type of power supply. This E141 can be conducted to the load (resulting in higher output ripple and noise), and it can be conducted back into the AC line. (Now you know where that stuff on TV came from).
- Apple designed this power supply with filter networks and shielding to greatly reduce Eilt.
HOW IT WORKS I
Regulation is accomplished by a switching transistor Q2 operating under control of a feedback network. The feedback network, consisting of a voltage comparitor and blocking oscillator, controls the duty cycle of the oscillator.
The energy is transferred from the primary to the secondary of the transformer and delivered to the output rectifier/filter. Here the waveform is rectified and averaged to provide a DC output level that is proportional to the duty cycle of the waveform.
Referring to the block diagram, Pigure x.x below, note that:
o The AC is passed through an EllI filter and then rectified to provide approximately 300 VDC across the capacitive input filters (C6, Cl, C8 C9 of the schematic diagram). This voltage is applied to the primary of the transformer (T2) by the switching elements (turning on power transister Q2). A linear current ramp is developed by the primary inductance of the transformer.
o When the switching elements are turned off, the energy stored in the transformer is transferred to a second set of rectifiers through a capacitive filter network to provide filtering of the output.
o The +5 volt output of the final rectifier network is compared to a reference voltage, and the error is fed back to a blocking oscillator.
o The blocking oscillator basically changes the frequency depending on the output voltage. This in turn changes the repetition rate of the switching elements, which changes the energy transfer through the transformer and voltage output. This is how regulation is accom-
9.3
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CAP FILTER
BLOCKING OSCILLATOR COMPARITOR
T R A
RECTIFIEP N S
F
SWITCHING ELEMENTS
CAP FI LIER
RECTIFIER
EM I
FILTER
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REGULATED DC OUTPUT
o
TT
DUTY-CYCLE CONTROL
OUTPUT RECTIFIER FILTER
p
SWITCHING MENTS
T
INPUT RECTIFIER
INPUT
AC
c.n
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ccfinpl.*ar rK.
pushed.
o If the output voltage should change in such a way that the blocking oscillator goes into saturation, the output is essentially cut off.
DETAILED HARDWARE DESCRIPTION (Refer to Schematic I
A THERMISTOR, Rl, is used to limit AC input surge current by its negative temperature coefficient of resistance. When cold, during turn on, RI has a high resistance; after it heats up, Rl has a low resistance.
VDRI is a varistor and is used as a transient suppressor. It keeps voltage spikes that result from power supply switching from affecting the performance of the power supply. It basically provides AC line surge current protection at turn on.
THE AC LINE SELECTABLE JUMPER, when connected to 220V position, causes the power supply to act as a conventional full wave rectifier. For 120V AC inputs the input circuitry becomes a voltage doubler.
THE EMI FILTER made up of Ti, Li, L2, and Cl, helps prevent high frequency RFI spikes from being conducted to the load or back into the AC line.
DB! is a diode rectifier bridge.
THE SWITCHING ELE)NT consists of the circuitry associated with Q2 and Ql. You may recall that the linear current ramp, developed in the primary of the transformer when Q2 is turned on, is transferred to the secondary when Q2 is turned off.
The turn on of Q2 is accomplished by R2 for starting, and thereafter by the feedback winding in T2 driven by R4 and ClO. This winding initiates turn on during the ringdown following the f lyback.
If a sufficient voltage is developed across R9, Ql will be forward bias. This would occur if by chance one of the output voltages were shorted. In that case, the oscillator would stop and shut off ail the outputs, pause for 1/2 second, and attempt to restart.
THE OUTPUT RECTIFIER DIODES, D7 through D12, provide rectification, but also protect internal components against reverse currents that could be injected into supply by an active load.
ICi helps accomplish regulation by comparing the output voltage against its own internai reference and delivering a voltage level to the base of Q3.
The emittet of Q3 is driven by a positive going ramp created by the inductive resistance associated with R14 while Q2 is on. When this voltage is sufficient to forward bias the emitter-base junction of Q3, conduction of Q2 is terminated.
You can now see that the operating frequency varies with the line and load.
OVERVOLTAGE PROTECTION is accomplished by sensing the +12v level via the re-
9.6
I
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sistor voltage divider of R17 and RiS referenced to the zener voltage on Zi. When the +12v output rises above tolerance, Q4 is turned on, which in turn triggers SCR1. SCRI then clamps the +12V to ground, causing the power supply to fold back.
9.7
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y
so
L
w 4ia ARt +0V OUTPUT aO.*JST 54 4) -
SCHEMATIC. APPLE /// POWER SUPPLY
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0.5V
OCOU
o-u, tZ
I' 'As
Ip
I.
I
IL, I Or.
ti!- I I'
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LS
IS, LI
TI II LA
SCHEMATIC: APPLE /// POWER SUPPLY
LAI 5W OUTPUt AOIL4TSt$tO
...(s sci
s
SS'
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*41.
u
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vuut"tua ,v o ulISV
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REF
BRI COl CO2 CO3 C04 CO5 C06 C07 C08 C09 Cb Cil C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 DOl D02 D03
APPLE III POWER SUPPL'
DESCRIPTION
AC Input Socket Connector Housing i CGT Crinp Terminal Double Side Tape Width3x4tnm Faston Tab Heatsink Insulator 298. 45X88.9MM Mut M3 P0.5 MS/NP On/Off Switch Pan PHL Pan M.0 Screw M#xlZ P0.5 BS/NP PHI. Pan M.0 Screw M3X8 P-0.5 aS/NP PHI. Pan H/C Screw M3X8 P-O.5 BS/NP PVC Coating CU Wire 100MM UL1OI5 PVC Coating CU Wire 80MM UL1015 PVC Coating CU Wire 95MM (11.1015 Rectifier RG3B Resistor, 68K +-5Z 1/4W, Carbon Film Resistor, 82K +-5Z 1/4W, Carbon Film SCR C122u Solder Bar Solder Bar 60/40 Spring Washer M3 BS/NP Standoff M3
Bridge Rectifier KBP1O Cap, 0.22uf, 25OVAC, Metaltized Paper Cap 0.luf, 250VAC, Metallized Paper Cap, 4700pf, 400 yAC, Ceramic Cap, 4700pf, 400 yAC, Ceramic Cap, 0.luf, 400 V, Polyester Cap, iOOuf, 250v, Electrolytic Cap, iOOuf, 250 V, Electrolytic Cap, lOOuf, 250v, Electrolytic Cap, lOOuf, 250V, Electrolytic Cap, lOOuf, 250V, Electrolytic Cap, O.00luf, 3Kv, Ceramic Cap, 2Zuf, 100V, Polyester Cap, i000uf, 10V, Electrolytic Cap, i000uf, 10V, Electrolytic Cap, i000uf, 10V1 Electrolytic Cap, i000uf, 10V, Electrolytic Cap, 330uf, 16v, Electrolytic Cap, 22ouf, 10V, Electrolytic Cap, O.22uf, 100V, Polyester Cap, l000uf, 10V, Electrolytic Cap, 0.22uf, 100V, Polyester Cap, l000uf, 10V, Electrolytic Cap, 330uf, 16v, Electrolytic Cap, 680uf, 16v, Electrolytic Cap, 330uf, 16V, Electrolytic Cap, 0.1/1KV, Ceramic Diode, Rectifier, RGPIOA Diode, Rectifier, RCPIÛM Diode, Recitifier, RGP104
9.10
QTY
PALT NUMBER
149-00200020
1
138-00000170
1
403-02200510
20
0270140001')
1
4O3-O22O07Ot.
1
398-00200060
1
183-00101410
2
394-00400011
1
278-01100010
1
403-01101810
2
391-20204141
3
391-20204061
1
391-20204021
1
356-12200571
1
357-1 1800545
1
356-12200566
3
226-10700011
2
240-68306022
2
240-82306022
1
227-13000010
1
366-00130010
0
366-00130010
10
392-00800031
8
393-00200100
226-30500010
1
068-22400010
1
068-10400010
2
055-47220001
2
055-47220001
1
058-10400100
4
057-101201170
4
057-101201170
057-10120170
4
057-101201170
1
057-22120080
055-10261328
2
058-22400120
6
057-10220020
6
057-10220020
6
057-10220020
6
057-10220020
057-33120080
1
057-22120060
1
058-22300080
057-10220020
058-22400120
057-10220020
3
057-33120080
1
057-68120010
3
05733120080
1
055-10360925
1
226-10400050
2
226-10400100
2
226-10400100
Apple Computer Inc · 1982
Page 0168 of 0730
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REF
D04 D05 D06 D07 D08 D09 DiO
DJ.1
D12 D13 Fi ICi Ji J2 J3 J4 Li L2 L3 L4 L5 L6 L7 L8 Ql Q2 Q3 Q4 ROl R02 R03 R04 R05 R06 ROl R08 R09 RIM R12 R13 R14 R15 R16 Rh
P.18
R19
P.20 P.21
R22 R23 R243
P.25
APPLE III POWER SUPPLY
DESCRIPTION
Diode, Rectifier, 1N400IGP Diode, Silicon, 1N5282 Diode, Silicon, 1N5282 Diode, Rectifier/Scr Assembly Diode, Rectifier assembly Diode, Rectifier Assembly Rectifier Assembly Schottky Diode S3SC3M Rectifier RG3B Diode, Silicon, 1N5282 Fuse 2.75A 125V Integrated Circuit, Regulator, TL43LCP Jumper Wire Jumper Wire Jumper Wire Jumper Wire Choke Choke Base Choke Choke 1.5tnR Choke Coil Assembly Choke Coil Choke Coil Choke Coil Transistor SD467 Transistor 2SC1358 Transistor SB561 Transistor S8561 Thermistor, 4R @25 C -4--10% 6R @ 25 C -4-20% Resistor, 150K l-5% 1/2W Resistor, 150K l-5% 1/2W Resistor, l--5% 47R 2w, Metal Oxide Resistor, l--5% 1/4W 1.2K Resistor, 5.6R +-5Z 1/4W Resistor, +-5% 56R 1/4W, Carbon film Resistor, +5% 120R 2W Resistor, l--5% 1/4W 15R ReBistor, l--5% 1/4W bR, Carbon Film Resistor, O.47R, Metal Film Resistor, -5% 114W 39R, Carbon Film Resistor, +-5% 270R 1/4W Resistor, +-5Z 270R 1/4W, Carbon Film Resistor, 8.2 -I-5% 1/4w, Carbon Film Resistor, l--5% 680R 1/4W Resistor, l--5% 1.8K, Carbon Film Resistor, +-5% 2.2K, Carbon Film Resistor, +-5% 2.7K 1/4W, Carbon Film
Resistor, +-5% 560R 1/4W, Carbon Film Resistor, 22R 1/4W -4--5%, Carbon film Resistor, lOOR +-5Z 1/4W, Carbon Film Resistor, 56R 1-5% 1/4W, Carbon Film Resistor, 56R 1-5% 1/4w, Carbon film Re sis tor, 12K +-5% 1/4W, Carbon Film Resistor, l--5% 1/4W 470R, Carbon Film
QTY
i
3 3
1
3
i 1
4 4 4
40
2 2
i 1 i 1 i i 1 i
2 2 1
2
1 1 1
2
1 1 1
3
1
PART NUMBER
226-10400080 2 12-10700200 2 12-10700200 853-00700010 853-00200 140 853-00200140 853-00200140 212-3 1100030 226-10700010 212-10700200 084-00200040 211-10800070 358-80810011 358-808 10011 358-80810011 358-80800001 852-201003 50 852-20100350 328-00 100030 328-00100010
85 2-20 1000 10
852-10 100370 328-00100060 328-00100060 209-11700463 209-102000 10
2 10-1 17 003 53
210-11700353 258-409700 15 240-15406033 240-15406033 248-47006063 240-12206022 240-56906022 240-56006022 248-12 106063 240-15006022 240-10006022 247-04786054 240-39006022
240-2 7 106033 240-27 106033
240-82906022 240-68106 022 240-18206022 240-22206022 240-27 206022
240-56106022 240-22006022 240-10106022 240-56006022 240-56006022 240-12306022
240-4 7 106022
9.11
Apple Computer Inc · 1982
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REF
R26 R27 R28 R29 R30 R31 R32 Ti T2 T3 VDRL
Z].
APPLE III POWER SUPPLY
DESCRIPTION
Resistor, +-2% 2.7K 1/4W, Metal Film Resistor, +-2% 2.7K 1/4W, Metal Film Resistor, 100K 4-5% 1/4W, Carbon Film Resistor, 100K 4-2% 1/4W, Carbon Film Resistor, -5% 56R 1W, Matai Oxide Film Resistor, +-5% 220R 1W, Metal Oxide Film Resistor, LP. w, Metal film Common Mode Choke Assembly Power Transformer assembly Control Transformer Assembly Varistor 26OVAC Zener Diode 9.6 to 10.V @ imA
QTY
PART NUMBER
2
247-2701502
247-27015022
2
240-10406022
240-10406022
1
248-56006052
1
248-22106052
1
247-10086054
1
852-20200010
1
852-10200760
1
852-10200680
1
256-26100014
1
22298085002
9.12
Apple Computer Inc · 1982
Page 0170 of 0730
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Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Í Apple /// Computer Information · Apple /// Level 2 Service Reference Manual Apple /// Computer Information Apple ///
Service Reference Manual
Section I of II . Theory of Operation Chapter io Apple][ Emulation
Written by Apple Computer 1982
Apple Computer Inc · 1982
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APPLE II EMULATION RESTRICTIONS
O
NO LANGUAGE CARD
O
NO ROM CARD
O
PADDLES ARE DIFFERENT
O
ENTER WITH SOFTWARE BUT ONLY
RESET WILL EXIT
10.1
Apple Computer Inc · 1982
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THE COLOR VIDEO CONNECTOR
Pin
Ñame Description
i
SG
Shield Ground.
2
XRG34 One of four GRB outputs. This (and pins 5, 9,
and 10) is a TTh output with instantaneous color
information. & linear weighted sum of these four
signals will form a true 16-color RGB video signal
3
SYNCR Composite synchronization signal with negative-
going tips.
4
PDE
Not used.
5
XRGBI See pin 2.
6
GND
Power and signal ground.
7
-5v
-5 volt power supply. A device may draw up to
200 ma through this pin.
8
+12V +12 volt power supply. A device may draw up to
500 ma through this pin.
9
XRGB2 See pin 2.
10
XRGB8 See pin 2.
il
8WVID Black and white composite video. This is an NTSC
composite video signal with negative-going synch
tips, I volt peak-to peak into a 75 ohm load.
Color information is encoded as a linear grey scale.
12
NTSC Color composite video. This is an NTSC-cotnpatible
video signal with negative-going sych tips, i volt
peak-to-peak into a 75 ohm load.
13
GND
Power and signal ground.
14
-12V -12 volt power supply. A device may draw up to
200 ma through this pin.
15
+5V
+5 volt supply. A device may draw up to i amp
through this pin.
This connector supplies 7 different video signals and 4 power supply voltages. Through this connector you can hook up the Apple to any NTSC color or black and white video monitor. With an additional. circuit you can hook up the Apple to a studio-quality RGB color monitor.
All power supply current ratings assume that no peripheral cards are installed in the system. If there are cards in the system, be sure to account for the current drawn by those cards.
10.2
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CR-RESOLUTION GRAPHICS (HI-'R.Es) MODE
The Apple )( emulation mode high resolution graphics are identical to the Apple ]( except some combinations of colors on the right edge of the screen will, cause the left edge pixels to blink. This is normal though distracting.
THE SPEAKER
The speaker function is identical to the Apple ]( with the following additional features.
A reference to location 49216 (or the equivalent addresses
-16336 or hexadecimal $C040) will cause a 0.1 second i KHz tone to be produced which is similar to the sound the AUTOSTART monitor makes when the BELL character Le sent to the screen. The advantage to this is 0.1 seconds of cpu time is returned to the user since only i microsecond is required to start the BELL sound.
I/I The AUDIO connector at the back of the Apple
provides the
same signal as the speaker. When you insert a miniature phone-tip
plug into this jack, the Apple's internal speaker is silenced; if
there is an amplifier or other device properly connected to the
plug, then that device will receive all audio signals generated by
the Apple. The signal is a 0.5 volt peak-to-peak audio signal on its tip and signal ground on its ring.
THE CASSETTE INTERFACE
The cassette interface is completely eliminated on the Apple
I/F. References to the cassette output port at 49184 (or the
equivalent -16352 of hexadecimal $CO20) will cause pin 39 of the I/O
slots to go low for a microsecond. This is for use by Apple /1/
native mode peripherals to deselect to $C800 ROM address space.
Reading the cassette input port at 49248 or the equivalents -16288 or hexadecimal $C060 will read joystick switch O into bit 7.
10.3
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I Table 10: Input Output Special Locations
Function
S peaker Beep
Deselect $C800
for Apple /1/
periperals (pin 39 in slots) Joystick switch O Joystick switch 1 Joystick switch 2 Joystick switch 3
AID Select O AID select O
AID Select i A/D Select i
AID Select 2 AID Select 2 A/D Ramp charge A/D Start timeout
A/D Timeout Clock millisecond cotinter ($N0)
Add re s s:
Decimal
Hex
49200 -16336 $CO30 49216 -16320 $C040
49184 49248 49249 49250 49251
-16352 -16288 -16287 -16286 -16285
$CO20 $C060 $C061 $C062 $C063
49240 -16296 $CO58 49241 -16295 $CO59
49246 -16290 $CO5E 49247 -16289 $CO5F
49242 49243 49244 49245
-16294 -16293 -16292 -16291
$CO5& $CO58 $CO5C $CO5D
49254 -16282 $C066
49264 -16272 $C070
Read/Write
R/W R/w
R/W R(bit 7) R(bit 7) R(bit 7) R(bit 7)
R/W R/W
R/W R/W
R/W R/W R/W R/W
R(bit 7)
R(bits 7-4)
Table 9: A/D Selection
A/D2
O o o
oi i
1
i
A/Dl
O
oi
1
o o
1
I
A/DO
O
i
o
1
oi
0
I
Input
Ground Joystick, Port B, X axis Joystick, Port B, Y axis Joystick, Port A, X axis Joystick, Port A, Y axis Clock Battery No connection Reference Voltage
10.4
I
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ANALOG INPUTS
The system has two joystick ports with provisions for two AID inputs each. Joystick Port A reads A/D inputs O and 2 while Port B reads inputs i and 3 as defined in BASIC and the monitor subroutine
P READ.
To read the AID inputs, the software must select the desired input and charge the ramp capacitor for at least 500 microseconds. Then the ramp is started and the time measured until the AID timeout goes low. The discharge time is proportional to the input voltage.
STROBE OUTPUT
The strobe output ($C040) has been replaced by a 0.1 second i KHz tone from the speaker.
I AUTOSTART ROM MONITOR ROM
The Apple J[ emulation only comes with a modified version of the Autostart ROM. This is in write protected RAN which is loaded when the Apple ]( emulation disk is booted.
10.5
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THE SYSTEM MONITOR
SAVING A RANGE OF MEMORY ON THE TAPE
Since there is no cassette port on the Apple /1/ the W (for WRITE)
cotand has no effect. The code in the Emulation mode Autostart Monitor contains an RTS instruction followed by NOP instructions, follosied by BRX instructions. This fills the space occupied by the WRITE subroutine (locations $FECD-$FEF4).
READING A RANGE FROM TAPE
Again, since there is no cassette port the R (READ) command has no effect. The READ subroutine contains an RTS followed by NOP
instructions, followed by BRX instructions (locations $FEFD-$FF2C).
SOME USEFUL MONITOR SUBROUTINES
$FBIE PREAD READ A JOYSTICK AXIS
PREAD will, return a number which represents the position of a joystick axis. You should pass the number of the joystick axis (0 to 3) in the X register. If this number is greater than 3, port A, Y axis is read. PREAD returns a number from $00 to $FF iii the Y register. The accumulator is scrambled.
Joystick
Port A, X axis Port B, X axis Port A, Y axis Port B, Y axis
Reference I
O
i
2 3
10.6
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pcompm
Address: Decimal
1008 1009
lolo loll
Hex
$370 $371
$372 $373
1012
1013 1014 1015
1016 1017 1018
$374
$373 $376 $377
$3F8 $379 $37A
Page Three Monitor Locations
Use:
Holds the address of the subroutine which handles machine language "BRiC" requests (normally $FA.59).
Soft Entry Vector. These two locations contain the address. of the reentry point for whatever language is in use. Normally contains $E003.
Powerup byte. Normally contains $45.
Holds a "JuMP" instruction to the subroutine which handles Applesoft J[ "&" commands. Normally $4C $58 $7F.
Holds a "JuMP" instruction to the subroutine which handles "USER" (CONTROL Y) commands.
10.7
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Built-In I/O Locatons
$0
$1
$2
$3
$4
$5
$6
$1
$C000 Keyboard Port A Input
$C008
scolo
Keyboard Port B Input Clear Keyboard Strobe
$CO20 Deselect all expansion 1/O space (pin 39) for Apple /1/ cards
$CO30 Speaker Toggle (lus) pulse
$C040 Speaker Beep (1 KBz for 0.1 second)
$CO50
gr
tx
nomix I mix i pri
sec
lores hires
I
$CO58 $C060
I
I
I
I
I
I
I
i
i
IA/DOIA/DOJA/D2IA/D2IA/DCHGIA/DSTJA/p1IA/Dhi
I
swo
I
¡
I
I____l___l
I
I
i SW i
I Sw 2
SW 3
I
j IRQ 2
I IRQ i I AID TMI MUX1
I
$C070 Clock millisecond output"($NO)
$C090-$CO9F
Slot 1 Device Select (pin 41) goes low during C1M
$COAO-$COAF
Slot 2 Device Select (pin 41) goes low during C1M
$COBO-$COBF
Slot 3 Device Select (pin 41) goes low during C1M
$COCO-$COCP
Slot 4 DevIce Select (pin 41) goes low during C1M
$COEO Disk Stepper Motor Phase A
$COEI Disk Stepper Motor Phase A
$COE2 Disk Stepper Motor Phase B
$COE3 Disk Stepper Motor Phase B
$COE4 Disk Stepper Motor Phase C
$COE5 Disk Stepper Motor Phase C
$COE6 Disk Stepper Motor Phase D
$COE7 Disk Stepper Motor Phase D
lAR
/
Apple Computer Inc · 1982
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CO8 Disk motor off
$CDE9 Disk motor on
$COEA Select DrivI (Built-in)
$COEB Select Drive 2 (First extertal)
$COEC Q6L
$COED Q6R
$COE Q7T..
$COEI Q7E
$COFO ACIA Receive/Transmit Data register
$COFI ACtA, Status register
$COF2 ACtA Command register
$COF3 ACtA Control register
$C100-$CIFF
Slot i I/O Select (Pin 1) goes low during CIM low
$C200-$C2FP
Slot 2 I/O Select (Pin 1) goes low during dM low
$C300-$C3FP
Slot 3 I/O Select (Pin 1) goes low during dM low
$C400-$C4FP
Slot 4 I/o Select Pin 1) goes low during Cfl1 low
10.9
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I
PERIPHERAL BOARD I/O
The Apple /1/ implements only slots i through 4. Slot 6 is
always a disk interface card and slots 5 and 7 emulate either a SERIAL or COMMUNICATIONS card. Slot O scratchpad RAM exists but no provision is made to put a LANGUAGE card or FIRMWARE card into the system. Thus the RAM is limited to 48K with a 12K ROM chosen at Boot time.
PERIPHERAL CARD I/O SPACE
Slot 6 device I/O space $COEO-$COEF contains the hardware for the disk interface. Slot 7 device I/o space $COFO-$COF3 contains the addresses for the onboard AdA.
PERIPHERAL CARD ROM SPACE
Slot 5 and slot 7 contain code which is functionally equivalent to the COMMUNICATIONS or SERIAL card for the Apple ](. They differ in that they use the built-in AdA. For a more complete explanation see "SERIAL AND COMMUNICATOÑS CARD EMULATION ,,
Slot 6 contains a copy of the Apple ]( 16 sector Boot PROM.
10.10
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ROM MEMORY
The Applesof t, Integer Basic, and Autostart Monitor "ROMS" are
/1/. actually write protected RAMa in the Apple
When the Emulation
mode disk is booted it loads RAN memory with an image of each set of
ROMs. Whichever language is selected when the Apple JE disk is booted is loaded into the address space ($D000-$FFFY) and write
pro tee ted.
RAM MEMORY
In Emulation mode there is always 48K of RAN. It is addressed $0000 to $BFFF. There is no. proviion for a slot O Language or Firmware card.
"USER 1" JUMPER
I/f. There is no "User 1" jumper in the Apple
THE CAME I/O CONNECTOR
/1/. There is no 16 pin Game I/O connector in the Apple
Rowever
there are two 9 pin "D" - joystick connectors.
THE JOYSTICK PORTS
/1/ The Apple
has to joystick ports (A and B). The A port will
NOT operate a silentype printer in Emulation mode. The physical
pinout is:
54321
9876
10.11
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appkzcompm
PORT A PINOIJT
Pin
Naine
i
SGND
2
+5V
3
GND
4
XO
5
SWI
6
+12V
7
GND
8
YO
9
SW3
Description Shield ground. +5 volt power supply. Power and Signal Ground. Horizontal analog input, PDL (0) in BASIC. Joystick switch 1, orange button. +12 volt power supply. Power and signal Ground. Vertical analog input, PDL (2) in BASIC. Joystick switch 3.
PORT B PINOUT
Pin
Nmae
i
SGND
2
+5v
3
CND
4
Xi
5
SW2
6
+12v
7
CND
B
'Ti
9
SWO
Description Shield Ground. +5 volt power supply. Power and Signal ground. Horizontal analog input, PDL (1) in BASIC. Joystick switch 2, orange button. +12 volt power supply. Power and signal ground. Vertical analog input, PDL (3) in BASIC. Joystick switch zero.
10.12
/
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THE KEYBOARD The keyboard is different in design but the locations of the
Keyboard Data Input and the Clear Keyboard Strobe are the saine. For more information see "THE KEYBOARD" in c1apter 1.
CASSETTE INTERFACE JACKS
I/I. There are no cassette interface jacki in the Apple
POWER CONNECTOR
The power connector is different but is not user accessible.
SPEAKER
The speaker is identical to the Apple J[.
PERIPHERAL CONNECTORS
The Apple ]( emulation redefines a few of the pins on the connector and adds several new ones.
The most significant difference is that interrupts will not be sent to the 6502 from the slots. In fact the IRQ (pin 30) is an input to the cpu so the card can't even determine if an interrupt is occuring. Thus Emulation mode runs without interrupts, period.
The RES (pin 31) is an output to the card and goes low when the RESET key is pressed on the keyboard. However the microprocessor is actually performing an NKL not a RESET.
10.13
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Peripheral Connector Pinout
CND
26
25
+5v
DMAOK
27
24
NOT USED
DMAI IONMI
28
23
NOT USED
29
22
TSADE (Open collector)
30
21
RDT (Open collector)
lORES
-mg -12V
-5v
31
20
I/o STROEE
32
19
PHO
33
18
R/'
34
17
AlS
SYNC
35
16
A14
C7M
36
15
A13
Q3
37
14
Al2
ii
38
13
All
LOCLR. C114
39
12
AlO
40
11
A9
DEV SEL
41
10
M
D7
42
9
Al
D6
43
8
M
D5
44
7
AS
D4
45
6
A4
D3
46
5
A3
D2
47
4
A2
Dl
48
3
Al
no
49
2
AO
+12v
50
1
¡/0 SELECT
10.14
Apple Computer Inc · 1982
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Peripheral Connector Signal Description
Pin:
Name: i/O SELECT
2-17
AU-AlS
18
R/
19
PRO
20
líO STROB!
21
RD!
22
TSADB
23
24
25
+5V
26
GND
27
DMA0F
Description:
This line, normally high, w-iii become low when the microprocessor references page $Cn, where n is the individual slot number. This signal become active during PRO (nominally 500ns) and will drive 12 LSTTL loads.
The buffered address bus. The address on these lines becomes valid within 300ns after the beginning of
dM and remains valid through PRO. These lines will each drive 8 LSTTL loads.
Buffered Read/Write signal. This becomes valid at the same time the address bus does, and goes high during a read cycle and low during a write. This line can drive up to 10 LSTTL loads.
A i MHz signal which is identical to dM. This line will drive 5 LSTTL inputs.
This line will go low during C1M when the address bus contains an address between $C000 and $CFFF. This line will drive 12 LSTTLI loads.
The 6502's RDY input. This line should change only during dM, and when low will halt the microprocessor on the next read cycle. This line has a 1K ohm p'ullup to +5V. This line should be driven from an open collector output.
A low on this line from the peripheral will cause the address bus to tn-state for Direct Memory Access (DMA) applications. This has a 1 K ohm resistor pullup to +5V. This should be driven from an open collector output.
Not used in an Apple /1/.
Not used in an Apple /11.
Positive 5-volt supply, 2.0 amps total for all peripheral boards together (but note a limit of 1.5 Watts per board).
System circuit ground. O volt line from power supply. Do not use for shield ground.
Acknowledge signal to the peripheral following 10.15
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28
DAt
29
IONMI
its request for the special Direct Memory Access (DMA) mode. Informs the peripheral that the DMA can now proceed.
Direct Memory Access (DMA) interrupt. Requests the A
Apple /1/ DMA mode. Has a i K ohm pullup to +5.
This should be driven from an open collector output.
Input/Output Non-Maskable Interrupt. This is equivalent to the tORES (pin 31) line as it will
execute the same code in the Autostart ROM. This
line should be driven by an open collector output.
30
IR
This line is ignored in Apple ]( emulation mode. It should be driven by a T'IL output.
31
LORES
Input/Output Reset signal used to reset the peripheral devices. Pulled low by a power on or RESET key. This line will drive 12 LSTTLI loads.
32
Inhibit line. When a device pulls this line low, all
system memory is disabled. This line has a I K ohm
pullup resistor to +5V and should be driven form an
open collector output.
33
-12v
!Tegative 12 volt supply, 200mA total for all peripheral boards together.
34
-5V
Negative 5 volt supply, 200mA total for all periperal boards together.
35
SYNC
36
C7M
The 6502 opcode synchronization signal. Can be used for external bus control signals. Will drive 10 LSTTL loads.
Seven MHz high frequency clock. Will drive 10 LSTTLI loads.
37
Q3
A 2MHz (nonsymetrical) general purpose timing signal. Will drive 10 LSTTL inputs.
38
CIM
Complement of CIM clock. This will drive 12 LSTTL loads.
39
IOCL&
Provides the $C800 space disable function directly without address decoding ($CFFF is used for Apple ][ peripherals. It is addressed from $CO2x. This line will drive 12 LSTTL loads.
40
CIM
Phase C1M clock. This Is the same as the microprocessor's 1 MHz clock. This will drive 12
LST'IL loads.
41
DEVICE SELECT This line becomes acive (low) on each peripheral
10.16
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
42-49 D7-DO
50
+12v
connector when the address bus is holding address between $COnO and $COnF where n is the slot number plus $8. This line will drive 12 LSTTL. loads.
The 8-bit system data bus. During a write cycle, data is set up by the 6502 less than 300ns after
the beginning of C[M. During a read cycle the 6502 expects data to be ready no less than lOOns
before the end of dM. These lines will drive 8 LSTTL inputs.
Positive 12 volt supply, 300A total for all peripheral boards together.
10.17
Apple Computer Inc · 1982
Page 0189 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
ppcompLtm
ROM LIWrINGS APPLE ] [ EMULATION MODE AUTOSTART ROM LISTING
The following is a listing of addresses which changed content in
the Autostart ROM to eliminate cassette I/O, read joysticks1 and the NMI vector to the RESET code.
redirect
I
b
,
THIIEFNHAIICTBtIADTOEBISISTTCHTAEOPAIPBNRLTEEEVREORNFUTPGTTEHNEREERSCAEETRIIVVNIEGCRIINSNGETTEOSRFRTUTHPHETISSPRIONICNETESEMSRUORLURApTTIIONNTERMORDUEP.T
FA49: 4C 10 FP
68 09 04 48 A5 45 FF16: 40
JMP IHBI'RQS
PtA ORA $34
PEA,
LDA $45 RTI
;JMP TO CODE TO INMIBIT INTERRUPTS
;GET PROCESSOR STATUS BYTE ;SET INTERRUPT INHIBIT BIT ;PUT STATUS BYTE BACK ON STACK ;RESTORE ACCUMULATOR ;RETIJRN WITH INThRRIJpTS [NHIBITTED
THE RESET KEY IN EMULATION MODE GENERATES AN NMI (NONMASKASLE
b b
INTERRUPT). RESET CODE
THEREFORE THE WHICH ALSO MAIOES
NMI VECTOR IS SET TO SURE THE DISK MOTOR
POINT STOPS
AI
THE
FFFA: 62 FA
08
Al) EE CX)
FA66: AD EC ) FA69: AD E8 CO FA6C: 20 84 FE FA6F: 20 2F YB FA72: 20 93 FE FA75: 20 89 FE
EA EA FA7A EA
RESET
DFB
CLI)
LOA LOA
LOA JSR JSR JSR, JSR NOP NOP NOP
RESET ;POINT NMI VECTOR TO RESET CODE
;BINARY ARITHMATIC PLEASE $COEE ;SET DISK READ $COEC $COE8 ;TURN OFF DISK SETNORM INIT SETVID SETKBD
;
THE CASSETTE READ ROUTINH SIMPLY RETURNS TO USER CALLS
10.18
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
FEFD: 60
READ RTS
FEFE-FFOA: EA
NOP
FF08: 22
FFOC-FFOF: 00
BR
FFI7-FF2C: 00
BRX
¡NO CASSETTE PORT - RETURN TO USER ;FILL CODE WITh NOPS ; STOP USER FROM JUMPING fl'TO MIDDLE OF CODE
a
THE CASSETTE WRITE ROUTINE SIMPLY RETURNS TO USER CALLS
FECD: 60
FECE-FEF2: EA FEF3-FEF5: 00
RTS
;N0 CASSETTE PORT - RETURN W USER
NOP
;FILL CODE WITH NOPS
BRX
¡STOP USER JUMPING INTO CODE
;
READ JOYSTICK AXIS. THIS IS THE SAME ENTRY ADDRESS .OF PREAD
;
WHICH READS THE GAllE PADDLES IN THE APPLE ] (
p
X REGISTER CONTAINS JOYSTICK AXIS AND Y RETURNS $OO-$FF OP JOYSTICK
a
;
X REGISTER
JOYSTICK AXIS
p
;
O
PORTA,XAXIS
i
PORTB,ZAXIS
2
PORTA,YAXIS
3
PORTB,YAXIS
FBIE: BA FBi?: 48
FB2O: 49 01,
FB22: AA F323: AD 59 CO F326: AD 5E Q) F329: AD 5k CX) FB2C: 4C C9 PC
PREAD
TEA PEA EOR S$Oi TAX LDA $CO59 LDA $CO5E
LDA $CO5A. JMP JOY2
;SAVE X REGISTER ;R.EMAP JOYSTICK ADDRESS ¡SET ANALOG MIJX TO PORT 3, X AXIS
FCC9: E8 FCCA: CA FCCB: 70 12 FCCD: AD 5F Q) FCDO: CA FCD1: FO OC FCD3: AD 58 CO
CA FO 06 FCD9: AD 5E 0)
JOY2
INE DEX BEQ JOY3 LDA $CO51 DEX BEQ JOY3 LDA $CO58 DEZ BEQ J0Y3 LDA $CO5E
10.19
;SET FLAGS ;PORT 8, X AXIS? ¡NO
;PORT A, X AXIS? ¡NO
;PORT B, Y AXIS? ;N0
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
FCDC: AD SB CO
FCDF: AD SC ) JOY3
FCE2: A9 OF
FCE4: 20 AB FC FC!7: AO 80
FCE9: AD SD CO
FCEC: A2 48
FCEE: CA FCEF: lo FD
JOY4
E8
JOY5
B9 E6 BF 2A
AD 66 CO
FCF9: 30 F6 FCFB: 8A
FCFC: lo 04 FCFE: A9 FF
FDOO: DO 01
FDO2: 2A F003: Aß
JOY6
FDO4: 68
AA
60
FDO7-FDOB: 00
LOA $CO5B LDA $CO5C LDA #$OF JSR WALT LDY #$80 LOA $CO5D LOX #$48 DEX BPL J0Y4 INI LOA $BFE6,T ROL LOA $C066
B4t J0Y5
TXA
BPL JOY6 LOA #$FF BN! JO'i7 ROL TAT PIA TAX RIS
BRX
;MUST BE PORT A, Y AXIS ;CHARGE CAPACITOR ;WAIT 800US
;START TIMEOUT ;WAIT 370US
;FALSE READ
;BIT 7 [S VOLTAGE CROSSOVER ;HAS VOLTAGE CROSSED OVER? ;YES
;WAS COUNT POSITIVE?
;NO ;USE $FP ;DOUBLE COUNT ;R.ETURN COUNT IN Y ;RESTOR.E X
;PILL SPACE
10.20
Apple Computer Inc · 1982
Page 0192 of 0730
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i Apple /// Computer Information · Apple /// Level 2 Service Reference Manual Apple /// Computer Information Apple ///
Service Reference Manual
Section I of II . Theory of Operation Chapter ii Schematic Diagrams
Written by Apple Computer. 1982
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple Computer Inc · 1982
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I.
- 7311.
-r
2.
ALL UNITS UNDER lEST ).OLEx PINS 705E ICCATED TOGET.
5. () = AL1 Ti,.il MOLEX Ptws TO ES LOCA-rED TOGETHE;.
'ATHIS SCHEMATIC EPRE5ENT5 ÀSSV 6IO-CIo AT JEV LEVEL*F.
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ENGINEERING RELEAS Thi, feytsion supeed.s all previc» s versions.
Please destroy ail old copies.
NOTICE OF PROPRIETARY PR*ERTY
Th. lniQçmatlon Contained hen in Is ihe
proprietary property of Apple Cort puto,, Inc.
The possessor agrees to the follov nq;
-
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MAIN IOG4C *2
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i.:i ¿i :ui; L.. la ;.;, ;L;.1
Page 0194 of 0730
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
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Page 0196 of 0730
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Apple Computer Inc · 1982
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Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
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Apple I/I Computer Schematics
Source Apple Service Level II Technical Reference
# 204-1022 Volume II
SCHEMATIC LIST
Disk Analog Disk Analog Main Memory Board Main Logic # 2 Parallel Printer Card 5V Memory Board ProFile Analog Board ProFile Controller Board ProFile Apple I/I Interface Card
050-0031-00 050-0031-C 050-0032-E 050-0039-H 050-0042-A 050-0044-B 050-5005-B 050-5006-A 050-5007-A
05/ 1980
04/1981
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Apple Computer Inc · 1982
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Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
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Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
I
Apple /// Computer Information
Apple ///.
Service Reference Manual
Section I of Il . Theory of Operation Chapter 12 . Floppy Disk Subsystem
Written by Apple Computer. 1982
Apple Computer Inc · 1982
Page 0251 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
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I/I THE DISK
SUBSYSTEM
I THEORY OF OPERATION
I/i The Disk /1/ subsystem, is a self contained Apple
peripheral which allows
user programs and data to be stored and retrieved on 5 1/4" floppy diskettes.
I/I The Apple /1/ supplies DC power, control signals, and a parallel data path to
the Disk
via the A///s main logic board Disk Conditioner (Controller)
Circuit. The Disk Conditioner sends DC power, control signals, and serial
data to the Analog Card via a 26conductor ribbon cablé.
The Analog Card contains disk read-write electronics, drivers for positioning Stepper Motor, and a transistor power switch. Analog Card also contains circuitry which causes its output signals to the disk conditioner circuit to be active only when the card is enabled. This allows up to 4 Analog Cards to share the same data path for a 4 drive system (one internal, three external drives).
Within the drive itself, movement of Stepper Motor rotates Actuator Cam. Head and Carriage Assembly's Cam Follower, rides in Actuator Cam's spiral groove. Two Guide Rods allow motion of Head and Carriage Assembly either towards, or away from Drive Door. This positions Read/Write Head to appropriate track, so that serial data nay then be transferred to and from disk using highlevel commands.
A - DISK CONDITIONER CIRCUIT
There are seven sections in the Disk Conditioner circuit: (Refer to Schematic of Disk Condit toner Logic)
PowerOn Reset
This circuit consists of one half of 556 Timer and one opencollector inverter. When power is applied, the outputs of the 9334/LS259 Address Latch (DPhO-3) are brought low which places the Disk Conditioning logic in the read mode, the Q output of the 556 timer (pin 5) goes high for about 65 mo, bringing inverter's output to ground. This resets the State Machine (Prom P6A), and the Drive Enable Multiplexers. The drive enable moltiplexer'. Z output is prevented from enabling the internal and external drives.
The BOOT ROM
The Boot ROM, though not a part of the disk conditioning circuit, contains the routine which down loads the operating system (SOS) from disk and then jumps into it. The LS323, an 8 Bit Parallel/Serial Register, is enabled (DEVSEL61) whenever the address COExxn is presented. the data, from the boot ron, is converted to serial at the output of pin 1 in the 74LS323 in a write operation.
Addressable Latch (9334 or 74LS259).
12.].
Apple Computer Inc · 1982
Page 0252 of 0730
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Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
ucarnpt*
This chip provides an eight software-controlled output. When DEVSEL6* (pie 9 of LS138 I/O Address Decoder) signal goes low (one of 16 addresses starting at [COExxnt, value of Address Line AO becomes the new value of D output pointed to by Address Lines Al-k3. Latch output D6 and D7 set operating mode of controller (read, write, etc). Q5 selects the internal drive. D4 controle MOTOR ON signal and DO to D3, set position of the Stepper Motor. Drive enable signala ENBL1I and ENBLIE are true when MOTOR ON signal is true and appropriate drive is selected.
State Machine (PROM P6A and 74LS174)
These two parta contain nucleus of Disk Conditioning Logic. A State Machine is a device capable of storing a value in a register. That value, in conjunction with external input, determines what the next register value should be and what oùtput should be generated. Value in register is, machines's Current State and next value is machine's Next State. State machine updates at each clocking, going from state to state and producing output base on state its in and value of its input just before clocking.
Current State, is value at Q2, Q5, Qi, and QO from 74LS174. Next state is value of D4-D7 from P6A PROM. Input to State Machine includes D6 and D7 from 9334, QA* output from 74LS174 Shift Register and A2-11. Output from State Machine is PROM signals DO-D3, which effect Shift Register. QO from 74LS174, which is high-order bit of Current State, forma WR DATA output. Since State Machine is clocked by two Megahertz Q3* signal, the state lasts for 500 ns.
Flux transitions on diskette are detected by Analog Card and are sent to Disk Conditioning Circuitry as RD DATA. These one microsecond positive going pulses appear at D4 input to 74LS174. NAND Gate and Inverter, which connect to 74LS174's Q3 and Q4 output, cause A4 input to P6k PROM to go low for one state following the falling edge of RD DATA. This information is ignored when writing out to disk. When reading from disk, however, this input forms the basta for determining whether a logic one or zero baa been read. A logic one is indicated by a four microsecond period. A logic zero, by an eight microsecond period between flux transitions.
Shift Register
74LS323 Universal 8 Bit Parallel/Serial Shift Register, transfers data
to and from the Apple /1/. When writing to disk, Shift Register under
control of State Machine, parallel loads a data byte from the A//I and shifts it left. This causes QA* output to effect State Machine's Al input. State Machine goes through a different state sequence for a logic one and a logic zero, which causes WR DATA to change value every four and eight microseconde, respectively.
When reading from disk, State Machine shifts appropriate logic levels into Shift Register's SL input. Resulting byte can be read by the A///.
Status of Write Protect switch in Disk Drive, comes into SR input of
12.3
Apple Computer Inc · 1982
Page 0254 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Shift Register from Analog Card. Under control of State Machine, Shift Register is placed into a shift right mode, allowing status of switch to be read by software.
MOTOR ON Circuit.
Q output from one half of 556 timer, forms MOTOR ON signal. MOTOR ON becomes true when B2-6 is brought to ground under software control. An enable is sent to one of the drives, and Drive Motor in selectd drive turns on. When software causes B2-6 to become high-impedance in order to turn off drive, Cl and R31 give drive a 2/3 second grace period before
MOTOR ON times out. This prevents drive from being turned on and off
when repeated accesses are made.
AlI EMUlATION MODE
With the AIISW* true and DEVSEL5* (addressed by CODxxn) selected, the internal and external drives are fooled into operating as an Apple II Disk Drive.
B - ANALOG CARD (Refer to Analog Card Schematic Diagram)
1. Enable Circuit
I/I A Disk Drive connected to the Apple
is always in one of three
operating modes:
a - Read Mode
Flux transitions on diskette are detected by MC3470P Floppy Disk Read Amplifier on Analog Card and are sent to the Disk Conditioner as one microsecond positive-going pulses across RD DATA* line.
Write Mode
Here WR DATA input to Analog Card determines polarity of write current passing through head.
Deselected Mode
In this state, drive is not currently performing any data transfers
with the Apple /1/.
A drived becomes enabled, when ENBL1I input to the Analog Card on
the selected drive goes low. This causes Ql to turn on because
current flows through R3 into pin 16 of tJLN2003's Darlington output. +12 volts is then supplied to Stepper Motor. Ql also provides a power source for Write and Erase Current circuits. In addition, ENBL1I signal also enable RD DATA* and W PROT tristate buffers and supplies a MTR ON control signal to Motor Control
Board through resistor R9.
12.4
Apple Computer Inc · 1982
Page 0255 of 0730
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Apple Computer Inc · 1982
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NOTICE OF PROPRI TARY PROPERTY
The information conuined herein Is the
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
d. Read Electronics
MC3470P Floppy Disk Read Amplifier and associated discrete components provide a one-chip interface between magnetic head of Disk Drive and RD DATA* input to Disk Conditioning circuit of the main logic board. HC3470P contains both analog and digital circuits which cause a TTL compatible pulse to be generated for each positive and negative peak of input signal.
Input voltage from head appears across pins 1 and 2 of MC3470P. ThiB signal passes through an amplifier and is differentially applied to a noise filter made up of R2l and R22, ClO and Cil and L3 and L4. Filter's output feeds back into MC3470P, where a differentiator circuit provides an output proportional to rate of change, with time, of input signal. In addition, a 90 degree phase lead is introduced which causes a zero crossing at differentiator's output to correspond with a peak at its input. L5, C13 and R23 determine characteristics of differentiator. R27 allows for correction of current imbalances within differentiator so that a sinusoidal input waveform produces evenly spaced RD DATA* pulses.
Zero crossings at output of differentiator cause output of a comparator within MC3470P, in conjunction with digital circuits, create a Time Domain Filter which checks against false zero crossing readings due to diatored input waveforms or noise. When a zero crossing is detected, mono #1, formed by R20, R32, and C7, is triggered. At end of its two microsecond period, output of comparitor is again checked. If it has not changed (valid zero crossing), mono #2 gets a trigger pulse that uses R19 and C8 to generate one microsecond RD DATA* pulse at pin 10 of MC34709P.
3. Write Electronics
During Read Mode (WR REQ* high), ULN2003 Darlington output at C4-l0, is close to ground potential. This prevents erase current switch Q2 from turning on and disables write current return path. During Write Mode, the anode of cR3 is pulled up to +5.7 V. Q2 receives base current through A.3-8, and provides current to erase coil of head. Rh serves as return for erase current, which is roughly 44 milliampa. Erase coil in head straddles both sides of readwrite head, preventing write current from spreading into adjacent tracks on diskette.
When writing out to diskette, flux tranaistions are placed on surface of diskette by changing polarity of current flow in head's readwrite coil. Write current enters read-write coil through its center tap, which is connected to return side of erase coil. Two of CA3146'g transistors connected to P.29 and P.30 form a current mirror which drives pin three of CA3146.
This establishes write current return path. When writing out to disk, WR DATA causes a differential voltage to be applied to pins 2 and 4 of CA3146, which causes a differential current flow in write coil. Each polarity reversal places a flux reversal on
12.6
Apple Computer Inc · 1982
Page 0257 of 0730
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- Apple /// Computer Information · Apple /// Level 2 Service Reference Manual diskette. (Current in R/W coil -6.8 ma P-P)
4. Write Protect Circuit
Ananlog Card only allows erase and write current to be generated when diskette has its write protect notch uncovered. If notch is absent (write protected), the Write Protech switch is held open even though diskette i. fully inserted into drive. This causes pullup resistor R12 to disable Cl-8, which causes WR REQ* signal to be pulled up to a false level by R15. This prevents write current mirror from supplying write current to head. Write Protect status is cnt to Disk Conditioning circuitry on Main Logic board as W PROT.
If Write Protect notch has been uncovered, Lt cause Write Protect switch within drive to close. Phase 1 signal frost the Disk Conditioning circuitry provides return path for current passing through switch. If Phase i signal i high, it indicates that Stepper Motor is in one of its two transient states between tracks. Write Protect circuits behave ma they do when the diskette is write protected. This provides partial coverage against writing when Stepper Motor is off track.
5. Stepper Motor Drivers
A ULN2003 Darlington Buffet-Inverter, provides a current return path for each of four Steper Motor winding., Phase A through Phase D. Ql. provides winding. with source current when dirve is enabled. Since input to each ULN2003 stage is provided by the Disk Conditioning circuit's 9334 Addressalbe Latch output, Stepper Motor is then under sof tware control.
Stepping in from Track O towards Track 34 (towards hub), requires Stepper Winding. to be energized in Phase A, B, C, D order. Each phase rotates Cast Follower enough to provide one-half track imvement of Read and Carriage assembly. Phase Ad and C are energized when head is on track, and Phase B and D are between track positions. Once head is positioned to desired track, power is removed from Stepper Motor to reduce power consumption.
Stepping out requires Stepper Motor winding. to be enegized in Phase D, C, B, A order. When booting, windings are pulsed enough times to guarantee that head is positioned over Track O.
12.7
Apple Computer Inc · 1982
Page 0258 of 0730
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Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
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12.9
Apple Computer Inc · 1982
Page 0260 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
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Apple Computer Inc · 1982
Page 0261 of 0730
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i Apple /// Computer Information · Apple /// Level 2 Service Reference Manual Apple /// Computer Information Apple ///
Service Reference Manual
Section lI of Il . Servicing Information
Chapter 13 Testing and Troubleshooting
Written by Apple Computer 1982
Apple Computer Inc · 1982
Page 0262 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Purpose;
I/I Title: Apple
Final Test
I/I This test is for the assembled Apple
I/I modules.
and for testing Apple
A. Equipment:
B/W Monitor with cable
Color Monitor, Sup'r'mod II, and adaptor (make your own adaptor)
(3 cables) External Disk. Paddle Port, External Speaker Cables
External Speaker Test Box
RS-232 Test Adaptor
Printer test card
I/I (4 each) Interrupt test cards
Apple
Test Diskette (889-0009 rev R)
B. Equipment Setup for Part I of test: (Note: Unless noted otherwise,
I/I.) ALWAYS make sure that the power is 0FF, before connecting or
disconnecting ANYTHING from the Apple
1. Connect all of the power cords to a suitable AC outlet. Note: Make sure that all power switches are in the 0FF position before plugging in any equipment.
2. Connect the B/W monitor cable to the RCA video output jack.
3. Connect the Color Monitor/Sup'r'mod II to the DB-15 jack.
4. Connect the joystick as follows: Connect the paddle port cable connector to the external disk drive socket. Connect the 2 DB-9 plug to the 2 DB-9 sockets. (The one with the shortest cable connects to the socket nearest the external drive connector, Port A. The other connects to Port B.
5. Plug one Interrupt test card into each of the four slots on
the Apple /1/ logic board.
6. Plug the RS-232 Test Adaptor into the DB-25 connector on the logic board. (P/N 890-0130)
III 7. Insert the Apple
Test Diskette into the drive and close the
drive door.
C. Test Procedure: (for part i of the test.) Follow the test procedure described in this section. The test should run as described. If there is a failure, some of the tests will automatically proceed to the next test, while others will require the operator to press certain keys, to tell the system what has failed. Proceed through all of the tests. If the system will not proceed through all of the tests, indicate on the RRT which test failed. Reject and repair any unit which does not perform as described in this procedure.
13.1
Apple Computer Inc · 1982
Page 0263 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
*TEST DISKETTES HAVE BEEN KNOWN TO CRASH - KEEP AN EXTRA COPY ON HAND
Power On. Turn the power supply switch on. The unit will perform a self test first. If the self test passes, the disk will boot. If there is a failure in the self test, or the disk drive does not boot, record the failure on the RRT and send the logic board for rework. (ALWAYS TURN THE POWER OFF BEFORE DISCONNECTING ANYThING FROM THE LOGIC BOARD.) When the disk drive boots, you will hear an audio signal of three beeps, followed by two beeps. You will then see a menu. Press the i key on the keyboard to run Automatic Test 1.
Interrupt test. The interrupt test will run automatically. If you see any of the following error messages, attempt to repair the A3 system and re-run the test.. Write the failure down on the RRT.
ERROR MESSAGE unable to set or clear D.xxx unable to set or clear E.xxx (anything) from SLOT X
SUGGESTED ACTION TO TAKE 6522 at H-10 (U 73) * 6522 at G-10 (U 97) * check slot for bad connector
* locations will be as follows for the "NEW" logic board:
D xxx E xxx
6522 at B-6 6522 at B-4
3. Video Test. The video tests will be loaded and run next. At the beginning of each test the screen will briefly display the name of the test being performed next and which keys to press, depending on the results. For reference, the following table lists the keys used for all of the video tests:
Space bar
Return key
Escape key
Left arrow key
Test passes Test fails Abort video test (QUIT) Retry the test
Except for the text mode test, each of the tests will display the same pattern. A picture of Winston Churchill will appear in the upper right corner. The lower half of the screen will display the following message:
If you can read this, and the test patterns above are clear, press space bar. Otherwise, press return.
HIRES MODE PAGE 1 - B & W pattern HIRES MODE PAGE 2 - B & W pattern (same as above) 280 x 192 COLOR HIRES MODE PAGE i - Will appear as a negative image. The color monitor will show red and black.
13.2
Apple Computer Inc · 1982
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- u
280 x 192 COLOR HIRES MODE PAGE 2 will appear as a green and white (or possibly green and yellow) pattern. SUPER HIRES MODE PAGE 1 - B & W pattern (same as above) SUPER HIRES MODE PAGE 2 - B & W pattern (same as above) AMIRES TEST PAGE 1 - On this and the following test the screen will be divided into 4 horizontal sections, each one being a different color. The top half of Winston Churchill and the diagonal pattern should be VIOLET. The bottom half of Winston Churchill and the diagonal pattern should be BLUE. The first two lines of the message should be GREEN, and the last two lines of the message should be GOLD or ORANGE. AMIRES TEST PAGE 2 - This test should display the same four color bars as the above test. COLOR BAR 7 GRAY SCALE TEST - will show vertical bars of different colors on the color monitor and bars of varying brightness on the B & W Monitor. The border is blue and the colors are : (from left to right) white, aqua, yellow, green, pink, grey, orange, brown, light blue, medium blue, grey, dark green, light purple, dark blue, magenta, and black. These colors correspond to white darkening to black on the Black & White monitor. (IMPORTANT. Make sure that there are sixteen (16) different shades on the Black & White monitor.) Apple II TEXT MODE PAGE 1 - The screen will display the following:
TRE QUICK BROWN PDX JIJMPS OVER LAZY DOGS
abcdefghijklmnopqurstuvwxyz 0123456789 (inverse)
(flashing)
APPLE II TEXT MODE PAGE 2 - The screen will show the following:
22222222222222222222 22222222222222222222 22222222222222222222
222 222 222 22222222222222222222 22222222222222222222 22222222222222222222 222 222 222 22222222222222222222
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Apple Computer Inc · 1982
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22222222222222222222 22222222222222222222
1. APPLE /1/ 40 COLUMN TEXT MODE TEST - The screen will be filled
with blocks of colors with the name of each color in each block.
m. APPLE ¡/1 80 COLUMN TEXT MODE TEST - The screen will contain
characters that are smaller than before. There will be 80 characters to a line. The characters may not appear clear on the color monitor, and this is OK. Lt is mainly important that they are clear on the B & W monitor. The first line of the display should read:
THIS LINE 0F TEXT IS EXACTLY 80 CHARACTERS LONG AND USES THE ENTIRE SCREEN WIDTH
4. Keyboard Test. This test will load and display a pattern on the screen.
a. Main Keyboard. Press the Left shift key and while holding it down press the 2 key. Press the Right shift key and while holding it down press the - key. Press the ctrl key and while holding it down press the A key. Press all of the remaining keys on the MAIN key board. Each time a key is pressed its character should disappear from the screen. Press the space bar last.
b. Numeric Keypad. A new pattern should appear on the screen which corresponds to the numeric keypad. This test should perform the same as the main keyboard test.
c. Special Function Keys. Press the Alpha-Lock key ONCE. It should lock into its new position. Press the space bar and hold it down. While still holding the space bar, press and hold both apple keys at the same time. Release all of the keys at the same time. Press the solid apple key and hold it down. While still holding down the solid apple key, press the space bar and hold it down. Release all of the keys at the same time.
d. Keyboard Interrupt test. Press any key on the keyboard except the alpha-lock, shift, control, or either of the apple keys to perform this test.
5. Clock/Calendar Test: This test is available for testing the clock/calendar when it becomes incorporated into the system.
6. Serial Port Test: This test will also load and run automatically. If it fails, replace the AdA chip (6551) and run the test again. If it still fails, write AdA on the RRT and repair the main
13.4
Apple Computer Inc · 1982
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r- - Apple /// Computer Information · Apple /// Level 2 Service Reference Manual logic board.
Joystick Port test: This test will run automatically. If any failures should occur, write the failure message on the RRT.
Test Results: The screen should show the following results:
TEST RESULTS
INTERRUPT VIDEO KEYBOARD CALENDAR/CLOCK ACtA PORT PADDLE PORTS RAM PRINTER PORT DISK SOUND ROM
(PASSED) (PAS SED) (PASSED) (NOT TESTED) (PAS SED) (PASSED) (NOT TESTED) (NOT TESTED) (NOT TESTED) (NOT TESTED) (NOT TESTED)
AUTOMATIC TEST i AUTOMATIC TEST 2 ESC ABORT TESTING
Tests A through F should always show passed, (except for test D) and tests G through K and test D should always show not tested. If any of tests A through F show failed, mark the RRT with the test that failed. If all of tests A through F show passed, proceed with part 2 of the Final test.
D. Equipment Setup for part 2 of test:
1. TURN THE POWER OFfl 2. Remove the following items from the logic board:
The joystick cables The four interrupt test cards. The RS-232 test adaptor. The DB-15 video connector 3. Plug the Printer Test Card into slot 1, and connect the printer cable to the DB-9 connector nearest the disk drive sockets and the other cable to the external disk drive socket. Connect the external speaker plug to the 2-pin connector on printer test card.
E. Test Procedure: (for part 2 of the test.) Please follow the test procedure described in this section. The test should run as described. Reject any assembly or unit which does not perf orn as described in this procedure. Complete all of the tests if possible. If the system will not perform any test, indicate on the RRT which test failed and diagnose, repair, and retest. 1. POWER ON. Turn the power on and the unit should perform
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Apple Computer Inc · 1982
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a self-test and boot just as it did earlier. If there is a failure in the self-test or the drive does not boot, record the failure on the RRT and repair. ALWAYS TURN ThE POWER OFF BEFORE DISCONNECTING ANYTHING FROM ThE LOGIC BOARD. After the disk boots, a menu will appear on the screen. Press the 2 key to run automatic test 2. Ram Address Test. This test will load and run automatically. The test results will depend on the amount of ram in the memory board. If the memory board is a 256K board the
results should say "R.AM MAP GOOD FOR A 256K SYSTEM". If the correct message appears, press the space bar, otherwise press the return key. Faulty RAN chips are reported in a message that identifies the board location of the chip in error.
Note: If a fault is discovered while testing the RAM on the 12 volt board, disregard the chip referred to in the error message and run the Final Test Revision 14. Revision 14 will correctly identify the chip in error. Revision R reports bad chip locations as defined on the 5 volt board and these messages are innaccurate for the older board.
If the space bar is pressed the system will perform a test on all of the ram in the system and report any failures. For this reason it is very important for you to have made the correct decision for the ram map address test above. If the system is a 256K system and the ran map says good for a 128K system and you press the space bar, only half of the ram will be tested and you may incorrectly PASS a system which FAILED.
Printer Port Test. This test will run automatically.
Disk Controller Test. This test will run automatically.
Sound Test.
CO30 SOUND TEST - The speaker will beep on and off.
C040 SOUND TEST - The speaker will beep on and off
as before but at a different pitch. Press the
space bar if you hear the sound, and return if
you do not.
e. Connect the external speaker cable from the printer
port test card to the external speaker jack on
the back of the Apple /1/ and press the return key.
FFEO SOUND TEST - The sound from the speaker
should start quietly and grow gradually louder.
It should then repeat. Press the space bar if it
performs as described here, and press the return
key if it does anything else. The sound should
be coming from the EXTERNAL speaker.
Disconnect the external speaker cable from the
logic board and press return. (NOTE: These are
I/I the ONLY times that you can connect or disconnect
anything from the Apple
with the power still
on, and the ONLY thing that can be connected or
13.6
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Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
disconnected is the external speaker cable.) The same sound as the previous test should be heard. The sound should come from the INTERNAL speaker again.
6. Rois Test. This test will load and run automatically. 7. Test Results: The screen should show the following
results
TEST RESULTS
INTERRUPT VIDEO KEYBOARD CALENDAR/CLOCK ACIA PORT PADDLE PORTS RAM PRINTER PORT DISK SOUND ROM
(NOT TESTED) (NOT TESTED) (NOT TESTED) (NOT TESTED) (NOT TESTED) (NOT TESTED) (PASSED) (PASSED) (PASSED) (PASSED) (PASSED)
AUTOMATIC TEST i AUTOMATIC TEST 2
ESC ABORT TESTING
Tests A through F should always show not tested) and tests G through K should always show passed. If any of the tests G through K show failed, record which test failed on the RRT and repair the module under test.
8. Additional keyboard tests: Press any key and hold it down. The key should automatically repeat. While still holding the same key down, press the Apple key nearest the space bar and the repeating key should repeat at a faster rate. (Approximately twice the speed) Press the right arrow key and the cursor dot should move to the right. Press the key harder and it should move twice as fast. Repeat the same test with the left arrow and down arrow keys. They should behave in the same manner described for the right arrow key except that they will of course move left and down, respectively. Press and hold the ctrl key with some finger on your left hand and then press and hold the
Apple Key next to the alpha lock with your left thumb. Use your other hand to press the Reset key. The system should respond with a right
13.7
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Apple Computer Inc · 1982
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pp-1 pointing arrow and a blinking line cursor. f. 1f any of these keyboard tests do not perform exactly as described here, record the failure on the reject tag, and send the unit for rework.
F. 1f the logic board passes all of the tests as described
above, turn the power off and complete the RRT. If
any of the tests failed, record the appropriate information on the RRT and repair. Retest after repair.
C. If you have a system or module that passes all these tests but suspect it to have a failure run other software on the unit/modules. Examples: Business
Basic, All Emulation, A /1/ Dealer Diagnostic.
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Apple Computer Inc · 1982
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L
16 SECTOR DISK III FINAL TEST (bOOT)
DESCRIPTION
1000T is a genera]. purpose internai, disk exercizer. It performs 1000 reads of ramdoinly selected tracks on the disk. It is to be used as a diagnostic tool and not as a qualification/acceptance test. The rest of this document provides a short description of how to interpret che displayed results.
When you first boot this diskette you will observe:
"*** 16 SECTOR DISK III FINAL TEST
This will indicate that the test booted up correctly with no problems. You will then observe the following:
TRACK ERRORS
3
(0) 0
*
19 (0)
0
4
(0) 0
*
20 (0)
0
5
(0) 0
*
21 (0)
0
6
(0) 0
*
22 (0)
0
7
(0) 0
*
23 (0)
0
8
(0) 0
*
24 (0)
0
9
(0) 0
*
25 (0)
0
10
(0) 0
*
26 (0)
0
11
(0) 0
*
27 (0)
0
12
(0) 0
*
28 (0)
0
13
(0) 0
*
29 (0)
Ø
14
(0) O
*
30 (0)
0
15
(0) 0
*
31 (0)
0
16
(0) 0
*
32 (0)
0
17
(0) 0
*
33 (0)
0
18
(0) 0
*
34 (0)
0
TOTAL: TIME:
SEEK: ADDR:
DATA: AVER:
WHAT DOES IT ALL MEAN?
The first column, numbered 3 to 18, and the column with numbers going from 19 to 34 represent track numbers. The column in brackets represents the number
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Apple Computer Inc · 1982
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e
of seek occuranceg that occur for each track. The column that has zera is tie number of errors that were encountered for each track. You will observe tha each time a track is read, it is shown in inverse, the number of occurances is incremented. If any seek, address, or data errors are found the number of errors are displayed.
A suary of the disk test is displayed at the very bottom of the monitor screen. The following are definitions as to what the messages mean.
o TOTAL: -- the tota]. number of errors for all tracks
o TIME: - the number of track seeks performed for all tracks
o SEEK: - the total. number of track seek errors observed for all tracks
o ADDR: - the total number of address errors observed for all tracks
o DATA: - the total number of data errors observed for all tracks
o AVGE: - the number of track seeks divided by the total number of errors observed for all tracks
NOTE: PLEASE MAKE BACKUP DISKETTES OF THIS I000T DISKETTE
WHAT CAN THIS TOOL TELL ME?
This tool is useful for getting a good idea as to the performance of the A//I internal disk drive. Based on the results, 1000T can give you an indication of electrical and mechanical problems. Examples: Errors within a small range of tracks could indicate cam or rail problems. Multiple data errors could indicate head wear. Address/seek errors could indicate a poor motor control board. These examples are not absolute nor do they exhaust all possibilities. This tool is also very useful for debugging interinittant disk problems.
WARNING: Do not rely solely on this diskette as a pass/fail indicator. If you find very many errors, run other Disk tests such as the DSPEED and Disk Alignment Aide.
Catastrophic errors are eask'y to find - your monitor screen will display "FAILS TEST". Other than catastrophic errors your monitor screen will display "PASSED TEST" at the end of 1000 passes(seeks).
HAPPY HUNTING!!!
'.J
13.10
Apple Computer Inc · 1982
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acomputaru
APPLE /1/
ESFI
The following flart is a guide for troubleshooting the Ple ¡/1. You
will carxy Cut various troubleshooting steps besed on s*.at that mey oecur
when first hooting Diagnostics. Start
or
with
that
the
mey be found by
instruction in
rxuninoinfg
tthheeDfleoaliearrStervTicheen
foll.ow the cçeration of the le /1/ through the floart tzti1 you reach
one of the lettered boxes (A through Q). Each lettered box has a list of
nuTbers in it; each runber rresponds with one of the troubleshooting steps
listed on the following pege. The order of the troublshooting steps in each
box is hased on o rules:
theck out the sore likely causes of the thle!n before the less likely causes.
ke the checks that can be ózne quickly and easily before those that take sore time and energy.
Rule i is broken only shen rule 2 applies.
C*ce you have ¡roduced the probln stçtan on the
I/I
the first thing you ould cb before trying any of the iurbered
steps below is:
Power OFF.
theck to meke sure all oetinecting cables are
properly 1-coked .
theck all boards to meke sure all IC chipe are properly seated.
Per again to see if the probln stili exists.
ALkYS YiJER
CARRY OEIl' 'IHE ER
ORE PERF4fl Y
SrEPS
.
IG.MD S'l'EP. '10 S
PBI4 }S
Each ap step listed below involves exchanging a krr.in god pert frOEn ir spares kit with the
questionable pert fr the le ¡/1. When aiaçing, yfiorustcjaunstsneeneifctththeeewcaabplefi(x8)estoththinegrs ornorodut.let'sto
fully install the new nodule and screw everything downif the new nodule &esn' t solve the prcbin
you'll just have to take it out again.
13.11
Apple Computer Inc · 1982
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HERE P1RE &rps REFERRED fl 'IHE BDXE W 'IHE DI?STIC FtD{ART:
1) 9.ap the appropriate oennecting cable. V - Video cable (if available)
PS = Per Supply cable DD - Disk ive cable KB Keyboard cable
(The keyboard ar disk drive
cables are identical to each
other Your Spares Kit nay
only list the W, bot
you can use it henever you
need to swap the KB cable.)
2) Swap the
r supply.
a) Qieck the er supp]y fuse first; swap it if it's borned lt.
3)
p the drive.
If the drive iroves to be the prcbletn, take the prcln
drive ar further isoloate the defective nodule
analog card or mechanical aaseTbly:
'n to the
Swap the analog card.
Swap the mechanical assexbly.
4)
p the mein logic board.
5) Swap the keyboard.
6) Swap the M mory board. (You nay have to reload tha r
board with the M fran the original board.)
7) Trybooting.
8) Try booting a different S boot diskette.
9) Swap the video nrxiitor (if you have a spare available).
10) Swap the speaker (if you have a spare available).
il) Swap (or
) the designated M IC chipe. (Oiisult the chip
nap in the Punning Diagretics J Aid.)
13.12
Apple Computer Inc · 1982
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Pov.r ON with
System Demo (SOS Diskette)
rror Messag On Screen (Internat
Diagnostics
ip VTA. ROM
ACtAM,soar eA/O
RAM trror Mesaqe or Continuous
RAM Test
-5
-4
- 1-OD
- i-Kh
-
: l-KB
-4
-6
-4
- lt
-6
-S
- l-KB
-b
- G-
-6
13.13
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Apple Computer Inc · 1982
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1'Succesiful
Boot
-18DOw.r On With Dealer Service
D iai7nos tics-
Run Tests
O
YKS
-ir -
Press Ctr 1-Reset For Warm Boot
l'i
It
VC S
-14
sos yuLuoi rai luit
n
MSsJe in
SC ree ii
V
-17-
Powei Ott.
OLIIOVO SysLom ucino Diskette
-5
- 1-KB
-
Problem Descrobed By
User AS Intermittent
NO
V
-28Apple ///
Is Fixed
NO
.5)
- 10 -4
NO
Run RAM lest
- 11
- 11.
-4 -6
-O-
-p-
- 1-Xii
- 1-DO
J 13.14
Apple Computer Inc · 1982
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A/// NO &,or cLOA.) J)f46,,f,I1
[ecw
11oc7rndt
,' / ' iti'l,4/Wvti4'L.
Y
A'1 Do7
Lt" -
'I
.'l#7(/X ai VfrL
fl4V'ìfS4' /'
r
L
4 MITO i'1At/i7v
I 3.'tze4 Th64/ &4iC
/ i 84 a A AsD fr pdet4i'7
R'AJ
7ES7ZS
,7:47'P4E; I
V 77 .?u4/
Hiwi 7Th
A4cW,7Oe
7E6r
,q,ss
HcAe'/s7Dr I
I
1,14siO,1Na,7etkte
L_
,'IO7A6'/ 7T
K(4 o-..
r
/j ZI3(
&W7C
13.15
Apple Computer Inc · 1982
Page 0277 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
I-
*PkZCOflWU
5V MEMORY. BOARD
RAM
TROUBLESHOOTING
PROCEDURE
AUG 1982
13.16
Apple Computer Inc · 1982
Page 0278 of 0730
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épcompL*
5V VOLT MEMORY BOARD RAM TROUBLESHOOTING PROCEDURE
To start with, be sure that your problem is caused by the 5v Memory Card. Some problems on the motherboard of the Apple
/1/ will, cause the symptoms similar to those caused by a bad
5v Memory Card. To check, replace the Memory Card with a known good one and check to see if the symptoms have disappeared.
If the problem has been isolated to the Memory Card,
I/f reconnect the bad 5V Memory Card in the Apple /1/
system under test and try to boot the Apple Confidence Diskette Version 1.1.
If it boots, select the memory test.
Relate your systems symptoms to the symptoms on the
Apple /1/ 5V Memory Card Troubleshooting Chart.
The corrective actions are listed in the order of most probable cause; therefore perform the corrective action in the order presented.
If all of the possiblities have been exhausted and the problem still exists, replace the bad SV Memory Card with a good one and send the bad one back to a Level II repair center.
Note: This interim RAM troubleshooting procedure is to be used with the Confidence Diskette Version 1.1. The memory test, in the current Confidence Diskette, does not test each and every memory location in RAM. This procedure will be superceded by the next version of the A/II Dealer Diagnostic.
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Apple Computer Inc · 1982
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¡II Apple
5V Memory Card Troubleshooting Chart
Symptom
Black Screen on Monitor; drive does not boot.
Monitor Screen contains garbage; Drive may try to boot.
Confidence Program loads into memory, displays menu, but will not run.
Memory test runs; displays RAM error message at the bottom of the screen.
Memory test runs; sections of the memory map are missing.
Recommened Action
Replace RAM chips 810 817 one at a time; Replace the non-RAN chips at locations D2 and E2.
Replace RAN chips 32 - B9 one at a time; Replace the non-RAN chips at locations D2 and E2.
Replace the non-RAM chips at locations D2 and E2; Replace RAN chips 82 B17 one at a time.
Decode the message using the procedure on Page 4. Replace the failed RAN.
Determine which section on the Memory Card contains the failed RAN using the procedure on page 8. Replace the RAN chips in that section one at a time; Replace non-RAM chips at locations D2 and E2.
13.18
Apple Computer Inc · 1982
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BANKS 3, 4, 5, 6
BANKS 0, 1, 2
LOW ADDRESS
(2oxx - 3FXX)
and
HIGH ADDRESS
(8oxx - 9FXX)
RANGES
T
1817161514131211109 8 7 6 5 4 3 2 1 I M_''4
A
MIDDLE ADDRESS (4OXX - 7FXX)
RANGE
E
B
c
D-
m
E
CC)
m
-L
Apple Computer Inc · 1982
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TRANSLATING ERROR MESSAS INTO PHYSICAL RAIl LOCATIONS
When you get an error message from the RAM test, you must translate it to determine which chip caused the failure. This procedure will show you how to do that. For example, suppose we get the error message:
BNK 83, ADR 20xx, EXP DF, T 5F
That means in Bank 83, Address Range 2OXX, ve expected DF but got 5F.
Now, how do you translate that into what to do?
To find out which row the failed RAM chip is in, disregard the 8, and look at the second number, in this case 3. If the second number is 0, 1, or 2, the bank is in row B. If the second number is 3, 4, 5, or 6, the bank is in row C. (See Figure 1). In our example, the bank was BNK 83, so ve know it is in row C. Now the meaning of the address. There are three address ranges, low, middle, and high. Low and high are in columns 2-9, and middle is in columns 10-17. Look at Figure 1 for the specific address ranges. In our example, the address was 2OXX (which is in the low address range), so we see that the trouble is in columns 2-9.
The problem is now narrowed down to a block of eight chips, the ones located in row C, columns 2 - 9 (positions C2 - C9). To find which of the eight it is, we have to decode the EXP and T parts of the message.
13.20
Apple Computer Inc · 1982
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e e
ttrir rirurrIrt IlI .IIII: liii
!II ri;rtïIï
I ih; .ibih.i,iLiI
o
w
FIGURE 2
1.21
Apple Computer Inc · 1982
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cc. r f
4) Translate the two hexadecimal digits from the EXP into binary.
HEX BINARY
i -O - 0000 0001
2 - 0010
3 - 0011
HEX BINARY
4 - 0100
5 - 0101
6 - 0110
7 - 0111
HEX BINARY HEX BINARY
8 - 1000 C - 1100
9 - 1001
D - 1101
A - 1010 E 1110
B - 1011
F - 1111
EXAMPLE (DF): D-1101, F-1111, DF-11011111
5) Translate the two hexadecimal digits from the binary.
T onto
EXAMPLE (5F): 5-0101, F-1111, 5F-01011111
6) Determine the binary digit (bit) that is different between the EXP and the QDT. The leftmost bit is D7 and the rightmo8t bit is DO. In our example the Dl bit is different. This indicates that the chip marked Dl in Figure 2 in the position C9 (remember, we already got it down to C2 - C9) is defective.
D
EXAMPLE: EXP
WT
76543210 DF-110l1111 5F-01011111
X-- (D7 is different)
13.22
/
Apple Computer Inc · 1982
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LOW ADDRESS
(2oXx - 3FXX)
and
HIGH ADDRESS (8oxx - 9FXX)
RANGES
A
i
MIDDLE ADDRESS (4oxx - 7FXX)
RANGE
Apple Computer Inc · 1982
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TRANSLATING MISSING SEa(ENTS OF THE MEMORY MAP DISPLAY INTO PHYSICAL RAN LOCATIONS
Sometimes the Memory Test doe8 not give an error message, but instead erases a portion of the memory map display, and continues to test the RAM. Figure 4 below is an example of a memory map display with a missing segment.
First, notice the bank(s) that are missing in Figure 4 (listed down the left side). Correlate the bank(s) to the physical row of memory. In our example, banks 3,4,5 and 6 are missing. This means that the failed RAN is somewhere in row C.
Determine the address range(s) that are missing (listed across the top.) Translate the address range(s) to the physical section. In our example, address ranges 5OXX 5FXX and 7OXX - 7FXX are missing. This falls within the address range 4OXX - 7FXX and tells us that the failed RAM is one of the eight which is physically located between ClO - Cil on the memory board.
Change the chips in that section, one at a time, retrying the RAN test each time. If the problem still remains, replace the old RAN back in the board and try another of the eight.
If you change all eight chips without fixing the problem, try the two non-RAN chips at location D2 and E2 0m the SV Memory Board.
DDS RAX3ES
(2øoc - 9F)
K
sank 2
3
4
5
6
7
9
9
g
0
0
0
0
0
F
64 96 128
0 1 2
.......................................................................,..............................
160
3 )C000000000cC00000000-
)OOCOOOC(------)OOOOOOOGccOc(
....... ... .................. ............... 192
224 256
4 5 6
oocococo------oCO-C0OO0C0(-c-----)ooccocoOooOoOc<
OOCOOOOOOOOOCOOCOOOOOO(
-000000-- coocccocccoc<
Extension ($8F)
13.24
FICTJRE 4
Apple Computer Inc · 1982
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acomp
13.25
I
Apple Computer Inc · 1982
Page 0287 of 0730
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ippkz comp*ar i:v
ST.NMARY
Translating Error Messages Into Physical RAM Locations
Error Message: BNK 84, ADR 37XX, EXP 40, oeT 48.
The physical row is determined by the bank number which is the bank is the last digit of the number in the BNK section. (Bank 4 in our example puts the problem in row C.)
Which half of the row is determined by the address range. Our example puts the problem in the right half of the Memory board (Columns 2-9).
The location of the failed RAN chip within the half row is determined by decoding the EXP and T messages.
HEX BINARY
O - 0000
i - 0001
2 - 0010
3 - 0011
HEX BINARY 4 - 0100 5 - 0101 6 - 0110
7 0111
HEX BINARY 8 - 1000 9 - 1001 A - 1010
B - 1011
HEX BINARY C - 1100 D - 1101 E - 1110 P - 1111
EXP (40): 4-0100, 0-0000, 40-01000000
T (48): 4-0100, 8-1000, 48-01001000
76543210 40: 01000000 48: 01001000
----X---
(D3 is different, so the RAM chip at C5 is bad in our example.)
18 1716151413121110 9 8 7 6 5 4 3 2 1
MIDDLE ADDRESS (4OXX - 7FXX)
RANGE
LOW ADDRESS
(2OXX - 3FXX) and
HIGH ADDRESS (8oXX - 9FXX)
RANGES
13.26 /
Apple Computer Inc · 1982
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ppcompturm
Translating Missing Sections on the Memory Physical RAM Locations
Display into
Determine which row the failed RAN is located from the Memory Map display.
Determine the half row the failed RAlf is located from the Memory Map display.
Replace the eight RAN chips in that half row, one at a time.
Replace the nonRAN chips D2 and E2.
co1
2-9
1g-17
f-
Sank 2
3
4
5
0
0
e
O
r0
rwJ(43
C 15
)C000000000000000000000oc
OOO
($)
6 0
O
COI
2-9
Y
9
9
9
g
e
p
13.27
I
Apple Computer Inc · 1982
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I/I USING THE APPLE
FLOWCHART
How to use this flow chart:
Start with the box at the top of the EXEC page.
Perform the action(s) indicated in each block. It's a good idea to take notes on what tests you've done and what the results were.
The diamond-shaped blocks are decision points. Many of them contain a test to be made, and a description of a possible result. After doing the test, take the YES exit path if the result you got from the test matches the one given; otherwise take the NO exit path.
Some decision blocks direct your path based on the results of a previous test (usually just before the decision point). Take the YES or NO exit path based on the results of the indicated test.
If the system successfully does everything that it should do in the EXEC flowchart, you will be directed to go to the flowchart section appropriate to the problem that you have (**** list here ****). If the system fails, a corrective action may be indicated, or you may be directed to the NO BOOT/NO RESET flowcharts for further tests.
Most terminal blocks (ones with no exit) contain a list of motherboard chip locations. Replace the chips at the indicated locations one at a time. After each substitution, test the system to see if the original problem has been fixed. If it is gone, great. If it is still there, try the next chip. If you run out of chips in the list, check the inputs and enables to the listed chips. If you find any that are faulty, trace the fault back towards the source.
Some terminal blocks will contain instructions for corrective action. Do what it says, then test the system.
If you haven't fixed the problem, you have reached a place where the flowchart won't help you (though you should suspect the area of the circuit that it has led you to). Good luck. Once you find the problem, see if you can fix the flowchart so that it will cover that problem. Notify Service Engineering in Cupertino of any errors you find in the flowchart, and of any additions or other suggestions you want to make.
13.28
Apple Computer Inc · 1982
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Flowcharting Wnrsheet
PROGRAMMER CHART IO
L1'4'Q7 CHART NAME #4///
PROGRAM NO
DATE PROGRAM NAME
PAGE _J__ 0F__L
4'Z(A -
connect logic and memory P03 into teat I'5t5*
Aaaupt ion:
everything except
for th, logic tedi or memory being tested ia known rood
attempt to boat FINAL TEST disk
80 tO $0 soar
ttovch.xt
Successful mean. that you hear the beep aridi or see the "REV R BOOTED
L li, ff9
Tea
L'
y-.
o
go to flowch*rl appropriate fo: the st.ted nroblem
L13
13.29
Apple Computer Inc · 1982
Page 0291 of 0730
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PROGRAMMER LrIART IO
4' CHART NAME
007
Flowcharting Worksheet
PROGRAM N
(A/O
7)
DATE PROGRAM NAME
PAGE
Does 88 Pin 40
-. Blink L beforu
AS,
Doe. 38 Pin 37 Clock et 0 2 J4Z
86 n
Does 38 Fins 9-2 except tor 18,20 21 clock during power up?
36
c1o!n7tt no 2 IZ
.5
vit ch to - 1
on rese
-mm
Tes
88
pini 9 - 25
no
2 is.
i9 21 high 7 ei
ye.
87, AlI
ri, D5
812
pin
Using hi
T
8
ne pini 26-33
insitia.
yea
C3
i.. pini 12-19
C3
rensitio
no
3 13
no oscifleter
no
ClO, £10
ne
85,36
't'o
88
13.30
Apple Computer Inc · 1982
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PROGRAMMER CHART IO
CHART NAME
'
b.c ths rat sap flesh on th. acree during boot?
Ye.
Doe. Pin U of JiG ?raci.i.tion during boot?
Flowcharting Worksheet
PROGRAM NO
Rag
Ne
sap flash o
lcee
)A1F PROGRAM NAME
Ye.
Whole
rows chova
bd
errer se. lage
S A GE
ROM VIA ACIA A/D ¿IP
interns iv. casa
Y..
Retry ceag.
get into sea ter sqde
CTR1..RS?)
try to turn the drive on cø DI4/CØY.A)
PAGE ......L.... OF-3.--
Replace bad
chipe REPLACE 81
replace L12
replace K12,Jlø
Repite. Kil
Ro
Jlø
in ii Tran tions
"ci
oot
Y..
Cycle Disk ht,. Lia..
(cOEO. eOErfX)
o
RA3SITION
URING 3
Ye.
Y..
Motor on
t
Yes
Light On
'I
Replace 39
Doe. Kil pins 6 &
8 Tranait ion Dring loot?
REPLAGE KlO
Io
L12
Pin 6 Low
l!o
Replace
LU
Repiac. L13
Replie. K9
Lii Pin 5 High
Replace
LU
13.31
1UIE
Apple Computer Inc · 1982
Page 0293 of 0730
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Ilowcharting Worksheet
PROGRAMMER CHART ID
CHART NANE NO 8007
('E-*P.R'.OyG'M)M NO
DATE PROGRAM NAME
PAGE
Do the Dita Li.i (ptna i-16) on connector tr&nsittefl?
Do the tiding 1n& flO,11; Gli, 12 Pin
i.i-iìi tr&nsitiøn?
Do the &ddr.e$ Lin..
on coeCtOT .117
(Pin.-10,2) trins-
ist ion?
Replies Appropriets Chip F10,11; 011,12
*9.
B5
pproprit.
Lp for Mdr n, £12, 13
fl2,13
c12, 13 D 13
13.32
Apple Computer Inc · 1982
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PROGRAMMER CHART tO
CHART NAME
VIDEO
Ftowcharting Worksheet
PROGRAM NO
OAT 4I1O/82
PROGRAM NAME
PAGE L........OF_L
Apple Computer Inc · 1982
Page 0295 of 0730
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PROGRAMMER CI4ART ID
CHART NAME
VIDEO
Flowcharting Worksheet
PROGRAM NO
DATE PROGRAM NAME
3/10
PAGE 2
OF&...__ f
Apple Computer Inc · 1982
Page 0296 of 0730
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PROGRAMMER CHART IO
CHART NAME
VIDEO
Flowcharting Worksheet
PROGRAM NO
DATE 1I
PROGRAM NAME
PAGE
LIC 1J-12 SetaJd Pss
Pic 10 11,12
Spec eber
A5
f..
ic ie-lG
Pic 114_16
Should Pe..
El
p.cebsr
The
Shouldn't
3e
fiere
No Proble* vith Video
13.35
Apple Computer Inc · 1982
Page 0297 of 0730
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PROGRAMMER CHART ID
CHART NAME
Video
PROGRAM PIO
DATE PROGRAM NAME
IiO PAGE 4 OF
îEi
E1OJ
J3F4
H3
H2
No Proble* Motherboard
olp
Video
Yea
Q4 RP4
09
13.36
Apple Computer Inc · 1982
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PROGRAMMER CHART IO
CHART NAME
&'/Ec
Flowcharting Worksheet
PROGRAM NO
DATE PROGRAM NAME
PAGE
H6
OJD3
E6
13.37
Apple Computer Inc · 1982
Page 0299 of 0730
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5 ... .......
PROGRAMMIR, CHART ID
CHART NMAE
Vid.o
PROGRAM MO
DATE 3110 PRO(RAM NAME
PAG...........OF...L....
Cs
Pin 2
F3
ran
Cs
CS
Pin 4
Trin
H3
CS
n 23
Nb
Hi
Cs
EìJ
Shouldn't
bi
Her.
Hb
13.38
Apple Computer Inc · 1982
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PROGRAMMER CHART ID
CHART NAME
Keyboard
PROGRAM NO
DATE V1/
PROGRAM NAME
PAGEL..........O..2........
Keyboard Probleas
Rwi KID Diagnostics
Test Main Keyboard
No Logic Icar Problem
(Keyboard fait urs)
Y"
V H12,J12. H14
HI I
No Character Resoved
¡
Palee
1114,H8 1110,X11
True
1114
lest
NU.TIC
Teat Special Keyi
yes
13.39
Apple Computer Inc · 1982
Page 0301 of 0730
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PROGRAMMER CHART ID
CHART NAME
PROGRAM P40
KEYHOARD
DATt 4I1ki
PROGRAM NAME
PACE ...2........OL.L.
REPE EBRO"
UT? DIAGNTI
HOLD DOWII A LETTER
KEY
Exit Diagnostici
Enter J'nitOr
Type cOød then hold down vach of the aoditier
kesas you presi (*LTiS)
Pod. Key cØ8 Content
None
TO
t.l Shift ¡ 7F 79_
AiphaLock 75
Replace
J12
gy cft8 Content
Open apple ED
Solid Apple OD
Nons
PD
SLOW REPEAT
cac
Ye'
Presi the solid-apple key too
Fast repeat
ES
Rø.Cl8,Cl7
C75,CR3,CR2
CR3 ,CR5
Error in R. C. Tining Circuit
c16
Tes
No Probl in keyboard Logic
13.40
Apple Computer Inc · 1982
Page 0302 of 0730
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f PROGRAMMER CHART IO
CHART ÑAME
-232
Flowcharting Worksheet
PROGRAM NO
DATE PROGRAM NAME
PAGE LL....0F..il....
3LEEz1
13.41
Apple Computer Inc · 1982
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PROGRAMMER CHART ID
CHART NAME PERI
Flowchartlng Worksheet
PROGRAM NO.
DATE PROGRAM NAME
PAGE
eck PeriFMral Slot Pin 19 for Traaiti
D11,FT
Does Pin 35 of Peripheral Slots
I Switch Between
I.IZ and 2 ISIZ
El.
E5 C//'7c,
/3A4
34z-oe'4,
'ICIe &nd 6 Pini li-il. re very h*rd to see. It they trigger the scope, they're prob&bly ok&y.
uLL43E[ l
13.42
Apple Computer Inc · 1982
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PNOGRAMMER CHART ID_
PROGRAM NO
_CHART NAMEP IPBIRA3. S1ß1 PROBI2M
DAIC PROGRAM NAME
PAD L.....oLL...
15
P.iinn i17
R9
nl,
Te.
a6
J
'J No
Ye.
VJ 09
'xis and .76 pine ii-1h are vary hard to .ee. If they trigger the scope, they're probably okay.
13.43
Apple Computer Inc · 1982
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0RAMMEfl
CHART ID
CHART NAME
DISK
Flowcharting Worksheet
PROGRAM NO
DATE PROGRAM NAME
3/15
PAGE. L_OF
L13
Loop o extern&1
disk test
xli
K12
InIrr IJ
1 E;
V(r1nt r n (. -
U'LPJ
13.44
Apple Computer Inc · 1982
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PROGRAMMER CHART ID
CHART NAME
Flowcharting Worksheet
PROGRAM NO.
DATE PROGRAM NAME
3/15 PAGE .L_..0FJ_.....
¡.13 ¡.12 J3.].
LU
K9
13.45
Apple Computer Inc · 1982
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PROGRAMMER CHART ID
CHART NAME
DISI
Flowchartlng Worksheet
PROGRAM P40
DATE PROGRAM NAME
KlO
Kil
K12
Jig Kit Juj
13.46
Apple Computer Inc · 1982
Page 0308 of 0730
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dowcharting Worksheet
PROGRAMMEA CHART ID
CHAUT NAME
PROGRAM NO...............
DATE
SOUND
PROGRAM NAME
PAGE
Audio Prob1.
Run
Audio Diagno$tic
Al
oua. S interni
RS RP9
No Audio Probiss
îi
13.47
Apple Computer Inc · 1982
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PROGRAMMER CHART ID
CHAflI
Flowcharting Worksheet
PROGRAM NO
DATE PROGRAM NAME
PAGEJOF..j....
:iw
Îi
13.48
Apple Computer Inc · 1982
Page 0310 of 0730
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PROGRAMMER CHART ID
CHART NAME
Flowcha?Iing Worksheet
ROM
PROGRAM NO
DATE PROGRAM NAME
PAGE
.OF_L..
RON TEST TAX LURE
39
LjL3EID
13.49
Apple Computer Inc · 1982
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PROGRAMMER CHART IO
CHART NAME
Iowciarting Worksheet
LGRAM NO.
i1ertve
DATE PROGRAM NAME
PAGE .!__OF....i...
SILENTYPE PROBLEM
.1 RUN PRINTER PORT TESTER
IN A LOOP
SEE 'LOOPING DIAGNOSTI'
BROKEN TRAC! CONNECTOR
.73
L3.2
.79 1,
13.50
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
-J
u coni* r
FAULT ISOLATION - TIPS MD HINTS
The following pieces of information are by no means an absolute guarantee of success in isolating a failure mode. This is intended only as a CUIDE or AID to assist you in finding a logical and likely place to begin your troubleshooting of the particular failure moda. F6E6 TEST (12V MAIN LOGICS)
RJJ1 indicates a memory failure. Use the chart included below to determine which chip on the moemory board is failing. Other possibilities are the memory board
connectors. If is is an addressing problem, check J17, (the connector on the right) and if it is a data problem, check J16, (the connector on the left).
LAX FAILURE ART 128T SYST( DISPLAY
DIAGNOSTIC
A 1 showing any place that a dot is shown here indicates a failure. The position of the one shows which chip has failed. The chart below shows the chip location on the memory board.
B9 38 37 36 35 84 33 82
B17 816 315 B14 313 812 311 BiO
B9 38 B7 36 35 34 B3 82
317 316 BiS C14 313 B12 Bu BiO Cil C16 C15 C14 C13 C12 Cil ClO
D9 D8 Dl D6 D5 D4 D3 D2
D17 D16 D15 D14 D13 D12 Dii DiO
C9
'2 C7 C6 CS C4 C3
ROM indicates that the ROM failed. Check the ROM at 89 (341-0031-01). Usually
the ROM itsely is bad when this message appears.
VIA indicates that a register in one of the 6522's has failed. These two parts are the 40-pin IC's at location 36 and 85.
ACIA indicates that the 6531 located at Bi has failed. AID ia an indicator of a bad read of either the high or 1w reference voltage of the 9708 chip located at M9.
ZP indicates a zero page register failure. The zero page register is port B of
13 51
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Apple Computer Inc · 1982
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the 6522 located at B6. Other possible chips for this failure are the 5257e at locations D7 and D8 or the Ls132 at D4. This is where the zero page portion of the address gets fed to the system memory. Also note the NOT ZPGE signal which should originate at the LSS I at BI 1.
RETRY is a message the system gives when it is unable to "boot" the disk that is (or should be) in the internal disk drive.
OTHER FAILURE MODES: These are usually idetified when running the normal system test diskette.
NO RESET is probably the most difficult porblem to fix and the easiest to identify. It's main symptom is that when power is truned on, absoultely NOTHING happens. The disk does not even ATTEMPT to boot and there are no beeps. Keep in mind that SIGNATURE ANALYsIs is a very good way to find a NO RESET problem. Below are some of the things that you can check fairly quickly:
Is the keyboard light lit and is the LED on the PC boared lit. It not make sure all power is available. +5VDC, 5VDC, +12VDC, & 12VDC.
Make sure that +5VDC and ground is available at each row. (Especially rows B, D, F, & G).
Check the levels at the RESET, NMI, IRQ, and RDY pins of the CPU at B7.
Swap the ROM (B9) with a known good ROM. If there is no difference replace the original.
Swap the CPU (B7) with a known good CPU. If there is no difference replace the original.
NOTE: These last two items are the most common reasons for NO RESET.
Power OFF and check for shorts on the Address or Data Bus.
Make sure that all clocks are runing. Phase O, PRE1M, 14M, 3.5M, and 7M.
Other devices that are frequently causes of NO RESET are listed below:
LOCATION
Row F & C Row B C3 Row E & F AS D13 D6 D3 & D7 K9 D9 Dli
DEVICE
7643 6522 8304 74S153 NE556 74S374 74LS244 74S257 74LSO4 74LS02 74S74
COMMENTS
high failure items B6 is more likely high failure items high failure items and supporting circuitry high failure items high failure items Not very often not very often moderate failure item Make sure its not LS
13.52
Apple Computer Inc · 1982
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ppI - r1
-I
G7 & 37 G8 RB 38
74LS133 74LS139 74L504 74LS32
high failure items high failure items high failure item moderate failure item
For a RAM addressing problem check the memory board connector on the right side, (317), and for a RAN data problem check the memory board connector on the left, (J16). NOTE: A RAM data problem will USUALLY run the F6E6 test.
Miscellaneous reset problems have been caused by the following:
diode CR4
reversed, open or missing
RPI9 (s19) Xtal
3 3K shorted not oscillating
reset key
bad
power or ground
missing due to open pi/ trace
It may also help you to know that there is an 85% chance of the problem being
I/I found on sheets 2 and 3 of the Apple
schematic, and a 13% chance of being
found on sheets 9 and 4. Good luck on the other 2%.
NO BOOT is recognized by the fact that the system actualy ATTEMPTING to boot even though it doesn't succeed. Video may or may not be present. You may see the RETRY mes8age, and the disk may run itself off, or it may stay on. Some of the more common things to check are;
The 9334's at L12 and L13.
The 74LSO4 at 19.
The mostly likely choices are:
device
location
74LS323
KlO
74S471
Kil (P6A prom)
74LS174
112
I/I Concentrate your troubleshooting efforts on sheet 6 of the Apple
schematic,
unless you find a problem with the NOT devsel-6, or the NOT Q3 signals. Any
other problem external to sheet 6 would most likely also show up in a RAN test,
or video test.
VIDEO probleme can be very simple at times and downright troublesome at other times. Some of the nose common failures are:
By far, the most likely candidates, are the 74LS374'a, located at E2, F3, F2, F3, G2, & ClO. These IC's are the cause of >70% of the video problems.
It is also a good idea to check the two 2114's located at E4 and E5.
The next moat frequent failure is the 74LS153 at LB. This is U90 as shown on sheet 5 of the schematic.
Video problems are also very likely to be misdiagnosed timing problems. For these check the 64Sl95 at DiO and the 74LS374 at Dli.
If the video horizontal or vertical sync appears to be messed up, check the 74LS161's located at F10, Fil, Gil, and G12.
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If none of the above items point you toward the real problem, begin your troubleshooting on sheet 5 of the schematic where 80% of the problems occur, and if necessary, go on to sheet 9 where most of the remaining video problemB will be found.
Keep in mind that an off-frequently crystal can kill the color or produce bad color.
INTERRUPT problems almost always end up being one of the VIA'S (or p522's).
However, there have been a few other reasons for interrupt failures as de-
scribed below:
ib NMI is a symptom for sheet 8 of the schematic. Check the 74LS132 at
,jQ. and the 74LS139 at Jil.
IRQ signal missing can be caused by the 74LS21 at
Sometimes the problem is noit actuaLly an interrupt problem but the systems
inability to communicate with the ihterrupt test cards. In the case of a
missing IO SELECT, check the 74LS138
and in the case of a missing
DEVICE SELECT, check the 74LS138 at K4.
Remember to check the connectors at the slots for continuity to the 74LS138's
mentioned above.
Lastly, here's what happens during the INTERRUPT test:
Step i Step 2 Step 3 Step 4 Step 5 Step 6
Step 7
Disable all interrupts, mask NMI, enable 1.0 space, reset ACIA, re set all four slots, and set up the 6522's as they are normally used. Check both 6522 lut enable register bits 0-6 to see if they can be set and cleared.
Vertify that IRQ and 10N111 are clear as they should be. Clear both 6522 interrupt flag registers and vertify that they are indeed clear. Check the 6522 interrupt flags to see if they can be set and cleared when enabled and vertify that they cannot be set when disabled. Repeat once for each slot.
Set slot IRQ by using IO SELECT and vertlfy by polling slot. Clear slot IRQ using CO2X and vertify by polling slot. C. Vertify that the 6522 at B6 caught the IRQ and that it was the correct one and that it can be cleared. Set slot IONMI using DEVICE SELECT and vertify by polling IONMI. Clear slot IONIC using CO2X and vertify by polling 1011X1. Check for shorts between slot IRQ's by setting IRQ on one slot at a time and checking each IRQ on the other slots.
AUDIO troubles are usualy fairly Simple to repair. The most common ailments
are listed below:
The most common frequent failure is the LM380 which is located at Mli, and
rarely you may find a problem in its associated circuitry, notably R36, a 1K
resistor and C12, a lOuf cap.
The second most frequent, usually noted on the C040 portion of the test, is
the 556 located at Al.
t
Another corn_mon ailment is Jil, the external speaker jack which is the mini-phone
jack at N4. Note that a bad contact in this jack can also preveùt you from
hearing any internal sound.
Failure of the CO30 test can be caused by the 74LS74 at R7.
And last, a failure of the FFEO test can be caused by either the 6522 at
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35, or RP9 the SIP located at C5.
ACIA problems are also ueually fairly simple and usually end up being caused by only a few items:
The most common failure is, of course, the 6551 itself. This is located at 32.
The next Items to check, will be the 1488 at J2 and the 1489 at K2. The third most common failure is .14, the 25 pin D connector at N2. The less likely things to check, are, the SEL6551 f rom the 74LS138 at RA7, and the RC network (or R.-pak) at N3.
PADDLE PORT problems frequently coincide with printer port problems. This is because they both share the DB-9 connector N1O, (J3). Some..causes of paddle port problems are:
The 9708 located at . This is the most common cause of failures. The second most frequent cause of failures is the RC network at NiO. Other things to check that can sometimes cause problems, are the9334's at locations H6, L12, and L13. These IC's supply some fo the enable neccessary during the paddle port tet, including the disk pahses, and disk side 2/1 signals used to test the switches, as well, as the ENSIO and ENSEL signals. Also check the enables coming from the 74LS138's at K4 and Kl. Finally check the 74Ls251 at L7 and its enables.
RAM FAILURES can be almost as much fun as no reset can be. Same of the things to look for are:
Of course, the most obvious thing to check is the F6E6 test results and see which row, group, chip(s) are causing problems. Also check the two memory board connectors .116 and .117 at this time.
You have about 982 chance of the problem being on sheet 2 of the schematic. With the highest probability, being the 74LS399 at A9 and the 74S3 74S374 at D13.
Next check the 7643's at locations Cb, Cil, C12, and C13, and then check the 74S153's at E12, E13, F12, and F13.
It may be a little help to do the following IF and ONLY IF you can get into the monitor routines using a CONTROL-APPLE-RESET:
Type the following:
FFDO: 0/FFDF:IF/FFEF:o (RETURN)
You have just set the bank register and zero page to O and disabled the screen and IO addresses. (Note that FFEF if the bank register and you may want to try settings other than O if this setup doesn't find your problem. Now type:
O.FFFF/X (RETURN)
The address bus should now be one big 16-bit counter and therefore easier to trace with an oscilloscope.
PRINTER. PORT failures will show up as paddle port failures most of the time.
The few exceptions are, that some of the polarities of the enables are reversed,
causing the signal direction to also be reversed. (For example, a paddle port INPUT becomes a printer port OUTPUT). Also, be sure to check the connections
to slot 1 to
way to check
insure that this, is to
the test hardware will function properly. The best check for continuity from slot 1 to slot 4, (except
for pins 1, 30, and 41).
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DISK failures will usually prevent the system from booting properly. There are, however, a few things which should be mentioned here. Ji and J6, the EXTERNAL and INTERNAL drive connectos, respectively, are in parallel, with the exception of pins 14, 21, 22, and 26. A disk phase of SIDE 2/1 failure will usually also show up as a switch failure in the paddle port test. The RC filter networks at N13 and M13 are also a good place to check for problems. (See the section below on usef lu addresses in order to toggle a particular signal).
KEYBOARD failures are another of those problems that, while they occur f requently, are neverthelessa, fai].ry simple fo correct. Some fo the more common failure modes are: If the fast repeat or the super fast repeat either fail to work, work all the time, or repeat way too fast, check the 556 located at LlO and also the C16 capaci tor. Another thing to check if there is no fast repeat is diode CR5, located M7. If the data from the keyboard is wrong, check the keyboard encoder chip at H14, (check its power connections too,) or one of the 74LS257's located at H12 or J12. If one of the above hasnt led to the problem, check the 74LS05 at H9, or the 74LS132 at RiO. Lastly, if the power light of the keyboard fails to light, check transistor Q9. ROM failures are almost ALWAYS, (99% of the time), the ROM chip itself located at B9. On rare occassions, it could be that the IC located at P9 is NOT a 341-0055, as it should be.
THERMAL or t1HEAT SENSITIVE" failures: (These should be vertified as heat sensitive as described in section 4.4 above).
After vertifying that the unit is actually heat sensitive, you will have to locate the area of the board where the problem is. Do this by looping on the portion of the diagnostic that failed and moving the heat gun over the affected areas. If the unit does not fail within a few minutes, move the heat gun to a different area fo the board and continue the process.
When the test begins to fail, you have found the correct AREA of the board. You may now want to use, a monitor command of some type with the X (or repeat) command, for your troubleshooting. The most frequently heat sensitive devices are the ROM located at B9, the 6502-B located at B7, and the 7643 PROMS (with the 342-OOxx numbers), scattered throughout the board.
TROUBLESHOOTING INFORMATION'
SYSTEM DEATH ERRORS and their meaning:
error code
meaning
$01
bad break (BRK) from SOS
$02
interrupt not found (but received at CPU)
$03
bad zero page allocation
$04
unable to lock NMI
$05
event queue overflow
$06
stack overflow
$07
data manager detected invalid request code
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$08
dmgr - too many device handlers (drivers)
$09
memory too small ((64K)
$OA
volume control block not usable
SOB
file control block crashed
$OC
allocation blocks invalid
SOD
directory is not correct
$OE
pathaame buffer overflow (too long)
$0F
invalid buffer number
$10
invalid buffer size (-0 or >16K)
ul
MONITOR AND ESCAPE COMMbNDS MONITOR COMMANDS:
COMMAND addrl addr2
REMARKS memory dump, to dump all memory locations
from address $30F! you would type, 3000.
30FF and press RETURN.
addrl:byte list
store byte(a) in memory, just like Apple }{,
to store data starting at address $3000, you
would type, 3000.00 Al PF 45 9C etc. To store
ascii data, you would type, 3000: 'DARRELL' for
block <addrl.addr2
high bit off, or 3000: "PAYNE" for hihg bit on. read block from disk into memory from address I
to address 2. Block must be in the range $0 to
$117 (O-280). For example, 0<2000.20FP would
read block O of the disk and store the data in
memory form $2000 to $20FF.
NOTE: i block + 512 bytes, and the SOS directory is at block 2.
block <addrl.addr2w
same as above except writes data from address 1
to address 2 onto the disk starting at block.
addr3<adcjri.addr2M
move data from memory beginning at location ad-
dress 1 and ending at address 2 into memory be-
ginning at address 3.
addr3<addrl.addr2v
Vertify that the date in memory from address 1 to
address 2 is the same as data in memory beginning
at address 3.
byte<addrl.addr2S
search memory for data that matches byte starting
at address 1 and continuing search through address
2.
addrG
call subroutine at address. This is the same as a
addrJ
JSR in assembly language, or a CALL in BASIC jump to address and begin executing code. This
is the same as a JMP in assembly language.
U
calls user routine. This actually does a JSR $3F8.
X
repeat entire command line. For example, COEO/
COE1/X will continue to toggle disk phase O on
and off.
Note that most of the Monitor commands are the same as they are in the Apple }{, except some have been added and others have been improved.
UW, 1,2 ESCAPE COMMANDS: These are achieved by pressing the escape key followed by the desired command:
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COMMAND Cuti-K or up arrow cuti-J or du arrow cntl-H or left arrow cuti-U or rt arrow L P
S 4 8
REMARKS
moves cursor up moves cursor down aoves cursor left moves cursor right clear to end of Line clear ro end of Page clear screen set 40-column display aey 80-column display
using the monitor to cause a particular signal or group of signals to toggle
back and forth between high and low levels, can be a valuable troubleshooting
tool. Listed below are some commands you can use from the monitor to do this.
i/I They are listed as they are found on the Apple
schematic, by signal name,
(all signals on sheet 2 of the schematic are grouped together, page 3 signals
likewise, etc.) The signal name is given first, and the next line gives the
Monitor commands you must eater to toggle that signal. {C}, means hold down the control key while pressing the next key, and {R} means press the return key. (NOTE: After you have typed a sequence of monitor instructions and used the oscilloscope to look at the signals produced, if you need to look at some different signal, ALWAYS reset the system, and use the CONTROL, APPLE, RESET sequence to re-initialize the system since it could possibly be in an unknown state, caused by either the problem you are trying to isolate, or the last instruction that you typed in).
Page 1 signals are listed on the page where they originate. Page 2 signals are normally all running. Address lines and bank switch signals are listed on the page where they originate.
Page 3 signals Address lines:
FFDO: O/FFDF :IF/FFEF" O{R}
O .FFFF/X{ R}
Data lines and R/W:
3000:A5 5AJ3000.3001/X{R} Page 4 signals: GB outputs, (74LS139)
FFCO/ FFDO/ FFEO/ FFFO/X{ R}
J6 outputs, (74LS138)
C000/C100/C200/C300/ C400/C500/C600/C700/x{R} K4 OUTPUTS, (74LS138)
C080/C090/COAO/COBO/COcO/cODO/COEO/COFO/X{R} K7 outputs, (74LS138)
C000/C01O/CO2O/CO30/CO4O/CO50/ccj60/C070/X{R} H6 outputs, (9334) CO50.CO5F/x(R} 6522, Port A, (Environment register) A000.A2 SA AL) AS 8E DF PF 8C DF FF 4C 04 AO{R} A000G{R}
6522, PORT B, (Zero page register) A000: A2 5A AL) AS 8E DO FF 8C DO PF 4C 04 AO{R} A000G{R}
Page 5 signals should always be toggling if the screen is enabled, and something is being sent to the screen, (whether or not it actually gets there).
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Page 6 signals
L13 outputs, (9334)
COW. COEF/X{ R) L12 OUTPUTS, (9334)
CODO. CODF/X( R}
Page 7 signals
BCKSW1-ECKSW4 A000:A2 5A AD AS 8E EE PF 8C E! PF 4C 04 AO{R}
A000G{ R}
Li outputs (bit 7 only), 74LS251
C060. CO6F/X{R.} Sound signals will toggle continuously f rom sound test ACtA signals
COPO: 55/COFO/COFO:AA/COFO/X{R}
Page 8 signals Keyboard A port read C000/CO1Q/X{R} Keyboard B port read
C008/CO1O/X{R}
I/I. Page 9 signals should all be running. These are all of the main timing
signals for the Apple
Useful. addresses to know: If you wish to know the status of the CPU at the time of a system failure,
($010-$10), you can use CONTROL-APPLE-RESET, to enter the monitor and then examine memory beginning at $19F0, for the information. NOTE, this applies
ONLY when the failure occurred while running under control of SOS.
$19F0-19F1 $19F2
$ 19F3
$19F4.. $19F5
PROGRAM COUNTER STACK POINTER ENV IRON1NT REGISTER ZERO PAGE REGISTER BANK REGISTER
$19F6 $19F7 $19F8
PROCESSOR STATE REGISTER ACCUMULATOR (A REGISTER) INDEX X (X REGISTER)
$ 19F9
INDEX Y (Y REGISTER)
NOTE: If the failure was a $02, (interrrupt not found the index register X should contain one of the following codes:
$00
$01 $02 $03 $04 $05 $06 $07 $08 $09
$OA $OB $OC $OD 50E $0F
TONMI was the interrupt ACtA was the interrupt CA2 from 6522.E was the interrupt CA! from 6522.E was the interrupt shift register from 6522.! was the interrupt CB2 from 6522 .E was the interrupt CEl from 6522 .E was the interrupt Timer 2 from 6522> e was the interupt Timer i from 6522. E was the interrupt CA2, 6522.D CAl, 6522.D (ANY SLOT but no slot found) Shift register, 6522.D CB2, 6522.D CBI, 6522.D Timer 2, 6522.D Timer 1, 6522.D
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4"
$10
»INTERRUPT NOT FOUND «
$11
SLOT i was the interrupt
$12
Slot 2 was the interrupt
$13
Slot 3 was the interrupt
$14
Slot 4 was the interrupt
Keyboard:
C000 - "KA" Port
Bit 7
6
5
4
3
2
1
O
drdy d6
d5
d4
d3
d2
dl
dO
COOS - "KB" port
7
6
5
4
3
2
1
0
dl
kybd A2
Al
alk ctrl ef t anyky
A2 is solid apple switch
Al is open apple switch
alk la alpha-lock
etri is control
sft is shift key (either one)
COlO - keyboard reset
Speaker
CO30 - toggle speaker (same as Apple }(
C040 - Hardware bell (one beep)
FFEO - Bit O - 5 Apple /1/ sound (1)-A)
Screen Control
CO50 - CO57 (see sheet 4 of schematic)
CO50,CO51 - TT mode
CO52,CO53 - MIX mode
CO54,CO55 - PAGE 2 mode
CO56 , CO57 - HIRES mode
Joysticks, switches, and printer port
CO58 - O5F (se sheet 4 of schematic)
CO58,CO59 - PDLO, Address O of AID
(also disable/enable output handshake)
CO5E, 5F - AXCO, Address i of A/D
(output handshake line false/true)
CO5A,CO5B - PDL2. Address 2 of A/D
CO5C,CO5D - A/D ramp start
(NOTE: To read a particular joystick pot set correct address
as follows:
A3 A2 Al <Address lines
joystick #1 (XO) O
O
i
(ro) O
i
O
joystick #2 (Xl) 0 1
1
t,
Then use CO5D to enable the RAMP of the A/D. Bit 7 of c060 is switch O
C061 is switch 1 C062 is switch 2 C063 is switch 3 C066 is the joystick timeout (selected above) CODC, GOOD is ENSEL (direction of CEI in 6522. D, SCO) CODE, CODF is ENSIO (serial data R/W in 6522. D, SER) Bit 7 is IRQ3 and Bit 7 is IRQ4 CO9X is Device select for Slot 1
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COAX is Device select for Slot 2
COBX is Device select for Slot 3
C0 la Device select for Slot 4
Clxx la IO select for Slot 1
C2XX is IO select for Slot 2
C3xx is IO select for Slot 3
C4xX is IO select for Slot 4
CODA disables Character Generator RAM write, and
CODB enables Character Generator write.
COD8 disables hire scroll, and
COD9 enables hires scroll. If enables, then COW, COE1 is set/clear address VA! COE2, COE3 is set/clear address VB1
COE4, CORS is set/clear address VC!
VC! VB! VAl results in...
O
O
O no scroll
o
o
i i horizontal line wrap
0
1
0 2 horizontal line wrap
0
1
1 3 horizontal line wrap
1
0
0 4 horizontal line wrap
1
0
1 5 horizontal line wrap
1
1
0 6 horizontal line wrap
1
1
1 7 horizontal line wrap
Disk drive Addresses
CODO, COD! clear/set external drive address AO COD2, COD3 clear/set external drive address Al
COD4, COD5 enable, external drive power
COD6, COD7 Side 1/Side 2 signal. If COD4 (enable), then
AO Al
Result. in...
O
O
no external drive
O
i
external drive #1
i
C)
external dirve #2
1.
1
external drive #3
CORO, COE1 disk phase O set/clear
COE2, COZ3 disk phase 1 set/clear
COE4, COE5 disk phase 3 set/clear
COE6, COE7 disk phase 3 set/clear
COE8, COE9 drive motor disable/enable (begins time out)
COEA, COEB select internal/external drive
RS-232 Port, AdA, (6551)
COFO is received or transmitted data
COF1 Writing any data causee a programmed reset, while Reading the
following:
Bit 7 IRQ
6
5
4
3
2
1
0
NOT
NOT
TDRO RDRf i OVERR PRMERR PARERI
DSR DCD
COF2 is the command register:
Bit 7-5 are parity check controls
Bit 4 is ECHO control
Bit 3-2 are transmit controls
Bit 1 is INT
Bit O is DTh
COF3 is the control register:
Bit 7 is STOPB
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ppkicompuarm
Bit 6-5 are word length
Bit 4 Is NOT XCLOCK
Bit 3-O are the BAUD rate
VIA 6522 system control registers PPDO - Zero Page Register (Z register)
FFDF - Environnent register (E register)
Bit 7
6
5
4
3
2
1 MHz
lOEN SCRN RSTEN WPROT PRSTK
FFD2 - data direction register B
PFD3 - Data direction register A
1
ROM i
FFD4 - FFD7 Timer i FFD8 - FFD9 Timer 2 (used by printer port)
FFDA - Shift register (used by printer port) CAl (in) Anyslot IRQ (will not clear)
CA2 (in) printer port input handshake
CB1 (out) Printer port clock C82 (out) Printer port serial data
CB2 (out) joystick address O set/clear
FFEO - interrupt flags in / sound out
Bit 7 - 101*11 (in)
Bit 6 - IOCT (in) Bit 5-0 interrupt flags in / bank register (in/out) Bit 7 - NOT GIRQ
Bit 6 - Not A }{SW
Bit 5 - Not IRQ2 Bit 4 - Not IRQ1 Bits 3-O - Bank register (B register) FFE2 - Data direction register B PFE3 - Data direction register A
FFE4 - FPE7 Timer 1. FFE8 - FFE9 Timer 2 (input to IOCT flag) FFEA - Shift register (used for VBL)
CA]. (in) clock/calendar IRQ
CA2 (in) keyboard IRQ CB1, CB2 (out) vertical blanking
List of interrupt flag location:
C000 - Bit 7 - Keyboard
C064 - Bit 7 - Slot 3
C065 - Bit 7 - Slot 4
C070 -
- real time clock (function in Z reg)
FFDD - Bit O - CA2, printer port input handshake
Bit i - CAl, anyslot IRQ Bit 2 - shift register
Bit 3 - CB2
Bit 4 - CB]. Bit 5 - Timer 2
Bit 6 - Timer i BIt 7 - IR1, any of the above 7 IRQ's
FFEO - Bit 6 - IOCT Bit 7 - global IRQ, any IRQ in the system Bit 5 - Slot 2 Bit 4 - Slot i
FFED - Bit O - CA2, keyboard
Bit 1 CAl
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Bit 2 Shift register Bit 3 - CBZ, VBL X 8
Bit 4 - CBI, VEL X i
Bit 5 - timer 2, IOCT (slot) Bit 6 - Timer i Bit 7 - IRQ< any of the above 7 IRQ's
Vertify the problem found. Whenever it is practical always try to replace the problem that you removed to see if the same symptom previously encountered returns. If you have indeed, found the correct problem, the same symptom will return. Otherwise, the probela probably still exists and further troubishooting i. called for.
Vertify the fix. Once you are confident that you have repaired a problem, RETEST the ENTIRE system using ALL of the methods, described above in section 4.0. If no further problems are encountered log and label the board as repaired, making sure that ALL documentation, including SYMPTON, SOLUTION, and METHOD pf fault isolation, (especially if it was a tricky one), are included. If you DO find another problem, then RESTAIT the diagnostic procedure and attempt to isolate and repair the NEW problem that you ahve encountered. Repeat the entire process as necessary, until ALL problems have been identified and corrected.
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I/I COMMON FAILURES (FOR SHOTGTJNNING)
SYMPTOM
PROBABLE CAUSE
SELF TEST (F6E6C)
Self-Test but characters wrong
Self-Test with AdA error message
745257 (1166 (C12], 1169 (C13]) 74LS374 (114, (M13fl
t1i]) 6551 (1198
No-Reset
A//I FINAL TEST: PART A
No-Boot:
C¿?4A/:Ç
Video: Wrong colors
Random Patterns
Sound:
No sound or weak sound Sound does't sweep
B8, D13
/3()2vJ Prom 4) (1414], D3, 1113, 1111 c,
C5 loo pf
Es, F10, Gli
1.14380 (11103 (14]) 6522 (1197 (diO])
Serial Port: Fails
6551 (1198 (BiO])
Paddle Port: Switch Fails Paddle Fails
74LS251 (11101 (J1lJ)
9708
(11105 (L5])
ROM: Fails:
341-0031 (U64 (DiO])
A//I VINAL TEST: PART B
Printer Port
6522 (U73 (BiO]) 74LS125 (U160 (MA]), 74LS126 (11161 (17])
This by no means exhaust the possible failures. Try to use your technical ability to find out what's wrong.
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M-1 FfrLufE t-A
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8/ 83 81
Bl SU. 13'S gp.j 813 812 8fl 81'
C1 Ci.
,q C13 Ci
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b8 b7 b Ct b/ b3 D2
2.
L7 bu. bit D,q '3 7)12 bit bIA
Ç13 4
67 6
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s_c. I
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7'
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3'1 3 L
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1317 8S BiS BJ'I 1313 6t2
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q
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rt i(. 8i. Br ß3 512. Bit ß:o
LI
7 c,c. c.'. 6s'f 4j3 412. CII 610
3 D9 b D7 b6 ),g D1 D3 2..
7-
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple Computer Inc · 1982
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i Apple /// Computer Information · Apple /// Level 2 Service Reference Manual Apple /// Computer Information Apple ///
Service Reference Manual
Section II of II . Servicing Information
Chapter 14 Parts Layout and Parts List
Written by Apple Computer . 1982.
Apple Computer Inc · 1982
Page 0329 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
LOCATION
A05 AOl A09 All 502 803 B05 806 B08 B09 BIO
Bu B12 313 CO3 C09 ClO
Cli.
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D02 D03 D04 DOS D06 DOl D08 D09 DIO Dli D12 D13 E02 E03 E04 E05 E07 E08 E09 ElO Eli E12 E13 F02 F03 F04 F05 F07 F08 F09 F10
I/I APPLE
IC PARTS BY LOCATION
DESCRIPTION
IC, 556 DUAl.. rtn IC, 556 DUAL TIMER IC, 74LS399, QUAD 2 INPUT MLIX IC, 74S74, DUAL D-TYPE FLIP-FLOP IC, ACtA 6551k IC,PIICROPROCESSOR CLOC1( 58167 IC, 6522 VERSATILE INTERFACE ADAPTER IC, 6522 VERSATILE INTERFACE ADAPTER IC, MICRO 6502B 3MHZ TEST & BURN-IN IC, ROM BOOT/MONITOR B & T IC, 74LS20, DUAL 4-INPUT NANO IC, 74LS51, AND OR INVERT IC, 74S175, QUAD D-TYPE SLIP FLOP IC, 74S86, QUAD 2 INPUT EXCLUSIVE-OR IC, 83043 8-BIT TRI-STATE IC, 74LS260, DUAL 5 INPUT NOR IC, PROM 1024 X 4 IC, PROM RAS 65,12 VOLT MEMORY BD IC, PROM RA365, 5 VOLT MEMORY
IC, PROM CASB65 ADDRESSING IC, PROM CASI28, 12 VOLT MEMORY IC, PROM CASB256, 5 VOLT MEMORY
IC, 74S257, QUAD DATA MULTIPLEXER IC, 74S257, QUAD DATA MULTIPLEXER IC, 74LS86,QUAD 2 INPUT EXCLUSIVE OR IC, 74S74, DUAL D-TYPE FLIP-FLOP IC, 74LS244, OCTAL BUFFERS/DRIVERS IC, 74S257, QUAD DATA MULTIPLEXER IC, 74S257, QUAD DATA MULTIPLEXER IC, 74LS02, QUAD 2 INPUT NOR IC, 74S195, 4 BIT PARALLEL SHIFT REG IC, 74S74, DUAL D-TYPE FLIP-FLOP IC, 74LS00, QUAD 2 INPUT NANO IC, 74LS374, OCTAL D-TYPE FLIP-FLOP IC, 74LS374, OCTAL D-TYPE FLIP-FLOP IC, 74LS374, OCTAL D-TYPE FLIP-FLOP IC, 1024 X 4 STATIC RAN 2114 IC, 1024 X 4 STATIC RAN 2114 IC, 74LS00, QUAD 2 INPUT HAND IC, 74LSO8, QUAD 2 INPUT AND IC, 74S10, TRIPLE 3 INPUT NANO IC, 74S86, QUAD 2 INPUT EXCLUSIVE-OR IC, 74LS283, 4 BIT BINARY ADDER IC, 74S153, DUAL 4 TO I LINE MLIX IC, 74S153, DUAL 4 TO 1 DATA MLIX IC, 74S374,OCTAL D-TYPE FLIP-FLOP IC, 74S374, OCTAL D-TYPE FLIP-FLOP IC, 74166,8 BIT SHIFT REGISTER IC, IC PROM 1024 X 4 IC, PROM 1024 X 4 IC, 74LS08, QUAD 2 INPUT AND IC, PROM, 1024 X 4 IC, 74LS161,SYNC BINARY 4 BIT UNTER
APPLE PART NUMBER
330-0556 330-0556 306-0399 308-0074 338-0002 331-8167 338-6522 338-6522 369-6502 342-0031 306-0020 306-0051 308-0175 308-0086 316-8304 306-0260 342-0043 341-0044 342-0061
342-0056 341-0042 342-0063
308-0257 308-0257 306-0086 308-0074 306-0244 308-0257 308-0257 306-0002 308-0195 308-0074 306-0000 306-0374 306-0374 306-0374 334-0005 334-0005 306-0000 306-0008 306-0010 308-0086 306-0283 308-0153 306-0153 308-0374 308-0374 302-0166 342-0045 342-0046 306-0008 342-0055 306-0161
14.1
Apple Computer Inc · 1982
Page 0330 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
LOCATION
Fil F12 F13 G02 G03 GOS GOl C08 G09 Gb Cil G12 H02
1103
1104
1106
1107
1108
1109 1110
Mli H12
1114
J02 J03 J04 J06 J07 J08 JO9 JiO Jil J12 K02 K04 K07
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I/I APPLE
IC PARTS BY LOCATION
DESCRIPTION
IC, 74LS161,SYNC BINARY 4 BIT COUNTER IC, 74S153, DUAL 4 TO 1 LINE MIlK IC,74S153, DUAL 4 TO 1 MULTIPLEXER IC, 74S374, OCTAL D-TYPE FLIP-FLOP IC,74LS157, QUAD 2 TO i DATA MUX IC, VIDEO CONTROL ROM IC, 74LS133, 13 INPUT tim IC, 74LS139, 2 TO 4 LINE DECODERS IC, ROM, SYNCHROM IC, 74LS374, OCTAL D-TYPE FLIP-FLOP IC, 74LS161SYNC BINARY 4 BIT COUNTER IC, 74LS161,SYNC BINARY 4 BIT COUNTER IC, 74LS00, QUAD 2 INPUT NAND IC, 74LS399, QUAD 2 INPUT MIlK IC, 74LS51, AND OR INVERT IC, 9334, TESTED & BURN-IN IC, 74LS74, DUAL 1) FLIP-FLOPS IC, 74LSO4, HEX INVERTERS IC, 74LSOS, OPEN COL HEX INV IC, 74LS132, QUAD 2 INP NAND SCH TRIGO IC, 74LS74, DUAL D-TYPE FLIP-FLOP IC, 74LS257, QUAD DATA MUX IC, ROM KEYBOARD ENCODER P3 IC, 1488 QUAD LINE DRIVER IC, 74LS151, 1 0F 8 DATA MUX IC, 74LS21, DUAL 4 INPUT AND IC, 74LS138, 3-TO-8 LINE DECODERS IC, 74LS133, 13 INPUT NAND IC, 74LS32, QUAD 2 INPUT OR IC, 74LS125,QUAD VU-STATE BUFFERS IC, 74LS126, QUAD ThI-STATE BUFFERS IC, 74LS139, 2 TO 4 LINE DECODERS IC, 74LS257,QUAD DATA MUX IC, 1489 LINE RECEIVER IC, 74LS138, 3-T0-8 LINE DECODER IC, 74LS138, 3-TO-8 LINE DECODERS IC, 74LS374, OCTAL D-TYPE FLIP-FLOP
IC, 74LS11, TRIPLE 3 INPUT AND IC, 74LSO4, HEX INVERTERS IC, 74LS323,8 BIT BIDIRECT SHIFT REG IC, PROM, STATE MACHINE P6A IC, 74LS174, REX D-TYPE FLIP-FLOP RESISTOR ARRAY, 47 OHMS IC, 74LS251, IC, DATA MULTIPLEXER IC, 74S153, DUAL 4 TO I LINE MUX IC, 556 DUAL TIMER IC, 9334, IC, 9334 IC, 9708, 6 CHANNEL 8 BIT A/D IC, LM38O AUDIO POWER AMPLIFIER RESISTOR ARRAY, 47 OHMS RESISTOR ARRAY, 47 OHMS R.ES1STOR ARRAY, 47 OHM RESISTOR ARRAY 47 OHM
APPLE PART NUMBER
306-0161 308-0153 306-0153 308-0374 306-0157 342-0032 306-0133 306-0139 342-0030 306-0374 306-0161 306-0161 306-0000 306-0399 306-0051 302-9334 306-0074 306-0004 306-0005 306-0132 305-0074 306-0257 342-0035 360-1488 308-0151 306-0021 306-0138 306-0133 306-0032 306-0125 306-0126 306-0139 306-0257 360-1489 306-0138 306-0138 306-0374
306-0011 306-0004 306-0323 342-0028 306-0174 112-0102 306-0251 308-0153 330-0556 302-9334 302-9334 356-9708 354-0380 112-0102 112-0102 112-0102 112-0102
14.2
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple Computer Inc · 1982
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PRINTED 23-Jul-62 13.26 EFFECTIVITY DATE. ALL
PERSONAL COMPUTER SYSTEMS INDENTED BILLB OF MATERIAL
BIL VERSION 29-Mar-79 PAGE 1
PARENT PART: olO-8156
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C CABLE. k C. POWER CORD
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A SWITCH. KOD KCC ALPS
A SWITCH. ALB KCC ALT ACTION
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A LAMP. BI-PIN SV lISA
MA PIN. LAMP
A PLATE. KEYBOARD *3 ALPS
A PCB.MAIN Ii PIGGYBACK.KBD.A3
A CRANK. KEYBOARD *3 ALPS
A CRANK GUIDE. STRAIGHT. ALPS
A ADAPTER, STRAIGHT KEYCAP
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A CABLE *69V. KEYBOARD A3
B PIVOT SPACEBAR CRANK KCC
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A SPACER. RESET SWITCH
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Page 0333 of 0730
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Apple Computer Inc · 1982
PRINTED 23-Jul-82 13:27 EFFECTIVITY DATE: ALL
PARENT PART: 610-0156
LEVEL
6 6 6 6 O 6 6 6 6 6 6 6 a 6 6 6 6 6 6 6
o 6 6 6 6 6 6 6 6 6 6 6 6
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6 6 6 6 6 6 6 6
6
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COMPONENT PART NUMBER
815-0097 015-0098 815-0099 815-0100 015-0101 815-0102 815-0103 015-0104 015-0105 815-0106 815-0107 815-0108 815-0109 815-0110 815-0111 815-0112 815-0113 OIS-0114 815-0115 815-0116 815-0117 015-0118 815-0119 015-0120 815-0121 915-0122 815-0123 OIS-0124 015-0125 815-0126 015-0127 815-0128 815-0129 BIS-0130 915-0131 815-0132 813-0133 815-0134 815-0133 815-0136 915-0137 815-0138 815-0139 815-0140 815-0141 815-0142 815-0143 815-0144 815-0145
PERSONAL COMPUTER SYSTEMS
INDENTED BILLOOF MATER IAL
BIL VERSION 29-Mar-79 PACE 2
INACT. F0. 250K APPLE III EAC: R ERCE CODE: A TYPE:
(JI: EA PROD CODE:
ECH: Allé ASSEMBLY OTY:
ABC: A PLAN CODE: U DATE: 08-Jul-82
E PART DESCRIPTION
R
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
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Apple Computer Inc · 1982
PRINTED 23-Jul-62 13:29 EFFECTIVITY DATE: ALL.
PARENT PART: 610-9156
LEVEL
6 6 6 6 6 6 6 6 6 o 6 o o 6 6 6 6 6 o 6 6 o 6
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COMPONENT PART NUMBER
815-0147 615-0149 815-0149 815-0150 815-0151 615-0152 815-0153 815-0154 813-0155 815-0156 815-0157 813-0156 815-0159 015-0160 815-0161 815-0163 815-0179 062-00320 062-00330 062-00340 062-00360 062-00370 062-00360 062-00390 062-00400 062-00410 062-00420 062-00430 062-00440 062-0049D 063-0079 600-0009 731-0001 561-2400 520-0100 517-0002 650-5201 650-4201 650-0201 050-0031 020-0024 101-2271 101-2331 101-2561 101-4102 101-4103 101-4104 101-4153 101-4202
PERBONAL COMPUTER SYSTEMS
INDENTED BuLB OF MATERIAL
UIL VERSION 29-Mar-79 PAGE 3
INACT.F0.256K APPLE III ERC: U SRCE CODE: A TYPE: a
UM: EA PROD CODE:
ECN: A116 ASSEMBLY 01V:
ABC: A PLAN CODE: U DATE: 08-Jul-82
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple Computer Inc · 1982
PDF compression, OCR, web optimization using a watermarked evaluation copy of CVISION PDFCompressor
PRINTED 23-Jul-82 13:30 EFFECTIVITY DATE; AU.
._._.._PERSON. COMPUTER BYSTEY.B
INDENTED BILLa 0F MATERIAL
IL VERSION 29-Mar-79 PAGE 4
PARENT PART; 610-0156
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Page 0336 of 0730
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple Computer Inc · 1982
PDF compression, OCR, web optimization using a watermarked evaluation copy of CVISION PDFCompressor
PRINTED 23-Jul-82 13:30 EFFECTIVITYDATE: ALL
PERS4ALCOtI'UTER SYBTEMS
INDENTED ILLB OF MATERIAL
IlL VERSION 29-Mar-79 PAQE
5
PARENT PART: 610-8156
LEVEL
4 4 4 4 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3
3
3 4 5
3 3 3 3 3 3 3 3 3 3 3 3 4 4 3 3 4 4 3
4
Ç
COMPONENT PART NUMBER
805-0035 410-1206 825-0084 914-0028 825-0054 590-0017 517-0040 561-2209 550-0107 561-2200 561-2211 561-2222 561-2233 561-2244 561-2255 561-2266 561-2277 561-2268 561-2299 830-0010 830-0011 930-0012 805-0057 830-0014 865-0005 946-0000 910-0364 800-0364 815-0364 909-0003 815-0087 825-0163 430-1005 825-0321 825-0057 410-1206 410-1410 860-0020 925-0066 699-0031 590-0032 517-0030 590-0050 420-1006 610-0011 815-0086 805-0031 610-4104
6&1I0(_-0fl1t.0'4'r,
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Page 0337 of 0730
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Page 0338 of 0730
Apple Computer Inc · 1982
PRINTED 23-Jul-82 13:32 EFFECTIVITY DATE: ALL.
PARENT PART: 610-8156
LEVEL
5 5 5
4
5 6
5
o
5 6
5 6
5
6 5
6 5
6 5
6
5
6
5
6 5
6 5
6 5
6 5
6
5
6
5 6
5 6
5 6
5 6
5 6
5 6
5 6
5
COMPONENT PART NUMBER
050-0047 112-0102 306-0011 305-0011 306-0125 305-0125 304-0000 305-0000 306-0002 305-0002 306-0004 305-0004 306-0005 305-0005 306-0008 305-0006 308-0010 307-0010 306-0020 305-0020 306-0021 305-0021 306-0032 305-0032 306-0051 305-0051 306-0074 305-0074 306-0006 305-0066 306-0138 305-0138 306-0126 305-0*26 306-0153 305-0153 306-0157 305-0157 306-0161 305-0161 306-0174 305-0174 306-0139 305-0139 306-0244 305-0244 306-0251 305-0251 306-0257
.PERSQNAL COMPER SYSTEMB
-
INDENTED BILLS OF MATERIAL
BIL VERSION 29-Mar-79 PAOE 6
INACT. FO. 256K APPLE III ERC: B SRCE CODE: A TYPE: *
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007 18-Jan-92
4
442 15-Jul-81
1
007 19-Jan-62
1
442 15-Jul-81
2
807 18-Jan-82
2
442 15-Jul-91
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807 10-Jan-82
t
442 15-Jul-91
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1
442 15-Jul-01
3
907 lB-Jan-82
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple Computer Inc · 1982
PDF compression, OCR, web optimization using a watermarked evaluation copy of CVISION PDFCompressor
PRINTED 23-JuI--82 13:32 EFFECTIVITYDATE: ALL
.__PERBONAL COIIPUTER SYSTEMS
INDENTED BILLS OF MATER IAL
811 VERSION 29-Mar-79 PACE 7
PARENT PART: 610-8156
INACT. FO. 25611 APPLE III ERC: B BRCE CODE: A TYPE: e
UM; EA PROD CODE:
ECN: Allô ASSEMBLY OFI':
I
ABC: A PLAN CODE: U DATE: 08-Jul-82
LEVEL
COMPONENT PART NUMBER
E PART DESCRIPTION -
R
PR B T $ A P CD C V P B L UN
EXTENDED ECN
OTV PER
C140
START
DATE
B/N
CLOSE
DATE
8/N
I-.
io-
5
306-0203
â
305-0283
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306-0323
6
305-0323
5
306-0374
6
305-0374
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306-0399
6
305-0399
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308-0074
6
307-0074
5
308-0086
6
307-0086
5
300-0151
6
307-0151
5
308-0153
6 - 307-0153
5
308-0175
6
307-0175
5
308-0195
6
307-0195
5
309-0257
6
307-0257
5
342-0032
6
341-0032
5
302-0166
6
301-0166
5
369-6502
6
368-6502
5
354-0390
6
353-0380
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342-0030
6
341-0030
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342-0031
6
341-0031
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338-6522
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337-6522
5
338-0002
6
337-0002
5
316-8304
6
315-8304
5
330-0556
6
329-0554
5
302-9334
6
301-9334
6
301-0259
5
360-1489
6
359-1488
5
356-9708
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355-9700
.11-1,_i p...,
A IC. 74L9293, TESTED & BURNED-IN
A a C P EA
A IC. 74L6283
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A IC. 74L9323. TEBTED.II BURNED-IN.
A * C P EA
A IC. 7418323
RI P 1 P B P EA
A IC. 74L6374. TESTED Si BURNED-ZN
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A IC, 7418399. TESTED Si BURNED-IN A IC. 7416399
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A IC. 745151. TESTED Si BURNED-IN
A IC. 746151
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A IC. 749175. TESTED Si BURNED-IN
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A * C P EA RI P 1 P B P EA
A IC. 749195. TESTED Si BURNED-IN
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A IC. 748195 OR 93600
RI P 1 P B P EA
A IC. 749257. TESTED Si BURNED-IN
A a C P EA
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RL P 1 P B P EA
A IC VIDEO CONTROL TOT I. BRN IN
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A IC. 74166. TESTED Si BURNED-IN
A IC. 74166
A e C P EA RI P 1 P B P EA
8 IC MICRO 65028 311HZ TESTSiBURN-IN
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A IC 111390 AUDIO PUR NIP T8T L 88M IN A e C P EA
0 IC. L11380 AUDIO POWER AMPLIFIER
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MA IC ROIl SYNCI-S0II WITH BURN-IN
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MA IC, ROIl BOOT WITH BURN-IN
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Page 0339 of 0730
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple Computer Inc · 1982
PDF compression, OCR, web optimization using a watermarked evaluation copy of CVISION PDFCompressor
PRINTED 23-Jul-02 13:33 EFFECTIVITY DATE: ALL
..PERBQNALCOIVUTER SYSTEMS
INDENTED lILLO O F MATER IAL
DIL VERSION 29-Mar-79 PAGE B
PARENT PART: 610-8156
INACT. FG. 256K APPLE III ERC: B ORCE CODE; A TYPE: *
Uil: EA PROD CODE:
ECPI: Allô ASSEMBLY (flY:
ABC: A PLAN CODE: U DATE: 06-Jul-82
LEVEL
6 5
5 5 5 5 5
6 7
5
6 5
6
5 S 5 5 5 5 5 5 5 5 5 5 5 5
5 5 5 5
5 5 5 5 5 5 5 5 5 5 5 5 5 S 5 5 5 5
COIPONEP.iT
PART PUISER
359-1409 372-3904 111-0003 111-0025 135-9*01 151-5501 342-0020 341-0028 335-0471 334-0005 334-2*14 306-0133 305-0133 820-0043 101-4112 101-4104 126-5102 197-0001 10*-4102 126-4102 101-4225 131-5401 372-4259 101-4335 *97-0004 101-4302 *01-4470 101-4474 101-4473 515-0053 371-4148 519-0011 519-0030 515-0001 515-0002 519-0014 519-0016 519-0017 155-5*02 519-0018 378-0001 511-1401 511-1601 5*1-1801 51*-2001 5*1-2401 511-2001 511-4001 342-0056
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PP PIPCPEA
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449 10-Aug-81 CO26 18-Jan-02 426 18-Jan-02 923 *8-Jan-82 433 19-Jan-82 479 10-Jan-82 831 10-Jan-82 454 10-Aug-81
877 18-Jan-92
449 31-Au-0i
007 10-Jan-82 442 15-Jul-81 503 19-Jan-02
26 18-Jan-82 426 18-Jan-92 426 18-Jan-92 487 I 8-Jan-92 426 18-Jan-82 426 18-Jan-92 426 1$-Jan-02 426 18-Jan-92 CO26 LB-Jan-82 426 18-Jan-02 449 18-Jan-82 426 18Jan-82 426 18-Jan-82 426 18-Jan-92 426 18-Jan-92 532 18-Jan-92 731 10-Jan-02 467 18-Jan-82 725 18-Jan-82 784 18-Jan-82 467 18-Jan-82 467 18-Jan-82 523 18-Jan-82 523 18-Jan-82 DC44 18-Jan-82 467 16-Jan-02 DC53 18-Jan-82 799 18-Jan-82 799 lB-Jan-82 799 16-Jan-82 799 18-Jan-82 799 18-Jan-82 799 10-Jan-82 799 16-Jan-82 831 18-Jan-82
CLOSE
DATE
S/N
Page 0340 of 0730
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Page 0341 of 0730
Apple Computer Inc · 1982
PRINTED 23-Jul-82 13:34 EFFECTIVITY DATE: ALL
PARENT PART 610-8156
LEVEL
7 5
6
7 5
6 7
5
a 7
5
6
7 5 5 5
6
5 5 5 5 5 5 5 5 5 5
6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5
COMPONENT PART NiMBER
335-0003 342-0043 341-0043 335-000] 342-0045 341-0045 335-0003 342-0046 341-0046 335-0003 342-0055 341-0055 335-0003 513-5002 515-0103 306-0260 305-0260 131-5101 126-6404 151-5101 132-6401 372-3906 101-4750 101-4152 101-4682 519-0032 306-0132 305-0132 375-0005 111-0018 111-0017 101-4330 101-4101 111-0014 101-4472 101-4153 101-4241 101-4105 101-4301 101-4471 125-5401 511-0801 132-6101 101-4181 119-2101 101-4125 133-2401 138-0002
Ut-0019
PERS0NAL COMPUTER SYSTEMS
-
.
INDENTED BILLS 0F PlATER IAL
UIL VERSION 29-Mar-79 PAGE 9
INACT.FQ.25&K APPLE III ERC: B SRCE CODE: A TYPE:
E PART DESCRIPTION R
UM: EA PROD CODE:
ECN: *116 ASSEMBLY 01V:
1
ABC: A PLAN CODE: U DATE: 08-Jul-02
PR B T B A P
CDCYPBLUPI
EXTENDED ECN
START
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S/N
CLOSE
DATE
S/N
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A RES 1/4W 5% 100 OHM
RP P 1 P C P EA
O RES ARRAY 9 X 1k OHM
PP P 1 P C P EA
A RES 1/4W 5% 4.7K OHM
RP P 1 P C P EA
A RES 1/4W 5V. 15k OHM
PP P 1 P C P EA
A RES 1/4W 5% 240 0H11
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A RES. 1/4W 5% IM 0H11
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A RES. 1/4W 5V. 300 OHM
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426 18-Jan-82
2
426 18-Jan-82
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426 18-Jan-82
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4
426 18-Jan-82
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426 18-Jan-82
2
426 18-Jan-82
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426 18-Jan-82
3
426 18-Jan-82
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433 18-Jan-82
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1t88--JJann--8822
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple Computer Inc · 1982
PDF compression, OCR, web optimization using a watermarked evaluation copy of CVISION PDFCompressor
PRINTED 23-Jul-82 13:34 EFFECTIVITY DATE: ALL
-. PERSONAL CO1JTER SYSTEMS
INDENTED P ILLS DF MATER IAL
BIL VERSION 29-Mar-79 PAGE 10
PARENT PART: 610-8156
INACT. FG. 256K APPLE Ìll ERC: P ORCE CODE: A TYPE: a
UM: EA PROD CODE:
ECN: AlIO ASSEMBLY OTY:
ABC: A PLAN CODE: U DATE: 08-Jul-82
LEVEL
COMPONENT PART NUMBER
E PART DESCRIPTION
R
PCRDSCTYP8 DALPUM
EXTENDED ECN
START
OTYPER CHO DATE
S/N
CLOSE
DATE
S/N
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0 5
6 5 S 5 5 5 5 5 5 5 5 5 5 5 5
6 5 5
6 5
4 5 5 5 5 3 3
4
3 3
3 3 3
4 5 6 6 8
6 6 6 6 4
307-0374 308-0000 307-0000 342-0035 341-0035 III-0001 13*-5701 112-0001 376-0001 119-2701 lOt-4103 101-4270 101-4121 750-0006 562-2405 101-4432 111-0006 831-0100 306-0014 305-0014 136-3101 342-0061 '341-0061 342-0063 341-0063 825-0233 942-0197 875-0005 126-6402 610-4256 805-0099 060-0010 865-0007 830-0019 000-0001 865-0006 825-0207 825-0312 610-5103 610-4103 610-0103 820-0025
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705-0009 515-0014 705-0011 705-0012 705-0004 610-0197
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426 18-Jan--82
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PP P 1 P C P EA
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20-Jan-92 21 -Jan b 21-Jan--82 21-Jan-92 21-Jan-92 21-Jan-02 21-Jan-82 21-Jan-02 21-Jan-82 21 -Jan-82 21-Jan-82
Page 0342 of 0730
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Page 0343 of 0730
Apple Computer Inc · 1982
PRINTED 23-JuL-02 13:35 EFFECTEVITYDATE: ALL
PARENT PART: 610-0156
LEVEL
5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 9 5 5 9 5 9
C
COMPONENT PART NUMBER
915-0089 815-0089 815-0090 015-0091 815-0092 815-0093 815-0094 815-0095 815-0096 815-0097 915-0098 815-0099 815-0100 915-0101 815-0102 815-0103 815-0104 815-0105 815-0106 815-0107 815-0100 815-0109 815-0110 815-0111 815-0112 815-0113
81-0114
815-0115 815-0116 815-0117 815-011a 815-0119 815-0120 815-0121 815-0122 815-0123 015-0124 815-0125 815-0126 815-0127 815-0128 815-0129 015-0130 815-0131 815-0132 819-0133 815-0134 815-0135
Ofli,S_-f011f3l6,
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.PERSONALC0MPUTER SYSTEMS
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. . e-s
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
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Page 0344 of 0730
Apple Computer Inc · 1982
-
I-.
PRINTED 23-Jut-82.13;36 EFFECTIVITY DATE: ALL
PERMLCuTER.UY6TEM9.. - . ......
INDENTED BILLS OF MATERIAL
IlL VERSION 29-Mir-79 PACE 12
PARENT PART: 610-8156
LEVEL
5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 S 5 5 5 5 5 5 S 5 5 5
5
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015-0138 815-0139 815-0140 815-0141 915-0142
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A024 26-Apr-82 816 26-Apr-82 6024 26-Apr-82 A024 26-Apr-82 6024 26-Apr-82
CLOSE
DATE
S/N
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple Computer Inc · 1982
PDF compression, OCR, web optimization using a watermarked evaluation copy of CVISION PDFCompressor
PRINTED 23-Jul-82 13:37 EFFECTIVITY DATE: ALL
..___PER80NALCOPUTER SYSTEMS
.
INDENTED BILLU OF MATERIAL
. BIL VERSION 29-Mar-79 PAGE 13
PARENT PART: 610-8156
INACT. F0. 25641 APPLE III ERC: B BRCE CODE: A TYPE: *
UM: EA PROD CODE:
ECH: A116 ASSEMBLY CITY.
I
ABC: A PLAN CODE: U DATE: 08-Jul-02
LEVEL
COMPONENT
PART NIJIIBER
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II
PR B T S A P
EXTENDED ECN
START
CD C Y P B L UM - (flY PER
CIlO DATE
8/N
CLUSE
DATE
S/N
5
610-0106
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A091 18-Jan-92
6
610-OIOÓD
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112-0102
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Page 0345 of 0730
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple Computer Inc · 1982
PDF compression, OCR, web optimization using a watermarked evaluation copy of CVISION PDFCompressor
PRINTED 23-Jul-82 13:38 EFFECTIVITY DATE: ALL.
PER?QL CDMPUTER SYSTEMS
INDENTED BILLS 0F HATER IAL
OIL VERSION 29-Mar-79 PAQE 14
PARENT PART: 610-0156
INACT.F0.256K APPLE III
3Jl:EA
-
PROD CODE:
ECN: Allá ASSEMBLY OTY:
t
ERC: B BOCE CQDE A TYPE: e
ABC: A PLAN CODE: U DATE: 08-Jul-82
LEVEL
6 7
6 7
6 7
6 7
6
7
6
7
6 7
6 7
6 7
6
7
6
7
6
7
6 7
6 7
6 7
6 7
6
7 6
7 6
7
6
7
6 7
6
7
6 7 7
6 7
COMPONENT PART NUMBER
306-0257 305-0257 306-0283 305-0293 306-0323 305-0323 306-0374 305-0374 306-0399 305-0399 309-0074 307-0074 308-0086 307-0086 308-0151 307-0*51 308-0153 307-0*53 309-0175 307-0175 300-0195 307-0195 308-0257 307-0257 342-0032 34*-0032 302-0166 301-0166 369-6502 368-6502 354-0380 353-0390 342-0030 341-0030 342-0031 341-0031 338-6522 337-6522 338-0002 337-0002 3*6-8304 315-8304 330-0556 329-0556 302-9334 301-9334 301-0259 360-1488 359-1488
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Page 0346 of 0730
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple Computer Inc · 1982
PDF compression, OCR, web optimization using a watermarked evaluation copy of CVISION PDFCompressor
._PRINTED 23-Jul-82_13:39
EFFECTIVITY DATE: ALL PARENT PART: 610-0156
pFRRflI4ALCCFutER_ SYSTEMS
-_.-81L VERSION 29-Mar-79 PAQE 15
INDE-N- IRD BILLS OF MATERIAL
INACT. F0. 256K APPLE III ERC: B ORCE CODE: A TYPE: *
tRI: EA PROD CODE:
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1
ABC: A PLAN CODE: U DATE: 08-Jul-92
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355-9709
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340-1489
7
359-1489
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111-0003
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111-0025
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135-9101
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151-550*
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342-0028
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341-0020
8 335-0471
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334-0005
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334-2114
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306-0133
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305-0133
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820-0043
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101-4112
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101-4104
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126-5102
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197-0001
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6
126-4102
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101-4225
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131-5401
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372-4250
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101-4335
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Page 0347 of 0730
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple Computer Inc · 1982
PDF compression, OCR, web optimization using a watermarked evaluation copy of CVISION PDFCompressor
PRINTED 23-Jul-82 *3:39 EFFECTIVITY DATE: ALL.
PER 90MAL COMPUTER 8YSTEMS
INDENTED ILLB OF MATERIAL
Bu. VERSION 29-Mur-79 PAQE 16
PARENT PART: 610-8156
LEVEL
6 7 8
6 7
8 o
7
8 o
7
8 6
7
8 6 6 6
7 6
6 0 6 6 6 6 6 6 6
7 6 6 6 6 6 6 6 o 6 6 6 6 6 6 6 6 6 6 6
COMPONENT PART NUMBER
342-0056 341-0056 335-0003 342-0043 341-0043 335-0003 342-0045 341-0045 335-0003 342-0046 341-0046 335-0003 342-0055 341-0055 335-0003 513-5002 515-0103 306-0260 305-0260 131-5101 *26-0404 *51-5101 *32-6401 372-3906 101-4750 *01-4152 101-4682 5*9-0032 306-0132 305-0132 375-0005 111-0018 111-0017 101-4330 101-4101 111-0014 101-4472 101-4153 101-4241 101-4105 101-4301 101-4471 125-5401 511-0801 132-6101 101-4181 119-2101 101-4125
1I 3,f3l -2's4,\0.;1n
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UM: EA PROD CODE: ABC: A PLA1I CODE: U
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426 18-Jan-82
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426 18-Jan-82
3
426 18-Jan-82
3
426 10-Jan-92
1
433 18-Jan-82
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43 1I n8-JIan- -n8.2,
Page 0348 of 0730
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple Computer Inc · 1982
PDF compression, OCR, web optimization using a watermarked evaluation copy of CVISION PDFCompressor
PRINTED 23-Jul-82 1339
EFFECTIVITY DATE: ALL
PEfiOMLQlUTER,, SYSTEMS
INDENTED 0 1118 0F MATE RIAL
SIL VERSION 29-Mar-79 PACE 17
PARENT PART: 610-8156
INACT. FO. 250K APPLE III ERC: B ORCE C011E: A TYPE:
UM: EA PROD CODE:
ECN: AlIO ASSEMBLY OTY:
1
ABC: A PLAN CODE: U DATE: 06-Jul -B2
LEVEL
COMPONENT
PART NiMBER
E PART DESCRIPTION
R
PR S T S A P CD C Y P 8 L IM
EXTENDED ECN
START
OTY PER
CHO DATE
8/N
CLOSE
DATE
SIN
6
6
7
6
7
6
7 6 6 6 6 6 6 6 6 6 6 6 6 6 6
7
6 o
7
6 7
6 6 6 6 4 4 4
5 4
4 3 3 3
4 4 2 3
3
3
3
3 2
111-0019 308-0374 307-0374 308-0000 307-0000
342-0035 341-0035
111-0001
131-5701 112-0001 376-0001 1*9-2701 101-4*03 101-4270 101-4*21 750-0006 562-2405 101-4432 111-0006 831-0100 306-00*4 305-0014' 136-3101 342-0061 341-0061 342-0063 341-0063 825-0233 942-0197 875-0005 126-6402 610-4256 865-0007 805-0099 860-0018 410-1410 860-0102 830-0031 420-1001 610-5197 825-0054 825-0066 590-0029 520-0020 515-0023 590-0070 515-0022 520-0030 942-0047
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Page 0349 of 0730
PDF compression, OCR, web optimization using a watermarked evaluation copy of CVISION PDFCompressor
Page 0350 of 0730
Apple Computer Inc · 1982
PRINTED 23-Jul-82 13:40 EFFECTIVITY DATE: ALL
PARENT PART: 610-8156
LEVEL
2 2 2
2 a
COPUONENT PART P&SMBER
942-0079 946-0009 946-0005 030-024 I 944-0059
END OF REPORT
_3ERRONALCuIWVTER SYSTEMS
INDENTED IILL OF MATERIAL
BIL VERSION 29-Mar-79 PACE 10
ÍNACT.FØ,25o1(APP[ïjjt
ERC: B ORCE CODE: A TYPE: a
liN: EA PROD CODE:
ECN: A1I6 ASSEMULY 01V:
1
ABC: A PLAN CODE: I) DATE: 08-Jul-82
E PART DESCRIPTION
R
PR 9 T 9 A P
CDCYPBLUN
EXTENDED ECN
START
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CLOSE
DATE
S/N
B INACT.90X,FO APPLE III SYSTEM A TAPE. BEALDI0 01-ASS WEB *341 A3 A TAPE. 3M *218 3/4" WIDE A CUSTOMER LETTER. A] CLOCK CHIP O BAS. POLY. Nih-STATIC. 24X34
EX X 7P C P EA
EX X 7P B P RL
ap. EX X I PC P RL
X
P EA
EX X 7P C P EA
I
A116 19-Jan-82
0. 0100 474 19-Jan-92
0. 0050 C*45 18-Jan-82
I
19-Jan-82
a
442 26-Apr-82
08-Jul-02 08-Jul-92 08-Jul-02 26-Apr-02
08-Ju 1-02
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple /// Computer Information
Apple ///
Service Reference Manual
Section II of Il Servicing Information
Chapter-is . Wire List
Written by Apple Computer. 1982
Apple Computer Inc · 1982
Page 0351 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
mp u
I/I THE APPLE
WIRE LIST
The following list is to be used for finding circuit components which are connected to each other.
INTEPRETING WIRE LIST NOMENCLATURE
Schematic Page Nuither (Add i to this nuther)
Part Description
I
Type
C''6
2Otf
2
ALÌLECT
/
Part Reference Designator
Ner'of Pins
1412
Loition
I/I This wire list has schematic page nuithers for the old Apple
Schematic.
Please add i to the schematic page nuther for the correct page.
15.1
Apple Computer Inc · 1982
Page 0352 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
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,
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I
Z
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Z
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Z-fl
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Z
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1-Z3
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Z
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t-LD
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Apple Computer Inc · 1982
Page 0353 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
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i
TCAP
C15-1 U105-4
2
GND
C16 8 47P 2 ER H14
i
C16-I U1Ol-1
2
U107-2 C16-2 R47-2
Cil 8 .1U 2 MON Ml
i
U96-13 U96-12 U96-8 P.40-2
X3-1 C75-i
2
U164-6 Cil-2 X5-2 C75-2
X2-1
C18-1
Cil-i
C18 8 .OSU 2 cER M8
i
U96-i3 U96-i2
X3-i C75-1
2
CND
U96-8
P.40-2
X2-I
C18-i
Cil-I
C20 8 .1U 2 MON
i
UPRST*
C20-I Ul13-6
2
GND
U113-2 P.44-2 X4-2
C6-1
C21 8 .LU 2 MON AS
i
U113-8
2
GND
R46-2
1.1113-12
C21-I
C22 8 .1U 2 MON C12
i
U107-31
2
CND
C22-1
C23 9 .1.0 2 MON B14
i
Q1O-2
2
GND
P.90-2
P.91-i
C23-i
R49-1
C25 I .IU 2 MON P47
i
+5ff
2
GNDF
C26 i .IU 2 MON
i
-5ff
-
2
CNDF
C27 i .1U 2 MON Mli
I
+12ff
2
CNDP
7/ 2FV
C28 i .111 2 NON MiO
i
-12ff
2
CNDF
- ÍZ
C29 i .111 2 MON J2
15.3
Apple Computer Inc · 1982
Page 0354 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
1
+12V
2
GND
C30 1 .IU Z MON J2
1
+5v
2
GND
C31 1 .1U 2 MON Kl
1
+12V
2
CND
C32 i .1U 2 MON K2
1
+12v
2
CND
C33 i .1U 2 MON K4
1
+12v
2
GND
C34 i .iU 2 MON K6
1
+12V
2
GND
C35 i .1U 2 MON Ml
L
-12V
2
GND
C36 i .1U 2 MON Ml
1
-5V
2
GND
C37 i .ITJ 2 MON A2
1
+5V
2
GND
C38 i .1U 2 MON KS
1
+5v
2
GND
C39 i .1U 2 MON KlO
1
+5v
2
GIlD
C40 i .1U 2 MON K12
1
+5V
2
GIlD
C41 L .iU 2 MON M6
1
-12v
2
GIlD
C42 i .ltJ 2 MON CL.
15 4
4,
Apple Computer Inc · 1982
Page 0355 of 0730
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pIa - m
i
+3V
2
GND
C43 i .113 2 MON G12
1
+5V
2
GND
C44 1 .113 2 MON C12
1
+5v
2
GND
C45 i .1U 2 MON F,
1
+5v
2
CND
C46 1 .113 2 MON Al2
i
+3V
2
GND
C47 i .111 2 MON E14
i
+5v
2
GND
C48 1 .1U 2 MON M6
1
-5v
2
GND
C5O 1 .113 2 MON Dl
i
+5v
2
GND
C51 1 .113 2 MON 38
1
+5V
2
GND
C52 i .113 2 MON A6
1
+3V
2
CND
C53 i .IU 2 MON £4
1
+5v
2
CND
C54 1 .113 2 MON D4
i
+5v
2
GND
C35 t .113 2 MON C2
1
+5V
2
GND
C56 i .IU 2 MON 310
15.5
Apple Computer Inc · 1982
Page 0356 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Øippkz comp.tur
n
1
+5v
2
GND
C57 i .1U 2 MON B12
1
+5V
2
GND
C58 i .IU 2 MON AlO
i
+5v
2
CND
C59 9 lOP 2 CER A8
i
CS6522
R68-2 U73-21,
2
GND
C59-1
U97-24
C60 i 220U 2 AL-ELECT Nil
+5FV
2
GNDF
C61 i 220U 2 AL-ELECT N7
i
GNDF
2
-STy
C62 i 220U 2 AL-ELECT NU
i
+12FV
2
CNDF
C63 i 220U 2 AL-ELECT M10
1
CNDF
2
-12FV
C64 i .1U 2 MON F14
i
+5v
2
GND
C65 i .1U 2 MON A4
1
+5v
2
CND
C66 i 220P 2 ER MS
i
R96-2 C66-1
2
GND
C67 i 22OP2CERL.1
i
R93-2 C67-I
2
GND
C68 i 220P 2 CER Li
I
R94-2 C68-1
2
GND
15.6
Apple Computer Inc · 1982
Page 0357 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual /
693 ¿ LII' Z NOW 9V
t
AÇ+
Z
Z-693
Z-ÇL 1-181(1 Z-lSifl
OLD L 1U Z NOW BY
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Z-LL
Z
UND
9-191(1
Zt-t9Ifl
I-OLD
TLD 8 fit Z .L3312 tW
I
ZT-6CIfl
Z
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UND
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I
Z-O0flI 1-LD TT-(1
Z
UND
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I
Ct-96fi Zt-96fl 9-96(1 Z-0w
1-CX T-SLD
Z
9-9ifl Z-LTD Z-ÇX Z-SLD
t-ZX
t-913
t-LTD
9L3 ¿ LIP Z NOW 8W
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9-cOin Z-LCB
Z
UND
T-BC T-9L3
LL3 t JOZZ z 'iaD ¡'J
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Z-c6
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UND
t-LLD
8L3 L ¿001 Z 3
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1-8L3 UND
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Apple Computer Inc · 1982
Page 0358 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
t *ça - r1
36-4 U167-9 31-4
5
GNDF
6
DP112
36-6 U166-8 31-6
7
GNDF
8
DPH3
J6-8 U167-8 31-8
9
-12FV
10
WRREQ
36-10 11166-.7 31-10
11
+5FV
12
+3FV
13
+12FV
14
ENBLI.E*
31-14 Ul66-5
15
+12FV
16
R3DAA
36-16 U166-4 31-16
17
+12FV
18
WRDATA
36-18 U166-3 Jl-18
19
+I2FV
20
WRPROT
36-20 U167-% 31-20
21
£NBL3.E*
31-21 t1166-2
22
ENBL2.E*
J1-22 U167-t
2)
All*
U167-5 31-23 36-23
24
SDE2/1
36-24 U167-;' 31-24
25
NO C0NNECTI0r
26
EXT*
31-26 U167-2
32 1 9PIN 9 9D
1
2 3
4
5
6 7 8
9
CNDF +5FV CNDF
X0 U169-9 32-4
SW2 U169-7 32-5 +12FV CNDF Yo U169-6 32-8
SUO
U16-8 32-9
33 1 9P1N 9 9D
15.8
Apple Computer Inc · 1982
Page 0359 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
pp-I
i
CNDF
2
+5FV
3
GNDF
4
Xi/ SER
.13-4 17169-3
5
SW1/MGNSW
.13-5 U169-2
6
+ 12FV
7
CNDF
8
Y1IxCO
.13-8 (7169-4
9
SW3/SCO
J3.-9 (7169-5
.14 1 25P1N 25 25D
I
GNDF
Z
TXD
J4-2 U172-9
3
DATA IN
.14-3 U172-8
4
RTS
.14-4 17172-7
5
CTS
J4-5 U172-6
6
DSR
.14-6 17172-5
7
01W?
8
DCD
.14-8 17172-3
9
No CONNECTION
10
NO CONNECTION
11
NO CONNECTION
12
NO CONNECTION
13
NO CONNECTION
14
NO CONNECTION
15
NO CONNECTION
16
NO CONNECTION
17
NO CONNECTION
18
NO CONNECTION
19
NO CONNECTION
20
DTR
.14-20 U172-4
21
NO CONNECTION
22
NO CONNECTION
23
MO CONNECTION
24
NO CONNECTION
25
NO CONNECTION
.15 1 ISPIN 15 15D
I
GNDF
2
XRCB4
.15-2 P17-3
PIS-3
15.9
Apple Computer Inc · 1982
Page 0360 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
pcompt*a
3
t3YNC
J5-3 P17-9 P18-6
4
PDLNT*
35-4 U72-14
S
XRGB1
35-3 Pli-7 P18-S
6
GNDF
7
-57V
8
+127V
9
XRGB2
J5-9 P17-S P18-4
10
XRGB8
35-10 P17-i P18-2
11
B&WVID
35-11 RIS-2 310-1 P18-7
12
NTSC
35-12 RiZ-2 P18-8
13
GNDF
14
-127V
15
+57V
J6 i 26P1N 26 RI3BON
i
GNDF
2
DPHO
J6-2 Ui66-9 31-2
3
GNDP
4
DPH1
36-4 13167-9 31-4
5
CNDF
6
DPH2
36-6 U166-8 Ji-6
7
CNDP
8
DPH3
J6-8 13167-8 J1-8
9
-127V
10
WRREQ
J6-lO 13166-7 Ji-lo
11
+57V
12
+57v
13
+127v
14
ENBL1.t*
36-14 U166-6
15
+127V
16
RDDATA
36-16 13166-4 31-16
17
+I2FV
18
WRDAIA
36-18 U166-3 31-18
19
+127V
20
WRPROT
J6-20 13167-4 J1-20
21
NO CONNECTION
-ø)
15.10
I
Apple Computer Inc · 1982
Page 0361 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
"s
ampLt
22
NO CONNECTION
23
AII*
(J167-5 J1-23 .16-23
24
SXDE2/1
36-24 TJ167-7 31-24
25
NO CONNECTION
26
INT*
36-26 11167-3
Ji i 26P1N 26 RIBBON
i
r.? O
37-1 U107-17
2
ICYL
J7-2 U107-18
3
KVCC
37-3 Q9-2
4
KY 2
37-4 TJ107-19
5
APPLEII*
37-5 PlI-5 11106-12 11164-5
6
KY3
37-6 U107-20
7
APPLE1*
37-7 Pli-4 11111-3
8
KY4
.17-8 11107-21
9
CAPLCK*
37-9 Pli-3 U109-13
10
KY5
37-10 U107-22
11
CONTROL*
J7-1l 11179-13 11107-23 U109-1O Pli-2
12
KY8
37-12 11107-25
13
GNDF
14
10(0
37-14 11171-9
15
1RES!T*
11139-12 R80-i C71-1 11179-15 37-15
16
10(2
37-16 U171-8
17
1(X7
37-17 11171-7
18
KXI
37-13 11171-6
19
KX5
.17-19 11171-5
20
10(3
J7-20 11171-4
21
KX4
J7-21 U171-3
22
KY9
15.11
Apple Computer Inc · 1982
Page 0362 of 0730
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ppcompm
.17-22 U107-26
23
1C'f6
.17-23 11107-23
24
SHIFT*
.17-24 Pli-6 U107-29
25
KY7
.17-25 11107-24
26
KX6
.17-26 U171-2
.18 1 lOPIN lo PWR Cl
1
-12v
2
CND
3
CND
4
GND
5
ONO
6
-5v
7
+5v
8
+5v
9
+12V
lo
+12v
.19 1 2PIN 2 MOLEX Mli
1
AUDIO
.19-1 R69-1
2
+5v
JiO 1 2PIN 3 RCA
i
8&WVID
.15-11 RIS-2
2
CNDF
3
CNDF
.110-1
P18-7
Jil i 3PIN 3 MINPHONE
1
EXTSPK1
Jll-1 R34-1
2
EXTSPK2
.111-2 11172-2
3
CNDF
J12 i 5OPIN 50 EDO
i
IOSELI*
U74-14 .112-1
2
AO
.115-2 .114-2 .113-2 J12-2 112-6 1197-38 1198-13
U101-li 1194-13 1173-38 U75-13 U63-18 U177-13
3
AI
.115-3 .114-3 .113-3 .112-3 112-10 1197-37 U98-14
U101-lO 11177-1 1194-1 U73-37 U75-1 1163-16
4
A2
.115-4 J14-4 .113-4 .112-4 US-6 11101-9 1197-36 U177-2 U94-2 1175-2 1173-36 U63-14
15.12
Apple Computer Inc · 1982
Page 0363 of 0730
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ppkzconxtarm
5
A3
315-5 314-S J13-5 J12-5 U5-10 11109-1 Ulli-i
1197-35 13177-3 1194-3 1175-3 1173-35 1163-12
6
M
315-6 314-6 313-6 312-6 U9-6 1177-1 1176-1
U112-2 U63-9
7
AS
315-7 314-7 313-7 312-7 119-10 1176-2 1177-2
11112-3 1163-7
8
A6
315-8 J14-8 313-8 312-8 132-4 1.777-3 U76-3
1371-10 U63-5 Uil-li
9
Al
315-9 314-9 313-9 312-9 U13-l0 1177-4 1176-6
Uil-i 1163-3
10
AB
315-10 314-10 313-10 312-10 U67-4 1174-1 1171-6
112-12 1113-6 1113-4
il
A9
315-11 J14-11 J13-11 312-Il US-4 1174-2 1171-S
1167-7
12
AlO
315-12 314-12 313-12 J12-12 U128-1 1174-3 1171-4
1167-9
13
All
315-13 314-13 313-13 312-13 11128-12 116-6 1171-3
11150-13 U74-5 1167-12 113-5 11174-5
14
Al2
315-14 314-14 313-14 J12-l4 U9-12 13155-11 11165-14
1370-4 1371-2 U174-6
15
A13
315-15 314-15 313-15 J12-15 1.7128-4 13155-12 U165-15
1171-1 1170-7 116-5 U3-6 11174-7
16
A14
315-16 314-16 313-16 312-16 113-7 11147-4 1370-9
116-16 11174-4
17
AiS
315-17 314-17 313-17 312-17 U3-4 U147-3 1170-12
11174-16 116-7
18
R/W*
315-18 314-18 313-18 312-18 133-3 11136-9 U180-17 U176-6 13165-11 11160-11
19
PHD
A/I
313-19 13136-11 J14-19 313-19 312-19 U124-5 1365-37
R96-1
20
IOSTRB*
315-20 11150-12 J14-20 J13-20 J12-20
21
RDY
315-21 11164-8 314-21 313-21 312-21 P14-4 U65-2
22
TSADB*
315-22 312-22 314-22 J13-22 U163-3 P14-3
23
SPARE2
15.13
Apple Computer Inc · 1982
Page 0364 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
4a compt ix.
24 25 26 27 28
29 30 31
-- 32
33 34 35 36
37
38 39 40
41 42
43
44
45
46
315-23 .112-23 .114-23 J13-23 SPARE1
J15-24 .112-24 314-24 313-24 +5V GND
DMAOK
U144-8 312-27 315-27 .114-27 .113-27 DMAI*
U176-2 312-28 J15-28 .114-28 313-28 tJ163-5 P14-2
¡J 153-9
IONML* 315-29 U97-17 314-29 J13-29 U139-13 312-29
IRQI* U101-14 312-30 P2-7 13148-1
tORESET* 312-31 313-31 J14-31 315-31 P14-6 ¡3164-2 U164-4 1396-4 U94-15
IN}L*
J15-32 314-32 .113-32 312-32 13176-4 13165-13 P14-S -12v -5v
SYNC
1365-7 1J136-1 315-35 13174-3 314-35 .113-35 312-35 C7M
315-36 314-36 313-36 312-36 13141-9 U119-2 U146-12
1390-14
Q3
314-37 1385-3 315-37 313-37 312-37 13117-12 R93-1
13154-2
PEEIM*
312-38 313-38 314-38 315-38 13123-6 R95-1 CO2X*
J15-39 1377-13 314-39 313-39 312-39 PRE1M
J12-40 313-40 314-40 J15-40 13119-12 U73-25 U123-5 U97-25 U139-1O &94-1
DEVSEL1* 312-41 1376-14
D7
315-42 314-42 313-42 J12-42 U68-12 316-24 13111-12 U101-5 U91-7 1369-12 P15-9
315-43 314-43 313-43 U91-13 U69-9 P15-8
05 315-44 314-44 313-44 1391-6 U69-7 P15-i
D4 315-45 314-45 313-45 1391-14 1369-4 P15-6
312-43 312-44 312-45
U68-13
1368-14 1368-15
316-23 316-22 316-21
U111-9
13111-7 ¡3111-4
315-46 314-46 313-46 J12-46 1368-16 316-20 ¡3109-12
15.14
Apple Computer Inc · 1982
Page 0365 of 0730
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pIamp
091-5 066-12 P15-S
47
DZ
315-47 314-47 313-47 312-47 068-17 316-19 0109-9
091-15 066-9 P15-4
48
Dl
315-48 314-48 313-48 312-48 068-18 316-13 U109-7
091-4 066-7 P15-3
49
00
J15-49 J14-49 313-49 312-49 U68-19 316-17 0109-4
U91-16 066-4 P15-2
50
+12V
313 1 SOPIN 50 LX
1
IOSEL2*
U74-13 313-1
2
AO
315-2 314-2 313-2 312-2 U2-6 097-38 U98-13 U101-Il 1J94-13 U73-38 075-13 063-18 0177-13
3
Al
315-3 314-3 313-3 J12-3 02-10 097-37 098-14
0101-10 0177-1 094-1 073-37 075-1 063-16
4
AZ
315-4 314-4 313-4 312-4 US-6 U101-9 097-36 0177-2 U94-2 075-2 073-36 063-14
5
A)
315-5 314-5 313-5 312-5 US-10 U109-1 0111-1
097-35 U177-3 094-3 075-3 073-35 U63-12
6
A4
315-6 314-6 313-6 312-6 U9-6 U77-1 U76-1 0112-2 U63-9
7
AS
315-7 314-7 313-7 312-7 U9-10 076-2 077-2
0112-3 063-7
8
M
ilS-8 314-8 313-8 312-8 U2-4 077-3 U76-3 lui-10 063-5 071-11
9
Al
315-9 314-9 313-9 312-9 U13-10 077-4 076-6 071-7 063-3
10
Aß
315-10 314-10 313-10 312-10 U67-4 074-1 U71-6 02-12 013-6 013-4
11
A9
315-11 314-11 313-11 312-11 US-4 U74-2 071-S 067-7
12
AlO
315-12 314-12 313-12 312-12 U128-1 074-3 071-4 U67-9
13
Alt
J15-13 314-13 313-13 J12-13 U128-12 06-6 071-3
0150-13 U74-5 067-12 03-5 U174-5
14
Al2
15.15
/
Apple Computer Inc · 1982
Page 0366 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
9pIa coput u
315-14 314-14 313-14 312-14 U9-12 13155-11 13165-14 U70-4 1371-2 U174-6
15
A13
315-15 314-15 313-15 J12-15 13128-4 U155-12 13165-15
Uil-i U70-7 136-5 133-6 U174-7
16
A14
315-16 314-16 313-16 312-16 133-7 13147-4 1370-9
136-16 13174-4
17
AIS
315-17 314-17 313-17 312-17 U3-4 13147-3 1370-12
U174-16 136-7
18
R/W*
315-18 314-18 313-18 J12-18 133-3 13136-9 U180-17
U 176-6 U165-11 Ut 60-11
19
PRO
J15-19 13136-11 314-19 313-19 312-19 U124-5 1365-37
R.96- i
20
LOSTR3*
315-20 13150-12 314-20 313-20 312-20
21
RDT
315-21 13164-8 314-21 313-21 312-21 P14-4 U65-2
22
TSADB*
315-22 312-22 314-22 313-22 U163-3 P14-3
23
SPARZ2
J15-23 312-23 314-23 JI 3-23
24
SPAREI
315-24 312-24 314-24 Ji 3-24
25
+5v
26
GND
27
DMA0
13144-8 ¿12-27 315-27 314-27 313-27
28
DMAI*
13176-2 312-28 315-28 J14-28 313-28 13163-5 P14-2
U 153-9
29
IONNI*
J15-29 U97-17 314-29 313-29 13139-13 312-29
30
IRQ2*
U101-IS 313-30 P2-6 13148-2
31
IORESET*
J12-31 313-31 314-31 315-31 P14-6 13164-2 13164-4
1396-4 1394-15
32
11411*
315-32 314-32 313-32 J12-32 13176-4 U165-13 P14-5
33
-12v
34
-5v
35
SYNC
1365-7 13136-1 315-35 U174-3 314-35 313-35 312-35
36
C7M
315-36 314-36 313-36 312-36 U141-9 13119-2 U146-12 U90-14
37
Q3
314-37 U85-3 315-37 313-37 312-37 13117-12 R93-1
15.16
Apple Computer Inc · 1982
Page 0367 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
*1pp-u
11154-2
38
PREIM*
312-38 313-38 314-38 315-38 11123-6 R95-1
39
CO2X*
315-39 1177-13 314-39 313-39 312-39
40
PRZLM
312-40 313-40 314-40 315-40 U119-12 1173-25 U123-5
U97-25 U139-10 R94-1
41
DEVSEL2*
313-41 1176-13
42
Dl
315-42 314-42 J13-42 312-42 1168-12 316-24 11111-12
11101-5 1191-7 U69-12 P15-9
43
D6
315-43 314-43 313-43 312-43 1168-13 316-23 11111-9
1191-13 1169-9 P15-8
44
D5
315-44 314-44 J13-44 312-44 1168-14 316-22 11111-7
1191-6 1169-7 P15-i
45
D4
315-45 314-45 313-45 312-45 U68-15 J16-21 11111-4
1191-14 U69-4 P15-6
46
D3
315-46 314-46 313-46 312-46 U68-16 316-20 11109-12
U91-5 U66-12 P15-5
47
D2
315-47 314-47 313-47 312-47 U68-1l 316-19 11109-9
U91-15 U66-9 P15-4
48
Dl
-
315-48 314-48 313-48 312-48 1168-13 316-18 11109-7
1191-4 1166-7 P15-3
49
DO
315-49 314-49 J13-49 312-49 1168-19 316-17 U109-4
1191-16 1166-4 P15-2
50
+12V
314 1 5OPIN 50 EDG
1
IOSEL3*
1174-12 314-1
2
AO
315-2 J14-2 313-2 J12-2 U2-6 1197-38 1198-13
U101-Il 1194-13 U73-38 U75-13 U63-18 U177-13
3
Al
315-3 314-3 313-3 312-3 U2-10 1197-37 1198-14
11101-10 U177-1 1194-1 1173-37 1175-1 U63-16
4
A2
J15-4 314-4 313-4 312-4 US-6 U1O1-9 1197-36
11177-2 1194-2 U75-2 1173-36 U63-14
5
113
J15-5 314-5 J13-5 312-5 US-10 11109-1 11111-1
U97-35 11177-3 1194-3 1175-3 U73-35 U63-12
6
A4
15.17
Apple Computer Inc · 1982
Page 0368 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
J15-6 314-6 J13-6 .112-6 119-6 1177-1 U76-1
1J112-2 1163-9
7
AS
J15-7 314-7 J13-7 J12-7 U9-10 1176-2 U77-2 (1112-3 U63-7
8
A6
JI. 5-8 314-8 313-8 312-8 U2-4 1177-3 (176-3
U71-10 U63-5 Uil-li
9
A7
Ji 5-9 314-9 J13-9 312-9 U13-10 (177-4 1176-6 (171-7 U63-3
10
AB
315-10 314-10 J13-i0 J12-1O 1167-4 U74-1 U71-6 U2-12 U13-6 1113-4
il
A9
JiS-li J14-11 313-11 312-11 US-4 1174-2 1171-5
1167-7
12
AlO
315-12 J14-12 313-12 312-12 U128-1 (174-3 U71-4 U67-9
13
All
315-13 314-13 J13-13 312-13 U128-12 116-6 U71-3
(1150-13 U74-5 U67-12 U3-5 U174-5
14
Al2
J15-14 314-14 .313-14 312-14 U9-12 11155-11 U165-14
1170-4 1171-2 11174-6
13
A13
315-13 314-15 313-15 J12-15 11128-4 U155-12 U165-15 Uil-i U70-7 116-5 U3-6 11174-7
16
A14
315-16 314-16 313-16 312-16 U3-7 U147-4 U70-9 116-16 U174-4
17
A15
313-17 314-17 313-17 312-17 U3-4 11147-3 1170-12 U174-16 (16-7
18
R/W*
315-18 314-18 313-18 312-18 U3-3 U136-9 U180-17
11176-6 U165-11 U160-il
19
F110
315-19 U136-11 J14-19 313-19 312-19 11124-5 (165-37 R96-1
20
IOSTRB*
31 5-20 U150-12 314-20 313-20 312-20
21
RD?
J15-21 11164-8 314-21 .113-21 312-21 P14-4 U65-2
22
TSADR*
315-22 J12-22 314-22 J13-22 11163-3 P14-3
23
SPARZ2
313-23 312-23 J14-23 313-23
24
SPARE1
315-24 312-24 314-24 313-24
25
+5V
15.18
/
Apple Computer Inc · 1982
Page 0369 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
*pêa compt*
26
CND
27
DMAOK
U144-8 312-27 315-27 314-27 313-27
28
DMAI*
11176-2 312-28 315-28 J14-28 313-28 U163-5 P14-2
UI 53-9
29
IOPThtI*
315-29 U97-17 314-29 313-29 U139-13 312-29
30
IRQ3*
U97-7 314-30 P2-4 U148-4
31
IORESET*
312-31 313-31 314-31 315-31 P14-6 U164-2 11164-4
U96-4 U94-15
32
INlt*
J15-32 314-32 313-32 312-32 U176-4 11165-13 P14-5
33
-12V
34
-5v
35
SYNC
U65-7 U136-1 315-35 U174-3 314-35 313-35 312-35
36
C7!1
315-36 314-36 313-36 312-36 11141-9 U119-2 U146-12
U90-14
37
Q3
J14-37 U85-3 315-37 J13-37 312-37 U117-12 R93-1
Ui 54-2
38
PRE1M*
312-38 313-38 314-38 315-38 U123-6 R95-1
39
CO2X*
J15-39 1177-13 J14-39 313-39 312-39
40
PRE1M
312-40 313-40 314-40 315-40 U119-12 U73-25 U123-5
1.197-25 11139-10 R94-1
41
DEVSEL3*
314-41 U76-12
42
07
315-42 314-42 313-42 312-42 1168-12 316-24 11111-12
11101-5 1391-7 1169-12 P15-9
43
D6
315-43 314-43 J13-43 312-43 1168-13 316-23 U111-9
1191-13 U69-9 P15-8
44
05
315-44 314-44 313-44 312-44 1168-14 316-22 11111-7 U91-6 1169-7 P15-7
45
04
315-45 314-45 313-45 312-45 1168-15 316-21 11111-4 U91-14 U69-4 P15-6
46
03
315-46 J14-46 313-46 312-46 1168-16 316-20 11109-12 U91-5 1166-12 P15-5
47
1)2
315-47 314-47 313-47 312-47 1168-17 316-19 11109-9 U91-15 1166-9 P15-4
15.19
Apple Computer Inc · 1982
Page 0370 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
48
Dl
315-48 314-48 313-48 312-48 1168-18 316-18 11109-7 U91-4 U66-7 P15-3
49
DO
315-49 J14-49 313-49 312-49 1168-19 316-17 11109-4
U91-16 U66-4 P15-2
50
+12v
J15 i 50P1N 50 EDG
1
IOSEL4*
1174-1.1 315-1
2
AO
315-2 314-2 313-2 312-2 U2-6 1197-38 U98-13
11101-11 1194-13 1173-38 U75-13 1163-18 11177-13
3
Al
315-3 J14-3 313-3 312-3 U2-i0 1197-37 1198-14
11101-10 U177-1 U94-1 1373-37 U75-1 U63-16
4
Al
315-4 J14-4 J13-4 312-4 115-6 11101-9 1197-36
U177-2 U94-2 U75-2 1173-36 U6)-14
5
A3
J15-5 314-5 313-5 312-5 US-10 13109-1 UllI-i
U97-35 11177-3 U94-3 1175-3 1373-35 1163-12
6
£4
315-6 314-6 313-6 312-6 119-6 U77-1 U76-1
11112-2 1163-9
7
AS
315-7 314-7 313-7 312-7 U9-10 U76-2 U77-2 11112-3 U63-7
8
A6
315-8 314-8 J13-8 312-8 112-4 1177-3 U76-3 U71-10 U63-5 1171-11
9
Al
315-9 314-9 313-9 312-9 1113-10 1177-6 1176-6 117 1-7 U63-3
10
A8
JiS-lO 314-10 J13-1O 312-10 U67-4 U74-1 U71-6
112-12 1113-6 1113-4
11
A9
J15-11 314-11 313-11 312-11 US-4 1174-2 1171-5
1167-7
12
AlO
315-12 314-12 313-12 312-12 U128-i 1174-3 1171-4
1167-9
13
All
315-13 314-13 313-13 312-13 11128-12 116-6 U71-3
U150-13 1374-5 U67-12 U3-5 11174-S
14
Al2
J15-14 314-14 J13-14 J12-14 U9-12 11155-11 11165-14 U70-4 Ui 1-2 11174-6
15
A13
315-15 314-15 313-15 312-15 U128-4 11155-12 13165-15
15.20
Apple Computer Inc · 1982
Page 0371 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Uil-i U70-7 U6-5 U3-6 U174-7
16
£14
315-16 314-16 313-16 .112-16 U3-7 1.1147-4 U70-9
U6-16 U174-4
17
AlS
315-17 314-17 313-17 312-17 U3-4 U147-3 1170-12
U174-16 U6-7
18
R/W*
315-18 .114-13 J13-18 312-18 113-3 U136-9 U180-17
U176-6 U165-11 11160-11
19
PHO
315-19 11136-11 314-19 313-19 .112-19 U124-5 U65-37
R96- i
20
IOSTRB*
315-20 11150-12 314-20 313-20 312-20
21
RDY
.115-21 11164-8 314-21 313-21 312-21 P14-4 1165-2
22
TSADB*
315-22 312-22 314-22 313-22 11163-3 P14-3
23
SPARZ2
315-23 312-23 314-23 313-23
24
SPARE1
315-24 312-24 314-24 313-24
25
+5v
26
GND
27
DMAOK
U144-8 312-27 315-27 314-27 313-27
28
DMAI*
1.1176-2 .112-28 315-28 314-28 313-23 11163-5 P14-2
U 153-9
29
IOUMI*
315-29 U97-17 314-29 313-29 U139-13 312-29
30
IRQ4*
U97-6 315-30 P2-3 U148-5
31
IORESET*
312-31 313-31 314-31 315-31 P14-6 1.1164-2 U164-4
1196-4 1194-15
32
INH*
315-32 314-32 313-32 312-32 U176-4 U165-13 P14-S
33
-12v
34
-3V
35
SYNC
1165-7 11136-1 315-35 11174-3 314-35 313-35 312-35
36
dM
315-36 314-36 J13-36 312-36 11141-9 U119-2 11146-12
U90-14
37
Q3
314-37 1185-3 315-37 313-37 312-37 U117-12 R93-1 U154-2
38
PRELM*
312-38 .113-38 314-38 J13-38 U123-6 R95-1
39
CO2X*
15.21
Apple Computer Inc · 1982
Page 0372 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
315-39 U77-13 314-39 J13-39 312-39
40
PRE1M
312-40 313-40 314-40 315-40 U119-12 1373-25 U123-5
U97-23 U139-10 R94-1
41
DEVSEL4*
315-41 1376-11
42
Dl
315-42 314-42 313-42 312-42 1368-12 316-24 13111-12
13101-5 U91-7 1369-12 P15-9
43
D6
315-43 J14-43 313-43 312-43 U68-13 316-23 U111-9
1391-13 1369-9 P13-8
44
D5
315-44 314-44 313-44 312-44 1368-14 316-22 13111-7
1391-6 1369-7 PIS-7
45
134
313-45 314-45 313-45 312-45 1368-15 316-21 13111-4
1391-14 1369-4 P15-6
46
133
315-46 314-46 313-46 312-46 1368-16 316-20 11109-12
1391-5 1366-12 PIS-5
47
132
315-47 314-47 313-47 312-47 1368-17 316-19 13109-9
1391-15 1366-9 P15-4
48
Dl
J15-48 314-48 313-48 312-48 U68-18 316-18 U109-7
1391-4 1366-7 P15-3
49
DO
315-49 J14-49 313-49 312-49 1368-19 316-17 13109-4
1391-16 U66-4 P15-2
50
+12v
316 1 2SPIN 25 LNGMOLEX
1
1330
316-1 1366-3 1380-13
2
DEI
316-2 1366-6 1380-8
3
1332
316-3 1366-10 1380-14
4
1333
316-4 U66-13 U80-7
5
1334
J16-5 1369-3 1380-17
6
1335
J16-6 1369-6 1380-4
7
1336
316-7 1369-10 1380-18
8
D37
316-8 1369-13 1380-3
9
DAO
J16-9 U10-4 U84-13 U66-2
10
DAI
15.22
Apple Computer Inc · 1982
Page 0373 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
.116-10 (110-5 1384-8 U66-5
11
DA2
J16-11 (110-12 (184-14 U66-t1
12
DA3
.116-12 (166-14 (184-7
13
DA4
J16-13 (169-2 1384-17
14
DAS
J16r14 U695 U844
15
DM
.116-15 1369-11 (184-18
16
DAl
.116-16 13153-5 1384-3 (169-14
17
-
DO
J15-49 .114-49 .113-49 .112-49 (168-19 .116-17 U109-4 U91-16 1366-4 P15-2
13
Dl
.115-48 J14-48, .113-48 .112-48 (168-18 J16-18 U109-7 1391-4 U66-7 P15-3
19
D2
.115-47 .114-47 J13-47 .112-47 1368-17 J16-19 U109-9 (191-15 (166-9 P15-4
20
D3
.115-46 .114-46 .113-46 .112-46 1368-16 .116-20 U109-12
1391-5 1366-12 P15-5
21
D4
.115-45 .114-45 .113-45 .112-45 (168-15 .116-21 (1111-4
U91-14 1369-4 P13-6
22
D5
.115-44 .114-44 .113-44 .112-44 1368-14 .116-22 13111-7
(191-6 U69-7 P15-7
23
D6
.115-43 J14-43 .113-43 .112-43 U68-13 .116-23 13111-9
U91-13 (169-9 P15-8
24
Dl
.115-42 .114-42 .113-42 .112-42 (168-12 J16-24 13111-12
U101-5 U91-7 1369-12 P15-9
25
GND
.117 1 25P1N 25 UWMOLEX
1
GND
2
+3v
3
+12V
4
AR6
.117-4 (113-9 P16-S
5
ALS
R99-2 .117-5
6
AR4
.117-6 (19-7 P16-6
7
ALS
.117-7 US-9 P16-3
3
ARi
15.23
Apple Computer Inc · 1982
Page 0374 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
öa comptt m
317-8 US-7 P16-2
9
ARI
R98-2 317-9
10
ARO
R97-2 317-10
11
RAMR/W*
317-11 U150-8
12
RASO.3*
317-12 R58-2 Bi-2
13
RAS1.2*
317-13 R59-2
14
317-14 R60-2
15
RAS6.7*
J17-15 R61-2
16
-5V
17
CASO*
317-17 134-2
18
CASI*
317-18 U4-5
19
CAS2*
317-19 U4-6
20
CA33*
317-20 U4-9
21
CAS4,6*
317-21 t34-12 22
134-15 317-22
23
AX*
13124-8 132-2 U13-2 139-2 US-2 317-23 24
U13-7 317-24
25
GND
319 1 3PIN 3 MOLEX H14
i
UIJTSUNK*
J19-1 U118-9 13162-8
2
FIELDOUT
13126-19 319-2
3
FIELDIN
319-3 U121-18 R63-1
13120-9
320 1 lOPIN 10 MOLEX Hl
i
SYNC11
320-1 P17-10 13126-5 P3-2 P4-6
2
RGB2
320-2 P17-6 P4-3 P3-4 P10-6 U90-5 1390-13
1389-10
3
C3.SM
13132-10 U141-i0 U146-13 13119-7 320-3
4
RGB4
P4-4 P17-4 P3-S P10-7 U90-4 U90-iO 1389-7
15.24
Apple Computer Inc · 1982
Page 0375 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
320-4
5
RGB8
320-5 P4-5 P17-2 P3-6 P10-3 1190-11 1190-3
1189-2
6
RGB1
1189-13 P17-B P4-2 P3-3 320-6 P10-4 U90-6
1190-12
7
PORCPAGE
1187-6 P10-2 320-7
8
COLRGATE
320-8 U147-2 11126-6
9
COLORKILL*
U147-13 1187-11 320-9
10
GND
321 1 SPIN 5 MOLEX 814
1
HPEDIS
11135-2 321-1 R54-1
2
CI4M*
11141-13 11146-8 U124-11 321-2
3
UUTRST*
U124-13 11119-1 11123-1 R53-2 11114-1
11120-1 U118-i 11117-1
4
UUTT.TPRST
R92-2 U162-1l 321-4 U164-3
5
CND
J21-3
11116-1
Li 5 2711 2 Li MIO
1
P3-9
2
GNDP
R55-2
CS-I
Li-1
1.2 i 30U 2 FILl Ml
i
+5V
2
+5FV
1.3 1 10(1 2 P1L2 1.7
1
-5V
2
-sri
L4 I 3011 2 FILl Ml
1
+12v
2
+I2FV
1.5 1 iOU 2 P11.2 1.7
1
-12v
2
-I2FV
Ql 4 3904 3 TRI Cl
1
U72-24 QI-I
2
Q1-2 as-2
3
+3V
Xi-2
15.25
Apple Computer Inc · 1982
Page 0376 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Q2 4 3906 3 TRI Cl
L
Q2-1
2
+5V
3
Q3-2
Cl-1 Q2-3
Rie-2
aloi-1
Q3 4 3904 3 TRi 81
i
CND
2
Q3-2 Q2-3 RIOl-i
3
PWRDN*
U72-23 Q3-3 C2-1
36-2
Q4 5 3904 3 TRI Mi
i
Ris-1
2
P4-i
3
+5V
Q4-1 Q4-2
R16-1
Q9 8 MPSUSI 3 TRI L14
i
.+5FV
2
KVCC
J7-3 Q9-2
3
Q9-3 R43-1
Ulil-lO
QiO 9 4258 3 TRI 313
i
QIl-i
2
QlO-2
3
R52-I
R48-2 R90-2 Ql0-3
QiO-i P31-i Yl-1
C23-1
R49-1
Qil 9 4258 3 TRI B13
1
QiI-i R48-2 QiO-i
2
Y1-2 QL 1-2 R49-2
3
Ql1-3 331-1 U146-10
U146-5
U146-2
Q12 5 3904 3 TRI Li
i
R12-1 R13-1
2
P3-I Q12-2
3
+5V
Q12-1
Pl 2 1K 10 SIP1O C14
1
+5v
2
PCAS46*
U4-13 U6-14 Pi-2
3
PCAS1*
Pi-3 U4-4 U6-12 U128-10
4
PCAS2*
Pi-4 1.14-7 U6-11
5
PCAS5,7*
t14-14 Fi-5 136-13
6
PCAS3*
U128-2 13128-13 Pi-6 U3-i1
7
PCASO*
134-8
15.26
Apple Computer Inc · 1982
Page 0377 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
PI-7 174-3 173-14
8
PUSELB
U4-17 PI-8 173-13
9
PCASO,3*
Pi-9 U3-12 BI-1
lo
NO CONNECTION
P2 4 iX 8 S1P8 34
1
+5V
2
NO CONNECTION
3
IRQ4*
U97-6 315-30 P2-3 17148-5
4
IRQ3*
1797-7 314-30 P2-4 17148-4
5
NO CONNECTION
6
IRQ2*
17101-15 J13-30 P2-6 U148-2
7
IRQL*
17101-14 312-30 P2-7 17148-1
8
NO CONNECTION
P3 5 SP) 10 SIP1O L9
i
P3-i Q12-2
2
SYNCH
320-1 P17-10 U126-5 23-2 P4-6
3
ROEl
1789-15 P17-8 24-2 P3-3 320-6 P10-4 U90-6
1790-12
4
RGB2
320-2 P17-6 P4-3 P3-4 P10-6 1790-5 U90-13
1789-10
5
RCB4
24-4 P17-4 23-5 P10-7 1790-4 U90-10 1789-7 320-4
6
RCB8
320-5 P4-S Pli-2 P3-6 P10-3 1790-11 1790-3 U89-2
7
NTSCA
23-7 1190-7
8
NTSCB
P3-8 U163-8
9
P3-9 R35-2 CS-i Li-1
lo
NO CONNECTION
P4 5 SP4 8 SIP8 MS
1
P4-i Q4-2
2
RGB1
U89-15 P17-8 P4-2 P3-3 320-6 P10-4 1790-6
1790-12
3
R082
320-2 P17-6 P4-3 23-4 210-6 U90-5 1790-13
1789-10
15.27
Apple Computer Inc · 1982
Page 0378 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
ölppkz cor .fr'?Jr ,.
4
RGB4
P4-4 P17-4 P3-S P10-i 1390-4 (190-10 1389-7
J20-4
5
RGB8
J20-5 P4-S pli-2 P3-6 P10-3 U90-ll 1390-3
1389-2
6
SYNCH
J20-1 P17-10 13126-5 P3-2 P4-6
7
NO CONNECTION
8
+5V
P8 5 1K 6 SIP6 F4
i
+5V
2
NO CONNECTION
3
DXS
U89-12 U86-5 P8-3
4
DX4
1389-13 U86-16 P8-4
5
DX6
1389-5 1386-19 P8-S
6
0X7
1389-4 1386-2 P8-6
P9 7 SP9 8 SIP8 CS
i
SliM SND
835-2 P9-i ClO-i
2
SND5
P9-2 1397-15
3
SND4
P9-3 1397-14
4
SND3
P9-4 1397-13
5
SND2
P9-S 1397-12
6
SND i
P9-6 U97-11
7
SNDO
P9-7 1397-10
B
+5V
RJ8-2
PlO 5 1K 8 SIP8 04
1
+5v
2
FORCPACE
1387-6 P10-2 J20-7
3
RGB8
.120-5 P4-S P17-2 P3-6 P10-3 (190-11
1389-2
4
RGB1
1389-15 P17-B P4-2 P3-3 .120-6 P10-4
1390-12
5
NO CONNECTION
6
RG82
(190-3 1390-6
15.28
Apple Computer Inc · 1982
Page 0379 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
320-2 P17-6 P4-3 P3-4 P10-6 1390-5 1390-13
U89-1O
7
RGB4
P4-4 P17-4 P3-S P10-i 1390-4 U90-10 1389-7
320-4
8
NO CONNECTION
P11 8 1K 8 SIP8 1.14
1
+5F'!
2
CONTROL*
Ji-li U179-13 13107-28 U109-10
3
CAPLCK*
37-9 Pli-3 U109-13
4
APPLEI*
.17-7 Pli-4 13111-3
5
APPLEII*
37-5 P11-5 U106-12 13164-5
6
SHIFT*
37-24 Pli-6 U107-29
7
NO CONNECTION
8
NO CONNECTION
Pli-2
P13 5 1K 6 SIP6 G3
i
GND
2
DO
U88-14 U86-12 P13-2
3
DX2
1388-5 U86-15 P13-3
4
DX3
1388-2 U86-6 P13-4
5
D1
1388-11 1386-9 P13-S
6
NO CONNECTION
P14 3-4-8 1K 6 SIP6 Ml
1
+5V
2
DMAI*
13176-2 .112-28
11153-9
3
TSADB*
.115-22 .112-22
4
R.DY
.115-21 U164-8
5
INR*
315-32 J14-32
6
IORESET*
312-31 313-31
U96-4 1394-15
.115-28
314-22
.114-21 .113-32
314-31
.114-28
.113-22
313-21
.112-32 315-31
.113-28 13163-5 P14-2
13163-3 P14-3 J12-21 P14-4 U65-2 13176-4 U165-13 P14-5 P14-6 13164-2 U164-4
P15 3 3.3K 10 SIPlO C3
1
+5V
2
DO
15.29
Apple Computer Inc · 1982
Page 0380 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
pcomp
J15-49 .114-49 .113-49 .112-49 U68-19 J16-17 (1109-4 U91-16 (166-4 P15-2
3
Dl
315leS J14-48 .113-48 .112-48 (168-18 .116-18 (1109-7
U91-4 U66-7 P 15-3
4
D2
.115-47 .114-47 .113-47 .112-47 tJ68-17 .116-19 (1109-9
(191-15 (166-9 P15-4
5
D3
.115-46 314-46 313-46 312-46 (168-16 .116-20 (1109-12
(191-5 (166-12 PIS-5
6
D4
.115-45 .114-45 .113-45 J12-45 U68-15 .116-21 (1111-4
(191-14 (169-4 P15-6
7
D5
J15-44 .114-44 .113-44 312-44 (168-14 J16-22 U111-7
(191-6 (169-7 PIS-7
8
D6
J15-43 .114-43 313-43 312-43 (168-13 316-23 (1111-9
U91-13 U69-9 P15B
9
Dl
315-42 J14-42 .113-42 312-42 (168-12 316-24 (1111-12 U1O1-5 (191-7 (169-12 P15-9
10
NO CONNECTION
P16 2 330 8 SIPS F13
1
+3V.
2
AR2
317-8
3
AR)
317-7
4
ARO
P16-4
5
AR6
317-4
6
AR4
J17-6
7
AR5
R99-1
8
ARi
P16-8
US-7 P16-2 US-9 P16-3 P.97I (12-7
U13-9 P16S
(19-7 P16-6
(19-9 P16i
R98-1 (12-9
P17 5 75 10 SIPIO M9
1
XRB8
35-10 P17I P18-2
2
RGB8
J20-5 P4S P17-2 P3-6
(189-2
3
XRCB4
.15-2 P17-3 P18-3
4
RGB4
P4-4 P17-4 P3-5 P10-7
P10-3 U90-4
(190-11 (190-10
(190-3 (189-7
15.30
Apple Computer Inc · 1982
Page 0381 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
ppkzui
320-4
3
XRCB2
35-9 P17S P18-4
6
RGB2
320-2 pli-6 p4_3 P3-4 P10-6 U90-5 1.T90-13
U89l0
7
XRGB1
35-3 P17i P18S
8
RGLI
1189-15 P17-8 P4-2 P3-3 320-6 P10-4 1190-6
1190-12
9
XSYNC
35-3 P17-9 P18-6
10
SYNCH
320-1 P17-10 U126-5 P3-2 P4-6
P18 5 220P 8 51P8 M9
1
GND
2
XRGB8
35-10 P17i P18-2
3
XRGB4
35-2 Pli-3 P18-3
4
XRG32
35-9 P17-5 P18-4
5
XRCBI
35-5 P17-7 P18-5
6
XSYNC
35-3 P17-9 P18-6
7
s&wvID
35-11 LIS-2 310-1
8
NTSC
35-12 R12-2 P18-8
P18i
P19 4 3.3K 10 SIPIO B6
1
+5V
2
SEL.IM
11180-15 U174-2 U150-3 U73-9
3
lOEN
1173-8 P19-3 11147-10
4
SCRN
11154-13 U73-7 P19-4
5
RESETLK*
11179-14 1173-6 P19S 11139-5
6
RWPR
1173-5 P19-6 11180-16
7
PRIMSTK
U73-4 P19i 11158-9
3
ROMSEL2
1173-3 U64-21 P19-8
9
ROMSELI
11165-10 U73-2 P19-9
10
PH2M
P19-2
15.31
Apple Computer Inc · 1982
Page 0382 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
pcomputarmc
P19-to U141-5 U65-39 17176-17
R4 4 100K 2 QW A2
1
+5V
2
Q2-1
Cl-1
R4-2
RS 4 47K 2 QW CZ
1
+12V
2
Qi-2 R5-2
R6 4 410K 2 QW £2
1
+5v
2
PWRDN*
U72-23 Q3-3
CZ-i
R6-2
R9 4 3.314 2 QW £2
i
R9-t
2
GND
Ti-i
Xi-1
UlOS-lO
R12 5 47 2 QW N6
i
Ri2-1
2
NTSC
J5-12
R13-1 R12-2
Q12-1 P18-8
R13 5 75 2 QW N6
i
RiZ-1
2
CND
R13-1
Q12-i
RIS 5 47 2 QW M6
i
RiS-i Q4-i
2
B&WVID
J5-i1 R15-2
R16-1 J1O-1
P18-7
R16 5 75 2QW NS
I
RiS-i
2
GND
Q4-1
R16-i
R31 6 41K 2 QW N14
i
DTIM
R31-1
2
+5V
U164-10
C7-2
U96-2
U96-6
R34 7 3K 2 QW N5
i
EXTSPK1
J1l-1 R.34-I
2
C78-1 U103-2
R34-2
R36-1
R35 7 4.7K 2 QW G6
i
AIISPKR
R35-1 U173-9
2
SUMSND
R35-2 P9-i Cia-1
R78-2
15.32
Apple Computer Inc · 1982
Page 0383 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
R36 7 1K 2 QW 1412
i
C78-1
2
CND
U103-2
R34-2
R36-1
937 7 4.3K 2 QW 1.9
1
+12V
2
U105-8
P37-2
938-1
C76-1
R38 7 1.1K 2 QW 1.9
1
U105-8
2
GIlD
P37-2
R38-1
C76-1
R39 7 1.214 2 QW 1.9
1
+12v
2
U105-6
P39-2
C9-1
940 8 iN 2 QW 1.11.
i
ANYKEY
13107-4 R40-1 X2-2 U106-11
2
1.196-13 U96-12 U96-8 R40-2
X3-1 C75-1
U109-3 X2-1 C18-i
Cil-1
943 8 1K 2 QW G13
i
Q9-3
2
GND
R43-1
Ulil-lO
R44 8 2.214 2 QW A6
1
+5V
2
UPRST*
C20-1 13113-6
13113-2
R44-2
X4-2
X6-1
945 8 15K 2 QW AS
1
+5V
2
13113-13
945-2
R46-1
946 8 3.314 2 gV AS
I
13113-13 R45-2 P46-i
2
U113-8 946-2 13113-12
C21-1
R47 8 100K 2 QW H14
1
13107-3
2
U107-2
R47-1 C16-2
R47-2
R48 9 180 2 QW A13
1
+12v
2
Qil-I
R48-2
QiO-i
949 9 47 2 gV A13
i
qlo-2 990-2 R91-1
2
Y1-2 Q1i-2 R49-2
C23-1
949-1
15.33
Apple Computer Inc · 1982
Page 0384 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
pcomp*m
R51 9 75 2 QW A13
i
Q11-3
2
GND
R31-1
U146-1O
U146-5
U146-2
R52 9 47 2 QW Al2
i
R.52-1 q1O-3 Yi-1
2
NO CONNECTION
RS) 9 1K 2 QW C14
1
+5V
2
UUTRST*
U124-13 U119-1 U123i
U120i U118-1 U1i7-1
R53-2 U114-1
121-3
U1i6-1
R54 9 1K 2 QW C9
i
HPEDIS
11135-2 J21-1
2
GND
R.54t
R55 5 1K 2 QW KS
I
COLORBURST
R551 TJ147-12
2
P3-9 R.55-2 CSi
Li-1
R57 7 10K 2 QW LS
1
+5V
2
PDLOT*
U1O1-13
U105-7
L57-2
R58 2 27 2 QW C14
i
RRASO.3*
R58i U12-3
2
RASO.3*
J17-12 R38-2
Bi-2
R59 2 27 2 QW Ci4
i
RRAS1.2*
P39i U12-6
2
RAS1.2*
317-13 R59-2
R60 2 27 2 QW E12
i
R601 U12-8
2
p,k54.s*
317-14 R60-2
R61 2 27 2 QW D12
i
RRAS6.7*
R61-1 U12i1
15.34
i
Apple Computer Inc · 1982
Page 0385 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
2
RAS6 7*
317-15 P61-2
P63 9 3K 2 QW Gli
i
FIELDIN
319-3 U121-18
2
GND
P63i
P.65 6 1K 2 QW H9
1
+3V
2
MOTON*
U179-1 U92-15
U178-13
P.65-2
U164-12
U92-16
R66 6 iX 2 QW Lii
i
U92-9
2
GND
U91-9 P.66i
R-67 6 1K 2 QW L9
1
+3V
2
U161-1i
U92-5
R67-2
R-68 9 3K 2 QW Fi
I
PCS6522
R68i 13180-14
2
CS6522
P.68-2 1373-24 C59i
1397-24
R69 7 33 2 QW Mil
i
AUDIO
39-1 P.69i
2
P69-2 13103-6
RiS 7 1MEC 2 QW A8
1
+3V
2
C69-2 P75-2 Ui81i 13181-2
P76 7 1.5K 2 QW M
1
+5V
2
P76-2 ,R17i U181-13
P77 7 6.8K 2 QW Aß
1
P.76-2
2
P77-2
R-771 U181-13 Ú181-8 U181-12
dO-1
R78 7 6.8K 2 QW Ai
i
13181-9 P78i
2
SUMSND
R-35-2 P9i Cbi R78-2
P.79 4 3K 2 QW A4
1
+5v
2
CKIRQ*
15.35
I
Apple Computer Inc · 1982
Page 0386 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
1cpkzcomp
U72-13 R79-2 U97-40
R80 8 10K 2 QW M14
i
KRESET*
U139-12 R20-1
2
+5V
C71-1
U179-15
J7-15
R.81 1 240 2 QW N4
i
Xi-2
2
GND
Rß1-1
R85 7 3K 2 QW N4
1
+5V
2
SV1/MGNSWUF
R85-2 U169-19
1173-39
U10i-3
R86 7 1.1K 2 QW J9
i
R86-1
2
GND
U160-6
11161-2
R.7 7 15K 2 QW Ji
1
+12v
2
PCTS
R87-2
11172-15
11100-4
R88 7 15K 2 QW Ji
1
+12v
2
PDSR
R8-2
11172-16
11100-10
R89 7 15K 2 QW .12
1
+12V
2
PDCD
R89-2
11172-18
11100-13
R90 9 1.5K 2 QW A13
1
+12V
2
Q10-2
R90-2
R91-1
C23-i
R49-1
R91 9 1.1K 2 QW Al2
1
Q1O-2
2
GND
R90-2
R91-1
C23-1
R49-1
R92 8 1K 2 QW A4
1
TRESET
11113-5 R92-i
2
UUTUPRST
R92-2 11162-11
J21-4
U164-3
R93 1 120 2 QW Li
i
Q3
.114-37
1185-3
.115-37
.113-37
J12-37
11117-12
P33-1
15.36
Apple Computer Inc · 1982
Page 0387 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
U154-2
2
R93-2 C67-1
R94 1 120 2 QW Li
i
PREDI
,312-40 313-40 314-40
1197-25 11139-10 R94-1
2
R94-2 C68-1
315-40
U119-12
U73-25
L1123-5
R95 1 120 2 QW Li
i
PRE1M*
312-38 J13-38
2
R95-2 Cil-1
314-38
315-38
11123-6
R95-1
R96 1 120 2 QW M5
i
Puo
315-19 11136-11
R96-1
2
R96-2 C66-1
314-19
313-19
J12-19
11124-5
U65-37
R97 2 33 2 QW E13
i
ARO
P16-4
2
ARO
R97-2
R97-i i2-7 J17-10
R98 2 33 2 QW E13
ARi
P16-S
2
ARi
R98-2
R98-1 317-9
U2-9
R99 2 33 2 QW F12
I
ARS
R99-1
2
ARS
R99-2
119-9 P16-7 J17-5
RIMO 2 100 2 QW D12
i
C14M
11146-6
2
R100-2
RiflO-i 11117-10 C74-1 114-11
11119-9
U79-7
1185-11
RiOl 4 100K 2 QW A2
I
Q3-2 Q2-3 RiOl-i
2
GND
R102 6 470 2 QW L9
i
+5v
2
Q3*
U93-9 U136-12
11131-5 R102-2
U91-12 RU)3-1
U117-i1
11146-1
11117-2 11117-3
U135-12
15.37
Apple Computer Inc · 1982
Page 0388 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
COT11 9 00E Z ¡ib 6I
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90111 t l i Z
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Z-90111 Z-59111 O1-CLifl
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'z-CLIfl
El-CLIn
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Z
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Z-10111 L-'zttfl
Z-90111 c-91Tfl
'z-90111
01-90111
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80111 I )11 Z Nb Ça
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60111 I
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Z-60111 OT-CZlfI
t-%'Zlfl 'z'-'zZifl ot-'zzin CT-tVtfl 'z-LTTIÎ -Li1fl
Li-Ola 'z-9'zlfl 'z-CZtfl
9-Lun ¿-Lila
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Z
zA
61-LBfl Z-In 'z-'zÇIfl Zt-OZlfl
C
c-lZTfl C-In 'zl-91111
'z
Twts
'z-In Il-cn
S
EH
tT-Ttfl S-In 9'-TZtfl
9
EA
ET-Ozjfl ct-in c-çtn 9-In
L
UND
9
UND
6
ON NO11.MN0)
01
flS
01-in E-Zfl
Ii-in
Apple Computer Inc · 1982
Page 0389 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
11
V4
1187-19 Ui-2 11154-4 U120-12 UI-11
12
GND
13
SUM3
Ui-13 U9-11
14
ILS
11121-4 Ui-14 U116-13
15
V3
U120-13 Ui-15 U154-5 UI-6
16
+3V
112 2 S153 16 F13
1
GND
2
11124-8 112-2 1113-2 119-2 115-2 317-23
3
S1fl44
Ui-10 112-3
4
A6
J15-8 .114-8 313-8 312-8 U2-4 1177-3 1176-3
1171-10 U63-3 U71-11
5
HO
11114-14 112-5
6
AO
J15-2 314-2 313-2 312-2 U2-6 1197-38 1198-13
11101-li U94-13 U73-38 U75-13 1163-18 11177-13
7
ARO
P16-4 R97-1 U2-7
8
GND
9
ARi
P16-8 R98-i U2-9
lo
Al
J15-3 314-3 313-3 312-3 112-10 1197-37 U98-i4
11101-10 11177-1 1194-1 1173-37 U75-1 U63-16
11
Hi
U114-13 112-il Ul55-9
12
A8
315-10 314-10 313-10 312-10 U67-4 1174-1 1171-6 U2-12 1113-6 Ui3-4
13
VI
11121-22 112-13 11118-11 1113-5 1113-3
14
AY*
1113-14 1111-3 119-14 115-14 112-14 11153-3 116-15
113-i
15
GND
16
+3V
øQI
113 2 7643 18 34l.O&6 Cl2
i
AY*
U13-14 U11-3 U9-14 US-14 U2-14 U153-3 U6-13
113-1
2
RDHI RES
11175-1 1111-17 113-2 U6-3 U126-9
15.39
Apple Computer Inc · 1982
Page 0390 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
3
R/W*
J15-18 J14-18 J13-18 J12-18 U3-3 11136-9 11180-17
11176-6 11165-11 11160-11
4
A15
J15-17 .114-17 J13-17 .112-17 U3-4 11147-3 1170-12
11174-16 116-7
5
All
J15-13 .114-13 .113-13 J12-13 11128-12 U6-6 (171-3
11150-13 U74-5 1167-12 (13-5 11174-5
6
A13
.115-15 .114-15 J13-15 .112-15 11128-4 11155-12 11165-15
1171-1 1170-7 116-5 113-6 (1174-7
7
A14
.115-16 .114-16 .113-16 .112-16 113-7 U147-'4 U70-9
116-16 11174-4
B
Ql
116-8 U131-4 U3-8 11124-12 U117-14
9
GND
lo
GND
11
PCAS3*
U128-2 U128-13 Pi-6 113-11 (14-8
12
PCASO,3*
Pi-9 113-12 81-1
13
PUSELB
114-17 PI-8 113-13
14
PCASO*
PI-7 114-3 113-14
15
PRASO.3
U128-5 U11-14 U12-i 113-15 U6-4
16
PRASI.2
U12-4 1111-13 113-16
17
ABK2
116-1 U11-6 1110-7 (13-17
18
+5V
114 2 S374 20 D13
i
CND
2
CASO*
J17-17 114-2
3
PCASO*
Pi-7 154-3 113-14
4
PCASL*
Pi-3 U4-4 116-12 11128-10
5
CAS1*
.117-18 U4-5
6
CAS2*
.117-19 114-6
7
PCAS2*
FI-4 U4-7 U6-i1
8
PCAS3*
11128-2 U128-13 P1-6 U3-ll 9
U4-8
15.40
Apple Computer Inc · 1982
Page 0391 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
acompm
317-20 U4-9
10
GND
11
R100-2 C74-1 U4-11
12
CAS4,6*
317-21 34-12
13
PCAS4,6*
14
U4p-513,7L*J6-14 Pi-2
114-14 Pi-5 U6-13
15
CAS5,7*
114-15 .117-22
16.
USELS
U4-16 U66-i 1169-1
17
PUSELB
114-17 Pi-8 113-13
18
NO CONNECTION
19
NO CONNECTION
20
+5V
115 2 S153 16 E12
CND
2
A.X*
0124-8 U2-2 1113-2 U9-2 US-2 317-23
3
V2*V5
11121-8 U154-8 US-3
4
A9
JIS-lI 314-11 313-11 312-11 US-4 U74-2 U71-5 U67-7
5
11121-7 U5-5 U114-12 085-8
6
A2
315-4 J14-4 313-4 312-4 US-6 U1O1-9 U97-36
11177-2 U94-2 1175-2 U73-36 1163-14
7
AR2
317-8 115-7 P16-2
8
GND
9
AR3
317-7 US-9 P16-3
10
A3
315-5 314-5 313-S 312-S US-10 U109-1 11111-i
1197-35 U177-3 1194-3 U75-3 U73-35 063-12
11
SUMI
Ui-4 115-11
12
US-12 U128-3
13
MUXI
11101-12 U175-14 US-13
14
AY*
U13-14 U11-3 119-14 US-14 U2-14 11153-3 06-15
U3- i
15
CND
16
45V
15.41
Apple Computer Inc · 1982
Page 0392 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
mp
U6 2 7643 18 341-0042 C13
i
ABK2
U6-1 1.111-6 U10-7 U3-17
2
ABKI
U6-2 1111-5 (110-2
3
RDHIRES
11175-1 Uil-li U3-2 (.76-3 (1126-9
4
PRASO.3
11128-5 UL1-14 U12-1 113-15 116-4
5
A13
.115-15 .114-15 J13-15 .112-15 (1128-4 U155-12 U165-15 U71-1 1170-7 116-5 U3-6 11174-7
6
All
.115-13 .114-13 .113-13 .112-13 11128-12 U6-6 1.771-3
11150-13 1174-5 U67-12 113-5 11174-5
7
A15
.115-17 .114-17 .113-17 .112-17 113-4 U147-3 (170-12 (3174-16 116-7
8
Ql
(36-8 U131-4 U3-8 11124-12 U117-14
9
GIlD
10
GND
11
PCAS2*
pi-4 U4-7 116-11
12
PCASI*
Pi-3 (14-4 116-12 U128-10
13
PCAS5,7*
(14-14 Pi-5 116-13
14
PC4,5*
U4-13 U6-14 Pi-2
15
AY*
U13-14 Ul1-3 (19-14 US-14 112-14 11153-3 (36-15
(33-1
16
A14
.115-16 314-16 J13-16 312-16 113-7 11147-4 1170-9 (36-16 U174-4
17
ABK3
116-17 U11-7 1110-10
18
+5V
(39 2 S153 16 F12
1
GIlD
2
U124-8 112-2 U13-2
3
MUX2
U9-3 11175-13
4
U9-4 11128-11
5
SUM2
UI-1 (19-5
6
A4
315-6 314-6 313-6
(3112-2 1163-9
119-2 115-2 317-23 J12-6 119-6 Uil-i
U76-1
3.5.42
-I
Apple Computer Inc · 1982
Page 0393 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
*p - I
7
AR4
J17-6 09-7 P16-6
8
GND
9
AR5
1t99-1 09-9 P16i
10
AS
315-7 314-7 313-7 J12-7 u9-10 076-2 U77-2
U112-3 U63-7
11
SUM)
Ui-13 09-11
12
Al2
315-14 314-14 313-14 312-14 09-12 U155-11 0165-14
070-4 U71-2 U174-6
13
MUX3
09-13 U175-12
14
AY*
U13-14 011-3 09-14 US-14 02-14 0153-3 06-15
03-1
15
GND
16
+5V
010 2 LS399 16 A9
I
UlOi 0153-6
2
ASK1
U6-2 U11-5 010-2
3
BKSWI
U97-2 010-3
4
DAO
316-9 010-4 084-13 066-2
5
DAl
316-10 U10-5 U84-8 U66-5
6
BKSW2
097-3 U10-6
7
ABK2
06-1 011-6 010-7 03-17
8
CD
9
CLKBK
0136-8 U10-9
10
ABK)
U6-17 011-7 010-10
il
BKSW3
097-4 UlOIL
12
DA2
316-11 010-12 U84-14 U66-11
13
S5D
5109-2 U124-1 0124-4 U124-10
0123-10 0123-13 U117-4 0117-5
14
GND
15
A3K4
Uilis 0174-1 010-15 0158-10
16
+5v
U10-13 0117-6
0146-4 U117-7
U123-4
15.4J
Apple Computer Inc · 1982
Page 0394 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
jamp
1311 2 7643 18 341-0044 Cii
i
ZPACE*
Uil-i 13174-15 1367-1 13131-8 1370-1
2
PAS
1311-2 13174-17 1367-3 13158-6
3
AY*
U13-14 1311-3 139-14 133-14 112-14 13153-3
133-1
4
PAlS
13135-10 1311-4 1370-13 1365-25
S
ABIC1
136-2 U11-5 1110-2
6
ABK.2
136-1 Ui1-6 1310-7 133-17
7
ABK3
U6-17 Uil-i 1310-10
8
CND
9
GND
10
GND
11
PRAS6.7
U12-12 Uil-il
12
PR.A54.5
1312-9 Ui1-12
13
PRASI.2
1312-4 1311-13 133-16
14
PRASO.3
11128-5 1111-14 U12-1 133-15 U6-4
15
ABK4
1311-15 U174-1 1110-15 13158-10
16
RPS1i
13158-13 1311-16 U126-2
17
RJ»IIRES
13175-1 1311-17 113-2 136-3 U126-9
18
+5V
136-15
U12 2 SOG 14 D12
i
PRASO.3
11128-5 U11-14 1112-1 133-15 136-4
2
RAS
U152-13 13130-9 13119-14 U12-2 U12-5
3
RRASO.3*
R58-I 1312-3
4
PRASI.2
U12-4 1311-13 133-16
5
RAS
13152-13 U150-9 13119-14 1312-2 U12-5
6
RRASI.2*
R39-1 1312-6
7
CND
8
RRAS4.5*
R60-1 1112-8
9
PRAS4.5
1312-10
U12-i0
1312-13
U12-13
15.44
Apple Computer Inc · 1982
Page 0395 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
U12-9 U11-12
lo
RAS
13152-13 1.1150-9 11119-14 1112-2 1112-5 1112-10 U12-13
11
R&A56.7*
R61-1 1112-11
12
PRAS6 .7
U12-12 Uil-li
13
AS
U152-13 U150-9 11119-14 1112-2 1112-5 Ui2-i0 1112-13
14
+5V
1113 2 S153 16 Ei)
i
CND
2
AX*
11124-8 U2-2 1.713-2 U9-: US-2 317-23
3
Vi
11121-22 112-13 13118-11 '113-5 U13-3
4
Aß
.115-10 314-10 313-10 312-10 1167-4 U74-1 1171-6
112-12 1113-6 1113-4
S
Vi
11121-22 112-13 0118-li 1113-5 U13-3
6
AS
315-10 J14-10 .113-10 312-10 1167-4 1174-1 1171-6
112-12 1113-6 T3U-4
7
AR7
U13-7 317-24
8
GND
9
ABk
317-4 111.3-9 P16-5
10
A7
.115-9 314-9 .113-9 .112-9 1113-10 1177-4 1176-6
1171-7 1163-3
11
vo
U121-2 1113-11 11L18-11
12
U13-12 11128-8
13
PG2*
1187-9 1113-13
14
AY*
1113-14 U11-3 119-14 115-14 112-14 U153-3 U6-15
113-1
15
GND
16
+5V
;
1163 3 LS244 20 06
1
1170-15 13163-4 U67-15 1163-19 U63-1
2
PAO
1364-8 1163-2 U65-9
3
Al
313-9 314-9 313-9 312-9 U13-10 1177-4 1176-6
117 1-1 1163-3
4
PAl
15.45
./
Apple Computer Inc · 1982
Page 0396 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
acompui
U64-7 1163-4 1165-10
5
A6
315-8 314-8 313-8 312-8 132-4 1177-3 U76-3
Uil-LO 1163-5 Uil-il
6
PA2
U64-6 U63-6 U65-i1
7
AS
315-7 314-7 313-7 J1'-7 U9-10 U76-2 U77-2
U112-3 U63-7
8
PA)
1164-5 U63-8 1365-12
9
£4
315-6 314-6 313-6 J12-6 119-6 1377-1 U76-1
13112-2 1363-9
10
CND
11
PA4
1164-4 U63-11 U65-13
12
A3
J15-5 314-5 J13-5 312-5 US-10 U109-1 13111-1
1197-35 11177-3 U94-3 1175-3 1173-35 1163-12
13
PAS
1164-3 1163-13 1165-14
14
£2
315-4 J14-4 313-4 312-4 US-6 11101-9 U97-36
11177-2 1194-2 TriS-2 1373-36 1163-14
15
PA6
U64-2 U63-15 1165-15
16
Ai
J15-3 314-3 313-3 312-3 132-10 1397-37 1398-14
13101-10 U177-1 U94-1 1173-37 1375-1 1163-16
17
PA7
1164-1 U63-17 1365-16
18
AO
315-2 314-2 313-2 312-2 U2-6 U97-38 U98-13
U101-il U94-13 1373-38 1375-13 1163-18 11177-13
19
U70-15 13163-4 U67-15 1163-19 1363-1
20
+5v
1364 3 2332 24 39
1
PAl
1164-1
2
PA6
1164-2
3
PAS
U64-3
4
PA4
1364-4
5
PA)
U64-5
6
PA2
1164-6
7
PAl
1363-17 1165-16 1163-15 1365-15
U63-13 1365-14
1363-11 1365-13 1163-8 1165-12
U63-6 1165-11
15 46
Apple Computer Inc · 1982
Page 0397 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
1164-7 1163-4 1165-10
8
FAO
1364-8 1363-2 1165-9
9
IDO
U98-18 1365-33 U97-33 1172-15 1373-33 1364-9 1168-1
10
ID i
U98-19 1363-32 097-32 1172-16 1373-32 1364-10 U68-2
11
1D2
1398-20 1365-31 1197-31 1372-17 1373-31 1164-11 U613-3
12
NO CONNECTION
13
1D3
1398-21 065-30 1197-30 U72-13 1373-30 U64-13 1368-4
14
1D4
TJ98-22 065-29 1397-29 U72-19 U73-29 1364-14 068-5
15
Ins
1198-23 065-28 U97-28 1372-20 1373-28 1364-15 068-6
16
1D6
1398-24 065-27 U97-27 1172-21 073-27 1364-16 1368-7
17
1D7
1398-25 1165-26 1197-26 U72-22 U73-26 1364-17 068-8
18
PAl i
U64-18 U144-12 U65-20 U67-13 13135-4
19
PAlO
064-19 13155-6 1365-19 1167-10
20
TROMSEL*
13153-8 13162-13 U64-20
21
ROMSEL2
1173-3 1364-21 P19-8
22
PA9
1164-22 11155-5 1365- 18 1367-6
23
PPAS
13158-4 11152-4 11158-5 1165-17 U64-23 0132-5
24
+5v
1165 3 65028 40 88 GND
2
RDY
315-21 11164-8 314-21 313-21 312-21 P14-4
3
NO CONNECTION
4
IRQ*
1197-21 1365-4 1398-26 1397-9 1173-21
S
NO CONNECTION
6
NMI*
U139-6 1365-6 13155-2
7
SYNC
1165-7 0136-1 315-35 0174-3 314-35 313-35
8
+5V
9
FAO
U64-8 1163-2 1365-9
10
PAl
1364-7 U63-4 065-10
11
PA2
065-2 312-35
15 47
J
Apple Computer Inc · 1982
Page 0398 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
- r
064-6 063-6 065-11
12
PA)
064-5 063-8 1.165-12
13
PA4
064-4 063-11 065-13
14
PAS
064-3 063-13 1165-14
15
PA6
064-2 063-15 065-15
16
PAl
064-1 U63-17 065-16
17
PPA8
tfl58-4 0152-4 0158-5 065-17 064-23 0132-5
18
PA9
064-22 0155-5 065-18 1167-6
19
PAlO
1.164-19 0155-6 U65-19 067-10
20
PAll
064-18 11144-12 065-20 067-13 0135-4
21
CND
22
PAI2
U65-22 U135-9 070-3
23
PAI3
U65-2 0135-8 1170-6
24
PAI4
U65-24 U135-11 1170-10
25
PA15
U135-1O 011-4 1170-13 065-23
26
¡Dl
1198-25 U65-26 U97-26 072-22 073-26 1164-17 068-8
27
¡06
1198-24 U65-27 097-27 072-21 073-27 064-16 068-7
28
IDS
t198-23 065-28 U97-28 072-20 073-28 064-15 068-6
29
¡04
1198-22 U65-29 097-29 1172-19 U73-29 U64-14 1168-5
30
1D3
U98-21 065-30 U97-30 072-18 073-30 064-13 068-4
31
¡02
1198-20 065-31 097-31 072-17 U73-31 064-11 068-3
32
¡DL
098-19 065-32 097-32 U72-16 U73-32 U64-1O U68-2
33
IDO
1198-18 065-33 097-33 072-15 U73-33 064-9 068-1
34
IR/W*
1198-28 U97-22 0112-14 073-22 0163-11 1165-34 0160-12
35
NO CONNECTION
36
NO CONNECTION
37
PRO
.115-19 0136-11 J14-19 J13-19 J12-19 U124-5 065-37 R96-1
38
CND
15.48
Apple Computer Inc · 1982
Page 0399 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
39
PH2M
P19-10 U141-5 U65-39 U176-17
40
RESET*
U65-40 U162-1O U98-4 U97-34 U73-34 1J75-15 1179-9
U 173-1
U66 3 S257 16 03
1
USELI
U4-16 U66-1 U69-1
2
DAO
.316-9 U10-4 1184-13 U66-2
3
DBO
J16-1 1166-3 U80-13
4
DO
J15-49 .314-49 J13-49 312-49
1191-16 1166-4 P15-2
5
DAI
316-10 U10-5 U84-8 1J66-5
6
051
.316-2 U66-6 1180-8
7
Dl
.315-48 .314-48 .313-48 .312-48
1191-4 U66-7 P15-3
8
GND
9
02
.315-47 .314-47 313-47 312-47
1191-15 U66-9 P15-4
10
D82
316-3 1166-10 U80-14
11
DA2
316-11 1110-12 U84-14 U66-11
12
03
J15-46 314-46 313-46 312-46
U91-5 U66-12 P15-5
13
083
316-4 066-13 U80-7
14
DA3
316-12 1166-14 1184-7
15
EN257
U176-14 1166-15 1169-15
16
+5v
1168-19 1168-18 1168-17
U68-16
316-17 J16-18 316-19 316-20
11109-4 11109-7 11109-9 11109-12
1167 3 S257 16 08
i
ZPACE*
Uil-i U174-1S U67-i U131-8 1170-1
2
U67-2 U132-6
3
PAS
1111-2 11174-17 1167-3 U158-6
4
AS
JIS-lO 314-10 313-10 312-10 1167-4
U2-12 013-6 U13-4
5
Zi
1174-1
1171-6
15.49
Apple Computer Inc · 1982
Page 0400 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
1172-6 1367-5 U73-11
6
PA9
1364-22 13155-5 1365-18 1J67-6
7
A9
JI 5-11 J14-11 313-11 312-11 US-4 1374-2 U71-5
U67-7
8
9
Al O
JiS- 12 314-12 313-12 312-12 U128-1 1174-3 U71-4
1167-9
10
PAl O
1364-19 13155-6 1365-19 U67-10
li
Z2
1372-7 U67-ll U73-12
12
All
J 15-13 314-13 313-13 312-13 U128-12 U6-6 U71-3
UI. 50-13 1374-5 1367-12 133-5 13174-5
13
PAll
1364-18 13144-12 1365-20 1367-13 U135-4
14
23
1172-8 1167-14 1373-13
15
U7 0-15 13163-4 1367-15 1363-19 1363-1
16
+5v
1368 3 8304 20 C3
i
IDO
U98-13 1165-33 1397-33 U72-i5
2
IDI
1398-19 U65-32 U97-32 1172-16
3
102
1198-20 1165-31 1197-31 1172-17
4
1D3
U98-21 1365-30 1197-30 U72-18
5
1D4
U98-22 1365-29 1197-29 1372-19
6
1D5
U98-23 1365-23 1397-28 1372-20
7
1D6
1398-24 1165-27 1397-27 1372-21
8
1D7
U98-25 U65-26 U97-26 1372-22
9
EN8304
13176-13 1168-9
10
CND
11
IR*/W
U91-3 1368-11 U158-2 U163-10
12
D7
J15-42 J14-42 313-42 J12-42
13101-5 1391-7 1169-12 P15-9
13
D6
J15-43 314-43 J13-43 312-43
U91-13 1169-9 P15-8
1373-33
U73-]2
1373-31 1373-30 1373-29
U73-28
1373-27
U73-26
U68-12
1168-13
U64-9 U68-1 U64-1O 1368-2
1164-11 1368-3 1164-13 1368-4 1364-14 1368-5
U64-15 1368-6 1364-16 U68-7 U64-17 1368-8
J16-24 U111-12 J16-23 11111-9
15.50
.1
Apple Computer Inc · 1982
Page 0401 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
pc3mpu
14
D5
.115-44 J14-44 .113-44 .112-44 U68-14 .116-22 U111-7
1391-6 U69-7 P15-7
15
D4
.115-45 .114-45 .113-45 .112-45 1368-15 .116-21 U1i1-4
U91-14 U69-4 P15-6
16
D3
J15-46 .114-46 .113-46 J12-46 1368-16 .116-20 U109-12
1391-5 1366-12 P15-S
17
D2
.115-47 .114-47 .113-47 .112-47 1368-17 .116-19 13109-9
1391-15 1366-9 P15-4
18
Dl
.115-48 .114-48 .113-48 .112-48 1368-13 .116-18 13109-7
U91-4 U66-7 P15-3
19
DO
315-49 314-49 J13-49 J12-49 1368-19 .116-17 13109-4 U91-16 U66-4 P15-2
20
+5v
U69 3 S257 16 D2
1.
IJSEL3
134-16 1366-1 1369-1
2
DA4
J16-13 1369-2 1384-17
3
DM
316-5 1369-3 U80-17
4
D4
315-45 J14-45 313-45 312-45
1391-14 U69-4 P15-6
S
DAS
J16-14 1369-5 U84-4
6
DBS
316-6 U69-6 U80-4
7
1)5
J15-44 314-44 313-44 312-44
139 1-6 1369-7 P15-7
8
GND
9
D6
315-43 314-43 313-43 312-43
U91-13 U69-9 P15-8
10
D86
316-7 1369-10 1380-18
11
DA6
J16-15 1369-11 1384-18
12
Dl
315-42 314-42 313-42 312-42
U101-5 U91-7 1369-12 PiS-9
13
D37
316-8 1369-13 1380-3
14
DAl
316-16 U153-5 U84-3 U69-14
U68-15
1368-14 1368-13 1368-12
316-21 316-22 J16-23
.116-24
13111-4 13111-7 13111-9
U111-12
15 51
Apple Computer Inc · 1982
Page 0402 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
appcompL*m
15
EN257
(3176-14 (366-15 (369-15
16
+5V
(370 3 S257 16 07
1
ZPAGE*
Uil-i U174-15 U67-i U131-8 U70-1
2
Z4
(372-9 U70-2 (373-14
3
PAl2
U65-22 TJL3S-9 U70-3
4
Al2
315-14 314-14 313-14 J12-14 (39-12 (3155-11 (3165-14
(370-4 U71-2 U174-6
5
25
(373-15 U70-5
6
PA13
(365-23 (3135-8 U70-6
7
A13
J15-15 314-15 313-15 J12-l5 U128-4 (3155-12 U165-15
(371-1 (370-7 U6-5 U3-6 (3174-7
8
CND
9
A14
315-16 314-16 313-16 312-16 U3-7 (3147-4 U70-9
U6-16 U174-4
10
PAI4
U65-24 (3135-il (370-10
11
Z6
U73-16 U70-11
12
A15
315-17 314-17 313-17 312-17 (33-4 (3147-3 (370-12
(3174-16 U6-7
13
PAI5
(3135-10 (311-4 (370-13 (365-25
14
27
U73-17 U70-14
15
(370-15 U163-4 U67-15 (363-19 (363-1
16
+5v
U71 4 LS133 16 C7
i
A13
J15-15 314-15 313-15 312-15 (3128-4 U155-12 (3165-15
uil-i U70-7 (36-5 (33-6 U174-7
2
Al2
315-14 314-14 313-14 312-14 (39-12 U155-11 (3165-14
U70-4 (371-2 (3174-6
3
All
315-13 314-13 313-13 312-13 (3128-12 U6-6 (371-3
(3150-13 U74-5 U67-12 U3-5 U174-5
4
AlO
315-12 314-12 313-12 312-12 (3128-1 (374-3 (371-4
(367-9
15.52
Apple Computer Inc · 1982
Page 0403 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
ppcomp*m
5
A9
315-11 .114-11 J13-11 312-11 J5-4 U74-2 1.171-5
1167-7
6
A8
315-10 .114-10 .113-10 .112-10 1167-4 U74-1 1171-6
U2-12 ¡.113-6 U13-4
7
Al
J15-9 J14-9 .113-9 J12-9 1113-10 ¡377-4 U76-6
Uil-i U63-3
8
CND
9
U112-1 1171-9
10
A6
.115-8 .114-8 .113-8 .112-8 112-4 1177-3 1176-3
Uil-lO 1163-5 1171-11
11
A6
315-8 314-8 313-8 .112-8 112-4 1177-3 1176-3
1171-10 1163-5 1171-11
12
AIISW*
U165-6 1171-12 U97-8 U178-1 11178-13 U177-15 1187-3
U 155-3
13
- C-FXXX
U71-15 11180-2 U71-14 1171-13 11147-6 U147-9 11165-1
14
C-FXXX
U71-15 U180-2 U71-14 U71-13 U147-6 11147-9 11165-1
15
C-FXXX
Uil-iS 11180-2 1171-14 1171-13 11147-6 11147-9 11165-1
16
+5v
U72 4 58167 24 53
i
CO7X*
11180-6 U77-7 11112-13
2
CLXRD
U72-2 11158-3
3
U72-3 11112-12
4
NO CONN!CTION
5
20
1172-5 1.1132-4 U73-iO
6
Zi
1172-6 1167-5 1173-11
7
22
1172-7 1167-11 1173-12
8
Z3
1172-8 1167-14 1173-13
9
24
1172-9 U70-2 U73-14
10
'(2-1 1172-10 C3-3
11
C4-1 U72-11 '(2-2
12
GND
13
CKIRQ*
1172-13 P.79-2 1197-40
14
PDINT*
35-4 U72-14
11158-1
1172-1
11150-5
11148-13
15 53
Apple Computer Inc · 1982
Page 0404 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
ppcompr
15
IDO
U98-18 065-33 097-33 U72-15 073-33 U64-9 U68-1
16
IDi
U98-19 U65-32 U97-32 U72-16 073-32 U64-1O 068-2
17
1D2
098-20 U65-31 097-31 072-17 073-31 U64-11 068-3
18
1D3
098-21 065-30 097-30 072-18 073-30 U64-13 068-4
19
1D4
098-22 065-29 097-29 072-19 073-29 U64-14 068-5
20
1D5
098-23 065-28 097-28 072-20 U73-28 U64-15 068-6
21
1D6
098-24 065-27 U97-27 072-21 073-27 064-16 068-7
22
1D7
098-25 065-26 U97-26 072-22 U73-26 U64-17 068-8
23
pWP,DN*
U72-23 Q3-3 CZ-i Rb-2
24
U72-24 Qi-i Xi-2
073 4 6522 40 B6
GND
2
ROMSEL1
0165-10 073-2 P19-9
3
RCMSEL2
U73-3 U64-21 P19-8
4
PRIMSTIC
¡173-4 P19-7 0158-9
5
RPR
073-5 P19-6 0180-16
6
RESETLK*
U179-14 073-6 P19-5 U139-5
7
SCRN
U154-13 073-7 P19-4
8
lOEN
073-8 P19-3 0147-10
9
SEL1M
0180-15 0174-2 0150-3 U73-9
10
za
072-5 U132-4 ¡173-10
11
Z1
072-6 067-5 073-11
12
Z2
072-7 067-11 073-12
13
Z3
072-8 U67-14 073-13
14
Z4
072-9 070-2 073-14
15
Z5
U73-15 U70-5
16
Z6
073-16 070-11
P19-2
15 54
-
Apple Computer Inc · 1982
Page 0405 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
1.7
1373-17 U70-14
18
SCO
13160-3 1373-18 U160-5 (3101-1
19
SER
1373-19 13160-8 13161-9
20
+3v
21
IRQ*
U97-21 (365-4 1398-26 (397-9 (373-21
22
IR/W*
1398-28 (397-22 13112-14 U73-22 U163-11 (365-34 U160-12
23
ifDX
13112-5 1373-23 13148-9
24
CS6522
R68-2 1373-24 C59-1 1397-24
25
PRE1M
312-40 .313-40 314-40 315-40 (3119-12 (373-25 ¡3123-5 (397-25 (3139-10 R94-1
26
IDi
(398-23 U65-26 (397-26 (372-22 U73-26 U64-17 U68-8
27
1D6
1398-24 U65-27 (397-27 1372-21 (373-27 U64-16 (368-7
28
I.D5
1398-23 1365-28 1397-28 (372-20 ¡373-28 U64-15 (368-6
29
1D4
¡398-22 U65-29 U97-29 1372-19 1373-29 1364-14 (168-5
30
1D3
1398-21 (365-30 U97-30 1372-18 1373-30 (364-13 (368-4
31
1D2
U98-20 U65-31 1397-31 U72-17 (373-31 1364-11 1368-3
32
¡Dl
1398-19 U65-32 (397-32 U72-16 (373-32 U64-10 1368-2
33
IDO
1398-18 U65-33 U97-33 1372-15 (373-33 (364-9 1368-1
34
RESET*
1365-40 13162-10 U98-4 U97-34 U73-34 U75-15 (379-9 13173-1
35
A3
J15-5 J14-5 .313-5 J12-5 (35-10 (3109-1 13111-1
U97-35 13177-3 1394-3 1375-3 1373-35 1363-12
36
A2
J15-4 .314-4 313-4 312-4 (35-6 13101-9 1397-36
U177-2 U94-2 1375-2 U73-36 U63-14
37
Al
315-3 J14-3 313-3 312-3 U2-1O U97-37 1398-14
(3101-10 (3177-1 U94-1 1373-37 1375-1 U63-16
38
AO
.315-2 314-2 313-2 312-2 (32-6 (397-38 1398-13
U101-Il 1394-13 (373-38 1375-13 (363-18 13177-13
39
SW1/MCNSWUT
R85-2 U169-19 (173-39 U101-3
40
IOLRQ
15.55
I
Apple Computer Inc · 1982
Page 0406 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
U73-40 U155-10
(174 4 LS138 16 36
A8
315-10 314-10 313-10 312-10 (167-4 U74-1 U71-6
U2-12 U13-6 U13-4
2
A9
315-11 314-11 313-11 J12-11 US-4 (174-2 U71-5
(167-7
3
AlO
315-12 314-12 313-12 312-12 (1128-1 (174-3 U71-4
U67-9
4
GPH1
U162-3 U76-4 13141-6 (174-4
5
All
315-13 314-13 313-13 312-13 u128-12 (16-6 (171-3 13150-13 (174-5 1367-12 (13-5 U174-5
6
CXXX
U176-15 (174-6 13150-1 U147-8
7
C7XX*
13176-16 U74-7
8
GND
9
C6XX*
(1176-7 (174-9
lo
(174-10 U176-5
11
IOSEL4*
(174-11 315-1
12
IOSEL3*
(174-12 314-1
13
IOSEL2*
(174-13 J13-1
14
IOSELI*
(174-14 312-1
15
C0Xx*
(177-5 (174-15 U76-5
16
45V
(175 4 9334 16 116
1
AI
315-3 314-3 313-3 312-3 U2-10 (197-37 U98-14
(1101-10 U177--1 (194-1 (173-37 (175-1 (163-16
2
A2
313-4 314-4 313-4 312-4 US-6 (1101-9 U97-36
U177-2 (194-2 U75-2 (173-36 U63-14
3
A3
315-5 314-5 J13-5 312-5 US-10 13109-1 UlIl-I
U97-35 0177-3 (194-3 (175-3 U73-35 (163-12
4
TEXT
U87-23 (173-4
S
MIX
1387-1 (175-5
6
PACE2
15.56
Apple Computer Inc · 1982
Page 0407 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
ópp*acomP
1387-4 1175-6
7
HIRES
087-2 1375-7
8
GND
9
POLO
0105-16 U75-9
10
P01.2
13160-4 0105-2 075-10
11
POLEN
0105-3 073-11
12
AXCO
0161-5 075-12 0105-1
13
AO
315-2 314-2 J13-2 312-2 02-6 U97-38 098-13
11101-il 094-13 073-38 1373-13 063-13 U177-13
14
c05x*
077-10 075-14
15
RESET*
065-40 11162-10 098-4 U97-34 1373-34 1375-15 U79-9 0173-1
16
+5v
U76 4 LS138 16 1(4
I
A4
315-6 314-6 313-6 J12-6 139-6 077-1 1376-1 0112-2 1363-9
2
AS
315-7 314-7 313-7 312-7 09-10 U76-2 077-2 0112-3 063-7
3
A6
315-8 314-8 313-8 J12-8 02-4 U77-3 U76-3
1371-10 U63-5 071-11
4
GNU
11162-3 U76-4 13141-6 U74-4
5
cOxx*
1177-5 074-15 076-5
6
A7
315-9 314-9 313-9 312-9 1313-10 1177-4 1376-6 Uil-i U63-3
7
8EL6551*
098-3 1176-7 0148- 12
8
CND
9
DEVSEL6*
1394-14 076-9 U91-2
10
DEVSEL5*
0177-14 U76-10
11
DEVSEL4*
315-41 1376-11
12
DEVSEL3*
314-41 1176-12
13
DEVSEL.2*
J13-41 076-13
15.57
s,
Apple Computer Inc · 1982
Page 0408 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
- u
14
DEVSELI*
312-41 U76-14
15
NO CONNECTION
16
+3V
Uil 4 LS138 16 Kl
i
A4
313-6 314-6 313-6 312-6 U9-6 1377-1 ¡376-1
11112-2 U63-9
2
AS
315-7 314-7 313-7 312-7 ¡39-10 1376-2 1377-2
U112-3 ¡363-7
3
A6
315-8 314-8 J13-8 312-8 U2-4 1371-3 1376-3 U71-1O 1163-5 U71-11
4
Al
J15-9 314-9 J13-9 312-9 ¡313-10 1377-4 ¡376-6
U71-7 U63-3
5
cOxx*
1177-5 1174-15 1376-5
6
GPR2
U150-2 ¡377-6 U162-4
7
CUlX*
U180-6 1377-7 U112-13 U158-1 U72-1 ¡3150-5 13148-13
8
CND
9
CO6X*
¡3101-7 1377-9
10
CO5X*
¡377-10 U75-14
11
C04X*
1177-11 11181-6
12
SPKR*
11173-11 ¡377-12
13
CO2X*
315-39 U77-13 314-39 313-39 312-39
14
CLRSTRB*
¡3106-1 1177-14
15
K3D*
U109-15 ¡3111-15 ¡377-15
16
+5v
1378 5 LS374 20 E3
1
ENHREG*
11175-11 ¡378-1
2
DC7
¡379-2 1378-2 1382-14 11136-4
3
DV?
1186-3 U78-3 1180-2 U84-2 U136-3 U136-2
4
DVS
U82-3 1386-4 1378-4 1381-3 1380-5 1184-5
5
DC5
1179-4 1378-5 1182-13
15.58
Apple Computer Inc · 1982
Page 0409 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
6
DC3
1579-10 U78-6 U82-12
7
DV)
U82-2 1586-7 U78-7 1581-2 1580-6 1584-6
8
DVL
U82-1 1586-8 1578-8 USi-i 1580-9 U84-9
9
DCI
1579-12 1378-9 1582-11
lo
CND
11
QO
Uil 9-13 15150-10 U117-15 U131-2 U78-11
12
DCO
1379-14 1578-12 1581-14
13
IWO
1582-17 U86-13 1578-13 1581-17 1380-12 1584-12
14
DV2
1582-16 1586-14 1578-14 1581-16 1580-15 U84-13
15
DC2
1579- 11 1578-15 U81-13
16
DC4
1379-5 1578-16 U81-12
17
DV4
U82-15 1586-17 U78-17 U81-15 1580-16 1584-16
18
DV6
U78-18 1586-18 1582-4 1581-4 U80-19 U34-19
19
DC6
1578-19 1579-3 1581-11
20
+3v
1579 5 74166 16 F4
CND
2
DC7
1579-2 1578-2 U82-14 15136-4
3
DC6
1378-19 1579-3 U81-1l
4
DC5
U79-4 1578-5 1582-13
s
DC4
1579-5 1578-16 U81-12
6
13153-11 Ui 9-6
7
CI4M
15146-6 Ri00-1 U117-l0 U119-9 U79-7
8
GND
9
RESET*
1565-40 15162-10 1598-4 U97-34 1573-34
15173-1
10
DC)
U79-10 1578-6 1582-12
11
DC2
U79-l1 1578-15 1581-13
12
DCI
U79-12 1578-9 U82-1l
U85-11
1575-15
U79-9
15.59
Apple Computer Inc · 1982
Page 0410 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
13
BTU
1388-3 U85-18 13162-5 1379-13 1383-4 U83-1
14
DCO
1379-14 1378-12 U81-14
15
LDPS*
U117-9 U79-15 U131-6
16
+5V
Uso 5 LS374 20 F2
i
VBEN
USO-i 13132-11
2
DV7
1386-3 1378-3 1380-2 1384-2 13136-3 13136-2
3
DB7
316-8 U69-13 1380-3
4
DB5
316-6 1369-6 1380-4
5
DV5
1382-3 1386-4 U78-4 1381-3 1380-5 1384-5
6
DV3
U82-2 1386-7 1378-7 138 1-2 1380-6 1384-6
7
DB3
J 16-4 U66-13 1380-7
8
DBL
Ji 6-2 U66-6 U80-8
9
DV1
U82-1 U86-8 1378-8 138 1-1 1380-9 1384-9
10
OND
11
C1M
U 132-2 U135-1 13119-10 13123-11 13180-5 1398-27
1384-11
12
'wo
U82-17 U86-13 1378-13 U81-17 1380-12 1384-12
13
DBO
316-1 1366-3 U80-13
14
D82
316-3 1366- 10 U80-14
15
DVZ
U82-16 1386-14 1378-14 1381-16 1380-15 1384-15
16
DV4
1382-15 1386-17 1378-17 1381-15 1380-16 1384-16
17
DB4
316-5 1369-3 1380-17
18
DB6
J 16-7 U69-10 U80-18
19
DV6
1378-18 U86-18 1382-4 1381-4 U80-19 U84-19
20
+5V
1380-11
USi 5 2114 18 ES
i
DV1
1382-1
U86-8
U73-8
U81-1
U80-9
1384-9
15.60
Apple Computer Inc · 1982
Page 0411 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
I uJdwddL
Z E '7 S
9 ¿ S 6 01 TI Zt El
t
St 91 ¿1 81
Z80 5 7hZ 21
t
Z t
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ç 9 ¿
6 01
SAD Z-ZBfl
SAD
¿-980
¿-81.0
Z-190
9-020
9-'7Bfl
E-Z8fl 7-980 '7-BLD 5-190 5-080 S-'78fl 9Ml
91-81.0 81-98(1 7-ZBfl '7-18(1 61-08(1 61-'îBll
VA
E-TZlfl S-SLTf1 II-9110 5-ZBfl S-180 ta
Z-TZIfl 9-51.1(1 71-911(1 9-Z80 9-18(1
1-TZtfl L-5110
S3IUQ
01-ESO 8-9ZTfl
ET-9110 SI-EVO 71-5811
8-Z8fl 8-19(1 ¿1-1.9(1
L-Z90
L-180
0t-Z8fl 93G
61-BIO
91-51.1(1 01-18(1
t-610 II-190
9-'7'7Tfl
5-61.0 91-810 Z1-TBfl
11-61.0 51-81.0 Cl-190
'71-61.0
7AG
SI-Z9fl
ZAG 91-Z80
OAU
¿1-ZBfl
ZI-9L0
¿T-9911
71-990
LI-9811
71-180
LI-9111 '71-BLD Et-øLfi
SI-190 91-180 ¿T-120
91-08(1
SI-020
ZT-OBfl
91-'78fl ÇT-'79fl Z1-'7Bfl
tAG
1-ZBfl 9-99(1 2-81.0 1-180 6-080 6-?Bfl SAC
Z-Z9fl
SAC
t-Z8fl
L-990 7-990
¿-BUt
'7-BL,fl
Z-190 9-080 Bfl t-1 S-080
9-'7Bfl
c-'790
9ACI
81-Lfl VA
BI-980
7-t2fl
7-19(1
61-08(1
6t-8fl
£-TZIfl S-cLin II-9110 S-ZBLi c-190 ta
Z-TZTfl 9-SLID 71-8110 9-Z80 9-12(1
1-TZlft L-SLIO ET-8110 51-EBD '71-59(1 L-Z9fl L-190
01-E8fl 8-9Z10 9-Z8fl 9-18(1 ¿1-L8fl
ON LNNO) NOI
,ITZazt
Apple Computer Inc · 1982
Page 0412 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
pk - m
1382-10 13175-16 U81-10 U144-6
11
DCI
1379-12 1378-9 1382-11
12
DC3
1379-10 U78-6 1382-12
13
DC5
U79-4 1378-5 U82-13
14
DC7
1379-2 1378-2 1382-14 13136-4
15
DV4
1382-15 U86-17 1378-17 1381-15 1380-16 1384-16
16
DV2
1382-16 086-14 U78-14 U81-16 1380-15 1384-15
17
DVO
1382-17 1386-13 U78-13 U81-17 U80-12 1384-12
18
+5V
1383 5 S151
I
2 3 4
5 6 7
8 9 lo
11
12 13 14
15 16
16 J3 3T0
U88-3 1385-13 U162-5 1379-13 U83-4 1383-1 BT1
(188-6 1383-2 U85-19 U85-17 BTO*
1383-3 U162-6 rro
088-3 1385-18 13162-5 1379-13 1383-4 1383-1
wrwx
1185-13 1383-5
NO CONNECTION BL
097-16 1383-7 1385-7 UL26-16 CND
AutORES
1383-9 U87-16 DRIRES
1383-10 U126-8 ¡382-8 1381-8 1387-17 LNV
U83-11 13173-5 CND GND
Vc U121-L 13175-7 13118-13 U83-15 083-14 U82-7
Vc 13121-1 ¡3175-7 13118-13 U83-15 U83-14 U82-7 +5V
U81-7
¡381-7
¡384 5 LS374 20 E2
t
VAEN
U84-1
2
DV7
1386-3
3
DAl
13132-3 ¡378-3 ¡380-2
1384-2
¡3136-3
0136-2
15.62
Apple Computer Inc · 1982
Page 0413 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
pp - ,
J16-16 11153-5 1184-3 U69-14
4
DA5
JI'S-14 1169-5 1184-4
5
DV5
U82-3 1186-4 1173-4 1181-3 1180-5 1184-5
6
DV3
1182-2 1186-7 1178-7 1181-2 1180-6 1184-6
7
DA3
J16-12 1366-14 U84-7
8
DAl
.116-10 UI0-5 U84-8 1166-5
9
DVI
1182-1 1186-8 1178-8 Usi-i 1180-9 1184-9
10
CND
u
ci>t
11132-2 11135-i 11119-10 U123-ll 11180-5 1198-27 1180-11
1184-11
12
DVO
1382-17 1186-13 1178-13 U81-17 1180-12 1384-12
13
DAO
.116-9 1110-4 U84-13 1166-2
14
DA2
.116-11 1110-12 1184-14 1166-11
15
DV2
1182-16 1186-14 1178-14 1181-16 1130-15 1184-15
16
DV4
1182-15 1186-17 1173-17 1131-15 1180-16 1384-16
17
DA4
J16-13 1169-2 1184-17
13
DA6
J16-15 1169-11 1184-13
19
DV6
1173-18 1386-18 1182-4 1181-4 U80-19 1184-19
20
+3V
1185 5 LS374 20 C2
CND
2
QO*
11152-12 11144-2 1185-2
3
Q3
.114-37 1185-3 .115-37 .113-37 .112-37 11117-12 R93-1
11154-2
4
CIM*
11153-2 11123-2 11119-11 11120-2 11118-2 11116-2 11114-2
11126-11 1183-4 U144-5 11132-12 11150-4
5
D1M*
1185-5 1186-11
6
DEL
1185-6 1188-15
7
EL
Uq7-16 1183-7 1185-7 U126-16
3
15.63
Apple Computer Inc · 1982
Page 0414 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
cippkz «wí
inc.
U121-7 115-5 11114-12 1185-3
9
DM2
11132-9 1185-9
10
CND
11
C14I
11146-6 R100-1 11117-10 U119-9 1179-7 1185-11.
12
BTMIJXD
1185-12 1189-1
13
3TMUX
1185-13 1183-5
14
BT2
1188-10 U85-14 U85-16
15
3T3
U88-13 U85-15
16
8T2
1188-10 1185-14 1185-16
17
BTL
1188-6 1183-2 U85-19 U85-17
18
BTO
1188-3 U85-18 11162-5 1179-13 1183-4 U83-1
19
STI
1188-6 1183-2 U85-19 U85-17
20
+5V
1186 5 LS374 20 F3
i
0E374
1187-15 1186-1
2
DX7
U89-4 1186-2 P8-6
3
DV7
1186-3 1173-3 1180-2 1184-2 11136-3 11136-2
4
1182-3 1186-4 1173-4 U81-3 1180-5 1184-5
5
DX5
1189-12 U86-5 P8-3
6
DX3
U88-2 (186-6 P13-4
7
DV3
1182-2 1186-7 1178-7 1181-2 1180-6 1184-6
8
DV1
1182-1 1186-8 1178-8 1181-1 1180-9 1184-9
9
Dxl
1188-11 1186-9 P13-S
10
GND
11
DIM*
1185-5 (386-11
12
DXO
1188-14 1186-12 P13-2
13
OVO
1182-17 U86-13 (378-13 1181-17 1180-12 1184-12
14
DVZ
1182-16 1186-14 1178-14 1181-16 U80-15 1184-15
15.64
I
Apple Computer Inc · 1982
Page 0415 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
pcompm
13
DX2
(183-5 (386-15 P13-3
16
DX4
(189-13 (186-16 P8-4
17
DV4
(382-15 (186-17 U73-17 U81-15 (180-16 (334-16
13
DV6
(178-13 (386-18 (182-4 (381-4 (180-19 (184-19
19
DX6
(189-5 (186-19 P8-5
20
+3V
(187 5 2316 24 341-0032 G5
i
4IX
U87-1 (175-5
2
HIRES
(187-2 (175-7
3
AIISW*
U165-6 (171-12 (197-8 LUiS-1 (1178-13 U177-15
(1155-3
4
PACE2
(187-4 U75-6
5
V3L
(3175-15 U87-5 (197-19 (197-13 U121-19 U154-6
6
FORCPAGE
U87-6 P10-2 J20-7
7
+5v
8
CND
9
PC2*
(187-9 (113-13
10
SEL374
(187-LO U132-13 (1132-1
11
COLORKILL*
(1147-13 U87-11 J20-9
12
GND
13
AHIRES
(388-1 (187-13 (1141-1
14
CH8O*
(3139-9 U153-12 U87-14
15
0E374
(187-15 (186-1
16
AIILORES
(183-9 (187-16
17
DHIRES
(183-10 (1126-8 U82-8 (381-8 U87-17
13
NO CONNECTION
19
V4
(387-19 Ui-2 (1154-4 (3120-12 UI-li
20
GND
21
+5v
22
V2
(3120-14 (1154-10 U87-22
(187-3
15.65
Apple Computer Inc · 1982
Page 0416 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
I
23
24
TEXT
tJ87-23
+5v
U75-4
J88 5 LS157 16 G3
I
AHIRES
U88-1 U87-13 U141-1
2
DX)
U88-2 1J86-6 P13-4
3
BTU
1188-3 U85-18 U162-5 U79-13
4
U89-3 1188-4
5
0X2
1188-5 1186-15 P13-3
6
BT1
U88-6 1183-2 U85-19 1185-17
7
1189-6 1188-7
8
CND
9
1189-11 1188-9
10
BT2
1188-10 1185-14 U85-16
lt
0X1
1188-11 U86-9 P13-S
12
1189-14 1188-12
13
BT3
1188-13 1185-15
14
DXO
tJ88-14 1186-12 P13-2
15
DBL
U85-6 1188-15
16
+5V
U83-4
U83-1
1189 5 LS399 16 1(3
I
BTMUXD
1185-12 1189-1
2
RGB8
J20-5 P4-S P17-2 P3-6 U89-2
3
1189-3 1188-4
4
0X7
1189-4 1186-2 P8-6
5
0X6
1189-5 1186-19 P8-5
6
1189-6 U88-7
7
RGB4
P4-4 P17-4 P3-S P10-7
J20-4
3
GND
9
C1(DSP
11141-11 U89-9
10
RGB2
.120-2 P17-6 P4-3 P3-4
NO-3
U90-4 P10-6
1190-11 1190-3
U90-10 1189-7
1190-5 1190-13
15.66
Apple Computer Inc · 1982
Page 0417 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
1189-10
11
1189-11 1188-9
12
DXS
1189-12 1186-5 28-3
13
DX4
1189-13 1186-16 P8-4
14
U89-14 1188-12
15
KGB ¡
1189-15 217-8 24-2 P3-3 320-6 P10-4 1190-6
1190-12
16
+5v
U90 5 LS153 16 tfi
1
GND
2
C3.5M*
U135-13 U119-6 11147-1 1190-2
3
RCB8
.320-5 P4-5 P17-2 P3-6 P10-3 1190-11 1190-3 U89-2
4
RCB4
P4-4 P17-4 P3-5 P10-7 1190-4 U90-10 1189-7 J20-4
5
RG32
.320-2 P17-6 P4-3 P3-4 P10-6 1190-5 1190-13
1189-10
6
RGBI
1189-15 P17-8 P4-2 P3-3 .320-6 P10-4 1190-6
1190-12
7
NTSCA
P3-i U90-7
8
GND
9
NTSCB*
11163-9 1190-9
10
RGB4
P4-4 P17-4 P3-S P10-7 1190-4 1190-10 1189-7 J20-4
11
RG88
.320-5 P4-5 P17-2 P3-6 P10-3 U90-11 1190-3
1189-2
12
RGBI.
1189-15 P17-8 P4-2 P3-3 .320-6 P10-4 U90-6
1190-12
13
RGB2
J20-2 P17-6 P4-3 P3-4 P10-6 1190-5 U90-13
1189-10
14
C7M
.315-36 .314-36 J13-36 .312-36 11141-9 11119-2 1190-14
15
CND
16
+3V
11146-12
J91 6 LS323 20 KlO
15.67
Apple Computer Inc · 1982
Page 0418 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Ícacomput
1
1192-7 1191-1.
2
DEVSEL.6*
(194-14 1176-9 1191-2
3
IR*/W
(191-3 U68-11 11158-2 U163-10
4
DI
J15-48 314-48 313-48 312-48 1168-18 316-18 11109-7
1191-4 U66-7 P15-3
5
03
315-46 314-46 313-46 312-46 (168-16 316-20 11109-12
(191-5 U66-12 P15-5
6
D5
315-44 J14-44 313-44 312-44 (168-14 316-22 (1111-7
(19 1-6 1169-7 P15-7
7
07
315-42 314-42 313-42 312-42 (168-12 316-24 11111-12
11101-5 1191-7 (169-12 P15-9
8
1192-2 (191-8
9
1192-9 119 1-9 R66-1
10
CND
11
DWRPROTT
11167-17 (191-11
12
Q3*
U93-9 U136-12 U91-12 (1117-11 11117-2 11117-3 11135-12
(3131-5 R102-2 R103-1 11146-1
13
D6
315-43 314-43 J13-43 312-43 1168-13 J16-23 11111-9
1191-13 1169-9 P15-8
14
04
315-45 J14-45 313-45 J12-45 1168-15 316-21 11111-4
119 1-14 1169-4 P15-6
15
02
J15-47 314-47 313-47 312-47 1168-17 316-19 11109-9
(391-15 1166-9 P15-4
16
DO
315-49 314-49 313-49 312-49 1168-19 316-17 11109-4
(191-16 U66-4 P15-2
17
NO CONNECTION
18
U92-8 (191-18
19
1192-6 U91-19
20
+5V
1192 6 S471 20 341-0023 LUI
1
(393-15 U92-1
2
U92-2 (391-8
3
(392-3 (194-11
4
11163-13 U94-12 (392-4
5
11161-11 1192-5 R67-2
6
U92-6 U91-19
7
(392-7 (191-1
8
1192-8 (191-18
9
U92-9 (391-9 R66-1
15.68 0'
Apple Computer Inc · 1982
Page 0419 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
pp-1
lo
CND
11
1393-6 1392-11
12
U93-14 1392-12
13
1393-4 1392-13
14
U93-3 1392-14
15
MOTON*
13179-1 1392-15 11178-15 R65-2 13164-12 U92-16
16
HOTON*
13179-1 U92-15 13178-15 R65-2 13164-12 1392-16
17
1393-7 1392-17
18
1393-5 U92-18
19
DWRDATA
13166-18 1192-19 1393-2
20
+5v
1393 6 L.S174 16 K12
I
SSS
R107-2 13106-2 11106-4
13114-7 13116-5
2
DWRDATA
13166-lS 1392-19 1393-2
3
1393-3 1192-14
4
1393-4 1392-13
3
U93-5 1392-13
6
1393-6 1392-11
7
1193-7 1392-17
8
CND
9
Q3*
1193-9 U136-12 1391-12
13131-5 R102-2 R103-1
10
13161-13 1393-10
11
1393-12 U161-12 1393-11
12
1393-12 13161-12 1393-11
13
DRDATA
U166-17 1393-13
14
1393-14 1392-12
15
1393-15 1392-1
16
+5v
13106-10
13117-11 13146-1
11106-13 U93-1 13117-2 U117-3
13114-10 13135-12
1194 6 9334 16 1.13
I
Al
315-3 J14-3 J13-3 312-3 132-10 1397-37 1398-14
13101-10 13177-1 1394-1 U73-37 1375-1 1363-16
2
42
315-4 314-4 313-4 312-4 135-6 11101-9 U97-36
U177-2 1394-2 1375-2 U73-36 1363-14
3
A3
J15-5 314-5 313-5 312-5 135-10 13109-1 13111-1
1397-35 13177-3 1394-3 1375-3 1373-35 U63-12
4
VAl
11166-12 13175-4 U94-4
5
VSI
15.69
Apple Computer Inc · 1982
Page 0420 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
U167-12 U175-3 ¡.194-5
6
VCI
¡3166-13 U175-2 ¡394-6
7
PDPIi3
¡3167-13 ¡394-7
8
CND
9
MOTEN*
¡3164-11 U94-9
lo
DEXT*
¡3167-18 ¡394-10 ¡3178-2 U163-1
11
¡392-3 ¡394-11
12
U163-13 U94-12 ¡392-4
13
AO
J15-2 314-2 J13-2 312-2 ¡32-6 ¡397-38 ¡398-13
ulol-li ¡394-13 U73-38 ¡375-13 U63-18 U177-13
14
DEVSEL6*
U94-14 ¡376-9 ¡391-2
15
IORESET*
312-31 313-31 314-31 315-31 P14-6 ¡3164-2 ¡3164-4
U96-4 U94-15
16
+5v
¡396 6-8 556 14 L10
i
NO CONNECTION
2
DTIM
R31-1 U164-1O
C7-2
¡396-2
¡396-6
3
NO CONNECTION
4
IORESET*
312-31 313-31 314-31 315-31 P14-6 U164-2 U164-4
¡396-4 ¡394-15
5
MOTON
¡3164-13 ¡396-5
6
DT1M
R.31-1 ¡3164-10 C7-2 ¡396-2 ¡396-6
7
CND
8
U96-13 U96-12 U96-8 R40-2 X2-1 C18-1 Cil-1
X.3-1 C75-1
9
¡396-9 ¡3139-1
10
¡396-10 ¡3162-2 ¡3139-2
11
NO CONNECTION
12
U96-13 ¡396-12 ¡396-8 R40-2 X2-1 C18-1 C17-1
X3-1 C75-1
13
¡396-13 ¡396-12 U96-8 R40-2 X2-1 C18-1 Cil-1
X3-1 C75-1
14
+3V
¡397 7 6522 40 35
1
GND
2
BKSW1
¡397-2 ¡310-3
3
BKSW2
¡397-3 ¡310-6
15 70
Apple Computer Inc · 1982
Page 0421 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
4
BKSW3
1197-4 UlO-li
5
NO CONNECTION
6
IRQ4*
U97-6 315-30 P2-3 11148-5
7
IP.Q3*
1197-7 314-30 P2-4 U148-4
8
AIISW*
11165-6 U71-12 U97-8 11178-1 U178-13 11177-15 1187-3
Ui 55-3
9
IR
1197-21 U65-4 1198-26 1197-9 U73-21
lo
SNDO
P9-i U97-lO
Il
SNDI
P9-6 1197-11
12
SND2
P9-S 1197-12
13
SND3
P9-4 U97-13
14
SND4
P9-3 1197-14
15
SND5
P9-2 1197-15
16
BL
1197-16 U83-7 U85-7 11126-16
17
IONML*
J15-29 1197-17 314-29 313-29 11139-13 312-29
18
VBL
11175-15 1187-5 1197-19 U97-18 11121-19 11154-6
19
VBL
11175-15 U87-5 1197-19 1197-18 11121-19 U154-6
20
+5V
21
IRQ*
U97-21 1165-4 U98-26 1197-9 U73-21
22
IRIW*
1198-28 1197-22 U112-14 1173-22 U163-11 1165-34 11160-12
23
1197-23 U148-1O U112-6
24
CS6522
R68-2 1173-24 C59-i 1197-24
25
PRE1M
312-40 313-40 314-40 J15-40 11119-12 U73-25 11123-5
1197-25 11139-10 R94-1
26
1D7
U98-25 U65-26 1197-26 1172-22 1173-26 U64-17 1168-8
27
1D6
U98-24 U65-27 1197-27 1172-21 1173-27 1164-16 1168-7
28
T.D5
U98-23 U65-28 U97-28 1172-20 U73-28 1164-15 U68-6
29
1D4
1198-22 1165-29 1197-29 1172-19 U73-29 1164-14 1168-5
15.71
Apple Computer Inc · 1982
Page 0422 of 0730
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- -Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
30
1D3
1398-21 (365-30 1197-30 (372-18 (373-30 1.164-13 1368-4
31
1D2
1398-20 U65-31 U97-31 U72-17 1373-31 1364-11 1368-3
32
IDI
1398-19 U65-32 1197-32 1372-16 (373-32 1364-10 1368-2
33
IDO
1398-18 (365-33 1197-33 1172-15 1373-33 (364-9 (368-1
34
RESET*
U65-40 (3162-10 (398-4 U97-34 U73-34 1175-15 U79-9
Uil 3-1
35
A)
315-S J14-5 313-5 312-5 US-10 U109-I 13111-1
1397-35 (3177-3 U94-3 U75-3 (173-35 U63-12
36
A2
315-4 314-4 313-4 312-4 US-6 13101-9 1397-36
13177-2 U94-2 (375-2 1373-36 U63-14
37
Al
315-3 314-3 313-3 312-3 132-10 (397-37 1398-14
(3101-10 (3177-1 U94-1 1373-37 U75-1 (363-16
38
AO
315-2 314-2 313-2 312-2 132-6 U97-38 (398-13
13101-11 (394-13 U73-38 U75-13 (363-18 (3177-13
39
KBDLNT*
U1O6-6 (397-39
40
CKIRQ*
1372-13 R79-2 U97-40
1398 7 6531 28 B2
i
GND
2
+5V
3
SEL.6551*
1398-3 (376-7 13148-12
4
RZSET*
1365-40 U162-i0 (398-4 (397-34 U73-34 1375-15 U79-9
(3173-1
S
NO CONNECTION
6
ACIACLK
U98-6 (3140-S
7
NO CONNECTION
B
RTS*
U99-12 U98-8
9
CTS*
U 100-6 1398-9
10
TXD*
1399-4 U98-1O
11
DTR*
U99-9 (398-il
12
RXD*
U100-3 1398-12
13
AO
315-2 J14-2 J13-2 312-2 U2-6 (397-38 U98-13
15.72
/
Apple Computer Inc · 1982
Page 0423 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
éczu
U101-li 1394-13 1373-38 1375-13 U63-18 13177-13
14
Al
J15-3 J14-3 J13-3 J12-3 U2-1O U97-37 1398-14
13101-IO 13177-1 1394-1 1373-37 1375-1 1363-16
15
+5v
16
DCD*
13100-11 U98-16
17
DSR*
U100-8 U98-17
18
IDO
1398-18 U65-33 1397-33 1372-15 U73-33 U64-9 1368-1
19
IDi
1398-19 U65-32 U97-32 1372-16 1373-32 1364-10 1368-2
20
102
1398-20 1365-31 1397-31 1372-17 U73-31 1364-11 1368-3
21
103
098-21 1365-30 1397-30 1372-18 U73-30 U64-13 1368-4
22
1D4
1398-22 U65-29 1397-29 U72-19 1373-29 1364-14 U68-5
23
11)5
1398-23 U65-23 1397-28 U72-20 U73-28 U64-15 1368-6
24
106
1398-24 U65-27 1397-27 1372-21 1373-27 1364-16 1368-7
25
11)7
1398-25 U65-26 1397-26 1372-22 1373-26 U64-17 1368-8
26
IRQ*
U97-21 U65-4 U98-26 1397-9 1373-21
27
C1M
U132-2 U135-1 13119-10 (3123-11 13180-3 U98-27 1380-11
1384-11
28
IR/w*
U98-28 1397-22 U112-14 U73-22 13163-11 1365-34 13160-12
1399 7 1488 14 72
1
-12V
2
NO CONNECTION
3
NO CONNECTION
4
TXD*
1399-4 1398-10
5
+5v
6
PTXD
13172-12 1399-6
7
GND
8
PDTR
U172-17 1399-8
9
DTR*
1399-9 U98-11
10
+3V
11
PRTS
0172-14 U99-11
12
RTS*
(199-12 U98-8
15.73
4/
Apple Computer Inc · 1982
Page 0424 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
pcompu
13
+5v
14
+12v
U100 7 1489 14 K2
1
PRXD
13172-13 U100-1
2
NO CONNECTION
3
RXD*
U100-3 ¡198-12
4
PCTS
R87-2 ¡1172-15 11100-4
5
NO CONNECTION
6
CTS*
WOO-6 U98-9
7
CND
8
DSR*
13100-8 ¡198-17
9
NO CONNECTION
10
PDSR
R88-2 U172-16 13100-10
11
U100-1l 1398-16
12
NO CONNECTION
13
PDCD
R89-2 U172-18 13100-13
14
+5V
U101 7 LS251 16 L7
1
scp
11160-3 1173-18 13160-5 ¡flOt-1
2
SW2UP
11101-2 ¡3169-14
3
SWI/HCNSWUF
R85-2 11169-19 1173-39 ¡1101-3
4
SWOCIF
11101-4 11169-13
5
D7
315-42 J14-42 113-42 J12-42 1168-12 J16-24 U1l1-12
U1O1-5 1191-7 1369-12 P15-9
6
110 CONNECTION
7
CO6X*
11101-7 1377-9
3
GND
9
A2
J15-4 J14-4 J13-4 J12-4 135-6 11101-9 U97-36
11177-2 U94-2 1175-2 U73-36 1163-14
10
Al
J15-3 J14-3 J13-3 J12-3 112-10 ¡197-37 1398-14
11101-10 ¡1177-1 1394-1 ¡373-37 1175-1 1163-16
11
AO
JL5-2 J14-2 J13-2 J12-2 U2-6 1197-38 1198-13
11101-11 1194-13 1173-38 U75-13 1163-18 U177-13
15.74
Apple Computer Inc · 1982
Page 0425 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
12
MUX1
13101-12 ¡3175-14 135-13
13
PDLOT*
¡3101-13 U1O5-7 R57-2
14
IRQI*
13101-14 312-30 P2-i ¡1148-1
15
IRQ2*
13101-15 313-30 P2-6 13148-2
16
+5V
13103 7 380N-8N 8 Mii
i
NO CONNECTION
2
C78-1 13103-2
3
CND
4
CND
5
CND
6
R69-2 13103-6
7
+12V
&
C13-1 U103-8
R.34-2
R.36-i
13105 7 9708 16 M9
i
AXCO
13161-5 U75-12 ¡3105-1
2
PDL.2
13160-4 U105-2 1375-10
3
PDLEN
U105-3 ¡375-11
4
TCAP
C15-i 13105-4
5
GND
6
13105-6 R39-2 C9-1
7
PDLOT*
U101-13 ¡3105-7 R57-2
8
13105-8 R37-2 R38-1 C76-i
9
NO CONNECTION
10
R9-1 Ti-i Xi-1 13105-10
11
Y1/XCOUF
13161-6 U169-17 ¡3105-11
12
PX1/SER
¡3105-12 13161-8 ¡3160-9 13169-18
13
YOU?
U105-13 U169-15
14
+3V
15
XOUF
¡3105-15 U169-12
16
PDLO
13105-16 1375-9
13106 8 LS74 14 Rl!
1
CLRSTRB*
13106-1 1377-14
2
853
15.75
J
Apple Computer Inc · 1982
Page 0426 of 0730
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- Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
9.107-2 13106-2 11106-4 U106lO 11106-13 1193-1 11114-10
11114-7 U116-5
3
11139-3 U106-3
4
S5B
9.107-2 11106-2 11106-4 U106-1O U106-13 1193-1 11114-10
U114-7 13116-5
5
11106-5 11111-14
6
KBDINT*
11106-6 1197-39
7
CND
8
NO CONNECTION
9
KAPPLEII*
11106-9 X3-2 11111-6
10
S5B
R107-2 U106-2 11106-4 11106-10 U106-13 1193-1 11114-10
11114-7 U116-5
11
ANYKEf
11107-4 R40i X2-2 13106ii U109-3
12
APPLEII*
J7-5 Pli-5 U106-12 U164-5
13
85B
9.107-2 13106-2 11106-4 11106-10 11106-13 1193-1 11114-10
U114-7 11116-5
14
+5v
11107 8 AY3600 40 H14
i
C16i 11107-1
2
11107-2 C16-2 R47-2
3
U107-3 947-1
'e
ANYKEY
11107-4 9.40-1 X2-2 11106-11
5
NO CONNECTION
6
KSEIFT*
U107-6 U109-6
7
ASCII7
U107-7 11111-13
8
ASCII6
11107-8 UllilI
9
ASCIIS
11107-9 11111-5
10
ASCII4
11107-10 11111-2
11
ASCII3
11107-11 U109-14
12
ASCII2
11107-12 11109-11
13
ASCIII
11107-13 U109-5
14
ASCIIO
11107-14 U109-2
15
CNDF
16
DTRDY*
11109-3
15.76
Apple Computer Inc · 1982
Page 0427 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
,pkzcomp
U107-16 U162-1
17
KYO
J7-1 11107-17
13
ICTI
37-2 U107-18
19
KY2
37-4 U107-19
20
ICY3
J7-6 U107-20
21
CY4
37-8 11107-21
22
KY5
37-10 U107-22
23
Y6
37-23 U107-23
24
KY7
37-2.5 11107-24
25
KYB
37-12 11107-25
26
KY9
37-22 11107-26
27
-12FV
28
CONTROL*
37-11 11179-13 11107-28 11109-10 Pli-2
29
SHIF*
J7-24 pli-6 11107-29
30
+SFV
31
11107-31 C22-1
32
NO CONNECTION
33
KX7UF
11171-14 11107-33
34
KX6UF
11171-19 11107-34
35
KXSUF
11171-16 11107-35
36
KX4tF
U171-18 11107-36
37
10C3U?
11171-17 11107-37
38
KX2UY
11171-13 11107-38
39
KX1UF
11171-15 U107-39
40
IOUF
11171-12 U107-40
11109 8 LS257 16 312
1
A)
J15-5 314-5 313-5 312-5 US-10 U109-1 11111-1
1197-35 U177-3 1194-3 1175-3 1173-35 1163-12
2
ASCIIO
11107-14 U109-2
15.77
Apple Computer Inc · 1982
Page 0428 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
- pp u
3
ANYKEY
U107-4 R40-1 X2-2 11106-ti 11109-3
4
00
315-49 314-49 J13-49 312-49 1168-19 J16-17 11109-4
LJ91-16 1366-4 P15-2
5
ASCIX1
11107-13 13109-5
6
KSHIFT*
11107-6 13109-6
7
Dl
J15-48 314-48 313-48 312-48 1168-1$ J16-18 U109-7
U91-4 U66-7 P15-3
8
CND
9
02
J15-47 J14-47 313-47 J12-47 1168-17 316-19 U109-9
U91-15 U66-9 P15-4
10
CONTROL.*
37-11 U179-13 11107-28 13109-10 Pli-2
11
ASCII2
U107-12 U109-11
12
03
315-46 J14-46 313-46 312-46 1168-16 J16-20 U109-12
1191-5 1166-12 215-5
13
CAPLCK*
J79 P11r3 U109-13
14
ASCIL3
11107-11 U109-14
15
KZD*
11109-15 U111-t5 1177-15
16
+5v
UlIl 8 LS257 16 H12
I
A3
J15-5 314-S 313-5 312-5 Us-10 11109-1 13111-1
1197-35 U177-3 U94-3 1175-3 1173-35 U63-12
2
ASCII4
U107-10 U111-2
3
APPLEI*
37-7 Pli-4 13111-3
4
D4
315-45 314-45 313-45 312-45 1168-15 316-21 11111-4
1191-14 1169-4 P15-6
5
ASCIIS
13107-9 U1l1-5
6
1CAPPLEII*
11106-9 X3-2 U111-6
7
D5
J15-44 314-44 313-44 312-44 1168-14 316-22 11111-7
iJ91-6 U69-7 P15-7
8
CND
9
D6
315-43 J14-43 313-43 J12-43 1168-13 316-23 11111-9
15.78
1
Apple Computer Inc · 1982
Page 0429 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
- -
1.391-13 U69-9 PIS-8
lo
Q9-3 P.43-i 11111-10
li
ASCII6
U107-8 Ulil-li
12
Dl
J15-42 314-42 J13-42 312-42 1168-12 316-24 11111-12
11101-5 1191-7 1169-12 P15-9
13
ASCII7
11107-7 11111-13
14
11106-5 Ui11-14
15
KBD*
11109-15 13111-15 U77-15
16
+5v
11112 4 LS139 16 C8
1
U1L2-1 U71-9
2
A4
315-6 314-6 J13-6 312-6 119-6 U77-1 .376-1
11112-2 1163-9
3
AS
315-7 J14-7 313-7 312-7 119-10 1176-2 1177-2
L1112-3 1363-7
4
FFCX*
11165-7 13112-4
5
FPDX*
11112-3 1173-23 11148-9
6
FFEX*
U97-23 U148-1O 13112-6
7
NO CONNECTION
8
GND
9
NO CONNECTION
IO
NO CONNECTION
11
NO CONNECTION
12
1372-3 11112-12
13
CO7X*
11180-6 1377-7 11112-13 11158-1 U72-1 11150-5 11148-13
14
IR/W*
1198-28 U97-22 13112-14 1373-22 U163-11 1165-34 U160-12
15
IOSTOPD*
13123-9 U112-15 11180-3
16
+3V
11113 8 556 14 AS
I
NO CONNECTION
2
UPRST*
C20-1 U113-6
3
NO CONNECTION
4
+3V
5
TRESET
11113-5 P.92-I
6
UPRST*
C20-1 U113-6
11113-2 11113-2
R44-2
P.44-2
X4-2 X4-2
X6-1 X6-1
15.79
-I
Apple Computer Inc · 1982
Page 0430 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
pIacomp
7
GND
8
11113-8 R46-2 U113-12 C21-1
9
FLASH
TJL13-9 11136-5
lo
+5V
11
NO CONNECTION
12
11113-8 R46-2 11113-12 C21-1
13
11113-13 R45-2 R.46-1
14
+5v
11114 9 LSI6I 16 F10
i
IJTJTRST*
11124-13 11119-1 U123-1 R53-2 U1l4-1 J21-3 U116-1
11120-1 11118-1 11117-1
2
CIM*
U153-2 11123-2 11119-11 U120-2 11118-2 11116-2 tJll4-2
11126-11 1185-4 11144-5 11132-12 11150-4
3
CND
4
GND
5
GND
6
CND
7
S5B
R107-2 11106-2 11106-4 11106-10 U106-13 U93-1 'J114-1O
11114-7 11116-5
8
GND
9
HPE*
11135-3 U152-2 11114-9 U116-9 11116-12
10
S5B
R107-2 11106-2 11106-4 U106-1O 11106-13 1193-1 U1l4-10 U114-7 11116-5
11
H3
11114-11 Ui-5 11121-6
12
112
U121-7 US-5 U114-12 U85-8
13
Hl
11114-13 112-11 11155-9
14
HO
U114-14 112-5
15
U1l6-10 U114-l5 U116-7
16
+5v
11116 9 LSI6I 16 F11
1
UUTRST*
11124-13 11119-1 11123-1 R33-2 U114-1 J21-3 11116-1
11120-1 11118-1 U117-1
2
CIN*
11153-2 11123-2 11119-11 11120-2 U1l8-2 11116-2 11114-2 11126-11 1185-4 U144-5 11132-12 11150-4
3
GND
4
CND
5
S53
R107-2 11106-2 U106-4 11106-10 11106-13 U93-1 11114-10
15.80
Apple Computer Inc · 1982
Page 0431 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
pacompu
U114-7 U116-5
6
1J116-6 U121-17 U118-3
7
U116-l0 11114-15 11116-7
8
GND
9
HPE*
11135-3 U152-2 11114-9 11116-9 11116-12
10
11116-10 U114-15 11116-7
11
VA
11121-3 U175-5 11116-11 U82-5 1581-5
12
HPE*
11135-3 U152-2 11114-9 U116-9 U116-12
13
RS
15121-4 UI-14 11116-13
14
H4
11121-5 UI-3 11116-14
15
11118-5 15116-15 11118-10 11118-7
16
+5v
15117 9 S195 16 DIO
i
UUTRST*
11124-13 15119-1 11123-1 R53-2 11114-1 J21-3 11116-1
11120-1 11118-1 15117-1
2
Q3*
1193-9 U136-12 U91-12 15117-11 U1t7-2 U117-3 11135-12
11131-5 R102-2 R103-1 15146-1
3
Q3*
U93-9 11136-12 1191-12 13117-Il 11117-2 11117-3 11135-12
11131-5 R102-2 R103-1 15146-1
4
S5D
R109-2 U124-i 11124-4 11124-10 1110-13 U146-4 U123-4
11123-10 U123-13 U117-4 11117-5 11117-6 U117-7
5
S5D
1(109-2 11124-1 11124-4 11124-10 1110-13 U146-4 U123-4
11123-10 11123-13 15117-4 15117-5 15117-6 U117-7
6
S5D
1(109-2 11124-1 U124-4 11124-10 1110-13 11146-4 U123-4
U123-1O U123-13 11117-4 15117-5 11117-6 15117-7
7
S5D
1(109-2 11124-1 U124-4 11124-10 1110-13 11146-4 11123-4
11123-10 11123-13 U117-4 15117-5 11117-6 11117-7
8
CND
9
LDPS*
15117-9 1179-15 U131-6
10
C14M
11146-6 R100-1 11117-10 11119-9 1579-7 U85-11
11
Q3*
1193-9 U136-12 1191-12 11117-11 15117-2 11117-3 11135-12
11131-5 R102-2 1(103-1 15146-1
12
Q3
J14-37 1585-3 .115-37 J13-37 J12-37 11117-12 1(93-1
11154-2
15.81
Apple Computer Inc · 1982
Page 0432 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
*p - r'
13
NO CONNECTION
14
Ql
U6-8 11131-4 113-8 11124-12 U117-14
15
QO
U119-13 U150-1O U117-15 U131-2 1178-11
16
+5v
11118 9 L.S16 1
I
2
3 4 5 6
7 8 9
10 11 12 13 14 15 16
16 GlI UUTRST*
11124-13 11119-1 11123-1 R53-2 11114-1 J21-3 11116-1
11120-1 11118-1 UI 17-1
CIM* 11153-2 11123-2 11119-11 11120-2 11118-2 11116-2 11114-2 11126-11 1185-4 11144-5 U132-12 11150-4
Coz
Jll6-6 11121-17 11118-3 CND 11118-5 U116-15 11118-10 11118-7
S5060 11120-3 U121-15 11118-6 11118-5 11116-15 11118-10 11118-7 CND
UUTSTJNX* J19-1 11118-9 11162-8 11120-9 11118-5 11116-15 11118-10 U118-7
vi
11121-22 112-13 11118-11 1113-5 U13-3 vo 11121-23 U13-1l U 118-12 VC 11121-1 11175-7 11118-13 1183-15 U83-14 U82-7 U81-7 VB 11121-2 U175-6 11118-14 U82-6 U81-6 11120-5 11118-15 U120-4 U120-1O 11120-7 +5V
11119 9 S175 16 B12
1
UUTRST*
11124-13 11119-1 11123-1 R53-2 11114-1 J21-3 11116-1
U120-1 11118-1 U117-1
2
dM
J15-36 J14-36 J 3-36 J12-36 U141-9 11119-2 U146-12
1190-14
3
C7M*
U119-3 11153-13 11119-4
4
C7M*
11119-3 11153-13 11119-4
5
11119-5 11146-11
6
C3.5M*
11135-13 U119-6 U147-1 1190-2
7
C3.5M
U132-10 U141-1O U146-13 11119-7 J20-3
15.82
/
Apple Computer Inc · 1982
Page 0433 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
amp
8
GND
9
Cl 4M
U146-6 R100-1 13117-10 13119-9 U79-7 1385-11
10
clx
13132-2 13135-1 13119-10 U123-11 13180-S 1398-27 U80-11
1384-11
11
CIM*
13153-2 13123-2 13119-11 13120-2 13118-2 13116-2 13114-2
U126-11 1385-4 U144-5 U132-12 13150-4
12
PRE 1M
312-40 313-40 314-40 315-40 U119-12 1373-25 U123-5
1397-25 13139-10 R94-1
13
QO
U119-13 13150-10 U117-15 U131-2 1378-11
14
RAS
13152-13 13150-9 U119-14 1312-2 1312-5 U12-10 1312-13
15
NO CONNECTIOI
16
+5V
13120 9 LSI6I 16 G12
1
UUTRST*
13124-13 13119-1 13123-1 R53-2 13114-1 321-3 13116-1
U120-1 13118-1 13117-1
2
CIM*
13153-2 13123-2 13119-11 13120-2 13118-2 13116-2 13114-2 13126-11 U85-4 U144-5 13132-12 13130-4
3
S5060
13120-3 U121-15 13118-6
4
13120-5 U118-15 U120-4 13120-10 13120-7
5
U120-5 U118-15 13120-4 13120-10 13120-7
6
CND
7
13120-5 U118-15 13120-4 13120-10 13120-7
3
GND
9
UUTSUNK*
319-1 13118-9 U162-8 13120-9
10
U120-5 13118-15 U120-4 13120-10 13120-7
11
V5
U120-1l U154-9
12
V4
1387-19 1.11-2 U154-4 13120-12 Ui-11
13
V3
13120-13 131-13 U154-5 UI-6
14
V2
U120-14 U154-i0 U87-22
15
U162-9 U120-15
16
+5v
13121 9 2316 24 341-0030 C9
i
VC
13121-1 13175-7
2
VB
13121-2 13175-6
13118-13 13118-14
U83-15 1383-14 U82-6 1381-6
U82-7
U81-7
1.5.83
Apple Computer Inc · 1982
Page 0434 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
3
VA
U121-3 U175-5 L1116-11 U82-5 U81-5
4
115
U121-4 Ui-14 U1i6-13
5
114
11121-5 Ui-3 U116-14
6
113
U114-11 Ui-5 11121-6
7
112
U121-7 US-5 11114-12 U85-8
8
V2*V5
U121-8 U154-8 US-3
9
RSYNH
11121-9 U126-4
10
RCOLRGT
U121-10 U126-7
11
RTC'IJRT
U126-13 Ulil-li
12
GND
13
RBL
Ul21-13 U154-12
14
RRFSH
U121-14 U126-3
15
S5060
11120-3 11121-15 11118-6
16
RFIELD
11121-16 U126-18
17
CO
11116-6 U121-17 11118-3
18
FIELDIN
.119-3 11121-18 P43-i
19
V8L.
11175-15 1187-5 1197-19 1197-18 11121-19 U154-6
20
CD
21
+5v
22
Vi
11121-22 U2-13 11118-11 1113-5 1113-3
23
vo
U121-23 U13-li 11118-12
24
+5v
11123 9 $74 14 Dli
i
UUTRST*
11124-13 U119-i U123-i 1153-2 11114-1 J21-3 U116-1
11120-1 11118-1 11117-1
2
CIN*
U153-2 11123-2 11119-11 11120-2 U118-2 11116-2 U114-2
11126-11 U85-4 11144-5 11132-12 11150-4
3
AX
11124-9 11123-3
4
S5D
R109-2 U124-1 U124-4 11124-10 1110-13 11146-4 11123-4
15.84
Apple Computer Inc · 1982
Page 0435 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
apkzcomp
(3123-10 U123-13 U117-4 0117-5 0117-6 0117-7
5
PREIM
.112-40 .113-40 .114-40 .115-40 (3119-12 073-25 (3123-5
(397-25 U139-1O P.94-i
6
PREIM*
.112-38 J13-38 J14-38 .115-38 (3123-6 P.95-i
7
GND
8
NO CONNECTION
9
IOSTOPD*
U123-9 (3112-15 (3180-3
10
SSD
P.109-2 (3124-1 (3124-4 U124-1O U1O-13 U146-4 (3123-4
(3123-10 (3123-13 (3117-4 U117-5 (3117-6 Ui17-7
11
CIM
U132-2 (3135-1 (3119-10 U123-11 (3180-5 U98-27 (380-11
(384-11
12
FSPACE*
(3180-1 (3176-1 (3165-12 0123-12 (3148-8
13
S5D
R109-2 (3124-1 (3124-4 U124-1O 010-13 U146-4 (3123-4
U123-iO (3123-13 (3117-4 U117-5 (3117-6 U117-7
14
+5V
(3124 9 S74 14 All
i
S3D
P.109-2 (3124-1 (3124-4 U124-1O (310-13 U146-4 (3123-4
(3123-10 (3123-13 (3117-4 (3117-5 (3117-6 U117-7
2
U124-2 (3152-8
3
U124-3 (3146-3
4
S5D
R109-2 (3124-1 (3124-4 (3124-10 (310-13 U146-4 0123-4
(3123-10 (3123-13 (3117-4 (3117-5 (3117-6 U117-7
5
PHO
J15-19 0136-11 .114-19 .113-19 J12-19 (3124-5 (365-37
R96-1
6
NO CONNECTION
7
GND
8
(3124-8 U2-2 U13-2 U9-2 US-2 J17-23
9
AX
(3124-9 0123-3
10
SSD
P.109-2 U124-1 (3124-4 U124-10 U1O-13 U146-4 U123-4
0123-10 U123-13 (3117-4 (3117-5 U117-6 (3117-7
11
C14M*
(3141-13 U146-8 U124-11 .121-2
12
Ql
(36-8 U131-4 U3-8 (3124-12 U117-14
13
UIJTRST*
1J124-Í3 (3119-1 0123-1 P.53-2 U114-1 .121-3 0116-1
(3120-1 U11S-1 (3117-1
14
+5V
15.85
I
Apple Computer Inc · 1982
Page 0436 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
U126 9 L5374 20 GlO
I
GND
2
RFS1L
U158-13 Uil-le 13126-2
3
RRFSH
U121-14 U126-3
4
RSYNCH
U121-9 U126-4
5
SYNCH
J20-1 Pii-lO U126-5 P3-2 P4-6
6
COLRGATE
J20-8 U147-2 13126-6
7
RCOLRGT
U121-i0 U126-7
8
DRIRES
U83-10 U126-8 U82-8 1381-8 U87-17
9
RDHIRES
13175-1 U1l-17 133-2 136-3 U126-9
lo
GND
11
CIM*
U153-2 13123-2 U119-11 U120-2 U118-2
U126-11 U85-4 13144-5 13132-12 13150-4
12
TCWRT
13126-12 13144-4
13
RTCWRT
13126-13 U12l-11
14
U126-14 13152-1 13154-11
15
U158-12 U126-15
16
BL
1397-16 1383-7 1385-7 U126-16
17
13126-17 13152-3
18
RFIELD
13121-16 U126-18
19
FIELDOUT
13126-19 .119-2
20
+5v
U116-2
U114-2
13128 2 S86 14 ElO
i
AlO
.115-12 .114-12 .113-12 J12-12 U128-1
U67-9
2
PCAS3*
U128-2 13128-13 P1-6 U3-1l 134-8
3
U5-12 13128-3
4
A13
Jis-ls .114-15 .113-15 .112-15 13128-4
1371-1 1370-7 136-5 133-6 U174-7
5
PRASO.3
U128-5 1311-14 U12-1 133-15 136-4
6
13128-9 U128-6
7
CND
1374-3 1371-4
13155-12 U165-15
15.86
Apple Computer Inc · 1982
Page 0437 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
éIppIa mpi.*ir Wi
8
1113-12 11128-8
9
11128-9 11128-6
10
PCASI*
Pi-3 114-4 116-12 11128-10
11
119-4 U128-I1
12
All
J15-13 J14-13 J13-13 J12-13 11128-12 116-6 1171-3
13
p3* 11150-13 1174-5 U67-12 U3-5 U174-5
11128-2 U128-13 Pi-6 U3-11 114-8
14
+5v
11131 3-9 LS51 14 Bu
i
U152-6 11144-10 11131-1
2
QO
U119-13 11150-10 11117-15 11131-2 1178-11
3
U131-3 11135-5
4
Ql
116-8 U131-4 113-8 U124-12 11117-14
5
Q3*
U93-9 U136-12 U91-12 U117-11 UIi7-2 U117-3
11131-5 R102-2 R103-I U146-i
6
LDPS*
(J1i7-9 U79-15 11131-6
7
GND
8
ZPAGE*
Uil-i 11174-15 U67-1 U131-8 1170-L
9
DHA1
11131-11 1116.3-6 U131-lO 11131-9 U160-13
lo
DMA1
11131-11 11163-6 11131-10 11131-9 11160-13
11
DMAI
11131-11 11163-6 11131-10 11131-9 11160-13
12
U135-6 11131-12
13
11144-9 11131-13 11155-4
14
+5v
11135-12
U132 3-5-7 LS86 14 D4
i
SEL.374
1187-10 11132-13 U132-1
2
C1M
U132-2 11135-1 11119-10 U123-11 11180-5 U98-27
1184-11
3
VAEN
U84-1 11132-3
4
ZO
U72-5 U132-4 U73-1O
S
PPA8
11158-4 11152-4 11158-5 1165-17 1164-23 11132-5
6
1167-2 11132-6
7
CND
8
11140-3 11132-8
1180-li
15.87
/
Apple Computer Inc · 1982
Page 0438 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
9
DR2
11132-9 1185-9
10
C3 5M
U132-10 U141-lO U146-13 U119-7 J20-3
u
V3EN
1180-1 11132-11
12
CIM*
U153-2 U123-2 11119-11 11120-2 11118-2 11116-2 1J114-2
11126-11 U85-4 11144-5 U132-12 11150-4
13
SEL.374
U87-10 11132-13 11132-1
14
+5V
11135 3-9 L.S260 14 C9
i
CLM
11132-2 11135-1 11119-10 11123-11 11180-5 1198-27 U80-11
1184-11
2
HPEDIS
11135-2 J21-1 R54-1
3
HPE*
U135-3 11152-2 11114-9 11116-9 U116-12
4
PAil
1164-13 11144-12 1165-20 U67-13 11135-4
5
11131-3 U135-5
6
11135-6 11131-12
7
CND
8
PA13
U65-23 U 135-8 1170-6
9
PAI2
U65-22 11135-9 U70-3
10
PAlS
11135-10 1111-4 1170-13 1165-25
11
PA14
1165-24 U135-1i 1170-10
12
Q3*
1193-9 11136-12 1191-12 11117-11 11117-2 U117-3 11135-12
11131-5 R102-2 R103-1 11146-1
13
C3.SM*
U135-13 11119-6 11147-1 1190-2
[4
+5V
11136 2-5 LS5I 14 H4
SYNC
1165-7 U136-1 J15-35 U174-3 J14-35 J13-35
2
DV7
1186-3 1178-3 1180-2 U84-2 11136-3 11136-2
3
DV7
1186-3 1178-3 1180-2 1184-2 11136-3 11136-2
4
DC7
1179-2 U78-2 U82-14 U136-4
5
FLASh
11113-9 11136-5
J12-35
15.88
Apple Computer Inc · 1982
Page 0439 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
6
13173-2 13136-6
7
GND
8
CL3K
U136-8 U10-9
9
R/W*
J15-13 .114-13 .113-13 .112-13 133-3 U136-9 U180-17
U176-6 U165-11 U160-11
lo
IND*
13136-10 U147-5 13174-12
11
P110
.115-19 U136-ll .114-19 .113-19 .112-19 13124-5 1365-37
R96-1
12
Q3*
1393-9 13136-12 1391-12 U117-l1 U117-2 13117-3 13135-12
13131-5 R102-2 R103-1 13146-1
13
NO CONNECTION
14
+3V
13139 5-8 LS132 14 HiO
i
1396-9 13139-1
2
1396-10 13162-2 13139-2
3
13139-3 13106-3
4
13139-4 13139-11
5
RZSETLK*
13179-14 1373-6 P19-5 U139-5
6
NMI*
13139-6 1365-6 U155-2
7
CND
8
13139-8 13154-1
9
C}180*
13139-9 13153-12 U87-14
10
PRE1M
.112-40 .113-40 .114-40 .115-40
U97-25 U139-1O R94-1
11
U139-4 13139-11
12
KRESET*
13139-12 R80-1 C71-1 13179-15
13
10N111*
J15-29 U97-17 .114-29 .113-29
14
+5v
U119-12
.17-15 U139-13
1373-25 .112-29
U123-5
13140 7-9 S74 14 D5
i
SSC
R108-2 13140-1
2
U140-6 U140-2
3
U140-3 13132-8
4
S5C
R108-2 13140-1
5
ACIACLK
U98-6 13140-5
6
U140-6 U140-2
7
CND
13140-4 U140-4
13140-10
U140-i0
U140-13 13140-13
i 5.89
Apple Computer Inc · 1982
Page 0440 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
j
B
NO CONNECTION
9
11152-9 U140-9
lo
SSC
R108-2 U140-1 13140-4 U140-1O 13140-13
11
L7152-1O 13152-11 13140-11
12
PHASEN
11140-12 13180-13
13
S5C
R108-2 13140-1 13140-4 11140-10 U140-13
14
+5V
13141 4-5 LSOO 14 112
L
AHIRES
1188-1 1387-13 13141-1
2
U141-2 11141-B
3
U141-12 U141-3
4
U141-4 13150-6
5
P112M
P19-10 11141-5 1365-39 11176-17
6
CPH1
U162-3 U76-4 U141-6 1174-4
7
GND
8
U141-2 11141-8
9
dM
J15-36 J14-36 .113-36 .112-36 U141-9 13119-2
U90-14
10
C3.5M
U132-10 U141-10 13146-13 13119-7 .120-3
11
CKDSP
11141-11 1189-9
12
U141-12 11141-3
13
CI4M*
U141-13 11146-8 11124-11 .121-2
14
+5V
13146-12
11144 3-5 LS2O 14 BIO
I
ENCWRT
U177-10 11144-1
2
QO*
13152-12 11144-2 1385-2
3
NO CONNECTION.
4
TCWRÎ
U126-12 13144-4
S
CIM*
11153-2 U123-2 11119-11 U120-2 13118-2
11126-11 U85-4 11144-5 U132-12 U1S0-4
6
WE2114*
1182-10 11175-16 1381-10 13144-6
7
GND
8
DMAOK
13144-8 .112-27 .115-27 J14-27 .113-27
9
13144-9 U131-13 U 155-4
U116-2
11114-2
15.90
Apple Computer Inc · 1982
Page 0441 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
- m
lo
0152-6 0144-10 13131-1
11
NO CONNECTION
12
PAIL
064-18 13144-12 1365-20 1367-13 13135-4
13
TROMSEL
13162-12 U144-13
14
+5v
11146 9 S86 14 313
i
Q3*
1393-9 13136-12 1391-12 0117-11 13117-2 13117-3 0135-12
13131-5 1UO2-2 R103-1 13146-1
2
Q11-3 R51-1 13146-10 U146-5 U146-2
3
13124-3 0146-3
4
SSD
R109-2 13124-1 13124-4 13124-10 1310-13 11146-4 11123-4 13123-10 13123-13 U117-4 13117-5 13117-6 U117-7
5
Q11-3 R51-1 0146-10 13146-5 U146-2
6
CL4M
11146-6 R100-1 13117-10 U119-9 079-7 1385-11
7
GND
8
C 14N
0141-13 U146-8 0124-11 .121-2
9
CND
10
Q11-3 R51-1 13146-10 13146-5 13146-2
11
13119-5 13146-11
12
C71!
JI5-36 .114-36 J13-36 .112-36 0141-9 13119-2 13146-12 U90-14
13
C3.5M
0132-10 11141-10 0146-13 13119-7 .120-3
14
+5V
13147 4-5 LS1I 14 KS
1
C3.5M*
13135-13 13119-6 0147-1 1390-2
2
COLRG.A1E
J20-8 13147-2 13126-6
3
A15
.115-17 J14-17 .113-17 .112-17
U174-16 136-7
4
A14
.115-16 .114-16 .113-16 J12-16
06-16 0174-4
5
IND*
U1]6-10 13147-5 U174-12
6
C-FXXX
1171-15 U180-2 1371-14 U71-13
7
CND
133-4 13147-3 U70-12 133-7 13147-4 U70-9
13147-6 13147-9 0165-1
15.91
Apple Computer Inc · 1982
Page 0442 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
8
CXOC
13176-15 U74-6 U150-1 U147-8
9
C-FC
1371-15 13180-2 1371-14 1371-13 13147-6 U147-9 13165-1
10
lOEN
1373-8 P19-3 13147-10
11
13147-11 U155-13
12
COLORBIJRST
P35-i 13147-12
13
COLORKILL*
13147-13 1387-11 320-9
14
+5V
U148 4 LS21 14 34
1
IRi*
13101-14 312-30 P2-i U148-i
2
IRQ2*
1H01-15 313-30 P2-6 11148-2
3
NO CONNECTION
4
IRQ3*
1397-7 J14-30 P2-4 13148-4
5
IRQ4*
1397-6 315-30 P2-3 U148-5
6
13155-8 13148-6
7
GND
8
FSPACE*
13180-1 13176-1 U165-12 U123-12 13148-8
9
FYDX*
13112-5 1373-23 11148-9
IO
PFEX*
1397-23 13148-10 U112-6
11
NO CONNECTIOK
12
SEL6551*
1398-3 1376-7 13148-12
13
CO7X*
U180-6 1377-7 1H12-13 13158-1 U72-1 13150-5
14
+5v
13148-13
U150 2-4 SlO 14 E9
13176-15 U74-6 13150-1 U147-8
2
GP}12
13150-2 U77-6 13162-4
3
SELIM
U180-15 13174-2 U150-3 U73-9 P19-2
4
CIM*
13153-2 13123-2 U119-11 13120-2 U118-2 13116-2 U114-2
13126-11 1385-4 13144-5 13132-12 13150-4
5
CO7X*
13130-6 1377-7 U112-13 U158-1 1372-1 U150-5 13148-13
6
U141-4 13150-6
7
GND
15.92
Apple Computer Inc · 1982
Page 0443 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
ppcomputwiX
8
RAMR/W*
.317-il 13150-8
9
RAS
13152-13 U150-9 U119-14 U12-2 1312-5 1312-10 1312-13
lo
QO
13119-13 13150-10 U117-15 U131-2 1378-11
11
WRAMEN
13180-12 U150-11
12
IOSTRB*
.115-20 13150-12 314-20 313-20 J12-20
13
All
315-13 314-13 .113-13 312-13 13128-12 136-6 U71-3
13150-13 1374-5 1367-12 133-5 13174-5
14
+5V
13152 3-9 LSOO 14 El
i
U126-14 13152-i U154-ll
2
HPE*
13135-3 13152-2 13114-9 13116-9 U116-12
3
13126-17 U152-3
4
PPA8
13158-4 13152-4 13158-5 1365-17 1364-23 13132-5
5
13158-8 13152-5
6
13152-6 13144-10 13131-1
7
CND
8
13124-2 13152-8
9
13152-9 U140-9
10
13152-10 13152-11 13140-11
13.
13152-10 13152-11 13140-11
12
Q0*
13152-12 13144-2 1385-2
13
RAS
13152-13 13150-9 13119-14 1312-2 1312-5 1312-10
14
+5v
1312-13
13153 2-4-5 LSO8 14 58
i
U158-11 U153-1 13180-4
2
CIM*
13153-2 13123-2 13119-lI 13120-2 13118-2 13116-2 13114-2
13126-il 1385-4 13144-5 13132-12 U150-4
3
AY*
1313-14 U1l-3 139-14 US-14 U2-14 U153-3 U6-15
133-1
4
S399
13174-14 U153-4
5
DAl
J16-i6 13153-5 1384-3 1369-14
fi
1310-1 13153-6
7
GND
8
TROMSEL*
13153-8 U162-13 1364-20
9
DMAI*
15.93
Apple Computer Inc · 1982
Page 0444 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
cippkz compu
I
10
11 12 13 14
13176-2 .112-28 .115-28 J14-28
U 153-9
ROMSEL*
13153-10 13165-9 13176-3 TJ153-11 1379-6
CH8O* 0139-9 13153-12 1387-14
C7M* 0119-3 13153-13 13119-4 +5v
.113-28
U163-5
P14-2
13154 5-9 LSO8 14 F8
1
13139-8 U154-i
2
Q3
J14-37 U85-3 .115-37 .113-37 0154-2
3
13173-3 U154-3
4
V4
1387-19 UI-2 13154-4 13120-12
5
V3
0120-13 Ui-15 U154-5 Ui-6
6
VBL
0175-15 1387-5 1397-19 U97-18
7
CND
8
V2*V5
0121-8 13154-8 US-3
9
V5
U120-11 U154-9
10
V2
U120-14 13154-10 1387-22
11
13126-14 U152-1 13154-11
12
RBL
13121-13 13154-12
13
SCRN
13154-13 U73-7 P19-4
14
+5V
.112-37 13117-12 UI-11
13121-19 13154-6
R93-1
0155 3-4-8 LSO2 14 D9
1
13155-1 U164-I
2
NMI*
0139-6 1365-6 13155-2
3
AIISW*
13165-6 1371-12 U97-8 13178-1
13155-3
4
U144-9 13131-13 13155-4
5
PA9
064-22 13155-5 1365-18 1367-6
6
PAiO
1364-19 13155-6 1365-19 067-10
7
GND
8
13155-8 13143-6
9
HI
13178-13
U177-15
U87-3
15.94
Apple Computer Inc · 1982
Page 0445 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
ppcompr
11114-13 U2-11 11155-9
lo
IOIRQ
1173-40 11155-10
11
Al2
315-14 314-14 313-14 312-14 119-12 U155-11 U165-14
1170-4 Ui 1-2 11174-6
12
A13
315-15 314-15 J13-15 J12-15 11128-4 11155-12 11165-15
1171-1 1170-7 116-5 U3-6 U174-7
13
11147-11 U155-13
14
+5V
11158 3-4-9 L532 14 38
I
CO7X*
U180-6 1177-7 11112-13 11158-1
2
IR*/W
1191-3 U68-11 11158-2 11163-10
3
CLKRD
U72-2 11158-3
4
PPA8
11158-4 11152-4 U158-5 1165-17
5
PPA8
11158-4 11152-4 11158-5 1165-17
6
PA8
U11-2 11174-17 U67-3 U158-6
7
CND
8
U158-8 11152-5
9
PRIMSTX
U73-4 P19-i U158-9
10
A3K4
U11-15 U174-1 1110-15 11158-10
11
11158-11 U153-1 U180-4
12
11158-12 U126-15
13
RFSH
11158-13 1111-16 U126-2
14
+5v
1172-1 11150-5
U64-23 11132-5 U64-23 11132-5
U148-13
11160 3-7 L.S125 14 39
1
ENSEL
11161-4 U160-1 11177-11 11161-1
2
PSW3/SCO
11169-16 U161-3 U160-2
3
SCO
11160-3 1173-18 11160-5 11101-1
A
PDL.2
U160-4 U105-2 U75-10
5
Sco
0160-3 1173-18 11160-5 11101-1
6
R86-1 11160-6 U161-2
7
CND
8
SER
073-19 11160-8 11161-9
15.95
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
9
PX1/ SER
(3105-12 ¡3161-8 11160-9 ¡3169-18
10
EN S IO
11160-10 U177-12 11161-10
11
R/W*
J15-18 J14-18 J13-18 J12-18 113-3 11136-9 ¡3180-17
11176-6 ¡3165-11 (3160-11
12
IR/W*
1198-28 ¡397-22 ¡3112-14 U73-22 U163-1I (365-34 U160-12
13
DMA1
¡3131-11 U163-6 U131-10 U131-9 ¡3160-13
14
+5v
11161 6-7 LSIZ6 14 JiO
1
ENSEL
¡3161-4 U160-1 ¡3177-11 U161-1
2
R86-1 UL6-6 U161-2
3
PSW3/SCO
11169-16 U161-3 U160-2
4
ENSEL
U161-4 ¡3160-1 11177-11 ¡3161-1
5
AXCO
11161-S U75-12 11105-1
6
Y1/XCOU1
¡3161-6 11169-17 11105-11
7
CND
8
PX1/SER
¡3105-12 11161-8 11160-9 11169-18
9
SER
1173-19 11160-8 U161-9
10
ENSIO
U160-1O 11177-12 11161-10
11
U161-11 1192-5 R67-2
12
1193-12 (1161-12 1193-11
13
U161-13 1193-10
14
+5v
11162 3-4-5-8-9 LSO4 14 118
I
DTRDY*
11107-16 11162-1
2
U96-10 (1162-2 11139-2
3
CPM1
(3162-3 U76-4 U141-6 (374-4
4
GPH2
11150-2 1177-6 ¡3162-4
5
STO
1188-3 ¡385-18 ¡3162-5 U79-13
6
BTO*
1183-3 11162-6
7
GND
8
UUTS(JNK*
J19-1 11118-9 (3162-8 11120-9
1183-4
1183-1
15.96
/
Apple Computer Inc · 1982
Page 0447 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
9
11162-9 U120-15
10
RESET*
1165-40 11162-10 U98-4 1197-34 1173-34 1175-15 1179-9
11173-1
11
UUTUPRST
R92-2 11162-11 321-4 11164-3
12
TROMSEL
11162-12 11144-13
13
TROMSEL*
11153-8 11162-13 1164-20
14
+5v
11163 3-5-6 LSO4 14 K9
1
DEXT*
11167-18 1194-10 11178-2 11163-1
2
PLNT*
11167-19 11163-2 11178-5
3
TSADB*
315-22 312-22 314-22 313-22 11163-3 P14-3
4
U70-15 11163-4 1167-15 U63-19 1163-1
5
DMAI*
11176-2 J12-28 315-28 314-28 313-28 11163-5 P14-2
UI 53-9
6
DMA1
11131-11 11163-6 U131-10 Ui)1-9 11160-13
7
GND
8
NTSCB
P3-8 U163-8
9
NTSC3*
11163-9 1190-9
10
IR*/W
U91-3 1168-11 11158-2 U163-i0
11
IR/W*
U98-28 1197-22 U112-14 1173-22 11163-11 1165-34 U160-12
12
DWRP.EQ
11166-14 U163-12
13
11163-13 1194-12 1192-4
14
+5V
11164 2-6-8 LSO5 14 H9
i
11155-1 11164-1
2
IORESET*
312-31 313-31 314-31 315-31
1196-4 1194-15
3
UUTUPRST
R92-2 11162-11 321-4 U164-3
4
IORESET*
312-31 J13-31 314-31 315-31
1196-4 1194-15
5
APPLEIL*
37-5 Pli-5 U106-12 11164-5
6
11164-6 C17-2 X5-2 C75-2
P14-6 P14-6
11164-2 11164-2
U164-4 U164-4
15.97
Apple Computer Inc · 1982
Page 0448 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
7
GND
8
RD!
J15-21 13164-8 J14-21 J13-21 J12-21 P14-4 U65-2
9
PRDY
U164-9 U174-13
10
DTIM
R31-1 13164-10 Cl-2 1396-2 U96-6
11
MOTEN *
U164-11 1394-9
12
MOTON*
13179-1 1392-15 13178-15 RaS-2 U164-12 U92-16
13
MOTON
U164-13 1396-5
14
+5V
U165 4 LS133 16 Ji
I
C-FXXX
Uil-IS 13180-2 1371-14 1371-13 U147-6 U147-9 13165-1
2
S5A
R106-2 U165-2 13165-3 U165-4 U165-5 U173-4 13173-13
Ui 73-10
3
S 5A
R106-2 13165-2 U165-3 13163-4 13165-5 U173-4 13173-13
U173-10
4
S5A
R106-2 13165-2 13165-3 13165-4 13165-5 U173-4 13173-13
U1.73-l0
SSA RIQ6-2 13165-2 U173-l0
13165-3
U165-4
13165-5
U173-4
U173-13
6
AIISW*
13165-6 U71-12 1397-8 U178-1 13178-13 U177-15 U87-3
13153-3
7
FPCX*
13165-7 U112-4
8
CND
9
RQMSEL*
13153-10 U165-9 1317 6-3
10
ROMSELL
13165-10 U73-2 P19-9
11
aIw*
315-18 J14-18 J13-18 J12-18 133-3 U136-9 13180-17
13176-6 U165-11 13160-11
12
FSPACE*
U180-1 13176-1 13165-12 13123-12 U148-8
13
INH*
315-32 J14-32 313-32 J12-32 U176-4 13165-13 P14-S
14
Al 2
315-14 314-14 313-14 312-14 U9-12 13155-11 13165-14
1370-4 U71-2 Ui 74-6
15
Al 3
J15-15 314-15 J13-15 312-15 U128-4 13155-12 13165-15
15.98
Apple Computer Inc · 1982
Page 0449 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
U71-1 1.170-7 U6-5 133-6 73174-7
16
+5V
73166 6 FILTER 20 N13
I
GNDY
2
ENBL3.E*
.11-21 U166-2
3
WRDXA
.16-18 U166-3 Ji-ls
4
RDDAIA
.16-16 U166-4 ii-16
5
ENBLI.E*
.11-14 73166-5
6
ENBLI.t*
J6-14 U166-6
7
WRREQ
.16-10 U166-7 .11-10
8
DPH2
J6-6 U166-8 Jl-6
9
DPHO
J6-2 13166-9 J1-2
lo
CNDF
11
GNDF
12
VAi
1.1166-12 1.1175-4 1.194-4
13
VCI
73166-13 73175-2 7394-6
14
DWRREQ
1.1166-14 1.1163-12
15
PENBL1,I*
73166-15 1.1178-4
16
PENBLE*
1.1166-16 U178-7
17
DRDATA
(.1166-17 7393-13
18
DWRDATA
73166-18 7392-19 U93-2
19
PENBL3,E*
1.1166-19 U179-7
20
GNDF
73167 6 FIITER 20 M13
2
EXT*
il-26 U167-2
3
INT*
J6-26 73167-3
4
WRPROT
J6-20 73167-4 J1-20
5
AII*
73167-5 .11-23 J6-23
6
ENBLZ.E*
15.99
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
ppcomp
31-22 U167-6
7
SIDE2/L
36-24 .0167-7 .11-24
S
DPH3
.16-8 U167-8 .11-8
9
DPIII
36-4 13167-9 J1-4
10
CNDF
11
CNDF
12
VB1
15167-12 U175-3 094-5
13
PDPU3
0167-13 1394-7
14
PSIDE
U167-14 13177-7
15
PENBL2,E*
U167-15 0179-6
16
PAIl
0178-12 U167-16
17
DWR2T
0167-17 091-11
18
DEXT*
0167-18 U94-1O U178-2 U163-1
19
PINT*
0167-19 0163-2 0178-5
20
CNDF
- 11169 7 FILTER 20 NiO
L
-
GNDF
2
SWI/NGNSW
J3-5 0169-2
3
X1/SER
33-4 0169-3
4
Y1/xCO
33-8 13169-4
5
SW3/SCO
33-9 13169-5
6
YO
0169-6 J2-8
7
SW2
U169-7 32-5
8
suo
0169-8 J2-9
9
X0
0169-9 J2-4
10
CNDF
11
GNDF
12
XOUF
0105-15 U169-12
13
SWOUF
0101-4 0169-13
14
SW2UF
15. 100
I
Apple Computer Inc · 1982
Page 0451 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
t
pI compLt ui
11101-2 11169-14
15
YOIJF
13105-13 11169-15
1f,
PSW3/SCO
U169-16 11161-3 11160-2
17
Y1/XCOUF
13161-6 U169-17 U105-11
18
PX1/SER
11105-12 11161-8 U160-9 11169-13
19
SWI/MGNSWIJT
R85-2 11169-19 1173-39 11101-3
20
GNDF
Ul71 8 FILTER 20 K13
CNDF
KX6
37-26 11171-2
3
KX4
37-21 U171-3
4
KX3
- J7-20 11171-4
5
KX5
37-19 11171-5
6
KXI
37-18 11171-6
7
10cl
37-17 11171-7
8
10(2
J7-16 11171-8
9
KXO
37-14 11171-9
10
GNDF
11
GNDF
12
101013F
13171-12 11107-40
13
1012117
13171-13 U107-38
14
101711V
11171-14 11107-33
15
101113F
13171-15 11107-39
16
KX5UF
13171-16 11107-35
17
KX3UF
13171-17 U107-37
18
KX4UF
11171-13 11107-36
19
KX6IJF
11171-19 11107-31e
20
GNDF
13172 7 FILTER 20 N3
15.101
Apple Computer Inc · 1982
Page 0452 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
ìcçpla t r
i
CNDF
2
EXTSPK2
J11-2 (3172-2
3
DCD
.14-8 (3172-3
4
J4-20 (3172-4
5
DSR
J4-6 (3172-5
6
CTS
J4-5 (3172-6
7
RTS
J4-4 (3172-7
8
DATAIN
.14-3 (3172-8
9
TXD
J4-2 (3172-9
10
GNDF
11
cim
12
PTXD
(3172-12 U99-6
13
PRXD
1J172-13 (3100-1
14
PRTS
(3172-14 U99-11
15
PCTS
R87-2 (3172-15 (3100-4
16
PDSR
R38-2 (3172-16 (3100-10
17
PDTR
(3172-17 U99-8
18
PDCD
R89-2 (3172-18 (3100-13
19
PEXTSPK
(3172-19 dO-2
20
GNDF
(3173 5-7 LS74 14 Hl
1
RESET*
(365-40 U162-10 U98-4
(3173-1
2
(3173-2 (3136-6
3
(3173-3 (3154-3
4
S5A
R106-2 (3165-2 (3165-3
(3173-10
S
INV
(383-11 U173-5
E,
NO CONNECTION
7
CND
8
(3173-8 (3173-12
AIISPKR
U97-34 (373-34
(3165-4 (3165-5
U75-15 U173-4
U79-9 U173-13
15. 102
'-I
Apple Computer Inc · 1982
Page 0453 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
r- -
R35-1 U173-9
10
55A
R106-2 U165-2 (.1165-3 U165-4 U165-5 U173-4 (3173-13
UI 73-10
11
SPKR*
11173-11 (377-12
12
U173-8 U173-12
13
SSA
R106-2 (3165-2 (3165-3 (1165-4 (3165-5 (3173-4 U173-13
Uil 3-10
14
+5V
(.1174 2 7643 18 341-0043 ClO
i
ABK4
(.111-15 (3174-1 (310-15 (3158-10
2
SELIM
(3130-15 U174-2 (3130-3 (373-9 P19-2
3
SYNC
U65-7 (3136-1 315-35 (3174-3 314-35 313-35 J12-35
4
A14
J15-16 314-16 313-16 312-16 U3-7 (3147-4 (370-9
(36-16 (3174-4
5
All
315-13 J14-13 J13-13 312-13 U128-12 U6-6 (371-3 U150-13 (374-5 (367-12 U3-5 (3174-5
6
Al2
J15-14 314-14 313-14 312-14 (39-12 U155-1l (3165-14 U70-4 (.171-2 U174-6
7
A13
315-15 314-15 313-15 312-15 (1128-4 (3155-12 (3165-15 (371-1 U70-7 (.16-5 U3-6 (3174-7
S
CND
9
GND
10
CND
11
NO C0NZCTI0N
12
IND*
U136-lO U147-5 (1174-12
13
PRD!
(3164-9 (3174-13
14
S399
(3174-14 (3153-4
15
ZPAGE*
Uil-i (3174-15 (367-1 (3131-8 U70-1
16
AlS
315-17 314-17 313-17 312-17 (33-4 (3147-3 U70-12 (3174-16 U6-7
17
PA8
(311-2 (3174-17 (367-3 U158-6
18
+5v
(3175 2 7643 18 341-0055 F9
i
RDHIRES
15. 103
Apple Computer Inc · 1982
Page 0454 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
*pcomp
U175-1 U11-17 133-2 116-3 U126-9
2
VC1
11166-13 U175-2 1394-6
3
VB!
11167-12 13175-3 1194-5
4
VAl
11166-12 U175-4 U94-4
5
VA
11121-3 13175-5 13116-11 1382-5 1381-5
6
VB
1.1121-2 11175-6 13118-14 1382-6 1381-6
7
VC
U121-1 13175-7 13118-13 1.183-15 1183-14 1382-7 1181-7
8
GND
9
GND
10
CND
U
ENHREG*
11175-11 1378-1
12
MUX3
139-13 U175-12
13
UJX2
119-3 11175-13
14
MUX1
11101-12 13175-14 US-13
15
VBL
13175-15 1187-5 U97-19 U97-18 13121-19 U154-6
16
1JE2114*
1382-10 U175-16 U81-10 11144-6
17
SCR
13177-9 U175-17
13
+5V
111764 7643
i
2
3
4 5 6
7 8 9 IM 11
13 341-0045 F5 FSPACE*
11180-1 13176-1
DMAI*
11176-2 .112-28
U153-9 ROMSEL*
U153-10 U165-9 INB*
.115-32 .114-32
U74-1O U176-5 R/W*
315-18 .114-13 11176-6 U165-11
C6XX*
11176-7 CND
CND GND
RAMEN
1174-9
13165-12 U123-12 11148-8 .115-28 .114-28 .113-28 U163-5 P14-2
11176-3
.113-32 .112-32 13176-4 U165-13 P14-S
.113-18 J12-18 113-3 U136-9 U180-17
13160-11
15. 104
Apple Computer Inc · 1982
Page 0455 of 0730
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r-Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
U180-7 13176-11
12
NO CONNECTION
13
EN8304
(7176-13 1368-9
14
EN257
U176-14 1366-15 U69-15
15
CXXX
13176-15 U74-6 U150-1 13147-8
16
C7XX*
(3176-16 1374-7
17
P1I2N
P19-10 U141-5 1365-39 U176-17
18
+5v
13177 6 9334 16 L12
i
AI
J15-3 .114-3 .113-3 J12-3 (72-10 1397-37 1398-14
tuOi-lO U177-1 1394-1 (373-37 1375-1 1363-16
2
A2
.115-4 J14-4 J13-4 J12-4 135-6 13101-9 U97-36
(1177-2 1394-2 1375-2 1373-36 U63-14
3
A)
.115-5 .114-5 .113-5 .112-5 135-10 13109-1 13111-1
1197-35 (3177-3 1394-3 U75-3 U73-35 U63-12
4
EXTO
13179-2 (3177-4
5
EXT1
13179-3 13177-5
6
INTON
13177-6 13178-3
7
PSIDE
13167-14 13177-7
8
CND
9
SCR
13177-9 U175-17
10
1CWRT
13177-10 13144-1
11
ENSEL.
13161-4 13160-1 (3177-11 13161-1
12
ENSIO
13160-10 13177-12 U161-10
13
AO
.115-2 .114-2 .113-2 J12-2 132-6 1397-38 U98-13
13101-11 (394-13 1373-38 1375-13 1363-18 U177-13
14
DEVSEL5*
13177-14 (776-10
15
AIISW*
13165-6 1371-12 1397-8 U178-1 (3178-13 U177-15 (387-3
1315 5-3
16
+5v
L1178 3-6 LS257 16 LII
15. 105
,1
Apple Computer Inc · 1982
Page 0456 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
i
ALI SW*
U165-6 U71-12 097-8 0178-1 U178-13 0177-15 087-3
I
1.
UI 55-3
DEXT*
0167-18 094-10 0178-2 0163-1
3
INTON
U177-6 U178-3
4
PENBL1 ,I*
0166-15 0178-4
5
PINTa
0167-19 0163-2 0178-5
6
NENBLE*
0179-5 0178-6
7
PBLE*
0166-16 U178-7
8
cw
9
NO CONNECTION
10
NO CONNECTION
11
NO CONNECTION
12
PALI
0178-12 U167-16
13
AIISW*
0165-6 071-12 U97-8 0178-1 0178-13 U177-15 1187-3
11155-3
14
CND
15
MOTON*
0179-1 092-15 0178-15 R65-2 0164-12 U92-16
16
+5v
0179 6-8 LS139 16 311
i
MOTON*
0179-1 092-15 0178-15 R65-2 U164-12
2
EXTO
U179-2 0177-4
3
EXT1
0179-3 0177-5
4
NO CONNECTION
5
NENBLE*
0179-5 0178-6
6
PENBL2,E*
U167-15 0179-6
7
PENBL3 ,E*
U166-19 0179-7
8
CND
9
NO CONNECTION
10
NO CONNECTION
Il
X6-2 0179-11
12
NO CONNECTION
13
CONTROL*
37-11 U179-13 0107-28 0109-10 PlI-2
14
RESETLK*
0179-14 073-6 P19-5 U139-5
U92-16
15.106
Apple Computer Inc · 1982
Page 0457 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
jppkzcomp
KRESET*
11139-12 R80-1 C71-1. 11179-15 .77-15
16
+3V
i 9 7643 18 341-0046 F7
1
FSPACE*
11130-1 11176-1
2
CFXXX
1171-15 U180-2
11165-12 11123-12 11148-8
1171-14 1171-13 U147-6 11147-9
11165-1
3
IOSTOPD*
11123-9. U112-15 11180-3
4
11158-11 11153-1 T.fl80-4
5
C1(
11132-2 11135-1 11119-10 11123-11 11180-5 1198-27 1180-11
1184-11
6
C07X*
11180-6 1177-7 U112-13 11158-1 1172-1 11150-5 11148-13
7
RAMEN
11180-7 11176-11
8
CND
9
CND
10
CND
11
NO CONNECTION
12
WRAMEN
11180-12 11150-11
13
PHASEN
11140-12 11180-13
14
PCS6522
R68-1 11180-14
15
SEL1M
11180-15 11174-2 11150-3 1173-9 P19-2
16
RWPR
1173-5 P19-6 11180-16
17
R/W*
.715-18 .714-13 .713-18 .712-18 U3-3 11136-9 U180-17
11176-6 U165-11 11160-11
18
+sv
1181 7 556 14 Al
i
C69-2 RiS-2 11181-1 11131-2
2
C69-2 R75-2 11131-1 11181.-2
3
NO CONNECTION
4
+5V
5
11181-5 11181-10
6
CO4X*
1177-11 11131-6
7
CND
8
R77-2 U181-8 11181-12 C70-1
9
11181-9 RiS-1
10
11181-5 11131-10
11
NO CONNECTION
12
R77-2 U181-8 11131-12 C70-1
Apple Computer Inc · 1982
15. 107
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r
13
P.76-2 P.77-I tJI8l-13
14
+5V
Xl SCHOTTKY 2 DIODE A2
i
R9-1 ti-i Xi-I UlOS-lO
2
U72-24 Qi-i Xi-2
X2 3 1N4148 2 DIODE LiD
1
1J96-13 U96-iZ U96-8 P.40-2
X3-1 C75-1
2
AW(KEY
U1O7-4 P.40-i X2-2 U106-11
X2-i Cia-1 U109-3
Cil-1
X3 8 1N4148 2 DIODE Lii
1
U96-13 U96-12 U96-8
X3-1 C75-1
2
KAPPLEII*
U106-9 X3-2 LT1IL-6
P.40-2
X2-1
C18-i
C17-1
X4 8 1N4148 2 DIODE AS
+3V
2
LTPRST*
C20-1 1J113-6
U113-2
P.44-2
X4-2
X6-1
X5 8 1N4148 2 DIODE Ml
CND
2
1.1164-6
Cil-2
X.5-2 C75-2
X6 8 1N4148 2 DIODE 6
i
IJPRST*
C20-i 11113-6
Z
X6-2 U179-Ii
tJ113-2
R44-2
X4-2
X6-i
X7 I LED 2 LED M4
1
+3V
2
Xi-2 R8I-1
Yl 9 14MHZ 2 KTALI Al2
i
P.52-I QiO-3 Vi-1
2
Vi-2 Qli-2 P.49-2
Y2 4 32KHZ 2 XTAL2 A3
i
Y2-1 1172-10
2
C4-i U72-ll
C3-3 Y2-2
END OF DATA
15. 108
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i Apple /// Computer Information · Apple /// Level 2 Service Reference Manual Apple /// Computer Information Apple ///
Service Reference Manual
Section II of Il . Servicing Information
Chapter 16 Module Replacement Procedures
Written by Apple Computer . 1982
Apple Computer Inc · 1982
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'I ö1ppkz conì
APPLE III
MODULE REPLACEMENT PROCEDURES
TABLE OF CONTENTS
I. Peripheral Logic Access Cover Removal Il. Peripheral Card Removal/Installation
Keyboard Replacement Analog Board Replacement - Disk Assembly Disk Mechanical Assembly ReplacementDisk Assembly Power Supply Replacement Logic Assembly Removal Logic Assembly Replacement
Memory Board Removal Memory Board Installation Encoder Board Removal Encoder Board Installation Main Logic Board Replacement
PAGE
2-35 2-37 2-39 2-42 2-46 2-48 2-51 2-54
16.1
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1. PERIPHERAL LOGIC ACCESS COVER REMOVAL
I/I. Power down the Apple
Disconnect the AC power cord from the source
I/I. and then from the power supply receptacle of the Apple
Disconnect all external cables. Refer to Figure 1.1.
Lift up the front edge of the Apple and tilt it up 90 degrees so that it rests on the back side of the casting.
Locate the 1/4 turn locking screw on each side of the Apple and, with a flat blade screw driver, turn each one 1/4 turn counterclockwise to loosen. Do not attempt to remove these screws as they are self capturing and will not normally come out. Refer to Figure 1.2 item A.
III Lower the Apple
to the operating position and with a hand on each
side of the access cover lift up and pull forward to remove. Refer to
FIgure 1.3.
To replace the cover reverse the procedure as outlined in steps i through 5.
-
EXTERNAL PORT A PORT B COLOR VIDEO 81W AUDIO PORT C POWER SUPPLY POWER
FLOPPY
VIDEO
RS232 RECEPTACLE SWITCH
DISK
FIGURE 11
16.3
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9T
Apple Computer Inc · 1982
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*acomm
TI. PERIPHERAL CARD REMOVAL/INSTALLATION
Power down the Apple 1/I. Disconnect the AC power cord from the source
I/I. and then the power supply receptacle of the Apple
Remove the peripheral logic access cover. Refer to Procedure I.
Locate the desired peripheral card. Refer to Figure 2.1 for slot number assignment. Disconnect all cords or cables connected to the peripheral card or cards to be removed.
Grasping the card firmly with both hands (using thumbs and forefingers) gently pull straight up on the card to free it from the connector and gu-ide slots. Refer to Figure 2.2.
NOTE: If the card is too firmly captured to allow removal using just the fingers, a metal hook in the pilot hole near the top rear of the card nay be used to gain a better grip on the card. Be careful not to tilt or rotate the card, or damage to the card and/or connector may occur.
CAUTION: Never remove or install any card or device with the power or. or catastrophic shorting of signal to power supplies may occur.
To replace a peripheral card reverse the procedure as outlined in steps I through 4.
To install a new peripheral card, remove the RFI shield card (dummy card) from the desired slot and follow the detailed procedure enclosed with the new peripheral card.
SLOT #
4
3
2
I/O
SLOTS
¡IN
i
k1__ J)©@ 11rj 1»
FIGURE 2.1
16.5
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FIGURE 2.2
1.6.6
J
Apple Computer Inc · 1982
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III. KEYBOARD REPLACEMENT
Power down the Apple /1/. Disconnect the AC power cord from the source and then from the power supply receptacle of the Apple /1/.
Place the Apple on its right side with the bottom facing you. Locate, remove and retain the five (5) keyboard cover mounting screws located two each on the right and left ends and one in the front center. Refer to Figure 3.1 item A. Remove the keyboard cover. Place the Apple back into its normal operating position.
Locate and remove the two (2) retaining screws on the left end of the keyboard. Refer to Figure 3.2 item A. Loosen the right two (2) retaining screws. Refer to Figure 3.2 item B.
Remove the keyboard by lifting the left end and sliding the right end from under the loosened screws. Refer to Figure 3.3.
Disconnect the keyboard cable, located on the middle rear edge of the exposed keyboard. Refer to Figure 3.2 item C. Do not pull on the cable. Disconnect by using a screwdriver to push on the tab on the cable connector. Refer to Figure 3.2 item D.
Install the replacement keyboard by reversing the steps as outlined in 1 through 8 above. Observe that the keyboard cable makes a tight turn where it wraps to the underside of the keyboard. This is necessary if the keyboard cover is to fit properly.
Caution: Exercise care when tightening the five (5) keyboard cover screws to keep from stripping the threads in the cover.
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FIGURE 31
16.8
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Apple Computer Inc · 1982
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a__a.-.-.-u--a-sRa-a--I-a----
Apple Computer Inc · 1982
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appkz
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IV. ANALOG BOARD REPLACE1ENT - DISK ASSEMBLY*
Power down the Apple /1/. Disconnect the AC power cord from the source
I/I. and then from the power supply receptacle of the Apple
Remove the peripheral logic access cover. Refer to Procedure I.
Locate the two Tinnerman retaining clips which hold down the Disk Assembly shield. Refer to Figure 4.1 item A.
Using the blade of a screwdriver, slide the clips forward until the enlarged slots of th clips are around the mounting posts.
Remove and retain the clips.
Remove and retain the Disk Assembly shield by flexing the side out (Figure 4.1 item B) and lifting up on the shield. NOTE: The shield is only retained by the spring tension of the sides and four dimples which fit into depressions of the disk casting.
Disconnect the disk ribbon cable by pushing on the center tab of the plug with a small screwdriver. Do not pull it out by the cable. Refer to Figure 4.2 item A. Disconnect the read/write head cable. Refer to Figure 4.2 item B. Do not attempt to remove motor control cable yet. Refer to Figure 4.2 item D.
Remove and retain the two small Phillips head mounting screws which hold the Analog board at the front of the casting. Refer to Figure 4.2 item C.
To remove the Analog board, gently slide the left front of the board forward until it clears the guide holding the left edge. Then slide the right rear of the board to the left until it clears the guide holding the right edge. Refer to Figure 4.3. Tilt up the right rear of the board and lift clear.
At this time disconnect the motor control cable. Refer to Figure 4.2 item D. Note there are four nylon locking pawis which engage two holes in the board from both the top and bottom. These must be disengaged before the connector can be disconnected.
Install the replacement Analog board by reversing the steps as outlined in i through 10 above.
* The Disk Assembly is comprised of two modules, the Analog Board and the Disk Mechanical Assembly.
16.10
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p---.-. Apple /// Computer Information · Apple /// Level 2 Service Reference Manual Ipia mput
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.!nhIII!IIIlf
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FIGURE 4.2
16.12
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*p - I
V. DISK MECHANICAL ASSEMBLY REPLACEMENT-DISK ASSEMBLY*
III. Power down the Apple /1/. Disconnect the AC power cord from the source
and then from the power supply receptacle of the Apple
Remove the peripheral logic access cover. Refer to Procedure I.
Remove the disk shield. Refer to steps 3 through 6 in Procedure 1V.
Disconnect the disk ribbon cable by pushing on the center tab of the plug with a small screvdriver. Refer to Figure 5.1 item A. Do not pull on the cable.
Scribe a line on the Apple /1/ chassis along the front (Figüre 5.1 item
B) and left side (Figure 5.1 item C) of the Disk Assembly bezel. This line will provide a location reference when the Disk Assembly is re-installed.
Locate the two Phillips head screws which mount the Disk Assembly to the Apple chassis. They can be seen by looking down through the front diskette guide and door assembly. Refer to Figure 5.1 item D.
Completely loosen the two mounting screws but let them remain sitting where they are.
Loosen (Don't Remove!) the Phillips head screw through the retaining clip which holds the lower left rear edge of the Disk casting. Refer to Figure 5.1 item E.
Remove the Disk Assembly by sliding it forward until it clears the retaining spring clip and then lift it from the chassis.
Recover the two front screws from the Disk Assembly.
Separate the Axalog Board from the Disk Mechanical Assembly as outlined in Procedure IV step 9.
Insta'l the replacement Disk Mechanical Assembly by reversing the steps as outlined in steps i through 11 above. Use the reference mark made in step 5 to insure proper alignment of the Disk Assembly.
* The Disk Assembly is comprised of two modules, the Analog Board and the Disk Mechanical assembly.
16.14
.1
Apple Computer Inc · 1982
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jappkz oemputar rc.
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R1IIIIIIIII1If III.
ti
FiGURE 5.1
16.15
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Apple Computer Inc · 1982
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VI. POWER SUPPLY REPLACENET
I/I. Power down the Apple
Disconnect the AC power cord from the source
f/I. and then remove it from the power supply receptacle of the Apple
Disconnect all external cables.
III Turn the Apple
upside down with the keyboard facing you and place on
a soft pad.
NOTE: You may want to place a foam block under the keyboard to keep the unit from rocking while it is upside down.
Loosen (Don't Remove!) the two Phillips head screws located on the rear edge of the power supply bottom cover, near the on/off switch and power supply receptacle. Refer to Figure 6.1 item A.
Locate and loosen the eight (8) screws securing the power supply bottom to the chassis. Refer to Figure 5.1 item B. These screws may be captured and if so should not come free of the assembly.
Lift up the front edge and slide the power supply forward until the rear edge clears the two rear mounting screws. Gently lift up the power supply assembly to gain access to the electrical connector. Refer to Figure 6.2.
Disconnect the power supply connector by pressing in the tabs while
gently pulling. Refer to Figure 6.2 item A. 1f the leads are secured to the power supply by a wire tie, cut the tie. The power supply can now be removed.
Prior to replacing or re-installing the supply replace the wire tie, if one was removed.
When re-installing the power supply, insert the cover under the two rear most screws and lower the power supply into place.
Tighten all screws.
CAUTION: When re-installing the securing screws use only enough torque to rotate the screw. These screws will strip out the chassis, if excessive torque is applied. Also, be certain that the screw is not starting at an angle to avoid cross-threading. If it appears the screw is cross-threading, back it out and try again.
16.16
Apple Computer Inc · 1982
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FIGURE 6.1
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16.17
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Apple Computer Inc · 1982
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FIGURE 6.2
16.18 4,
Apple Computer Inc · 1982
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- lic
VII. LOGIC ASSEMBLY REMOVAL*
I/f. Power down the Apple
Disconnect the AC power cord from the source
and then from the power supply receptacle of the Apple /1/.
Disconnect all external cables.
Remove the peripheral logic access cover and all peripheral cards, or RFI shield cards. Refer to Procedure I and II.
Replace the access cover to protect disk bezel.
Place the Apple upside down on a soft pad. The rear of the Apple should face you.
Locate the ten (10) Phillips screws around the edge of the Logic access panel. Refer to Figure 7.1 item A. Locate the two (2) additional recessed screws that are about one and onehalf inches in from the rear edge of the panel. Refer to Figure 7.1 item B.
Loosen these twelve (12) securing screws. These screws may be captured and if so should not come free of the access panel.
CAUTION: The logic board is attached to the access panel, and is still connected electrically to the keyboard, disk, speaker and the power supply. Cable travel allows the access panel to be tilted from the chassis about 45 degrees.
Slowly tilt up the access panel from the right side. Allow the panel to remain resting on its edge nearest the power supply. Refer to Figure 7.2.
Note the orientation and routing of the cables. While supporting the logic board from the underside remove the speaker cable (Figure 7.2 item A), the keyboard cable (Figure 7.2 item B), the disk cable (Figure 7.2 item C), and the power supply cable (Figure 7.2 item D).
The logic assembly is now free from the Apple and can be accessed for testing and repair.
To reinstall the logic assembly reverse the procedure as outlined in steps I through IO above.
CAUTION: Make sure cables are installed correctly and are not crimped or punctured by the mounting hardware when reinstalling the logic assembly.
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- r
* The Logic Assembly is comprised of either three -.r four itw*jor e1..ment, depending upon the time of manufacture. Th nrlter Logic Asse!lbIies have
four major elements: the access panel, the Lir l.'gic hoard module, th'
Memory board module and the Encoder board module. The later Logic Assemblies
have the Encoder board incorporated into the Main Logic board, and therefore, have three major elements: the access panel, the Main Logic board module and the Memory board module.
4k
HGURE 7.1
*'4
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VIII. LOGIC ASSEMBLY REPLACEMENT
Before implementing any of this procedure the Logic Assembly must first be removed from the Apple. Refer to Procedure VII.
MEMORY BOARD REMOVAL
I. With the Logic Assembly placed flat on the work surface, use both hands to lift off the Memory board (Figure 8.1 item A) from tue Main Logic board.
NOTE: The mechanical connection is also the electrical connection. Take care and lift straight up, or bending/breaking of the male connector pins mounted in the Main Logic board will occur.
MEMORY BOARD INSTALLATION
Align the connectors of the replacement Memory board over the connectors of the Main Logic board. The best way to do this is to tilt the Memory board and align the first pins on each side and lower the raised edge slowly, starting the next pins on each side as it is lowered. CAUTION: Make sure that the board is properly oriented. The reference notches on the Memory board IC should face to the rear of the Logic Assembly (towards the output connectors).
Check that all the male pins are started correctly into the female connector of the Memory board. If any of the male pins are not properly started, lift up the Memory board slightly and "wiggle" it until the pins are aligned.
Once the pins of the connectors are all aligned, gently push straight down on the connectors on both sides of the Memory board until the connectors are fully seated.
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C. ENCODER BOARD REMOVAL (early version of Logic Assembly only)
Locate Encoder board mount standoff. Refer to Figure 8.1 item B.
NOTE: The Encoder board connector on the Main Logic board has been re-formed for clearance purposes. This repositioning does not allow the strïdoff to match the pilot hole of the Encoder board. Therefore, the standoff can be removed, if you choose.
Remove the Encoder board from its connector.
D. ENCODER BOARD INSTALLATION (early version of logic assembly only)
1. Engage the replacement Encoder board on the connector and press into place.
E. MAIN LOGIC BOARD REPLACEMENT
1. Remove and retain the Memory board as detailed in Procedure VIII section A.
Remove and retain the Encoder board as outlined in Procedure VIII section C. (early version of logic assembly only)
Locate the retaining screw. Refer to Figure 8.1 item C. Remove and retain. Slide the board out from the peripheral connector opening of the access panel.
Lift off and set aside the Main Logic board.
CAUTION: Make sure that the insulating mylar shield (or substitute insulator) located between the board and the access panel remains in place before replacing the Main Logic board.
Place the replacement Main Logic board into the access panel, making sure that the peripheral connectors are aligned into their respective cutouts in the rear of the access partei.
Replace the retaining screw.
Replace the Encoder board. Refer to Procedure VIII section D.
Replace the Memory board. Refer to Procedure VIII section B.
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o
1
FIGURE 8.1
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élPpkz
APPLE ¡/1 DEALER SERVICE DIAGNOSTICS REFERENCE
1NTROD1CTION
I/I The DiAGNOSTIC disk (part #652-0327), used in conjunction with this document
will allow you to diagnose Apple
failure modes at the modular level.
Additionally, RAN failures may be diagnosed to the chip level.
The descriptions of the tests that follow contain information relative to the
specific test environment that 'u are using. For instance, it will be
necessary to evaluate test resxilts differently when using color verses BW
monitors.
EQUIPMENT REQUIRED
Apple /11 computer.
External Disk /1/ drives natiwe to system under test.
B&W monitor w! cable.
I/I Apple
Diagnostic diskette.
I/I Apple
External Test diskettes as required. *
* See MAKE TEST DISKS.
OPTIONAL EQUIPMENT RGB Color Monitor, NTSC CaL.nr Monitor, or Color Receiver. Suprmod'II, for Color Receiver. NTSC adapter, for Color Receiver and NTSC Color Monitor.
Cables.
EQUIPMENT SETUP
As ALWAYS, insure that the ApIe 11f POWER is OFF BEFORE )NNECTING OR
I/I. DISCONNECTING AIq!THING from the ppie f // or any equipment connected to th*
Apple
Connect external drives natiwe to system under test. Connect BW Monitor to JiO or, Where available: connect Color Monitor, NTSC adapter, and Sup'r'mod II to J5, as required. â. Connect power sources to system under test. Turn on monitor power. Install Diagnostic diskette in UUT internal drive. Install External Drive Test diskettes in external drives as reuiteii.
I/I RUNNING DIAGNOSTICS
There are three critical operations that happen in order to rmn Apple
Diagnostics.
With proper test setup configured as above and Diagnostic diskette installed
I/I in internal drive, turn on Apple
power.
Power on internal diagnostic.
This fast internal diagnostic is described further in
f/I Apple
owners guide. Refer to that document with
questions on the start-up diagnostic. Let it suffice to
say that these tests must be passed before the disk
boot process may begin.
Boot Disk boot is a several stage process that begins with the execution of a code block contained in ROM. On a successful
16.25
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(
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f/I APPLE
DEALER SERVICE DIAGNOSTICS REFERENCE
boot, control is passed to code loaded from disk. Several loads and transfers of control are made resulting in the loading and execution of the Diagnostic program.
3. Diagnostic Having come this far is a vote of confidence for correct system operation. Now, under control of the Diagnostic, a thorough investigation of system hardware resources may begin.
DIAGNOSTIC NU Alter a sucesaful boot load of the diagnostic program, the following menu will be presented.
TEST ALL
VIDEO SOUND RAN MAP
DISK KEYBOARD ROM
(NOT TESTED) (NOT TESTED) (NOT TESTED) (NOT TESTED) (NOT TESTED) (NOT TESTED)
RAM TEST MAKE TEST DISKS
CHOOSE:
ESC( APE
A(CCEPT S(KIP
The menu you actually see on the screen will show the 'TEST ALL' option in inverse video. This is to indicate that if the A' or A(CCEPT key is depressed) the inverse menu option will be selected for execution. Individual tests or the two special functions may be made candidates to A(CCEPT by S(KIPing through the list of manu options, with the 'S' or S(KIP key. As a menu option is S(KIPped, it is returned to normal video, and the next logical
menu option is inverted or highlighted. Finally, the Diagnostic program itself nay be exited by depressing the 'ESC', or ESC(APE key. Actually the TAB key performs this function as well. This
will feature allows diagnostics running on an Apple JE that use the same menu
selection technique to 'feel' the same. ESC(CAPing the Diagnostic tests
prompt the user to reboot.
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computar r
I/I APPLE
DEALER SERVICE DIAGNOSTICS REFERENCE
TEST ALL
A(CCEPTin8 this option will sequentially perf orn all of the diagnostic modules below:
VIDEO SOUND RAM MAP DISK KEYBOARD ROM
Each of the Diagnostic modules operates in a manner identical to that encountered if each were A(CCEPTed individually. For a detailed discription of the various Diagnostic modules, consult the following sections for each module by name.
VIDEO
The VIDEO Diagnostic module will test all of the various screen and color
f/I. modes available on the Apple
You will be asked to make a subjective
evaluation of each of the video node tests. Of course if you are not using a
Color Monitor, you will not be able to verify that the colors used in the test
are actually present. Users of B&W Monitors will only be able to observe the
different colors used as 16 shades of grey. An additional inconvenience that
B&W Monitor users will have to put up with is that many B&W Monitors are not
capable of displaying 16 linearly arranged shades of grey with a single
setting of the mortitor controls. In the description of each of the video mode
tests, a warning will be given if this problem is anticipated.
The responses used for all of the video mode tests uses the format below:
SPACE BAR.
RETURN KEY ESCAPE KEY LEFT ARROW KEY
TEST PASSES
TEST FAILS LEAVE VIDEO TESTS RETRY TRE TEST
Except for the text node and 16 color tests, each of the tests will display the same pattern: A picture of Winston Curchill will appear in the upper left corner, and a grid of diagonal lines will appear in the upper right corner, followed by a prompt field at the bottom of the screen.
RIRES MODE i - B&W pattern.
RIRES MODE 2 - B&W pattern.
280 x 192 COLOR RIRES MODE 1 - Will appear as a negative image. A color monitor will show red and black.
280 x 192 COLOR HIRES MODE 2 - Will appear as a green and white! or yellow pattern.
16.27
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4,
APPLE /1/ DEALER SERVICE DIAGNOSTICS REFERENCE
SUPER HIRES MODE i - 86W pattern as in 1.
SUPER RIRES MODE 2 - 86W pattern as in 1.
AHilES TEST i - On this and test 8, the screen will be divided into 4 horizontal sections, each a different color. The top half of Winston and the diagonal pattern are blue. The first two lines of the message are green, and the last two lines of the message are gold or orange. You may expect to have difficulty resolving the gray scale differences that represent these colors on a B&W Monitor on this and test 8.
AHIR.ES TEST 2 - pattern as in 7.
COLOR BAR & CRAY SCALE TEST - will display vertical bars of different colors. The border is blue. The colors, in order from left to right are: white, aqua, yellow green, pink, grey, orange, brown, light blue, medium blue, grey, dark green, light purple, dark blue, magenta, and black. When viewed on a 86W Monitor, these colors will appear as a grey scale darkening from: white on left to black on right. You may expect to have difficulty resolving the gray scale differences that represent these colors on a 86W Monitor on this test. Although you will not be prompted for a response on this test, you must respond in the manner defined above. (That is... press space bar if test passes, etc.)
APPLE II TEXT MODE i - This screen will display:
THE QUICK BROWN FOX JUMPS OVER THE LAZY DOGS
abcdefghijklmnopqrstuvwxyz 0123456789 (inverse)
(flashing)
APPLE II TEXT MODE 2 - will display:
22222222222222222222 22222222222222222222 22222222222222222222
222 222 222 22222222222222222222 22222222222222222222 22222222222222222222 222 222 222
2 2222222 2 222 22 22 2 222
22222222222222222222 22222222222222222222
APPLE /1/ 40 COLUMN TEXT MODE - display will be divided into sixteen
16.28
Apple Computer Inc · 1982
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mptt f
I/f APPLE
DEALER SERVICE DIAGNOSTICS REFERENCE
blocks each of one of the sixteen colors white through black. Each block ril1 have a text phrase in a complementary color that describes the background color. You may expect to have difficulty resolving the gray scale differences that represent these colors on a B&W Monitor on this test. Although you will not be prompted for a response on this test, you are required to respond in the manner described above.
13. APPLE /1/ 80 COLUMN TEXT MODE - will display characters that are much
smaller. In fact, you may expect to have difficulty reading these characters on a NTSC Color Monitor or Color Receiver due to the inherent 3.8 mhz bandwidth limitation of these types of displays. BW composite video and RGB Color nxnitors will display this test screen in full splendor.
SOUND
SOFT BELL - The speaker will beep on and off. Press the space bar if you hear the sound. Press the return key of you do not.
HARD BELL - Same as 1. above but at a different pitch.
DAC OUTPUT - The digital to analog converter will produce a sound at the speaker output that periodically is of zero amplitude that grows in amplitude to be cut off again to zero amplitude. The change in amplitude should be regular and of constant pitch (except for the cut off of sound at max amplitude).
RAM MAP
This test does a cursory test of the rae to determine the configuration in the unit ixder test. The results will be displayed as a message discribing the rae map determined in the test. cg:
RAM MAP GOOD FOR A 126K SYSTEM
If the message does not correspond to the physical configuration determined by inspection, press press return key to reject test. If the message describes the true configuration, press the space bar.
DISK
At this time you will be prompted to remove the Apple /1/ Diagnostic Diskette,
and to insert the Internal Drive Test Diskette. Previous to this point, you should have inserted any External Drive Test Diskettes in external drives as required. This setup is acknowledged by depressing the return key. You will then be required to enter the number of external drives connected to the unit under test. At this point the test runs automatically, terminated with a disk test summary f or each drive specified above.
I/I Upon completion of disk tests, you will be prompted to reinsert the Apple
Diagnostic Diskette. You will acknowledge this operation by depressing the return key.
16.29
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Apple Computer Inc · 1982
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f/I APPLE
DEALER SERVICE DIAGNOSTICS REFERENCE
KEYBOARD
ALPHANUMERIC - depress each of the keys on the alphanumeric keyboard end verify that its representation on the display is removed. Three keys require special key stroke sequences to test their function. These sequences are described at the top of the keyboard test screen. If, after depressing all alphanumeric keys, some key representations remain on the test display, then type the sequence CTRL-S.
SPECIAL FtflCTION KEYS - Depress the ALPHA LOCK key and note that the state of the ALPHA LOCK key changes. Leave the ALPHA LOCK key in the UP state.
Depress OPEN APPLE key and note that its state is reported as down.
Depress any key, (except SPACE or RETURN), and hold. Note the REPEAT SPEED. Anything from 5 to 15 / sec is acceptable. While holding a key down in repeat mode, depress the CLOSED APPLE key. Note that the REPEAT SPEED will increase to approximately double the normal rate.
Accept or reject this test as prompted at the bottom of the screen.
The SOLID APPLE key test will prompt you with a key stroke sequence that must be followed exactly. Perform the indicated operations as the test proceeds automatically.
NUMERIC KEYPAD - same as in 1. above.
ROM
This test le a straight forward go, no-go test, that reports the message: ROM
PASSES... / ROM FAILS...
At this point, if you had selected the TEST ALL option, the main menu will appear with the test suary to the right of each of the test options.
16.30
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Apple Computer Inc · 1982
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I/I APPLE
DEALER SERVICE DIAGNOSTICS REFERENCE
OTHER DIAGNOSTIC OPTIONS
The Diagnostic Diskette menu contains two other options that may be accepted for execution. These options are separated from the options described above because they are 'one way' trips, in that upon completion of the execution of these modules, you will be required to reboot the unit under test. These modules are described below.
RAM TEST
This test performs a thorough exercising of all ram contained in the system. This test takes several seconds to complete and should not be interrupted. On invocation of this module however, you are given the chance to return to main menu. Successful completion of this test module is indicated by the display of a diagnostic message on the upper left hand corner of the display. This message will contain a matrix of dots (.) and ones (1), if ram errors are encountered. These are placed in the matrix in a logical fashion. Ran chip failures may be determined by comparing ones (1) found in the displayed matrix against the ram chip locator matrix below.
39 38 37 B6 85 84 33 82 * 817 816 315 814 813 B12 Bu 810 * 39 38 87 36 B5 84 83 82 B17 816 BiS 814 813 812 811 310 Cil C16 CiS C14 C13 C12 Cli Cb D9 D8 D7 D6 D5 D4 D3 D2 017 D16 DiS D14 D13 D12 Dli DiO C9 C8 C7 C6 CS C4 C3 C2
* DISREGARD THESE WO ROWS ON 96K SYSTEMS NOTE: All other diagnostic messages displayed shall be disregarded.
No prompt will be given to reboot the system under test.
MAKE TEST DISKS
You will use this module to prepare Drive Test Diskettes used in the DISK test
module described above. Upon accepting this module you will be prompted to remove the Diagnostic Diskette. You will then be prompted to enter the drive number corresponding to the test diskette you wish to make. Enter this number <1 - internal , 2..4 - external>,
f olloved by depressing RETURN. You will be asked to insert a blank diskette into internal drive and acknowledge by depressing RETURN. The utility will inform you that it is creating the test diskette for the drive that you specified in the operation above. A 'DONE message' will be displayed ori completion. You will be asked if you want to make another diskette. If you reply 'y' the above process will be repeated, otherwise you will be prompted to reboot.
16.31
Apple Computer Inc · 1982
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Apple Computer Inc · 1982
I
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4
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..-_ __.__-_..--.---.---.____.
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a £
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ENGINEERI G RElEASE
This revision superse s all previous verSiC.
Please destroy all old opses.
NOTICE OF PROP
The intormatiOfl co
IETARY PROPERTI
ained herein s IN
proprietary properly f Apple Computer. tn
The posseszOr agree to the toIIowiflg
Il) To maintain tnìs ocument in conlideflct
(Il) Not to reproduC (Ill) Not to reveal c
copy it. :!ith it in whole or par
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple Computer Inc · 1982
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-I
7Iof0leflCa*,SS.)a.U.lovsqer.n1.p0Ct,4CeaVt .Ic1.%3SjMAUrrJfff.llNalV.Cx5n$SolbCn%bt'acITnflra1n1a5s
l 514(61 .tt'suzz)
ENGINEERING R E LEASE This revision supersedes all previous versions.
Please destroy all od Copi. NOTICE OF PRO'EiF1;V PROPERTY
The infoim.tion cort,iid herein is the
proprietary property ol API k Computer, Inc. The possessor agrees to 1h tollowing;
(I) To mainLan l -cun tnt in contidence. (li) Not to reproduce or ccpy it. (Ill) Not Io r.veal or pubhaF ft ïn whole or part
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Page 0493 of 0730
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
ÚP2 cornpucr Inc.
DOCUMENT NO.
PAGE
4
064-0167
0F
14
DUMPER LOCATIONS
SCREW
6 PLCS
FIG.2
LOG)C BOARD ASSEMBLY
BOTTO.M PAN
DRAWN BY
OPERATION NO. TITLE
7. eLgrTh' A20
LOGIC BOARD PAN ASSY.
16.34
Apple Computer Inc · 1982
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cappcz oemputar ¡nc.
-POWAESRSSUMPLPLYY
¶CREW5
S PL..
DOCUMENT NO. PAGE 11
064-015&.
OF
14
FI.5 -
SUPPLY
CA9LE
SCREW5 (a)
- CASTING
REAR
DRANBY
I0PREAOTI4OON NO. ITIILEINSTALL POWER SUPPLY,
16.35
Apple Computer Inc · 1982
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ccTpp rnper
NO1
PAGE
3
06 4-0022
OF
FIG. I LOGIC-
BOARD PAN
KEYBOARDLOGIC BOARD CABLE
LOGIC BOARD A5SEMBLV
¡-SPEAKER CABLE
-DISK DRIVE-
LOGIC BOARD CABLE
ath4J DRAWN BY
IOPERATION NO.
050
TITLE
INSTALL LOGIC BOARD ASSY.
18.36
Apple Computer Inc · 1982
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i Apple /// Computer Information · Apple /// Level 2 Service Reference Manual Apple /// Computer Information Apple ///
Service Reference Manual
Section II of Il Servicing Information Chapter 17 General Appendix
Written by Apple Computer. 1982.
Apple Computer Inc · 1982
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ep -
FEAILrRING:
STARRING:
,
APPLE /1/ SYSTEM OVERVIEW
E] EXTENDED DISPLAY [J EXPANDED RAM
] NEW PROCESSOR DESIGN [3 BUILT IN I/O 1] APPLE LI EMULATOR
THE APPLE /1/ PROCESSOR
* 6502 rNsrRucTtoN SUBSET * RELOCATABLE BASE REGISTER PAGE * RELOCATABLE STACK * 256K BYTE ADDRESS RANGE
vio go
* NTSC COLOR COMPOSITE VIDEO * NTSC B/W COMPOSITE VtL)EO * SYNC * 4 PRIMARY INDEPENDENT VIDEO LINES * MIX TO FROM RGS APPLE COLORS
THREE LINES CAN DRIVE TTL RGB MONITOR FOUR INDEPENDENT VIDEO OUTPUTS CAN BE GENERATED
DISPLAY MODES
* GRAY SCALE ON 51W OUTPUT * RAM CHARACTER GENERATOR (128 CHAR.) * 40 X 24 CHARACTER 31W TEXT (2K BYTES RAM) * 80 X 24 CHARACTER B/W TEXT * 40 X 24 CHARACTER COLOR TEXT
(16 BACKGROUND, 16 TEXT COLORS) * 280 K 192 31W HIRES (8K RAN) * 560 X 192 5/W HIRES * 140 X 192 16-COLOR RIRES * 280 X 192 16-COLOR HIRES WITH 40 X 192
BACKGROUND/FOREGROUND RESOLUTION
I/O
* FOUR APPLE II BUS PERIPHERAL SLOTS * ONE BUILT IN DISK DRIVE * CONTROLLER FOR THREE ADDITIONAL DRIVES * RS 232 PORT (COMPLETE) * SILENTYPE PORT * TWO PADDLE PORTS (AID INPUTS) * EXTERNAL SOUND JACK (SIX BIT AUDIO,
HARDWARE BEEPER * EXPANDED VIDEO LINES
17.1
Apple Computer Inc · 1982
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acompr
* CLOCK/CALENDER
I/O BLOCK TRANSFER * PERMITS LIP TO I PAGE (256 BYTE) FAST
I/O TRANSFER WITHOUT DMA HARDWARE ON PERIPHERAL * TRANSFERS AT UP TO THE RAM CYCLE RATE APPLE II EMULATION RESTRICTIONS * NO LANGUAGE OR ROM CARD * PADDLES ARE DIFFERENT * ENTER WITH SOFTWARE BUT ONLY RESET WILL EXIT
17.2
Apple Computer Inc · 1982
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Apple III I/O System Programmer's Guide
Debugging Tools
6.1 Development Monitor
The current version of the diagnostic/boot ROM includes a monitor that nay be useful for debugging. TRE MONITOR IS NOT A PART OF TRE SUPPORTED Apple III SOFTWARE AND IT MAY BE CHANCED OR DELETED IN FUTURE VERSIONS 0F THE BOOT ROM. MONITOR SUBROUTINES MUST NOT BE CALLED FROM DRIVERS OR INTERPRETERS.
6.2 Monitor Commands
The monitor commands are listed below. Commands are read directly from the keyboard; blanks are not used except as data separators in a (byte list). Command lines nay be up to 79 characters long and are always terminated by a
RETURN. Multiple commands may be entered on the same line using a slant (I)
as a command separator. Numeric data is always entered in hex. ASCU
strings may be entered by enclosing then in single or double quotes. If single quotes (') are used, bit 7 of each byte will be clear; if double quotes (") are used, bit 7 will be set.
(address) :: numeric value O..FFFF (address range) :: (address) I (address).{address)
<byte) ::= numeric value O..FF I Single byte string (byte list) ::a one or more bytes separated by blanks (block mum) ::- numeric value O..117
(address range) (address) : (byte list) (byte) < <address range) S (address) < (address range) M (address) < (address range) V (block nun) < <address range> R (block nun) < (address range) W (address) G (address) J
U X
RETURN
Memory dump Memory store Memory search Memory move Memory verify Read disk Write disk Subroutine call (JSR) Execute code (JMP) Call user subroutine (JSR $3F8) Repeat cammand lime Continue memory dump
When dumping memory, the output can be suspended then stepped by pressing the
space bar; pressing any other key will resume normal output. Pressing the TAB key vili terminate processing of the command line.
6.3 Escape Commands
Escape commands may be used during command input to move the cursor or control the display. Escape mode is entered by typing an ESCAPE; the cursor
is changed to a flashing plus sign (+) to identify escape mode. Any character that is not an escape command will terminate escape mode.
f or X 4 or jC
or H'
. or U'
Move cursor up Move cursor down Move cursor left Move cursor right
17.3
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- Apple III I/O System Prograer's Guide
L
Clear to end of line
P
Clear to end of page
S
Home cursor and clear screen
4
Set 40 column display
8
Set 80 column display
6.4 Zero Page Locations
58 59 SA 53 5C 3D 714,75
76,77 78,79 7A,73
Wjdow left Window right Window top Window.bottom Rorizomtal cursor position Vertical cursor gosition
Al A2 A) A4
6.5 Entering Addresses
adri adrl.adr2 adr3<adrl.adr2
6.6 Pointer Usage
Memory dump: Memory store: Memory move: Memory verify: Memory search:
Al, AZ A :- adri Al, A) :- adri A2 :- adr2 Al, A) :- adri A2 :- adr2
A4 :- adr3
(Al) (A)) (A4) :- (Al) (A4) : (Al) A4 : (Al)
17.4
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Apple Computer Inc · 1982
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a compu
r
APPLE 1/1 LOGIC SIGNAL SOURCE
The location of the signal source is described first by the page number of the schematic followed by its coordinates.
SIGNAL
6551se1* aO-a7 a8-all a12-a15 abki abk2 abk3 abk4 ahires altlores altstk* apple j* apple jj*
arO anyky arO ari ar2 ar3 ar4 ar5 ar6 audio ax,ax* axco bckswl,3 bi
cO8xn-eOFxn cOxxn-clxxn
clm,clm* ci4m,* c35m,c3,5m* c7m,c7in* caplk* casO* casl* cas2* cas3*
cas47*
cas5,6* ch8O* clkbat cikenSO
LOCATION
5-4a 4-4d 4-4e 4-4b 3-2c 3-2e 3-2c 3-2c 6-4a 6-4a 5-lb 9-4b 9-4b 3-3b 9-4c 3-3d 3-3d 3-3c 3-3e 3-3c 3-3b 3-3b 8-lb 10-Sa 5-2a 8-4b 10-lb 5-4a 5-4b 5-4b 1O-4c 1O-4c 10-4b 9-4b 3-2e 3-2e 3-2e 3-2e 3-2e 3-2e 6-4a 5-2d 6-2d
MEAN INC
ACIA SEL ADDRESS BUS (EXTERNAL)
ADDRESS BANK i ADDRESS BANK 2 ADDRESS BANK 3 ADDRESS BANK 4 AHIRES APPLE II LORES ALTERNATE STACK APPLE SWITCH 1 APPLE SWITCH 2 RAM ADDRESS X ANYKEY (DEPRESSED)
ADDRESSS MIJX SELECT BANKSWITCH BLANKING ADDRESS DECODE ADDRESS DECODE CLOCK 1 MEGHERTZ CLOCK 14 MEGHERTZ
CAPS LOCK SWITCH COLUMN ADDRESS SELECT (RAM)
CHARACTER (80 COLUMN) CLOCK BATTERY CLOCK ENABLE 80 (COLUMN)
17.5
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ppcompt*arn
clkirq* clrkl* clrstrb* coirgate
C O19
control* cs6522 cts cOOx-cO7x cxxx
c-f xxx dO-dl
daO,da7
data tri
dbO-db7 dcû,dc7
d cd
devsell ,6* dhires dmal* dmaok dphO,dph3 dsply dar dtrdy,*
dtr dvø,dvl dxo,dx7 en257 en8304
enbi 1, e*
enblt,i* enbi2, e*
enbl3, t
encwrt enhreg*
ensel.
e n to
PDLO
ext *
ext a pk f fcx*
f fdx*
f f ex*
f Le tdout f space*
gph i
g ph 2
hO,h3 h4,h5 hires
h pe *
idO-id7
i nd *
5-ic 6-4a 6-3a 10-Lb 10-ib 9-Ab 1O-4a 8-Ic 5-3a 5-4b 5-4c
1O-3b 8-ic 1O-4b 6-3d 8-ic 5-Aa 5-Aa 4-4d
7-4 b
10-lb 8-ic 9-Ac 8-ic 6-4d 6-3a 5-3d 5-3d 7-2c l-2c 7-2b 7-2b l-2e 3-3c l-2e l-2e 5-2a 7-4b 8-lb 5-3e 5-3c 5-3c
10-lb 5-3b 5-3e 5-3e
10-2d lO-2d
5-2a
I O-2d
A-3c 3-3a
17.6
CLOCK INTERRUPT
CLEAR STROBE (KEYBOARD) COLOR GATE COMPENSATE CONTROL KEY
CLEAR TO SEND (ELA) ADDRESS DECODE
ELA
VIDEO BUS (CHAR GEN OUT) DATA CARRIER. DETECT DEVICE SELECT DHIRES DIRECT MEMORY ACCESS IN DMA OK DISK (MOTOR) PHASE X
DIS PLAY
DATA SET READY (ELA) DATA READY (KEYBOARD) DATA TERMINAL READY VIDEO BUS (RAM LATCH OUT) VIDEO BUS (COLOR LATCH OUT) ENABLE RAN BUS TO DATA BUS ENABLE MPU XCVR ENABLE DISK i EXTERNAL ENABLE DISK I INTERNAL ENABLE DISK 2 EXTERNAL ENABLE DISK 3 EXTERNAL ENABLE CHARACTER RAM IJRITE ENABLE GRAPHICS REGISTER (LATCH) ENABLE EXT PRINTER SELECT ENABLE SERIAL I/O PADDLE ADDRESS O EXTERNAL (DRIVE) EXTERNAL SPEAKER
VIDEO STATE VIDEO STATE
INTERNAL DATA BUS
Apple Computer Inc · 1982
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tnh* int*
b lankin
ioen
i onmi
iosell,4* iostopd* iostrb* io sync irql,4* i r'/w i r/w
k bin t*
k bo *
kreset* kvcc
ldp s *
mix
mux 1 ntni *
ntsca,b oe374
pa B
pal5 page 2 pcasø*
peas 1* pc as 2* peas 3*
pdtnt*
pd 12
pdlen
pd lot *
pg2* phO
porirs t
prasO, 3* prasi,2* pras4, 5* pras6, 7*
p re im
pwrdwu* qO,q3
ram nw
ras, raa*
raqO, 3* rasi, 2*
ras 4, 5* ras6, 7*
r bi
rcikpwr rcolrgt rddata
r dy
5-4e 7-2d 8-3c 5-lb 9-2b 5-4b 1O-4b 5-4b 4-3b S-3c 4-Zc 4-3c 9-2c 5-3a 9-4b 9-4b 1O-4c 5-2a 3-3c 9-lb 6-2b 6-4a 4-4b 4-4b 5-2a 3-2d 3-2d 3-2d 3-2e 5-le 5-2a 5-2a 8-3a 6-4a 1O-3a 9-3a 3-2b 3-2b 3-2b
3-2 b
1O-4b 5-2d
1O-3c 3-lb
1O-4b 3-lb 3-lb 3-lb 3-lb
10-ic 5-2d
lO-le 7-2d 3-3a
17.7
INHIBIT (ROM) INTERNAL (DRIVE)
I/O (DEVICES) ENABLE I/O NON MASKABLE INTERRUPT I/O SELECT I/O STOPPED I/O STROBE I/O SYNC
INTERNAL READ/WRITE
KEThOARD INTERRUPT KEYBOARD STROBE(ENABLE KEY TO DATA RESET KEY KEYBOARD VCC L(AD PARARELL SHIFT REGISTER
ENABLE COLOR LATCH OUTPUTS PROCESSOR ADDRESS 8 PROCESSOR ADDRESS 15
PROM CAS X
POWER DOWN INTERRUPT (CLOCK) PADDLE ADDRESS 2 PADDLE ENABLE (ADC RAMPSTART) PADDLE OUT (RAMPSTART)
PROCESSOR O POWER ON RESET PROM RAS X
PRE 1 MEGAHERTZ POWER DOWN Q STATE (ZMEG)
RAM ROW ADDRESS SELECT
ROM BLANK CLOCK POWER ROM COLORGATE READ DATA (DISK) READY
Apple Computer Inc · 1982
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cont ,
rdy*
reset*
rset1k* rfteld
r fsh rgbi, rgb8 romsel*
roase 1,1
rrormfshe 12
rtcwrt
rts
rs ync rwpr rwrpro t r /u 8399
s 50/60 sco
scr
scrrt
sel 2m*
se 1374
ser shift*
spkr*
s um4
s uiu3
s um2
s umi
synch t cwrt t ext tromsel trolnsel* tsadb*
t xd
useib
vO, vi
v2 , v5
va vb,vc vbl.
we 2114
wrda ta
w rame a
Wrprot wrreq xO,x7 yO,y9 zO,z7 zpage*
3-3e
9-2 b
5-lb 10-lb
10-lb
6-3b 5-3b
5-lb 5-lb 10-lb
lO-le
8-ic
10-ic
5-lb
10-i b
3- 3a
10-lb
5-ib
l-2e
5-lb
5-lb
6-4a
5-ib
9-3c 5-3a 3-3d 3-3d 3-3d 3-3d
10-lb
10-lb 5-2a 4-3a 5-3d 4-4d 8-ic 3-2e
1O-2c
LO-2b
lO-2c 10-2e 1O-ic 6-4d 7-2d
IO-4a
7-2d 7-2d 9-4c 9-4e
5-ib
4-4b
RESET LOCK REFRESH RED,GREEN,BLUE ROM SELECT
ROM REFRESH ROM TIME CHARACTER RAN WRITE REQUEST TO SEND ROM SYNC
READ WRITE
SELECT 50 HZ/60 HR
SERIAL CLOCK SCROLL SCREEN SELECT 2 MEG
SELECT ORDER 0? 374 'S to dvx bux
SERIAL DATE SHIFT KEY SPEAKER (STROBE)
TIME CHARACTER RAM WRITE
MICROPROCESSOR SELECT B RAN BUS
WRITE ENABLE CHARACTER RAM WRITE DATE (DISK) WRITE RAN ENABLE WRITE PROTECT WRITE REQUEST KEY SCAN KEY SCAN ZERO PAGE ADDRESS BITS ZERO PAGE
17.8
Apple Computer Inc · 1982
Page 0505 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple Computer Inc · 1982
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I
2
I
NOTE; 135.1St OIlIwISL SflCifllD
ic. C014130StC13JT3 wrvI40«JT
5OCKT
Z)ALL 07H15. COI4PONEJJTS TO i-.av APPRO.m3aTE I.0 SOCII,LT3
au.ns wines as. vo a. tac.. auss naas (ira.t u n).
NOTI PO&ARIZATION
eeT z COtP.JECT5 TO me RIVETCO TO eOaoO B4FORE 5OLoRÍNß(rreMOaß
DIOA5MTI1CA3STt(I*C,1L.3DE0 U1T3EHTETp(COIIOE.TIIPKtCT3PIlItL.ECEIIMEAUCSSTSTPEIMCIILLTY1tPAPluIIENStio34t4Rj1uCOnISoOmNr&s0SiLc1eatPuaoOTs(CaTitO
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CONTAINII4C, THIS IC. -
?PILS.
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Page 0506 of 0730
4 PCS
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ir
7 PLOS
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
HOW TO READ PROM (ROM) LOGIC EXPRESSIONS
X' -- The single quote at the end of an expression means that the state of the signal is true when low, or it may represent the inversion of the state of the signal.
* - Defines a logic AND operation. The expressions on either side of the asterisk is ANDed.
+ - Defines a logic OR operation. The expression on either side of the asterisk is OR'd.
() -- Defines the boundaries of a logic expression. A new expression is defined by what ever is inside of the brackets.
RULES FOR INTERPRETATION
Always interpret (transform) the expression within the brackets first. Interpret AND (*) logic operations before OR (+) operations.
EXAMPLE:
Given:
INPUTS: AIISW' MIX VBL
RIRES V2
TEXT V4
OUTPUT: DEIRES - (AIISW*HIRES*(TEXT+MIX*v2*v4) '+AIISW' *HIRES)*f3L'
LOGIC REPRESENTATION: MIX
TEXT AIISW HIRES
io
dei.
......±M.
.'- ,z- ,.
r' J-,s,
11 --2-h.
.t-
6
i.,,
)-_-, +z
2--s
DRIRES VBL
17.10
Apple Computer Inc · 1982
Page 0507 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
PROM 341-0043
A-All
B-Al 2
C-A13 D-A14
E- IO SYNC F_SEL.2M#
G-ABK4 H-PA8 L-A15 J-ZPACE' D0-S399
Dl -PRDY' D2-IND'
S399.ZPACE*PAB'*A15'*A14'*A13'*Al2*A1l
PRDY' .IOSYNC*SEL2M*AZK4
IND'(A3J4*(ZPAGE*PA8')')'
17.11
Apple Computer Inc · 1982
Page 0508 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
ppcomp*m
PROM 341-0042
A-A 13 8-All
C-A15 D-LND' E-DHIRES F-ABK1 C-ABK2
H-A81C3 1-A14
J-AY
D0-PCAS4 , 7' D1-PCAS5 ,6'
D2-PCASI' D3-PCASZ'
ASK1 ')*(A14'*A13'+A14*A13)).
AY*IND*ABK3'*(A3K2#*AKl '*Aj3+K2'*A5Kl+K2*Kl '*Al5')*Aj4+Ay*IMD'*K1*
A13'))'
PCASI -(DRIRES
PCAS2 -(DuRES
AY*IND*ABK1
17.12
Apple Computer Inc · 1982
Page 0509 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
ROM 341-0032
3-3
C- S4
D-VBL - PACE2
F-AIISW' C-HIRES H-MIX
I-TEXT J-V2 K-V4
D0 PC2
D1-SEL374 D2-COLRKL D3-AHIRES D4-CH8O'
D5-OE74
D6-AIILORES
D 7- DuRES
PC2AIISW*(uIRES*MIX'*TEXT , ) '*HIRES*PACE2*54*VBL'
SEL374..(VBL'*(AIISW*(PAGE2'*(TEXT +MIX*V2*V4)'+PAC32*(TEXT +MIX*V2*V4))+ ÀIISW'*(HIHES(PAGE2*S4)'+I!IRES'*(PACE2*s4))))'
COLRKL'(AIISW*TEXT +AIISW*(HIR!S'*(MIX+TEXT ')+HIRES*TEXT '))'
AHIRESa'AIISW'*(RIRES*MIX*TEXT )
C1i8O'(AIISW'*MIXy
0E374(ALISW*HIRES'*(TExT +MIX*V2*V4)'AIISw*MIX'*TExT )'
AIIL0RESAIISW*HIRES*(TExT +MIX*V2*V4)'+AIISW'*HIR.ES*MIx*TEXT
DHIRES(AIISW*uIRES*(TEXT +MIX*V2*V4)'+AIIsw'*HIRES)*vßL
17.13 ,1
Apple Computer Inc · 1982
Page 0510 of 0730
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- Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
PROM 341-0046 LI/BO
A-C 1M B-007 r
C-RAMEN
D- D SP
E-LOSTOPD'
F-CFcXX GFSPACE
M-R/WN I-RWRPROT J-SEL2M' DO-PCS6522 DI -PHASEN D2"WRANEN
PCS6522-(IOSTOPD' C IM+FSPACE' * 1M')'
PHASEN_((SEL2M'*CO7X')*IOSTOPD'*FSPACE+FSPACE*C1M'+C1M'*SEL2M4C1M'*DSPLY*
RAllEN)'
RAMENRAllEN*(RWRPROT*C_FXXX)'áR/WN'*(DSPLY*C1M')'
17.14
Apple Computer Inc · 1982
Page 0511 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
pplacompr
PROM 341-0056
A-All
B-Al 3
C-A14 0-AlS E=R/WN F-DHIRES G-AY H-ABK2 1-PRASI ,2
J-PRAS03
DO-PCASO' D1-PUSEL.B 02-PCASO, 3 D3-PCAS3'
PCAS(Y-(PRASO,3 *(DHI5'*Ay'+Ay*(A15'*A14*A13'*A11 '*R/WN'+A15'*A14'*A13'* R/WN+A15*A14'*A13+A15*A14*A13 '*All)))'
PUSEL.B -PRASO,3 *(A15'*A14'*A13'*Aj1+A15*A14*A13'*A11 +Al5*Al4*A13)+PRASO,3 * PRASI,2 *(A15'*A14*A13+A15*A14'*A13')+PRASQ,3 *pFJ.S1,2 '*(A15'*A14'*A13+A15'* A14*A13')+PRASO3 *PRA$l,2 *(Aj4'*A13+A14*Aj3)+pRA3O3 '*PRASL,2 '*A14'
PCASO,3 -(PRASO3 *(D}tIRES'*Ay'+Ay*(A15'*A14'*A13'*A11+A15*A14*A13'*AjI '+AlS* A14*A13))+PRASO,3 *(DMIS'*Ay'+Ay*(A15'*Al4'*A13'*A11'*R/JN'+A15'*Aj4'*A13'* R/WN+A15*A14'*A13+A15*A14*A13'*Al1)))
PCAS3'-(PRASO,3 *(DMIPZS*Ay'+Ay*(AI5'*A14'*A13'*A1j+A15*A14*A13'*All'+A15I A14*A13)))'
17.15
Apple Computer Inc · 1982
Page 0512 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
pp - 1
PROM 341-0044 X4S
AABKI
8-ABK2
C- ABK 3
D-PAlS E-AY' F-PA8 G-ZPAGE' H-DHIRES
t-R.FSH
J-ABK4 D0-PRASO,3 Di-PRAS1 ,2 D2-PRAS4 ,5 D3-PRAS6,7
PRASO,3 _AY'*(DRIRES'+RPSH)+((ARK4*(ZPACE*PA8')')'+A3K1*ABI(2*ABI3)*Ay
PRAS1,2
ABKI*A3K2*A6K3)+AY*ABK3'*(ABKl '*ABK2*ABK4*(ZPAGE*PM' )'*pAI54ABK1*AB*(ABK4*( ZPACE*PAS')'*PAIS)')
PRAS4 5
f*Ay'9y*ABK2'*ABK3'*(ABI(j '*ABx4*(zpAGE*p'y*pA15+ABK1*(ABK4*(
ZPAGE*PA8')'*PAlS))
PRAS6,1 ABK4*(ZPACE*PA8 )'*pAjS)')
L7.16
Apple Computer Inc · 1982
Page 0513 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
acompm
PROM 341-0045 ¿J/7(,
A-CSXXN
C-C6XXN
D-IN)i'
E-ROMSEL' F-DMAI' G-FSPACE' M-PH2M t-C7XXN J- CXXX DOEN2 57 D1-EN8304
D3-RMEN
EN257.(Pt2M*R/WN*R0MSEL'*INR'*FSPACE'*(C5XXN *C6XXN*C7XXN*CXXX) )'
EN8304a(PH2M*PSPACE' *MSEL' *D4JI')'
RANEN.ROMSEL'*INH'*FSPACE'*(C5XXN *C6LCJ*C7UNAQQ'
17.17
Apple Computer Inc · 1982
Page 0514 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
''' 'pt*r mc.
PROM 341-0055
A-VA
c-vc D-VAL E-V81
F-VCJ,
C-DHIRES
11-SCR
I-WE2114'
J-VBL. DO-MUX!
D1-MUX2 02-MUX3 D3-ENHREG'
O/7. /
MUXl.((DHIRE3'+$*(VA*VAj
SCR'))'
VB! )+VB*VBL) '*(VC*VCl '+VC'*VC1))+VC*SCR)
ENREG'-DHIS'*2jL4'
17.18
Apple Computer Inc · 1982
Page 0515 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
òp1a - ,'
ASCII Conversion
-.sc:: Cov:rs1on abs
DEC .Asc:: OCTAL HZ:: BINARY 76543210
O
:tL
Ø 00000000
i SOR 001 01 00000001
2 STX 002 02 00000010
3 ETX 003 03 00000011
¿e
EOT 004 04 00000100
5 ENQ 005 05 00000101
6 ACK 006 06 00000110
7 BEL 007 07 00000111
8 ES 010 08 00001000
tr 9
HT
10
011 09 00001001 012 ØA 00001010
11 vr 013 03 00001011
12 F!
14 OC 00001100
13 CR 015 OD 00001101.
14 so 016 0E 00001110
15 SI 017 OF 00001111
16 OLE 020 10 00010000
17 DC1 021 11 00010001
18 DC2 022 12 00010010
19 DC3 023 13 00010011
20 DC4 024 14 00010100
21 NAK 025 15 00010101
22 SYN 026 16 00010110
23 ETh 027 17 00010111
26 CAN 030 18 00011000
25
1 031 19 00011001
26 SUB 032 LA 00011010
27 ESC 033 lB 00011011
28 FS Ø34 1C 00011100
29 CS 035 1D 00011101
30 RS 036 lE 00011110
31 US 037 1F 00011111
DEC ASCII OCTAL REX S tÀ.RY
763 ¿e 32 12
64 Q 100 40 01000000
65 A 101 41 01000001 66 B 102 42 01000010 67 C 103 43 01000011 68 D 104 44 01200100
69 E 105 45 01000101 70 F 106 46 01000110 71 C 107 47 01000111 72 H 110 48 01001000
73 I 111 49 01001001 74 J 112 4A 01001010
75 K 113 4B 01001011 76 L 114 4C 01001100 77 ri 115 4D 01001101
78 N 116 4E 01001110 79 0 117 4F 01001111
80 P 120 50 01010000
81 Q 121 51 01010001 82 R 122 52 01010010
83 S 123 53 01010011
84 T 124 54 01010100
85 U 125 55 01010101
86 V 126 56 01010110
87 w 127 57 01010111
88 X 130 58 01011000
89 Y 131 59 01011001
90 z 132 SA 01011010
91
( 133 53 01011011
92
134 5C 01011100
93
J
135 SD 01011101
94
136 5E 01011110
95
137 5F 01011111
17.19
Apple Computer Inc · 1982
Page 0516 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
1pcomptt,r,
DE ASCII OCTAL HEX
3
SP
33
!
"
35
i
36
S
37
33
39 '
.Ø
(
1
)
*
33 +
33
,
35 -
46 .
47 /
60 20
041 21 042 22
43 23
044 24 045 25 036 26 047 27 050 28
051 29 052 2À 053 2B 054 2C 055 2 056 2E 057 2F
43 0 060 30
49
1
061 31
50 2 062 32
51 3 063 33
52 4 064 34
53 5 065 35
54 6 066 36
55 7 067 37
56 8 070 38
57 9 071 39
58 : 072 1k
59
;
073 3E
60 < 074 3C
61 - 075 3D
62 > 076 3E
63 ? 077 3F
SARY
100000
1Ø0Ø1 00100010 00100011 00100100 00100101 00100110 00100111 00101000 00101001 00101010 00101011 00101100 00101101 00101110 00101111
00110000 00110001 00110010 00110011 00110100 00110101 00110110 00110111 00111000 00111001 00111010 00111011 00111100 00111101 00111110 00111111
DEC ASCII OCTAL HEX
96
,
9
a
98
b
99 c
10 d 11 e
102 f
103
g
104 h
105 1
106 j
107 k
108 1
109
110 n
111 o
140 60
141 61 142 62 143 63
144 64 145 65 146 66 147 67
150 68 151 69 152 6A
153 6B 154 6C 155 6D 156 6E 157 6F
112
p
160 70
113
q
161 71
114 r 162 72
115 s 163 73
116
t
164 74
117 u 165 75
118 y 166 76 119 u 167 77
120 x 170 78
121 y 171 79
122
z
172 7A
123
173 73
124
174 7C
125
175 7D
126
176 7E
127 DEL 177 7F
3APY
01100000
011000l 0110010
01100011 01100100 01100101 01100110 01100111 01101000
01101001 01101010 ØllOIØU 01101100 01101101 01101110 01101111
01110000 01110001 01110010 01110011 01110100 01110101 01110110 01110111 01111000 01111001 01111010 01111011 01111100 01111101 01111110 01111111
17.20
1
Apple Computer Inc · 1982
Page 0517 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
g
Apple I!! Computer lnlormotion
APPLE I!! PICTURES
ADDED BY DAVID T CRAIG 2006
Apple Computer Inc · 1982
Page 0518 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
g
p'aD
'II
î
Apple Computer Inc · 1982
Page 0519 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple Computer Inc · 1982
Page 0520 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
p.
¿I
I,
...-, '.í
Apple Computer Inc · 1982
Page 0521 of 0730
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Í Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple 1/! Computer Inormotion
APPLE /1/
SYSTEM DATA SHEET
ADDED BY DAVID T CRAIG 2006
Apple Computer Inc · 1982
Page 0522 of 0730
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ruApple /// Computer Information · Apple /// Level 2 Service Reference Manual
t#.__ Whas EX LIBR1S David T. Craig 67230 (USA)
Apple Computer Inc · 1982
Page 0523 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
The Apple III
The Most Powerful Personal Computer In Its Class
Too much information? Not enough time? The Apple III was created to meet the information-handling needs of decision makers at all levels, in every size and kind of company. And the Apple II! can grow with you, so as your responsibilities increase, your ability to handle them stays one step
ahead. You can use the power of your
Apple III to create financial forecasts, budgets, and reports; for accounting, resource management, and project scheduling; in electronic communications, software development, and computer-assisted training. Over 400 business programs are available today for the Apple III - plus the extensive library of CP/M® business software (with the Apple SoftCardT" III). And most Apple II Plus programs will run in the Apple Ill's "emulation" mode.
The Apple III: the personal computer for business.
Powerful features for professional needs.
The Apple Ill is ready to go as soon as you unpack it, connect a monitor, and provide power. No interface cards are required, and you don't have to open the computer. The Apple Ill already has a built-in disk drive, video outputs for color and monochromatic displays, and a numeric keypad.
Other built-in features include:
Large User Memory. The Apple Ill's 256K of internal memory means you can work with sophisticated programs and large financial and text documents, quickly and efficiently.
Color Graphics. The 16-color graphics capability of the Apple III allows you to grasp the meaning of charts and graphs quickly. If you're not using a color monitor, your information is displayed in 16 shades, so the facts still stand Out clearly.
High-Resolution Video. The Apple I/I displays 107, 520 points of information on the screen (560 horizontal x 192 vertical) in text and monochromatic graphics modes. While text is normally presented in an 80-column by 24-line monochromatic format, it can be switched to 40-column monochromatic or color-on-color.
Accessory Connectors. The most common accessories plug right into the Apple Ill. Connectors and interfacing hardware are already built in for the Apple Daisy Wheel Printer (or other serial printer), the Apple Silentype Printer, external floppy disk drives, color and monochromatic video displays (NTSC, RGB, and composite), a modem, and hand controls. The Apple Ill also has four inside expansion slots for additional accessories.
Apple III Sophisticated Operating System: it does it all for you.
Today. . . you can bring financial models into reports, insert names into form letters automatically, and turn numbers into charts, because the Apple Ill's Sophisticated Operating System (SOS) treats all your files identically. And, since applications programs written for the Apple Ill are all based on this common SOS formatting, you can combine them on a ProFil&M mass storage system and move freely from one to another. The uniformity of SOS also provides an ideal environment for software development.
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Tomorrow.. . you can expand your Apple I//elegantly. Because SOS controls all communications with accessories, you don't have to figure out how to make the computer work with a new printer, disk drive, or modem. SOS does this for you by using special files known as device drivers." Apple I/I programs come with the most commonly-used device drivers, and you can make programs compatible with new equipment by copying a driver file for the new device onto a program disk. Your software can just as easily be revised to take advantage of SOS upgrades, and of hardware enhancements to the computer itself.
Installation's easy. Learning is, too.
Because the Apple III already has a built-in disk drive and video connector, the computer is ready to work as soon as you connect a monitor and provide power. Then, Apple makes it just as easy to learn how to use it. A comprehensive Owner's Guide gets you started, and a System Demonstration disk introduces you to the computer's text editing and graphics capabilities. Reference manuals and SOS utilities disks are included for more advanced needs, and additional tutorials on the computer and its programs are also available.
Durable. Dependable. Reliable.
The Apple III is dependable, inside and out. Outside, it has a rugged diecast aluminum chassis. Inside, electronics based on advanced microprocessor circuitry assure reliable operation. The system also meets
UL and CSA standards. Every time the computer is powered
up, it performs a brief self-diagnostic routine. Should problems arise, help is close at hand, because of Apple's extensive dealer/service network. Average turnaround time on Apple I/I
servicing is less than one day.
Standard Features 256K internal memory (RAM) Built-in disk drive Custom microprocessor circuitry High-resolution color graphics
(16 colors) 80-column, 24-line text display, upper and lower case Contoured typewriter-style keyboard; 61 keys; all 128 ASCII codes; auto-repeat on all keys Numeric keypad (13 keys) Special-purpose keys: Up-Arrow, Down-Arrow, Left-Arrow, RightArrow; programmable Open-Apple and Solid-Apple; TAB; SHIFT; ALPHA LOCK; CONTROL; RETURN; ENTER; ESCAPE Quick-connect plugs for disk drives, video and audio devices, serial printers, modems, and hand controls Four expansion slots for accessory interface cards Apple I! Plus emulation mode High-quality sound generation Lockable case Self-testing diagnostics on powerup
Optional Accessories Monitor I/I or color monitor Apple Daisy Wheel Printer Apple Dot Matrix Printer Apple Silentype Printer Disk III floppy-disk drives ProFile hard-disk systems Apple SoftCard III System (for CP/M capability) Parallel Card III Serial Card III Programming languages (Business BASIC, Pascal, COBOL) Cursor I/I joysticks
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Technical Specifications
Video Display: Text and graphics may be displayed simultaneously. Graphics modes:
280 x 192, 16 colors (with some limitations);
280 x 192, monochromatic; 140 x 192, 16 colors; 560 x 192, monochromatic; All Apple//modes (in emulation) Graphics commands allow either of two screen buffers to be displayed. Text modes: 80-column, 24-line mono-
chromatic; 40-column, 24-line, 16-color
foreground and background; 40-column, 24-line mono-
chromatic. All text modes have a softwaredefinable, 128-character set (upperand lower-case), with normal or inverse display.
Central Processing Unit (CPU): The custom-designed microprocessor circuitry of the Apple Ill utilizes the 65028 as one of its major components. Other circuitry provides extended addressing capability, relocatable stack, zero page, and memory mapping. Type:
6502B. Clock Speed:
1.4 MHz average; 1.8 MHz maximum. Operations Per Second (8-bit):
Up to 750,000. Data Bus:
Two 8-bit formats, combined for extended addressing. Address Bus: 19 bits. Address Range: 262,144 bytes (256k). Registers: Accumulator (A); Index Registers (XV); Stack Pointer (S); Program Counter (PC); Environmental Register (E); Bank (B); Zero Page (Z); Processor Status (P).
U Memory: 256k dynamic RAM; 4k ROM (initialization and self-test diagnostics).
SOS (Sophisticated Operating System): Handles all system I/O; Can be configured to handle standard
or custom I/O devices and peripherals by adding or deleting "device drivers"; All languages and application programs access data through the SOS file system.
In puts and Outputs: keyboard:
61 keys on main keyboard; 13 keys on numeric keypad; Full 128-character, ASCII
encoded; All keys have automatic repeat; Four directional-arrow keys with
two-speed repeat; Two user-definable Apple keys; Seven other special keys: SHIFT,
CONTROL, ALPHA LOCK, TAB, ESCAPE, RETURN, ENTER. Storage Devices: One 5.25-inch floppy disk drive built in, 140K (143,360) bytes per diskette; Three additional drives can be connected by daisy-chain cable (Total: 560k bytes on-line storage); Up to four ProFile hard-disk drives (5 megabytes each) may be added with plug-in interface cards. Video Output: RCA phono connector for NTSC monochromatic composite video; DB-15 connector for: NTSC color composite video; NTSC monochromatic composite
video; RGB color video; Composite sync signal; Power supply voltages. Color signals appear as 16-level grey scale on monochromatic displays. Audio Output: Built-in two-inch speaker; miniature phono jack on back panel; Driven by 6-bit D/A converter or fixed-frequency "beep" generator. Serial (Printer/Modem) Port: RS-232C compatible, DB-25 female connector; Software-selectable baud rate and duplex mode. One port may be used for the Silentype printer.
One port may be used for the Silentype printer. Expansion:
Four 50-pin expansion slots (fully buffered, with interrupt and DMA priority structure).
Joystick/Silentype Ports: Two DB-9 connectors.
Languages Available: Apple Business BASIC, Apple Ill Pascal, Apple Ill COBOL.
Emulation Mode: Provides hardware emulation of 48k byte Apple Il Plus. Allows most Apple li programs, with the exception of Pascal and FORTRAN, to run without modification.
Electrical Specifications: The Apple 1/rs power cord should be plugged into a three-wire 110-120 volt outlet.
Physical Specifications: Height: 4.8 inches (12.20 cm) Depth: 18.2 inches (46.22 cm) Width: 17.5 inches (44.45 cm) Weight: 26 lbs. (11.8 kg) The Apple Ill meets the following agency regulations: UL 114 Office Appliances and Business Equipment. CSA 22.2, No. 154Data Processing Equipment.
The Apple Ill Personal Computer System Package U.S. Order Number A3S0256 With your order for an Apple Ill System you will receive: 256K Apple Ill; Power cord; Monitor cable; System Demonstration disk; System Utilities disk; System Utilities Data disk (contains
device driverfiles, character sets, and keyboard layouts); Apple li Plus Emulation disk; Owner's Guide; Standard Device Drivers Manual; Warranty and service information.
Specifications or products may change without notice. Apple, the Apple logo, ProFile, and Sileritype are trademarks of Apple Computer, Inc. SoftCard is a trademark of MicroSoft corporation. CP/M isa trademark of Digital Research, Inc.
nAPPLE COMPUTER, INC.
'A
ppla computar
20525 Mariani Avenue Cupertino, California 95014
(408) 996-1010 TLX 171-576
A3F5147 300K 7/83
PRINTED IN U.S.A
Apple Computer Inc · 1982
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i Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple I/I Computer I&ormotion
APPLE I/I
SYSTEM DIAGRAM
Apple Computer Inc · 1982
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Iuu_I
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111E
Apple Computer Inc · 1982
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i Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple /1/ Computer Inlormotion
DESIGN PflIENI
Potent # 268,584 -- Apple /11 Computer
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Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
United States Patent [19]
Jobs et al.
[Il] Des. 268,584
[451
Apr. 12, 1983
[54] PERSONAL COMPUTER
[75] Inventors: Steven P. Jobs, Los Gatos; Jerrold C. Minock, Palo Alto; Dean A. Hovey,
Los Altos; David M. Kelley, Palo Alto, all of Calif
[73] Assignee: Apple Computer, Inc.. Cupertino, Calif.
Term:
14 Years
AppI. No.: 203,502
Fikd:
Nov. 3, 1980
mt. CI.
D14-02
U.S. Cl.
1)14/106
Field of Search
D14/l00, lOI, 102, 103,
D14/105. 106,107,111,113, 114; 3U/4l9, 708,
709, 900; 340/365 R; D18/7
References Cited
U.S. PATENT DOCUMENTS
D. 218,933 10/1970 Cook D. 229,945 1/1974 Santulli D. 252,086 6/1979 Calverly
D14/106 D14/106 D14/106
Primary ExaminerSusan J. Lucas
Attorney, Agent, or FirmBlake! y, Sokoloff, Taylor &
Zafman
CLAIM
The ornamental design for a personal computer, sub. stantially as shown.
DESCRIPTiON
FIG. I is a perspective view of the personal computer
showing our new design; FIG. 2 is a top view thereof; FIG. 3 is a front elevational vsew thereof; FIG. 4 is a right side view thereof; FIG. 5 is a left side view thereof; FIG. 6 is a rear elevational view thereof; and. FIG. 7 is a bottom view thereof.
i
Apple I/I Conputer
Apple Computer Inc · 1982
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U.S. Patent Apr. 12, 1983 Sheet i of 3 Des. 268,584
iii. .l*u*IIauuuUUURUUflRII*P
Jjz2
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
U.S. Patent Apr. 12, 1983 Sheet 2 of 3 Des. 268,584
Jz3
Apple Computer Inc · 1982
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U.S. Patent Apr. 12, 1983 Sheet 3 of 3 Des. 268,584
a Co o
DD oo
1J1H =1
nl- Tr
¡r
I
I
li
i
ri
1ilhllllhItli
J97
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple I/I Computer lnormation
DESIGN PATENT
Patent # 273,191 -- Monitor 1/I
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Apple Computer Inc · 1982
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United States Patent [19]
Oyama et al.
[ii] Des. 273,191
[45] Mar. 27, 1984
[54] COMPUTER DATA DISPLAY MONITOR
[75] Inventors: Terrell A. Oyama, San Jose; Loren D. Stirling, Pleasanton, both of Calif.
[73] Assignee: Apple Computer, Inc., Cupertino, Calif.
[**] Term:
14 Years
[21] Appi. No.: 321,235
[221 Filed:
Nov. 13, 1981
[52)
[58) Field of Search
3./365 R,
D14/!13 D14/l00-117; 711, 720, 7
[56]
References Cited
U.S. PATENT DOCUMENTS
D. 250,020 10/1978 Pycha
D14/113
OTHER PUBLICATIONS
Computer Design, 2/80, p. 17, Hitachi. Ltd., Color Monitor.
Primary ExaminerSusan J. Lucas Attorney, Agen4 or FirmBlakely, Sokolofl Taylor &
Zafman
[57]
CLAIM
The ornamental design for a computer data display monitor, substantially as shown and described.
DESCRIPTION
FIG. 1 is a perspective view of a computer data display monitor showing our new design; FIG. 2 is a front view thereof; FIG. 3 is a top view thereof; FIG. 4 is a right side view thereof; FIG. 5 is a rear view thereof; and, FIG. 6 is a bottom view thereof.
3
\Açkor III
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
U.S. Patent Mar. 27, 1984 Sheet 1 of 2 Des. 273,191
Jq2
,'
JL -
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
U.S. Patent Mar. 27, 1984 Sheet 2 of 2 Des. 273,191
liii 111111 D
00000fJ0000011 L
00 00 0000 00 0. DOC 0000 tI CII 0.
Li
\ J6
D
flflfflIll
iliflEllifhElfiD
ElElElIIIIElElD
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U
Apple Computer Inc · 1982
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i Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple I!! Computer lnormotion
DESIGN PATENT
Potent # 273,295 -- ProFile Hard Drive
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Apple Computer Inc · 1982
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United States Patent (19]
Stewart
(Il] Des. 273,295
, (43]
Apr. 3, 1984
(34] HARD DISK DRIVE
(73] Inventor: James L Stewart, San bee, Calif.
(73) Assignee: Apple Computer, Inc., Cupertino, Calif.
(SS] Term:
14 Years
AppI. No.: 322,922
Filed:
No,. 19, 1981
(52] U.S. a.
(58] FIeld ot$.seth
D14/109 D14/I0ß-116;
D13/41; 361/380, 390, 394; 360/97, 98, 133;
364/900
[56]
Reteresc.s ted
U.S. PATENT DOCUMENTS
3,789,273 1/1974 O'Brien 3,899,794 8/1975 Brown, Jr.
360/97 X D14/109 X
OTHER PUBLICATIONS
North Star Computen, Inc., Catalog, 5-1980, p.8, Hard Disk Drive.
Radio Shack TRS-80 m Microcomputer Catalog
RSC-3, ©1979, p. 10, VOXBOX rt.s Housing.
Primari &amiae,Susan J. Lucas Attors,y Agea& or flmsBlakely, Sokoloff, Taylor &
Zafman
[57]
CLAIM
The ornamental design for a hard disk drive, substan.. daily as shown and described.
DESCRIPTION
FIG. i Is a perspective view of the hard disk drive showing my new design; PIO, 2 Is a top view thereof: F10,3 Is a front view thereof; FIG, 4 is a rear view thereof; FIG. 3 Is a right side view thereof; and FIG. 6 Is a left side view thereof.
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Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
U.S. Patent Apr. 3, 1984 Sheet i of 2 Des. 273,295
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11111111 liii I 11111 II
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Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
U.S. Patent Apr. 3, 1984 Sheet 2 of 2 Des. 273,295
I IIItIIIIIIIIIIIII -
111111111111111111111111111111 -
J5i6
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
g
Apple I/I Computer lnlormotion
APPLE I/I PATENT
Patent#4,383,296 -- 10 May 1983
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Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
United States Patent [19]
Sander
estivf,h1 C"py
[11)
4,383,296
[45] May 10, 1983
[54) COMPUTER WITH A MEMORY SYSTEM
FOR REMAPPING A MEMORY HAVING TWO MEMORY OUTPUT BUSES FOR HIGH RESOLUTION DISPLAY WITH SCROLLING OF THE DISPLAYED CHARACTERS
[75] Inventor: Wendell B. Sander, San Jose, Calif.
[73] Assignee: Apple Computer, Inc., Cupertino, Calif.
AppI. No.: 150,630
Filed:
May 16, 1980
Int. Cl?
GO6F 13/06; GO6F 3/14
U.S. CL
364/21» 340/726;
340/799
[58) Field of Search ... 364/200 MS File, 900 MS File;
340/726, 798, 799; 358/17
[56]
References Cited
U.S. PATENT DOCUMENTS
3,821,730 3,893,075 3,903,510 3,980,992 4,136,359 4,150,364
6/1974 Carey et al. 7/1975 Orban et al.
9/1975 Zobel 9/1976 Levy et al, 1/1979 Wozniak
4/1979 Baltzer
340/799 X 340/799 X 340/726 X
364/200 358/17
364/900 X
FOREIGN PATENT DOCUMENTS
1351590 5/1974 United Kingdom 1482819 8/1977 United Kingdom 1496563 12/1977 United Kingdom 1524873 9/1978 United Kingdom
Primary E.xaminerRaulfe B. Zache Attorney, Agent, or FirmBlakely, SokolofT, Taylor & Zafman
[57]
ABSTRACT
A microcomputer system with video display capability, particularly suited for small business applications and home use is described. The CPU performance is en-
hanced by permitting zero page data to be stored throughout the memory. The circuitry permitting this capability also provides a pointer for improved direct memory access. Through unique circuitry resembling "bank switching" improved memory mapping is obtained. Four-bit digital signals are converted to an AC chroma signal and a separate luminance signal for display modes. Display modes include high resolution
modes, one of which displays 80 characters per line.
22 ClaIms, 9 Drawing FIgures
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Apple Computer Inc · 1982
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Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
U.S. Patent May 10, 1983
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Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
U.S. Patent May 10, 1983
Sheet 3 of 8
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Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
U.S. Patent May 10, 1983
Sheet 4 of 8
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Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple Computer Inc · 1982
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Apple Computer Inc · 1982
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U.S. Patent May 10, 1983
Sheet 8 of 8
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Apple Computer Inc · 1982
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4,383,296
2
8-bit data bus and yet provide high data rates (16-
COMPUTER WITH A MEMORY SYSTEM FOR bits/MHz) needed for high resolution displays. A first
REMAPPING A MEMORY HAVING TWO
plurality of memory devices are connected to a first
MEMORY OUTPUT BUSES FOR HIGH
memory output bus; these memory devices are also
RESOLUTION DISPLAY WITH SCROLLING OF 5 connected to the data bus. The memory includes a sec-
THE DISPLAYED CHARACTERS
ond plurality of memory devices which are also con-
BACKGROUND OF THE INVENTION
nected to the data bus; however, the outputs of these second devices are coupled to a second output memory
The invention relates to the field of digital computers, bus. First switching means permit the first and second
particularly microcomputers, having video display ca- 10 memory buses to be connected to the display for high
pabilities.
data rate transfers. Second switching means permit
Prior Art
either one of the memory buses to be connected to the data bus during non-display modes.
In the last few years, there has been rapid growth in
The addressing capability of the memory is greatly
the use of digital computers in homes by hobbyists, for enhanced not only through bank switching, but through
small business and for routine engineering and scientific a novel remapping which does not require the CPU
application. For the most part, these needs have been control associated with bank switching. In effect, the
met with self-contained, relatively inexpensive mi- "unused" bits from one of the first and second memory
crocomputers or microprocessors with essential periph- buses are used for remapping purposes. This mode of
erals, including disc drives and with relatively easy to 20 operation is particularly useful for providing toggling
manage computer programs The design for computers between two separate portions of the memory.
for these needs requires considerable ingenuity since
The display subsystem of the described computer
each computer must meet a wide range of applications generates video color signal in a unique manner. A 4-bit
and because this market is particularly cost conscious. color code as used in the prior art, is also used with the
A home or small business computer must, for exam- 25 described display subsystem. However, this code is used
ple, operate with a number of different program lan- to generate an AC chrominance signal and a separate
guages, including those requiring relatively large mem- DC luminance signal. This provides enhanced color
ories, such as Pascal. The computer should interface with a standard raster scanned display and provide a
capability over similar prior art color displays.
wide range of display capabilities, such as high density 30 BRIEF DESCRIPTION OF THE DRAWINGS
alpha-numeric character displays needed for word pro-
cessing in addition to high resolution graphics displays. To meet these specialize computer needs, generally
requires that a relatively inexpensive microprocessor be used and that the capability of the processor be en- 35 hanced through circuit techniques. This reduces the overall cost of the computer by reducing, for example, power needs, bus structures, etc. Another important consideration is that the new computers be capable of
FIG. i is a block diagram showing the major components and subsystems of the invented and described
microcomputer system. FIGS. 2 and 3 together show the central processing
unit (CPU) and the architecture associated with this CPU, particularly the address bus and data bus.
FIG. 2 is a circuit diagram primarily showing the address bus and the logic means associated with this
using programs developed for earlier models. As will be seen, the presently described microcom-
40
bus.
FIG. 3 is a circuit diagram primarily showing the
puter is ideally suited for home and small business appli- data bus and its interconnection with the memory buses
cations. It provides a wide range of capabilities includ- (A bus and B bus), bootstrap read-only memory, and
ing advanced display capabilities not found in compara- input/output ports.
ble prior art computers.
45 FIGS. 4, 5 and 6 show the memory subsystem.
The closest prior art computer known to applicant is
FIG. 4 is a circuit diagram primarily showing the
commercially available under the trademark, Apple-II. circuitry for selecting between address signals from the
Portions of that computer are described in U.S. Pat. No. address bus and display counter signals.
4,136,359.
FIG. 5 is a circuit diagram primarily showing the
50 generation of various "select" signals for the memory
SUMMARY OF THE INVENTION
devices.
A digital computer which includes a central process-
HG. 6 is a circuit diagram showing the organization
ing unit (CPU) and a random-access memory (RAM) of the random-across memory and its interconnection
with interconnecting address bus and data bus is de- with the data bus and memory output buses.
scribed. One aspect of the present invention involves 55 FIGS. 7 and 8 illustrate the display subsystem of the
the increased capability of the CPU by allowing base page or zero page data to be stored throughout the memory. Alternate stack locations and an improved direct memory access capability are also provided by
invented computer. FIG. 7 is a circuit diagram showing the circuitry for
generating the digital signals used for the video display. FIG. 8 is a circuit diagram of the circuitry used to
the same circuitry. Detection means are used for detect- 60 convert the digital signals to analog video signals.
ing a predetermined address range such as the zero
FIG. 9 is a graph of several waveforms used to de-
page. This detection means causes a special register scribe a prior art circuit and the circuit of FIG. 8.
(Z-register) to be coupled into the address bus. The contents of this Z-register provide, for example, a
pointer during direct memory access, or alternate stack 65
DETAILED DESCRIPTION OF THE INVENTION
locations for storing data normally stored on page one.
A microcomputer system capable of driving a raster
The memory of the invented computer is organized scanned video display is disclosed. In the following
in an unusual manner to provide compatibility with the description, numerous specific details such as specific
Apple Computer Inc · 1982
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3
4
part numbers, clock rates, etc, are set forth to provide a16-bit address bus is shown in FIG. 3 with its intercon-
thorough understanding of the present invention. How-nections to the remainder of the computer. The pin
ever, it will be obvious to one skilled in the art that the number for each interconnection is shown adjacent to
inventive concepts described in this patent may be prac- the corresponding line. In many cases, the nomencla-
ticed without these specific details. In other instances, 5 ture associated with the 6502A (CPU 65) is used in this
well-known circuits have been shown in block diagram application. For example, pin 6 receives the nonmaska-
forni in order not to obscure the present invention in bIc interrupt signal (NMI), and pin4is coupled to re-
unnecessary detail.
ceive the interrupt request signal (IRQ). Some of the
Referring first to FIG. 1, in general the described signals employed with the CPU 65, which are well-
computer includes a central processing unit (CPU) 65, 10 known in the art, and which are not necessary for the
its associated data bus 42, address bus 46, a memory understanding of the present invention are not de-
subsystem and a display subsystem 58.
scribed in detail in this application, such as the various
The address bus 46 from the CPU is coupled to the synchronization signals and clocking signals. The ad-
memory subsystem to permit the selection of locations dress signals from the CPU 65 are identified as AO-A7
in memory. Some of the address signals pass through a 15 and A5-Ais. The data signals associated with the CPU
multiplexer 47. For some modes of operation, signals 65 are shown as DO-D7. As will be apparent to one
from a register 52 are coupled through the multiplexer skilled in the art, the inventive concepts described in
47 onto the bus 46. The register 52 is identified as the this application may be employed with other micro-
Z-register and is coupled to the multiplexer 47 by the Z processors.
bus. The general description of the multiplexer 47 and 20 Referring now to FIGS. 2 and 3, the general architec-
its control by the logic circuit 41 are described in detail ture, particularly the architecture associated with the
in conjunction with FIG. 2. In general, the circuitry CPU 65 can best be seen. The address signals AQ-A7 are
shown to the left of the dotted line 53 is included in coupled to a buffer 103 by the bus shown primarily in
FIG. 2 while the CPU 65, memory 50, data bus 42 and FIG. 2. These address signals are also coupled to the
multiplexer 43 are shown in detail in FIG. 3.
25 ROM 50. The signals Ao-A7 after passing through the
The address bus Nl is coupled to the read-only mem- buffer 103 are coupled to the memory subsystem The
ory 50. The output of this memory is coupled to the address signals A5-Ai5 (higher order address bits) are
computer's data bus 42. The read-only memory (ROM) coupled through lines shown in FIG. 2 to the multiplex-
50, as will be described, stores test routines, and other ers 47a and 47b. The contents of the Z-register 52 of
data of a general bootstrap nature for system initializa- 30 FIG. lis also connected to the multiplexers 47a and 47b
tion.
through the Z-bus (Z i-Z7). The multiplexers 47a and
The data bus 42 couples data to the random-access 47b allow the selection of either the signals
memory (RAM) 60 and to and from I/O ports. This bus from the CPU 65 or the contents of the Z-register
also couples data to the Z-register 52 and other com- (Zi-Z7) for addressing the RAM 60. The output of
monly used registers not illustrated. The data bus 42 35 these multiplexers are shown as A5-A15; this designa-
receives data from the RAM 60 through the A bus and tion is used even when the Z-bus is selected. Note in the
B bus which are selected by multiplexer 43. The periph- case of the Zo signal, this signal is coupled to the multi-
eral Bus N2 is used, as is better illustrated in FIG. 3, for plexer 47a through the exclusive OR gate 90 for reasons
coupling to peripherals.
which are explained later. The address signals As-Ai i
The memory subsystem is shown in detail in FIGS. 4, 40 are also coupled to the ROM 50, thus the signals
5 and 6. The address control means which receives Ao-Aii are used for addressing the ROM 50. The sig-
addresses on bus 46, makes the final selection of mem- nals As-Ais are connected to the logic circuit shown in
ory locations within the RAM 60. Bank switching, the lower left-hand corner of FIG. 2; this logic circuit
addressing for display purposes, scrolling and other corresponds to the logic circuit 41 of FIG. I.
memory mapping is controlled by the address control 45 The input and output data signals from the CPu 65
means 59 as will be described in greater detail in con- are coupled by a bidirectional bus to the bidirectional
junction with FIGS. 4 and 5. The PAM 60 is shown in buffer 99 (FIG. 3). This buffer is selectively disabled by
detail in FIG. 6. The counter 58 which is sychronized gate 100 to allow the output of ROM 50 to be communi-
with the horizontal and vertical display signals, pro- cated to CPU 65 and during other times not pertinent to
vides signals both to the address control means 59 and 50 the present discussion. The direction of flow through
to the display subsystem 48.
the buffer 99 is controlled by a read/write signal cou-
The display subsystem receives data from the RAM pled to the buffer through inverter 101. Data from the
60 on the A bus and B bus and converts these digital CPU 65 is coupled through the buffer 99 and bus 42 to
signals to video signals which control a standard raster the RAM 60 or to I/O ports. Data from the RAM 60 is
scanned display. A standard NTSC color signal is gen- 55 communicated to CPU 65 or bus N2 from the A bus and
crated on line 197 and a black and white video signal on B bus through the buffer 99. The 4 lines of the A bus and
line 198. The same signals used to generate these video 4 lines of the B bus are coupled to the multiplexer 43a.
signals can be used to generate separate red, green, blue Similarly, the other 4 lines of the A and B buses are
(ROB) video signals. The display subsystem 48 receives coupled to the multiplexer 43b. Multiplexers 43a and
numerous timing signals including the standard color 60 43b select the 8 lines of the A bus or B bus and commu-
reference signal shown as 3.5 MHz (C3.5M). This sub- nicate the data through to buffer 99 and bus 42. These
system is described in detail in FIGS. 7 and 8.
multiplexers are selectively disabled (for example, dur-
COMPUTER ARCHITECTURE
ing writing) by gate 102. As will be described later, the 16 lines of the A bus and B bus permits the reading of
In the presently preferred embodiment, the CPU 65 65 16-bits from the RAM at one time. This provides a data
(microprocessor) employed with the described com- rate of 16-bits/MHz which is necessary, for example,
puter is a commercially available component, the for an 80 character per line display. The data is loaded
6502A. This 8-bit processor (8-bit data bus) which has a into the RAM 60, 8-bits at a time.
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The ROM 50, as mentioned, stores test programs,
Next assume that page one has been selected by the
data needed to initialize various registers, character CPU and that the ALT STK signal is low, indicating
generation data (for RAM 162 of FIG. 7) and other the alternate stack locations are to be selected. (A flag is
related data. Specific programs employed in the pres- set by the CPU to change the ALT STK signal). Since
ently preferred embodiment of the computer are set 5 the ALT STK signal is low and Ag is high, a high outforth in Table I. The ROM 50 is selected by control put occurs from the gate 81. All the inputs to gates 83
signals coupled to its pins 18 and 20, identified as signals and 84 are low, therefore, high outputs occur from both
ROM SEL and T ROM SEL. Any one of a plurality of these gates. The conditions of gate 87 are met, causing
commercially available read-only memories may be a high output from this gate and lowering the output
used for the ROM 50. In the presently preferred em- 10 from the gate 89. The Z-bus is thus selected by the
bodiment, commercially available Part No. SY2333 is multiplexers 47a and 47b. This allows the contents of
used.
the Z-register to be used as alternate locations. Non-
Referring now to this logic circuit (lower left-hand zero page locations are assured by inverting Ag. The
corner of FIG. 2), the NAND gate 81 receives the exclusive OR gate 90 acts as a selective inverter. If Ag
address signal Ag and also the alternate stack signal identified as ALT STK. The output of this gate pro-
15
is high and Zo is low, then Ag at the output of the multi-
plexer 47a will be low. Note that during zero page
vides one input to the AND gate 87. The Ag signal is also coupled through the inverter 82 to one input terminal of the NAND gates 85 and 86. The address signals A9 and A10 are coupled to the input terminals of the 20 NOR gate 83. The output of this gate is coupled to one input terminal of the NAND gates 85 and 86 and the
AND gate 87. The address signals Ail-A 15 are coupled to the input terminals of the NOR gate 84. The signal Ai1 is also coupled to an input terminal of the NAND 25
selection when Ag is low, the Zo signal is directly communicated through gate 90 to the output of multiplexer
47a.
Thus, the logic circuits along with the ALT STK signal allows alternate stack locations to be selected through the Z-bus. This further enhances the performance of the CPU which would otherwise be limited to page one for stack locations.
The logic circuit of FIG. 2 is also used along with the Z-register to provide a pointer during direct memory
gate 85.
access (DMA). Assume that direct access to the com-
The outputs of the AND gates 87 and 88 (through puter's memory is required by a peripheral apparatus.
NOR gate 89), controls the multiplexers 47a and 47b. To initiate the DMA mode the CPU provides an ad-
When the output of gate 89 is low the Z-bus is selected, otherwise the address signals from the CPU 65 are se-
30
dress between F800 and R8FF. Through a logic circuit not illustrated in FIGS. 2 and 3, the ROM SEL signal is
lected.
brought low for addresses between F000 and FFFF.
The logic circuit above-described, along with the This signal is communicated to gate 93 and causes the
Z-bus and Z-register provide enhanced performance for output of gate 92 to rise (DMA 1 is high at this time).
the computer. First, this circuit permits the zero page or 35 This rise in potential is communicated to one input of base page data to be stored throughout the RAM 60 the gate 85. Additionally, gate 85 senses that the address
rather than just on zero page. Secondly, this circuit bits Ag, Ag and A10 are low. This information is coupled
enables addressing of alternate stack locations (other to gate 85 through the inverter 82 and the NOR gate 83
than page one). Lastly, this circuit through the Z-regis- as high signals. Also the fact that A11 is high is directly
ter provides a RAM pointer for direct memory access 40 communicated to gate 85. Thus, with the address be-
(DMA).
tween F800 and F8FF the DMA OK signal drops in
Assume for purposes of discussion that the CPU 65 is potential. This is sensed by the peripheral apparatus
addressing the zero page of memory. That is, the higher which in turn causes the DMA I signal to drop and
order address bits Ag-A15 are all zeros. The zeros for provides a ready signal to the CPU 65. With the com-
A9-A15 are detected by the gates 83 and 84. If all the 45 pletion of this handshake, data may begin to be trans-
inputs to these gates are zeros, the outputs of these gates ferred to the RAM.
are high which condition is communicated to the gate
The DMA I signal through gate 93 and inverter 93
87. Ag which is also low, insures that the output of gate forces the T ROM SEL signal low. This signal in addi-
81 will be high. Thus, all the inputs to gate 87 are high, tion to being communicated to the ROM 50, is coupled
causing the signal at the output of the gate 89 to drop. 50 to the buffer 99 through gate 100, disabling this buffer
When this occurs, the Z-bus is selected. Instead of all (during the reading of ROM 50). Also, the ready signal
the binary zeros from the CPU being coupled to the causes the CPU to come to a hard stop. Importantly, the
main memory (RAM 60), the contents of the Z-register DMA 1 signal, after passing through the inverter 94 and
form part of the address for the memory. Therefore, the gates 88 and 89, assures the selection of the Z-regis-
even though the CPU 65 has selected the zero page, 55 ter. The contents of the Z-register are fixed and provide
nonethelessdata may be written into or from any loca- a pointer to a page in the RAM.
tion of RAM 60 (including the zero page). This en-
Under the above conditions, the CPU increments the
hances the performance of the CPU, since for example, lower 8-bits of the address signal. The ROM 50 fur-
the time consumed in shifting data to and from a single nishes the instructions for incrementing the address,
zero page is minimized.
60 specifically SBC #1 and BEQ. The peripheral appara-
Normally, the CPU 65 selects page one for stack tus provides the data or receives the data in synchroni-
locations. This occurs when Ag is high and Ag-Ai are zation with the CPU operation. The peripheral also
low. Assume first that the alternate stack locations have furnishes a read/write signal to indicate which opera-
not been selected. Both inputs to gate 81 are high and its tion is to occur. Data is then written into RAM via bus
output is low. The low input to the gate 87 prevents the 65 N2 and bus 42, or read from RAM via the A and B buses
selection of the Z-bus. Thus, for these conditions the and bus N2.
address signals A0-A7 select stack locations on page
Importantly, with the above DMA arrangement,
one.
addresses from the peripheral apparatus are not neces-
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sary and the Z-register is used to provide a pointer to a lower right-hand corner of FIG. 6, the various signals
page in RAM 60.
applied to each device (including the address signals),
MEMORY SUBSYSTEM
along with the corresponding pin numbers are shown. Other circuitry not illustrated is the refresh control
The memory sybsystem shown in FIG. i as the ad- 5 circuitry which operates in a well-known manner in
dress control means 59 and RAM 60 is illustrated in conjunction with the CÄ, RAS and address signals to
detail in FIGS. 4, 5 and 6 as mentioned. In FIGS. 4 and refresh the dynamic devices.
5, the memory control means is shown, while in FIG. 6
Each row of memory devices 106 receives a unique
the memory devices and their organization are illus- combination of CAS and RAS signals. For example,
trated. The address control means of FIGS. 4 and 5 lo row iii receives CAS 5, 7 and RAS 4, 5; similarly, row
receives the address signals from the CPU 65 (Ao-A 15), 112 receives CAS O and
0, 3. The generation of
the count in the vertical and horizontal counters these CA and RAS signals is described in conjunction
(counter 58 of FIG. 1) which are used during display with FIG. 5. These signals (along with the 14-bit ad-
modes, control signals from the CPU and other signals. dress signals) permit the selection of a single 8-bit loca-
In genreal, this control means develops the address I 5 tion in the 96K byte memory (for writing) and also the
signals which are coupled to the RAM of FIG. 6 includ- selection (for reading) of I 6-bit locations.
ing the column address and row address signals, com-
The memory of FIG. 6 may be expanded to a 128K
monly referred to as CAS and RAS. Other related func- byte memory by using 32K memory devices, such as
tions are also shown in FIGS. 4 and 5, such as the cir- Part No. 4132. In this case, four rows of eight, 32K
cuitry which provides display scrolling, indirect RAM 20 memory devices are used with each row receiving two
addressing and memory mapping.
CAS and RÄS signals.
The CPU of FIG. 3 provides a 16-bit address for
Before reviewing FIG. 4, a general understanding of
addressing the memory. Under ordinary circumstances the organization of the display is helpful. The display, this address limits the memory capacity to 64K bytes. during certain modes, is organized into 80 horizontal
This size memory is insufficient in many applications, as 25 segments and 24 vertical segments for a total of 1920 for example, to effectively use the Pascal program lan- blocks. 11-bits of the counter 58 of FIG. i are used as
guage. As will be described in greater detail, the address part of the address signals for the memory to access data
control means of FIGS. 4 and 5 enable the use of a for displaying during these modes. These counter sig-
memory having a 96K byte or 128K byte capacity. One nals are shown in FIG. 4 as Ho-H5 and V0-V4. During
well-known technique which is used with the present 30 other display modes each horizontal segment is further invention for increasing this capacity is bank switching; divided into 8 segments (e.g. for displaying 80 alpha
this--s-w--it-c-h--in--g-o-ccurs under the contol of the CPU. In
addition, the address control means uses a unique indi-
numeric characters per line). This requires 3 additional vertical timing signals shown as VA, VB and V in
rect addressing mode which provides the benefits of FIGS. 4 and 7.
bank switching, however, this mode does not require 35 Often in the prior art, two separate counters are used CPU control. This greately enhances CPU operation to supply the timing/address signals for accessing a
with the larger memory (as will be described) when memory when the data in the memory is displayed. The
compared to the CPU controlled bank switching.
count in one counter represents the horizontal lines of
Referring first to FIG. 6, the RAM configuration is the screen (vertical count) and the other the position
illustrated for a capacity of 96K bytes. The memory is 40 along each line, (horizontal or dotcount). In many prior
organized into six rows, each of which includes eight art displays the most significant bit of the dot counter is 16K memory devices such as rows 111 and 112. In the used to increment the line counter. Data in memory
presently preferred embodiment, Part No. 4116 MOS intended for display is mapped with a one-to-one corre-
dynamic RAMs are used. (The pin designations and lation to the counts in these counters. In another prior signal designations refer to this memory device.) Obvi- 45 art system (implemented in the Apple-II computer sold
ously, other memory devices may be employed, Input data to these memory devices 106 is provided
from the bus 42. Each line in the bus 42 is connected to
by Apple Computer, Inc.) this one-to-one correlation is not used. Rather, to conserve on circuitry, a single
counter is employed and a more dispersed mapping is
the data input terminal of one device 106 in each row. used in the memory. (Note that where a maximum honThe interconnection of this bus with each of the mcm- 50 zontal count of 80 is used, this number cannot be repre-
ory devices is not shown in FIG. 6 in order to overcom- sented by all ones in a digital counter and thus the vertiplicate this drawing. By way of example, however, line cal counter cannot easily be incremented by the most 107 connects the data bit D7 to the data input terminal significant bit in the horizontal counter.) Since this of one of the memory devices in each of the six rows. more dispersed mapping technique is part of the prior
Three rows of devices 106 have their output termi- 55 art and not critical to an understanding of the present
nais coupled to the A bus, and three rows are similarly invention, it shall not be described in detail. However, coupled to the B bus. By way of example, line 108 con- the manner in which it is implemented shall be discussed nects three output terminals of devices 106 to the DB7 in conjunction with the adder 114 of FIG. 4. For purline of the B bus while line 109 connects three output poses of discussion, the signals from the counter 58 of terminals of the devices 106 to the DA7 line of the A 60 FIG. i are designated as either vertical (V) or horizon-
bus.
The described memory devices 106 are each orga-
tal (H). Referring now to FIG. 4, the selection of either the
nized as a I6KX1 memory. Thus, each device receives counter signals on the address signais from the CPU is
a 14-bit address 7-bit addresses.
which is time multiplexed into two, This multiplexing occurs under the
65
made
these
by the multiplexers 116, 117, 118 and 119. Each of commercially available multiplexers (Part No.
control of the CAS and RAS signals as is well-known. The lines coupling the address signals to each of the
devices in FIG. 6 are not illustrated. However, in the
153) couples one of four input lines to an output line. There are eight inputs to multiplexers 116, 117 and 118 and the outputs of these multiplexers provide the ad-
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lo
dress signals for the memories (ARO through ARS). The development of the Ci and C3 signals is illustrated in
multiplexer 119 has four inputs on its pins 3, 4, 5, 6 and FIG. 5.) The gates 124, 125 and 126 provide mapping
provides a single output on pin 7, the AR6 address compensation within the memory. As the computer and
signal. (The signals supplied to pins 11, 12 and 13 of memory are presently implemented, the sequence in
multiplexer 119 are for clamping purposes only.)
5 which the various portions of the display are generated
The AX signal is applied to the pm 14 of each of the is not the same as the sequence in which the data is
multiplexers. The signal on this line and the signal ap- removed from memory for display. These gates provide
plied to pin 2, determines which of the four inputs is compensating addresses and, in effect, cause a remap-
coupled to each of the outputs of the multiplexers. The ping so that the proper sequence is maintained when
AX signal is a RAM timing signal for clocking the first 10 data is read from the memory for the display. These
7 bits and second 7 bits of the multiplexed 14-bit address gates are shown to provide a complete disclosure of the
applied to each of the memory devices 106. The other presently preferred embodiment, however, they are not
control signal to the multiplexers is developed through critical to the present invention.
the AND gate 123. The inputs to this gate are the dis-
In operation, the circuitry of FIG. 4, as mentioned,
play signal (DSPLY) which indicates that the computer 15 selects the address signals which are applied to each of
is in a display mode and a clocking signal, specifically a the memory devices, either from the CPU or counter if
1MHz timing signal (dM). The output of the AND the display mode is selected. It should be noted that not
gate 123 determines whether the address signals from all of the address bits from the CPU are coupled to the
the CPU or the signals associated with the counter 58 of multiplexers 116 through 119. Some of these address
FIG. 1 are selected.
20 bits, as will be described in conjunction with FIG. 5, are
Assume for purposes of discussion that the display used to develop the various CAS and RAS signals and
has not been selected, and thus, the output of gate 123 is thus select different rows within the memory of FIG. 6.
low. The AX signal then selects for pin 7 of multiplexer
The scrolling operation which is used is somewhat
116 first the address signal Ao and then A6. Likewise, unusual in that each line of the display is separately
each of the multiplexers selects an address signal (ex- 25 moved up (line-by-line) with one line of data in memory
cept for those associated with exclusive OR gates 124 being moved for each frame. This technique provides a
and 125 which shall be discussed). If the display signal uniform, esthetically pleasing, scroll. Scrolling the
is high and an output is present from the gate 123, then, screen one line per frame can be achieved by moving all
by way of example, the AX signal first causes the Hi the data in the memory into a new position for each
signal and then the V1 signal to be connected to the 30 frame. This would be very time consuming and imprac-
ARi address line. Similarly, signals corresponding to tical. With the described technique, only one-eighth of
the vertical and horizontal count are coupled to the the data in the memory is moved for each new frame.
other address lines during display modes.
Referring to the adder 121, as mentioned, the signals
The adder 114 is an ordinary digital adder for adding VA, VB Vc are the three least significant vertical
two 4-bit digital nibbles and for providing a digital sum 35 counter bits from the counter 58. These bits or counts,
signal. A commercially available adder (Part No. 283) is by way of example, represent the 8 horizontal lines of
employed. The carry-in terminal (pin 7) is grounded each character. In adder 12, a 3-bit digital signal, VAi,
and no carry-outs occur since one of the inputs (pin 12) VBI and VC1, is added to the count from counter 58.
is grounded. The adder sums the digital signal corre- This 3-bit signal is constant during each frame, how-
sponding to H3, H. and H5 with the digital signal corre- 40 ever, it is incremented for each new frame.
sponding to V3, V4, V3, V4. The resultant sum signal is
During a first frame, 000 is added to the vertical
coupled to the multiplexers 116, 117 and 118 as illus- count. During a second frame, 001 is added; and during
trated. the summing of these horizontal and vertical a third frame, 010 is added, and so on. By adding this
counter signals is used to provide the more dispersed digital signal to the count from counter 58, the ad-
mapping as previously discussed.
45 dresses to the memory are changed in the vertical sense.
The adder 121 is identical to adder 114 and is coupled During the first frame when 000 is added, the display
to sum the three least significant vertical counter bits remains unaffected. During the next frame, when 001 is
from the counter 58 (FIG. 2) with the signals VAl, VB1 added to the vertical count, instead of first displaying
and VCI. The sum is selected by the multiplexer 120 the first line of a character, the second line of each
during the high resolution display modes and also dur- 50 character is displayed at the top of each character space
ing scrolling as will be described. These sum signals are and each subsequent line of the character is likewise
coupled to the multiplexers 117, 118 and 119. During moved up one line. If data in memory is not moved, the
the low resolution display modes, the mulpxer 120 first line of the character would appear at the bottom of
couples ground signals or the page 2 signal (PG2) to the each character. Note when 001 is added to Ill from the
multiplexers 117, 118 and 119. (The P02 signal is used 55 counter, 000 results. Thus, the first line of characters
for special mapping purposes, not pertinent to the pres- would be addressed when the beam is scanning the
ent invention.) During the high resolution modes when eighth line of characters. To prevent this, the data cor-
the display is not being scrolled, the VAl, VB2 and responding to the first line of each character is moved in
VB3 signals are at ground potential and thus no sum- memory for this frame. The first line of one character is
ming occurs within adder 121 and the VA, VB and VC 60 moved up and becomes the bottom line of the character
signals are coupled directly to the multiplexers 117, 118 directly above it. When 010 is added, the process is
and 119.
again repeated. For example, the third line of each char-
The address signals Ato, Aji, and Aj3 from the CPU acter is first displayed in each character space and the
are coupled to the multiplexers 117, 118 and 119, re- second line of each character is moved up to become
spectively, through exclusive OR gates 124, 125, and 65 the bottom line of the character directly above it. This
126, respectively. The other input terminals to gates 124 process is repeated to scroll the data. The movement of
and 125 receive the C3 signal, while the other input data in memory is controlled by the CPU in a well-
terminal of the gate 126 receives the Ci signal. (The known manner.
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12
Thus, through use of adder 121, an even, continuous 4. These four signals (or alternatively four signals from
scroll is obtained without moving all the data in mem-
ory for each frame. Rather, only th of the data is
moved for each frame.
Referring now to FIG. 5, the circuitry used to extend
the addressing from the CPU is illustrated. In general, the CAS signals are generated by the ROMs 127 and
128. The RAS signals are generated by the ROM 132. The multiplexer 130 allows the selection of either the
the A bus) provide four of the inputs (address signals) to the ROM 132. The other inputs to this ROM are the DHIRES, Z PAGE, PAS, PA15, RFSH (refresh), and AY signals. These address signals select the RAS 0, 3; RAS 1, 2; RAS 4,5 and RAS 6,7 signals. The ROM 132 is programmed to implement the following four equations.
bank switching signals, or the unique indirect address- 10 ing mode when "bank switching" occurs without direct commands from the CPU.
PRASO,3 =AY.(DHIRES+ RFSH) +(ABK4(Z Page.Al))+ ABK1.ABK2.ABK3).AY
The CAS ROM 127 receives as an address the following signals: PRAS43, PRAS 1,2 AY, DHIRES, R/W, A11, A13, A14, and A15. As the PRAS4, 3 and 15 PRAS 1, 2 represent the RAS signals being used. These
signals are high when the respective RAS signal is ac-
PRAS1,2 =AY.(DHIRES + RFSH)+AY.(ABK. T.ABK2.ABK3.(ABK4.(ZPAGE.ÄÏ).PA15.
+ ABK1.ABK2.ABK3) +AY03.(.
1.ABK2.ABK4.(ZPAGE.PAM).PA15 + ABKl.ABK2.(ABK4-(ZPAGE.Pï)-PXi5)
tive.
As previously mentioned, the AY signal is high for
display modes and the DHIRES signal is high for high resolution display modes. The CAS ROM 128 receives
20
PRAS4,5 RFSHAY + AY.ABI(2.ABK3-(ABK.
1.ABK4.(ZPAGE.PÄI).PA15 + ABK1.(ABK. 4.(ZPAGE.PAS).PA15)
as address signals the ABK!, ABK2, and ABK3 signals and also DHIRES, AY, IND, A11, A13, A14, and A15.
The ROMS 127 and 128 are programmed to imple-
PRAS6,7 RFSHAY + AY.ABK3.(ABK1.ABK. 2.ABK4-(ZPAGE.PAS).PAI5+ABK1.ABK. 2.(ABK4-(ZPAGE.PAS).PA1S)
ment the following equations.
25 Thus, the bank switching signals (along with the other
PCASO = (PRASO.3(DHIRES.AY + AY.(AB.TÏ3Äfl.R/\VN + j.Äi.R/WN + Al-
5.il.Al3 ± A15A14A13Xii)))
input signals to ROM 132) select predetermined rows in
memory in conjunction with the CAS signals.
(I)
The output signals of the ROM 132 are coupled
PCAS2 =(DHIRESAY + AY(ABKI.ABK2ABK. + ABKI.ABK2.ABK3).(A15.A14-
through the NAND gates 142, 143, 144 and 145 to the 30 memory. The other input terminals of these gates re-
)+ AY.IND.AKi.ABK2.ABK3.Al5.(Al4.Al3-
ceive the RAS timing signal. In this manner, the output
+ A14.A13))
(2) signals of the ROM 132 are clocked through the gates
PCAS3 = PRASO.
3.(DHIRES.AY + AY.(At5.A14.A13.All + Al-
5.Al4.j5.fl + A15A14.A1i)))
142 through 145 to provide the RAS signals shown in
(3)
35
FIGS. 5 and 6. An important feature to the presently described com-
PCAS4,6= (AY.IND.ABK3.A15.(ABKI.ABK+ ABK1).ABK2)
(34.Al3± A14 ÏI) + AY.lND.ABK3.(Bk.
i.Al5+2ABKl +ABK2N-
1.ARAu+Al5 ÄiD) + AY.iND.0K5.ABK2.(.ABK.
i +Al5.i)-(AAD+Ai4-i3))
puter is provided by the circuitry shown within the dotted line 146. The AND gate 14.8 receives, at its input
terminals, the DA7, Al2, and C3 signals. The NOR gate
40 149 receives the zero page and Ais signal. The output of gate 149 provides one input to the gate 14.8 and also one input to the AND gate 150. The output of gate 14.8
(4) provides another input signal to gate 150 and this signal
PCAS5,
7, = (AY.ffb.03.(ABKlABK2+ ABK1. ABK2).(TLAi4.Al3 +Al5.A13.D)+AY-1.
+ ABK2-ABK-
i +ABK2ABK1-A15).A14+AY.INDABK. l.ABK2.ABK3.(B.Al4)+ AY.1ND.1. JABK2.(ÄÏI-ABK1 +Al5-ABKl).(Th.Al3-
+A14.A13))
(line 153) is one of the two control signals coupled to 45 the multiplexer 130. The AND gates 150 and 151 also
receive a SYNC signal and the d'o signal. The output of the gates 150 and 151 are coupled to a NOR gate 152 with the output of the gate 152 (line 154) coupled to the other control terminal of the multiplexer 130. (5) 50 The gates 150, 151 and 152 effectively form a clock
for multiplexer/register 130 (multiplexer 130 is a com-
In effect, these ROMs are programmed to allow selec- mercial part, Part No. 399, which effectively is a regis-
tion of predetermined rows in the memory, based on the ter/multiplexer). This selects the lower four input lines
address signals A10, A13, Aj4 and Aj, (ignoring for a to the multiplexer 130. However, because of the syn-
moment the contribution of the AS signals and the 55 chronization signal applied to gate 151, the multiplexer
other signals appearing in the equations). The outputs of the CAS ROMs 127 and 128 are cou-
pled to the register 131. Register 131 is a commercially available register which permits the enabling of output signals (Part No. 374). During accessing of the memory 60 the various CAS signals (CAS O through CAS 7) are
130 selects the bank switching signals each time an OP
code is fetched by the CPU. To understand the operation of the circuit shown
within the dotted line 146 it should be recalled that the memory of FIG. 6 provides a 16-bit output. As men-
coupled to the memory of FIG. 6 to permit selection of tioned, during certain display modes, 16-bits/macc. are
the appropriate memory devices. The signal USELB needed for display purposes. In nondisplay modes, only
from CAS ROM 127 through register 131 selects either 8-bits are required, particularly for interaction with the
the A bus or B bus. This signal is coupled to the multi- 65 CPU. When the memory is addressed by the CPU dur-
plexers 43a and 43b of FIG. 3.
ing the indirect addressing modes the data on the A bus
During normal operation, the multiplexer 130 selects is not ordinarily used. However, with the circuitry
the bank switching signals BCKSW 1 through BCKSW shown within the dotted line 146, this otherwise "un-
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14
used" data is put to use to provide the equivalent of the word 0001 is placed in the shift register and circulated
bank switching signals through multiplexer 130.
at a rate of 14 MHz. The resultant signal which has a
Whenever the CPU selects a predetermined range of component of 3.5 MHz is shown on line 206. The phase
addresses, the multiplexer 130 selects the equivalent of relationship of this component to the 3.5 MHz reference
the bank switching signals from the A bus provided 5 signal determines the color of the resultant video signal.
DA7 is high. (This occurs when addressing as zero page This relationship is changed by changing the 4-bit word
the address space -1800 through 1FFF.) Once the signal placed in the shift register. As explained in the above-
on line 153 is high it is latched through gates 150, 151 referenced patent, if the signal 1000 is placed in the
and 152 causing the multiplexer 130 to select the four register and circulated, the resultant phase relationship
bits from the A bus (assuming the timing signals are 10 of the 3.5 MHz component results in the color brown,
high). Even if the next reference from the CPU is not to this signal is shown on line 208. With this prior art
this special address range, the multiplexer 130 nonethe- technique, the luminance was determined by the DC
less remains latched with the four bits from the data bus. component of the signals such as shown on lines 206 and
Once the SYN pulse drops, however, which is an indi- 208.
cation that an OP code is being fetched, the signal on IS The display subsystem 48 of FIG. i also uses 4-bit
line 154 rises in potential, causing the multiplexer to words to generate the various color signals in a manner
switch back to the bank switching signals.
somewhat similar to the above-described system. Refer-
Effectively, what occurs is that when the CPU selects ring to FIG. 8, 4-bit words representative of colors (16
this special address range, (and provided DA7 is high) possible colors) are coupled to the bus 180. (The genera-
the bits DAO through DA3 which are stored in mem- 20 tion of these words shall be described in detail in con-
ory, cause a remapping, that is, the address from the junction with FIG. 7.) Instead of using a shift register
CPU accesses a different part of the memory. With the which circulates the 4-bit work, the same result is
fetching of each OP code, the mapping automatically achieved by using a multiplexer 205 which sequentially
returns to the bank switching signals. Importantly, the selects each of the lines of the bus 180. The signals on
remapping, which occurs is controlled by the bits stored 25 bus 180 also provide a luminance signal and a black and
in the RAM (DA4 through DA3). Thus, with the white video signal with a gray scale.
remapping information stored in RAM, toggling can
The 4 lines of the bus 180 are coupled to multiplexer
occur between different portions of the memory with- 205; this multiplexer also receives the C7M and the
out requiring bank switching signals, or the like from C3.5M timing signals. These two timing signals cause
the CPU. This enhances the CPU's performance since 30 each of the four lines to be sequentially selected and
CPU time is not used for remapping. Additionally, it coupled to line 191. (Note that the order in which each
provides an easy tool for programming.
of the lines of the bus 180 is selected does not change.)
For some program languages it is desirable to sepa-
In effect, the multiplexer operates to serialize the
rate data and the program into separate portions of the parallel signal from bus 180. Assume for sake of expla-
memory. For example, the 128K memory can be di- 35 nation that the digital signals on bus 180 are 1000 as
vided into two 64K memories, one for program and one indicated in FIG. 8. The signal on line 191 will then be
for data. Switching can occur between these memory 10001000... . The output of the multiplexer 205 cou-
portions without the generation of bank switching sig- pled to the input of the inverter 204 also receives in a
nals by the CPU with the above described circuit. This sequential order, the signals from bus 180, however, in
arrangement is particularly useful when using the Pas- 40 a different order. For the example shown, the input to
cal program language.
inverter 204 is 00100010. . . After inversion, this results
DISPLAY SUBSYSTEM
in the signal 11011101 . . . on line 192. Effectively, the signals on lines 191 and 192 are added by resistors 199
The display subsystem 48 of FIG. 1 receives data and 200. The resultant waveform is an AC signal (no
from the A bus and B bus and converts the data into 45 DC component) shown in FIG. 9 on line 209. Thus,
video signals which may be used for displaying alpha- with the described circuit, a chroma signal is generated,
numeric characters or other images on a standard raster having a predetermined phase relationship to the 3.5
scanned cathode ray tube display. The display subsys- MHz color reference signal. This phase relationship
tem 48 specifically generates on line 197, a standard which is varied by changing the signals on bus 180
NTSC color video signal and a video black and white 50 determines the color of the video signal on line 197.
video signal on line 198 (FIG. 8). This display subsys-
In the prior art display discussed above, the DC com-
tem, in addition to other inputs, receives a synchroniza- ponent of the color signal determines the luminance. In
tion signal, and several clocking signals. For sake of the present invention, the signals on bus 180 are coupled
simplicity, the standard color reference signal of to the base of transistor 195, consists of an AC signal
3.579545 MHz is shown as C3.5M. Twice this fre- 55 from resistors 199 and 200, and the luminance level also
quency and four times this frequency are shown as C7M determined by the signals on bus 180. These inputs to
and C14M, respectively.
transistor 195, along with the C3.5M signal, generate a
Before describing the details of the display subsystem NTSC color signal on line 197 of improved quality
48, a discussion of a prior art display system will be when compared to the discussed prior art system.
helpful in understanding the present display subsystem. 60 In some cases, the signals on bus 180 are all binary
In U.S. Pat. No. 4,136,359, a video display system is ones or all binary zeros. When this occurs, there is no
described which is implemented in a commercially AC component from resistors 199 and 200 (no color
available computer, Apple-II, sold by Apple Computer, signal) and the resultant signal on line 197 is either
Inc., of Cupertino, Calif. In this system, 4-bit digital "black" or "white."
words are shifted in parallel into a shift register. These 65 The lines of bus 180 are also coupled through resis-
words are then circulated in the shift register at 14 MHz tors to the base of a transistor 196. Each of these resis-
to define a waveform having components at 3.5 MHz. tors have a different value to provide a "weighting" to
Referring to FIG. 9, line 206, assume that the digital the binary signal.
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16
This weighting is used for non-color displays to pro- mode, multiplexer 166 selects bus 181. Thus, typically,
vide "gray" shades as opposed to having a display with the multiplexer 171 receives the signals from bus 174.
only black and white. The binary signals on bus 180
For purposes of description above, and also for pur-
drive the transistor 196 to provide a video signal on line poses of explaining for some of the display modes below
198. RGB is generated with weighted sums of these 5 a simplifying assumption has been made. The signals
saine five signals.
coupled to the bus 180 by multiplexer 171, for most
Referring now to FIG. 7, data from memory is cou- modes, are controlled by the serialized signal on line
pled from the A bus and B bus to registers 159 and 158, 190. This serialized signal is in sychronization with the
respectively. These registers are clocked by the 1 MHz C7M or C14M clocking signals. The multiplexer 205 of
clocking signal and its complement, thus permitting the 10 FIG. 8, which as described above, does the "spinning"
sequential transfer of 8-bit words every 0.5 msec. As for the parallel digital signal on bus 180, operates in
will be described, in some display modes the data is sychronization with the multiplexer 171. In the descrip-
transferred at the 2 MHz rate, and in other display tion above, and except when otherwise noted below, it
modes, at a 1 MHz rate.
is assumed that, by way of example, if the multiplexer
The registers 158 and 159 are coupled to an 8 line 15 171 is coupling all binary ones and zeros onto bus 180.
display bus 160. This display bus transfers data to regis- the signal on line 191 will be either ones or zeros. Also
ters 164 and 173, and also addresses to a memory 162. for this condition the signal on line 192 will be all binary
The registers 164 and 173 and memory 162 are enabled zeros or ones, and thus, no AC signal is generated at the
during specific display modes as will be apparent.
base of transistor 195. However, as actually imple-
The character memory 162, in the presently preferred 20 mented, there is a "phase" difference between the
embodiment, is a random-access memory which stores clocking of the multiplexer 171 when compared to the
patterns representative of alpha-numeric characters. sampling of the signals from bus 180 by the multiplexer
Each time the computer is powered up, the character 205. This results in a first constant AC signal on the gate
information is transferred from the ROM 50 into the of transistor 195 even when it appears that all binary
character memory 162 during an initialization period. 25 ones are on bus 180, and a second constant AC signal
During character display modes, the signals from the when all binary zeros are on the bus 180. Thus, in this
display bus 160 are addresses, identifying particular specification, when it states that "black" or "white
alpha-numeric characters stored within the character signals are being generated, instead, as currently imple-
memory 160. The vertical counter signals VA, V8, and mented, two constant colors are generated on a color
Vc (previously discussed in conjunction with adder 121 30 display. Where a true black and white is desired, color
of FIG. 4) identify the particular line in each character suppression is introduced such as through the color
which is to be displayed. Thus, the generation of the burst signal.
digital signals representative of each of the characters
The circuit of FIG. 7, along with the circuit of FIG.
occurs in an ordinary manner. The 7-bit signal represen- 8, provides the capability for several distinct display
tative of each line of each character (memory output) is 35 modes. The first of these modes provides a display con-
coupled to the shift register 167. Through timing signals sisting of 40 characters (or spaces) per horizontal line.
not shown, either the register 164 or the character mem- This requires a data rate of 8-bits/MHz or half the data
ory 162 is selected to allow the shift register 167 to rate the memory is capable of delivering. In this mode,
receive either data directly from the A bus or B bus, or data is loaded from the A bus during every other 0.5
alpha-numeric character information from the memory 40 .ssec period. (B bus is not used during this mode.) This
162.
data addresses the character memory 162, and along
The 7-bits of information from either memory 162 or with the signals VA, VB and Vc, provides the appropri-
register 164 are serialized by the shift register 167 either ate character line (7-bits) to the shift register 167. Dur-
at a 7 MHz rate or 14 MHz rate, depending upon the ing this mode, registers 164 and 173 are disabled. The
display mode. The serialized data is coupled by line 185 45 shift register 167 for this mode shifts the data at a data
to the multiplexer 169, pins 1 and 4. The inverse of this rate of 7 MHz (note CH8O is high, allowing the 7 MHz
data is also coupled to multiplexer 169, pin 3. Line 185 signal from gate 175 to control the shift register 167).
is also coupled as one input to the multiplexer 166 and to Each 7-bit signal is shifted serially onto line 185 and
the register 170 (input 1).
then to line 189 since multiplexer 169 selects pin 4. The
The output i of register 170 (line 186) is coupled to 50 data is shifted through the register 170 onto line 190.
the multiplexer 169, pin 1; to register 170 (input 2); and The serial binary signal on line 190 causes the selection
to multiplexer 166. Output 2 of register 170 (line 187) is of buses 183 or 184.
coupled to input 3 of register 170 and also to multiplexer
The four lines of bus 183 during this mode are cou-
166. Output 3 of register 170 (line 187) provides a third pled to + V (register 173 is disabled); therefore the input to the multiplexer 166. Input 4 of the register 170 55 selection of bus 184 provides four binary ones. The
receives the output of the multiplexer 169 (line 189). selection of bus 184 provides four binary zeros through
Output 4 of register 120 (line 190) provides one control bus 181. Thus, the serial binary signal on line 190 pro-
signal for the multiplexer 171.
vides either all binary ones or all binary zeros to bus
The multiplexer 171 selects either the four lines of bus 180. As discussed, the circuit of FIG. 8 will provide a
183 or the four lines of bus 184. The output of multi- 60 black and white display with 40 characters per line.
plexer 171, bus 180, provides the 4-bit signal discussed
If the inverse and flashing timing means 172 is se-
in conjunction with FIG. 8. During one of the high lected, each time the shift register 167 is loaded, multi-
resolution display modes (AHIRES), the multiplexer plexer 169 shifts between pins 3 and 4. This causes the 171 is controlled by a timing signal from the output of characters to change from white characters on a black
the gate 178.
65 background to black characters on a white background,
The multiplexer 166 selects either the lines of bus 181 and so on.
or bus 182. The output of this multiplexer provides the
During the 80 character per line display mode, the
signals for the bus 184. In all but the AHIRES display registers 158 and 159 are each loaded during sequential
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18
0.5 sec periods (this utilizes the 2 MHz cycle rate
During a first graphics mode, data from the display
previously discussed). The shift register 167 shifts the bus 160 is loaded into shift register 167 at the rate of
character data from memory 162 at a 14 MHz rate. The 7-bits/MHz. The data is serialized on line 185 and in the
serialized data at the 14 MHz rate is shifted through the manner previously described for displaying characters,
register 170 and again controls the multiplexer 171 as 5 controls the selection of all binary ones and all binary
previously described. (Note that register 170 is always zeros through the multiplexer 171. Note, as mentioned
clocked at the 14 MHz rate.) Flashing again can be before, in the presently preferred embodiment, unless
obtained as previously discussed.
color suppression is used, this will not result in a black
In another alpha-numeric character display mode, the and white display, but rather a two-color display. If a
background of each character may be in one color and io high bit is present on line 140 of the display bus, the
the character itself (foreground) in another color. This inverse and flashing timing means 172 causes the multi-
mode provides 40 characters per line. The character plexer 169 to alternate between pins 1 and 2. This
identification (address for RAM 162), is furnished on switching occurs at a 1 MHz rate and provides a phase
the A bus to register 159 at a frequency of 1 MHz. The shift for every other 7-bits of data coupled to the multi-
color information (background color and foreground 15 plexer 171 on line 190. This results in an additional color
color) is furnished on the B bus as two 4-bit words to being generated on the display for every other 7-bits of
register 15$. In the manner previously described, the data.
address from register 159 selects the appropriate char-
For the above-described graphics modes when shift
acter from memory 162 and provides this information to register 161 is shifting at a 7 MHz rate, 8-bits may be
shift register 167. The color information from the B bus 20 coupled to the bus 160 during each period. Specifically,
is transferred to register 173. For purposes of explana- as in the case of the differing background and fore-
tion, assume that the 4-bits identifying the color red for ground colors for the 40 character per line display
the background are on bus 184 (from register 173 and mode, two 4-bit color words are shifted into register 173
multiplexer 166) and that 4-bits representing the color at a rate of 1 MHz. Then, the multiplexer 171 selects
blue for the foreground are on bus 183. (Note that when 25 between two predetermined colors on buses 183 and
register 173 is enabled, the signals from the register 184. Note these colors can be changed at a 1 MHz rate.
override the binary ones and zeros which otherwise
appear on the lines of bus 174.) The serial binary signal representative of the character itself on line 190, selects either the color blue from bus 183 for the character itself or the color red from bus 184 for the background. The digital signals representative of these colors are
transferred to bus 180 and provide the color data to the
circuit of FIG. 8. For black and white displays, a
"gray" scale is provided through the weighting circuit associated with transistor 196 of FIG. 8. Again, the multiplexer 169 may, through the timing means 172, alternate between the signal of line 185 and its inverse,
which will have the effect of interchanging the fore-
30 35
In an additional color mode identified as "AHIRES," multiplexer 171 operates under the control of gates 176, 177 and 178. In effect, multiplexer 171 selects bus 184 and latches the signals on this bus every four cycles of the C14M clock. Data is shifted into the shift register 167 from the A bus and B bus every 0.5 sec the register 167 operates under the control of the C14M signal. Each data bit on line 185 is shifted first to line 186, then to line 187 and finally to line 188. These lines are coupled to the multiplexer 171 through multiplexer 166 which selects bus 182 since AHIRES is high. In effect, what occurs is that 4-bit color words are serialized onto line 185 and then brought back into parallel on bus 182.
ground and background colors.
40 Since multiplexer 171 latches the signals on bus 184
During the high resolution graphics modes, the character memory 162 is not used, but rather, data from the memory directly provides pattern information for display. This requires more mapping of data from within the main memory since new data is required for each 45
every four cycles of the C14M signal, a new color word is generated at a 3.5 MHz rate on the bus 180. The resultant display is 140 by 192 colored blocks wherein
each block can be any one of 16 colors.
line of the display. (Note that when characters are displayed, the character memory 162 provides the differ-
In the last display mode, typically used with color suppression, data is shifted into the shift register 167
ent signals required for the 8 lines of each character from the display bus at the rate of 14-bits/MHz. The
row.) During these high resolution modes, the register data is serialized onto line 185 and controls the selection
164 is enabled and the character memory 162 is dis- 50 of either all binary ones or all zeros through multiplexer
abled. Thus, the data from the A bus and B bus is shifted 171. This provides the highest resolution graphics dis-
into the shift register 167. In these modes, the "HRES" play for the system.
signal to multiplexer 169 causes this multiplexer to se-
Thus, a microcomputer with video display capability
lect between pins i and 2. Pin 2 provides the signal has been described. The computer is fabricated from
directly from the shift register 167 while the signal on 55 commercially available parts and provides high utiliza-
pin i is effectively the signal on line 185 delayed by one tion of these parts. Numerous existing programs includ-
period of the C14M signal. This delay occurs through ing many of those which operate on the Apple-II com-
the register 170 from input 2 to output 2 since register puter, may be employed in the above-described com-
170 is clocked at C14M.
puter.
60
65
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
F000.
F000 F000
FOOD F000 FOOD F000 Foco F000 F000 FOOO F000 F000 F000 F000 F000 F000 F000 F000. F000 0200 0302 F000 0080 OOEO. F000 0381 0082 0083 0084 0085
0088 0089 0089 008A 008D 0080
F000 F000 F000 F000
F0O
FOOD 0093 0094 0098 009F F000 F000
F000:
F000: F000:
F000: F000: 0095: 0095:
0096:
0097:
F000:
F000:
F000:
F000:
4,383,296
19
TABLE I
20
13
14 *
15 * j*
* '
18 * 19 * 20 *
CRITICAL TIMINQ
REQUIRES PAGE 8OUND 4
cONSIDERATIONS FOR
*
CODE AND DATA
*
-----CODE
*
VIRTUALLY THE ENTIRE *
'WRITE' ROUTINE
*
*
NUEI NOT CROSS
PACE COUNCARTEC
*
23 * CF.
BRANCHES iN *
.
24 * THE '14R1 rE. 'READ'.
*
25 * AND 'EAD AC' SUBRS *
26 * WHICH MUST NQT_ÇROS
*
4 PAGE 8OUNDAFTr ARE
*
28 * NOTED IN COMMLNTS
*
2*
*
30 ***************************
31 *
*
3323**
EQUATES
*
*
34 NBUFt EQU $200
35 NBUF2 EGU $302
3*
, (ZEF0 PA AT $300 Mt
37 HRDERRS EGU $80
38 DVTIOT EQU SEO
3*
4o IIiSLOT EQU $81 41 T0FRVN EGU IBSLOT+1
42 IBTIW. EGU IBSLOT+2
43 IBSECT EQU IBSLOT+3 44 ID8UFP EGU IBSLOT+4 &5
45 IBCN1D EQL) IBSLOT+6 4 IBSTAT ECU IDSLOT+7
47 IBSNOD EGU 48 CSUM EQU 49 IOBPDN EQU
II3SLOT+8 II3SMOD IBSLOT+9
USED ALSO FOR ADDRESS HEADER CKSUM
§0 lrIASI4 EUL' IBSLOT+$A 51 CUihk E,U IBSLOT+SR 52 DPV0TR. FU CURTR$.-7
53 SLOT 4, 'RIVE i 54 .SLOT 4 PIVE 2
55 .SLOT 5. DRIVE i
56 .SLOT 5. DRIVE 2 57 , 51.01 , DRIVE 1 58. SL.OT 6. DRIVE 2 59 RETRICNT EQU ISSLOT+$12
60 SEE3cCNT EGU IBSLOT+$13
61 flUE
EGU IBSLQT+$1A
62 ENVTEMP EGU IBSLOT+$TE
63 *Ifl5lQT+$IF NOT USED 64 *
66 e*.*R*l***.,.,,Ø,s,*.,..
61*
68 * ----READADR---- *
6790**************************
71 COUNT 72 LAST
73 ÇKSUM 74 CSSTV
EGO IBSLOT+*14 'MUST FIND' COUNT.
EGO
EU
II!B5SL1OTH+$C14K;S'VODMD BBITY' TNIEELS.
EGU IBSLOT+$16 ;FOUR BYTES,
7*
76 *
CHECKSUM, SECTOR1 TRACK, AND VOLUME.
77 ************************
78 *
*
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
F90_Q F000: F000: F000: F000: F000: F000: F000: F000: F000: F000: F000: F000: F000: F000 F000 F000: F000: F000 F000. F000 F000 F000. F000 F000 0095 009D. 009E F000.
F000
F000:
F000 F000 0099 009A F000. F000:
F0Q_
F000: F000: F000:
F000:
C080: COSi: CO8C: CO8D: COSE: CO8F: FFEF: FFDF: 0080: 007F: F000: F000: F000: F000: F000: C088:
4,383,296
21
22
79 * ----WRITE----
*
80 *
*
81 * USES ALL NBUFS *
82 *
AND 32-BYTE
*
83 * DATA TABLE 'NISL' *
84 *
*
86 * -
87 ***********************
88*
*
89 *
READ---- *
90 *
*
91 *
USES ALL NULIFS
*
92 * USES LAST 54 BYTES *
93 * OF A CODE PAQE FOR *
94 * SIGNIFIÇANTBYTES *
95 * OF DNIBL TABLE.
*
96 *
*
97 ************************
98 *
99 ***********************
100*
*
101 *
---- SEEK ----
*
102 *
*
103 ***********************
104 TRKCNT EGLI COUNT
HALFTRKS MOVED COUNT.
105 PRIOR EGLI IBSLDT+$1C
106 TRKN
EQU I13SLOT+$1D
107 *
108
109 *
*
-. 110 * ---- MSWAIT ---- *
111 *
112 113 MONT!MEL Ethi CSSTV+2
MOTOR-ON TIME
114 MONTIMEH EGLI MONTIMEL+1 ,COUNTERS.
115
1 1 7
*****4*************
118 *
119 *
DEVICE ADDRESS
*
120 *
ASSIONMENTS
*
121 *
*
122 ************************
123 PHASEOFF EGLI $C08O
,STEPPER PHASE OFF.
124 PHASEDNEQU SCOB1
ON.
125 G6L
EOU $CO8C
1G7L,GÓLREAD
126 06H
EGLI $CO8D
;07L,GÓHSENSE WPROT
127 071.
EGO $CO8E
;G7H,G6L=WRITE .
12E 07H
EGLI $CO8F
.G7H,Q6HWRITE STORE
129 INTERUPT EQU $FFEF
130 ENVIRON EGLI $FFDF
131 ONEMEO EGU $80 132 TWOME EGLI $7F
133
134 *
135 * EQUATES FOR RWTS AND BLOCK
136 * 137 *******************************
138 MOTOROFF FG') $C088
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
C089:
CO8A:
CO8B:
C081: COBO
009'
0097
0098
0099
0099:
09 A
0083
o os ;
0081
0080V
F000
FOCO.
F000
DOC
F000 F000 F000 AQ 01
)OQ; Aá 81 f 04 84 94 F00) OF F007 66
F008. ÓA F009 A
,1OA 6A F0013 thA FOOC 8 SB FOOE AD DF FF F011 85 9F F013 FO i J
r_-c) I J
C') 20 213 f-1
oi 08
F-Cil 7 AS 95
'Ol9 85 99
fi 1(3 4'- 8
r-0113 H' 9
FC,1F "' EQ F021 EJ5 QA F023 AS 82 F025 CS 84 F027 35 04
F02' 03
F074 A
F020 PD 89 C' p021- -0 01
F030 EL3 DL' BA CL. :-- 4C F
r017 ¿9 F038 F0 04 F034 29
frQ313 AO 07
VC3r :) 56 FI roo CO
'41 (C') FA F043 08 F044 AS 83 F046 46 81 r-04E 2:' 05 FI
r-' 413
r :--.s
F048 29 FC'4C 00 17
F04E
4,383,296
23
24
139 MOTORON EGU $C089
140 DRVOEN EGU
141 DRV1EN EGU
142 PHASON EQU
143 PHSOFF EQU
144 TEMP
EQU
145 CSUMI EQU
146 SECT EQU
147 TRACK EGU
148 TRN1 EGU
149 VOLUME EQU
150 IDRERR EGo
151 IBDERR EQU
152 II3WPER EGU
153 IBNODRV EGU
ICOBA SCOBB $C081 $COB0 CSSTV TEMP
C SUM 1+ 1 SEC 1+ 1
TRACK
TR AC K+ i
HPflEPRI 3
r$R ZIER R
HPDERRS+ i
HRDERRS
PUT ADDRESS INFO HERE
155
156 *
157 *
-L..L1TEA
*
*
158 *
AND SECTOR
0
15
*
160
161 *
162 REGFWTE LDY $1
RETRY COUNT
0
LI'X 1351.OT
GET SLOT $ FOP THIS OFEFAI1ON
Le-4
'Ic'hTCt-4DFEECTNTERMOINNLYEONTENRTECEALP.Ir''ArrF PEP :4).).
166
PLA
167
POR A
1613
ROlf A
GET INTERUPT FLAG INTO OIT 7
FOR A
POP A
1 '1
MAbI4
172
LOA ENVIRON
PRESERVE ENVIRONMENT
173
STA ENYtEMP
174 1--S * NQ
.f-$í - (F THE r1.:TQR IO- ON.. TREN START IT
iSP 'f*DRV
OET ZERO FLAG 1F MOiO STOPPE!:
178
OHR
SAVE TEST RESULTS
179
LDA 1OBUFP
MOVE OUT POINTER TO L1VFFEP INTO 7F-AGE
IBO
STA 913F
t DA I13!3'JFP+I
STA t)UF+1
23
*5VPIOT
1134
STA MONTTMEN
195
LOA IBDPVN
DETERMINE DRIVE ONE OR TWO
186
ClIP TORPDN
SAME DRIVE USE' BEFORE
irr'
)- IÙCPDN
S--C IT FOR NEIl TIME
PHP
RESULTS i:)F COMPARE
113
P38
tPO
LOA
191
0CC
12
1NX
1J J1VSEI. LDA
A MOTaRON
DRIVSEL
DHVOEN, X
DRIVE NUMER Irjos CARRY ,TUPN ON TRE DF1'E BRANCH IF DRIVE I SELECTED ;SLECT DRIVE 2
I4
390 'ETlMEG
INSURE ONE ME';AHFPTZ OPERATION
15
PIP
, WAS IT SAME Df1IVE
196
!3EQ OK
197
PLP
MUST INDICATE DRiVE OFF BY SETTING ZERO
198
LDV $7
199 000WAIT -iSP NSWAIT
DELAY 150 MS BEFORE STEPPING , (ON RETI.JRN A''
FLAQ)
200
DEY
201
ONE DPVWAIT
202
PHP
;NOW ZERO FLAG SET
203 0K
LDA IBTRK
;GET DESTiNATION TRACK
204
LOX 1BSLOT
RESTORE PROPER X (SLCJT.16)
.05
iSP IIYSEEK
AND GO TO IT
:06 oNOW AT TIlE DESIRED TRACK WAS TRE rIOTOF
:L7 * -3f-J TO 91'-PT WITH
70f3
RLP
WAS MOTOR ON'
209
lINE TRYTRK
IF SO DON'T DELAY CET IT TODAY'
210
Apple Computer Inc · 1982
Page 0563 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
FO4E
FO4E.
FO4EA0 12
OO:8
'051 00
Q' j -- U
'' t
)C5" E. A 059 D
F058 FOSU FO5B F050
F050 F058 F050 20 20 Fi FOSE Lt( 05
F A) A' F30 F02 4( EP F05
V'ThS
4,383,296
25
26
;i MOTOR WAU OFF, WAIT FoR IT TO SPEED UP
:12 *
¿13 MOTOF
LDY 0*12
WAIT EXACTLY 100 US FOR EA:H COUNT
214 CONWAIT DE
ONE:
t-
IN
:ONWAIT MON) IMEL
COUNT UP TO 0000
IN MONTIME
ONE MOTOF
'I0
iNC MONTIMEH
ONE. F1OTOF
'
221
222 * 22X3 * MOTOR SHOULD BE UP TU SPEED
:'7A ir IT Si ILL LOORS STOPPED THEN r-fl; LP tUE 15 NOT PRESENT
22 *
227
;.:'U2S
JSR CHRDRV ONE I P RR
4L' UEPP LA $ II3NODRY
IS DRIVE PRESENT
VIE CONTINUE NU GET TELL EM NO OF
-r
JMF HNDLERR
2.2 77 234
* NOW CHECk IF IT IS LOCATE IHE CORRECT
NOT THE FORMAT DISk COMMAND SECTOR FOR THIS OPERATION
O5 AS 07
FD9 C9 03
FOl3 030 73
FOD A
ro-E o:
7l F'
AL DF F
:7 '1-
F075 SD DF FF
FOld 2') C F. F070 AO 7F
F071) 034 o:
FO7F A& BI i-oat 20 BD fl F08490 21
F096 24 EID
FÇi'IEI 3: Ql
.0:1) : - 'L-;
i. :
FORF AS BC
F01 48
FO9 C P4 p-4 D., 4F
FRP5 A-----'
FC3 2« 0 F F090 A9 00
F090) 20 -35 Fi
FOAO 68
I-DAI ;- :
F744 4C '03 F
..,
Ll
t:.-
,-::3
.:
-
;i43
4. 1RTTk
.4'
--
-'
¿
."
--
r -'4CR
74
rî.o
cMP OCS
PUF' 1«;-; L_L A
.ILL
STA
1FF' LO
--
oc: DIT DM1
II3CMD
A) LDflE
$3 ALLOONE
A
1F 1RK2
i: NY I PO J
WOMEG
ENVIRON
$ti- PRENI03I.D
'u
-
L-
Ut
-IP io
PORIGHT
1MAS
NOINTR1
-
1''
,-t
.
-i'
26
2'
2ó
.. -
-0).AL1 C Ai
'p.
LDA PRA DEC ONE LOA
SR LOA
,JSR
PLA oSR
,'MP
RETRYCNT TRYADR
CURTRR.
SEERCNT DWVERR *$60 SETTRR *000
MYSEER.
MYSEEk TPYTPH2
CE î CUMMAND DUDE lt t NU1.L C OMMANO GO HOME
COMMAND IN RANGE:-
NsC):r
DO NOTHING CARRY1 FOR
READ
MUNi PREN i VIII. t
L
i
SHIr-T TO HIGH SPEED
WRiTE
ONLY 127 RETRIES nr: ANY RINI)
GET FLOT NUM INTEl X-REG
PEAL' NEYT ADDRESS F TELL:
;IF READ IT RIGHT HURRAH'
SHOULD IFATERUPTS 0E ALLOWED7
NO- DON'T ALLOW THEM
RE--ENABLED AFTER READ/REMDADP'WRIT'
ANOTHER MISTAE
FAILURE
WELL LET IT 0 1H15 TIME
SAVE TRACk WE REALLY WANT ,ONL RECALIBRATE ONCE
TR lit) TO RECALIBRATE A SECOM RECALIBRATE ALL OVER AGAIN ;PRETEND TO BE ON TRACk 80
TIME ERROR
MOVE TO TRACk 00
OC) TO CORRECT TRACk 1H15 TIME! LOOP flACk, TRY AGAIN ON THIS TRACk
F_:A7 FOA7 FOA7
FOA7 A4 99 FOAP CA BC F040 ro 0E FOAD FOADAS 8C
2'-8
269
141E. NOW READ AN ADDRESS FIELD CORRECTLY. MAE SURE 1H15 IS THE TRACR SECTOR AND VOLUME DESIRED.
270 RDPIGHL LIlY TRACk
ON THE RIGHT TRACk"
21
-t IJRTRk
¿72
11E;
IRR
IF so GODO
¿'3 *
))'k.. tNL. FPOM THIS TIF'
274
LOA CURTRk
PRESERVE DESTINATION TRACk
FOAF 48
275
PHA
F020: 96
276
IVA
FOBI 20 25 FI
277
JSR SETTRk
F084 6F
278
PLA
FOS5:20 0$ Fi 27
FOlU: 4C $6 FO 2$O
JJUqPPTMRY YA? _jj.HAA$D PECALIRRATE
FOIl:
2ß2 *
ß3 * DRIVE IS ON RIOH1' TRACk CHECk VOLUME MISMATCH
F059 F032 AS 9A F080 85 89
284 * 285 RTTPF' 286
--
L DA VOLUME
STA IBSMOD
QET ACTUAL VOLUFIF HEIlE ' TELL OPSYS WHAT VOLUME HUE THERE
Apple Computer Inc · 1982
Page 0564 of 0730
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FOBF A 98
FOCi CS 84
FOC3 FO 02
F-0C5 DO 13F
F0C' A 87
1-0CV 4A
FOCA 90 20 FOCC 20 48 F1
FOCF BO US
r- :i i AL DF FF i)Ú42? 7F
C)3F ¶3L DF Ft
LOD9 20 il F3
ODC BC AS FODE A, 81
rIFO io
A 00
ro& ?( 34
FOES 8 FOE6 AV 82
FOEB 3t3
: & its r-CFE4 [iL 8(3 C 1 C'Li.- 24 S[i FC'E' 20 C-i FjF2 8
FCF3 A F
33L DF
1- FA
i
r-
FiIFC QJ E2
i-t'FE AO 81
i-tOO 50 Eó
4: 0& F'
4,383,296
27
28
287 CORRECTVOL LOA SECT
CHECK IF THIS IS THE RIGHT DECTOR
288
CMP IBSECT
289
BED CORRECTSECT i 1F SD. 00 WHATEVER WANTED
290
BNE TRYADR2
NO TRY ANOTHER SEC TOR
291 COFRECTSECT LIlA IBCMD READ 0 WRITEfl
2-'?2
L.SR A
THE CARRY HILL 1ELL
293
8CC WRIT
i CARRY WAS SET FOR READ OPERATION.
294
JSR READIÓ
i CLEARED FOR WRITE
295
RCS TRYADR2
CARRY SET UPON RETURN IF DAD READ
LOA ENV IRON
AND #TWOMEG
STA I:rlv i RON
,SET TWO MEGAHERTZ 1100E
299
JSR POSTNIJ31 DO PARTIAL POSTN]III3LE CONVERSiON
.300
BCE
301
LDX
302 ALLL'NE '.L;
303
LOA
:4
13CC
TRYADR2 II3SLDT
*10
AL.00NE1
i CHERSUM ERROR i RESTORE SLOTN'JM INTO X
NO ERROR
SKIP OVER NEXT [iVIE Al
1i (IPCODE
305 DPVERP PLA
:too
LOA
107 HNIILERR SEC
) ALI-CNE1 [-iTA
itUl'O)
t_Df
LIT
:tit
13Ml
312
CLI
313 NOINTR2 LOA
REMOVE CUR TRR
*IBPERR iBAD DRIVE
INDICATE AN ERROR
IBSTAT
GIVE HIM ERROR#
MOTCIROFF X i TURN IT OFF
i rlASik
0F4-0)LO INTERUPTS [3E ENABL EL
NQINTR2
BRANCH IF NOT
ENVTEMP
RESTORE ORIGINAL ENVIRONNENT
314
OTA E NV I R ON
.
IJt I TE i
WRITE: NYBBLES N01
:31
13CC ALLD ONE
IF NO ERRORS
314
LOA #IBWPER
DISK IS WRITE PROTECTED
31Q
DVC HN DL E R R
TAREN IF TRULY WRITE PROTECT ERROR
JMF r YADR2
OTHERWISE ASSUME AN INTERUPT MESSED
THINGS UP
FI 37 F105 F 103
t' 105 t 105
t t0 C'.\
1-jl:-t- i-19
F100 2') 1 Ft F103 20 2E Fl F10 85 85
os o':
t t t:-: A') -t.'
'liA Q5 EiS Fi 1. 20 00 F4
Fit AO ('3
F118 QO-
FliC 23 4A F3 FUF VA
jj * 17 T4E 7FE' ROUTINE SEERS TRACtS N' IN SLOT *X/$1O 3 * IF DRIVNO is NEGATIVE. ON DRIVE O
'5 * IF DRIVNO LS POSITIVE. ON DRIVE I
:,i'E- : J7 MY :EEk ACt. A ET iFKN1
- ASSUME TWO PHAEE STEPPER SAVE DESTINATION TRACRr*2)
-.31-5k ALLOFF
;TURN ALL PHASES OFF ro 13E SURE
L30
.)SR DRVINDX
GET INDEX TO PREVIOUS TRACK FOR CURRENT
331
LOA DRVOTRP. i
DRIVE
-
ÏA .IJRTRK
1H10 IS WHERE I Ari
LOA TRRNI
AND WHERE ¡ 'M GOING TO
3'4
STA rRvoTcr'
335 GOOFEK ,JSR SEE'
GO THERE
33, ALL(JFF LDY *3
t TURN OFF ALL PHASES BEFORE RETURNING
337 NXOFF l'VA
t (SEND PHASE IN ACC.
138 339
JSR CLRPHASE DEY
;CARRY IS CLEAR
PHASES SHOLD 9E TURNED OFF
F120: 10 F9 340
F122 46 ØC 341
F12460
342
PL $10FF
LPR CtTK
RIS
DIVI PE 1.$ DO
tALL OFF... NOW IT'S DARK
F125.
344 *
F125:. 345 * THIS SUBROUTINE SETS THE SLOT DEPENDENT TRACK
F125
346 * LOt'AT ION
347 *
F 12 20 3E Vi 348 SETTRK JSR DRVINDX , GET INDEX TO DRIVE NUMBER.
F12895 85 349
STA DRVOTRK,X
F12A-60
350
RIS
F128:
351 ******************************
F120 F120:
352 *
-
-
-
-- -
33 * )LR TO TELL IF MOTOR IS STOPPED
F120
F120
355 * IF MOTOR IS STOPPED CONTROLLER'S
F128: F128
356 * SHIFT REG WILL NOT BE CHANGING.
_357 *
F1211
358 * RETURN Y=0 AND ZERO FLAG SET IF IT IS STOPPED
Apple Computer Inc · 1982
Page 0565 of 0730
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F128 F128 F120:A0 00 FI2D BD BC CO F130: 20 3D FI
FI3F. DO 03 F13A 8
F130 oo ro
F13'.
rv3f:
F1? F13[ 8A F140 4A F14 AA
FF1l44. -:4A
F14 Ai
F14 &) F147 O F148
FI4
F14i, F14&
F14c-
FI 48
4,383,296
29
30
359 360
******************4************
ÏCHDRV LDY *0
IIT LOOP COUNTER
362 CHKDRV1 LDA c6L,X
READ THE SHIFT REG
363
JSR CDRTS ;DELAY
364
PHA
363
PLA
MORE DELAY
366
CMP (L X
HAS SHIFT REG CHANGED
367
BNE CRDRTS
;VES, MOTOR IS MOVING
388
DEY
,N0,DEC RETRY COUNTER
369
UNE CHDRV1 ;AND TRY 256 TIMES
370 CkDRTS RT3
THEN RETURN
371 *
372 DRVINDX PHA
;PRESERVE 4CC
373
TXA
;GET SLOT(*$1O)/8
374
LSR A
375
LSR A
376
LSR A
377
ORA I!3DRVN
FOR DRIVE O OR i
378
TAX
; INTO X FOR INDEX TO TAULE
379
PLA
RESTORE ACC.
380 381
*********R*TS********************
382
383 * NOTE: FORMATTINC ROUTINES
384 *
NOT INCLUDED FOR SOS
385 386
*******************************
F141:
F148: F148:
F148: F148: F148: F148: F148: F148: F148: F148: F148: F148: F148. F148 F148: F148: F148: F148: F148: F148: F148: F148: F148: F148: F148: F148: F148: F148: F148: F148:
3e
390 *
READ SUBROUTINE *
391 * (16SECTOR FORMAT) *
392 393
***************************
394 *
*
395 * READS ENCODED BYTES *
396 * INTO NI3UF1 AND NBUF2 *
397 *
*
398 * FIRST READS NBUF2
*
399 *
HIGH TO LOWE *
400 * THEN READS NBUFI
*
401 *
LOW ID HIGH. *
402 *
*
403 * ---- ON ENTRY ---- *
404 *
*
405 * XREG: SLOTNUM
406 *
TIMES *10.
*
*
407 *
*
408 * READ MODE (G6L, G7L) *
409 *
*
410 * ---- ON EXIT
*
411 *
*
412 * CARRY SET IF ERROR. *
413 *
*
414 * IF NO ERROR:
*
415 *
AREG HOLDS $AA. *
416 *
XREG UNCHANGED. *
417 *
-REG HOLDS *00. *
418 *
CARRY CLEAR.
*
419 * ---- CAUTION
*
420 *
*
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
4,383,296
31
32
F148.
421 *
OBSERVE
*
F148:
422 *
'NO PAGE CROSS'
*
F148:
423 *
WARNINGS ON
F148:
424 * SOME BRANCHES!!
*
F148:
425 *
*
F148
426 *
ASSUMES--- *
F 148:
427 *
*
F148
428 * 1 USEC CYCLE TIME *
F 14G
429 *
F148
430 **************************
F148 AO 20
f:14A 88
431 R EAD 16 LDY **20 -- 432 RYiiC DEY
'MUST FIND' COUNT.
IF CANT FIND MARKS-
,j413 FO 6B
433
BEG RDERR
,THEN EXIT WITH CARRY SET
:14I) BD BC CO 434 RD1
LDA GOL, X
READ NIDL.
F150 10 FC
435
I3PL RD1
***NO PAGE CROSS' **'
F15249 D5
436 RSYNC1 EOR *$D5
IDATA MARK 1?
F154. DO F4
437
BNE RSYNC
,LOOP IF NOT.
riso EA
438
p3,7 r[) SC CO 439 RD2
NOP LDA Q6L X
DELAY BETWEEN NIBLS.
15A lo FD
440
BPL R D2
*** NO PAGE CROSS! ***
F15C C9 AA
441
CMP *SAA
DATA MARK 2?
F 15E: DO F2
442
F160. AO
443
BNE RS YNC I LDV 0$55
(IF NOT. IS IT DM1?)
;INIT P41UF2 INDEX.
F102
444 *
(ADDED NIÍL DELAY
F2 BD BC CO 445 RD3
LOA
F165 10 FD
446
DPL RD3
GóL X ;*** NO PAGE CROSS
***
F167 C9 AD
447
1-169 DO E7
440
cliP ø_*A
lINE PSYNC1
DATA MARK T'
(IF NOT LS IT DM')
(1613 130 Oc Cr 4o4980* 4
FIAE 10 F13
451
(170 99 02 03 45
CARRY SET IF DM31
LOA ,36L X
l3P1 804 STA NBUF2 Y
,*** NO PAGE CRUStS ***
STORE BYTES DIRECTLY
Fil_3 AD EF FF 453
f1c
i:5 813 40
454 455
LDA ORA DPL
INTERUPT ¡MASIs GOSERV
POLL INTER'JPT 1_INE
(THIS MAY DE 'sri:'
.,:r.'o
DAt: Foi'.
,.' O F170 IO EE
17D CO
4l
458 ROS
DE Y
OPt. IN Y
804
INDEX TO NEXT
(FIRST TIME Y")'
FI7F Iii) OC (( 459 RD5A
t-1 1) FO
4t)
LOA 06L X
DPI ROS',
GET ENCODED BYTE) rj r'JOLFI
4: 1:t.:: 9 00 0 4&.i
1St AL) EF FI
51 Nt(P 1. Y LOA 1NTERUP3
POLL INTERUPT LiNE
F189 05 813
463
ORA 1MAS)4
(THIS MAY BE USE!) TO INVALIDATE POLL-
F1813 10 2D
464
13PL GOSERV
F1PD CO E4
4",S
CRY #$E4
WITHIN i MS 0F COMPLETION'
r i er DO FC
ONE ROS
F191 OR
4 k-'
I N Y
FiR ¡3D BC C 4ó8 F11),:
LOA (1-l- X
NO POLL FROM N'_3W ON
F195 10 F13
469
I3PL RDa
F197 99 00 OT 470
STA NBUF1 'f
FI9A Ce
471
¡NY
FINISH OUT NI3UF1 PAGE
F190 1)0 F5
47,
ONE FIDa
'-191) 131) BC C- 47:1 Ro-: IkNUM LOA (jL, X
GET CHECFkSUM IFYTE
(1A0 10 FIl
-('4
1301. RDCIkSUM
F142 05 96
475
STA CKSUM
F144 EA
476
NOR
EXTRA DELAY BETWEEN BYTES
FIAS BD BC CO 477 RD.'
(iA'-3 i-.) F13
(-10,, :9 DE
--1(7'8
LOA 6L X
OPI. Rt17
c:rip $DE
,*** NO PAGE CROSS' *** FJRST BIT SLIP MARF«'
i-lAC 1)0 GA
-1RO
liNE R1)ERR
ERR IF (JOT)
-
FIAE EA
481
NOR
DELAY BETWEEN NIBLS
FIAF BD BC CO 4132 8DB
F1132 10 FO
483
LDA 06L X
BPL 8DB
,*** NO PAGE CROSS' ***
1134 09 AA
404
F1B F) SF
FlIP *$AA DEA PDEXIT
SECOND BIT SLIP FIARIA
(DOME IF IT IS'
F1119 JO
-.'ò FI000FI '5E o
INDICATE 'ERROR EXIT
F189 60
4137
RT8
RETURN FROM READ16 OR RDADR16
Fi ¡lA
488 *
r-104 4C 133 F' 4(39 GOSERV ,JMP SERVICE
GO SERVICE INTERUPT
Apple Computer Inc · 1982
Page 0567 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
F1BD: FIDD: F1BD: F1DD F13D: F1DD; F1BD: FIBD:
F113D FiB!)
lBD F1DD. FIBD:
V1D
ri Bi)
F1BD
FiB!). FiB!):
1i3D ÎLU)
FIUD
1DT) r 1LL
Ft'3L FiB!).
-1BD FIBD.
II)!)
11D
1!)!)
'12D
I
- iLiD 1EL)
F1Y3D
FI Br)
F1BD:
i Dr) 1-1 LL)
r:
FII4D FUlL)
F113!) 13E
F1BD'
F1BD:A0 FC F1BF:84 9
4,383,296
33
34
491 ****************************
492 *
*
493 * READ ADDRESS FIELD *
4-?4 *
SUI3FEOUTINE
*
4'?5 w
(1&-SCíO FORMAI)
*
49Ó *
*
497 ****************************
4Q8 *
*
4Q *
READS VL:LUrIE.. TRACk *
'f00 *
AND SECTOR
*
*
502 * ---- ON ENTRY ----
*
503 *
*
504* XREC SLO'rNUM TIMES $10 *
505
50 * hEAD MflDE ( 0L
7L
YY7 *
*
50G *
ON EXIT -----
*
50 *
*
510 * CARRY SET (F ERROR
*
511 51 51
514 *
51
5iç:. *
SF7
51E' -
51 *
520 *
1F NO ERROR
A--REG HOLDS oA
YREG HOLDS $00.
*
XREG UNCHANGED.
*
CARRY CLEAR
*
*
CSSTV HOLD'. CHcUM *
SECIOh. TRACi. AND *
VOLUME READ.
*
521 *
*
52 *
USES TEMPS COUNTS
*
s:: *
514 *
LAST C5JM AND
4 I3YTE AT CST¼
52. *
---.-- EXPECTS --.---
*
527 *
*
520
ORIGINAL toSECTOR
*
NORMAL.. DEN:I NIBLS
*
5
-
.4-B[î) ODD BIlS
THEN EVEN
*
53 *
*
533
----- CAUTIDN ------
*
534 G
*
53*
or3srP r
*
'NO PACF kDS
-
*
WARN i w-
*
53G *
SOME BRANCHES' !
*
539 *
*
540 *
---- ASSUMES ------
*
4 1
52
i USEC ('.LE TIfF
* 41-'
44
545 RDADR1Ó LDY #$FC
46
STY COUNT
* ; 'MUST FiND' COUNT.
Apple Computer Inc · 1982
Page 0568 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
1:1Cl CB 1-1C2 DO 04
Lo 95
FC. FO r-w c
rD ['O FO EA
i)OD BC CS ct.! AA
AO 03
49 00
EiS 8Q
0!) Si:
o 85 95
EI) BC
10 FU
1') r'
r-r
'l' l'O Al
i (4
F219: F219
ç::? i q
F21Q
r
,IQ
F219 F219
219
-21
1''
4,383,296
35
36
547 RDASYN INY
54B
549 550
51 RDAI
552
51 PL)A'3";l 554 555
5Se RDA;:
s:-
!3NE PDAI
INC COUNT
BQ RDERR
LOA SPL
Cr11
OoL, X RDA1 *31>5
BNE RDAS'iN
NOP
L.DA
DEL cr-io
06L. X O DA.
* $ AA
.LOW ORDER OF COUNT s (2K l'IIBLS TO FIND
APR MARK. ELSE ERR) READ NIBL.
* NO PACE CROSS' AIS MARV. 1'
(LOOP IF NOT) A[)DED NII3L DELAY
'-* rio PA'E FRLJS'- « r
ADF MARK 2'
Of!!.: R DAS N
(IF MIST, 15 IT Ari;
57_)1 *
5o2 RDA:
LOY *33
INDEX FOR 4-DYTE FE.i:
(ADDED NIRL DELAY)
[IFA GOL. X
ROAS
A7)-q 140 PA.,E. CRO'CL' A.'A
ADO lARK 3
5,6 * 547
ONE Pi)ASN1
IF- NOT. IS 11 AFt
(LEAVES CARRY SET i)
L DA *30
INIT CHECKSUM
568 RDA! LO S T Ç, C SUM
':-)9 kr.
A
U-AD ODD DIT r4L!3s
NsJ PACE CPfl'Nr
PU. A STA LAST
-AL IL-14 DOL) SITS. (SAVE THEN)
o L :.ii
5 -3 RDA'
L DA 06L. X
READ 'EVEN DIT NIEL
74
P P L R DAS
*** NO PACE CROSS' *
AM) L A T
N'Er4SE ODD AHI) EVEN P
5T5,5[ DATA I3YTF
1-
'1'
C o',3r-'
S 'A
DE /
130 RDAFLD
r Av
. PorNo
LOOP ON 4 bAIA DYTES - IF FINAL CHECKSUM
o:o:LRO. THEIJ ERO!)I-
-
X
r f55 T fljT-5JP f4iD
NO PASr CRLf-S)
LIII-' #3Dt
ore: HDEFP
ERROR 1F NONMATCH
). 'CE T '), 01).'. -
s'tr' s-.'.
DELAY (NO TNTERUPTS FROM NOL (JHS
'-LCOND DIT--SLI!' NIi3[ -'- NO PACE COULIS - o.-
ROE 5 - I
AT
WE1
ONE
C LS PU-;
ir)
oi:o Pu':-:;;:
ERROR IF NONFIATCH CL.EAR CARRY ON
NORMAL READ EXITS
2
3
*
4
WRITE SUBR
*
5
(to-SECTOR FORMAT) *
O
*
7
*
WRITES DATA FROM *
NOUF1 AND r4DUF2 *
*
FIRST NOUF2.
HIGH TO LOW.
*
THEN NOUF1,
*
is
LOW TO HIGH
*
*
- - ON FNTF?, --- - *
is
*
19
X-REG SLOTNUM
*
20
TIMES $10.
*
21
*
*
ON EMT -------- *
*
CARRY SET IF ERROR. *
Apple Computer Inc · 1982
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4,383,296
37
38
F219 F219
26 *
27*
(W PR(JT VIOLATION) *
*
,-' 1
F 219
20 * IF NO L4RQR
*
,:-; *
F219
'1G
ARE,. UNCERTAiN *
F219
31 * XREG UNCHANGED *
F219
'32 *
YREG HOLDS $00 *
F219
33 *
CARR' CLEAR
*
F-2 19
"14 *
*
F219
35 * ---- ASSUMES ---- *
F-219 F21
F2 j9
*
37 * 1 USEC CYCLE TIME *
38*
*
r2 1
39 ************************
¿t A
F2 IA
. WR1TF16 SEC
'II
C: V
ANTICIPATE WPRDT RR TI) INDICATE WRITE PROTECT ERPCIF INSTEAD OF
F'2 I B si: SI) CC 42
L"A O6H
INTERUPT
F21E BD 8E CC) 43
L2A Q7L X'
SENSE WPROT FLAG
F221 30 F5
44
13M! WEXIT
BRANCH IF FlOT WRITE PROTECTED
F-223 A9 FF
F- 225 91 9F CO F 221) lIC BC CO
45 WPTI 47
LEA $3FF
SA Q:'H X
(iRA OiL. X
SYNC DATA. (5) GOTO WRITE lIUDE
,
(4)
F- 2213 AC 04
4)3
LEY *34
(2) FOP FIVE N1IXL.S
F22 D EA
49
NEW
(2)
F 22E 48
50
PHA
(4)
F22F 68
51
PLA
(3)
40
52 WSNC
14> EXACT TIMING
F 2 31
;'c SL
F A "F- WNIBL7
(3) EXACT TIMING
.
(13,9,6) WRITE NC
F235 88
55
F236 DO ES
56
DEY BNE WSYNC
(2)
(2*) MUST NOT CROSS PAGE
F236 A D5
57
F 23A 20 DC F2 58
F23D A' AA
59
LDA *3135
)R WNIDL9
1.04 *$AA
(2) 1ST DATA MAR14
- (1596) (2 2ND DATA MARR
F23F 20 DC F2 60
F242 A9 AD
al
JSR WNIBL9 LDA **AD
(159,6) (2) RP DAT,MARK.
F244 20 BC F2 62
USR WNIBL9
i (15.96)
F247 AO 55
63
LDY *355
, (2) NDUF2 INDEX
F249 EA
64
NOP
i (2 FOR TIllING
F24A EA
65
NOP
(2)
F248 EA
66
NOP
(2)
F24C DO 08
67
BNE VRYFRST i (3) BRANCH ALWAYS
F24E AD EF FF 68 WINTRPT LDA INTERUPT (4) POLL INTERUPT LINE
F251 05 813
69
ORA IMASK
, (3)
F253 EA F254 10 SD F256 :30 00
71
BPL SERVICE
72 VRYFRST BMI WRTFRST
(2)
(2) BRANCH IF INTERUPT HAS OCCURFD
(3. FOR TIMINO
i
F258 89 02 03 73 WRTFRST LOA NBUF2. Y
(4)
F2513 913 BD CO 74 F2SE 130 BC CO 75
STA 08H X LOA GÓL- ,(
(5) STORE ENCODEE' BYÏE
i
(4) TIME MUST 32 U PER i3TE
F261. 88
76
F262: 10 EA
77
F264: 98
78
DEY BPL WINTRPT IVA
,(2)
i (3) (2 IF BRANCH NOT TAKEN) 2) INSURE NO INTERUPT THIS BiTE.
F265: 30 03
79
13Ml WMIDLE
F267: AD EF FF 80 WNTRPT1 LDA INTERUPT
(3) BRANCH ALWAYS. (4) POLL INTERUPT LINE
F26A: 05 813
81 WMIDLE ORA 1MASK
, (3)
F26C; EA
82
F26D:30 02
83
F2ÓF: 10 42
84
NOP 13M! WDATA2 DPL SERVICE
i (2)
(3> BRANCH IF NO INTERUPI QO SERVICE INTERUPT.
F271: CS
55 WDATA2 INY
; (2)
F272: 139 00 02 86 F27S: 90 BD CO 87
LDA NBUF1.Y
STA G6HX
( (4'
; (5) STORE ENCODED DYTE
F278: BD 8C CO 88
F279:C0 E4
89
F270: 00 ES
90
LOA 6L X CPY **E4 !3NE WNTRPT1
( (.4)
(2) WITHIN i MS 0F COMPLETION? (3) (2) NO KEEP WRITTINQ AND POLLINO.
F27F: EA
91
NOR
(2)
F280: CB
92
INY
(2)
F281 EA
93 WDATA3 NOP
(2)
F282:EA_,,,
94
MOP
;(2)
F283: 48
95
PHA
1(4)
F284: 68
96
F285: 89 00 02 97
PLA
i (3)
LOA NBUFIY i (4) WRITE LAST OF ENCODED BYTES
Apple Computer Inc · 1982
Page 0570 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
F288 91) SD CO
FBB BD 3C CO F2BE AS 96
F290: CB F291.D0 EE
F293: F0 00 F-295 20 BD F' F298 A9 DE F29A 20 c r:;' F29D:A9 AA F29F 20 BC F F2A2 A9 ELI r:2A4 20 i)C F:
-2A7. A FF
F.2A9 20 LC F
F2AC: BD 8E CC' F2AF:BD SC CO
F282:60 F233:
F203 38 F284. 2C 54 F3 r2D7:20 AC F r2riA 58 c14L O F::IC
F1.LIC
F20C
F2LC
-PC IB
VI3D 4(3
I RI' o:
r:c5 .,O
F2C F2CÓ F2CÔ F2CO F 2C6
F2C6 F2C J-2C:ó
r .: .
ç. :r. ¿,
co 12Có
"e! C
c o
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F2C6 F2CÓ F2CO
r;:co r 2C ,
F2C.
F2C 6
F2C6
I-2C
F2CO 42 02
F2CB AO 00 F2CA: SB F2CB81 913
4A
3E 01 03
4,383,296
39
40
98
TA 06H X
(5) WITHOUT POL.L.IN. INTEFd.)PTS
LOA GOL. X
(4)
tOC
LOA C,SUM
(3) NORMALLY FOR TI-1INO
101
INY
102
UNE WDATA3
(2>
i4103
LÌEiO
WPC:kUM JR
I OS
LOA
()/
,JR
WRCKSUM
WNIF3L7 *SDE WNIBL9
(3) BRANCH ALWAYS (13,9.6) GO L.RITE CHt:c. 'M
2' DM4. BIT SLIP MAR)'
(159.6) WRITE IT
107
i:108
10?
LOA
SJSR
L.DA ,.)SR
*$AA WNIBL9
*$E13
WNIRLC?
(2) DM5. 311 SLIP MAR
(159.6) WRITE Ii.
2) 0Mo. BIT SLIP t1AP
1'.9.6) 14R1V1. IT
1)1
LOA *$FF
TURN-OFF
11k.
UP 14N1111.9
ci 9) WRITE 3
113 NOWRITE L.IDA Q7L. X
4O).)T UF WRITE MODE
114
LOA QOL. X
TO READ MODE.
115
RIS
116 *
.RETURN FROM WRITE.
117 53ER.'(CE SE)'
TREAT INTEPUPTION AS ERROR
118 119
10
lIlT
')5
BPEPY IT
CL. I
;SET VFLAQ TO INDICATE INTERUPT TA IT OUT or WRITE MOPE' COULD NOT HAVE GOT HFRE WITHOUT CLI OR
.1
RIS
102 123
t
124
7-BI r NILIL. WRITE SUBPS *
125
*
A-RE( UPE) FIIOR EXIT
CA)I1 CLEARED
*
*
129 130 WNILIL9 CLC
131 WNIE)).7 F' HA
9 CYCLES THEN WRITE 7 CYCLES THEN WRITE
.3'
r: I L:)
:TPAA 0(0OH.XX
NIUL WPITF. ¶(UE1 CLOI3OERS AC(. NUT CARE:
13b 14é *
P TS
135
139 *
e
140 * PRENIBLIZE SUBR
*
141 * (16-SECTOR FORMAT)
*
142 *
*
143
144 * 145 * CONVERTS 2b6 BYTES OF
*
*
1 4o 4
147 * 148 * 149 *
USER DATA IN (BUE)
ENCODED BYTES TO RE
INTO
**
WPITEN DIRECTLY TO DISI ENCODED CHECK SUM IN
*
*
150 * ZERO PAGE 'CRSUM' 151 *
* *
152 * ----- OF) ENTRY ---- *
I 3*
154 * HUF IS 2-HTE: POINIER
*
*
155 *
156 e
TO 256 RYTES OF USER DATA.
* *
157 *
*
I 5)3
---.- ON EXiT -- ---- *
I 59 * i 60 e
161 162
163 * 104 e
A-R (HECk SUM X-REG UNCERTAIN Y-REG HOLDS O CARRY SET.
* * *
* *
*
165
* t.4
16e. PRENIBI6 LOX *S2
START NBUF2 INDEX
167
LDY *0
START USER BUF INDEX.
168 PRENXB1 DEY
NEXT USER BYTE
169
LOA (BUF)Y
L.13R A
SHIFT TWO BITS OF
171
ROL. NOUF2- i. X . CURRENT USER D' TE
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
F201 4A F202 3E 01 03 F2D5 99 01 02 F208 E8 F-209 EU 56 F200 90 ED F200 A 00
F2DF 98
F2EO DO E8 F2E2 AO 56
EE4 59 00 03
2' 3F
F'2E9 AA
F2EABD 55 F3 F2ED 99 01 03 F2FO 139 00 03
80
),-r 4 30 EF: F 2 29 7F'
F2FS 59 Gi 02
F2FB.AA F2FC BD 55 F3
F2FF 99 00 02 F302 09 31 o:
F305: CS
F306. DO FO
F300 AA
r 3) 55 F3
r2((: 5 96
F3OE 4C 4C F3
F311
F311
F311
FJ11
F311
F311 F311
'
F-311 AO 55
F713 A9 00
l-31 PE 02 03
F118 D 00 fl
F318 99 02 03
F31E88
F31F 10 F4
F321 CC
F322 BU 00 0 p125 SD 00 F7 F328 99 00 02 F323C8
F32C DO F4 132E 46 96 F330. SD 00 F3 F733 38
F334: DO 16 F336-A2 56
F338 CA
F339 30 F13
338 09 00 02 SE 02 03
F341 24 F342: 5E 02 03. F34524 F346 91 98
F348 CR
r'349 D) ED
F348: 18
F34C
F34C:AD DF FF
)34F 09 80 (351 BD DF Fr
F354 0
4,383,296
41
42
2 1
LSR A
INTO CURRENT NBUFT
173
ROL NOUF2-1.X DYTE
174
STA NBUFI+1,Y (6 BITS LEFT)
175
INX
FROM O TO 355
CP $$5
1 7
pCc
1 'e
LL»
179
TYA
180
UNE
181
LOY
1E2 PRENIB3 EOR
103 PRENII32 AND
PPEN B I
*c
PRENIO1
*356
NBUF2-2 ' *33E
BR I F NO IJRAPARÍJUND
RESET NBJF2 IND1
USER BUF INDEX (DONE IF ZERO)
(ACCO FOR CHECK SUM)
LD INE WITH PF(EV1Ut.iS STEIP GARBAGE OIT!
1B4
TAX
TU FrJPFl RUNNING CF4FÇ UM
185
FDA NIUL X
GET ENCODED ELIIV
186
STA NIIUF2-1Y REPLACE PREVIOUS
187
LDA NI4UF2-2, Y RESTORE ACTUAL PREVIOUS
188
i 3'
2NF frENI 0 3
lUL)' UT IL. ALL UF NBUF2 I G LONVERTED
iC
Nr #3
191 PREN1B4 EDO NBUF1+1. ' NOW DO THE SAt1. r:oP
192
TAX
NIBBLE BUFFER 1
193
LOA N!DLX
TO DG ANY BAC(k TRAC(IN )NIIUF1-i)
194
STA NBUFI. '
195
IDA NOUF I + 1
PB( OVER THAT WHICH lB NOW 'PREVIOUS'
19
INY
197
BNE PREN 134
198
TAX
199
LDA NItL X
USE LAST AS CHECK SUM
200
STA CRSUM
201
,JMP SET1MC
;ALL DONE.
203
204*
*
205
POSTNIBLIZE SUBR
*
2O *
16-SECTOR F'ORNAr
*
207 *
208
209 *
210 POSTNID16 LDY *355
211
LOA #30
212 PNIPL.1 L 3 NULIF2 Y
FIRST CONVERT, i:o TNIT CHECA BUM ':.FT ENCCiDE(' O''TF
BiT NIFtLES
21'
COR DNIOL. X
214
STA NHUF2Y
REPLACE WITH 6 I4iT EGLI-
215 216 21:' 218 PtL10L-
i'
220
221 222
22:3
224 225 226 227 POSTi 22$ POST2 229 230
231
232 233 234 235 236
DEY
IIPL PNII3LI
N
OX NHUFI y' L.1R rULOL- X
GA NBUF1 Y
THY
ONE PNIBL2
LOX C(11UM
FUN DNII3L X
BNE PcJSTERR
LDX *356
DEX
0Ml POSTi LLr'. NOUFI. Y
L.OF rJ!31.,,F2. X
ROL. A
LSR NBL'F2 X
ROL A
OTA RUF) Y INI
LOOP UNTIL DOTJE WITH NI0L.r 13uFrER 2
NOW YC)
. OU THE 04(11: Id 'Ir'
. NIBBLE DiFFER I OC) ALL 256 DYTE1
MARE SURE CHE:. $UM MATCHF.13)-.TTER ((L ZERU ANT IC 104 r( EP#fl(BRANCH IF IT IS . INIT N8UF2 INDEX
NBL'F IDX 355 TO $0
. WRAPAROUND IF JE
SHIFT 2 OMS FROM * CURRENT NBUF2 N(I)L ; INTO CURRENT NI3UFI NIOL , hITE DF USER cATA . NEXT USER BYTE
237
ON). F'O!T2
238
cL:
GOOD DATA
239 POSTERO EGU
240 SET1ME LOA ENVIRON
241
URA $ONEE.G
242
LIA ENVIRON
243 5EV
OrG
'FT TO CiNE. I' 3AHEPT L1iCk RATE . (NV 119fJ) TO SET VELAG
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
4,383,296
43
44
F355 F355: F355
F? 55,
r355:
F355 F355'
r 355
F355
245 **************************
246*
*
24: * 6-BIT IO 7-BIT
*
24G * NIEL CONVERSION TABLE *
225409********************3********
251 *
*
* CODES WITH MORE THAN *
253 * ONE PAIR OF ADJACENT *
254 * ZEROES OR WITh NO *
r
255 * ADJACENT ONES (EXCEPT *
F355:
ç: 355:
256
257 *
137) ARE EXCLUDED. * *
F5 F355
258
C,?6 97 9A ;i5q NIrn.
DFI3 $96,$97$9A
F358: 913 90 9E 260
DFB $913, $9D 59E
F- 351-L 9F A6 A7 261
DFI3 $9F, $A6, $A7
F3SE: A13 AC AI) 262
DFB $A13, $AC SAI)
F361 : AE AF 132 263 F264: 133 134 135 264
137 139 265
DFL3 $AE,$AF,$132
DFI3 $I33$B4.$B5
DFB $I36,$B7,$1)
FÔA. 13A BL) EC
DFI) SEA, $1313, EC
F341): ED BE 13F 267
DFB $BDJ$13E1$EF
F370: C13 CD CE 268
DFI) $C13.$CD$CE
F373: CF 1)3 1)6 269 F?Th' 1)7 1)9 DA 270
DF2 $CF, $D3. 51)6
DFL3 $D7,5D9$DA
F379 DB DC [)[.' 271
DFI3 5DB, $DC $DD
F:7C. DE .)r L..- "c_.7i__) r:31: E E7 E9 273
DFI) SDE, $DF, $E5
DFI3 $E6, $E7 $E9
F382 EA EF1 EC 274
DFR SEA, $E13, SEC
F385: EI.' EE EF 275
F388: F2 F3 F4 276
DFI3 SED, SEE, $EF
DFB sF2, SF3, SF4
F?Efl: F5 F6 F7 277
DFB SF5, SF6. SF7
F3EE. F9 FA FE 278
DFI? SF9, SFA, 5FB
F391 FC FI,) FE 279
0FB SEC, $FD SEE
F394: FF F395. F395:
f: Q 5
280
DFB 5FF
282 **************************
283 *
*
284 *
7-BIT TO 6-BIT
*
F395. F395: F395
F?-' 5
ç'-'. L: *
2
1*
287 *
28Es *
22809i*'
DENIDLILF' TAEL *
6-3ECTOR rORMAn *
*
VALID CODES
*
$Q6 TO 5FF ONLY.
*
3Q1 *
* ' 1)E WITH MOPE tH4.N
F395
293 * ONE PAIR OF ADJACENT *
F395: F395.
294 * ZEROES OR WITH NO * 295 * ADJACENT ONES (EXCEFT *
29é- * ¡BIT 7) ARE EXCLUDED 4
F 3 95
29
F395 00
2B
B Pik
ONE I3YE r LEF T 'OVEI"
F300.
299 DNII3L EQU REGRWTS+$300
F396' 00 01 .8 300
DFB $00,501.598
F399 99 02 03 301
DFB $99, $02. $03
Apple Computer Inc · 1982
Page 0573 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
F39C9C 04 05 F39F 06 AO Al F4A2 A2 A3 A4 F3ASA507 08
F3AB A8 A9 AA
F3A13.09 OA 013
F3AE OC OD t' EThI 91 0E 0E F31r4 10 11 12
F397: 13 88 14
F3EA: 15 16 1
3i3D 18 19 lA rí co ci c -JC3 C3 (.4 C
: 7 Ç3 F3C9C9 CA 113 F3CC CC 1C ID F3CF: lE DO Dl F3D2 D2 iF D4
3D5 D5 2') 21 F3DF3D8 22 23 F3DB:24 25 2& F3DE 27 28 EQ F3EI:E1 E2 E3
3E4 E4 29 2A
FJE! 213 EB 2C
F-'3EA 2D 2E 2F
F3ED:30 31 32 F3FO. FO Fi 33 FIF'3 34 35 36
'3F.J 3/ 3c5 Fti
F3F-? 39 3A 313
F3FC. BC 3!) 3E.
F3FF: 3F
F400. F400: F400: F400: F400: F400: F400:
F400:
F400:
F400: F400:
F400: F400: F400: F400: F400: F400:
F400: F400:
F400: F400: F400: F400: F400: F400: F400:
4,383,296 45
302
DFI3 $CiC,$04,$C5
303
DFt3 $06g $AO $A1
304
DFB 3A2 $A3. t.A4
30
0FB sAS, $07, $08
306
0FB $A8, $A9, $AA
307
0FB $09, $0A $013
0F3 $OC $OD $130
3 r
l)FB $L1 50E. $0F
310
¡'F13 $1(111 $12
311
DFI3 513,5138,514
:i 12
L)F9 $i5$16,$17
J 13
0FB $1B.$19$A
4
1.F
c.:. ::i
'-'I C
F13 5C.3 5(4, 3'3
13 ¶LC6.C7 $:'
317
DFI3 $C9, SCA, $113
318
L)F13 $CC,$1C$1D
319
DFI3 $1E,$D0$D1
LFJ3 $02. $1F. $04
'321
Dr3 $D5. $2O 121
322
DF
$D!3 $22r $23
323
DFD $24f $25k $26
324
DFL $27. $28 $E0
325
DFI3 $F1.$E2$E3
Q3 $L4. $29. $2A
'327
)FI3 $213.$ES.$2
T)FT3 $20 $2E. '-
329
DFB $30. $31 $32
330
0F13 $F0 $F1 $33
3.31
DFI3 $34.. $35, $26
-jj $37. $3g. %
323
3V!) $39 $3A. $
334
0FR $3(, $3D. $2E
335
DFJ3 $3F
337 *************************
338*
*
339 * FAST SEER SUBROUTINE *
340*
*
341 *************************
342*
*
343 * ---- ON ENTRY ---- *
344*
*
345 * X-REG HOLDS SLOTNUM *
346 *
347*
348 * 349 * 350 *
351*
352 * 353 * 354 * 355 * 356 * 357 * 355 * 359 * 360 * 361 * 362 *
lIMES $10.
*
*
A-REG HOLDS DESIRED *
HALFTRACR.
*
(SINGLE PHASE) *
*
CURTRR HOLDS CURRENT *
HALFTRACR.
*
*
ON EXIT
*
*
A-REG UNCERTAiN.
*
Y--REG UNCERTAIN.
*
X-REG UNDISTURBED.
*
*
CURTRR AND TRKN HOLD *
FINAL HALFTRACK. *
Apple Computer Inc · 1982
Page 0574 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
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373 * FOR MOTOR ON TIME *
374 *
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*
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376 * ---- VAR IAI3LES USED --- *
377*
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379 * PRIOR SLOTTEMP
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Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
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Apple Computer Inc · 1982
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51
52
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TIME WAS VALID ,HI BYTE CHANGED
,** SUCCESSFUL ASSEMDLY ND ERRORS
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
4,383,296
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54
FOET9 ALDONE t
EDITO AL.1.00NE
F119 AL1OFF
F AA 13 ANL DG i
F1 213 C HK DR V
F050 CON WA I T
97 0551V
.'F479 BLOCK W
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97 CSUMI
913 130F 98 CKSUM ?FODF CORREO TVOL
89 CSUM
F300 DNII3L
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52 1I)DR'N 81 II3SLOT
F31 II3WPER
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85 113'3UFP 80 IBNODRV
89 II3SMOD 813 IMASK 95 LAST 99 MONTIMEL
MOT 0k F45' MSWA .1 T
F355 N IB L F2AC MOHR I TE
CDB NOTORDI F105 N1Y.3EEF ?FOéDO NODRIVERR F1113 NXOFF
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130 ONE MEG
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F217 RDEXIT 93 RETRYCNT
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F2133 SERVICE
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FF139 TINER1H 95 TRfSCNT
F088 TRYADR2
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F0&.5 TRYTPK F2'.'l WDA1A2
7F TWOMEG F281 WDATA3
WI NT R P T
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7F223 WRIl
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80 HRDERRS
Bi I DSLOT IDERR
85 LIIBUFP
Bi II3WPER
83 I13TRV 87 IBCMD
82 ICPERR 84 IBSECT 88 II3STAT
09 IBSMOD
93 R E TR YC NT
95 COUNT 97 TEMP 99 TRACK
913 F'R IOR
0200 NI3UF i
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0302 N13UF2
813 IMASK
95 LAST 97 CSSTV 99 MONTIMEL
9A VOLUME
9F ENVTEMP
C066 .JOYRDY
COBO P HA SE OFF 0089 MOTOR ON
'0001 PHASON
COBA DRVOEN
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FOA7 RDRIGHT FOE0 ALLDONE FOF3 NOINTR2 ?F116 GOSEER
F1213 CHKDRV
F01313 RTTRK
FOES DRVERR FOF9 WRIT
F119 ALLOFF F12D CHKDRVI
'F4A8 ANALOG F1213 CHKDRV1 F44A CLRPNASE
95 COUNT BC CURTRK 85 DRVOTRK F0313 DRVWAIT
T'FOAO GOCAL1
F1I3A GOSERV 87 II3CMD
T' 83 II3RERR 88 II3STAT
FFEF INTERUPT F425 MAXTST FO4E MOTOF F461 MSW2 0302 NI3UF2 FOF3 NOINTR2 F044 OR COBO PHASEOFF F315 PNII3LI F34C POSTERR ?F2E7 PRENII32 CÓBD 06H F4913 QUIT
F1813 R134
FiAS RD7
F11313 RDA3
F2OE RDA7 FIC1 RDASYN FOA7 RDRIGHT F152 PSYNCI
98 SECT F400 SEEK F34C SET1MEG F4213 STEP2 FF138 TIMER1L
9E TRKN FO7F TRYADR
.A VOLUME F2113 WEXIT
F21313 WNII3L7
F219 WRITE16 F230 WSYNC
BO ONEMEG
82 II3DRVN 85 DRVOTRK 89 CSUM
BC CURTRK 95 TRKCNT 97 CSUM1
99 TRRNI 98 BOF
EO DVMOT 'C080 PHSOFF
COBB MOTOROFF COBC 06L F000 REGRWTS FO4E MOTOF F0713 TRYTRR2
?FOAO GOCAL1 ?FOBF CORRECTVOL
FOEB HNDLERR F105 MYSEEK
FilS NXOFF
F1313 CKDRTS
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
FI3E ORVINEiX F152 RSYNC1 FI7D ROS FiAS RD7
F1131) RDADR1
F102 RDA2 riF2 ROAS F218 (JEXIT F24E WINTRPT F2ÓA WMIDLE
F2AC NIJI4RITE
F2J3F WNII3L ?F2EJ PRENIJ32
F315 PNII3L1 F34C POBTERR F400 SEER F425 MAXTST F446 BETPHASE
F456 M13J1
'F479 DLOCI0
7F4AE3 AN4LDG FF09 TII'1LATCH
0.10
0000
4,383,296
55
56
F148 READ16
F14A RSYNC
F157 RD2
F162 RD3
FI7E RD5A
F192 RDÓ
F1AF ROS
F108 RDERR
F1C1 RDASYN
F1C8 RDA1
F1DD RDA3
FiES RDAFLD
F204 RDAÔ
F2OE RDA7
F219 WRITE16
?F223 WRT1
F256 VRYFRST
F258 WRTFRST
F271 WDATA2
F281 WDATA3
F263 SERVICE
F2BC WNIDL9
F2CÓ PRENID15
F2CA PRENII31
F2FS PRENII34
F300 DNIDL
F322 PNII3L2
F336 POSTI
F34C SET 1MEO
F354 5EV
F4OA SEEK2
F410 OUT
?F429 STEP
F420 STEP2
F44A CLRPHASE
?F455 SEEKRTS
F461 MSW2
F467 ONTAI3LE
F47E TRIkSEC
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F4A13 ANLOG1
F4C4 G000TIME
FF09 TIMER1H
FFDF ENVIRON
7
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F140 ROl
F1613 RD4
F190 RDCKSUM
F1I3A GOSERV
FiCO RDASN1 FlEA RDA4 F217 RDEXIT
F230 WSYNC F267 WNTRPT1 F295 WRCSUM
F2130 WNIBL7 F2E4 PRENIB3 F311 POSTNIB1Ó F338 POST2
F355 NIOL F41F MINTST
F444 SEE$SEND F456 MSi'JAIT F470 OFFTAJ3LE
F4AO SECTAI3L FF08 TIMER1L FFEF INTERUPT
0000 0000. 0000:
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Apple Computer Inc · 1982
Page 0579 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
4,383,296
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58
F F ) 2.
FFD3. FEtO:
4ó 5Y502 47 YSD3
48 SYSEO
tFFD2 SFFD3 EECiU sEFFO
FFEF.
49 BNKSW EGLI $FFEF
FFE2
50 SYSE2 LOU SFFE2
FFE3:
Si SYSE3 EGLI $FFE3
F025:
52 COOT EGO $FC25
Fi)07:
FL'F.
53 CFWUTI EGLI SF007 54 kEVIN EGLI %FDOF
F BC 7:
55 SETCVH EGO $FBC7
F099:
56 CLDSTRT EGLI SF098
F090:
57 SETUP EGLI SF090
F901 0000.
58 MONITOR EGLi SF901
59*
NEXT OBJECT FILE NAME IS DIAG. ODJ
F4C5: F4CS:0O 131 132
60
ORG 5F4C5
61 RAMTBL DFI3 $O,SB1$82,$BA,189.S10,S0113
FACS: DA 89 lo
F4CB:00 13
F4CD:
62 CHPG
EQU *
F4CD: 52 41 CD 63
DCI 'RAM'
F400: 52 4F CD 64
DCI 'ROM'
F403: 56 49 CI F406: 41 43 49 66
DCI
'IA'
DCI 'ACiA'
F4D9: Cl
FADA: 41 2F C4 67
DCI 'AID'
F40044 49 41 68
DCI 'DIA;C4OSTIC'
F4EO: 47 4E 4F
F.E3: 53 54 49
F4EÓ: C3
F4E7: SA DO
DCI 'lE
F4E9: 52 45 54 70
DCI 'RETRY'
F4EC:52 D9
F4EE:
71 *
F4EE: F4EE:
72 * SETUP SYSTEM
73*
FAEE:
F4EE;A9 53 F4FO: BD DF EF F4F3:A2 00 F4FS:8E E0 EF
74 * 75 76 77 78
LDA *152+ROM TURN OFF SCREEN. SET 2MHZ SPEED
STA SYSD1
AND RUN OFF ROM
LDX *100
5tT DAMS SWITCH TO ZERO
STX SYSEG
F4FS:BE EF FF 79 F4FD:BE DO EF 50
STX BNKSLJ SIX ZPREG
AND SET ZERO PAGE SAME
F4FE: CA
81
F4FF:8E D2 EF 82
F502: 8E 03 Fr 83
DEX STX SYSD2 STX SYSD3
PROGRAM DDR'S
9A
84
TXS
ES
F507:A9 0F
86
I N X
LDA flor
F509; BD E3 PF 87
F5OC:A9 3F
98
PSOE; BD E2 FE 89
STA SYSE3 LDA $13F STA SYSE2
F'lt:A0 06
90
LDY *106
F513: 39 DO CO 91 DiSKI LOA DISKOFF. Y
88
DEY
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F524: F524: F524:
93
DEY
94
BPL DISK1
95
LDA KEYBD
96
AND $$04
97
liNE NXBYT
9e
99*
ri RECON
100 * VERIFY ZERO PAGE
101 *
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
F524. A9 01 F526: 95 00 F525 L'S 00 F52A: DO FE FS2C. OA F520: DO F7 FS2F. ES F530 DO F2
F532: F532: BA F533 48 F534. E8 F535: DO FB F537: CA F538: 86 18 F53A: 68
F53B:C5 18 F53D: DO ED F53F:C6 18 F541:DO F7
F543: 68 F544: DO E4 F546: F546: F546:
F546:A2 OB F548: 95 10
F54A: CA F54D: 10 F13 F54D: F540: A2 02
F54F:86 19 F551:A9 00 F553: AO FF F555:91 18 F557: Dl 18 F559: FO 07 F558: 20 48 F7 F55E:94 10 F56O:A6 19
F562: EB
F563:E0 CO F565: DO E8 F567:A2 20 F569:EE EF FF F5ÓC:AD EF FF FSÓF:29 OF F571'C9 03 F573: DO DA
F575: F575: F575: 20 90 FD
F578:A2 00 FS7A: 8E E0 FF
F570: CA
F57E:BE D2 FF F581:BE D3 FF F584:A9 3F F586: GD E2 FF F589:A9 OF F588:BD E3 FF F5BE:A2 10 F590: 20 38 F7 F593:A2 00 F595: 86 SD F597:A9 04
4,383,296
59
60
102 NXL'YT 103 NXBIT 104 105 NOG000 106
107 108 109
LOA STA
CMP
SNE ASL BNE INX BNE
*$O1
ZRPG. X ZRPG, X
N00000
A
NXDIT
NXBYT
ROTATE A i THROUGH EACH BIT IN THE O FG TO COMPLETELY TEST THE PAGE. HANG IF N0000L; TRY NEXT BIT OF EYTE UNTIL BYTE IS ZERO.
CONTINUE UNTIL PAGE IS DONE.
110 *
111 CNTWR 112 113 114
TXA PHA INX SNE CNTWR
PUSH A DIFFERENT BYTE ONTO THE STACK UNTIL ALL STCK BYTES ARE FULL.
115
DE X
THEN PULL THEM
116
STX PTRLO
117 PULET PLA
OFF AND COMPARE TO THE COUNTER GOING
118
CMP PTRLO
BACKWARDS. HANG IF
119
BNE N0000D
THEY DON'T AGREE.
120
DEC PTRLO
GET NEXT COUNTER BYTE
121
BNE PULUT
CONTINUE UNTIL STACK
122
PLA
IS DONE. TEST LAST BYTE
123
BNE N00000 AGAINST ZERO.
124 *
125 * SIZE THE MEMORY
126 *
127
LDX *$08
ZERO THE BYTES USED TO DISPLAY
128 NOMEM STA ZRPG1. X THE DAD RAM LOCATIONS
129
DEX
EACH BYTE A CAS LINE
130 131 *
BPL NOMEI9
ON THE SARA BOARD.
132
LDX *$02
STARTING AT PAGE 2
133 NMEM1 STX PTRHI
TEST THE LAST BYTE
134
LDA *$00
IN EACH HEM PAGE TO
135
LDY *SFF
SEE IF THE CHIPS ARE
136
STA (PTRLO).Y THERE. (AVOID O & STK PAGES)
137
ClIP (PTRLO),Y CAN THE BYTE BE O'D?
138
BEG NMEM2
139
SJSR RAM
NO. FIND WHICH CAS IT IS.
140
STY ZRPG1X SET CORRES. BYTE TO FF
141
LDX PTRHI
RESTORE X REGISTER
142 NMEM2 INX
AND INCREMENT TO NEXT
143
CPX *SCO
PAGE UNTIL I/O IS REACHED.
144
L3NE NMEMI
145
LOX *$20
THEN RESET TO PAGE 20
146
INC BNKSW
AND QOTO NEXT BANK TO
147
LDA I3NKSW
CONTINUE. (MASK INPUTS
148
AND *$OF
FROM BANKSWTTCH TO SEE
149
CMP *$03
WHAT SWITCH IS SET TO)
150
BNE NMEM1
CONTINUE UNTIL DANK '3'
151 *
152 * SETUP SCREEN
153 ERRLP )SR SETUP
CALL SCRM SETUP ROUTINE
154
LDX *$OO
SETUP I/O AGAIN
155
STX SYSEO
FOR VIA TEST
156
DEX
PROGRAM DATA DIR
157
STX SYSD2
REGISTERS
158
STX SYSD3
159
LDA *$3F
loo
STA SVSE2
161
LDA *SOF
162
STA SYSE3
163
LDX *S10
HEADING OF 'DIAGNSTICS' WITH
164
iSR STR NT
THIS SUBROUTINE
165 ERRLP1 LOX *$0O
PRINT 'RAM'
166
STX CV
SET CURSOR TO 2ND LINE
167
LDA *$O4
SPACE CURSOR OUT 3
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
F5 20 C7 F!
1F55CFAa20037e
F5AI' F5A1:B5 10 F5A3 AO 08 F5A OA FSA6 48 F5A7 A9 4E F5A9 90 02
F5413 49 31
F5AD 20 25 FC
F5130 68
F5131 88 F5132 DO rl
F5134 20 07 F5
F-513? CA F598 10 E7 F534: F5BA F5 lIA F5134 9A F-51313 SC EF FF
F513E 98 F-513F GD DO FE F5C2 85 PF
Fr3:Ci 49C8B
r s: -. 4)3
FSC7 68 F5CO CB F5CQ CO 20
F5:Ú 0') FI
SC-i' 4') 00
5' OC DO F F5132 86 18
F5DA EB
F3135 96 19
F50? 84
F5113 11 18
r'5C-A D') 06 F5DC E0 1F F5DE DO F4
r5EC' F0 05
F SF2
F2 42 lA
'SL4 :o 713 F'
F SF7 F5E 7 FSE7
('SF" 49 00 ESE-' 48
V5EA 42 F0 FSEC 85 18
FSEEGá 19 FSFO A2 FF
R'44
FOF6: DO 06
F5 LÇÇ._
FSFA:DO 02 F5FC:AO EF
F5FE: CB
F5FF:DO Fi FóO1:E6 19
F603: DO ED
F605: AB
F606: FO 05
F608:A2 03 F6OA:20 70 F7
FÓOD:
4,383,296
61
62
168 16 170 171 RAFIWT1
JSR SETCVH
)SR STRUT
LDX *S07
EGU *
(X STILLO ON RETURN)
THE
SU!ROUTXNE
FOR 8Y1ES 7 - O IN
172
LOA ZRPG1.
173
LDY O8
174 RAMWT2 ASL A
OUT EACH BIT AS A
OR '1' FOR' INDICATE BAD OR MISSING
CHIPS SUDROUT1NE 'RAM'
RAM
175
PHA
SETS UP THESE BYTES
176
LOA *SAE
LOAD A ' ' TO ACC
177
13CC RAMWT4
I 'B
LOA #%31
LOAD A '1' TO ACC
I 7 RAMWT4 ,JSR COOT
AND PRINT IT
180
PLA
RESTORE DYTE
181
DEY
AND ROTATE ALL B
I S
lINE RAMWTO
1 F3.)
JSR CROUT1
CLEAR TO END OF LINE
1 84
DE
185
jIPI. RAMWT1
186 *
187 * ZPG5ST TEST
1813
189
I QQ
TXS STY 13NI"Si'
191 ZP1 192 193 194 195
TYA STA .5TA INY TYA
ZPREG
STKO
î "-
P HA
197
P LA
198
I N 'r
199
CP'r *$20
35F L
LD $$'i'
¿4REG
203 2o4 ZP2 203
2)5
ST PTRLO INX STX PTRHI
CTXA''"_:»'
ONE 7P3
20
CPX *$1F
21:'
LINE ZP2
211
212 ZP'I
233
21'
8ES
EQ'.
LDI
SP
ROMTST
*
$S1A
3IESSEAR
CHIP IS THERE BAD zECNO 414; SO PPINT 'ZP' MESSAGE' S SET FLAC (2MHZ MODE)
215
216 * ROI TEST ROUTINE
r.r 217 *
-:18 RoIl
LOA sit)»)
¿19
TAY
SET POINTERS TO
tF000
220
rx sii-:
221
STA PTRLO
""2
STX PTRHI
SET X TO $FF
223
LOX *$FF
FOR WINDOWING I/O
224 RrJMT'-Yrl EDIl )PTRLO). COMPUTE CHKSUM ON
225
CPr PTRH)
EACH ROM BYTE
226
ONE R0NT812 WINDOW OUT
27
CPY *IF _ANES FFCOrFEF
220
ONE ROPITST2
229
LDY *$EF
230 ROMTST2 IN?
231
ONE ROMTST 1
232
INC PTRH!
233
ONE ROMTST i
234
TA?
TEST ACC. FOR O
235
BEG VIATST
YES, NEXT TEST
236
LDX *S03
PRINT 'ROM' AND
237
%JSR MESSERR SET ERROR
238 *
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
F6OD:
F6OD.
F600: 18
FÓOE: DB
F6OF:AD EO EF
F612: 29 3F
F614:
18
F6AD EF FF
Fo19.29 4F
F61D65 16
F6ID-60 DO FF
F62085 18
F622: AD DF FE
F625 29 5F
F62765 18
F629 6D D2Fr
F62C 6D D3 FF
Ff. 60 E2 FF
F632 éD E3 FF
F5T:' C9 El
ç:c f-6: -O 05 A2 Qé
F61?L 20 713 F7
F3E
.2E:
113
F63F AQ Q1 F641:2D Fi CO F644: éD F2 CO F647: 60 F3 CO
1-64A.C9 10 F/-4CFO 05 F&,4E A2 09 Fé50: 20 713 F7
F653:
F653:
F653
"53 A9 CO
BI) DC F
F58.AD SA CO r45flAD SE CO FcE.AD SC CO
-1 AO Ö
F663: 88 F664 DO FD F666: AD 50 CO
F66'? CR
ro6A ro OA F,6C AD 66
F6ÓF' 30 F8 F671 98 F672 29 EQ F674 FO 05 F67 F6 A2 OD F678 20 7B r-7
F6713 F6713
67B AD 08 CO F6E, OA
4,383,296
63
64
239 * VIA TEST ROUTI
240 *
241 VIATST CLC
SET UP FOR ADDING BYTES
242
CLD
243
LDA SYSEO
MASK OFF INPUT BITS
244
AND $3F
AND STORE BYTE IN
245
STA PTRLO
TEMPOR. LOCATION
246
LOA 2NKSW
MASK OFF INPUT BITS
247
AND #$4F
AND ADD TO STORED
248
ADC PTRLO
BYTE IN TEMP. LOC.
249
ADC ZPREG
ADD REMAINING
250
STA PTRLO
REGISTERS OF THE
21
LDA SYSD1
VIA'S
252
AND *$SF
(MASK THIS ONE)
253
ADC PTRLO
AND TEST
254
ADC SY.5D2
TO SEE
255
ADC SYSD3
IF THEY AGREE
256
ADC SYSE2
WITH THE RESET
257
ADC SYSE3
CONDITION.
25
CMP #*EO+ROM El?
259
REO ACIA
YES. NEXT TEST
260
LL)X *$06
NO. PRINT 'VIA' MESS
261
JSR MESSERR
262 *
23 * ACtA TEST ROUTINE
264 *
AND SET ERROR FLAC
265 ACtA
SETUP FOR ADDITION
266
.DA #$9F
MASK INPUT BITS
267
AND ACIAST FROM STATUS REG
268
ADC ACIACM AND ADD DEFAULT STATES
269
ADC ACIACN OF CONTROL AND COMMND
270
CMP *$10
REGS. =1O'
271
flEO ATD
YES, NEXr TEST
72
LDX *%09
NO ACIA' MESEAQE ANt'
273
JSR rIESSERR
274 *
275 * A/D TEST ROUTINE
276 *
THEN SET ERROR FLAQ
277 ATE
LDA *$C0
278
STA $FFDC
279
LOA PDLEN+2
280
LDA PDLEN±6
281
LOA PDLEN4
282
LDY *S20
283 ADCTST1 DEY
WAIT FOR 40 USEC
284
8NE ADCTST1
285
LDA PDLEN+5
2P6 ADCTST3 TN
91
0E ADCERR
250
LOA AD ro
289
DM1 ADCTST3
290
TYA
291
AND $SEO
292
293
IEQ
AD(FRR EU
*'-EYPLUQ
294
L). 0D
295
296 *
USR rIESSERR
SET A/D RAMP COUNT FOR CONVERSION : 255ERROR 1F DIT 7 =1
YES. CONTINUE NO. MOVE COUNT TO ACC ACC<327
NO,
PRINT 'A/O' MESS AND SET ERROR FLAC
297 * KEYBOAD PLUGIN TEST
298 *
2''9 EYPLUG L rA IKEiBD
IS $'.Y'3D PLUOGED JN
ASL A
IS LIGHT CURRENT
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
F67F lo 41 F081 AD DF FF F084 10 03
58 4C 93 F.
F89
F689: F689 F689. A9 77 F688 80 DF FL
ó8E 20 X9 F F6'1 49 10 F693:2D oe co F696 DO 09 F698. 2C io co F6913 AD 50 CC F-E 20 01 F?
FoAl 42 01
F043 86 87
F645. CA
F646 86 85 FOAO A9 AQ
B
F,A: 4A
FÓAD 95 91 FOAF 84 F680 20 79 F4
F5133 'O (DA A 1C
F,j47 ;ù 39 F,'
F6134 20 0F F0 FOOD BO E2 F6B AC 00 AO
4,383,296
65
66
301
BeL SEX
302
LOA SYSD1
303
BPL RECON
304
iMP EPRLPI
305 *
3C * fECLNFI(,UfE BSTEM
307 *
PRESENT7) NO BRANCH IS ERROR FLAG SET7 12MHZ MODE) NO BPANCF4 ERFOP. HANG
308 RECON EGU *
309
LDA $S77
TURN ON SCREEN
3iD
STA SYSD1
311
.i5 CLOSTRI INITIAI.ILE MONITOR AND DEFAULT CHARACTER
312
L0 #$10
TEOT FOR APPLE t"
SET
313 314 315
:i31fr.
318 fl)T
AND EYBD lINE BOOT
f311 4BDSTR13
IDA GRMD 'SP MflNITOP lUX *1
NO DO REGULAR BOOT CLEAR EYNOARD
AND NEVER COME. BACk. PEA!) BL0C O
'319
SIX IBCMD
320
DEX
321
SIX IBBUFP
INTO RAM AT $A000
:3327i
LDA #$A0
CTA Ir3BUFP+i
:324
L'R A
F014 TRACk BO
:325
STA PREVTRR MAkE IT RECALIBRATE TOO
326
1X4
327
JSR 8LOC1O
:33
(3(C flUsUflT
IF (4E VE SUCCEEDED. DO LT UP
LU' $$1(
3:3C
;? CTFtT
'RETR
331
JSR (EYIN
332
13CC 13001
333 '0J3001 .)MP $4000
GO TO IT FOOL.
r
z
9VSTFM L
37 *
FoC2 AC 7F
FC4 98
337 SEX
L.DV
338 SEXI
IVA
F-OCS 29 FE
339
AND
FOC7 49 4E
340
EOR
F6(Q FC 03
341
BEO
FÓCI:B9 00 CO 342
FÔCE: 99
343 X2
: iPfR
*$7F
$$FE *$4E SEX2
LDA D(Y
TR YFR 0M
7F TO O
ADD.
4EOR4F?
YES SkP
(Y$D4 Y
N0 CDNT NXT Afl9
FÓCF:DO F3
344
F6DIAD 51 CO 345
BNE SE Xl LDA TXTMD
SET TXT
FáD4:I39QÇ1
F6D7:B9 00 C2 FÓDA: B9 oo C3
F6DD: 81. 00 .4
FÓEO:AD FF CF
346_$X3 ..__LP
341
LDA
348
LDA
3.4! . _..
350
LDA
9LL1Y...EXERCS__
. -
SLT21 Y
ALL
SLT3 Y SLOTS
EXPROM
.
.
.- - -
DISADLE EXPANSION ROM AREA
FÓE3: CB
351
I NY
F6E4: DO EE
352
ONE SEX3
F6EÓ:
353 *
F6EÓ:
354 * RAM TEST ROUTINE
FÓEÓ:
355 *
F6EÓ;A9 73
356 USRENTRY LDA **72+ROM
F6E8:SD DF FF 357
STA SYSD1
FÓEB:A9 18
358
LOA $S18
FÓED:8D DO FF 359
STA ZPREQ
FÓFO:A9 00
360
LDA *$OO
F6F2:A2 07
361
LOX *107
F6F4:95 lo
362 RAMTSTO STA ZRPO1. X
FÓFÒ: CA
363
DEX
F6F7: 10 F8
364
BPL RAMTSTO
FÓF9: 20 84 F7 365
JSR RAMSET
FÓFC: 08
366
PHP
F6FD:20 F7 Fi 367 RAMTST1 JSR RAMUT
F700: 20 F7 F7 368
JSR RAMWT
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
28 6A 08 20 Al F7 F709: DO F2 F7013:20 84 F7
F7OE08
F7OF20 F13 F7
F712: 48
F713:A9 00
F71591 18
F717 68
F71828
F719 ÓA F71A:08 F7113 20 Al F7 F71E DO EF F720 F720 P720 F720 AQ 00 F722 BD EF FF F725 BD DO FF
1I'aA2 07
Lfl 10 18
F2L) p' lO
F72F CA F730 10 F8 F732. 20 7E F7 E'35 AC 75 F5
P 738
F738 F738
1 ».3
f :)3
4,383,296
67
68
369
PLP
370
ROR A
371
PHP
372
JSR PTRINC
373
BNE RAMTST1
374
,JSR RAMSET
375
PHP
37 RAMTST4 JSR
377
PHA
378
LDA
379
STA
380
PLA
RAMRD
**00
(PTRLO)Y
381
PLP
382
ROR A
383
PRP
-
384
USR PTRINC
385 386 *
ßNE RAMTST4
387 * RETURN TO START
388 * 389
LDA*$0O
390
STA BNKSW
391
STA Z
392
LDX
O7
393 RAMTST6 LDA PHPX
394
STA ZRPG1JX
395
DEX
396
BPL RAMTSTÓ
97
J8 ERO
398
UMP ERRLP
399 ******************************
400 * SARA TEST SU13ROUTINES
401 ***.*************************
402 *
40T * irIfl1T INE -IR i N') 4W I TE
F7E1 DI) L F4
r7:3u 4f3
[)
I
'L -43 10 F'45 4' 07 FO
/48
1-749
1- '48: 48 F749 BA F74A 4A
F74:4A
f-74C 4A
!4fl 4A
IF- 64E4)A8
F750 28
F'Sl:AA
r- -m:. 1II)
-
405 STRWT LDA CHP(, X
4O
PHA
407
ORA *$8O
4(
JSR 0U1.
INX
1t)
PLA
411
I3PL TFsT
412
)MP CROUT1
413 *
414 '
IffjI: j-f-
AM
415
41e. AM
f-
417
TXA
418
LR A
419
LS1 A
420
421
LI
422
í-H
423
LSR A
424
PLP
425
TAX
42
. LA AM1L3L
NORMAL VIDEO PRNT
NXT CHR
CLP TO END OF LINE
SV ACO
CONVT
ADD TO USE FOR 8 ENÏF''
LOOKUP
Ir
Apple Computer Inc · 1982
Page 0585 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
FF5- lñ 14 69
F758 Al) EF- FF A2
F7513 29 CF
43(
F7t3L) AA
4131
- ';: EC
..ci F.: i.?
- :-
' AA
43'-
H764 AA
43&
:7d,3 AA
43
,.,-:
6t DC .
7:")7rJçF),C-.A' :'
T
29 0:'
7H AA 68
44 k'
44
44 34,,
'
-
44,
44: RAMI
44's
44"
4,383,296
r-[ r-,rc
í-H
LDA i3iSJ AND *OF
TA
L
L5f
. SR
1R
1 --_,)
,.r-:I
A
A A
L.
.1
-
1-Arli
t.; A1i,Ö
-
:- :
*' . ir t
:r
A'
LA
70 :0 C-ET WHF H
SET PROPER
RAM CON.F-
TO VAL
GA!4SN
-I-,
7I 20
i-
-!7L A9 F3
F? 680E CÍ Fi-
F784
F784
F184.
F7R4 A;: o i
L
]A
V783 AO 00
F/8A A9 AA
FSC .38
cr. -i
'r oc-'
A IA
F75t 09 80
F3 80 1Q 14 9A9 02
i 3' I
'-A A? OC
:
1
F7QE 28
F- 'F 68
FAO.6t)
r- 'Al
F7At 48
:..
.
.
_4
Çti s'.í T.T .Nï
4Y EFF:- LL:4 *r2+POM
45,
---TA -'D1
45 458
*
I-,
459 * SUDROUTINE RAMSET
460 *
4''4E RA1F F LI *toi 'JT. ;r
46:3
464 465
446/ FAML
LDV $00 LOA *$AA
SEC PHA
4-& 469
L FI-7- 3IW
ORA #$80
470
ETA IDN
471
LOA #02
A
cT, PTRHI
4'-
I D' #0O
.j74
FTPL0
475 476
477
478 * 4/ 480 *
PLY PL A
RS
1 NL P INC
481 PTRINC PHA
FR'lr MF:.-.;E i-
OET MH rIO
Apple Computer Inc · 1982
Page 0586 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
j 'v. Q3 91
: t'V..4 0G cu
ri V. tV t t
-v. -
i -.
.
. ç.
:J:-
O.I
t r
'?C
.-. '-: i /
i-.
-- '-n
3
.1
:. :J
.
--.
-
.,
-j :. c'i î L-
IL 8t'
E8
t'bt
-Eft
. t'
3E1.i
i
t I
Et':.-'.--i
- .-j :r-
'11d i
., ç,
96Z'E8't'
)N[ O'ThLLd
N(I
L3
c».1
d t] T
'
-
'I Hd I
4I ss cl
'.)]I Id .DN
.-i: ...tss
-»
:
i
I
L
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9
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t
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ci _1
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ddlVr'd
rit,ji
WV
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Apple Computer Inc · 1982
Page 0587 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
: ici
L! :;
'kf ¿,
73
5?7 IdAtin L 53 539
4,383,296
PLC? y
L- i
-
r AMERR.
R T C
C E E 3V ASSEMDLY NO ER OP S
C0F3 AC1ACN
FÓ3E ACIA
COF2 ACIACM
F676 ADCERR
F6&3 ADCTST1
F669 ADCTST3
C066 ADTO
F653 ATD
F479 CLOCRIO
FFEF I3NKSW
FÓA1 flOUT
F4CD CHPG
F532 CNTWR
FC25. COUT
F007 CROUT1
F513 DISK1
CODO DISKOFF
F575 ERRLP
F77E ERROR
CFFF EXPROM
F6BF 008001
85 IUDUFP
87 LI3CMD
1419 IUNK
COOS KEYBD
FDOF ISEVIN
F670 KEYPLUG
F770 MESSERR
FS2A NOGOOD CO58 PDLEN
91. PREYTRK FS3A PULUT
F901 MONITOR
F546 NOMEM 1810 PHP
19 PTRHI F772 RANGO
FS4F NMEM1
F526 NXBIT
F788 PINC1 F7AI PTRINC F776 RAMI
F7613 RAMO
F708 RAMERR3
F7EA RAI'1ERR4
P71)7 RAMERR2
F7F1 RAMEZRR!3
F7FD RAMRD
F761) RAMSET1
F4C RAMThL
F6F4 RAMTSTO
F7OF RAt'1T614
F72A RAMTSTÓ
FSM RAMWTt
F7F7 RAMWT
F5AS RAMWT2
F689 RECON
F5F2 ROMTSTI
F5FE ROMTST2
F5E7 ROMTST
FBC7 SETCVH F6CE SEX2
F090 SETUP F6D4 GEX3
F6C4 SEX1 ClOG SLT1
C300 SLT3 FFDF SYSDI
C400 SLT4 FFD2 SYSD2
PF STRO FF03 SY6D3
FFE2 SYSE2 F601) VIATST
FFE3 SYSE3 PSDE ZP1
COSi TXTMD F504 ZP2
FFDO ZPREO
10 ZRF'Gl
00 ZRPG
00 ZRPG
01 ROM
10 ZRPG1
19 FIRMI
lA ENK
SDCV
87 113CMD
91 PREVTRK
PF SThO
lelo PHI'
C000 KYOD
COOS KEYED
7C047 ADAS
CO5O GRMD
COSi TXTMD
C06ó ADTO
CODO DISKOFF
COPi ACIAST
COF3 ACIACN
C100 SLTI
C200 SLT2
C4OC) SLT4
CFFF EXPROM
F479 BLOCKID
F4CD CHPG
F513 DISK1
F524 NXBVT
F52A N0000D
F532 CMTWR
FS3A PULET
F54F NN1EM1
F562 NMEM2
F575 ERRLP
F5A1 RAMWTI
F5AS RAMWT2
F5AD RAMWT4
F504 2P2
FSE2 ZP3
F5E7 ROMTST
F5FE ROMTST2
FÓOD VIATST
FÓ3E AC IA.
F663 ADCTST1
F669 ADCTST3
F676 ADCERR
F669 RECON
FéAl BOOT
FÓJ3F 001300T
FhC4 SEX1
F6CE SEX2
F6D4 SEX3
FÒF4 RAMTSTO
F6FD RAMTST1
F7OF RAMTST4
F738 STRWT
F748 RAM
F760 RAMO
F776 RAMi
F7713 MESSERR
F77E ERROR
F7130 RAMSET1
F7A1 PTRINC
F706 PINC2
F7C3 RETS
F7C9 RAMERA
F7D7 RAMERR2
F/EA RAMERR4
F7F1 RAMERRS
F7F7 RAMWT
F901 MONITOR
FDC7 SETCYM
FC2S COt.IT
FDOF EYIN
F098 CLDSTPT
FD9D SETUP
FFD2 SYSP2
FFD3 SYSD3
FFDF SYSDI
FFE2 SYSE2
FFE3 SYSE3
FFEF UNKSW
NEXT OBJECT FILE NAME, IS MON. OBU
F7FF:
ORG *F7FF
F7FF
*
74
COVi ACIAS'T ?C04? ADRE-
IA BNR FD9E) CLDSTPT
SD CV F593 ERRLI-'i CO50 ORNO COlO KBDSTRB C000 KYJ3D F562 NNEM2 F524 NXI3YT F7136 PINC2
16 PIALO F748 RAM
F7C9 RAMERA F784 RANSET F6FO RAMTST1 FSAD RAMWT4 F7C3 RETS
01 ROM F6C2 SEX C200 SLT2 F733 STRWT FFEO SV SEO ?FÓE6 USRENTRY F5E2 ZP3
18 P TR LO 8S IBJ3UFP
1419 I BNK Colo KDDSTRD COSS PDLEN COF2 ACIACM C300 SLT3 F4CS RAMTEL F526 N X BIT F548 NOMEM F593 ERR LP i F5BE zPi F5F2 ROMTSTI F653 ATD F678 KEYP LUG F6C2 SEX ?FÓE6 USRENTRV F72A RAMTSTÓ F772 RAMOO F784 RAMSET
F7138 P INC 1 F7D13 RAMERR3 F7F13 RAMRD'
F007 CROUTI FFDO ZPREG FFEO SYSEO
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
4,383,296
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7
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11
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12
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13
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'i
i
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i
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18
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19
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Apple Computer Inc · 1982
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F876 FO 87
F878 E9 01
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R87: E
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69 70 71 RET3 72
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88 89
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93 94
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1
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#1 RET2
*1 ET2
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PE1
i
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#1 RET2
i'ET2
1
Et1:-
#1
R(T2
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21T'
dl
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Apple Computer Inc · 1982
Page 0590 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
4,383,296
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FC, 8
791l,
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RET2
80
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114
'C3C *1
rq, r4 -:)TA j-( F.'? i, i
11
i
f RDE F0 20
117
OEL ET-'
]
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r-8ko. E9 01
118
SBC *1
1EG RET2
{.
-f,-,
L ,.-
12
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i :r
L;
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F90 i F C> i
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0073: 0074.
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0077. 0078: 0079:
f4
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4 C.F.f.0C EGO $58
LrIAR; N EGO
7 RMAR(1N EGO
S WTNTGP EGO
9 WINETM E:QU
10 CH
EGO
i i Cv
EGO
12 i-AS4i
G.0
13 AS4H EGO
14 rASeL EGO
15 BASSH EGO
1- TEAS'L EGO
i7 TEAS4H EGO
I TEASEL EGO
19 TLAS8H EGO
20 FOROND EGO
21
ND EGO
22 MODES EGO
23 CURSOR EGO
24 STACV EGO
25 PROMPT EGO
26 TEMPX EGO
27 TEMPY EGO
28 CSWL EGO
29 CSWH EGO
30 KSWL EGU
31 VSWH EGO
32 PCL
EGO
33 PCH
5GO
34 AlL
EGO
1H
EGO
34 A2L
EGO
37 A2H
EGO
38 A3L
EGO
39 A3h
EGO
SC F" NLOC
SC R NLOC 4-i
SCRNLCC-2
5CR NLOC +3 £CRNLOC.k.4
SC R NLOC + 5
-s SC R NLOC
SCRNLGC +7 LCR NLOC +8 SCRNLOC +9
SCRNLOC+$A SCRNLOC+L3
SC R NL OC + SC
5CR NLCC +$5
SC R NLCC + SE
SC R NLOC +5F
SCRNLCC+$1O
SCRNLOC+SI i
SCPNLOC-$ 2
SCRNLOC +3 13 SCRNLCC +3 14 SCRNLOC+%1 5
SCRNLOC +3 16 SCRNLOC+$l7 SCRNLQC+$18
SCPNLOC +5 19 SCRNLOC+$ i A 3CR NLOC +5 lB
SC R NLOC +5 IC
A1L+1 AIL+2 AIL+3 A1L+4
Al L+ 5
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
0074:
0078: 007C
007D: 007E;
0080: 0069: F901:
C000:
CO 10:
F901: 03FB:
F479: F699: F4EE:
0050: 0081:
0082:
0085: 0087: F901 F901. F901 'DA F902 86 6A F904 F904. DG F905 20 3A FC F908 AO OA F9OA 9A F900.A9 DF F930 85 60 F9OF:20 05 FC F912 20 67 F9 F915: 20 2C F9 F91 84 70 f-9iA AO 11
F1C ee
F9ID.30 E5 F91FD9 OC F9 F922. DO F8 F924,20 5E F9 F927 A4 70 F929 4C 15 F9 F92C: F92C: A2 00 F92E. 86 76 f-30 96 77 F22. 91 7E p934 CB F935 49 00
C9 OA F939 90 06
6 88 F930. C. FA F93F'90 2A F941:A2 03 F943. OA F944: OA p945 OA F946 OA F947 OA F948: 26 76 F94A 26 77 F94C CA F940: 10 F8 F94F'AS 7C F951 DO 06
4,383,296
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82
40 A4L
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41 A4H
EGU AIL+7
42 STATE. EGli AIL+8
43 YSAV
EGLI A1L+9
44 INI3UF EGLI A1L+$A
AND $8
45 TEMP
EGLI A1L+*C
46 MASK
EGO CURSOR
47 *
48 KOD
EGL.) $C000
49 KBDSTRI3 EGO scolo
50 *
51 USERADR EGLI $3FB
52 BLOCKIO EQU SF479
53 RECON EGLI SF689
AS OF 12/20/79
54 DIAGN EGO $F4EE
55 INBUFLEN EGO $50
;ONL'( BO BYTES ($3A0-3EF)
56 I3SLOT EGO $81
57 IBDRVN EGO IBSLOT+1
58 IO20FP EGO IDSLOT+4
59 IDCMD EGO IBSLOT+6 60 *
61 ENTRY EGO *
62
TSX
SIX STACK
64 *
65 MON
CLD
MUST BE HEX MODE
66
35R DELL
67 MONZ 68 69
LDX STACK TX, LDA $30F
70
SIA PPOMPT
71
JSR GETLNZ
72 SCAN
)9P ¿STATE
73rXTINP 35R QETNUM
74
STY YSAV
Lt *511
RESTORE STACK TO ORiGINAL L.00AI1CIN
PROMPT IAPPLE FOP CPA..Th
GET A LINE OF INPUT SET REGULAR SCAN
ATTEMPT TO READ HEX DYIL SlOPE CURRENT iNPUT Fo1l.iILr 17 COMMANDS
.6 CMDSRCH LEV
77
8Ml
78
CNR
79
ONE
80
J'R
81
LOI
82
'Mf-
MON
CMDTABY
CMDSRCH
T(JSUD
YSAV NXTINP
GIVE UP IF UNRECOGNIZABLE FOUND NO KEEP LOOK ING PERFORM FUNCTION GET NEXT POINTER DO IIEXI COMMAND
83 *
84 GETNUM LOX *0
CLEAR A2
85
STX A2L
9
I3T A2H
87 NX T CHP 89
L DA
i r
I NBUF Y
B'M INDEX FCR NEXT TIME
89
EOR *320
90
CMP *$A
TEST FOR DIGIT
91
13CC DIGIT
SAVE IT IF 1-
AEC *$83
TEST FOP HEX A-F
93
:r $FA
94 95 DIGIT
occ DIGRET
LDX *
96
ASL A
97
ASt. A
98
ASI. A
ASI A
lOO NT131T ASL A
SHIFT HEX D11T5 INTO A2
101
ROL A2L
102
ROL A2H
103
DEX
104
LPL NXTIr
105 NXTBAS LDA STATE
106
ONE NXTBS2
SHIFTED ALL YET' IF ZERO THEN COPY TO A1 3
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
F953: 95 77 F955: 95 75 F957: 79 F959 ES FQ5AF0 F3
FQ5C DO D4 FQ5E: F95E: A9 FA F960: 48
F961 2 1C F F964 48 F965: AS 7C F967: AO 00
84 7C
F9613: 60 F9ÓC: F96C: F96C: 00 F9ÓD: 03 F9ÓE: 06 F9ÓF: ED
EE EF FO
El r974: 99
911
AO
93 A7 F979 AB F97A: 95
F't3 Cé,
F97C: F97C. 7C
F970 7A
F97E: 213 F97F: 13F F98C'. 77
3A
C2
IB
F9c34: A3 Oc
F9Se,: 06 F987 t47
F9Z4Z3: U7
Fe159: 99
E?.A Ç?fl -933. 25
Ft-'&jC:Eó JA E98E. 00 02
ED 71
9;.i E6 :4
FP9:C4?4.EDCo' 055
ç:c)c:,E3. 3
f;9Q9. F) IC,
FB.A5 74
ç.cc;1; ';c
F$9 ES a so
4,383,296
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84
107
LDA A2N. X
108
STA A1H,X
109
STA A3H. X
HO NX11352 INX
1.11
112
113 *
flEO NXTT3AS T3NE NXTCHR
114 TOSUB 115 116 117
LDA $CASCII 1PUSH ADDRESS OR FUNCTION
PIlA
¡AND RETURN TO IT.
LDA CMDVECSY
PIlA
118
LDA STATE
119 ZSTAIE ' *0
sPASS MODE VIA ACC.
120
STY STATE
121 DIQRET RIS
122*
123 CMDTAB EGU *
¡ RESET STATE OF SCAN
124
DFB $0
125
DFB $3
G G0 (CALL) SUBROUTINE
J
JUMP (CONES PROGRAM
126
DFB $6
M
MOVE MEMORY
127
0FB SED
R =READ DISK BLOCK
128
DFB SEE
U
USER FUNCTION
129
DFB SEF
V =VERIFY MEMORY BLOCKS
130
DFD SF0
s W =WRITE DISK BLOCK
131
DFB SF1
X
REPEAT LINE OF COMMANDS
132
0F8 $99
SP =SPACE (BYTE SEPARATOR)
133
DF!3 $913
° ASCII (HI BIT ON)
134
DFJ3 SAO
/ ASCII (HI BIT OFF)
135
DFB $93
SET STORE MODE
136
DFB $A7
RANGE SEPARATOR
137
DFB SAS
/
COMMAND SEPARATOR
138
DFB $95
1k3Mr9".) *
DFB 5C6
00i 141 CMDVEC EGU *
142
DF2
143
0FB JUMPi
=DEST/SOURCE SEPARATOR CR =CARRAGE RETURN
144
DF MOVEi
145
DFD READi
146
DFB USER-1
147
DFrs VRFY-1
148
DFB L4RTE-1
149
0FB REPEATi
t 50
DFÛ SPCE-1
151
DFE ASCII-1
1Is5-t2''
LIEFE ASCIIOÏ
DFr-3 SETIIODEI
54
Dra SETFIODE-1
s '-i
DFÜ SEPi
I 50
LiFE DESTi
15 Y
ÙFÌ3 CRMON-1
15S î-
159 *
loo N.XTA4 INC AAL
;BUMP 16 BIT POINTERS
1L 1_J1a
I £ '
1. OC.
16:3 NXTA1
14
I3NE NXTA1
NC A4H
INC AlL
I3NE TSTA1
;BUIP Ai
165
INC AXH
160
SEC
,IN CASE 0F ROLL OVER.
167
I-e.-0'S TSrA;
3EG RETAl
LDA AIL
SEC.
ttci._ca'rt n j -'i
SBC A2L
STA TEMP
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
4,383,296
85
86
A2 A5 75
72
2A4 E5 77
17.1
r2Af3 D) (i
1
sa
LL)A AH SDC A2i OA TErIP
3N: RETA i
ct.c
1F Al LESS THAN OR E:GUAL T
I ThEN CNV CL$ N. IIETt.N
F9AC: F9AC:
ti? ETA1 iu 178 e
179 *
F9AC:48
180 PRBYTE PHA
,SAVE LOW NIBBLE
F9AD:4A
181
F9AE: 4A
182
LSR A LSR A
;SHIFT HI NIBBLE TO PRINT.
F9AF:4A
183
LSR A
F930:4A
184
LSR A
F9131:20 37 F9 185
JSR PRHEXZ
F934: 68
186
PLA
F9B5:29 0F
187 PRHEX AND *SOF
1STRIP HI NIBBLE
F987: 09 BO F9B9:C9 BA
188 PRHEXZ ORA #$B0
189
CMP **BA
;MAKE IT NUMERIC
IS 1L'9'
F9313:90 02 F9BD:69 06
;MAKE IT 'A''F'
F9BF: 4C 25 FC 192 PRHEX2 JMP COUT
F9C2:
193 *
F9C2: 20 AC F9 F9CS:
194 PROYCOL JSR
195 *
PROYTE
F9C5:A9 BA
196 PRCOLON LDA #SBA
;PRINT A cOLON
F9C7:DO F6
F9C9:
F9C9:A9 07 F9CB:24 68
197 198
*
BNE PRHEX2
199 TST8OWID LOA #7
200
BIT MODES
BRANCH ALWAYS
ANTICIPATE a TEST FOR BO
F9CD:50 02
201
BVC SVMASK
F9CF: A9 OF
202
LDA #$F
F9DI:85 69
203 SVMASK STA MASK
F9D3:6O
F9D4: F9D4: BA
204 205
*
RTS
206 A1PC
TXA
TEST FOR NEW PC
F905: FO 07
207
BEG OLDPC
F9I7: 13574
208 A1PCI LDA A1L X
F9DQ95 72
209
STA PCL X
F9DHCA
210
DEX
F9DC; 10 F9
211
BPL A1PC1
F9DE: 60 F9DF:
212 OLDPC RIS
213*
F1DF 85 69
214 ASCII1 STA MASK
a SAVE HI BIT STATUS
F9E1 A4 7D F9E3: 131 7E F9E5:E6 70 F9E7:A0 00 F9E9:C9 A2
215 ASCII2 LDY YSAV
MOVE ASCII TO MEMORY
21ó
LDA (INI3UFh Y
217
INC YSAV
;BUMP FOR NEXT THING.
218
LDY *0
219
CMP **A2
,ASCII "
F9ED:D0 05
220
BNE ASCI ¡3
;NOPE1 CONTINUE.
F9ED.A5 69
221
LDA MASK
F9EF. 10 29 F9F1:60 F9F2:C9 A7 F9F4:D0 05
222
T3PL BITON
223
RIS
224 ASCII3 CMP **A7
225
ONE CRCHK
;HE'S CHANGED MODES. 1NOv HE'S DONE.
ASCII ' ?
,NO, TEST FOR EOL.
F9F4 A569
226
LOA MASK
F9FB 30 13
227
13Ml 3110FF
CHANGE MODES.
F9FA:60
F9F13: C98D
F9FD:F0 07
F9FF:25 FAOI.2ôAF FA
228 229 CRCHK 230
231
232
RIS CMP BEG N4
,JSR
**8D
ASC DONE
STORI
;END OF LINE? .YES. FINISHED aGO STORE IT'
FAO4: DO DB
233
ONE ABC 112
aDO NEXT.
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
FAOÓ: 60
FAO7:
F407 38 F408 90
F409. 18
FA0A AA FAOR:86 7C
FAO!): 49 84
FAOF. DO 7D FAI! A FF FAIJ 30 CA
FA15A9 7F
FAI?: IO C6
FAt 2C oo co
1-A1C io oj
FAtE 4 0F FE:
LA" FA:'l & t_c- ¿..t
FA3 4C 12 F9
F426
FA;.?h O AO FA rA2c' 4C 08 F?
FA2C
FA2C 20 92 F9
f-A2F BO SD
i
i
t'- t
'4
FA,3 3 - I 'A
2Q BC C
F-A:s .0 F7
F- .'iA 50
c'i JC' -i3 F'r
:_ rit: F:
r.\A.?
.74
i. 1
}'A4? DI !4
FA44 F0 06
J
r-)
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rrr
i t,4t, ¿c E FC
r Al: 'r, 8
FA4V 90 EF
VA5I. 60
FA.
f:\t A5 713
F4'' .A-4 ç
2(
AC
FC?
AS 74
r:A59. 20 C2 F9
FA5C-flI 74
FASE 20 70 FA F-At-! 2'» 73 FA
FAb4 At) 75
FAc ac AC F9
FASQ. AS 74
FAoN 20 C2 F9
FA&E
74
F-A/C' 2C AC Ç,
FA7:3 A-' Aù
F475 4Ç 25 FC
PATh.
A'i. -i-' F- S
r
F47C :G FP.7D 20 D4 F9 LI 'AnOtjÇ_\t ¿." / c. FAEJ
t, t :1
4,383,296
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88
234 ASCDONE RIS
235. -
236 ASCII SEC
237
DEE $90
238 ASCIIO CLC
239 CI4MDE
240 241
'CD-uY'DC.
241 fIlON 244
245 3110FF 24e
247 REPEAT 249 24
TAX SIX
EOR
UNE LDA 1KB LDA ERL DIT
!3PL
\MP
STATE flEA ERROR
fiEF
ASC Ill
*$7F
ASC Ill
R13D
P E PEAT 1
KEY IN
250 REPEAT! PLA
251
PLA
252
253 * 54 *
iMP SCAN
255 CRMON JS1'i EL!
c.CU/- *
-JMP MUNI
258 MOVE
e_Ji'
-nJSraR
ISlA i ERROR
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Apple Computer Inc · 1982
Page 0595 of 0730
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Apple Computer Inc · 1982
Page 0596 of 0730
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Apple Computer Inc · 1982
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Apple Computer Inc · 1982
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4,383,296
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Apple Computer Inc · 1982
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Apple Computer Inc · 1982
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4,383,296
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298
1311
¿t',
I3PL
300
J.P
301
CMP
'3 C' 2
303 304
IBEG Ct1
305
306 STÍJPLSI LDA
307
13P1.
30G NOETOP LOA
309
JMP
310 *
*WOTCR
PALlID
NOSTOP
KEYIN3
flAO
STOPLST
flBD
NOS TOP EJ L YP2
LttJ
ttT.D:FLST
GOUT
TEST FOR START/STOP
REAr) KED IS ¿T A SPACE?
¿VES, PAUSE IlL NEXT KEYPRESS .GUIT THIS OPERATION?
¿NO1 IGNORE THIS KEY. YES, RESTART
FDOC.6C 70 00 311 RDI'cEY JMP (KSWL)
rDOF:
312 *
FDOF: A9 7F
313 KEYJN LOA $47F
FD1185 83
314
STA TBAS4H
F01320 88 F0 315
JSR PICK
F016: 48
316 KEVIN1 PHA
F05720 35 F0 317
JSR KEYWAIT
Fr,IA:BO 08
319
ECS KEYIN2
FDICA5 69
319
LOA CURSOR
FD1E:20 9D FC 320
JSR DISPLAY
F021:20 35 FD 321
JSR KEYWAIT
F02468
322 KEYIN2 PLA
FD25:08
323
PHP
FD26. 42
324
PHA
F02720 °D FC 325
JSF DISPLAY
;MAVE FtWE F1FUT 15 CUNSUR
¿OC READ SCREEN
SAVE CHr AT cuFc.c JITIQN
s TEST FOR KEYPRESS
¿GO ai IT GIVE THEr Y. )NDF:RsCORE FOR A TIME
¿OC) %EE ir KEYPRESSED
SAVE KEYPRESS 3TATUS
FD2A: 3
326
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F0213, 28
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FD2E: AL) 00 CC F031:2C 10 CO F034: 60 FD?5: E6 62 F037 DO 09
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FD3J3 AL? 7F
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327
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328
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329 VEYIN3 [DA
330 VP'fNA ÍUT
331
QT5
332 REYWAIT TiC
333
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334
335
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33
CLC
337
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s TEST FOR DONE
Fß40:FQ 05
336
BEG KEYRET
;RETtMP4 ¿F TIMED OUT
FD42:O 00 CC 339 KWAIT2 ASt KED
rD45 90 FE ED4? oC'
340
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341 KE7REI RN
FD4G
342 *
FD4B
343 *
F048
344 ESCI EGU *
F048 20 77 FI) 345
JSR OOESC
FT.' TP AS 68
346 ES:APE LOA MODES
TO + SLC"i 'rIH cJrzc
Fr!D 29 uO
347
AND *SBO
1)3V 49 AB
348
EQA flAD
F051:9b 69
349
STA CURSOR
F053: 20 OC FD 350 ESCi
JSR RDKEV
;RFAD NEXT CHARACTER
FD56.A0 08
351
LDY *8
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-r58 D FO EF 352 ESC2
CMP ESCTABL. Y
FF'5D F0 ED
353
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FIM) 88
354
DEY
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355
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LOOP TIL FOUND üR DUNE
F060
356 *
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GO READ A CHARACTER
FDç,2, 25 oB
358
AND MODES
FPt4 85 69
359
STA CURSOR
SAVE STANDARD C'PBOP
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361
CMP *399
ESCAPE CHARACTER:
FDÓOF0 DE
362
BEG ESCAPE
FOOD C9 95
363
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;FORWARD COPY?
FDÖF UD 06
364
F071 20 88 Fj) Jét
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QET CHARACTER FROM SCREEIJ
Apple Computer Inc · 1982
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98
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225
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229
1Ç79 AB
230
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JSR LOA LSR 74V
*1
WINOTM LASTLN
SETCV RMARGIN
A
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IS IT THE LAST LINE? YES CLEAR IT
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MOVE SOURCE TO DESTINATION
DIVIDE BY 2
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Apple Computer Inc · 1982
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loo
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301
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312
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318
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398 KEYWAIT
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331
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348
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349
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351
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-rse 09 f0 EF 352 ESC
CMP ESCTABL V
FI"SD F0 LB
353
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F[t) 88
354
DEY
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355
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359
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361
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364
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Apple Computer Inc · 1982
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102
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FD77:
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366 367 368 e 369 QOCSC
ORA 01GO RTS
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370
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LOA ESCVECT Y
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373
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376
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DFB
37
0FB
379
0FB
380
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381
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INPUT BUFFER AT $3A0
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20
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Apple Computer Inc · 1982
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Apple Computer Inc · 1982
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106
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Apple Computer Inc · 1982
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Apple Computer Inc · 1982
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Apple Computer Inc · 1982
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Apple Computer Inc · 1982
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4,383,296 113
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Apple Computer Inc · 1982
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F912 SCAN
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Apple Computer Inc · 1982
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118
I claim:
In a digital computer which includes a central
The improvement defined by claim 7 including a read-only memory coupled to said address bus and said
processing unit (CPU), a random-access memory data bus.
(RAM), an address bus interconnecting said CPU and
The improvement defined by claim 8 wherein said
RAM such that said CPU addresses locations in said 5 stored signal in said register means provides a pointer
RAM and a data bus interconnecting said CPU and for locations in said RAM during a direct memory ac-
RAM, said CPU for certain functions addressing prede- cess transfer.
termined locations in said RAM with a predetermined
li. The improvement defined by claim 9 wherein said
range of address signals, an improvement comprising: detection means for detecting said predetermined
10
read-only memory in response to signals on said address
bus provides instructions to said CPU causing it to
range of address signals, coupled to said address increment address signals during said direct memory
bus; register means for storing digital signals, coupled to
access transfer. In a digital processor used in conjunction with a
said data bus, and;
display, said processor including a data bus and an ad-
15
switching means for coupling said digital signals dress bus, a memory comprising:
stored in said register means to said address bus
a first plurality of memory devices for storing data,
when said detection means detects said predeter-
coupled to receive data from said data bus;
mined range of said address signals;
a first memory output bus coupled to receive data
whereby data for said certain functions normally 20 from said first plurality of memory device;
stored by said CPU in said predetermined locations
a second plurality of memory devices for storing data
may be stored elsewhere in said RAM, thereby
coupled to receive data from said data bus;
enhancing the performance of said computer.
a second memory output bus coupled to receive data
The improvement defined by claim 2 wherein said
detection means detects all binary zeros.
25
The improvement defined by claim i wherein said
from said second plurality of memory devices; addressing means coupled to said address bus for
providing address signal for addressing said first
switching means comprises a multiplexer controlled by
and second plurality of memory devices;
said detection means for selecting said register means.
first switching means for selecting data from one of
The improvement defined by claim i including a
said first and second memory buses for coupling to
read-only memory coupled to said address bus and said 30
said data bus, said first switching means coupled to
data bus. The improvement defined by claim 4 wherein said
said first and second memory bus and said data bus; second switching means for selecting data from said
stored signals in said register means provide a pointer
for locations in said RAM during a direct memory ac-
cess transfer.
35
first and second memory buses for coupling to said display, said second switching means coupled to said first and second memory buses and said dis-
The improvement defined by claim 5 wherein said
play; and,
read-only memory in response to signals on said address
circuit means for coupling one of a selected said first
bus provides instructions to said CPU causing it to
and second memory buses to said addressing means
increment address signals during said direct memory
access transfer.
40
In a digital computer which includes a central
such that data from said selected one of said buses provides addressing information for selecting subsequent locations in said memory devices when
processing unit (CPU), a random-access memory
said data bus is receiving data from the other of
(RAM), an address bus having a first plurality and a
said memory buses,
second plurality of lines for coupling said CPU with said RAM, and a data bus interconnecting said CPU 45 and RAM, said CPU for certain operations addressing
whereby said memory provides data for a high resolution display and whereby some data stored in said memory is used for remapping locations in said
predetermined locations in said RAM with address signals on said first plurality of lines by coupling a pre-
memory. The memory defined by claim 12 wherein said
determined address on said second plurality of lines, an circuit means comprises a multiplexer, said multiplexer
improvement comprising:
50 selecting between said data from said selected one of
register means for storing signals, coupled to said data said buses and bank switching signals coupled to said
bus; multiplexing means coupled to said second plurality
of lines and said register means for selecting signals
multiplexer. The memory defined by claim 13 wherein said
multiplexer is controlled by a logic circuit which is
from one of said second plurality of lines and said 55 coupled to said address bus and said selected one of said
register means; logic means coupled to said second plurality of lines
buses.
The memory defined by claim 14 wherein said
and said multiplexing means for causing said multi- logic circuit causes said multiplexer to select said bank
plexing means to select signals from said register switching signals each time said processor switches an
means when said CPU couples said predetermined address on said second plurality of lines; whereby said signals from said register means pro-
OP code. In a digital computer with a memory, which is
used in conjunction with a raster scanned display, said
vide alternate locations in RAM for storage associ- display including a digital counter which provides a
ated with said certain operations. The improvement defined by claim 7 wherein said
65
vertical count representative of the horizontal line scanned by the beam for said display, said memory
predetermined address is all binary zeros.
providing data for displaying rows of characters, an
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
4,383,296
119
120
addressing means coupled to said memory for scrolling nal and wherein said detectioiz circuit also detects ad-
displayed characters, comprising:
dresses for page one on said address bus, and said multi-
an adder having a first and a second input tenninal, plexer selects said register if said page one addresses are
the output of said adder providing a portion of an detected and said alternate stack signal is in a predeteraddress signal for said memory, said first terminal 5 mined state.
of said adder being coupled to receive the lesser significant bits of said vertical count; said computer providing a periodically repeated sequence of digital numbers coupled to said second
In a digital computer which includes a central processing unit (CPU), a random-access memory (RAM), an address bus interconnecting said CPU and
terminal of said adder, said sequence of digital 10 RAM such that said CPU addresses locations in said
numbers provided by said computer having a maxi- RAM and a data bus interconnecting said CPU and
mum value equal to the number of scanned lines in RAM, said CPU for certain functions addressing prede-
each of said rows,
termined locations in said RAM with a predetermined
whereby the characters on said display are scrolled range of address signals, an improvement comprising: with a minimum of movement of data within said 15 detection means for detecting said predetermined
memory.
The addressing means defined by claim 16
range of address signals, coupled to said address
bus;
wherein said sequence of digital numbers is incremented
for each displayed frame.
20
In a ditital computer which includes a single chip
central processing unit (CPU), a random-access mem-
ory (RAM), an address bus interconnecting said CPU
and RAM such that said CPU addresses locations in
said RAM, and a data bus coupled to said CPU and 25 RAM, said CPU for certain functions addressing the
zero page in said RAM by providing binary zeroes on
certain lines of said address bus; an improvement com-
prising:
register means for storing digital signals, coupled to said data bus, and;
switching means for coupling said digital signals stored in said register means to said address bus when said detection means detects said predetermined range of said address signals, said switching
means also for coupling said digital signals stored in
said register means to said address bus when a certain direct memory access (DMA) signal is in a predetermined state;
a detection circuit for detecting said binary zeroes on 30 a read-only memory (ROM) coupled between said
said certain lines of said address bus;
address bus and said data bus, said ROM in re-
a register for storing digital signals, said register cou-
sponse to signals on said address bus providing
pled to said data bus for receiving digital signals
instructions to said CPU on said data bus to cause
from said data bus; and,
said CPU to increment address signals when said
a multiplexer for selecting between said digital signals 3
DMA signal is in said predetermined state;
stored in said register and said certain lines of said address bus, said multiplexer being controlled by said detection circuit so as to select said register when said binary zeroes are detected on said certain lines of said address bus; whereby data for said certain functions normally stored on page one of said RAM, may be stored elsewhere in said RAM, and still easily addressed by said CPU.
The improvement defined by claim 18 wherein
said register providing a pointer for locations in said RAM when said DMA signal is in said predetermined state, and said register providing RAM address signals when said certain functions are selected by said CPU,
whereby data for said certain functions normally
stored by said CPU in said predetermined locations may be stored elsewhere in said RAM, thereby enhancing the performance of said computer.
one of said stored signals from said register is coupled to
The improvement defined by claim 21 wherein
said multiplexer through an exclusive OR gate, said gate said switching means comprise a multiplexer which
being coupled to one of said certain laies of said address selects said register when said detection means detects
bus.
all binary zeroes or when said DMA signal is in said
The improvement defined by claim 18 or 19 50 predetermined state.
wherein said computer provides an alternate stack sig-
55
60
65
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¡ Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple I/I Computer Inormotion
APPLE I/I Plus PATENT
PoLen#4,533,9O9 -- O6Augus 1983
ADDED BY DAVID T CRAIG 2006
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Uñited States Patent [19]
Sander
[ii] Patent Number: [45] Date of Patent:
4,533,909
Aug. 6, 1985
[54] COMPUTER WITH COLOR DISPLAY
[751 Inventor: Wendell B. Sander, San Jose, Calif. [73] Assignee: Apple Computer, Inc., Cupertino.
Calif.
Appl. No.: 560,529
Filed:
Dec. 12, 1983
Related U.S. Application Data
[601 Continuation of Ser. No. 394,801, Jul. 2. 1982. abandoned. which is a division of Ser. No. 150,630, May 16, 1980, Pat. No. 4,383,296.
mt. Cl.' U.S. Cl.
[58] Field of Search
GO9F 9/30 340/703; 340/803;
340/802 340/701, 703
[56]
References Cited
U.S. PATENT DOCUMENTS
4,136.359 1/1979 Wozniak
358/Il
4.310.838 1/1982 Jusoetal. 4,360.804 11/1982 O'nura
340/701 340/703
Primary ExaminerDavid L. Trafton Attorney, Agent, or Fir,nBlakely, Sokoloff. Taylor &
Zafman
[57]
ABsTRACT
A microcomputer system with video display capability.
parcularly suited for small business applications and house use is described. The CPU performance is enhanced by permitting zero page data to be stored throughout the memory. The circuitry permitting this capability also provides a pointer for improved direct
memory access. Through unique circuitry resembling "bank switching" improved memory mapping is obtained. 4-bit digital signals are converted to an AC
chroma signal and a separate luminance signal for display modes. Display modes include high resolution modes, one of which displays 80 characters per line.
11 Claims, 9 Drawing Figures
i
Apple II! Plus Computer
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
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Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
U.S. Patent Aug 6, 1985
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Apple Computer Inc · 1982
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U.S. Patent Aug. 6, 1985
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Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
U.S. Patent Aug. 6, 1985
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
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Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
U.S. Patent Aug. 6, 1985
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Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
i
4,533,909
2
The memory of the invented computer is organized
COMPUTER WITH COLOR DISPLAY
in an unusual manner to provide compatibility with the 8-bit data bus and yet provide high dala rates (16-
This is a continuation of application Ser. No. 394,801 bits/MHz) r.eeded for high resolution displays. A first filed July 2, 1982. now abandoned, which is a divisional 5 plurality of memory devices are connected to a first of application Ser. No. 150,630 filed May 16, 1980, now memory output bus; these memory devices are also
U.S. Pat. No. 4,383,296.
connected to the data bus. The memory includes a second plurality of memory devices which are also con-
BACKGROUND OF THE INVENTION
nected to the data bus; however, the outputs of these
The invention relates to the field of digital computers, 10 second devices are coupled to a second output memory
particulariy microcomputers, having video display ca- bus. First switching means permit the first and second
pabilities.
memory buses to be connected to the display for high data rate transfers. Second switching means permit
Prior Art
either one of the memory buses to be connected to the
In the last few years, there has been rapid growth in the use of digital computers in homes by hobbyists, for small business and for routine engineering and scientific application. For the most part, these needs have been met with self-contained, relatively inexpensive microcomputers or microprocessors with essential peripherals, including disc drives and with relatively easy to manage computer programs. The design of computers
15 20
data bus during non-display modes. The addressing capability of the memory is greatly
enh&iced not only through bank switching, but through a noael remapping which does not require the CPU contrcl associated with bank switching. In effect, the "unusei" bits from one of the first and second memory buses a-e used for remapping purposes. This mode of operation is particularly useful for providing toggling between two separate portions of the memory.
for these needs requires considerable ingenuity since
The display subsystem of the described computer
each computer must meet a wide range of applications 25 generates video color signal in a unique manner. A 4-bit
and because this market is particularly
conscious.
color code as used in the prior art, is also used with the
A home or small business computer must, for exam- described display subsystem. However, this code is used
ple, operate with a number of different program lan- to generate an AC chrominance signal and a separate
guages, including those requiring relatively large mem- DC luminance signal. This provides enhanced color
ories, such as Pascal. The computer should interface 30 capability over similar prior art color displays.
with a standard raster scanned display and provide a
wide range of display capabilities, such as high density
BRIEF DESCRIPTION OF THE DRAWINGS
alpha-numeric character displays needed for word pro-
FIG. i is a block diagram showing the major compo-
cessing in addition to high resolution graphics displays. nents and subsystems of the invented arid described
To meet these specialized computer needs, generally 35 microcomputer system.
requires that a relatively inexpensive microprocessor be
FIGS. 2 and 3 together show the central processing
used and that the capability of the processor be en- unit (CPU) and the architecture associated with this
hanced through circuit techniques. This reduces the CPU, particularly the address bus and data bus. FIG. 2
overall cost of the computer by reducing, for example, is a circuit diagram primarily showing the address bus
power needs, bus structures, etc. Another important 40 and the logic means associated with this bus. FIG. 3 is
consideration is that the new computers be capable of a circuit diagram primarily showing the data bus and its
using programs developed for earlier models.
interconnection with the memory buses (A bus and B
As will be seen, the presently described microcom- bus), bootstrap read-only memory, and input/output
puter is ideally suited for home and small business appli- ports. cations. lt provides a wide range of capabilities includ- 45 FIGS. 4, 5 and 6 show the memory subsystem. FIG. ing advanced display capabilities not found in compara- 4 is a circuit diagram primarily showing the circuitry
ble prior art computers.
for selecting between address signals from the address
The closest prior art computer known to applicant is bus and display counter signals. FIG. 5 is a circuit diacommercially available under the tradema;k, Apple-II. gram primarily showing the generation of various "se-
Portions of that computer are described in U.S. Pat. No. 50 lect" signals for the memory devices. FIG. 6 is a circuit
4,136,359.
SUMMARY OF THE INVENTION
diagram showing the organization of the random-access memory and its interconnection with the data bus and
memory output buses.
A digital computer which includes a central process-
FIGS. 7 and 8 illustrate the display subsystem of the
ing unit (CPU) and a random-access memory (RAM) 55 invented computer. FIG. 7 is a ciicit diagram showing
with interconnecting address bus and data bus is de- the circuitry for generating the digital signals used for
scribed. One aspect of the present invention involves the video display. FIG. 8 is a circuit diagram of the
the increased capability of the CPU by allowing base circuitry used to convert the digital signals to analog
page or zero page data to be stored throughout the video signals. memory. Alternate stack locations and an improved 60 FIG. is a graph of several waveforms used to dedirect memory access capability are also provided by scribe a prior art circuit and the circuit of FIG. 8.
the same circuitry. Dettction means are used for detecting a predetermined address range such as the zero page. This detection means causes a special register
DETAILED DESCRIPTION OF THE INVENTION
(Z-register) to be coupled into the address bus. The 65 A microcomputer system capable of driving a raster
contents of this Z-register provide, for example, a scanned video display is disclosed. In the following
pointer during direct memory access, or alternate stack description, numerous specific details such as specific
locations for storing data normally stored on page one. part numbers, clock rates, etc., are set forth to provide
Apple Computer Inc · 1982
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3
.
4
a thorough understanding of the present invention. nections to the remainder of the computer. The pin
However, it will be obvious to one skilled in the art that number for each interconnection is shown adjacent to
the inventive concepts described in this patent may be the corresponding line. In many cases, the nomencla-
practiced without these specific cetails. In other in- turc associated with the 6502A (CPU 65) is used in this
stances, we!1known circuits have been shown in block 5 application. For example, pin 6 receives the nonmaska-
diagram form in order not to obscure the present inven- bic interrupt signal (ÑMI), and pin 4 is coupled to re-
tion in unnecessary detail.
ceive the interrupt request signai (W). Some of the
Referring first to FIG. I, in generai the described signals employed with the CPU 65, which are weil-
computer includes a central processing unit (CPU) 65, known in the art, and which are not necessary for the
jd . its associated data bus 42, address bus 46 a memory 10 understanding of the present invention are not de-
subsystem and a display subsystem 58.
detail in this application, such as the various
The address bus 46 from the CPU is coupled to the synchronization signals and clocking signals. The ad-
memory subsystem to permit the selection of locations dress signals from the CPU 65 are identified as Ao-Ai
in memory. Some of the address signals pass through a
d A8-A15. The data signals associated with the CPU
multiplexer 47. For some modes of operation, signals 15 65 are shown as Do-Di. As will be apparent to one
from a register 52 are coupled through the multiple er skilled in the art, the inventive concepts described in
47 onto the bus 46. The register 52 is identified as the this application may be employed with other micro-
Z-register and is coupled to the multiplexer 47 by the Z
bus. The general description of the multiplexer 47 and
Referring now to FIGS. 2 and 3, the generai architec-
its control by the logic circuit 41 are described in detail 20
in conjunction with FIG. 2. In generai, the circuitry
shown to the left of the dotted line 53 is included in
FIG. 2 while the CPU 65, memory 50, data bus 42 and
multiplexer 43 are shown in detail in FIG. 3.
The address bus NI is coupled to the read-only mcm- 25
ory 50. The output of this memory is coupled to the
computer's data bus 42. The read-only memory (ROM)
50, as will be described, stores test routines, and other
data of a general bootstrap nature for system initializa-
zion.
30
The data bus 42 couples data to the random-access
memory (RAM) 60 and to and from 1/O ports. This bus
also couples data to the Z-register 52 and other com-
monly used registers not illustrated. The data bus 42
receives data from the RAM 60 through the A bus and 35
turc, particularly the architecture associated with the
CPU 65 can best be seen. The address signais Ao-Ai are to a buffer 103 by the bus shown primarily in
FIG. 2. These address signais are also coupled to the ROM 50. The signals Ai-A7 after passing through the
buffer 103 are coupled to the memory subsystem. The address signals Ag-Ai (higher order address bits) are
coupled through lines shown in FIG. 2 to the multiplexers 47e and 47b. The contents of the Z-register 52 of
FIG. I is also connected to the multiplexers 47a and 47b through the Z-bus (Z i-Z7). The multipiexers 47a and 47b allow the selection of either the signals Ag-A15
from the CPU 65 or the contents of the Z-register (Z1 2i) for addressing the RAM 60. The output of these muitiplexers are shown as Ag-Al5; this designa-
B bus which are selected by multiplexer 43. The periph- tion is used even when the Z-bus is selected. Note in the
eral bus N2 is used, as is better illustrated in FIG. 3, for case of the Z0 signai, this signai is coupled to the multi-
coupling to peripherals.
plexer 47e through the exclusive OR gate 90 for reasons
The memory subsystem is shown in detail in FIGS. 4, 5 and 6. The address control means which receives
which are explained later. The address sigflals Ag-A ii
are also coupled to the ROM 50, thus the signals
addresses on bus 46, makes the final selection of mcm- Ao-A j are used for addressing the ROM 50. The sig-
ory locations within the RAM 60. Bank switching, nais Ag-A15 are connected to the logic circuit shown in
addressing for display purposes, scrolling and other the lower left-hand corner of FIG. 2; this logic circuit
memory mapping is controlled by the address control corresponds to the logic circuit 41 of FIG. 1.
means 59 as will be described in greater detail in con- 45 The input and output data signals from the CPU 65
junction with FIGS. 4 and 5. The RAM 60 is shown in are coupled by a bidirectional bus to the bidirectional
detail in FIG. 6. The counter 58 which is sychronized buffer 99 (FIG. 3). This buffer is selectively disabled by
with the horizontal and vertical display signals, pro- gate 100 to allow the output of ROM 50 to be communi-
vides signais both to the address control means 59 d cated to CPU 65 and during other times not pertinent to
to the display subsystem 48.
o the present discussion. The direction of flow through
The display subsystem receives data from the RAM the buffer 99 is controlled by a read/write signai cou-
60 on the A bus and B bus and converts these digital pied to the buffer through inverter 101. Data from the
signais to video signals which control a standard raster CPU 65 is coupled through the buffer 99 and bus 42 to
scanned display. A standard NTSC color signal is gen- the RAM 60 or to I/O ports. Data from the RAM 60 is
crated on line 197 and a black and white video signal on ss communicated to CPU 65 or bus N2 from the A bus and
line 198. The same signals used to generate these video B bus through the buffer 99. The 4 lines of the A bus and
signais can be used to generate separate red, green, blue 4 lines of the B bus are coupled to the multiplexer 43e.
(RGB) video signais. The display subsystem 48 receives Similarly, the other 4 lines of the A and B buses are
numerous timing signals including the standard color coupled to the multiplexer 43b. Multiplexers 43e and
reference signal shown as 3.5 MHz (C3.5M). This sub- 60 43b select the 8 lines of the A bus or B bus and commu-
system is described in detail in FIGS. 7 and S.
nicate the data through to buffer 99 and bus 42. These
COMPUTER ARCHITECTURE
multiplexers are selectively disabled (for example, during writing) by gate 102. As will be described later, the
In the presently preferred embodiment, the CPU 65 16 lines of the A bus and B bus permits the reading of
(microprocessor) employed with the described corn- 65 16-bits from the RAM at one time. This provides a data
puter is a commercially available component, the rate of 16-bits/MHz which is necessary, for example,
6502A. This 8-bit processor (8-bit data bus) which has a for an 80 character per line display. The data is loaded
16-bit address bus is shown in FIG. 3 with its intercon- into the RAM 60, 8-bits at a time.
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5. The ROM 50, as mentioned, stores test programs,
data needed to initialize various registers, character generation data (for RAM 162 of FIG. 7) and other
6
Next assume that page one has been selected by the
CPU and that the ALT Si K signal is low, indicating the alternate stack locations are to be selected. (A flag is
related data. Specific programs employed in the presently preferred embodiment of the computer are set
forth in Table 1 of U.S. Pat. No. 4,383,296. The ROM 50 is selected by control signals coupled to its pins 18 and 20, identified as signals ROM SEL and T ROM
SEL. Any one vf a plurality of commercially available read-only memories may be used for the ROM 50. In
the presently preferred embodiment, commercially
available Part No. SY2333 is used. Referring now to this logic circuit (lower left-hand
corner of FIG. 2), the NAND gate 81 receives the address signal Ag and also the alternate stack signal identified as ALT STK. The output of this gate provides one input to the AND gate 87. The Ag signal is
5
10 15
set by the CPU to change the ALT STK signal). Since the ALT STK signal is low and Ag is high, a high output occurs from the gate 81. All the inputs to gates 83
and 84 are low, therfore, high outputs occur from both these gates. The conditions of gate 87 are met, causing a high output from this gate and lowering the output from the gate 89. The Z-bus is thus selected by the multiplexera 47a and 47b. This allows the contents of the Z-register to be used as alternate locations. Nonzero page locations are assured by inverting Ag. The exclusive OR gate 90 acts as a selective inverter. If A8
is high and Zo is low, then Ag at the output of the multiplexer 47a will be low. Note that during zero page selection when Ag is low, the Zo signal is directly communicated through gate 90 to the output of multiplexer
also coupled through the inverter 82 to one input terminal of the NAND gates SS and 86. The address signals A9 and A10 are coupled io the input terminals of the
20
47L
Thus, the logic circuits along with the ALT STK signal allows alternate stack locations to be selected
NOR gate 83. The output of this gate is coupled to one through the Z-bus. This further enhances the perfor-
input terminal of the NAND gates 85 and 86 and the mance of the CPU which would otherwise be limited to
AND gate 87. The address signals Ai 1-A 15 are coupled to the input terminals of the NOR gate 84. The signal Ait is also coupled to an input terminal of the NAND
25
page one for stack locations. The logic circuit of FIG. 2 is also used along with the
Z-register to provide a pointer during direct memory
gate 85.
access (DMA). Assume that direct access to the com-
The outputs of the AND gates 87 and 88 (through puter's memory is required by a peripheral apparatus.
NOR gate 89), controls the multiplexers 47a and 47b. To initiate the DMA mode the CPU provides an ad-
When the output of gate 89 is low the Z-bus is selected, 30 dress between F800 and F8FF. Through a logic circuit
otherwise the address signals from the CPU 65 are se- not illustrated in FIGS. 2 ani 3, the kOM SEL signal is
lected.
brought low for addresses bctween F000 and FFFF.
The logic circuit above-described, along with the This signal is communicated to gate 93 and causes the
Z-bus and Z-register provide enhanced performance for output of gate 92 to rise (D1L3i is high at this time).
the computer. First, this circuit permits the zero page or 35 This rise in potential is communicated to one input of
base page data to be stored throughout the RAM 60 the gate 85. Additionally, g:tte 85 senses that the address
rather than just on zero page. Secondly, this circuit bits Ag, A9and Aio are low This information is coupled
enables addressing of alternate stack locations (other to gate 85 through the inverter 82 and the NOR gate 83
than page one). Lastly, this circuit through the Z-regis- as high signals. Also the fat that Ait is high is directly
ter provides a RAM pointer for direct memory access 40 communicated to gate 85 Thus with the address be-
(DMA).
tween F800 and F8FF the DMA Ol signal drops in
Assume for purposes of discussion that the CPU 65 is potential. This is sensed oy the peripheral apparatus
addressing the zero page of memory. That is, the higher which in turn causes the DMA i signal to drop and
order address bits Ag-Ai are all zeros. The zeros for provides a ready signal to the CPU 65. With the com-
A9-Ai are detected by the gates 83 and 84. If all the 45 pletion of this handshake, data may begin to be trans-
inputs to these gates are zeros, the outputs of these gates ferred to the RAM.
are high which condition is communicated to the gate
The DMA i signal through gate 93 and inverter 93
87. Ag which is also low, insures that the output of gate forces the T ROM SEL signal low. This signal in addi-
81 will be high. Thus, all the inputs to gate 87 are high, tion to being communicated to the ROM 50, is coupled causing the signal at the output of the gate 89 to drop. 50 to the buffer 99 through gate 100, disabling this buffer
When this occurs, the Z-bus is selected. Instead of all (during the reading of ROM SO). Also, the ready signal the binary zeros from the CPU being couìed to the causes the CPU to come to a hard stop. Importantly, the
main memory (RAM 60), the contents of the Z-register IDMA i signal, after passing through the inverter 94 and form part of the address for the memory. Therefore, the gates 88 and 89, assures the selection of the Z-regiseven though the CPU 65 has selected the zero page, 55 ter. The contents of the Z-register are fixed and provide
nonetheless data may be written into or from any loca- a pointer to a page in the RAM.
tion of RAM 60 (including the zero page). This en-
Under the above conditions, the CPU increments the
,i. ,;. ------ hances the performance of the CPU, since for example, lower 8-bits of the address signal. The ROM 50 fur-
.'n,,vnmpr! in çhiftin data to and from a single nishes the instructions for incrementing the address,
zero page is minimized. Normally, the CPU 65 selects page one for stack
locations. This occurs when g is high and A9-A5 are
60
specifically SBC #1 and BEQ. The peripheral apparatus provides the data or receives the data in synchronization with the CPU operation. The peripheral also
low. Assume first that the alternate stack locations have furnishes a read/write signal to indicate which opera-
not been selected. Both inputs to gate 81 are high and its tion is to occur. Data is then written into RAM virbus
output is low. The low input to the gate 87 prevents the 65 N2 and bus 42, or read from RAM via the A and B buses
selection of the Z-bus. Thus, for these conditions the address signals A0-A7 select stack locations on page
one.
and bus N2. importantly, with the above DMA arrangement,
addiesses from the peripheral apparatus are not neces-
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7 sary and the Z-register is used to provide a pointer to a
page in RAM 60.
8 devices in FIG. 6 are not illustrated. However, in the lower right-hand corner of FIG. 6, the various signals applied to each device (including the address signals),
MEMORY SUBSYSTEM
along with the corresponding pin numbers are shown.
The memory subsystem shown in FIG. 1 as the ad- 5 Other circuitry not illustrated is the refresh control dress control means 59 and RAM 60 is illustrated in circuitry which operates in a well-known manner in
detail in FIGS. 4, 5 and 6 as mentioned. In FIGS. 4 and conjunction with the CAS, RAS and address signals to
5, the memory control means is shown, while in FIG. 6 refresh the dynamic devices.
the memory devices and their organization are illus-
Each row of memory devices 106 receives a unique
trated. The address control means of FIGS. 4 and 5 10 combination of CAS and RAS signals. For example, row
receives the address signals from the CPU 65 (Ao-A ia), 111 receives CAS 5, 7and RAS 4, 5; similarly, row 112
the count in the vertical and horizontal counters
(counter 58 of FIG. 1) which are used during display modes, control signals from the CPU and other signals.
receives CASO z.nd RAS 0, 3. The generation of these
CAS and RAS signals is described in conjunction with FIG. 5. These signals (along wih the 14-bit address
In general, this control means develops the address 15 signals) permit the selection of a ingle 8-bit location iii
signals which are coupled to the RAM of FIG. 6 includ- the 96K byte memory (for writing) and a1so the selec-
ing the column address and row address signals, commonly referred to as CAS and RAS. Other related functions are also shown in FIGS. 4 and 5, such as the cir-
tion (for reading) of 16-bit locations. The memory of FIG. 6 may be expanded to a 123K
byte memory by using 32K memory devices, such as
cuitry which provides display scrolling, indirect RAM 20 Part No. 4132. In this case, four rows of' eight, 32K
addressing and memory mapping.
memory devices are used with each row receiving two
The CPU 65 of FIG. 3 provides a 16-hit address for CAS and RAS signals.
addressing the memory. Under ordinary circumstances
Before reviewing FIG. 4, a general understanding of
this address limits the memory capacity to 64 K bytes. the organization of the display is helpful. The display,
This size memory is insufficient in many applications, as 25 during certain modes, is organized into 80 horizontal
for example, to effectively use the Pascal program lan- segments and 24 vertical segments for a total of 1920
guage. As will be described in greater detail, the address blocks. 11-bits of the counter 58 of FIG. I are used as
control means of FIGS. 4 and 5 enable the use of a part of the address signals for the memory to access data
memory having a 96K byte or 128K byte capacity. One for displaying during these modes. These counter sig-
well-known technique which is used with the present 30 naIs are shown in FIG. 4 as Ho-H5 and V0-V4. During
invention for increasing this capacity is bank switching; other display modes each horizontal segment is further this switching occur under the control of the CPU. In divided into 8 segments (e.g. for displaying 80 alpha
addition, the address control means uses a unique indi- numeric characters per line). This requires 3 additional rect addressing mode which provides the benefits of vertical timing signals shown as V4, V8 and Vç in
bank switching, however, this mode does not require 35 FIGS. 4 and 7.
CPU control. This greatly enhances CPU operation
Often in the prior art, two separate counters are used
with the larger memory (as will be described) when to supply the timing/address signals for accessing a
compared to the CPU controlled bank switching.
memory when the data in the memory is displayed. The
Referring first to FIG. 6, the RAM configuration is count in one counter represents the horizontal lines of
illustrated for a capacity of 96K bytes. The memory is 40 the screen (vertical count) and the cther the position
organized into six rows, each of which includes eight along each line, (horizontal or dot count). In many prior 16K memory devices such as rows 111 and 112. In the art displays the most significant bit of the dot counter is
presently preferred embodiment, Part No. 4116 MOS used to increment the line counter. Data in memory
dynamic RAMs are used. (The pin designations and intended for display is mapped with a one-to-one corre-
signal designations refer tc this memory device.) Obvi- 45 lation to the counts in these counters. In another prior
ously, other memory devices uay be employed.
art system (implemented in the Apple-II computer sold
Input data to these memory devices 106 is provided by Apple Computer, Inc.) this one-to-one correlation is from the bus 42. Each line in the be'. '2 is cor.nected to not used. Rather, to conserve on circuitry, a single
the data input terminal cf one device 1116 in each row. counter is employed and a more dispersed mapping is
The interconnection of this bus wirn ech of the mem- 50 used in the memory. (Note that where a maximum hori-
ory devices is not shown in FIG. 6 in order not to over- zontal count of 80 is used, this number cannot be repre-
complicate this drawing. By way of example, however, sented by all ones in a digital counter and thus the verti-
line 107 connects the data bit Dl to the data input termi- cal counter cannot easily be incremented by the most
nal of one of the memory devices in each of the six significant bit in the horizontal counter.) Since this
rows.
55 more dispersed mapping technique is part of the prior
Three rows of devices 106 have their output termi- art and not critical to an understanding of the present
nals coupled to the A bus, and three rows are similarly invention, it shall not be described in detail. However,
coupled to the B bus. By way of example, line 108 con- the manner in which it is implemented sha'l be discussed nects three output terminals of devices 106 to the DB7 in conjunction with the adder 114 of FIG. 4. For pur-
line of the B bus while line 109 connects three output 60 poses of discussion, the signals from the counter 58 of
terminals of the devices 106 to the DA7 line of the A FIG. 1 are designated as either vertical (V) or horizon-
bus.
The described memory devices 106 are each orga-
tal (H). Referring now to FIG. 4, the selection of either the
nized as a I6KXI memory. Thus, each device receives counter signals on the address signals from the CPU is
a 14-bit address which is time multiplexed into two, 65 made by the multiplexera 116, 117, 118 and 119. Each of
7-bit addresses. This multiplexing occurs under the these c3mmetcially available multiplexera (Part No.
control of the CAS and RAS signals as is well-known. 153) couples one of four input lines to an output line.
The lines coupling the address signals to each of the There are eight inputs to multiplexers 116, 117 and 118
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9 and the outputs of these multiplexers provide the address signals for the memories (ARO through AR5). The
10 terminal of the gate 126 receives the Ci signal. (The development of the Ci and C3 signals is illustrated in
multiplexer 119 has four inputs on its pins 3, 4, 5, 6 and FIG. 5.) The gates 124, 125 and 126 provide mapping
provides a single output on pin 7, the AR6 address compensation within the memory. As the computer and
signal. (The signals supplied to pins 11, 12 and 13 of S memory are presently implemented, the sequence in
multiplexer 119 arc for clamping purposes only.)
which the various portions ofthe display are generated
The XX signal is applied to the pin 14 of each of the is not the same as the sequence in which the data is
multiplexers. Th signal on this line and the signal ap- removed from memory for display. These gates provide
plied to pin 2, determines which of the four inputs is compensating addresses and, in effect, cause a remap-
coupled to each of the outputs of the multiplexers. The IO ping so that the proper sequence is maintained when
x, signal is a RAM timing signal for clocking the first data is read from the memory for the display. These
7 bits and second 7 bits ofthe multiplexed 14-bit address gates are shown to provide a complete disclosure of the
applied to each of the memory devices 106. The other presently preferred embodiment, however, they are not
control signal to the multiplexers is developed through critical to the present invention.
the AND gate 123. The inputs to this gate are the dis- 15 In operation, the circuitry of FIG. 4, as mentioned,
play signal (DSPLY) which indicates that the computer selects the address signals which are applied to each of
is in a display mode and a clocking signal, specifically a the memory devices, either from the CPU or counter if I MHz timing signal (TM). The output of the AND the display mode is selected. It should be noted that not gate 123 determines whether the address signals from all of the address bits from the CPU are coupled to the the CPU or the signals associated with the counter 58 of 20 mutiplexers 116 through 119. Some of these address
FIG. I are selected.
bits, as will be described in conjunction with FIG. 5, are
Assume for purposes of discussion that the display used to develop the various
and
signals and
has not been selected, and thus, the output of gate 123 is thus select different rows within the memory of FIG. 6.
low. The XX signal then selects for pin 7 of multiplexer
The scrolling operation which is used is somewhat
116 first the address signal Ao and then A. Likewise, 2 unusual in that each line of the display is separately
each of the multiplexers selects an address signal (ex- moved up (line-by-line) with one line ofdata in memcry
cept for those associated with exclusive OR gates 124 being moved for each frame. This technique provides a
and 125 which shall be discussed). If the display signal uniform, esthetically pleasing, scroll. Scrolling the
is high and an output is present from the gate 123, then, by way of example, the XX signal first causes the Hi 30 signal and then the V1 signal to be connected to the ARi address line. Similarly, signals corresponding to the vertica! and horizontal count are coupled to the
other address lires during display modes.
screen one line per frame can be achieved by moving all the data in the memory into a new position for each frame. This would be very time consuming and imprac-
tical. With the described technique, only one-eighth of the data in the memory is moved for eath new frame.
Referring to the adder 121, as mentioned, the signals
The adder 114 is an ordinary digital adder for adding 35 two 4bit digital nibbles and for providing a digital sum signal. A commercially available a&er (Part No. 283) is employed. The carry-in terminal (pin 7) is grounded and no carry-outs occur since one of the inputs (pin 12) is grounded. The adder sums the digital signal corresponding to Hi, H4 and H with the digital signal corresponding to V3, V4, V3, V4. The resultant sum signal is coupled to the multiplexers 116, 117 and 118 as illustrated. The summing of these horizontal and vertical counter signals is used to provide the more dispersed 4(
mapping as previously discussed. The adder 121 is identical to adder 114 and is coupled
to sum the three least significant vertical counter bits from the counter 58 (FIG. 2) with the signals VAl, VBI and VC1. The sum is selected by the multiplexer 120 so
VA, VB and Vc are the three least significant vertical counter bits from the counter 58. These bits or counts, by way of example, represent the 8 horizontal lines of each character. In adder 12, a 3-bit digital signal, VAl, VBI and VC1, is added to the count from counter 58. This 3-bAt signal is constant during each frame, how-
ever, it is incremented for each new frame. During a first frame, 000 is added to the vertical
count. During a second frame, 001 is added, and during a third frame 010 is added, and so on. By adding this digital signal to the count from counter 58, the ad-
dresses to the memory are changed in the vertical sense. During the first frame when 000 is added, the display remains unaffected. During the next frame, when COlis added to the vertical count, instead of first displaying
during the high resolution display modes and also dur- the first line of a character, the second line of each
ing scrolling as will be described. These sum signals are coupled to the multiplexers 117, 118 and 119. During
character is displayed at the top of each character space and each subsequent line of the character is likewise
the low resolution display modes, the multiplexer 120 moved up one line. If data in memory is not moved, the
couples ground signals or the page 2 signal (Pm) to the 55 first line of the character would appear at the bottom of
multiplexers 117, 118 and 119. (The Pt signal is used for special mapping purposes, not pertinent to the prescnt invention.) During the high resolution modes when the display is not being scrolled, the VA!, VB2 and
each character. Note when 001 is added to 111 from the counter, 000 results. Thus, the first line of characters would be addressed when the beam is scanning the eighth line of characters. To prevent this, the data cor-
VB3 signals are at ground potential and thus no sum- 60 responding to the first line of each character is moved in
ming occurs within adder 121 and the VA, VB and VC memory for this frame. The first line of one character is
signals are coupled directly to the multiplexers 117, 118 moved up and becomes the bottom line of the character
and 119.
directly above it. When 010 is added, the process is
The address signals Aio, Ait, and A13 from the CPU again repeated. For example, the third line of each char-
are coupled to the multiplexers 117, 118 and 119, re- 65 acter is first displayed in each character space and the
spectively, through exclusive OR gates 124, 125, and second line of each character is moved up to become
126, respectively. The other input terminals to gates 124 and 125 receive the Cj signal, while the other input
the bottom line of the character directly above it. This process is repeated to scroll the data. The movement of
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11
12
data in memory is controlled by the CPU in a well-
known manner.
(S)
Thus, through use of adder 121, an even, continuous PCASS. 7. = (AY. IND. ABK3 .(ABKI. ABK2 +
scroll is obtained without moving all the data in mem-
ory for each frame. Rather, OfliY th of the data is 5
ABK! .Y).(73.AI4.AI3 + Ai5.iT.
moved for each frame.
Referring now to FIG. 5, the circuitry used to extend
+ AY. IND. ABK3 .
ABKI . AIS +
tEe addressing from the CPU is illustrated. In general,
the
signals are generated by the ROMs 127 and
128. The RAS signals are generated by the ROM 132.
Io
ABK2 . ABKI ABK2. ABKI . i3). A14 + AY.
The multiplexer 130 allows the selection of either the bank switching signals, or the unique indirect address-
IND ABKI - ABK2- ABK3 -(AIS . A14) + AY.
ing mode when "bank switching" occurs without direct
IND. ABK3 .ABK2.(AIS .ABKI +AI5 ABK1).
commands from the CPU.
15
The CAS ROM 127 receives as an address the fol-
lowing signals: PRAS , 3, PRAS 1,2, AY, DHIRES,
(A14 .A13 + A14. A13))
R,'W, Au, Aj3, Aj4, and Ais. As the PRAS4, 3 and PRAS 1, 2 represent the RAS signals being used. These signals ire high when the respective RAS signal is active. As previously mentioned, the AY signal is high for display rncdes and the DHIRES signal is high for high resolution oisplay modes. The CAS ROM 128 receives as address signals the ABKI, ABK2, and ABK3 signals and also DIHRES, Y, IND, Ais, A1), A4, and
20 25
In effect these ROMs are programmed to allow selection of predetermined rows in the memory, based on the address signals Ajo, AI), AI4 and Ais (ignoring for a moment the contribution of the RAS signals and the other signals appearing in the equations).
The outputs of the CAS ROMs 127 and 128 are coupled to the register 131. Register 131 is a commercially available register which permits the enabling of output
The ROMS 127 and 128 are programmed to imple- signals (Part No. 374). During accessing of the memory
ment the following equations.
the various CAS signals (CAS O through CAS 7) are
coupled to the memory of FIG. 6 to permit selection of
(PRASO.3-(DHIRES
30 the appropriate memory devices. The signal USELB from CAS ROM 127 through register 131 selects either
A13 All . R/WN + AIS . A14 . AI) . R/WN + AIS.
the A bus or B bus. This signal is coupled to the multiplexers 43a and 43b of FIG. 3.
During normal operation, the multiplexer 130 selects Al4 .A!3 + Ai5.A14.A13- All))) 35 the bank switching signals BCKSW i through BCKSW
4. These four signals (or a!ternatively four signals from
the A bus) provide four of the inputs (address signals) to
(2) the ROM 132. The other inputs to this ROM are the
PCAS2 = (DHIRES- AY + AY -(ABK! . ABK2- ABK3-
DH!RES, Z PAGE, PA8, PAlS, RFSH (refresh), and
40 AY signals. These address signals select the RAS 0, 3;
[ND + ABKI - ABK2 - ABK3)-(AIS . Al4) + AY. IND-
RAS 1, 2; RAS 4, 5 and RAS 6, 7 signals. The ROM 132 is programmed to impiement the follcwing four equa-
ABKI . AB(2 - ABK3 - AIS .(AI4 -A13 +A14- A13)) tions.
__(3) 45
(6)
PRASO. 3 = AY. (DHIRES + RFSH) + (ABK4 - (Z Page.
PCAS3 = (PRASO, 3 -(DHIRES- AY + AY .(A15 . A14-
l'Ai)) + ABKI - ABK2 - ABK3). AY
- ______ -
PCAS4.6 = (AY. IND. ABK3 . AIS. (ABKI ABK2 +
So
(7)
PRASI, 2 = AY-(DHIRES + RFSH) + AY -(ABK! -
(4)
ATT(ABK4-ZPAGE- PAS)- PAIS) + ABKI.
55
ABKI). ABK2) - (iT. A13 + A14. iT) + AY. IND-
ABK2 - ABK3) + AY - ABK3 - ( ABKI - ABK2 . ABK4-
ABK3 .(ABK2- ABK! -AIS + ABK2 -ABK1 + ABK2.
ABK!
AY.i -ABKl.ABK2.iZT. 60
j). (ZPAGE.
PAIS + ABK! - ABK2 - (ABK4.
(ZPAGE - PA8)- PA IS)
(AIS . A14 . A13 + AIS. A14 . AI3) + AY. IND-
Aic5.ABK2.iT.ABKI + Al5.TABKI).(iT. 65 PRAS4,S = RFSH.V+ AY ABK2-
(8)
A13 + Al4- A13))
A5.(f.ABK4.(ZPAGE. PA8).
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13 -continued
4,533,909 14
line 154 rises in potential, causing the multiplexer to switch back to the bank switching signals.
PAI5 + ABKI .(ABK4.(zpAoE:i).PAl5)
Effectively, what occurs is that when the CPU selects
this special address range, (and provided DA7 is high)
5 the bits DAO through DA3 which are stored in mcm-
PR.AS6,7 = RFSH.ÄV+ AY. ABK3 .(ABKI.
(9) ory, cause a remapping, that is, the address from the CPU accesses a different part of the memory. With the
¡I5.ABK4.(ZPAGE.PA8.PAI5+ ABKI
fetching of each OP code, the mapping automatically returns to the bank switching signals. Importantly, the
10 remapping, which occurs is controlled by the bits stored
ABK2 . (AHK4 (ZPAGE PAS). PAIS) in the RAM (DA4) through DA3). Thus, with the
remapping information stored in RAM, togging can
Thus, the bank switching signais (along with the other occur between different portions of the memory with-
input signals to ROM 132) select predetermined rows in Out requiring bank switching signals, or the like from
memory in conjunction with the CAS signals.
The output signals of the ROM 132 are coupled through the NAND gates 142, 143, 144 and 145 to the
memory. The other input terminals of these gates re-
ceive the RAS timing signal. In this manner, the output
signals of the ROM 132 are clocked through the gates 142 through 145 to provide the RAS signals shown in
15
20
the CPU. This enhances the CPU's performance since
CPU time is not used for remapping. Additionally, it provides an easy tool for programming.
For some program languages it is desirable to separate data and the program into separate portions of the memory. For example, the 128K memory can be di-
FIGS. 5 and 6. An important feature to the presently described com-
vided into two 64K memories, one for program and one for data. Switching can occur between these memory
puter is provided by the circuitry shown within the portions without the generation of bank switching sig-
dotted line 146. The AND gate 148 receives, at its input terminals, the DAl, Ai', and C3 signals. The NOR gate
25
nals by the CPU with the above described circuit. This arrangement is particularly useful when using the Pas-
149 receives the zero page and A1 signal. The output of cal program language.
gate 149 provides one input to the gate 148 and also one input to the AND gate 150. The output of gate 148
DISPLAY SUBSYSTEM
provides another input signal to gate 150 and this signal
The display subsystem 48 of FIG. I receivs data
(line 153) is one of the two control signals coupled to 30 from the A bus and B bus and converts the data into
the multiplexer 130. The AND gates 150 and 151 also video signals which may be used for displaying alpha-
receive a SYNC signal and the 4)0 signal. The output of numeric characters or other images on a standard raster
the gates 150 and 151 are coupled to a NOR gate 152 scanned cathode ray tube display. The display subsys-
with the output of the gate 152 (l'ne 154) cnupled to the
other control terminal of the multiplexer 130.
35
tem 48 specifically generates on line 197, a standard NTSC color video signal and a video black and white
The gates iso; 151 and 152 effectively form a clock video signal on line 198 (FIG. 8). This display subsys-
for multiplexer/register 130 (multiplexer 130 is a com- tem, in addition to other inputs, receives a synchroniza-
mercial part, Part No. 399, which effectively is a regis- tion signal, and several clocking signals. For sake of
ter/multiplexer). This selects the lower four input lines to the multiplexer 130. However, because of the syn-
40
simplicity, 3.579545
the standard color reference signal of MHz is shown as C3.5M. Twice this fre-
chronization signal applied to gate 151, the multiplexer quency and four times this frequency are shown as C7
130 selects the bank switching signals each time an OP M and C14M, respectively.
code is fetched by the CPU.
Before describing the details of the display subsystem
To understand the operation of the circuit shown within the dotted line 146 it should be recalled that the
45
48, a discussion of a prior art display system will be helpful in understanding the present display subsystem.
memory of FIG. 6 provides a 16-bit output. As men- In U.S. Pat. No. 4,136,359, a video display system is
tioned, during certain display modes, 16-bits/msec. are described which is implemented in a commercially
needed for display purposes. In nondisplay modes, only 8-bits are required, particularly for interactior with the CPU. When the memory is addressed by the CPU during the indirect addressing modes the data on the A bus
is not ordinarily used. However, with the circuitry shown within the dotted line 146, this otherwise "un-
used" data is put to use to provide the equivalent of the bank switching signals through multiplexer 130.
Whenever the CPU selects a predetermined range of addresses, the multiplexer 130 selects the equivalent of the bank switching signals from the A bus provided
DA7 is high. (This occurs when addressing as zero page
the address space 1800 through 1FFF.) Once the
signal on line 153 is high it is latched through gates 150, 151 and 152 causing the multiplexer 130 to select the
50 55 60
available computer, Apple-II, sold by Apple Computer, Inc., of Cupertino, Calif. In this system, 4-bit digital words are shifted in parallel into a shift register These words are then circulated in the shift register at 14 MHz to define a waveform having components at 3.5 MHz. Referring to FIG. 9, line 206, assume that the digital word 0001 is placed in the shift register and circulated at a rate of 14 MHz. The resultant signal which has a component of 3.5 MHz is shown on line 206. The phase relationship of this component to the 3.5 MHz reference
signal determines the color of the resultant video signal. This relationship is changed by changing the 4-bit word placed in the shift register. As explained in the above referenced patent, if the signal 1000 is placed in the
four bits from the A bus (assuming the timing signals are register and circulated, the resultant phase relationship
high). Even if the next reference from the CPU is not to of the 3.5 MHz component results in the color brown,
this special address range, the multiplexer 130 nonethe- 65 this signal is shown on line 208. With this prior art
less remains latched with the four bits from the data bus. technique, the luminance was determined by the DC
Once the SYN pulse drops, however, which is an indi- component of the signals such as shown on lines 206 and
cation that an OP code is being fetched, the signal on 208.
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15 The display subsystem 48 of FIG. i also u4s-ebsit
16 transferred at the 2 MHz rate, and in other display
words to generate the various color signals in a manner
somewhat similar to the above-described system. Referring to FIG. 8 4-bit words representative of colors (16 possible colors) are coupled to the bus 180 (The genera-
tion of these words shall be described in detail in conjunction with FIG. 7.) Instead of using a shift register which circulates the 4-bit word, the same result is
achieved by u'ing a multiplexer 205 which sequentially selects each of the lines of the bus 180. The signals on
bus 180 also provide a luminance signal arid a black and
5
10
modes, at a 1 MHz rate. The registers 158 and 159 are coupled to an S line
display bus 160. This display bus transfers data to registers 164 and 173, and also addresses to a memory 162. The registers 164 and 173 and memory 162 are enabled during specific display modes as will be apparent.
The character memory 162, in the presently preferred
embodiment, is a random-access memory which stores patterns representative of alpha-numeric characters. Each time the computer is powered up, the character information is transferred from the ROM 50 into the
white video signal with a gray scale.
The 4 lines of the bus 180 are coupled to multiplexer 205; this multiplexer also receives the C7M and the
M/ timing signals (again, Commercial Part No. 135 is
char',;ter memory 162 during an initialization period. During character display modes, the signals from the
15 display bus 160 are addresses, identifying particular alpha-numeric characters stored within the character
used with the pin connections shown in FIG. 8). These two timing signals cause each of the four lines to be
memory 160. The vertical counter signals VA, VB, and Vc(previously discussed in conjunction with adder 121
sequentially selected and coupled to line 191. (Note that of FIG. 4) identify the particular line in each character
the order in which each of the lines of the bus 180 is 20 which is to be displayed. Thus, the generation of the
selected does not change.)
digital signals representative of each of the characters
In effect, the multiplexer operates to serialize the occurs in an ordinary manner. The 7-bit signal represen-
parallel signal from bus 180. Assume for sake of expla- tative of each line of each character (memory output) is
nation that the digital signals on bus 180 are 1000 as coupled to the shift register 167. Through timing signals
indicated in FIG. 8. The signal on line 191 will then be 25 not shown, either the register 164 or the character mem-
10001000. . . . The output of the multiplexer 205 cou- ory 162 is selected to allow the shift register 167 to
pled to the input of the inverter 204 also receives in a receive either data directly from the A bus or B bus, or
sequential order, the signals from bus 180, however, in alpha-numeric character information from the memory a different order. For the example shown, the input to 162. inverter 204 is 00100010. . . . After inversion, this results 30 The 7-bits of information from either memory 162 or in the signal 11011101 . . . on line 192. Effectively, the register 164 are serialized by the shift register 167 either
signals on lines 191 and 192 are added by resistors 199 at a 7 MHz rate or 14 MHz rate, depending upon the
and 200. The resultant waveform is an AC signal (no display mode. The serialized data is coupled by line 185
DC component) shown in FIG. 9 on line 209. Thus, to the multiplexer 169, pins 1 and 4. The inverse of this
with the described circuit, a chroma signal is generated, 35 data is also coupled to multiplexer 169, pin 3. Line. 185
having a predetermined phase relationship to the 3.5 is also coupled as one input to the multiplexer 166 and to
MHz color reference signal. This phase relationship the register 170 (input 1).
which is varied by changing the signals on bus 180
The output I of register 170 (line 186) is coupled to
determines the color of the video signal on line 197.
the multiplexer 169, pin 1; to register 170 (input 2); and
In the prior art display discussed above, the DC com- 40 to multiplexer 166. Output 2 of register 170 (line 187) is
ponent of the color signal determines the luminance. In coupled to input 3 of register 170 and also to multiplexer
the present invention, the signals on bus 180 are coupled 166. Output 3 of register 170 (line 187) provides a third
to the base of transistor 195, consists of an AC signal input to the multiplexer 166. Input 4 of the register 170
from resistors 199 and 200, and the luminance level also receives the output of the multiplexer 169 (line 189). determined by the signals on bus 180. These inputs to 45 Output 4 of register 120 (line 190) provides one control
transistor 195, along with the C3.5M signal, generate a signal for the multiplexer 171.
NTSC color signal on line 197 of improved quality
The multiplexer 171 selects either the four lines of bus
when compared to the discussed prior art system.
183 or the four lines of bus 184. The output of multi-
In some cases, the signals on bus 180 are all binary plexer 171, bus 180, provides the 4-bit signal discussed ones or all binary zeros. When this occurs, there is no 50 in conjunction with FIG. 8. During one of the high
AC component from resLtors 199 and 200 (no color resolution display modes (AHIRES), the multiplexer
signal) and the resultant signal on line 197 is either 171 is controlled by a timing signal from the output of
"black" or "white".
the gate 178.
The lines of bus 180 are also coupled through resis-
The multiplexer 166 selects either the lines of bus 181
tors to the base of a transistor 196. Each of these resis- 55 or bus 182. The output of this multiplexer provides the
tors have a different value to provide a "weighting" to signals for the bus 184. In all but the AHIRES display
the binary signal. This weighting is used for non-color mode, multiplexer 166 selects bus 181. Thus, typically,
displays to provide "gray" shades as opposed to having the multiplexer 171 receives the signals from bus 174.
a display with only black and white. The binary signals on bus 180 drive the transistor 196 to provide a video signal on line 198. RGB is generated with weighted
60
For purposes of description above, and also for purposes of explaining for some of the display modes below a simplifying assumption has been made. The signals
sums of these same five signals. Referring now to FIG. 7, data from memory is cou-
coupled to the bus 180 by multiplexer 171, for most modes, are controlled by the serialized signal on line
pled from the A bus and B bus to registers 159 and 158, respectively. These registers are clocked by the 1 MHz 65
190. This serialized signal is in sychronization with the C7M or C14M clocking signals. The multiplexer 205 of
clocking signal and its complement, thus permitting the sequential transfer of 8-bit words every 0.5 msec. As
FIG. 8, which as described above, does the "spinning" for the parallel digital signal on bus 180, operates in
will be described, in some display modes the data is sychronization with the multiplexer 171. In the descrip-
Apple Computer Inc · 1982
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4,533,909
17
18
tion above, and except when otherwise noted below, it identification (address for RAM 162), is furnished on
is assumed that, by way of example, if the multiplexer the A bus to register 159 at a frequency of 1 MHz. The
171 is coupling all binary ones and zeros onto bus 180, color information (background color and foreground
the signal on line 191 will be either ones or zeros. Also color) is furnished on the B bus as two 4-bit words to
for this condition the signal on line 192 will be all binary 5 register 158. In the manner previously described, the
zeros or ones, and thus, no AC signal is generated at the address from register 159 selects the appropriate char-
base of transistor 195. However, as actually imple- acter from memory 162 and provides this information to
mented, there is a "phase" difference between the shift register 167. The color information from the B bus
clocking of the multiplexer 171 when compared to the is transferred to register 173. For purposes of explana-
sampling of the signals from bus 180 by the multiplexer lo tion, assume that the 4-bits identifying the color red for
205. This results in a first constant AC signal on the gate the background are on bus 184 (from register 173 and
of transistor 195 even when it appears that all binary multiplexer 166) and that 4-bits representing the color
ones are on bus 180, and a second constant AC signal blue for the foreground are on bus 183. (Note that when
when all binary zeros are on the bus 180. Thus, in this register 173 is enabled, the signals from the register
specification, when it states that "black" or "white" 15 ovenide the binary ones and zeros which otherwise
signals are being generated, instead, as currently imple- appear on the lines of bus 174.) The serial binary signal
mented, two constant colors are generated on a color representative of the character itself on line 190, selects
display. Where a true black and white is desired, color either the color blue from bus 183 for the character
suppression is introduced such as through the color itself or the color red from bus 184 for the background.
burst signal.
20 The digital signals representative of these colors are
The circuit of FIG. 7, along with the circuit of FIG. transferred to bus 180 and provide the color data to the
8, provides the capability for several distinct display circuit of FIG. 8. For black and white displays, a
modes. The first of these modes provides a display con- "gray" scale is provided through the weighting circuit
sisting of 40 characters (or spaces) per horizontal line. associated with transistor 196 of FIG. 8. Again, the
This requires a data rate of 8-bits/MHz or half the data 25 multiplexer 169 may, through the tiring means 172,
rate the memory is capable of delivering. In this mode, alternate between the signal of line 185 and its inverse,
data is loaded from the A bus during every other 0.5 which will have the effect of interchanging the fore-
sec period. (B bus is not used during this mode.) This ground and background colors.
data addresses the character memory 162, and along
During the high resolution graphics modes, the char-
with the signals VA, VB and V, provides the apprcpri- 30 acter memory 162 is not used, but rather, data from the
ate character line (7-bits) to the shift register 167. Dur- memory directly provides pattern information for dis-
ing this mode, registers 164 and 173 are disabled. The play. This requires more mapping of data from within
shift register 167 for this mode shifts the data at a data the main memory since new data is required for each
rate of 7 MHz (note CH is high, allowing the 7 MHz line of the display. (Note that when characters are dis-
signal from gate 175 to control the shift register 167). 35 played, the character memory 162 provides the differ-
Each 7-bit signal is shifted serially onto line 185 and ent signals required for the 8 lines of each character
then to line 189 since multiplexer 169 selects pin 4. The row. During these high resolution modes, the register
data is shifted through the register 170 onto line 190. 164 is enabled and the character memory 162 is dis-
The serial binary signal on line 190 causes the selection abled. Thus, the data from the A bus and B bus is shifted
of buses 183 or 184
40 into the shift register 167. In these modes, the "HRES"
The four lines of bus 183 during this mode are cou- signal to multiplexer 169 causes this multiplexer to se-
pled to +V (register 173 is disabled); therefore the lect between pins I and 2. Pin 2 provides the signal
selection of bus 184 provides four binary ones. The directly from the shift register 167 while the signal on
selection of bus 184 provides four binary zeros through pin 1 is effectively the signal on line 185 delayed by one
bus 181. Thus, the serial binary signal on line 190 pro- 45 period of the C14M signal. This delay occurs through
vides either all binary ones or all binary zeros to bus the register 170 from input 2 to output 2 since register
180. As discussed the circuit of FIG. 8 will provide a 170 is clocked at C14M.
black and white display with 40 characters per line.
During a first graphics mode, data from the display
If the inverse and flashing timing means 172 is se- bus 160 is loaded into shift register 167 at the rate of
lected, each time the shift register 167 is loaded, multi- 50 7-bits/MHz. The data is serialized on line 185 and in the
plexer 169 shifts between pins 3 and 4. This causes the manner previously described for displaying characters,
characters to change from white characters on a black controls the selection of all binary ones and all binary
background to black characters on a white background, zeros through the multiplexer 171. Note, as mentioned
and o on. During the 80 character per line display mode, the
before, in the presently preferred embodiment, unless 55 color suppression is used, this will not result in a black
registers 158 and 159 are each loaded during sequential and white display, but rather a tvìo-color display. If a
0.5p sec periods (this utilizes the 2 MHz cycle rate high bit is present on line 140 of the display bus, the
previously discussed). The shift register 167 shifts the character data from memory 162 at a 14 MHz rate. The
inverse and flashing timing means 172 causes the multi-
plexer 169 to alternate between pins 1 and 2. This
serialized data at the 1.4 MHz rate is shifted through the 60 switching occurs at a 1 MHz rate and provides a phase
register 170 and again controls the multiplexer 171 as shift for every other 7-bits of data coupled to the multi-
previously described. (Note that register 170 is always plexer 171 on line 190. This results in an additional color
clocked at the 14 MHz rate.) Flashing again can be being generated on the display for every other 7-bits of
obtained as previously discussed. In another alpha-numeric character display mode, the
65
data. For the above-described graphics modes when shift
background of each character may be in one color and register 161 is shifting at a 7 MHz rate, 8-bits may be
the character itself (foreground) in another color. This mode provides 40 characters per line. The character
coupled to the bus 160 during each period. Specifically, as in the case of the differing background and fore-
Apple Computer Inc · 1982
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20
ground colors for the 40 character per line display
termined frequency so as to provide frequency
mode, two 4-bit color words are shifted into register 173
components at said frequency f;
at a rate of 1 MHz. Then, the multiplexer 171 selects
converting means, coupled to said serializing means
between two predetermined colors on buses 183 and
for converting outputs from said serializing means
184. Note these colors can be changed at a I MHz rate. 5
to an AC signal;
In an additional color mode identified as "AHIRES',
whereby a video chroma signal is generated.
multiplexer 171 operates under the control of gates 176,
2. The circuit defined by claim I including additional
177 and 178. In effect, multiplexer 171 selects bus 184 circuit means coupled to said digital word generation
and latches the signals on this bus every four cycles of means for providing a DC luminance signal.
the C14M clock. Data is shifted into the shift register iO 3. The circuit defined by claim i wherein said digital
167 from the A bus and B bus every 0.5 p. sec the register words are coupled to a resistive weighting network for
167 operates under the control of the C14M signal. providing a gray scale video signal.
Each data bit on line 185 is shifted first to line 186, then
The circuit defined by claim 1 wherein said digital
to line 187 and finally to line 188. These lines are cou- words are 4-bit words and werein said predetermined
pled to the multiplexer 171 through multiplexer 166 is frequency is equal to 4f.
which selects bus 182 since AHIRES is high. In effect,
The circuit defined by claim 4 wherein said serializ-
what occurs is that 4-bit color words are serialized onto ing means comprises a multiplexer which is controlled
line 185 and then brought back into parallel on bus 182. in sychronization with said frequency f.
Since multiplexer 171 latches the signals on bus 184
The circuit defined by claim 5 wherein said con-
every four cycles of the C14M signal, a new color word 20 verting means includes an inverter coupled to an output
is generated at a 3.5 MHz rate on the bus 180. The of said multiplexer.
resultant display is 140 by 192 colored blocks wherein
The circuit defined by claim 6 including additional
each block can be any one of 16 colors.
circuit means coupled to said digital word generation
In the last display mode, typically used with color means for providing a DC luminance signal.
suppression, data is shifted into the shift register 167 25 8. The circuit defined by claim 1 wherein said digital
from the display bus at the rate of 14-bits/MHz. The word generation means comprises:
data is serialized onto line 11i5 and controls the selection
a source of digital data for controlling said display;
of either all binary ones or all zeros through multiplexer
a first register coupled to receive data from said
171. This provides the highest resolution graphics dis-
source of data;
play for the system.
30 a multiplexer for selecting between two buses, the
Thus, a microcomputer with video display capability
output of said multiplexr coupled to said serializ-
has been described. The computer is fabricated from
ing means, said buses coupled to said first register,
commercially available parts and provides high utiliza-
a shift register coupled to receive data from said
tion of these parts. Numerous existing programs includ-
source of data, said shift register providing a serial-
ing many of those which operate on the Apple-II com- 35 ized digital signal for controlling said multiplexer.
puter, may be employed in the above-described com-
The c'rcuit defined by claim 8 including a charac-
puter.
I claim:
1. In a digitally controlled, raster scanned, video
ter memory for storing data representative of alpha numeric characters, said memory coupled to receive
address from said source of data, the output of said
display for use with a microcomputer, or the like, which 40 memory coupled to said shift register.
display provides color images in response to chroma
The circuit defined by claim 9 wherein when said
signals having predetermined phase relationships to a first register is disabled, one of said two buses is
reference signal of frequency (f), a circuit for providing clamped to provide all binary ones, and the other of said
a digitally controlled chroma signal comprising:
buses provides all binary zeros.
digital word generation means for generating prede- 45 li. The circuit defined by claim 10 wherein said shift
termined digital signals;
register is controlled by a plurality of clocking signals,
serializing means coupled to said generation means for repeating said word in a serial form at a prede-
all of which are synchronized with said frequency f. ****s
50
55
60
65
Apple Computer Inc · 1982
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i Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple I/I Computer lnormotion
APPLE I/I ROM INFO
ADDED BY DAVID T CRAIG 2006
Apple Computer Inc · 1982
Page 0634 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple 7//ROM Informatión
APPLE III ROM INFORMATION
by
I3k David Craig t.ViC4ì4Z1 Ansas
1986
This document describes the Apple /1/ microcomputer ROM organization. The ROM listing used was from Apple Computer's patent (# 4,383.296) of May 10. 1983 as assigned to Wendell B. Sander. The ROM listing appears to be from December 20. 197g.
The ROM occupies 4K bytes of memory in the address range $F000$FFFF. This ROM is used by the Apple i/i at system power-up to test various hardware components. initialize the character generator bitmap, and boot SOS (Sophisticated Operating System) from the Apple i/I's internal floppy diskette drive.
The ROM is organized as follows (routine names in lowercase were created by me since the source code did not contain a name at the particular location):
Addresses
F000-F124 F125-F12A F126-F130 F13E-F147 F148-F169 F1b-F1BC F1BD-F218 F219-F282 F2B3-F255 F2BC-F2C5 F2C6-F310 F311 -F354 F355-F395 F3g6-F3FF F400-F455 F456-F456
F47-F4F
F470-F476 F479-F49F
j Name
REGRWTS SETTRK CHKDRV DRVINDX
RED16
GOSERV
RDDR1 WRITE16 SERVICE WNIBL9 PRENIB16 POSTNIB16 NIBL DNIBL SEEK MSWAIT ONTABLE OFFTABLE BLOCKIO
I Description
Read/Write a disk track and sector Set slot dependent track location Check if disk motor is stopped Get index to drive number Read disk sector Interrupt service vector Read disk sector address field Write disk sector Interrupt servicer Write 7-bit nibbles to disk Pre-nibblize disk sector data Post-nibblize disk sector data 6-bit to 7-bit nibble conversion table 7-bit to 6-bit denibbleize conversion table Disk track seeker 100 microsecond delayer Disk phase ON time table (in 100 microsecs) Disk phase 0FF time table (in 100 microsecs) Read/write a disk block (2 sectors)
Apple /// Information
- i -
by Davû/ Craiq (i85)
Apple Computer Inc · 1982
Page 0635 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple 111812M /nformat,òn
F4AO-F4A7 F4A8-F4C4 F4C5-F4CC F4CD-F4ED F4EE-F522 F524-F531 F532-F545 F548-F574 F575-F5BQ F5BA-F5E6 FSE7-F6OC F600-F63D F63E-F652 F653-F67A F678-F688 F689-F6C 1 F6C2-F6E5 F5E6-F737
F78-F747
F748-F77A F77B-F783 F784-F7AO F7A1-F7C8 F7C9-F7F6 F7F7-F7FF F800-F900
FQO1-FQ2B F92C-Fg5D FQ2E-FQ6B
Fg6C-Fgle
FQ7C-F988 FQ8C-FQAB
FQAC-FQC1
FQC2-FQC8 FQCQ-FQD2
FQD4-FQDE FQDF-FAO6 FAO7-FA25 FA26-FA2B FA2C-FA3A FA3B-FA51 FA52-FA77 FA78-FA7A FA7B-FAB2 FA82-FAQO FA91-FA9Q FAQA-FAB7 FA88-FABF FACO-FAE8 FAEQ-F820
FB21-F848 FB49-FB4E FB4F-F892
SECTABL ANALOG RAMTBL CHPG DIAGN NXBYT CNT(UR
memsize
ERRLP
zpgstktst
ROSITST
VIATST ACIA AiD
KEYPLUG RECON SEX USRENTRY STRWT RAM MESSERR RAtISET PTRINC RAMERR RAMWT RETi ENTRY GETNUII TOSUB CMDTA8 CMDVEC NXTA4 PRBYTE PR8YCUL TST8OWIO A1PC
ASCII1 ASCII
CRMON MOVE VRFY MISMATCH USER JUMP
RWERROR
DEST SEP SETtIODE READ DUMP8 DUMPASC COL6O COL4O
Block to sector conversion table
Joystick read routine RAIl test bytes Hardware component phrases (eq R" "ROtI",...)
ROM system power-up entry (calls RECON [F689]
Test RASI page 0 (Zero Page) Test RAIl page 1 (Stack Page)
Size the RASI Display screen error line ("DIAGNOSTICS")
Test RAM zero page & stack page Test ROM hardware
ÇOi.
Test VIA hardware
Test ACIA hardware
Test A/O hardware Test keyboard plugin
Reconfigure system (tests for Apple-1 key)
System exerciser
Main RASI tester
Error massage string writer
Determine size of RASI Display error message
Setup RAM
Increment extended addressing pointer
RASI error handler
RAM write
Nested RTS 'table' routine SARA Monitor entry point
Get number from user
Execute Monitor cormand
Monitor comand code table Monitor coninand vector table (byte-long entries) Increment 2 byte pointer Output a byte to screen Output a byte followed by a colon Test for 80-column screen width Test for new P.C.
Store user ASCII string into memory
Fetch ASCII character from keyboard Dump line of hexadecimal bytes due to user CR
Move bytes around in memory
Verify memory byte range Output verify mismatch data line User control vector
Transfer control to user routine
Output error number Copy source pointer to destination pointer
Test for seperator character in input line
Setup user mode
Handle Monitor READ disk block coavnand Output line of memory bytes Output line of memory bytes as ASCII
Setup 80-column display mode Setup 40-column display mode
Apple /// Information
2
y Da v/il cra, ('1985)
Apple Computer Inc · 1982
Page 0636 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple 1//ROM lnfòrmat,on
FBQ2-FBA3 FBA4-FBB6 FBB7-FBCB FBCQ-FBD4 F805-FBDO Fb09-FBF1 FBF2-FCO4 FCU5-FC24 FC2S-FC22 FC33-FC35 FC26-FCS1 FC52-FC5A FCSB-FCQC FCQD-FCAC FCAD-FC8A FCBB-FCD4 FCDS-FDOB FDOC-FOOE FDUF-FD47 FD48-FD5F FD6O-FD76 FD77-FD7E FD7F-F087 FDB8-FD97 FDQ8-FDC5 FDC6-FEAD FEAE-FEC4 FEC5-FFB3 FFB4-FFB7 FFB6-FF8O FFBC-FFBF FFCD-FFEF FFFO-FFFQ FFFA-FFFB FFFC-FFFO FFFE-FFFF
CONTROL cURUP CURIGHT
DLIRDOWN
LSTBACK URLEFT
CUIJT2
BASCALC1
COIJT
COI-iii
TSTBELL LNFD SCROLL DISPLAY DSPL8O NOTCR GETLNZ RDKEY KEVIN ESC3 ROCHAR GUESC ESC VECI PICK CLDSTART GENENTR VRETRCE CHRSET HOOKS VBOUNDS NMIIRQ applecwrite ESCTABL NMI RESET IRG
Handle usar control character input Handle cursor up motion Handle cursor right motion Handle cursor down motion Handle backspace motion Handle cursor left motion Output character to screen Compute character base address for screen output Output character to current output device Character output vector Handle BELL character output (beep speaker) Handle LINE FEED character output Scroll screen lines Display character on 40-column screen Display character on 80-column screen Handle non-control character output Read user ASCII line from keyboard Read keyboard key input vector Read raw keyboard key Handle ESC character cursor motion Read keyboard character ESC key cursor motion handler ESC key editing comand key code table Read character from current cursor location Cold boot system (initialize ROIl globals) Load character generator RAM with bitmap Wait/poll for CRT vertical retrace Character generator character bitmap table Output/Input vectors Screen dimension bounds (0,80.0.24) Nt1I request vector (JIIP RECON (F68] RTI) Apple Computer. Inc. 1Q80 copyright phrase ESC character table MII vector (FFCA] RESET vector (F4EE] (Power-up Diagnostics) IRG vector [FFCD]
The Eno'----
Apple /// information
S -
by David Craig (1955)
Apple Computer Inc · 1982
Page 0637 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
AeMh Ap1t//Í icq( (7-A &oZ Accer
(irtvd. {D T ..y'vre t L'M7
sfø
4t?I ¡2a'êS
o
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o
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O
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Source Code Listing
o
for
o
o o
A
ç'-J 'J
o
o
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o
o Sara ROM
o
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000$FEFF
o
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VL5LO1'J i.
o
(tee AI//p64t+
v5Ofrt)
o
David T. Craig
o
736 Edgewater
o
Wichita, Kansas 67230
o
Ck't. ctgO
Apple Computer Inc · 1982
Page 0638 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
0000000000000000000000
'p-4
r1
oo
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'.4
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0000000000000000000000
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Apple Computer Inc · 1982
Page 0639 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
t
10/31/89 9:56
0000 0000
0000
0000 0000 0000 0000 0000
000g
Foga F000 F000 F000 F000 F000 F000 F000 F000 F000 F000
F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000
F000 F000
F000 F000 F000 F000
F000 F000
F000 F000 F000 F000 F000 F000
F000 F000 F000
F000
F000 F000 F000 F000 F000
F000 F000 F000 F000 F000 F000 F000
F000 F000 F000
F000
F000 F000
F000 F000 F000 F000 F000 F000
F000 F000 F000 F000 F000 F000 F000
f000
0200 0302
0080 00E0
0081 0082 0083 0084 0085 0087 0088 0089 0089 008A 008B 008C 0085
0093 0094 009B 009F
0095 0095 0096 0097
HD:Apple i/:ROM - Disk I/O
I/I ;d APPLE
ROM - DISK I/O ROUTINES
d*gCgOPgYgRIgGgHTgg19g7g9 gBYggAPgPgLEggCOgMgPUgTEgRg,gIgNCg.ggggggsggggg*ugg*gggí*
.ABSOLUTE
.PROC DISKIO
.ORG
0F000
CRITICAL TIMING
*
REQUIRES PAGE BOUND *
CONSIDERATIONS FOR
*
CODE AND DATA
*
CODE
*
VIRTUALLY THE ENTIRE *
'WRITE ROUTINE
*
MUST NOT CROSS
*
PAGE BOUNDARIES
CRITICAL BRANCHES IN *
THE 'WRITE', 'READ, *
AND READ ADR' SUBRS
WHICH MUST NOT CROSS
PAGE BOUNDARIES ARE
*
NOTED IN COMMENTS
*
EQUATES
*
NBUF1 NBUF2
.EQU .EQU
0200 0302
HRDERRS
.EQU
80
DVMOT
EQU
0KO
IBSLOT
.EQU
81
IBDRVN
.EQU
IBSLOT+1
IBTRI<
.EQU
IBSLOT+2
IBSECT
.EQU
IBSLOT+3
IBBUFP
.EQU
IBSLOT+4
IBCMD
.EQU
IBSLOT+6
IBSTAT
.EQU
IBSLOT+7
IBSMOD
.EQU
IBSLOT+8
CSUM
.EQU
IBSMOD
IOBPDN
.EQU
IBSLOT+9
IMASK
.EQU
IBSLOT+0A
CURTRK
.EQU
IBSLOT+ØB
DRVOTRE
.EQU
CURTRK-7
SLOT I, DRIVE i
SLOT 4, DRIVE 2
SLOT 5, DRIVE 1
SLOT 5, DRIVE 2
SLOT 6, DRIVE i
SLOT 6, DRIVE 2
RETRYCNT .EQU
IBSLOT+12
SEEKCNT
.EQU
IBSLOT+13
OUF
.EQU
IBSLOT-flA
ENVTEMP
EQU
IBSLOT+1E
IBSLOT+$1F NOT USED
(ZERO PAGE AT $300)
& 5 USED ALSO FOR ADDRESS HEADER CKSUM
----READADR----
k
**************************
COUNT LAST CKSUM CSSTV
EQU
IBSLOT+14
'MUST FIND COUNT.
.EQU
IBSLOT+14
'ODD BIT' NIBLS.
.EQU IBSLOT15
CHECKSUM BYTE.
.EQU
IBSLOT+16
FOUR BYTES
CHECKSUM, SECTOR, TRACK, AND VOLUME.
----WRITE----
*
USES ALL NBUFS
*
AND 32-BYTE
DATA TABLE 'NIBL'
*
** ** ** ** ** * * ** ** * * ** ** ** * *
** **** ** ** ** k A ** ** AA * A
USES ALL NBUFS
*
USES LAST 54 BYTES
*
OF A CODE PAGE FOR *
-
Page 1
I
Apple Computer Inc · 1982
Page 0640 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
f
10/31/89 9:56
F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000
F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F000 F002 F004 F006 F008 FØØA F005 FØ0C FØØD
F00E FØ0F F010 F012 F015 F017 FO1A FØ1B
FØ1D
0095 009D 009E
0099 009A
C080 0081 C08C C08D CØ8E CØ8F FFEF FFDF 0080 007F
C088 C089 CØ8A CØ8B C081 C080 0097 0097 0098 0099 0099 009A 0083 0082 0081 0080
AO 01 A6 81 84 94 A9 05 85 8F 08
68 6A 6A 6A 6A
85 SB AD DFFF 85 9F 20 2BF1 08 AS 85 85 9B
HD:Apple i/:ROM - Disk I/O
SIGNIFICANT BYTES
*
OF DNIBL TABLE.
*
Page 2"
TRXCNT PRIOR TREN
.EQU .EQU .EQU
COUNT IBSLOT+1C IBSLOT+1D
HALFTRACKS MOVED COUNT.
----MSWAIT----
MONTIMEL MONTIMEH
.EQU .EQU
CSSTV+2 MONTIMEL+1
¡ MOTOR-ON TIME ¡ COUNTERS.
DEVICE ADDRESS
*
ASSIGNMENTS
PHASEOFF PHASEON 06L
06H Q7L 07H INTERUPT ENVIRON ONEMEG TWOMEG
.EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU
00080 OCOB1 ØCØ8C ØCØ8D ØCØ8E 0008F OFFEF ØFFDF 80
7F
; STEPPER PHASE OFF. STEPPER PHASE ON.
;
Q7L,Q6L=READ
;
Q7L,Q6H=SENSE WPROT
;
Q7H,Q6L=WRITE
; Q7H,Q6}1-WRITE STORE
EQUATES FOR RWTS AND BLOCK
MOTOROFF MOTORON DRVOEN DRV1EN PHASON PHSOFF TEMP CSUM1 SECT TRACK TRENi VOLUME IBRERR IODERA IBWPER IBNODRV
.EQU .EQU .EQU .EQU .EQU .EQU .EQU
EQU
.EQU .EQU .EQU .EQU EQU EQU
.EQU .EQU
00088 00089 ØCØ8A ØCØ8B 00081 00080 CSSTV TEMP
CSUM1-I-1
SECT+1 TRACK TRACK+1 IIRDERES+3 NRDERRS+2 HRDERRS+i HRDERRS
PUT ADDRESS INFO HERE
READ WRITE A
*
TRACK AND SECTOR
*
****** ************************
REGRWTS LOI
#01
; RETRY COUNT
LDX
IBSLOT
; GET SLOT f FOR THIS OPERATION
STY
SEEKCNT
ONLY ONE RECALIBRATE PER CALL
LDA
#005
STA
08F
PHP
; DETERMINE INTERRUPT STATUS
PLA
ROR
A
ROR
A
¡ GET INTERRUPT FLAG INTO BIT 7
ROR
A
ROR
A
STA
IMASK
LDA
ENVIRON
PRESERVE ENVIRONMENT
STA
ENVTEMP
JSR
CHKDRV
PHP
LDA
IBBUFP
; SET ZERO FLAG IF MOTOR STOPPED ; SAVE TEST RESULTS ; MOVE OUT POINTER TU BUFFER INTO ZPAGE
STA
BOF
J
Apple Computer Inc · 1982
Page 0641 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
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F01 F F021
F023 F025 F027 F029
F02 B F02 D
F02 E
F02 F
F032 F034 F035 F038 F030 FØ3C FØ3E FO3F F041 F044 F045 F047 F048 FO4A F040 FØ4F FØ4F F050 F052 F052 F052 F052 F054 F055 F057 F059 FØ5B F05D FØ5F
F058'
FØ5F
F058'
F058'
F058'
F05 F
F058'
F05F F062 F064 F066 F069 F069 F069 F069
F069 F06B F060 F06F F071 F072 F074 F077 F079 FØ7C
F078' F081
F083 F085 F088 FØ8A F080 FØ8F F091 F093 F095 F097 F099 F09B FØ9C FØ9E
FOAl FØA3 FØA6 FØA7 FØAA FØAC FOAC FØAC FØAC FØAC
AS 86 85 90 A9 E0 85 9A A5 82 C5 8A 85 BA 08 6A BD 8900 9001 ES BD 8ACØ 20 4CF3 28 FØOA 28 A0 07 20 56F4 88 DOFA 08 A5 83 A6 81 20 04F1
28 0017
A0 12 88 OØFO E6 99 00F7 E6 9A 30F3
20 2BF1 0005 A9 80 4C EAFØ
A5 87 F076 C9 03 B072 6A B000 AD DFFF 29 7F 8D DFFF 20 C4F2 AO 7F 84 93 A6 81 20 BPF1 9022 20 AAF1 C6 93 10F2 C6 94 0053 A5 8F 3ØEA A5 80 48 A9 60 20 25F1 A9 00 20 04F1 68 20 04F1 90D7
A4 99
HD:Apple i/:ROM - Disk I/O
Page 3"
LDA
IBBUFP+1
STA
BtJF+1
LDA
#DVMOT
STA
MONTIMER
LDA
IBDRVN
CMP
IOBPDN
; DETERMINE DRIVE ONE OR TWO SANE DRIVE USED BEFORE
STA
IOBPDN
SAVE IT FOR NEXT TIME
POP
KEEP RESULTS OF COMPARE
ROR
A
; GET DRIVE NUMBER INTO CARRY
LDA
MOTORON,X
TURN ON THE DRIVE
BCC
DRIVSEL
; BRANCH IF DRIVE 1 SELECTED
INX
SELECT DRIVE 2
DRIVSEL LDA
DRVDEN,X
JSR
SET1MEG
INSURE ONE MEGAHERTZ OPERATION
L'LE'
WAS IT SAME DRIVE?
BEQ
OK
PLP
MUST INDICATE DRIVE OFF BY SETTING ZERO FLAG
LDY
#07
DELAY 150 MS BEFORE STEPPING
DRVWAIT JSR
MSWAIT
(ON RETURN A=ø)
DEY
BNE
DRVWAIT
POP
NOW ZERO FLAG SET
0K
LDA
IBTRK
GET DESTINATION TRACK
LOX
IBSLOT
RESTORE PROPER X (SLOT*16)
JSR
MYSEEK
AND GO TO IT
NOW AT THE DESIRED TRACK WAS THE MOTOR ON TO START WITH?
PLP
WAS MOTOR ON?
ONE
TRYTOX
IF SO, DON'T DELAY, GET IT TODAY!
MOTOR WAS OFF, WAIT FOR IT TO SPEED UP
MOTOF
LDY
CONWAIT DEY
BNE
INC
BNE
INC
BMI
#12
CONWAIT MONTIMEL MOTOF MONTIMEH MOTOF
; WAIT EXACTLY 100 US FOR EACH COUNT ; IN MONTIME
; COUNT UP TO 0000
******************************
MOTOR SHOULD BE UP TO SPEED IF IT STILL LOOKS STOPPED THEN THE DRIVE IS NOT PRESENT.
JSR BNE NODRIVERR LOA JMP
CHKDRV TRYTRK
#IBNODRV HNDLERR
IS DRIVE PRESENT? ; YES, CONTINUE
NO, GET TELL EM NO DRIVE
NOW CHECK IF IT IS NOT THE FORMAT DISK CDMMAND, LOCATE THE CORRECT SECTOR FOR THIS OPERATION
TRYTRK
LDA
BEQ
CMP
( I4
BCS
___-
J
ROR BCS
Q'
LDA
\
AND
t,/Jrt
STA
JSR
TRYTRK2 LDY
STY
TRYADR
LOX
JSR
BCC
TRYADR2
JSR
DEC
BPL
DEC
ONE
LOA
0Ml
LOA
L'HA
LOA
JSR
LDA
JSR
GOCAL1
PLA
COCAL
JSR
BCC
IBCMO ALL000E #03 ALLDONE A TRYTRK2 ENVIRON #TWOMEG ENVIRON PRENIB16 #7F RETRYCNT IBSLOT RDADR16 RORIGHT CHKINT RETRYCNT TRYADR SEEKCNT ORVEOR 08F TRYADR CURTRK
#60 SETTRK #00 MYSEEK
MYSEEK TRYADR
; GET COMMAND CODE # ¡ IF NULL COMMAND, GO HOME To BED ¡ COMMAND IN RANGE?
NO, OD NOTHING! ¡ SET CARRY=1 FOR READ, 0 FOR WRITE ¡ MOST PRENTBBLIZE FOR WRITE
; SHIFT TO HIGH SPEED!
ONLY 127 RETRIES OF ANY KIND
GET SLOT NOM INTO X-REG READ NEXT ADDRESS FIELD ¡ IF READ IS RIGHT, HURRAH! BRANCH TO CHECK FOR INTERRUPTS ANOTHER MISTAKE!! WELL, LET IT GO TRIS TIME ¡ ONLY RECALIBRATE ONCE! ¡ TRIED TO RECALIBRATE A SECOND TIME, ERROR! ¡ ANOTHER MISTAKE!! ; WELL, LET IT GO THIS TIME
SAVE TRACK WE REALLY WANT
¡
RECALIBRATE ALL OVER AGAIN! ¡ PRETEND TO BE ON TRACK 80
ERROR!
MOVE TO TRACK 00
¡ GO TO CORRECT TRACK THIS TINE! LOOP BACK, TRY AGAIN ON TRIS TRACK
¡
RAVE NOW READ AN ADDRESS FIELD CORRECTLY. MAKE SURE THIS IS THE TRACK, SECTOR, AND VOLUME DESIRED.
RDRIGHT LDY
TRACK
ON THE RIGHT TRACK?
7
Apple Computer Inc · 1982
Page 0642 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
10/31/89 9:56
FØAE FØBØ FØB2 FØB2 F002 F0B2 FOB4 F005 F006 F007 FØBA F000
E'ØBE
FOCO FØC2 F0C4 F0C6 FØC8 FOCA F0CC FOCO FØCF FØD2 FØD4 F007 F0D9 F0DC FOUI F051 F053 F0E4 FØE6 FOES FØEA F050 FØED FOFO F0F3 FØF5 F058 F019 F019 FOFC FØFE F100 F102 F104 F104
1104 F104 F104 F104 F104 F105 F107 F1ØA F100 F1OF Fill F113 F115 F118 FilA F11B FilE Fill
F121 F123 F124 F125 F125 F125 F125 F125 F128 F12A F12B F128 F12B F12B F12B F12B F12B 1120 F12B F12B F12B F12B F120 F12D
C4 SC FØØE
AS SC 48
98
ØA 20 25F1
68 20 04F1 9ØCA
A5 9A 85 89 A5 98 C5 84 DØCØ A5 87 4A 902A 20 48F1 BØB6 AD DFFF 29 7F 8D DFFF 20 ØFF3 A6 81 BØA7 18 A9 00 9003 A9 82 38 85 88 BD 88C0 20 AAF1 AS 9F 8D DFFF 60
20 16F2 9005 A9 81 50E8 D086
ØA 85 99 20 18F1 20 3EF1 85 85 85 SC AS 99 95 85 20 00F4 A0 03
98 20 4AFI 88 10F9 46 8C 18 60
20 3EF1 95 85 60
A0 00 BD 8CCØ
HD:Apple /ll:ROM - Disk I/O
Page 4
CPY
CURTRE
BEQ
RTTRK
IF SO, GOOD
RECALIBRATING FROM THIS TRACK
LOA PHA
TYA
ASL
JsR PLA JSR
0CC
RTTRX
LDA
STA CORRECTVOL LDA
CMP BNE LOA LSR
3CC JSR
BCS
LOA
AND STA
JSR LDX
ALLDONE
BC S
CLC
LOA
DRVERR HNDLERR ALDONE1
BCC LOA SEC STA LOA JSR LOA
STA
RT S
CURTRK
¡ PRESERVE DESTINATION TRACK
A SETTOX
MY SEEK TRYADR2
VOLUME IBSMOD SECT IBSECT TRYADR2 IBCMD A
WRI T READ 16
TRYADR2 ENVI RON #TWOMEG ENVI RON POSTNIB1 6
TO SL UT
TRYADR2
#00 ALDONE i #IBDERR
IBSTAT MOTOROFF, X CHKINT ENVTEMP ENVIRON
GET ACTUAL VOLUME HERE TELL OPSYS WHAT VOLUME WAS THERE CHECK IF THIS IS THE RIGHT SECTOR
NO, TRY ANOTHER SECTOR READ OR WRITE? THE CARRY WILL TELL CARRY WAS SET FOR READ OPERATION, CLEARED FOR WRITE CARRY SET UPON RETURN IF BAD READ
¡ SET TWO MEGAHERTZ DO PARTIAL POSTNIBBLE CONVERSION RESTORE SLOTNUM INTO X CHECKSUM ERROR
NO ERROR SKIP OVER NEXT BYTE WITH BIT OPCODE BAD DRIVE INDICATE AN ERROR GIVE HIM ERROR TURN IT OFF BRANCH TO CHECK FOR INTERRUPTS RESTORE ORIGINAL ENVIRONMENT
WRIT
JSR
WRITE1 6
BCC
ALLOONE
LDA
#IBWPER
BVC
HNDLERR
BNE
TRYAOR2
WRITE NYBBLES NOW IF NO ERRORS DISK IS WRITE PROTECTED!! TAKEN IF TRUELY WRITE PROTECT ERROR OTHERWISE ASSUME AN INTERRUPT MESSED THINGS UP
THIS IS THE SEEK ROUTINE SEEKS TRACK N IN SLOT #X/$10
¡ IF DRIVENO IS NEGATIVE, ON DRIVE 0 ¡ IF DRIVENO IS POSITIVE, ON DRIVE i
MYSEEK
SEEK 1
GOSEEK ALLOFF NXOFF
ASL STA JSR JSR LOA STA LOA STA JSR LDY TYA JSR DEY BPL LSR CLC RTS
A TRKN1 ALLOFF DRVINDX DRVOTRK, X CURTRK TRKN1 DRVOTRK, X SEEK #03
CLRP HASE
NXOFF CURTRK
ASSUME TWO PHASE STEPPER. SAVE DESTINATION TPACK(*2) TURN ALL PHASES OFF TO BE SURE. GET INDEX TO PREVIOUS TRACK FOR CURRENT DRIVE
THIS IS WHERE I AM AND WHERE I'M GOING TO
GO THERE! TURN OFF ALL PHASES BEFORE RETURNING (SEND PHASE IN ACC.) CARRY IS CLEAR, PHASES SHOULD BE TURNED OFF
DIVIDE BACK NOW
THIS SUBROUTINE SETS THE SLOT DEPENDENT TRACK LOCATION
SETTRK
JSR
DRVINDX
STA
DRVOTRK, X
RTS
AA A A ***A AA AA Ak ***A ** A A
GET INDEX TO DRIVE NUMBER
SUBR TO TELL IF MOTOR IS STOPPED
IF MOTOR IS STOPPED, CONTROLLER'S SHIFT REG WILL NOT BE CHANGING.
RETURN Y=ø AND ZERO FLAG SET IF IT IS STOPPED.
CHXORV
LDY
#00
INIT LOOP COUNTER
CHKDRV1
LDA
Q6L,X
READ THE SHIFT REG
I
Apple Computer Inc · 1982
Page 0643 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
f
10/31/89 9:56
F130 F133
F134 F135 F138 F13A
Fl 3B
F13D F13E F13E F13F F140 F141 F142 F143 F145 F146 F147
F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148
F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F148 F14A F14B F140 F150 F152 F154 F156 F157 F15A FiSC F150 F160 F162 F162 F163 F166 F168 F16A
1 6C
20 30F1 48 68 DD 8000 D003 88 DØFØ 60 48 8A 4A 4A 4A 05 82 AA 68 60
AB 20 88 FØ6A BD SCCØ 10FB 49 05
00F 4
EA BD 8CC0 10FB 09 AA
DØF 2
AO 55 EA BD 8CCØ 10FB C9 AD
DOE 6
CXDRTS DRVINDX
HD:Apple ///:ROM - Disk I/O
JSR
CKDRTS
PHA
PLA
CMP
Q6L,X
BNE
CKDRTS
DEY
BNE
CHEORV1
RTS
PHA
TXA
LSR
A
LSR
A
LSR
A
ORA
IBDRVN
TAX
OLA
RTS
DELAY
HAS SHIFT REG CHANGED? ; YES, MOTOR IS MOVING
NO, DEC RETRY COUNTER ; AND TRY 256 TIMES ; THEN RETURN
; PRESERVE ACC. GET SLOT(*$10)/8
FOR DRIVE 0 OR i INTO X FOR INDEX TO TABLE RESTORE ACC.
NOTE: FORMATTING ROUTINES NOTE INCLUDED FOR SOS
******************** *****
READ SUBROUTINE
*
(16-SECTOR FORMAT) *
*************************
READS ENCODED BYTES * INTO NBUF1 AND NBUF2 *
FIRST READS NBUF2 HIGH TO LOW,
THEN READS NBUF1 LOW TO HIGH.
OH ENTRY
X-REG: SLOTNUM TIMES $10.
READ MODE (Q6L, Q7L
4- eeM L
'"
CARRY SET IF ERROR
IF NO ERROR: A-REG HOLDS $AA. X-REG UNCHANGED. Y-REG HOLDS $00. CARRY CLEAR. CAUTION
OBSERVE N0 PAGE CROSS
WARNINGS ON SOME BRANCHES!!
¡ i USEC CYCLE TIME
READ16 RSYNC RD1 RSYNC1 RD2
RD3
LDY
#20
DEY
; MUST FIND' COUNT. IF CANT FIND MARKS.
BEG
RDERR
THEN EXIT WITH CARRY SET
LOA
Q6L,X
READ NIBL.
BOL
ROI
*** NO PAGE CROSS!
EOR
#0D5
DATA MARMi?
BNE
RSYNC
LOOP IF NOT.
NOP
DELAY BETWEEN NTBLS.
LOA
Q6L,X
BPL
R02
NO PAGE CROSS! ***
CMP
#ØAA
DATA MARl< 2?
NNE
RSYNC1
(IF NOT, IS IT 0Ml?)
LDY
#055
INIT NBUF2 INDEX.
ADDED NIBL DELAY)
NOP
DELAY BETWEEN NIBLS.
LDA
Q6L,X
BPL
RD3
CMP
#ØAD
* ¡
NO PAGE CROSS!
¡ DATA MARX 3?
NNE
RSYNC1
; (IF NOT, IS IT DM1?)
(CARRY SET IF DM3!)
Page
I
Apple Computer Inc · 1982
Page 0644 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
f
10/31/89 9:56
F16C F16D F16E F171 F173 F176 F179 F178 F17D F17E F180 F181 F184 F186 F189 F18C F18E F190 F192 F194 F195 F198 F19A
Fi 9D
F19E
F 1AØ
F1A3
F 1A5
F1A7 F1AA F 1AA
F 1AA
F 1AA
F lAC
F lAB
F1BØ F1B2 F1B3 F184 F1B4 F1B7 F188
F189 F189 F189 F1B9 F189 F1B9 F189 F1B9 F189 F1B9 F1B9 F189 F189 F1B9 F1B9 F189 F1B9 F1B9 F1B9 F189 F1B9 F1B9 F1B9 F1B9 F1B9 F189
F lB 9
F189 F1B9 F1B9 F189 F1B9 F189 F1B9 F139 F189 FÌB9 F1B9 F189 F1B9 F189 F1B9 F1B9 F1B9 F189 F189 F1B9 F189
EA EA BD 8CC0 10FB 99 0203 AD EFFF 05 83 1037 88 10KB CB BO 6CC0 10FB 99 0002 AD EFFF 05 83 1024 C0 E4 DØEC CB BD SCCØ 10FB 99 0002
CB
DØF5 BD 8CCØ 10FB 85 96 20 01F2
24 8B 1004 24 8F 1001 58 60
20 AAF2 38 60
HD:Apple ///:ROM - Disk I/O
NOP
NOP
RD4
LOA
BPL
STA
LDA
ORA
BPL
DEY
BPL
RD5
INY
RD5A
LOA
BPL
STA
LDA
ORA
BPL
CPY
BNE
INY
8D6
LOA
BPL
STA
INY
BNE
RDCKSUM LOA
BPL
STA
JSR
Q6L,X RD4 NBUF2,Y INTERUPT IMASK GOSERV
RD4
Q6L,X RD5A NBUF1,Y INTERUPT IMASK GOSERV #0E4 RD5
Q6L,X RD6 NBUF1,Y
RD6 Q6L,X RDCKSUM CKSUM RDA6
DELAY BETWEEN NIBLS. DELAY BETWEEN NIBLS.
NO PAGE CROSS! *** STORE BYTES DIRECTLY POLL INTERRUPT LINE (THIS MAY BE USED TO INVALIDATE POLL) INDEX TO NEXT (FIRST TIME Y'=ø) ; GET ENCODED BYTES OF NBDF1
POLL INTERRUPT LINE ; (THIS MAY BE USED TO INVALIDATE POLL)
WITHIN i MS OF COMPLETION?
NO POLL FROM NOW ON
FINISH OUT NBUF1 PAGE GET CHECKSUM BYTE.
CHECK BIT SLIP MARKS
CHECK FOR INTERRUPTS
CHKINT
BIT
IMASK
8PL
$010
BIT
08F
BPL
$020
$010
CLI
$020
RTS
SHOULD INTERRUPTS BE ALLOWED? YES, ALLOW THEM.
GOSERV
JSR
SERVICE
RDERR
SEC
RTS
GO TO SERVICE INTERRUPT
READ ADDRESS FIELD
*
SUBROUTINE
*
(16-SECTOR FORMAT)
*
READS VOLUME, TRACK *
AND SECTOR
*
ON ENTRY
*
XREG: SLOTNUM TIMES $10 *
HEAD MODE (Q6L, Q7L)
*
OH EXIT ----
*
CAREY SET IF ERROR
*
IF NO ERROR:
*
A-REG HOLDS $AA.
*
Y-REG HDLOS $0g.
*
X-REG UNCHANGED.
*
CARRY CLEAR.
:
CSSTV HOLDS CHKSUM, *
SECTOR, TRACK, AND *
VOLUME READ.
*
USES TEMPS COUNT, LAST, CSUM, AND 4 BYTES AT CSSTV.
EXPECTS
ORIGINAL 10-SECTOR NORMAL DENSITY NIBLS
(4-BIT), ODD BITS, THEN EVEN
CAUTION
OBSERVE N0 PAGE CR055'
WARNINGS ON
Page 6
I
Apple Computer Inc · 1982
Page 0645 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
'10/31/89 9:56
F1B9 F1B9 F1B9 F1B9 FIB9 F1B9 F1B9 F1B9 F1B9 F1BB F1BD FiBS FiCO F1C2 F1C4 F1C7 F1C9 F1CB F1CD FiCE F101 F103 F1D5 F107 F1D9 F1D9 F1DC F1DE F1EØ F1E2 F1E2 F1E3 F1E5 FiEl FlEA F1EC FlED FiEF F1F2 F1F4 F1F6 F1F9 F1FB F1FC FiFE F1FF F201 F204 F206 F208 F2ØA F2ØB F205 F210 F212 F214 F215 F216 F216 F216 F216 F216 F216 F216 F216 F216 F216 F216 F216 F216 F216 F216
F216 F216 F216 F216 F216 F216 F216 F216 F216 F216 F216 F216 F216 F216 F216 F216 F216 F216
A0 FC 84 95 C8 0004 E6 95 FØF3 BD 8CCØ 10FB C9 05 DØFØ EA BD 8CC0 10FB C9 AA DØF2 AO 03
BD 8CC0 10FB C9 96 DØE7
78 A9 00 85 89 BD 8CCØ 10FB 2A 85 95 BD ECCO 10FB 25 95 99 97 00 45 89 88 10E7 A8 DØB6 BD ECCO 10FB C9 DE D0AD EA BD 8CCØ 10FB C9 AA DØA3 18 60
HD:Apple /ll:ROM - Disk I/O
SOME BRANCHES!!
*
*
;
;
---- ASSUMES
*
*
¡
i USEC CYCLE TIME
*
*
RDADR16 ROASYN RDA1 RDASN1 RDA2
RDA3
;
RDAFLO RDA4 RDA5
RDA6
RDA7 RDEXIT WEXIT
LDY
#ØFC
STY
COUNT
'MUST FIND COUNT.
INY
BNE
RDA1
LOW ORDER OF COUNT
INC
COUNT
BEQ
RDERR
; (2K NIBLS TO FIND ADR MARK, ELSE ERA)
LOA
Q6L,X
; READ NIBL.
BPL
RDA1
NO PAGE CROSS! ***
CMP
#0D5
ADE MARK i?
NNE
RDASYN
NOP
; (LOOP IF NOT) ; ADDED NIBL DELAY
LDA
Q6L,X
BPL
RDA2
NO PAGE CROSS! ***
CMP
#ØAA
ADE MARK 2?
BNE
RDASN1
(IF NOT, IS IT AMi?)
LDY
#03
INDEX FOR 4-BYTE READ
(ADDED NIBL DELAY)
LOA
Q6L,X
BPL
RDA3
ND PAGE CROSS! ***
CMP
#96
ADR MARK 3?
BNE
RDASN1
(IF NOT IS IT AMi?)
(LEAVES CARRY SET!)
SEI
DISABLE INTERRUPT SYSTEM
LOA
#00
INIT CHECKSUM
STA
CSUM
LDA
Q6L,X
READ 0D0 BIT' NIBBL
BPL
RDA4
ROL
A
;
NO PAGE CROSS! ***
¡ ALIGN ODD BITS, 1' INTO LSB
STA
LAST
LOA
Q6L,X
¡ (SAVE THEM) READ EVEN BIT' NIBL
BPL
ROAS
* NO PAGE CROSS ***
AND
LAST
; MERGE ODD AND EVEN BITS
STA
CSSTV,Y
; STONE DATA BYTE
EON
CSUM
DEY
BPL
RDAFLO
LOOP ON 4 DATA BYTES.
TA?
IF FINAL CHECKSUM
ENE
EDEER
NONZERO, THEN ERROR
LOA
Q6L,X
BPL
RDA6
FIRST BIT SLIP NIBBL " NO PAGE CROSS! *
CMP
#ØDE
BNE
RDERR
ERROR IF NONMATCH
NOP
LOA
06L,X
BPL
RDA7
; DELAY ; SECOND BIT-SLIP NIBL
ND PAGE CROSS! ***
CMP
#ØAA
BNE
RDERR
ERROR IF NOMATCH
CLC
CLEAR CARRY ON
RTS
; NORMAL READ EXITS.
A ;
;
WRITE SUBE
A
; (16-SECTOR FORMAT) A
*
;;AAA*A******************
*
WRITES DATA FROM *
;
NBUF1 AND NBUF2 *
A
¡ FIRST NBUF2,
A
HIGH TO LOW.
A
; THEN NBUF1,
*
;
LOW TO HIGH
*
* ;
; ---- ON ENTRY ---- *
A ;
; X-REG SLOTNUM
A
;
TIMES $10
A
* ;
* ;
; ---- ON EXIT ---- *
* ;
CARRY SET IF ERROR. *
; (W PROT VIOLATION) A
; IF NO ERROR:
¡
¡
A-REG UNCERTAIN.
X-REG UNCHANGED.
;
Y-REG HOLDS $00.
;
CARRY CLEAR.
Pagel"
./
Apple Computer Inc · 1982
Page 0646 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
10/31/89 9:56
F216 F216 F216 F216 F216 F216 F216 F216 F217 F218 F218 F213 F21E F220 F222 F225 F228 F22A F223 F22C F22D F22E F22F F232 F233 F235 F237 F23A F23C F23F F241 F244 F246 F247 F248 F249 F24B F24E F250 F251 F253 F255 F258 F253 F25E F25F F261 F262
F264 F267 F269 F26A F2SC F26E F26F F272 F275 F278 F27A F27C F270 F27E F27F F280 F281 F282 F285 F258 F283 F280 F28E F290 F292 F295 F296 F297 F29A F29D F29E F2AØ F2A2 F2A3 F2A6 F2A9 F2AA F2AA F2AD F2BØ F232 F2B4
38 B8
BD 8DCØ BD 8ECØ 30F5
A9 PS' 9D 8FCØ
1D 8CC0 AO 04 EA 48
68 48 68
20 BBF2 88 DØF8 A9 D5 20 BAF2 A9 AA 20 BAF2 A9 AD 20 BAF2 A0 55 EA EA EA 0008
AD HE'S'S'
05 83 38 1057 3000 B9 0203 9D 8DCØ BD 8CCØ 58 1ØEA 98 3003 AD EFFF 05 SB 38 3002 103C C8 39 0002 9D 8DCØ BO 8CCØ C0 E4 00ES EA CS EA EA 48 68 39 0002 90 8DCØ BD 8CCØ A5 96 C8 DONE F000 20 BBF2 48
68
B9 CØF3 20 BDF2 C8 CO 04 DØF5 18 BD 8ECØ BD 8CCØ 60
2C 54F3 20 A3F2 A5 8F 1002 85 83
HD:Apple ///:ROM - Disk I/O
*
---- ASSUMES ---- *
*
i USEC CYCLE TIME *
*
Page 8
¡
WRITE16
SEC
CLV
WRIT1 WSYNC
WINTRPT VRYFRST WRTFRST WNTRPT1 WMIDLE WOATA2
WOATA3
WRCKSUM WRBITSLMÌ( NOWRITE
LOA LOA BMI LOA STA ORA LOY NOP PEA PLA PEA PLA JSR DEY BNE LOA JSR LOA JSR LOA JSR LDY NOP NOP NOP BNE LOA ORA SEC BPL 3Ml LDA STA LDA DEY BPL TYA SMI LOA DRA SEC BMI BPL INY LDA STA LOA CPY BNE HOP
INY NOP HOP PHA PLA LOA STA LOA LOA INY BNE BEG JSR PHA PLA LDA JSR INY CPY BNE CLC LDA LDA RTS
Q6H,X Q7L,X WEXIT tOFF Q7H,X Q6L,X #04
WNIBL7
WSYNC #005 WNIBL9 #ØAA WNIBL9 #ØAD WNIBL9 #55
VRYFRST INTERUPT IMASK
SERVICE WRTFRST NBUF2,Y Q6H,X Q6L,X
WINTPPT
WMIDLE INTERUPT IMASK
WDATA2 SERVICE
NBUF1,Y Q6H,X Q6L,X #ØE4 WNTRPT1
NBUF1,Y 06H,X 06L,X CKSUM
WDATA3 WRCKSUM WNIBL7
BITSLIPMK,Y WNIBL
#04 WRBITSLMK
Q7L,X Q6L,X
ANTICIPATE WPROT ERR. TO INDICATE WRITE PROTECT ERROR INSTEAD OF INTERRUPT
SENSE WPROT FLAC. BRANCH IF' WRITE PROTECTED SYNC DATA. (5) GOTO WRITE MODE
(4)
(2) FOR FIVE NIBLS
(2)
(4)
(3)
(4) EXACT TIMING
(3)
(13,9,6) WRITE SYNC
(2)
(2*)
;
MUST NOT CROSS PAGE!
(2) iST DATA MARK
(15,9,6)
(2) 2ND DATA MARK
(15,9,6) (2) 3RD DATA MARK
(15,9,6) (2) NBOF2 INDEX (2) FOR TIMING
(2)
(2)
(3) BRANCH ALWAYS (4) POLL INTERRUPT LINE
(3)
(2)
(2) BRANCH IF INTERRUPT HAS OCCURED (3) FOR TIMING.
(4)
(5) STORE ENCODED BYTE (4) TIME MUST = 32 US PER BYTE!
(2)
(3) (2 IF BRANCH NOT TAKEN) (2) INSURE NO INTERRUPT THIS BYTE (3) BRANCH ALWAYS. (4) POLL INTERRUPT LINE
(3)
(2)
(3) BRANCH IF NO INTERRUPT
GO SERVICE INTERRUPT.
(2)
(4)
(5) STORE ENCODED BYTE
(4)
(2) WITHIN i MS OF COMPLETION? (3) (2) NO KEEP WRITTING AND POLLING.
(2)
; (2) (2)
; (2) (4)
(3)
; (4) WRITE LAST OF ENCODED BYTES ; (5) WITHOUT POLLING INTERRUPTS.
; (4)
(3) NORMALLY FOR TIMING
¡ (2)
; (3) (2)
¡ (3) BRANCH ALWAYS ; (13,9,6) GO WRITE CHECK SUM!!
; (3)
(4)
(4) LOAD BIT SLIP MARK
; (6,9,6) (2)
; (2)
; (2) (3)
; (2)
DUT OF WRITE MODE
;
; TO READ MODE. ; RETURN FROM WRITE
SERVICE BIT
SEV
SET VFLAG TO INDICATE INTERRUPT
JSR
NOWRITE
TAKE IT OUT OF WRITE MODE!
;
LDA
08F
BPL
$010
STA
IMASK
1
Apple Computer Inc · 1982
Page 0647 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
10/31/89 9:56
F2B6 F2B8 F2B9
F 2BA
F2DA F2BA
F 2BA
F 2BA
F 2BA
F2BA
F 2BA
F 2BA
F 2BA
F 2BA
F2BB F2BC F2BD F2CØ F2C3 F2C4 F2C4 F2C4 F2C4 F2C4 F2C4 F2C4 F2C4 F2C4 F2C4 F2C4 F2C4 F2C4 F2C4 F2C4 F2C4 F2C4 F2C4 F2C4 F2C4 F2C4 F2C4 F2C4 F2C4 F2C4 F2C4 F2C4 F2C4 F2C4 F2C6 F2C8 F2C9 F2CB F2CC F2CF F200 F2D3 F2D6 F2D7 F2D9 F2DB F2DD F2DE F2EØ F2E2 F2E5 F2E7 F2E8
F2 EH
F2EE F2F1 F2F2 F2F4 F2F6 F2F9
F2 FA
F2FD F300 F303 F304 F306 F307
F 30A
F30C F30F
F 30F
F30F
F 30F
F3ØF F3ØF '30F
C6 8F 58 60
18 48 68 9D 8DCØ iO 8CC0 60
A2 02 A0 00 88 Bi 9B 4A 3E 0103 4A 3K 0103 99 0102 E8 E0 56 90KO A2 00 98 DØE8 AØ 56 59 0003 29 3F AA BD 55F3 99 0103 B9 0003 88 DØEE 29 3F 59 0102 AA BD 55F3 99 0002 B9 0102 C8 OØFØ AA BD 55F3 85 96 4C 4CF3
$010
HD:Apple i/:ROM - Disk I/O
DEC
08F
CLI
RTS
COULD NOT HAVE GOT HERE WITHOUT CLI OK
7HIT NIBL WRITE StJBRS *
AREG OR'D PRIOR EXIT * CARRY CLEARED
WNIBL9
CLC
WNIBL7
PHA
PLA
WNIBL
STA
Q6H,X
ORA
Q6L,X
RTS
; (2) 9 CYCLES, THEN WRITE (3) 7 CYCLES, THEN WRITE
; (4)
; (5) NIBL WRITE SUB ¡ (4) CLOBBERS ACC. NOT CARRY
PRENIBILIZE SUBR
*
(16SECTOR FORMAT)
*
****** **********************
CONVERTS 256 BYTES OF
*
tiSER DATA IN (BUE) INTO *
ENCODED BYTES TO BE
*
WRITTEN DIRECTLY TO DISK *
ENCODED CHECK SUM IN
*
ZERO PAGE 'CKSUM'
*
ON ENTRY
*
BOF IS 2BYTE POINTER *
TO 256 BYTES OF USER *
DATA.
*
AREG CHECK SUM.
*
XREG UNCERTAIN
*
YREG HOLDS 0.
*
CARRY SET.
*
******** ********************
PRENIB16 PRENIB1
PRENIB3 PRENIB2
PRENIB4
LDX LDY DEY LOA LSR ROL LSR
ROL STA INX CPX BCC LOX TYA BNE LDY EOR AND TAX LOA STA LOA 0E? BNE AND EOR TAX LDA STA LDA IN? BNE TAX LOA STA JMP
#02 #00
(BUF),Y
A NBUF2-1,X A NBUF2-1,X NBUF1+1,Y
#56 PRENIB1 #00
PRENIB1 #56 NBUF2-2,Y #03F
NIBL,X NBUF2-1,Y NBUF2-2,Y
PRENIB3 #3F NBOF14-1,Y
NIBL,X NBUF1,Y NBUF1+1,Y
PRENIB4
NIBL,X CKSUM SET1MEG
**************************
¡
POSTNIBLIZE SUBR
*
16SECTOR FORMAT
*
START NBUF2 INDEX. START USER BUF INDEX. NEXT USER BYTE
SHIFT TWO BITS OF CURRENT USER BYTE INTO CURRENT NBUF2
;
BYTE. (6 BITS LEFT). FROM 0 TO $55
; BR IF NO WRAPAROUND RESET NBUF2 INDEX USER BOF INDEX
;
(DONE IF ZERO(
;
(ACC=Ø FOR CHECK SUM) COMBINE WITH PREVIOUS STRIP GARBAGE BITS TO FORM RUNNING CHECK SUM GET ENCODED EQUIV. REPLACE PREVIOUS RESTORE ACTUAL PREVIOUS
LOOP UNTIL ALL OF NBUF2 IS CONVERTED.
; NOW DO THE SAME FOR NIBBLE BUFFER i TO DO ANY BACK TRACKING (NBUF1-1(
RECOVER THAT WHICH IS NOW 'PREVIOUS'
USE LAST AS CHECK SUM
ALL DONE.
"s
Page 9
I
Apple Computer Inc · 1982
Page 0648 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
t
10/31/89 9:56
HD:Apple i/:ROM - Disk I/O
Page 10'
F30F
F3ØF 38
POSTNIB16 SEC
F310 A0 55
LOY
#55
FIRST CONVERT To 6 BIT NIBBLES
F312 A9 00
LOA
#00
INIT CHECK SUM
F314 F317 F31A F310 F31F
BE 0203 SII 00F3 3030 99 0203 88
PNIBL1
LOX
NBUF2,Y
EOP.
DNIBL,X
BMI
SET1MEG
STA
NBUF2,Y
DEY
GET ENCODED BYTE
SET 1 MHZ REPLACE WITH 6 BIT EQUIV.
F320 10A6 F322 C8
BPL
PRENIB1
INY
; LOOP UNTIL DONE WITH NIBBLE BUFFER 2 NOW Y=0
F323 BE 0002
PNIBL2
LOX
NBUF1,Y
00 THE SAME WITH
F326 5D 00F3
EOR
DNIBL,X
F329 99 0002
STA
NBUF1,Y
NIBBLE BUFFER 1
F320 C8 F32D D0F4 F32F A6 96
INI
NNE
PNIBL2
LOX
CKSUM
DO ALL 256 BYTES MAKE SURE CHECK SUM MATCHES
F331 5D 00F3 F334 0016
SOR
DNIBL,X
BNE
POSTERR
BETTER BE ZERO BRANCH IF IT IS
F336 A2 56
POSTi
LOX
#56
INIT NRUF2 INDEX
F338 CA F339 30FB
POST2
OEX
BMI
POSTi
NBUF lOX $55 TO $00 WRAPAROUND IF NEO
F33R B9 0002 F33E 5E 0203
LOA
NBUF1,Y
LSR
NBUF2,X
SHIFT 2 BITS FROM
F341 2A
ROL
A
CURRENT NBUF2 NIBL
F342 5E 0203
LSR
NBUF2,X
CURRENT NBUF1
F345 2A F346 91 98
ROL
A
STA
(BUF),Y
NIBL. BYTE OF USER DATA
F348 08 F349 DOED
INY
BNE
POST2
NEXT USER BYTE
F34B F340 F340 F34F
18 F34C AD DFFF 09 80
POSTERA SET1MEG
CLC
.EQU LOA ORA
*
ENVIRON #ONEREG
GOOD DATA SET TO ONE MEGAHERTZ CLOCK RATE
F351 80 DFFF
STA
ENVIRON
F354 60
SEV
RTS
(SEV USED TO SET VFLAG)
F355
F355
F355
F355
6-NIT TO 7-BIT
"
F355 F355
¡ NIBL CONVERSION TABLE *
F355
F355
F355
CODES WITH MORE THAN *
F355
ONE PAIR OF ADJACENT *
F355 F355
ZEROES OR WITH NO * ADJACENT ONES (EXCEPT *
F355
87) ARE EXCLUDED. *
F355
F355
**************************
F355
F355 96 97 9A 9B 9D 9E 9F )IRL .BYTE 96,97,9A,9B,9O9E,9F,ØA6,ØA7,ØAB,ØAc,ØAD,ØAS,ØAy,ØB2,ØB3,øB4,øB5 F3SC A6 A7 AB AC AD AS AF
F363 B2 B3 84 B5
F367 B6 B7 B9 BA BB BC BD
.BYTE 0B6,0B7,0B9,ØBA,ØBB,ØBC,ØBD,ØBE,ØBF,ØCB,ØCD,ØCE,0CF,0D3,0D6,0D7
F365 BE BF CB CD CE CF 03
F375 D6 D7
F377 09 DA DB DC DO DE DF
.BYTE 0D9,0DA,ØDB,ØDC,ØDD,ØDE,ØDF,0E5,0E6,0E7,0E9,ØEA,0EB,ØEC,ØED,OEE
F375 55 56 57 59 EA ER EC
F385 ED EE
F387 EF F2 F3 F4 F5 F6 F7
.BYTE ØEF,ØF2,0F3,ØF4,ØF5,0F6,ØF7,ØF9,ØFA.ØFB,ØFC,ØFD,ØFE,ØFF
F385 F9 FA FR FC FD FE FF
F395
F395
* *****
F395
F395
7-BIT TO 6-BIT
*
F395
DENIBLIZE TABL
*
F395
(16-SECTOR FORMAT> *
F395
F395
VALID CODES
*
F395
$96 TO 8FF ONLY.
*
F395
F395
F395
CODES WITH MORE THAN *
F395
ONE PAIR OF ADJACENT *
F395
ZEROES OR WITH NO
F395
ADJACENT ONES (EXCEPT *
F395 F395
BIT 7) ARE EXCLUDED * **************************
F395
F395 F300
DNIBL
.EQU
REGRWTS+300
F395 01 00 01
.BYTE 01,00,01
F398 98 99 02 03 9C 04 05
.BYTE 98,99,02,03,9C,04,05,06,0A0,0A1,0A2,0A3,0A4,0A5,07,08,0A8
F39F 06 AN Al A2 A3 A4 AS
F3A6 07 08 A8
F3A9 A9 AA 09 ØA 0H OC HO
.BYTE 0A9,0AA,09,HA,ØB,ØC,ØO,0B0,0B1,ØE,HF,iH,11,12,13,0B8,14,15
F3BO BN Bi 0E 0F 10 11 12
F 3B 7 13 B8 14 15
F 3BB 16 17 18 19 lA
.BYTE 16,17,18,19,1A
1
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
/
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Page 11
F 3C0 DE AA SB FF C4 C5 C6 BITSLIPMI< .BYTE ØDE,ØAA,ØEB,ØFF,0C4,0C5,0C6,0C7,0C8,0C9,ØCA,1B,ØCC,IC,1D,1E
F3C7 C7 C8 C9 CA lB CC 1C
F3CE 1D lE
F3DØ D0 Dl 02 1F D4 D5 20
.BYTE ØDØ,ØD1,0D2,1F,0D4,0D5,20,21,0D8,22,23,24,25,26,27,28,ØEØ,ØE1
F3D7 21 D8 22 23 24 25 26
F 3DE 27 28 E0 El
F 3E2 E2 E3 El 29 2A 2B E8
.BYTE 0E2,0E3,0E4,29,2A,2B4OE8,2C,2D,2E,2F,30,31,32,0F0,0F1,33,34
F3E 9 2C 20 2E 2F 30 31 32
F 3F0 F0 F1 33 34
F3F4 35 36 37 38 F8 39 3A
.BYTE 35, 36, 37, 38,0F8, 39, 3A, 3B,3C, 3D,3E, 3F
F 3FB 3B 3C 3D 3E 3F
F400 F400
A*** ********************k
F400
*
F400
FAST SEEK SUBROUTINE
F400 F400
*********************A***
F400
*
F400
ON ENTRY ---- *
F400
F400
X-REG HOLDS SLOTNIJM *
F400
TINES $10
*
F400
F400
A-REG HOLDS DESIRED *
F400
HALFTRACK.
*
F400
F400
CURTRK HOLDS DESIRED *
F400
HALFTRACK.
*
F400
F400
ON EXIT
F400
F4 øø
A-REG UNCERTAIN.
F400
Y-REG UNCERTAIN.
F400
X-REG UNDISTURBED.
F400
F400
CURTRK AND TREN HOLD
F400 F400
FINAL HALFTRACK.
F400
PRIOR HOLDS PRIOR
F400
HALFTRACK IF SEEK
F400
WAS REQUIRED.
F400
F400
MONTIMEL AND MONTIMEH
F400
ARE INCREMENTED BY
F400
THE NUMBER OF
F400
100 USED QUANTUMS
F400
REQUIRED BY SEEK
F400
FOR MOTOR ON TIME
F400
OVERLAP.
F400
F400
VARIABLES USED
F400
F400
CORTEX, TREN, COUNT,
F400
PRIOR, SLOTTEMP
F400
MONTIMEL, MONTIMEH
F400
F400
; *************************
F400
F400 85 9E
SEEK
STA
TREN
SAVE TARGET TRACK
F402 C5 8C
CM?
CURTRE
ON DESIRED TRACK?
F404 F042
BEQ
SE TP HA SE
YES, ENERGIZE PHASE ANO RETURN
F406 A9 00
LDA
#00
F408 85 95
STA
TRKCNT
HALFTPACK COUNT.
F40A A5 8C
SEEK2
LDA
CURTRK
SAVE CURTEI< FOR
F40C 85 90
STA
PRIOR
DELAYED TURN OFF.
F4ØE 38
SEC
F4ØF E5 9K F411 F031
SBC
TREN
BEO
SEEKEND
DELTA-TRACKS. BR IF CURTRK'OESTINATION
F413 BOO 6
BCS
OUT
(MOVE OUT, NOT IN)
F415 49 FF
EUE
80FF
CALC TEKS TO GO.
F417 E6 8C
INC
CURTRE
DECR CURRENT TRACK (OUT)
F419 9004
BCC
MINTST
(ALWAYS TAKEN).
F41B 69 FE F41D C6 8C
OUT
ADD
#ØFE
DEC
CURTEX
CALC TRACES TO GO. DECR CURRENT TRACK (OUT)
F41F C5 95
MINTST
CMP
TRKCNT
F421 9002
BCC
MAXTST
AND TRKS MOVED'
F423 A5 95
LDA
TRKCNT
F425 C9 09
MAXTST
CMP
809
F427 B002
BCS
STEP2
IF TRKCNT>$08 LEAVE Y ALONE (Y=$Ø8)
F429 A8
STEP
TAY
ELSE SET ACCELERATION INDEX IN Y
F42A 38
SEC
F4 2B 20 48F4
STEP2
JSR
SETP HASE
F42E B9 67F1
LDA
ONTABLE, Y
FOR 'ONTIME
F431 20 56F4
35E
MS MAT T
(100 USEC INTERVALS)
F434 AS 9D
LDA
PRIOR
F436 18
CLC
FOR PHASE OFF
F437 20 4AF4
JSR
CLRP HASE
TURN OFF PRIOR PHASE
F43A B9 70F4
LDA
OFFTABLE, Y
THEN WAIT OFFTIME'
F43D 20 56F4
JSR
MS WAIT
(100 USEC INTERVALS)
F440 56 95
INC
TRKCNT
'TRACKS MOVED COUNT.
/
Apple Computer Inc · 1982
Page 0650 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
f-
10/31/89 9:56
HD:Apple /fl:ROM - Disk I/O
F442 F444 F447 F448
F4 4A
F44C F44D F44F F450 F453 F455 F456 F456 F456 F456 F456 F456 F456 F456 F456 F456 F456 F456 F456 F456 F456 F456 F456 F456 F456 F456 F456 F456 F456 F456 F456 F456 F456 F456 F456 F456 F456 F458 F459 F45B F450 F45F F461 F462 F464 F466 F467 F467 F467 F467 F467 F467 F467 F467 F467 F467 F46E F470 F477 F479 F479 F470 F470 F47E F47F F481 F482 F484 F485 F487 F488 F48B F480 F490 F492 F494 F496 F498
F4 9B
F49D F49F F4A0 F4AØ F4A7
4A8
DOC 6
20 56F4 18 A5 BC 29 03 2A 05 81 AA BD 8000 A6 81 60
A2 11 CA DOFD E6 99 0002 E6 9A 38 E9 01 DØFØ 60
01 30 28 24 20 lE 10 1C 1C 70 2C 26 22 1F lE 10 1C 1C 86 83 AO 05 48 ØA 26 83 88 DØFA 68 29 07 A8 B9 AØF4 85 84 20 ØOFØ 0000 E6 86 E6 84 E6 84 20 ØØFØ C6 86 AS 88 60 00 04 08 OC 01 05 09 00
SEEKEND SETPHASE CLRPHASE
SEEKRTS
ÑA AA **
ONE
SEEK2
JSR
MSWAIT
CLC
LDA
CURTRÌ(
AND
#03
ROL
A
ORA
IESLOT
TAX
LOA
PHASEOFF,X
LDX
IBSLOT
RTS
AA AA ** AA AA **AA
(ALNAYS TAKEN) SETTLE 25 MSEC SET FOR PHASE OFF GET CURRENT TRACK MASK FOR 1 AND 4 PHASES DOUBLE FOR PHASE ON/OFF INDEX
TURN ON/OFF ONE PHASE ; RESTORE X-REG
AND RETURN
MSWAIT SUBROUTINE AA AA At At At At AA AA At At AttA AAA
DELAYS A SPECIFIED NUMBER OF 100 USEC INTERVALS FOR MOTOR ON TIMING
ON EXIT
A-REG HOLDS $00 X-REG HOLDS $00 Y-REG UNCHANGED CARRY SET
MONTIMEL, MONTINEH ARE INCREMENTED ONCE PER 100 USEC INTERVAL FOR MOTOR ON TIMING
ASSUMES
i USEC CYCLE TIME ** AA AA At ** **** ** At At A*AA
MENAIT
LDX
#11
MENi
DEX
BNE
MSW1
INC
MONT IMEL
BNE
MSW2
INC
MONT IMEH
MSW2
SEC
SOC
#01
BNE
MENAI T
RTS
At AA AA AA At AA ** ** At At **AA A
DELAY 86 USEC
DOUBLE BYTE INCREMENT
DONE IN INTERVALS (A-REG COUNTS)
PHASE UN-, OFF-TIME * TABLES IN 100-USEC * INTERVALS. (SEEN)
AA AA ** ** **
*A** ** **** *
ONTABLE OFFTABLE
.BYTE .BYTE
ø1,30,28,24,20,1E, 1D,1C, 1C 70,2C,26,22,1F,1E1D,1C,1C
B LOCK IO TRK SEC
QUIT SECTABL
STX LOY PHA ASL ROL DEY BNE PLA AND TAY LDA STA JSR BCS INC INC INC JSR DEC LOA RTS
.BYTE
IBTRK #05
A IBTRK
TRKSEC
#07
SECTAEL, Y INSECT REGR NT S QUIT IBBUFP+1 IBSECT INSECT
RE GR MT S
IBBUFP+i IB STAT
00,04,08,ØC,0i3O5,09,ØO
Page 12
I
Apple Computer Inc · 1982
Page 0651 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
f
10/31/89 9:56
F4A8 F4A8 F4A8 F4A8 F4A8
F 4A8
F4A8 F4A8 F4A8 F4A8 F4A8 F4A8 F4A8 F4A8 F4A8 F4A8 F4A8 F4A8 F4A8 F4A8 F4A8 F4A8 F4A8
F 4AB
F 4AE
F4B1 F4B3 F4B6 F4B8 F4B9 F4BC F4BF F4C1 F4C4 F4C5 F4C5
FFD9 FFD8 FFD9 C066
F4A8 80 D9FF AD EFFF 2D 66C0 30F8 AD 66C0 300C 18 AD D9FF AC 08FF 1003 AD D9FF 60
HD:Apple ///:ROM - Disk I/O
JOYSTICK READ ROUTINE
*
ENTRY ACC= COUNT DOWN HIGH
X&Y=' DONT CARE
*
EXIT ACC TIMER HIGH BYTE *
Y TIMER LOW BYTE *
CARRY CLEAR
*
IF CARRY SET, ROUTINE
*
WAS INTERRUPTED &
*
ACC & Y ARE INVALID
*
** A * ** ** *** * A * ** ** ******** ** ** *
TIMLATCH TIMER1L TIMER1H JOYRDY ANALOG ANLOG1
G000TIME
EQU EQU EQU .EQU
EQU STA LOA AND BMI LDA BMI CLC LOA LDY BPL LDA RTS
ØFFD9 ØFFD8 ØFFD9 00066
A
TIMLATCH INTERUPT JOYRDY ANLOG1 JOYRDY 0000TIME
TIMER1H TIMER1L GOODTIME TIMER1H
CARRY SHOULD BE SET! START THE TIMER!
WAIT FOR ONE OR THE OTHER TO GO LOW
WAS IT REALLY THE JOPYSTICK? NOPE, WHAT TIME IS IT? TIMES A SLIP SLIDIN AWAY NOW, WHAT TIME IS IT?
TIME WAS VALID! HI BYTE CHANGED
.END
Page 13
SYMBOL TABLE DUMP
AB - Absolute RF - Ref PB - Public
LB - Label DF - Def PV - Private
UD - Undefined PR - Proc CS - Consta
MC - Macro FC - Func
ALDONE1 LB FØEB
BITSLIPM LB F3CØ
CHEINT LB F1AA
CORRECTV LB F004
CURTRK AB 008C
DRVERR LB £058
DVMOT AB 0050
GOODTIME LB F4C4
IBBUFP AB 0085
IBRERR AB 0083
IBTRK AB 0083
JOYRDY AB C066
MONTIMEL AB 0099
MSW2
LB F461
NIBL
LB F355
0K
LB F048
PHASEON AB C081
POSTi
LB F336
PRENIB16 LB F2CI
06H
AB CØ8D
ROl
LB F14D
RD5A
LB F181
ROA4
LB FiEl
RDAFLO LB F155
RDEXIT LB F214
RSYNC LB FilA
SEEK
LB F400
SEEKRTS LB F455
5EV
LB F354
TIMER1L AB FF08
TRKN1
AB 0099
TRYTRK2 LB FØ7F
WDATA3 LB £275
WNIBL7 LB F2BB
WRIT
LB FOF9
ALLDONE LB F0E3
BLOCETO LB F479
CKDRTS LB F13D
COUNT AB 0095
DISKIO PR ----
DRVINDX LB F135
ENVIRON AB FFDF
GOSEEK LB F115
IBCMD AB 0087
IBSECT AB 0084
IBWPER AB 0081
LAST
AB 0095
MOTDF LB F052
MSWAIT LB F456
NODRIVER LB F064
ONEMEG AB 0080
PHASON AB 0081
PDST2
LB F338
PRENIB2 LB F2E5
Q6L
AB CØ8C
R02
LB F157
RD6
LB F395
RDA5
LB FiEF
RDASN1 LB F109
RDRIGHT LB FØAC
RSYNC1 LB F152
SEEK1
LB F105
SERVICE LB F2AA
STEP
LB F429
TIMLATCU AB FF09
TRKSEC LB F475
TWOMEG AB 007F
WEXIT LB F215
WNIBL9 LB F2BA
WRIT1
LB F220
ALLOFF LB F118
BOF
AB 009B
CKSUM AB 0096
CSSTV AB 0097
DNIBL LB £300
ORVOEN AB CØ8A
ENVTEMP AB 009F
GOSERV LB F1B4
IBDERR AB 0082
IBSLOT AB 0081
IMASK AB 008B
MAXTST LB F425
MOTOROFF AB C088
MYSEEK LB F104
NOWRITE LB F2A3
ONTABLE LB F467
PHSOFF AB C080
POSTERR LB F34C
PPENIB3 LB F2E2
07H
AB 008F
RD3
LB £163
RDA1
LB F104
RDA6
LB F201
RDASYN LB FiaD
READ16 LB F148
RTTRI(
LB F000
SEEK2 LB F4ØA
SET1MEG LB F340
STEP2 LB F42B
TRACK AB 0099
TRYADR LB F083
VOLUME AB 009A
WINTRPT LB F24B
WNTDPT1 LB F264
WRITE16 LB F216
ANALOG LB FIAS
CHKDRV LB F12B
CLRPHASE LB FI4A
CSUM
AB 0089
DRIVSEL LB F035
DRVOTRE AB 0085
GOCAL LB FØA7
HNDLERR LB FØEA
IBDRVN AB 0082
IBSMOD AB 0089
INTERtJPT AB FFEF
MINTST LB F41F
MOTORON AB C089
NBUF1 AB 0200
NXOFF LB FilA
OUT
LB F41B
PNIBL1 LB F314
POSTNIB1 LB F30F
PRENIB4 LB F2F6
Q7L
AB 008E
RD4
LB F16E
RDA2
LB FiCE
RDA?
LB F20B
RDCKSOM LB F1AØ
REGRWTS LB F000
SECT
AB 0098
SEEKCNT AB 0094
SETPHASE LB F448
TEMP
AB 0097
TRKCNT AB 0095
TRYADR2 LB F08A
VRYFRST LB F253
WMIDLE LB F267
WRBITSLM LB F297
WRTFRST LB F255
Assembly complete:
1076 lines
0 Errors flagged on this Assembly
ANLOG1 LB FIAD
CHKDRV1 LB F120
CONWAIT LB F054
CSUM1
AB 0097
DRV1EN AB CØ8B
DRVWAIT LB F041
GOCAL1 LB FØA6
HRDERRS AB 0080
IBNDDRV AB 0080
IBSTAT AB 0088
IOBPDN AB 008A
MONTIMEH AB 009A
MSW1
LB F458
NBOF2
AB 0302
OFFTABLE LB F470
PHASEOFF AB COBO
PNIBL2 LB F323
PRENIB1 LB F2CB
PRIOR AB 0090
QUIT
LB F490
ROS
LB F180
RDA3
LB F109
RDADR16 LB F1B9
RDERR LB FiB!
RETRYCNT AB 0093
SECTABL LB F4AØ
SEEKEND LB F444
SETTRK LB F125
TIMER1H AB FF09
TREN
AB 009E
TRYTRK LB F069
WDATA2 LB F265
WNIBL LB F2BD
WRCKSUM LB F292
WSYNC LB F22D
6502 OPCODE STATIC FREQUENCIES
ADC
1m
AND
8 I
Apple Computer Inc · 1982
i
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
r
10/31/89 9:56
HD:Apple ///:ROM - Disk I/O
ASL: BCC: HCS: BEQ: BIT: BMI: BNE:
BPL :
BVC CLC
CLI CLV
CMP
CPX
CPY DEC
DEX
DEY
EOR: INC: INX:
INY :
JMP:
JSR :
LDA:
LDX :
LDY :
LSR:
MOP :
ORA: PHA:
PHP :
l'LA:
PLI' :
ROL: ROR: RTS: SMC: SEC:
SEI
STA STX
STY TAX
TAY
TXA
TYA:
3
10
7 8
3
10 38
281m 921')m 1m 14 I
4 5 2
13
8
10
2
12
2
39 86 M 12 18
9
13
9
10
4
11 3
7 6
16
2
91m 1m 42
I
31 51
311m
4
******
AA
A
** AA AA AA
At AA AA AA At AA At AA AA AA AA AA AA AA AA AtA
AA AttA ** ** AA At AA At At AttA
************
AAAA
*****A******A*AAAAAAA*AAA*AAAAAAAAAAAAAAAAA*A****A**AA ** A**A**A**A**AAA****
*******
** AA AA *
Minimum frequency
i
Maximum frequency = 86
Average frequency
10
Unused opcodes:
BRX BVS CLD RTI SED TSX TXS
Program opcode usage: 87 %
Page 14
(1.00) That's all, Folks
Apple Computer Inc · 1982
Page 0653 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple Computer Inc · 1982
Page 0654 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
'10/31/89 9:47
0000 0000 00go 0000 000g 0000 0000 00go 0000 0000 0000 0000 0000
HD:Apple ///:ROM - Sara Tests
; ggAgPPgLgEgIg/IggRgOgMg-dDIIAgGÍgNO1SdTgICdRgOÍUgTdINgEgSgggÍggggggggggsggggdgggg
;dggCgOgPgYRdIdGsHgTg19g7g9gBÍYgAgPgPgLEggCOgMgPgUaTgEgRg, IdNgC.gggggggggsgggggdgd4sdgd
.ABSOLUTE .PROC SARATESTS
SARA DIAGNOSTIC TEST ROUTINES DECEMBER 18,
0000 000g 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 F405
F4CC F4C0
F4CD
F4CF F400
F4D2 F403 F405 F406
F4D9
F4DA
F4DC
F400 F404 F406
F4E7 F408 F4E9 F400
F4OE
F4EE
0001 0000 0010 0018 0019
ØØ1A
0087 0085 0091 F479 0050 00FF 1419 1810 0000 0008 0010
CO58 C047
COSO
0051 C066
CODO
C0F1 CØF2 C0F3 0100 C200 C300 C400 CFFF FF00 FFDF FF02 FF03 FFEØ FFEF FF02 FF03 F025 FDØ7 F001' FBC7 F098 F090 F901
00 Bl B2 BA 09 10 00
13
F4CD
52 41
CD
52 4F
CD
56 49 Cl 41 43 49 Cl 41 2F
C4
44 49 41 47 4E 4F 53 54 49
C3
5A
00
52 45 54 52
09
W. B000DNER & R. LASHLEY COPYRIGHT 1979 BY APPLE COMPUTER, INC.
ROM ZRPG ZRPG1
PTRLO PTRHI
BNI< IBCMD
IBBUFP PREVTRX BLOCKIO
CV STK0 iONIc POPO KYBO
KEYBD KBDSTPB POLEN ADOS
ORNO
TXTMO
ADTO DISKOFF ACIAST ACIACM ACIACN SLT1 SLT2 SLT3 SLT4
EXPI4OM ZPREG SYSD1 SYSD2
SYS03 SYSEØ
BNKSW SYSE2
SYSE3 COOT CROUT1 KEYIN SETCVH CLDSTRT SETUP MONITOR
.EQU .EQU .EQU
.EOU .EOU .EOU
.EQU .EQU .EQU .EQU
.EQU .EQU .EQU .EQU .EOU
.EQU
.EQU .EQU
.00U .00U
.EQU .EQU
.00U
.EQU
.00U .00U .00U
.EQU
.EQU .EQU
.EQU .EOU
.EQU .EOU
.EQU .EOU
.00U
.EQU
.EQU
.00U
.EQU
.EQU
.EQU .EQU
.EQU .EQU
01 00 10 ZRPG1+08
ZRPG1+09 ZRPG1+ØA
87 85
91
0F479 50
OFF 1400+PTRHI 1800-I-ZRPG1
00000 00008 00010 00O58 00047 00O50
00O51 00066 00000 0CØF1 000F2
ØCØF3
0C100 0C200
0C300 0C400 0CFFF ØFFD0
OFFDF 0FFD2 0FFD3 0FFEØ
OFFEF ØFFE2
ØFFE3 0FC25 0F007 0F00F
ØFBC7
0F098
ØFD9D
0F901
RAÌITBL
.ORG 0F4C5
.BYTE 00,ØB1,0B2,ØBA,0B9,10,00,13
CHPG
.EQU
*
.ASCII "RA"
.BYTE 000
M
.ASCII "RO"
.BYTE ØCD
M
.ASCII "VI"
.BYTE 0Cl
A
.ASCII "ACI"
.BYTE 001
;A
.ASCII "AI"
.BYTE 004
D
.ASCII "DIAGNOSTI"
.BYTE 0C3
C
.ASCII "Z"
.BYTE ØDØ
¡P
.ASCII "RETO"
.BYTE 009
Y
¡ SETUP SYSTEM
Page 1"' 1
Apple Computer Inc · 1982
Page 0655 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
t.
10/31/89 9:47
FlEE F4EE FlEE FIFØ F4F3 FIF5 F4F8 FIFB FIFE F4FF F502 F505 F506 F507 F509 F50C F5ØE F511 F513 F516 F517 F518 F51A F510 F51F F521 F524 F524 F524 F524 F526 F528 F52A F52C F520 F52F F530 F532 F533 F534 F535 F537 F538 F53A F538 F530 F53F F541 F543 F544 F546 F546 F546 F546 F548 F54A F54B F540 F54F F551 F553 F555 F557 F559 F55B F55E F560 F562 F563 F565 F567 F569 F56C
F561'
F571 F573 F575 F575 F575 F575 F578 F57A F57D F575
F581 F584 F586 F589 F588 \F58E
A9 53 8D DFFF A2 00 8E EØFF 8E EFFF 8E 00FF CA 8E D2FF 8E D3FF 9A E8 A9 0F 80 E3FF A9 3F 8D E2FF A0 0E B9 D0CØ 88 88 10F9 AD 08C0 29 04 0003 4C 86F6
A9 01 95 00 D5 00 D0FE ØA D0F7 E8 DØF2 8A 48 E8 00FB CA 86 18 68 C5 18 DØEB C6 18 DØF7 68 DØE4
A2 08 95 10 CA 10FB A2 02 86 19 A9 00 A0 FF 91 18 Dl 18 F007 20 48F7 94 10 A6 19 E8 E0 C0 DØE8 A2 20 EE EFFF AD EFFF 29 0F C9 03 DØDA
20 9DFD A2 00 8E EØFF CA 8E 02FF 8E 03FF A9 3F 80 E2FF A9 0F 8D E3FF A2 10
HD:Apple i/:ROM - Sara Tests
DISK1
LOA
#52+ROM
STA
SYSD1
LOX
#00
STX
SYSEØ
STX
BNKSW
STX
ZPREG
DEX
STX
SYSD2
STX
SYSD3
TXS
INX
LOA
#ØF
STA
SYSE3
LOA
#3F
STA
SYSE2
LDY
#ØE
LDA
DISKOFF,Y
DEY
DEY
BPL
DISK1
LOA
KEYBD
AND
#04
ONE
NXBYT
JMP
RECON
; VERIFY ZERO PAGE
NXBYT
LDA
#01
NXBIT
STA
ZRPG,X
CMP
ZRPG,X
NOG000
BNE
NOG000
ASL
A
BNE
NXBIT
INX
BNE
NXBYT
CNTWR
TXA
PHA
INX
ONE
CNTWR
DEX
STX
PTRLO
PULBT
PLA
CMP
PTRLO
ONE
N0000D
DEC
PTRLU
ONE
PULBT
PLA
BNE
NOGOOD
¡ SIZE IN MEMORY
LOX
NOMEM
STA
DEX
BPL
LOX
NMEM1
STX
LDA
LDY
STA
CMP
BED
JSR
STY
LDX
NMEM2
INX
CPX
ONE
LDX
INC
LOA
AND
CMP
BNE
#08 ZRPG1,X
NONEM #02 PTRHI #00 #0FF (PTRLO),Y (PTRLO),Y NMEM2 RAM ZRPG1,X PTRHI
#ØCØ NMEM1 #20
BNI1SW
BNKSW #OF #03 NMEM1
SETUP SCREEN
ERRLP
JSR
SETUP
LDX
#00
STX
SYSEØ
DEX
STX
SYSD2
STX
SYSD3
LOA
#3F
STA
SYSE2
LDA
#ØF
STA
SYSE3
LDX
#10
TURN OFF SCREEN, SET 2MHZ SPEED ¡ AND RUN OFF ROM ; SET BANK SWITCH TO ZERO
AND SET ZERO PAGE SAME
PROGRAM DDRS
ROTATE A 1 THROUGH EACH BIT IN THE 0 PG TO COMPLETELY TEST THE PAGE. HANG IF NOG000. TRY NEXT BIT OF BYTE UNTIL BYTE IS ZERO. CONTINUE UNTIL PAGE IS DONE. PUSH A DIFFERENT BYTE ONTO THE STACK UNTIL ALL STCK BYTES ARE FULL. THEN PULL THEM OFF AND COMPARE TO THE COUNTER GOING BACKWARDS. HANG IF THEY DONT AGREE. GET NEXT COUNTER BYTE CONTINUE UNTIL STACK IS DONE. TEST LAST BYTE AGAINST ZERO.
ZERO THE BYTES USED TO DISPLAY THE BAD RAM LOCATIONS EACH BYTE= A CAS LINE ON THE SARA BOARD. STARTING AT PAGE 2 TEST THE LAST BYTE IN EACH MEM PAGE TO SEE IF TUE CHIPS ARE THERE.. (AVOID 0 & STK PAGES) CAN THE BYTE BE O'D?
NO, FIND WHICH CAS IT IS. SET CORRES. BYTE TO $FF RESTORE X REGISTER AND INCREMENT TO NEXT PAGE UNTIL I/U IS REACHED.
THEN RESET TO PAGE 20 ; AND COTO NEXT BANK TO
CONTINUE. (MASK INPUTS FROM BANXSWITCH TO SEE WHAT SWITCH IS SET TO) CONTINUE UNTIL BANK '3
CALL SCRN SETUP ROUTINE ¡ SETUP I/O AGAIN ; FOR VIA TEST ; PROGRAM DATA DIR
REGISTERS
; HEADING OF DIAGNOSTICS' WITH
Page 2'
I
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
10/31/89 9:47
F590 F593 F595 F597 F599 F59C F59F F5A1
FIAi F5A3 F5A5 F5A6 F5A7 F5A9 F5AB F5AO FSBØ F501 FIB2 F5B4 F507 F5B8 F5BA F5BA F5BA FINA F5BB F505 F5BF F5C2 F5C4 F5C5 FSC6 F5C7 F5C8 F5C9 F5CB F5CD F5CF F502 F5D4 F505 F5D7 F5D8 F5DA F5DC F5DE F5EØ F552 F552 F554 F557 F557 F5E7 F5E7 F5E9 F5EA F5EC F5EE F5FØ F5F2 F5F4 F5F6 F5F8 FIFA F5FC FIFE F5FF F601 F603 F605 F606 F608 F6ØA F600 F600 F600 F600 F6ØE F60F F612 F614 F616 F619 F610 F61D F620 F622 F625 F627
20 38F7 A2 00 86 50 A9 04 20 C7FB 20 38F7 A2 07 F5A1 B5 10 AO 08 ØA 48 A9 AS 9002 A9 31 20 2SFC
68 88
OØF1 20 07FD CA 10E]
9A 8C EFFF 98 80 DOFF 85 FF CB 98 48 68 CB C0 20 DØF1 A0 00 BC DOFF 86 18 E8 86 19 8A 01 18 D006 50 1F DØF4 F005 F552 A2 lA 20 7BF7
A9 00 AB A2 F0 85 18 86 19 A2 FF 51 18 E4 19 0006 CO BF 0002 AO EF C8 DOF1 E6 19 O0ED AB F005 A2 03 20 70F7
18 DB AD 50FF 29 3F 85 18 AD EFFF 29 4F 65 18 60 DOFF 85 18 AD DFFF 29 5F 65 lB
HD:Apple i/:ROM - Sara Tests
Page 3
ERRLP1
RAMWT1 RAMWT2 RAMWT4
JSR LDX STX LDA JSR JSR LDX
.EQU LDA LDY ASL PHA LDA BCC LOA JSR PLA DEY ONE 3SR DEX BPL
STRWT #00 CV #04 SETCVH STRWT #07
*
ZRPG1,X #08 A
#ØAE RAMWT4 #31 COOT
RAMWT2 CROUT1
RAMWT1
TillS SUBROUTINE PRINT 'RAM SET CURSOR TO 2ND LINE SPACE CURSOR OUT 3
(X STILL=0 ON RETURN) ; THE SAME SUBROUTINE ¡ FOR BYTES 7 - 0 IN
OUT EACH BIT AS A
; ' ' OR ri, FOR INDICATE BAD OR MISSING RAM
CHIPS SUBROUTINE 'RAM'
RAM
SETS UP THESE BYTES
¡ LOAD A -' TO ADD.
; LOAD A rl. TO ACC. AND PRINT IT RESTORE BYTE AND ROTATE ALL 8
TINES ¡ CLEAR TO ENO DF LINE.
¡ ZPG & STR TEST
TXS
STY
BNKSW
ZP1
TYA
STA
ZPREG
STA
STKØ
INY
TYA
PilA
PLA
INY
CPY
#20
BNE
ZP1
LOY
#00
STY
ZPRRG
STX
PTRLO
ZP2
INX
STX
PTRHI
TXA
CMP
(PTRLO),Y
BNE
ZP3
CPX
#1F
BNE
2P2
BEQ
ROMTST
ZP3
.EQU
*
LOX
((lA
JSR
MESSERR
; ROM TEST ROUTINE
ROMTST
LOA
TAY
LOX
STA
STX
LOX
ROMTST1
EOR
CPX
ONE
CPY
BNE
LDY
ROMTST2
INY
BNE
INC
BNE
TAY
BEQ
LDX
JSR
#00
#ØFØ PTRLO PTRHI
((0FF
(PTRLO),Y PTRHI ROMTST2 #ØBF ROMTST2
((05F
ROMTST1 PTRHI ROMTST1
VIATST #03 MESSERR
¡ VIA TEST ROUTINE
CHIP IS THERE, BAD ZERO AND STACK SO PRINT 'ZP' MESSAGE ¡ & SET FLAG (2MHZ MODE)
SET POINTERS TO ¡ $F000
SET X TO 6FF FOR WINDOWING I/O ¡ COMPUTE CHKSÍJM ON EACH ROM BYTE, WINDOW OUT RANGES FFCØ-FFEF
; TEST ACC. FOR 0 ¡ YES, NEXT TEST ¡ PRINT 'ROM' AND ; SET ERROR
VIATST
CLC
SET UP FOR ADDING BYTES
CLD
LOA
SYSEØ
¡ MASK OFF INPUT BITS
AND
((3F
¡ AND STORE BYTE IN
STA
PTRLO
TEMPOR. LOCATION
LOA
BNKSW
¡ MASK OFF INPUT BITS
AND
#48'
¡ ANO ADD TO STORED
ADC
PTRLO
BYTE IN TEMP. Loe.
ADC
EPREG
¡ ADO REMAINING
STA
PTRLO
¡ REGISTERS OF THE
LOA
SYSD1
¡ VIA'S
AND
((5F
(MASK THIS ONE)
AOC
PTRLO
ANO TEST
I
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
t
10/31/89 9:47
F629 F62C F62F F632 F635 F637 F639 F63B F630 F63E F630 F630 F63F F641 F644 F647 F6IA F64C F640 F650 F653 F653 F653 F653 F655 F658 F650 F65E F661 F663 F664 F666 F669 F6EA FEEC F66F F671 F672 F674 F676 F676 F678 F670 F67B F67B F67B F670 F67F F681 F684 F686 F686 F686 F686 F688 F680 F68E F691 F694 F697 F699 F69C F69E F6A1 F6A3 F6A5 F6A6 F6A8 F6AA F6AC F6AD F6AF F6BØ F6B3 F605 F607 F6BA F600 F6BF F6C2 F6C2 F6C2
F6C2 F6C4 F6C5 F6C7 F6C9 F6CB F6CE F6CF
6D D2FF 60 03FF 6D 02FF 6D E3FF C9 El F005 A2 06 20 7BF7
18 A9 9F 2D Fico 6D F2CØ 60 F3CØ C9 10 F005 A2 09 20 7BF7
A9 CO BD OCFF AO SACO AO SECO AO 5000 AO 20 88 OØFO AO 50DB CB FØØA AD 66C0 30FB
98
29 RO F005 F676 A2 OD 20 7BF7
AD 08C0 0A 1041 AD DFFF 3Ø3C
A9 77 8D DFFF 20 9SFO 2C lOCO AD FFCF AD 2000 A9 10 20 08C0 0003 20 01F9 A2 01 86 87 CA 86 85 A9 AB 85 86 4A 85 91 8A 20 79F4 900A A2 1C 20 38F7 20 ØFFD BØE2 4C 00A0
AO 7F 98 29 FE 49 4E F003 09 0000 88 DØF3
HD:Apple i/:ROM- Sara Tests
Page 4
AOC
SYSD2
TO SEE
ADC
SYSD3
IF THEY AGREE
ADC
SYSE2
WITH THE RESET
AOC
SYSE3
CONDITION.
CMP
#ØEØ+ROM
=E1?
BEQ
ACTA
YES, NEXT TEST
LOX
#06
NO, PRINT 'VTA' MESS
JSR
MESSERR
; AND SET ERROR FLAG
ACIA TEST
ADIA
CLC
LOA
#9F
AND
ACIAST
ADC
ACIACM
ADC
ACIACN
CMP
#10
REQ
ATD
LOX
#09
3ER
MESSERR
SET UP FOR ADDITION MASK INPUT BITS FROM STATUS REG AND ADD DEFAULT STATES 01F CONTROL AND COMMAND
REGS. =10? YES, NEXT TEST ; NO, ACIA' MESSAGE AND THEN SET ERROR FLAG
A/D TEST ROUTINE
ATO ADCTST1 ADCTST3
ADCERR
LDA STA LDA LOA LDA LOY DEY BNE LOA
INY BEQ
LDA BMI TYA AND
REQ .000 LOX JSR
#ØCØ ØFFDC PDLEN+2 PDLEN+6 POLEN+4 #20
ADCTST1 PDLEN+5
ADCERR ADTO ADCTST3
#ØEØ KEYPLUG
*
#00 MESSERR
WAIT FOR 40 USED
SET A/D RAMP COUNT FOR CONVERSION
IF BIT 7=1? YES, CONTINUE NO, MOVE COUNT TO ACC ACC<32
NO,
PRINT 'A/D MESS AND SET ERROR FLAG
KEYBOARD PLUGIN TEST
KEYPLIJG
LOA
ASL
BPL
LOA
0Ml
KEYBD A SEX
5YSD1 SEX
IS KYBD PLUGGED IN?
(IS LIGHT CURRENT PRESENT?) NO, BRANCH IS ERROR FLAG SET? ERROR HANG
RECONFIGURE THE SYSTEM
RECON
LOA
#77
STA
SYSD1
JSR
CLDSTRT
BIT
KEDSTRB
LDA
EXPROM
LOA
00O20
LOA
#10
AND
KEYBO
BNE
BOOT
JSR
MONITOR
BOOT
LOX
#01
STX
IBCMD
DEX
STX
IBBUFP
LOA
#ØAØ
STA
IBBUFP+1
LSR
A
STA
PROVTRK
TXA
JSR
BLOCKIO
BCC
GOBOOT
LDX
BiC
JSR
STRWT
JSR
KEYIN
BCS
BOOT
GOBOOT
J14P
ØAØØØ
SYSTEM EXCERCISER
TURN ON SCREEN INITIALIZE MONITOR AND DEFAULT CHARACTER SET CLEAN KEYBOARD DISABLE ALL SLOTS TEST FOR °APPLE 1" NO, DO REGULAR BOOT AND NEVER COME BACK READ BLOCK 0
; INTO RAM AT $A000
¡ FOR TRACK 80 ; MAKE tT RECALIBRATE TOO!
¡ IF WE'VE SUCCEEDED. DO IT UP ; 'RETRY
; GO TO IT FOOL...
SEX SEX1
LDY
#7F
TYA
¡ TRY FROM ¡ $7F TO 0
AND
BOFE
ADD.=
EOR
#4E
$40 OR $4F
BEQ
SEX2
; YES, SKP
LOA
KYBO,Y
NO, DONT
SEX2
DRY
NEXT ADO
BNE
SEXÎ
I
Apple Computer Inc · 1982
Page 0658 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
10/31/89 9:47
F6D1 F6D4 F6D7 F6DA F6DD F6EØ F6E3 F6E4 F6E6 F6E6 F6E6 F6E6 F6E8 F6EB F6ED F6F0 F6F2 F6F4 F6F6 F6F7 F6F9 F6FC F6FD F700 F703 F704 F705 F706 F709 F7ØB F7RE F7ØF F712 F713 F715 F717 F718 F719 F71A F710 F7IE F720 F720 F720 F720 F722 F725 F728 F72A F720 F72F F730 F732 F735 F738 F738 F738 F738
F738 F738 F73B F73C F73E F741 F742 F743 F745 F748 F748 F748 F748 F749 F74A F74B F74C F740 F745 F74F F750 F751 F752 F755 F757 F758 F75B F75D F75E F75F F761 F763
AD 51CØ B9 00Cl B9 00C2 B9 00C3 B9 00C4 AD FFCF CB D0EE
A9 73 8D DFFF A9 18 80 DOFF A9 00 A2 07 95 10 CA 10FB 20 84F7 08 20 F6F7 20 F6F7 28 6A 08 20 A1F7 OØF2 20 84F7 08 20 FAF7 48 A9 00 91 18 68 28 6A 08 20 A1F7 DØEF
A9 00 BD EFFF BD 00FF A2 07 BD 1018 95 10 CA 10F8 20 7EF7 4C 75F5
BD CDF4 48 09 80 20 25FC 58 68 10F3 4C 0780
48 BA 4A 4A 4A 4A 08 4A 28 AA BD C5F4 1014 48 AD EFFF 29 0F AA 68 E0 00 F013 4A
HD:Apple i/:ROM - Sara Tests
SEX3
LOA
TXTMD
LOA
SLT1,Y
LDA
SLT2,Y
LOA
SLT3,Y
LOA
SLT4,Y
LOA
EXPROM
INY
BNE
SEX3
SET TXT EXCERCISE ALL SLOTS
DISABLE EXPANSION ROM AREA
RAN TEST ROUTINE
USRENTRY LDA
STA
LOA
STA
LOA
LOX
RAMTSTØ STA
DEX
BPL
JSR
PHP
RAMTST1
JSR
JSR
PLP
ROR
PUP
JSR
BNE
JSR
PHP
PAMTST4 JSR
PUA
LOA
STA
PLA
PLP
POR
PUP JSR
BNE
#72+ROM SYSD1 #18 ZPREG #00 #07 ZRPG1,X
RAMTSTØ PAMSET
RAMWT RAMWT
A
PTRINC PAMTST1 RAMSET
RAMRD
#00 (PTRLO,Y
A
PTRINC RAMTST4
; RETURN TO START
LOA STA STA LOX RAMTST6 LOA STA DEX BPL JSR JMP
#00 BNKSW ZPREG #07 PHPR,X ZRPG1,X
PAMTST6 ERROR ERRLP
; SARA TEST SUBROUTINES
STRWT
LOA
PUA
ORA
JSR
INX
PLA
BPL
JMP
SUBROUTINE PAM
RAM
PUA
TXA
LSR
LSR
LSR
LSR
PUP
LSR
PLP
TAX
LOA
BPL
PPA
LOA
AND
TAX
PLA
CPX
BEQ
LSR
CHPG,X #80 COOT
STRWT CRUtJT1
A A A A A
RAMTBL,X RAMO BNKS8 #ØF
#00 RAMi A
NORMAL VIDEO & PRINT NXT CHR CLR TO END OF LINE
SV ACC
;
CONVRT ADO TO USE FOR 8 ENTRY
LOOKUP IF VAL <0, GET WHICH
BANK? SET
Page 5
I
Apple Computer Inc · 1982
Page 0659 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
10/31/89 9:47
F764 F765 F766 F767 F769 F76B F76D F763 F770 F772 F774 F776 F778 F779 F77A F773 F773 F773 F77B F773 F780 F783 F784 F784 F784 F784 F786 F788 F78A F78C F780 F78E F78F F791 F793 F796 F798 F79A F79C F793 F79F F7AØ F7A1 F7A1 F7A1 F7AÌ F7A2 F7A4 F7A6 F7A8 F7AA F7AC F7AE F7BP
F7B2 F7B4 F7B6 F738 F7BA F7BC F7BE F700 F703 F704 F706 F708 F709 F709 F709 F709 F7CA F700 F703 F7DØ F701 F703 F7D4 F7D6 F709 F7DA F7DD F7DE F7DF F731
F733 F735 F737 F738 F739 F733
4A 4A CA DØØD 29 05 0009 8A F002 A9 03 9002 49 03 29 07 AA 68 60
20 38F7 A9 F3 80 DFFF 60
A2 01 86 lA A0 00 A9 AA 38 48 08 A5 lA 09 80 80 1914 A9 02 85 19 A2 00 86 18 28 68 60
48 36 18 0010 AS lA 100E A5 19 09 13 F006 09 17 0004 E6 19 E6 19 36 19 0007 C6 lA 06 lA 20 8DF7 68 A6 lA E0 FO 60
48 A6 19 A4 lA 3019 8A 301D 18 69 20 80 EFFF AA 20 48F7 68 48 AO 00 51 18 15 10 95 10 68 60 A9 00 80 EFFF
HD:Apple ///:ROM - Sara Tests
RAMO
RAMØØ PAhl
LSR
A
LSR
A
DEX
ENE
RAMi
AND
#05
BNE
RAMi
TXA
SEQ
RAMØØ
LOA
#03
ECC
RAMi
EOR
#03
AND
#07
TAX
PLA
RTS
PROPER PAM VAL ; CONVERT TO VAL
BANKSW
SUBROUTINE ERROR
MESSERR JSR
ERROR
LOA
STA
RTS
STRWT #0P2+ROM SYSD1
PRINT MESSAGE FIRST SET i MHZ MO
; SUBROUTINE RAMSET
RAMSET RAMSET1
LOX STX LDY LOA SEC PHA PH? LOA ORA STA LOA STA LDX STX PL? PLA RTS
#01 BNK #00 #ØAA
BNK #80 188E #02 PTRHI #00 PTRLO
¡
¡ SUBROUTINE PTRTNC
PTRINC
PINC2 PINOl RETS
PHA INC ENE LOA BPL LOA CM? BEQ CMP BNE INC INC INC BNE DEC DEC JSR PLA LOX CPX RTS
PTRLO RETS BUN PINC1 PTRHI #13 PINC2 #17 PINOl PTRHI PTRHI PTRHI RETS BNK BNK RAMSET1
BNK #ØFD
SUBROUTINE RAMERR
RAMERN
PUA
LOX
LDY
3Ml
TXA
BMI
CLC
ADO
RAI4ERR2
STY
TAX
RAMERR3 JSR
PLA
PHA
LDY
EOR
ORA
STA
PLA
RTS
RAMERR4 LOA
STA
PTRHI BNK RAMERR4
RAMEPR5
#20 BNKSW
RAM
#00 (PTRLO),Y ZRPG1,X ZRPG1,X
#00 BNKSN
Page 6
I
Apple Computer Inc · 1982
Page 0660 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
f
10/31/89 9:47
F7EE F7FØ F7F1 F7F3 F7F4 F7F6 F7F6 F7F6 F7F6 F7FB
F7FA F7FC F7FE F7FF F7FF
FØEA 38
09 60
CS DØEØ
49 PF 91 18 Dl 18
DØCB
60
HD:Apple fl/:ROM - Sara Tests
P.AM0005
BEQ SEC SBC INY ONE
RAMEPR3
#60
RAMEBR2
SUBROUTINE RAMMT
RAMMT RANRO
RETi
ROR
#ØFF
STA
(PTRLO,Y
CM?
(PTRLO,Y
ONE
RAMERR
RTS
.END
Page 7'
SYMBOL TABLE DUMP
AB - Absolute EF - Ref PB - Public
LB - Label UD - Undefined
DF - Def
PR - Proc
PV - Private CS - Consts
MC - Macro FC - FunC
ACIA ADCTST1 BLOCKIO CLDSTRT DISKI EXPROM IBNK EYED N00000 PHPR PTRINC
RAMOØ
RAMERR4
RAÌ1TBL
RAMMT
RETi ROMTST2 SEX1 SLT3 SYSD2
TXTMD
ZP3
LB F630 LB F663 AB F479 AB FOSS LB F513 AB CFFF AB 1419 AB C000 LB F52A AB 1810 LB F7A1 LB F772 LB F709 LB F4C5 LB F7F6 LB F7FE
LB F5FE LB FSC4
AB C300 AB FFD2
AB CO51 LB F502
ACIACM AB COF2
ADCTST3 LB F669
BNK
AB ØØ1A
CNTWR LB F532
DISKOFF AB CODO
GOBOOT LB F6BF
KBDSTRB AB C0i0
MESSERR LB F77B
NOMEM LB F548
PINC1 LB F7BB
PTRLO AB 0018
RAMi
LB F776
RAMERR5 LB F7FØ
RAMTSTØ LB F6F4
RANWT1 LB F5A1
RETS
LB F7C3
SARATEST PR
SEX2
LB F6CE
SLT4
AB C400
SYSD3
AB FFD3
USRENTRY LB F6E6
ZPREG AB FF00
ACIACN AORS
BNKSW COUT EBRLP
GOND
KEYBD MONITOR NXBIT
PINC2 PULBT
RAMERR
P.AMRD RAMTST1
RANWT2
ROM
SETCVI-I SEX3 STKØ SYSEØ
VIATST ZRPG
AB CØF3 AB C047 AB FFEF AB FC25 LB F575
AB CO50
AB C008 AB F901 LB F526 LB F706
LB F53A LB F7C9 LB F7FA
LB F6FD LB F5A5 AB 0001 AB FBC7
LB F6D4 AB 00FF AB FF00 LB F600 AB 0000
ACIAST ADTO BOOT CROUT1 ERRLP1 IBBUFP KEYIN
NMEM1
NXBYT PREVTRK
RAM RAMERR2 RAMSET RAMTST4
RAMWT4
ROMTST SETUP SLT1 STRWT SYSE2 ZP1 ZRPG1
AB CØF1 AB C066 LB F6A1
AB FDØ7
LB F593 AB 0085
AB FDØF LB F54F LB F524 AB 0091 LB F748 LB F706 LB F784 LB F7ØF
LB F5AD
LB F507
AB FD9D AB C100 LB F738 AB FF02 LB F5BE AB 0010
Assembly complete:
545 lines
0 Errors flagged on this Assembly
ADCERR ATO CHPG CV ERROR
IBCMD KEYPLUG NMEM2 POLEN PTRUI RAI4Ø RANERR3 RAMSET1 RAMTST6 RECON
ROMTST1 SEX SLT2 SYSD1 SYSE3 2P2
LB F676 LB F653 LB F4CD AB 0050 LB F770 AB 0087 LB F67B LB F562
AB CO58
AB 0019 LB F76B LB F7DA LB F780 LB F72A LB F686 LB F5F2 LB F6C2 AB C200
AB FFDF AB FF03
LB F5D4
6502 OPCODE STATIC FREQUENCIES
ADC : 10 AND : 12
************
ASL :
3
BCC : BCS
31m *
BEQ
BIT
1m 12 I *
BMI
4
BNE BPL CLC CLD :
CM? :
319311I
im 10
******************************* **********
CPX :
5
CPY :
2
DEC :
3
DEX :
9
DEY :
5
EOR: 5
INC :
6
INX :
6
INI :
6
JMP :
4
JSR : 29
LDA : 56
LOX :
24
** ** ** ** * * ** ** ** ** ** ** ** ** ** *
************************** ****************************** ******** ****************
LDY : 10
LSR :
9
** * * *
ORA: 3
PEA : 11
***********
PUP :
6
PtA : 12
PLP :
4
ROR: 2
RTS:
SOC :
61m
J
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
10131/89 9:47
HD:Apple ///:ROM - Sara Tests
SEC: 2 STA: 30
STX : 18
STY: 4 TAX: 4 TAY: 2 TXA: 6 TXS: 2 TYA: 4
**
****************** ************
Minimum frequency =
i
Maximum frequency = 56
Average frequency =
8
Unused opcodes:
SRK BVC BVS CLI CLV NOP ROL RTI SED SEI TSX
Program opcode usage: 80 %
(1.00) That's all, Folks
Page 8
i
Apple Computer Inc · 1982
Page 0662 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple Computer Inc · 1982
Page 0663 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
t
10/31/89 10:04
0000 0000 0000 0000 0000 0000 0000 0000 FiFE F7FE F7FE F7FF F800 F802 F804 F806 F808 F80A F8ØC F800 F810 F812 F814 F816 F818 F81A F81C F810 F820 F822 F824 F826 F828 F82A F82C F820 F830 F832 F834 F836 F838 F83A F83C F83E F840 F842 F844 F846 F848 F84A F84C F840 F850 F852 F854 F856 F858 FS5A FISC F85E F860 F862 F864 F866
F868 F86A F86C F860 F870 F872 F874 F876 F878 F87A F87C F87E F880 F882 F884 F886 F888 F88A F88C F88E F890 F892
F894 F896 F898
'89A
60 3F 09 01 FØFA E9 01 F0F6 E9 01 F0F2 E9 01 FØEE 09 01 FØEA E9 01 F006 E9 01 F002 09 01 F000 E9 01 FOCA E9 01 F006 09 01 F0D2
09 01 FØCE E9 01 FOCA E9 01 F0C6 E9 01 F0C2 El 01 FØBE E9 01 F0BA 09 01 FØB6 09 01 F0B2 El 01 F0AE
E9 01 F0AA 09 01 F0A6 E9 01 FØA2 09 01 FOIE 09 01 FØ9A 09 01 F096
El 01 F092 El 01 FOSE
El 01 FO8A E9 01 F086 09 01 F082 El 01 F002 09 01 FØ7C E9 01 F078 09 01 F074
09 01 F070 09 01 FØ6C
09 01 F068 09 01 F064
HD:Apple fl/:ROM - Momtor ggggìggggggggsgggggguggggs*gggggggggsiggggggggggggggg
;I;S APPLE /1/ ROM - MONITOR
gdCgOPgYdRgICgHgT g1g9g79ggBYddAdPP«LdE dCgOMgPgUgTEgRg,dIgNdC.dgggggggggggggggggggúgú
.ABSOLUTE .PROC MONITOR .ORG 0F7F0
RETi RET3
RTS .BYTE SBC SEQ SBC BEQ SOC SEQ SBC SEQ SOC BEQ SBC BEQ SOC BEQ SBC SEQ SBC BEQ SBC REQ SBC
BEQ SSC BEQ SBC SEQ SSC BEQ SSC SEQ SBC SEQ SBC BEQ SSC SEQ SSC BEQ SSC SEQ SBC BEQ SBC SEQ SSC BEQ SSC BEQ SSC SEQ SSC SEQ SSC SEQ SBC SEQ SSC BEQ SSC BEQ SSC SEQ SOC SEQ SBC BEQ SBC
BEQ SSC
BEQ SSC BEQ SSC
SEQ SBC
BEQ SBC BEQ
03F 801 RETi #01 RETi #01 RETi #01 RETi #01 RETi #01 RETi
#01 RETi #01 RETi #01 RETi #01 RETi #01 RETi #01 RETi #01 RETi #01 RETi #01 RETi #01 RETi #01 loTi
#01 RETi #01 RETi #01 RETi #01 RETI
#01 RETi #01 RETi #01 RETi #01 RETi #01 RETi
#01 RETi #01 RETi
#01 RETi #01 RETi #01 RETi #01 RET3 #01 RET2 #01 RET2 #01 RET2
#01 RET2 #01 RET2 #01 RET2 #01 RET2
Page 1
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Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
10/31/89 10:04
F89C E9 01 F89E F060 F8AØ E9 01 F8A2 F05C F8A4 E9 01 F8A6 F058 F8A8 E9 01 F8AA F054 F8AC E9 01 F8AE F050 F8B0 E9 01 F8B2 F04C F8B4 E9 01 F8B6 F048 F8B8 E9 01 PaRA F044 F8BC E9 01 F8BE F040 F8CØ E9 01 F8C2 FØ3C F8C4 E9 01 F8C6 F038 F8C8 E9 01 F8CA F034 P8CC E9 01 F8CE F030 F800 E9 01 F8D2 F02C F804 E9 01 F806 F028 F808 E9 01 F8DA F024 F8DC E9 01 F8DE F020 F8E0 59 01 F8E2 FO1C F8E4 59 01 F856 F018 F8E8 E9 01 F8EA F014 F8EC E9 01 F8EE F010 F8FØ E9 01 F8F2 FØØC F8F4 59 01 F8F6 F008 F8F8 E9 01 F8FA F004 P8FC E9 01 F8FE F000 F900 60 F901
F901 F901 0058
F901 F901 0058 F901 0059 F901 005A F901 005R F901 005C F901 ØØSD F901 005E F901 005F F901 0060 F901 0061 F901 0058 F901 0063 F901 0064 F901 0065 F901 0066 F901 0067 F901 0068 F901 0069 F901 006A F901 006R F901 006C F901 0060 F901 006E F901 006F F901 0070 F901 0071 F901 0072
F901 0073 F901 0074 F901 0075 F901 0076 F901 0077 F901 0078 F901 0079 '901 007A
RET2
SCRNLOC
LMARGIN RMARGIN OINTOP WINBTM
CI]
CV BAS4L BAS4H BAS8L BAS8H TBAS4L TBAS4H TBAS8L TRAS8H FORGND BKGND MODES CURSOR STACK PROMPT TEMPX TEMPY CSWL CSWH KSWL KSWH PCL
PCI]
AlL
AlI]
A2L A2H A3L
A311
A4L
HD:Apple i/:ROM - Monitor
SBC
#01
REQ
RET2
SBC
#01
REQ
RET2
SOC
#01
REQ
RET2
SBC
#01
REQ
RET2
SBC
#01
BEQ
RET2
SBC
#01
BEQ
RET2
SBC
#01
REQ
RET2
SRC
01
BEQ
RET2
SBC
#01
REQ
RET2
SBC
#01
REQ
RET2
SRC
#01
REQ
RET2
SBC
#01
REQ
RET2
SRC
#01
REQ
RET2
SBC
#01
REQ
RET2
SBC
#01
BEQ
RET2
SBC
#01
REQ
RET2
SBC
#01
BEQ
RET2
SRC
#01
REQ
RET2
SOC
#01
REQ
RET2
SRC
#01
BEQ
RET2
SRC
#01
REQ
RET2
SRC
#01
BEQ
RET2
SRC
#01
REQ
RET2
SBC
#01
BEQ
RET2
SRC
#01
REQ
RET2
RTS
.EQU
.EQO .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQO .EQU .EQU .EQU .EQU
.EQIJ
EQU .EQU .EQU .EQU .EQO .EQU
.EQIJ
.EQU .EQU .EQU .EQU .EQU .EQU .EQU EQU .EQU .EQU .EQU .EQU .EQU .EQU
58
SCRNLOC SCRNLOC+1 SCRNLOC+2 SCRNLOC+3 SCRNLOC+4 SCRNLOC+5 SCRNLOC+6 SCRNLOC+7 SCRNLOC+8 SCRNLOC+9 SCRNLOC+A SCRNLOC+ØB SCRNLOC+ØC SCRNLOC+ØD SCRNLOC+ØE SCRNLOC+ØF SCRNLOC+10 SCRNLOC+11 SCRNLOC+12 SCRNLOC+13 SCRNLOC+1l SCRNLOC+15 SCRNLOC+16 SCRNLOC+17 SCRNLOC+18 SCRNLOC+19 SCRNLOC+1A SCRNLOC+1B SCRNLOC+1C A1L+1 A1L+2 A1L+3 A1L+4 A1L+5 AIL+6
Page 2'
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Apple Computer Inc · 1982
Page 0665 of 0730
PDF compression, OCR, web optimization using a watermarked evaluation copy of CVISION PDFCompressor
Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
r
10/31/89 10:04
F901 0070 F901 001C F901 007D F901 007E F901 0080 F901 0069 F901 F901 C000 F901 C010 F901 F901 0358 F901 F479 F901 F686 F901 F4EE F901 0050 F901 0081 F901 0082 F901 0085 F901 0087 F901 F901 F901 F901 BA F902 86 6A F904 D8 F905 20 4EFC F908 A6 6A F90A 9A F903 AO DF F9ØD 85 6B F9ØF 20 D5FC F912 20 67F9 F915 20 2CF9 F918 84 70 F91A A0 12 F91C 88 F910 30ES F919' D9 6CF9 F922 D0F8 F924 20 5EF9 F927 A4 70 F929 4C 15F9 F92C F92C A2 00 F92E 86 76 F930 86 77 F932 01 7E P934 CB F935 49 BO F937 C9 ØA F939 9006 F930 69 88 F93D C9 FA F939' 902A F941 A2 03 F943 ØA F944 ØA F945 ØA F946 0A F947 ØA F948 26 76 F94A 26 77 F94C CA F94D 10F8 F949' A5 7C F951 0006 F953 05 77 F955 95 75 F957 95 79 F959 EB F9SA FØF3 F95C DØD4 F9SE F95E
F955 F9SE AO FA F960 48 F961 09 7DF9 F964 48 F965 A5 7C F967 A0 00 F969 84 7C F963 60 F96C F96C P96C 00 F960 03 F96E 06 F96F RB F970 EC F971 EE '972 EF
HD:Apple i/:ROM - Monitor
A4H STATE YSAV INBUF
TEMP MASK
.EQU .EOU .EQU .EQU .EQU .EQU
A1L+7 A1L+8 A1L+9 A1L+ØA A1L+ØC CURSOR
KBD KBDSTRB
.EQU .E0O
ØCØØØ 00010
USERADR BLOCKIO RECON DIAGN INBUFLEN IBSLOT IBDRVN IBBUFP IBCMD
.EOU .EQU .EQU EQU EQU EQU
.EQU .500 .EQU
358 0F479 0F686 ØF4EE 50
81
IBSLOT+1 IBSLOT+4 IBSLOT+6
AS OF 12/20/1979 ONLY 80 BYTES ($3A0-$3EF)
ENTRY MON MONE
SCAN NXTINP CMDSRCH
.EQU TSX STX CLO JSR LDX TXS LDA STA JSR JSR JSR STY LOI DEY 3Ml CMP BNE JSR LOI JMP
*
STACK
BELL STACK
#ØDF PROMPT GETLNZ ZSTATE GETNUM YSAV #12
MON CMDTAB,Y CMDSRCH TOSUB YSAV NXTINP
MUST BE HEX MODE
RESTORE STACK TO ORIGINAL LOCATION
; PROMPT (APPLE) FOR SARA MONITOR
GET A LINE OF INPUT SET REGULAR SCAN ATTEMPT TO READ HEX BYTE STORE CURRENT INPUT POINTER 18 COMMANDS
; GIVE UP IF UNRECOGNIZABLE FOUND? NO KEEP LOOKING PERFORM FUNCTION
; GET NEXT POINTER ¡ DO NEXT COMMAND
GETNUM
LOX
#00
CLEAR A2
STX
A2L
STX
A2H
NXTCHR
LOA
(INBUF),Y
INI
BUMP INDEX FOR NEXT TIME
EOR
#0B0
CMP
#ØA
TEST FOR DIGIT
BCC
DIGIT
ADC
#88
CMP
#ØFA
; SAVE IT IF 1-9 ; TEST FOR HEX A-F
BCC
DIGRET
DIGIT
LOX
#03
ASL
A
ASL
A
ASL
A
ASL
A
NXTBIT
ASL
A
ROL
A2L
¡ SHIFT HEX DIGITS INTO A2
ROL
A2H
DEX
BPL
NXTBIT
NXTBAS
LDA
STATE
; SHIFTED ALL YET?
BNE
NXTBS2
LDA
A2H,X
; IF ZERO THEN COPY TO Al,3
STA
A1H,X
STA
A3H,X
NXTBS2
INX
BEQ
HXTBAS
BNE
HXTCHR
SWITCH ROUTINE FOR CHARACTER
TOSUB
ZSTATE DIGRET CMDTAB
LOA PEA LDA PEA LDA LOI STY RTS
.EQU .BYTE .EYTE .BYTE .BYTE .BYTE .RYTE .BYTE
#ØFA
CMDVEC,Y
STATE #00 STATE
*
00 03 06 ØEB BEC 0ER
091F
¡ PUSH ADDRESS OR FUNCTION AND RETURN IT
¡ PASS MODE VIA ACC. ¡ RESET STATE OF SCAN
¡ G
GP (CALL) SUBROUTINE
¡ J =JUMP (CONT) PROGRAM
; M
MOVE MEMORY
¡ R =READ DISK BLOCK
S =MEMORY SEARCH
U =tJSER FUNCTION
V
VERIFY MEMORY BLOCKS
Page 3'
I
Apple Computer Inc · 1982
Page 0666 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
t
10/31/89 10:04
F973 F974 F975 F976 F977 F978 F979 F97A F970 F97C F970 F970 F97D F97E F97F F980 F981 F982 F983 F984 F985 F986 F987 F988 F989
F 98A
F9 8B
F9 BC
F980
F 98E
F98E F98E F990 F992 F994 F996 F998 F99A F99B F990 F99F
F 9A0
F 9A2
F9A4
F 9A6
F 9A8
F 9AA
F9AC F9AD F9AE F9AE F9AE F9AF F9BØ F9B1
F 9B2
F 9B3
F 9B 6
F9B7
F 9B 9
F9BB F9BD
F 9BF
F 9Cl
F904 F904 F907 F9C7
F 9C 9
F 9CB
F 9CB
F9CD F9CF F901 F903
F 9D5
F906 F906 F907 F909 F900 F900 F9DE F9EØ
F 9E 1
F 9E 1
F9E3
F 9E5
F9E7
9E 9
FO Fi 99 9B AO 93 A7 AB 95 CG
F970 90 8E 3F 03 08 8B 4E DG 2C 07 lA 1C CB CB AD A4 39
56 7A 0002 56 IB 56 74 0005 E6 75 38 F010 A5 74 38 E5 76 85 80 A5 75 55 77 05 80 0001 18 60
48 IA IA IA IA 20 B9F9 68 29 0F 09 BØ C9 BA 9002 69 06 4C 39FC
20 AEF9
A9 BA D0FG
A9 07 24 68 5002 A9 0F 85 69 60
BA F007 B5 74 95 72 CA 10F9 60
85 69 A4 7D Bl 7E E6 70 A0 00
CMDVEC
HD:Apple i/:ROM - Monitor
.BYTE ØFØ .BYTE ØF1 .BYTE 99 .BYTE 90 .EYTE ØAØ .BYTE 93 .BYTE ØA7 .BYTE ØAB .BYTE 95 .BYTE 006
W X SP
: . ;/
<
CR
=WRITE DISK BLOCK =REPEAT COMMAND LINE
SPACE (BYTE SEPARATOR) ASCII (HI BIT ON) =ASCII (HI BIT OFF) =SET STORE MODE =RANGE SEPARATOR =COMMAND SEPARATOR =OEST/SOtJRCE SEPARATOR =CARRIAGE RETURN
.EQIJ
*
.BYTE 90
.BYTE 8E
.BYTE 3F
.BYTE 003
.BYTE 08
.BYTE 80
.BYTE 4E
.BYTE 0D6
.BYTE 2C
.BYTE 007
.BYTE lA
.BYTE 1C
.BYTE ØCB
.BYTE ØCB
.BYTE ØAD
.BYTE 0A4
.BYTE 39
GO-1 ; JUMP-i
MOVE-i READ-i SEARCH-i USER-1 VRFY-i WRTE-1 REPEAT-i SPCE-1 ASCII-i
; ASCIIØ-i ; SETM000-1 ; SETMODE-1 ; SEP-i
DEBT-i CRMON-1
NXTA4 NXTA1 TSTA1
RETAl
INC
A4L
ONE
NXTA1
INC
A4H
INC
AlL
ONE
TSTA1
INC
A1H
SEC
BEQ
RETAl
LDA
AlL
SEC
SOC
A2L
STA
TEMP
LOA
A1H
SOC
A2H
ORA
TEMP
ONE
RETAl
CLC
RTS
; BUMP 16 BIT POINTERS BUMP Ai
; IN CASE OF ROLL OVER
¡ IF Ai LESS THAN OR EQUAL TO A2 ¡ THEN CARRY CLEAR ON RETURN
PROYTE
PHA
LSR
LSR
LSR
LSR
JSR
PLA
PRHEX
AND
PRHEXZ
ORA
CMP
0CC
AOC
PRHEX2
JMP
PRBYCOL JSR
PRCOLON LDA BNE
TST80WID LOA
BIT
BVC
LOA
SVMASI<
STA
RTS
A1PC
TXA
BEQ
A1PC1
LOA
STA
DEX
BPL
OLDPC
RTS
ASCII1
STA
ASCII2
LOY
LOA
INC
LOY
A A A A PRHEXZ
60F #000 #ØBA PRHEX2 #06 COUT
PRBYTE
#ØBA PRHEX2
#07 MODES SVMASK 60F MASK
SAVE LOW NIBBLE ; SHIFT HI NIBBLE TO PRINT.
; STRIP HI NIBBLE MAKE IT NUMERIC IS IT >9
MAKE IT A'-F
PRINT A COLON ¡ BRANCH ALWAYS ¡ ANTICIPATE ; TEST FOR 80
OLDPC A1L,X PCL,X
A1PC1
TEST FOR NEW PC
MASK YSAV (INBUF),Y YSAV #00
SAVE HI BIT STATUS ; MOVE ASCII TO MEMORY
BUMP FOR NEXT THING.
Page 4-'
/
Apple Computer Inc · 1982
Page 0667 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
10/31/89 10:04
F9EB F9ED F9EF F9F1 F9F3 F9F4 F9F6 F9F8 F9FA F9FC
F SF0
F9FD F9FF FAØ1 FAØ3 FAØ6 FAØ8 FAØ9 FAØ9 FAØ9 FAØB FAØD FAOF FAl2 FA15 FA18 FA1A FAlB FAlB FAlB FA1C FA1D FAll FA1F FA21 FA23 FA25 FA27 FA29 FA2B FA2D FA3Ø FA32 FA35 FA36 FA37 FA3A FA3A FA3A FA3D FA40 FA4Ø FA4Ø FA43 FA45 FA47
FA49 FA4C FA4E FA4F FA4F FA4F FA52 FA54 FA56 FASS
FA5A FA5D FA6Ø FA63
FA65 FA66
FASS FA68 FA6B FA6D FA70 FA72 FAiS FA7B FA7A FA7D
FA7F FAS2 FA8I FAS7 FASS FASC FA8C
A8F
C9 A2 D005 A5 69 1032 60 CS A7 D005 A5 69 302D 60
CS SD F007 25 69 20 C3FA 00DB 60
Bi 74 C5 7A 0006 20 7SFA 20 EFFC 20 94F9 901F 60
38 90 18 AA 86 7C 49 BA 0070 AS FF 3038 A9 7F 1031 2C 0000 1003 4C ØFFD 68 68 4C 12F9
20 BIFA 4C 08F9
20 9DF9 BØ5D Bi 74 91 lA 20 85F9 90F] 60
20 9DF9 304E Bl 74 Dl 7A F006 20 66FA 20 EFFC 20 8EF9 9ØEF 60
A5 73 20 AEF9 A5 7A 20 C4F9 31 7A 20 84FA 20 87FA A5 75 20 AEF9 A5 74 20 C4F9 Bi 74 20 AEF9 A9 AO 4C 39FC
40 5803
ASCII3 CRCHK ASCDONE
HD:Apple i/:ROM - Monitor
CMP
#0A2
BNE
ASCII3
LOA
MASK
BPL
BITON
RTS
CMP
t0A7
BNE
CRCHK
LDA
MASK
0Ml
BITOFF
RTS
; ASCII NOPE, CONTINUE.
HE'S CHANGED MODES.
ASCII ¡ NO, TEST FOR EOL.
CHANGE MODES.
CMP
#80
BED
ASCDONE
AND
MASK
JSR
STOR1
BNE
ASCII2
RTS
END OF LINE? YES, FINISHED
¡ GO STORE IT! ; DO NEXT.
SEARCH SRCH1
LOA
CMP BNE JSR JSR JSR BCC RTS
(A1L),Y A4L SRCH1 PRINTA1 CROUT
NXTA1 SEARCH
LOAD SEARCH BYTE
DUMP MEMORY
INCREMENT POINTER CONTINUE SEARCH RETURN
ASCII ASCIIØ CKMDE
GITON BITOFF REPEAT
REPEAT1 LFA36
SEC .BYTE CLC TAX STX BOR BNE LDA BCS LDA BPL BIT BPL
IMP PLA PLA JMP
90
STATE #ØBA ERROR #ØFF ASCII1 #7F ASCII1 EBD PEPEAT1 KEYIN
SCAN
INDICATE HI ON. (BCC - NEVER TAKEN) INDICATE HI OFF SAVE STATE RETAIN STATE ARE WE IN STORE MODE?
SET HI BIT UNMASKED
MASK HI BIT ALWAYS BRANCHES REPEAT UNTIL KEYPRESS
CLEAN UP STACK
CRMON
JSR
HL1
JMP
MONZ
MOVE
JSR
TSTA1
BCS
ERROR
MOVNXT
LDA
(A1L),Y
STA
(A4L),Y
JSR
NXTA4
0CC
MOVNXT
RTS
TEST VALID RANGE ¡ COMPARE BYTE FOR BYTE
BUMP BOTH Al AND A4 ¡ ALL DONE WITH MOVE
VRFY VOFY1
VRFY2 MISMATCH
PRINTA1
PRA1BYTE PPBYTSP PRSPC USER
JSR BCS LOA CNP BEQ JSR JSR JSR 3CC RTS
LOA JSR LOA JSR LOA JSR JSR LOA JSR LDA JSR LOA JSR LOA
314P
JMP
TSTA1 ERROR
A1L),Y (AIL),Y VRFY2 MISMATCH CROUT NXTA4 VRFY1
A4H PRBYTE A4L PRBYCOL (A4L),Y PRBYTSP PRSPC AlB PRBYTE AlL PRBYCOL (A1L),Y PRBYTE #ØAØ COOT
USERADR
¡ TEST VALID PANCE
¡ COMPARE BYTE FOR BYTE ¡ MATCH? ; YES, DO NEXT. ; PRINT BOTH BYTES
COTO NEWLINE
;
BUMP BOTH Al AND A4
; VERIFY DONE.
; PRINT ADDRESS OP A4
OUTPUT A COLON FOR SEPARATOR
;
; AND THE DATA PRINT THE BYTE AND A SPACE
;
LEAD WITH A SPACE OUTPUT ADDRESS Al
SEPARATE WITH A COLON
¡
PRINT BYTE POINTED TO BY Al
PRINT A SPACE
¡
END VIA OUTPUT ROUTINE.
;
Page 5
I
Apple Computer Inc · 1982
Page 0668 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
'10/31/89 10:04
FA8F FA9O FA91 FA94 FA97 FA97 FA97 FA9A FA9C FA9F FAA2 FAA5 FAA5 FAA7 FAA9 FAAB FAAD FAAE FAAE FAB1 FAB2 FAB4 FAB4 FAB6 FAB8 FAB9 FABB FABD FABF FAd FAC? FAC5 FAC7 FAC9 FACH FACC FACC FACE FACF FAD1 FAD? FAD4 FAD4 PAD6 FAD7 FAD9 FADB FADD FADF FAE1 FAE3 FAE5 FAE7 FAE8 FAEB FAED FAEF FAF1 FAF3 FAFS FAF7 FAFA FAFC FAFD FAFD FAFF
F801 F804 FBØ6 FBØ8 FBØA FBØA FBØB
F1100
FB10 F812 FB14 FB16 FB18 FB1B F810 F820 F823 FB25 FB27 FB29 FB2B FB2E FB3Ø
'833
68 68 20 D6F9 6C 7200
FA97 20 AEF9 A9 Al 20 39FC 20 Ø7FD 4C 04F9
AS 76 85 7A A5 77
85 711 60
20 B8FA
98
F010
C6 70 F045 CA 0016 C9 BA DØ4B 85 7C AS 76 91 78 E6 78 0002 E6 79 60
A4 7D 88 Bl 7E 85 7C 60
A9 01 2C A9 02 85 87 AS 74 85 85 AS 75 85 86 A6 711 A5 7A 78 20 79F4 BØAA E6 7A D002 E6 7B E6 75 E6 75 20 9DF9 9ØDF 60
AS 75 85 77 20 CBF9 05 74 85 76 0006
IA B095 20 C8F9 A5 74 85 7A A5 75 85 7H 20 9DF9 BORE 20 75FA 20 94F9 B010 AS 74 25 69 D005 20 35FB DORO 20 82FA DØEB
JUMP GO RWERROR ERROR2 ERROR DEST
SEP
BL1 SPCE STOR STOR1
DUMMY SETMODE SETMDZ READ WRTE SAVCMD RWLOOP
NOVER
DUMP8
TSTDUMP ERRORi DUMP DUMPØ
DUMP1 DUMP2
DUMP3
HD:Apple i/:ROM - Monitor
PLA PLA JSR JMP
.EQU JSR LOA JSR JSR aMP
LDA STA LDA STA RTS
A1PC @PCL
*
PRBYTE #ØA1 COUT NOSTOP MON
A2L A4L A2N A4H
¡ LEAVE STACK WITH NOTHIN STUFF PROGRAM COUNTER
;
JUMP TO USER PROG.
;
PRINT ERROR NUMBER ¡ PRINT THE OFFENDER
FOLLOWED BY A
ON IT.
OUTPUT A CARRIAGE RETURN (NO STOPLST)
;
COPY A2 TO A4 FOR DESTTNATION OP
JSR
SPCE
TYA
BEQ
SETMDZ
DEC
YSAV
BEQ
DtJMP8
DEX
BNE
SETMDZ
CMP
$ØBA
BNE
TSTDDMP
STA
STATE
LDA
A2L
STA
(A3L),Y
INC
A3L
BNE
DUMMY
INC
A3H
RTS
SEPARATOR TEST STORE MODE OR DUMP. ZERO MODE. BRANCH ALWAYS
; TEST FOR NO LINE IF NO LINE, GIVEN A ROW OF BYTES
; TEST IF AFTER ANOTHER SPACE
STORE MODE?
KEEP IT IN STORE STATE GET BYTE TO BE STORED PUT IT IN MEMORY. BUMP POINTER
ALSO USED FOR /' TO CLEAR MODE
LDY DEY LDA STA RTS
YSAV
(INBIJF).Y STATE
USE INPUT CHARACTER TO SET MODE
;
LDA .BYTE LDA STA LDA STA LOA STA LOX LOA
SEI JSR BCS INC BNE INC INC INC JSR BCC RTS
#01 2C #02 IBCMD AlL IBBUFP A1H IBBUFP+1 A4H
ML
BLOCKIO RWERROR
ML
NOVER
A411
A1N A1N T5TA1 RWLOOP
GET DISK COMMAND TO READ DUMMY BIT TO SKIP 2 BYTES SET DISK COMMAND TO WRITE
COMMAND FORMAT IS BLOCKNUMBER <ADDRESS END ADDRESS
SEND BLOCK NUMBER VIA X & A
NO INTERRUPTS WHILE IN MONITOR DO DISKO FEVER GIVE UP IF ERROR ENCOUNTERED BUMP BLOCK NUMBER
; BUMP RAM ADDRESS BY 512 BYTES
TEST FOR FINISHED NOT DONE, DO NEXT BLOCK
LDA
A1H
STA
A211
JSR
TSTRØWID
ORA
AlL
STA
A2L
BNE
DUMBØ
GET WIDTH MASK INTO ACC BRANCH ALWAYS
LSR
A
; DUMP?
BCS
ERROR
JSR
TST8ØWID
LOA
AlL
; SET FOR EITHER 80 OR 40 COLUMNS
STA
A4L
LOA
A1H
STA MN
JSR
TSTA1
TEST FOR VALID RANGE
BCS
ERRORi
JSR
PRINTA1
JSR
NXTA1
PRINT ADDRESS AND FIRST BYTE
;
BCS
DUMPASC
END WITH ASCII
LOA
AlL
TEST END OF LINE
AND
MASK
FOR 40/80 COLUMN
BNE
DUMP3
JSR
DUMPASC
BNE
DUMP i
BRANCH ALWAYS
;
JSR
PRA1BYTE
GO PRINT NEXT BYTE AND A SPACE
;
BNE
DUMP2
ALWAYS (ACC JUST PULLED AS $Aø)
Page 6'
/
Apple Computer Inc · 1982
Page 0669 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
10/31/89 10:04
FB35 FB35 FB37 FB39 FB3B F330 F340 F342 FB44 FB46 F348 FB4A FB4C FB4F F352 F354 FB56 F358 FB5A FB5D FB5D
E'BSD
FB5E FB61 FB63 FB63 F864 FB67 F369 FB6B FB6D FB6F FB71 F873 F875 F377 F879 FB7B FB7O FB7D FB7F FBB1 FBB3 FB85 FB85 FB87 FBB8 FB8A FB8B FB8E F891 F893 F395 FBS8 FB9A FB98 FB9C FB9D FB9F FBAØ FBA2 FBA2 FBA4 FBA7 FBA7 FBA9 FBAB FBAD FBAF FBB2 FB3S FB88 FBB8 FBB8 FBBA FBBC FBBE FBCØ FBC2 FBC3 FBC5 FBC7 FBC7 FBC7 FBC9 FBCB FBCB FBCD FBCF
BD1
A5 lA 85 74 A5 7B 85 75 20 87FA AO 00 Bl 74 09 80 C9 AO 8002 A9 AS 20 39FC 20 8EF9 B006 A5 74 25 69 D0E6 4C EFFC
38
AD 53C0 B004
18
AD 52C0 AS 68 09 40 3002 29 8F 85 68 09 7F 29 AØ 85 66 8002 A9 F0 85 67
AS 58 85 5C AS 5A
85 51)
A5 5C 48 A5 SD 48 20 C5FB 20 A2FB A5 58 85 SC 20 DDFB 90F4 68 A8 68 83 SC 98 3023
AS 5C 4C 89FC
C9 80 9065 C9 80 003A 20 A2FB 20 07FB dc 16FC
A5 5D C6 5D CS SA 0002 AS SB 38 E9 01 85 5D FBC7 FBC7 A5 50 104E
24 68 7002 E6 5C E6 5C
HD:Apple ///:ROM - Monitor
"s
Page 7
DUMPASC LOA
STA
LOA
STA
JSR
ASC1
LDY
LOA
ORA
CMP
BCS
LDA
ASC2
JSR
JSR
BCS
LDA
AND
BNE
ASC3
JMP
A4L
ML
A4H A1H PRSPC
#00 (AlL),! #80 #ØAØ ASC2
tOAS COUT NXTA4 ASC3 AlL MASK ASC1 CROOT
RESET TO BEGINNING OF LINE
PRINT AN EXTRA SPACE TO INDEX MEMORY INDIRECT
SET NORMAL VIDEO TEST FOR CONTROL CHARACTERS OK TO PRINT NON CONTROLS OTHERWISE PRINT A SPACE PUT IT OUT BUMP BOTH Al ANO A4 FINISHED TEST END OF LINE
NOT DONE, PRINT NEXT
C0L80
SEC
LOA
BCS
COL4Ø
CLC
LDA
SETBØ
LOA
ORA
BCS
AND
SET8ØA
STA
ORA
AND
STA
BCS
LDA
SET8ØB
STA
CLSCRN
LDA
STA
LDA
STA
CLEOP
LDA
PHA
LOA
PEA
JSR
CLEOP1
JSR
LOA
STA
JSR
BCC
PLA
TAY
PLA
STA
TYA
BCS
CLEOL
LOA
JMP
CONTROL CMP
DCC
TSTCR
CMP
BNE
CARRAGE
JSR
JSR
JMP
ØCØS3 SET8Ø
00O52 MODES #40 SET8ØA #ØBF MODES
((7F ((OAR
FORGND SET8ØB #ØFØ BKGND
LMARGIN CH WINTOP CV
CH
CV
SETCV CLEOL LMARGIN CH CURDOWN CLEOP1
CH
SETCV
CH CLEOL1
#80 OISPLAYX #80 TSTBACK CLEOL SETCRZ NXTLIN
INDICATE 80 COLUMNS GOTO 80 COLUMN MODE BRANCH ALWAYS ; INDICATE 40 COLUMNS DESIRED COTO 40 COLUMN MODE ASSUME 80 AND BRANCH IF IT IS ; BUT FIX FOR 40 IF NOT ; ISOLATE BIT 7 ; (BIT 7 SETS NORMAL/INVERSE) ; AGAIN ASSUMES 80 COLUMNS IF NOT, SET FOR/BACKGROUND COLOR
SET CURSOR TO TOP LEFT OF WINDOW
; NOM DROP INTO CLEAR END OF PAGE SAVE CURRENT CURSOR POSITION
CLEAR TO END OF FIRST LINE
GOTO NEXT LINE
RESTORE CURSOR POSITION GET DLD CV IN ACC AGAIN BRANCH ALWAYS CLEAR TO ENO OF LINE FIRST
IF INVERSE IF CARRIAGE RETURN THEN NEW LINE FIRST CLEAR TO THE END OF THIS LINE RESET CURSOR AND GOTO NEXT LINE (CARRY IS SET) THEN GOTO THE NEXT LINE.
CURUP
CURUP1 SETCV BASCALC CURDN1
LOA DEC CMP BNE LOA SEC SBC STA .EQU
EQU LOA BPL
CV CV WINTOP CURUP1 WINBTM
#01 CV
*
*
CV BASCALC1
TEST FOR TOP OF SCREEN ANTICIPATE 'NOT' TOP
IT'S NOT TOP, CONTINUE WRAP AROUND TO BOTTOM DECREMENT BY ONE
; SAVE NEW VERTICAL LINE
GET VALUES FOR FIRST PAGE ($400) ALWAYS
CURIGHT BIT
MODES
TEST FOR 80 OR 40
BVS
RIGHT1
INC
CH
RIGHT1
INC
CH
BUMP CURSOR HORIZONTAL
I
Apple Computer Inc · 1982
Page 0670 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
10/31/89 10:04
FBD3 FBD5 F807 F809 FBDB FBDD FBDD F800 FBDF FBE1 FBE3 FBE5 FBE7 FBE9 FBE9 FBEB FBED FBEF FBF1 FBF3 FBF5 FBF7 FBF9 FBFB FBFD FCØØ FCØ2 FCØ4 FCØ6 F006 FCØ8 FC0A F000 FCØE F010 F013 F013 F016 FC18 F019 F019 FC1A FO1B F010 FC1E FC20 F022 F024 F026 F027 F029 F023 F020
F029'
F030 F031 F033 F035 FC37 F038 F039 F039 FC3A F030 F035 F041
F043 FC45 F046 F047 FC4A FC4A F040 FC4E F051 F052 F054 F056 F059 F053 FC5B FC5D FOSE F061 F063 F065 F067 F068 FC6A 'C6B
A5 5C C5 59 A5 58 9050 85 50
E6 50 A5 50 CS 5B 90E2 A5 5A BØDC
C9 88 DOSO 24 68 7002 C6 50 C6 SC 3006 A5 5C C5 58 1038 20 38FB A5 59 85 SC 0007
C9 AO 909D 24 68 3002 29 7F 20 9DFC
20 CBFB B043 60
08 48 4A 29 03 09 04 85 5F 49 BC 85 61 68 29 18 9002 69 7F 85 5E ØA RA 05 5E 85 5E 85 60 28 60
48 84 6D 86 60 20 47FC A4 6D A6 60 68 60 60 6500
09 87 D004 AE 4000 60 09 8A DØE2 20 00FB 9000
AS SA 48 20 05FB A2 03 B5 5E 95 58 CA 1009 68 18
HD:Apple i/:ROM - Monitor
LOA
CH
TEST FOR NEW LINE
OMP
RMARGIN
SETCHZ
LDA
LMARGIN
JUST IN CASE WE HAVE.
BCC
CTRLRET
SETCVH
STA
CH
CURSOR AT START OF NEXT LINE
DROP INTO CURDOWN FOR WRAP AROUND
CURDOWN
INC
LOA
CMP
8CC
LOA
BCS
CV CV WINBTM CURDN1 WINTOP SETCV
MOVE CURSOR DOWN ONE LINE
;
ANTICIPATE NOT BOTTOM TEST FOR BOTTOM
BRANCH ALWAYS
TSTBACK CMP
BNE
CURLEFT BIT
BVS
DEC
LEFT8Ø
DEC
BMI
LOA
CMP
BPL
LEFTUP
JSR
LOA
STA
BNE
#88 TSTBELL MODES LEFT8Ø
CH CH LEFTUP CH LMARGIN CTRLRET CURUP RMARGIN CH CURLEFT
BACKSPACE? ; TEST FOR FOURTY OR EIGHTY MODE
TEST FOR WRAP AROUND
SAVE NEW CURSOR POSITION BRANCH ALWAYS
COUT2
CMP
3CC
BIT
BNl
AND
DISPLAYX JSR
#ØAØ CONTROL MODES DISPLAYX
#79'
DISPLAY
IS IT CONTROL CHARACTER
TEST FOR INVERSE NO PUT IT OUT STRIP HI BIT
INCHORZ JSR
NXTLIN
BCS
RTS
CURIGHT SCROLL
MOVE CURSOR RIGHT 1T5 BOTTOM, RESET CH=0 AND SCROLL RESET CH ONLY
BASCALC1 PHP
PHA
LSR
AND
ORA
STA
EDR
STA
PLA
AND
3CC
ADO
BSCLC2
STA
ASL
ASL
ORA
STA
STA
PLP
CTRLRET RTS
¡
COOT
PHA
STY
STX
JSR
LDY
LOX
PLA
RTS
000T1
JMP
A #03 #04 BAS4FI #00 BAS8H
#18 BSCLC2
#79'
BAS4L A A BAS4L BAS4L BAS8L
TEMPY TEMPX 000T1 TEMPY TEMPX
@CSWL
CALO BASE ADR TN BAS4L,H FOR GIVEN LINE NO. 0<=LINE NO.<$17 ARG=000PBCDE, GENERATE ; HAS4H=ØØØØØ1CD AND BAS4L=EABABØØØ
SAME FOR PAGE 2
SAVE CHARACTER
NORMALLY 000T1
TSTBELL CMP
BNE
BELL
LOX
ETS
LNFO
ClIP
BNE
JSR
BCO
#87 LNFD 00040
#8A CTRLPET CUROOWN CTRLRET
BELL?
;
; NO TEST FOR FORM FEED SOUND BELL
;
¡ LINE FEED?
¡ MOVE CURSOR DOWN A LINE BRANCH IF NO SCROLL NECESSARY.
SCROLL
SCRL1 SCRL2
LOA
WINTOP
PHA
JSR
SET0V
LOX
#03
LOA
BAS4L,X
STA
TBAS4L,X
DEX
BPL
SCRL2
PLA
CLC
; START WITH TOP LINE ¡ SAVE IT FOR NOW ¡ GET BASCALO FOR THIS LINE
MOVE CURRENT BASCALC AS DESTINATION
(TEMPORARY BASE ADDR.)
¡ GET DESTINATION LINE
Page 8
Apple Computer Inc · 1982
Page 0671 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
/
10/31/89 10:04
FC6C 69 01 FC6E 05 5B F070 BOlS F072 48 FC73 20 C5FB F076 A5 59 F078 4A FC79 AB FO7A 88 FC7B 30E4 FC7D Bi 5E F078' 91 58 FCB1 81 60 FCB3 91 64 F085 90F3 F087 AS 58 F089 4A
FC8A AB
FC8B B004 FCBD AS 66
F088' 91 5K F091 AS 67 F093 91 60 F095 08 F096 98 F097 ØA F098 CS 59 FC9A 9ØED
F090 60 F090 F090 24 68 FC9F 7000 FOAl 46 SC FCA3 06 50 FCA5 20 ADFC FCA8 A5 67 FCAA 91 60 FCAC 60 FOAD FCAO 48 FCAE AS 50 F080 4A F081 A8 F082 68 FCB3 BOFS FCB5 91 5K
FCB7 60 F088 FCB8 Bi 7E FCBA 20 39FC F080 09 88 FCBF FOlD Foci 09 98 FCC3 F008 F005 E6 80 F007 AS 80 F009 09 50 FCCB 0017 FCCD A9 DC FCCF 20 39FC F002 20 EFFC F005 FCOS F005 A5 6H FCD7 20 39FC FODA A0 01 F000 84 80 FCDE A4 80 FCEØ FØF3 FCE2 06 80 F054 20 60FD FCE7 A4 80 FCE9 91 7E FCEB 09 BD FCED 0009 FCEF FCEF FCEF 20 0000 FCF2 1013 FCF4 20 2EFD F0F7 09 AO FCF9 F007 FCFB 09 89 FOFO D008 FOFF 40 9FFA F002 AD Ø0CØ F005 10FB F007 A9 80 F009 40 39FC F000 F000 60 7000 FDØF
SCRL3
LASTLN CLEOL1 CLEOL2
DISPLAY
DSPBKGND
¡
DSPL8Ø
NOTCH
CANCEL GETLNZ CETLN BKSPCE NXTCHAN CROUT
STOPLST NOSTOP RDKKY
HD:Apple i/:ROM - Momtor
ADO
#01
CALCULATE SOURCE LINE.
CMP
WINBTM
IS IT THE LAST LINE?
BCS
LASTLN
YES, CLEAR IT
PUA
SAVE AS NEXT DESTINATION LINE
JSR
SETCV
GET BASE ADDR FOR SOURCE LINE
LOA
RMARGIN
MOVE SOURCE TO DESTINATION
LSR
A
DIVIDE BY 2
TAY
DEY
DONE YET
SMI
SCRL1
YES, DO NEXT LINE
LOA
(BAS4L),Y
STA
(TBAS4L),Y
LOA
(BAS8L),Y
STA
(TBAS8L),Y
BCC
SCRL3
BRANCH ALWAYS
LOA
LMARGIN
BLANK FILL THE LAST LINE
LSR
A
DIVIDE BY 2
TAY
BCS
CLEOL2
LOA
FORGND
(NORMALLY A SPACE)
STA
(BAS4L),Y
LDA
BKGND
(IF 80 COLUMNS, ALSO A SPACE)
STA
(BAS8L),Y
INY
TYA
TEST FOR END OF LINE
ASL
A
MOLT BY 2 AGAIN
CMP
RMARGIN
8CC
CLEOLL
CONTINUE IF MORE TO DO.
RTS
ALL DONE.
BIT
MUDES
BVS
DSPL80
LSR
CH
ASL
CH
JSR
DSPL8Ø
LDA
BKGND
STA
(BAS8L),Y
RTS
TEST FOR 40 OR 80 STORE THE SINGLE CHARACTERS AND RETURN INSURE PROPER 40 COLUMN DISPLAY BY DROPPING BIT 0
DISPLAY IN $400 PAGE. ALSO SET BACKGROUND COLOR
PUA
LOA
CH
LSR
A
TAY
PLA
BCS
DSPRKGND
STA
(BAS4L),Y
RTS
PRESERVE CHARACTER DETERMINE WHICH PAGE
BRANCH IF $900 PACE
LOA JER
CMP
SEQ CM? REQ
INC LOA CM? BNE LOA JSR JSR .EQU LOA JSR LDY STY LDY BEQ DEC JSR
LOY STA OMP BNE
.EQU BIT BPL JSR OMP BEQ CMP BNE JMP LOA BPL LDA JMP
(INBUF),Y COOT #88 BKSPCE #98 CANCEL TEMP TEMP #INBUFLEN NXTCHAR #ØDC COUT CROUT
*
PROMPT COOT
#01 TEMP TEMP GETLN TEMP ROCHAN TEMP (INBUF),Y #80 NOTCR
*
KBD NOSTOP KEYIN3 #ØAØ STOPLST #89 NOSTOP ERROR2 EBD STOPLST #80 COUT
ECHO CHARACTER BACKSPACE CANCEL?
NO WRAP AROUND ALLOWED. OUTPUT BACKSLASH
START AT BEGINNING OF INNUF
BACK UP INPUT BUFFER GET INPUT
TEST FOR START/STOP READ KBD IS IT A SPACE? YES, PAUSE TIL NEXT KEYPRESS. QUIT THIS OPERATION NO, IGNORE THIS KEY. YES, RESTANT
ThIP
9KSWL
Page 9
Apple Computer Inc · 1982
Page 0672 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
10/31/89 10:04
FD0F FD11 FD13 FD16 F017 FD1A FD1C FD1E FD21 FD24 FD25 F026 F027 FD2A FD2B FD2C FD2E F031 F034 F035 F037 F039 FO3B F030 F03E F040 F042 F045 F047 F048 FD48 F048 F048 F04B F010 FD4F F051 F053 F056 F058 F05B F050 FD5E F060 F060 F062 F064 F066 F069 F060 F060 FD6F F071 F074
F076 F077 F077 F079 F07A F070 FD7E FD7F
F080 F081 F082 F083 F084 F085 F086 F087 F088 F088 FD8A FD8B FD8C FD8E F090 F092 F094 F095 F097 FD98 FD98 F098 FD9A FD9D FD9D FD9E FDAØ \FDA2
A9 7F 85 63 20 88F0 48 20 35F0 B008 A5 69 20 9DFC 20 35F0 68 08 48 20 9OFC 68 28 90E8 AO Ø0CØ 2C loco 60 E6 58 0009 E6 63 A9 7F
18
25 63 F005 0E ØØCØ 90ER 60
F048 20 77FD A5 68 29 80 19 AB 85 69 20 ØCFD AØ 08 09 FØFF FØEB 88 10F8
A9 80 25 68 85 69 20 0CFD C9 9B FØDE C9 95 00D6 20 88FD 09 80 60
A9 FO 48 09 7FFD 48 60 Al
84 7C 62
5C EC CA DC 07
AS SC 4A A8 24 68 5005 9003 Bi 60 60 Bi 5E 60
FD98 A9 03 8D DOFF F090 D8 A2 03 86 7F BD BCFF
KEYIN KEYIN1
KEYIN2
KEYIN3 KEYIN4 KEYWAIT
KWAIT2 KEYRET
HD:Apple i/:ROM - Monitor
LOA
#7F
STA
TBAS4H
JSR
PICK
PHA
JSR
KEYWAIT
BCS
KEYIN2
LOA
CURSOR
JSR
DISPLAY
JSR
KEYWAIT
PLA
PHP
PHA
JSR
DISPLAY
PLA
PLP
0CC
KEYIN1
LOA
KBD
BIT
KBDSTRB
RTS
INC
TBAS4L
BNE
KWAIT2
INC
TBAS4H
LOA
#7F
CLC
AND
TBAS4H
BED
KEYRET
ASL
ROD
0CC
REYWAIT
RTS
MAKE SURE FIRST IS CURSOR GO READ SCREEN SAVE CHR AT CURSOR POSITION TEST FOR KEYPRESS GO GET IT ; GIVE THEM AN UNDERSCORE FOR A TIME GO SEE IF KEYPRESSEO SAVE KEYPRESS STATUS
READ KEYBOARD CLEAR KEYBOARD STROBE JUST KEEP COUNTING
; TEST FOR DONE
; RETURN IF TIMED OUT
Page
¡
ESC3 ESCAPE
ESCi ESC2
.EQU JSR LDA AND EOR STA JSR
LDY CMP BED DEY BPL
*
GUESC MODES #80 #ØAB CURSOR RDKEY #08 ESCTABL,Y ESC3
ESC2
SET TO + SIGN FOR CURSOR MOVES
READ NEXT CHARACTER TEST FOR ESCAPE COMMAND
LOOP TIL FOUND OR DONE
RDCHAR
LDA AND STA JSR CMP BED CMP ONE JSR ORA RTS
#80 MODES CURSOR RDKEY #9B ESCAPE
#95 REYRET PICK #80
GO READ A CHARACTER SAVE STANDARD CURSOR ; ESCAPE CHARACTER? ; FORWARD COPY? GET CHARACTER FROM SCREEN ; SET TO NORMAL ASCII
GDESC ESCVECT
PICK PICK40
LDA PHA LDA PHA RTS .BYTE .BYTE .BYTE .BYTE .BYTE .BYTE .BYTE .BYTE .BYTE
LOA LSR TAY BIT BVC ECC LDA RTS LOA RTS
#ØFB
ESCVECT,Y
ØA1 84 7C
62 5C
ØEC ØCA ØDC 0B7
CH A
MODES PICK4Ø PICK4Ø (BAS8L),Y
(BAS4L),Y
¡ CLEOL-i CLEOP-i
; CLSCRN-i ; CDL4Ø-1 ; C0L80-1 ; CURLEFT-i ; CURIGHT-i ; CURDOWN-i ; CURUP-i
GET A CHARACTER AT CURRENT CURSOR POSITION DETERMINE WHICH PAGE.
; AND IF 80 COLUMN MODE FORGET CARRY IF 40 COLUMNS
; GET CHARACTER FROM $400
CLDSTRT
.EQU
*
LDA
#03
STA
0FFD0
ZERO PAGE IS ON 3!
SETUP
.EQU
*
CLD
OF COURSE!
LOX
#03
STX
INBUF+1
SETUP1
LDA
NNIRQ,X
i
Apple Computer Inc · 1982
Page 0673 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
'10/31/89 10:04
FDA5 9D CAFF FDA8 BD B4FF FDAB 95 6E FDAD BD B8FF FDBØ 95 58 FDB2 CA FDB3 leED FDB5 85 82 FOB7 A9 AO FDB9 85 7E FDBB A9 60 FDBD 85 81 FDBF A9 FF FDC1 85 68 FDC3 20 63FB FDC6 FDC6 ØOAØ FDC6 ØØAØ FDC6 ØØA1 FDC6 00A2 FDC6 00A3 FDC6 00A4 FDC6 ØØCØ FDC6 CØDB FDC6 CØDA FDC6 FFEC FDC6 FFED FDC6 FDC6 FDC6 A9 78 FDC8 85 AO FDCA A9 08 FDCC 85 Al FDCE A9 F0 FDDØ 85 A4
FDD2 M 00
FDD4 AA FDD5 95 C0 FDD7 E8 FDD8 E0 20 FDDA DØF9 FDDC A9 05 FDDE 18 FDDF 08 FDEØ 48 FDE1 86 A2 FDE3 AØ 07 FDE5 A6 A2 FDE7 8A FDE8 91 AO FORA E8 FDEB 88 FDEC 3006 FDEE C0 03 FDFØ 00F5 FDF2 FØF1 FDF4 20 99FE FDF7 B008
FDF9 C9 ØA FDFB DØE6 FDFD A2 24 FDFF DØEØ
F501 68 FEØ2 28 FEØ3 A2 17 FR05 A0 05 FEØ7 36 C4 FEØ9 ØA FERA D0ØE FEØC 84 A2 FEØE C6 A4 FE1O F016
FE12 AA M
FE14 B9 C4FE FR17 2A FE18
FE18 AA A2 FEÌA 88 FE1B DØEA FElD CA FE1E 10E5 FE2Ø 08
FE21 48 FE22 20 28FE FR25 4C 01FR FR28
FR28 FE28 FE28
FE28 A2 1F FE2A A0 00
ADR CPORTL CPORTH CTEMP CTEMP1 YTEMP ROWTEMP CWRTON CWRTOFF CR2CTRL CB2INT
HD:Apple i/:ROM - Monitor
STA
ØFFCA,X
LOA
HOOKS,X
STA
CSWL,X
LDA
VBO(JNDS,X
STA
LMARGIN,X
DEX
BPL
SETUP1
STA
IBDRVN
LOA
IØAØ
STA
INBUF
LDA
#60
STA
IBSLOT
LDA
10FF
STA
MODES
JSR
COL4Ø
INPUT BUFFER AT $3A0 SET 40 COLUMNS, CLEAR SCREEN
.EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU
ØAØ ADR ADR+1 ADR+2
ADP.+3 ADR+4
ADR+20 ØCØDB ØCØDA ØFFEC ØFFED
Page 11
GENENTR LOA
STA
LDA
STA
LDA
STA
LOA
TAX
ZIPTEMPS STA
INX
CPX
BNE
LDA
CLC
PUP
PUA
GENASC
STX
GASCI1
LDY
GASCl2
LOX
GASCI3
TXA
STA
INX
DEY
BMI
CPY
BNE
REQ
GASCI4
JSR
BCS
CMP
SNE
LOX
BNE
CHYTES
PLA
PLP
LDX
CCOLMS
LDY
CSHFT
ROL
ASL
BNE
STY
DEC
REQ
LDY
LOA
ROL
LO? SHFTCNT DEY
BNE DEX BPL PHP PUA JSR JMP
#78 CPORTL #08 CPORTH #ØFØ YTEMP #00
ROWTEMP,X
#20 ZIPTEMPS 105
INIT SCREEN INDX LOCATIONS SET UP INDEX TO CHRSET
FAXE THE FIRST BIT PATTERN (PHANTOM 9TH BIT SHIFTED AS BIT 0)
CTEMP #07 CTEMP
GENERATE THE ASCII CODES FOR THE FIRST PASS
CCPORTL),Y
GASCT4 #03 GASCI3 GASCl2 NXTPORT CBYTES lOA GASCI1 #24 GENASC
$XXF=CHR 0 / 4 $XXE=CHR 1 / 5 $XXD=CHR 2 / 6 $XXC=CHR 3 / 7 $XXB=CHR 0 / I $XXA=CHR 1 / 5 $XX9CHR 2 / 6 $XX8=CHR 3 / 7 GO DECODE CHARACTER TABLE SECOND SET OF 4?
BRANCH ALWAYS RESTORE BIT PATTERN
#17 #05 ROWTEMP+4,X A SHFTCNT CTEMP YTEMP DONE YTEMP CHRSET-1,Y A
CTEMP
CSHFT
CCOLMS
(4 CHARACTERS OF 6 ROWS) (FIVE COLUMNS) BREAK BYTE INTO ; 5 BIT GROUPS BRANCH IF MORE BITS IN THIS BYTE
(NOTE. CARRY IS SET) ; BRANCH IF ALL DONE
GET CHARACTER TABLE INDEX
(CARRY KEEPS BYTE NON-ZERO UNTIL ALL 8 ARE ARE SHIFTED) RESTORE COLUMN COUNT GOT ALL FIVE BITS? NO, DO NEXT ALL ROWS DONE NO, DO NEXT SAVE REMAINING BIT PATTERN AND CARRY
STDRCHRS CBYTES
MOVE EM TO NON DISPLAYED VIDEO AREA
DONE
.EQU
STURCHRS LOX
11F
MOVE CHARACTER PATTERNS TO VIDEO AREA
STORSET LDY
#00
I
Apple Computer Inc · 1982
Page 0674 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
f
10/31/89 10:04
FE2 C
F52 E
F52 F
F531 FE33 FE34 F535 FE37 FE39 FE3C FE3E FE4Ø
FE4 i
F543 FE44 FE44
F54 6 F54 8
FE4 A
FE4D FE5Ø FES2 FE55 FE58 FE5B FE5D FE5F FE61
FE 63
FE65 FE67 FE68
FE 6A
FE6C
FE 6 D
FE6F F572 F574 FE75
FE7 7
FE7 9
FE7C
FE 7F
FE 80
FE 82
F584 F586 FE88 FE88 FE8A FE8C F585 FE9Ø FE91 FE93 FE96 FE98 FE99 F599 FS9B F590 FE9F FEA1 FEA3 FEA5 FEA7 FEA9 FEAR FEAR FEAE FEAE FEBO
FEB 3
FEB5 F537 FERA FEBC FEBF FEC2 FEC4 FEC5
FEC 5
FEC5 FEC5 FECC FED3 FED9 F550 FEE7
EEB
B5 C0 ØA 29 3E 91 A0 CA C8 CO 08 DØF3 20 99FE C9 08 F004 8A 1057 60
A9 01 85 A2 A9 60 2C DBCØ 20 AEFE AR 20 20 ARFE 2C DACØ 20 B8FE C6 A2 1016 A9 08 85 Al AO 07 Bl A0 18 69 08 91 AO 88 10F6 20 99FE 905F 60 AO 03 A9 7F 99 FCOS 99 FCØ7 88 10F7 A9 08 85 Al OOCØ
AO 07 Bi AO 49 20 91 AO 88 1OF7 20 99FE 90F0 60
A5 AO 49 80 85 AO 3002 E6 Ai A5 Al C9 OC 0004 A9 04 85 Al 60
85 A3 AD ECFF 29 3F 05 A3 80 ECFF A9 08 8D EDFF 2C EDFF FØFB 60
FEC5
F0 01 82 18 40 84 81 2F 58 44 81 29 02 15 01 91 7C 1F 49 30
8A08 431431 2A 22
13 E3 F7 C4 91 48 P.2 DA 24 C6 4A 62 8C 24 C6 F8 63 8C
STOROW
GENDONE GENl
NXTASCI NXTASC2
GEN2 UNDER
ALTCHR ALTC1
NXTPORT NOHIGH PORTDN VRETRCE VWAIT CHRSET
HD:Apple i/:ROM - Monitor
Page 12
LDA
ROWTEMP,X
ASL
A
SHIFT TO CENTER
ANO
#35
STRIP EXTRA GARBAGE
STA
(CPORTL),Y
DEX
IN?
CPY
#08
BNE
STOROW
JSR
NXTPORT
THIS GROUP DONE
;
; NO, NEXT ROW
CMP
#08
BED
GENDONE
ALL ROWS STORED?
TXA
BPL
STORSET
RTS
PARTIAL SET ($478-$5FF)
LOA
#01
STA
CTEMP
SET NORMAL MODE
;
LDA
#60
PREPARE TO SEND BYTES TO CHARACTER
BIT
CWRTON
GENERATOR RAM
JSR
VRETRCE
WAIT FOR NEXT VERTICAL RETRACE
LOA
#20
WAIT AGAIN
JSR
VRETRCE
BIT
CWRTOFF
CHARACTERS ARE NOW LOADED
JSR
ALTCHR
REPEAT THIS SET FOR OTHER 61 CHARACTERS
DEC
CTEMP
HAVE WE DONE ALTERNATES YET?
BPL
GEN2
LOA
#08
; NO, DO IT! BUMP ASCII VALUES FOR NEXT SET
STA
CPORTH
LO?
407
THE USUAL COUNTDOWN
LOA
CCPORTL),Y
CLC
AOC
#08
STA
(CPORTL),Y
DEY
BPL
NXTASC2
JSR
NXTPORT
BCC
NXTASCI
RTS
LO?
#03
SETUP ALTERNATE WITH UNDERLINES
LOA
#7F
STA
Ø5FC,Y
STA
Ø7FC,Y
DEY
BPL
UNDER
LOA
#08
STA
CPORTH
REE
GENi
LO?
#07
ADJUST ASCII FOR ALTERNATE SET
LOA
(CPORTL),Y
SOR
#20
$20--> $4O-->$60
STA
(CPORTL),Y
0E?
BPL
ALTC1
ADJUST THEM ALL
JSR
NXTPORT
3CC
ALTCHR
RTS
LOA
CPORTL
EOR
480
STA
CPORTL
BNl
NOHIGH
INC
CPORTH
LOA
CPORTH
CMP
#ØC
BNE
PORTDN
LOA
#04
STA
CPORTH
RTS
CONVERT $78->$F8 OR $F8-$78
STA
CTEMP1
LOA
CB2CTRL
ANO
43F
ORA
CTEMP1
STA
CB2CTRL
LOA
408
STA
CB2INT
BIT
CB2INT
BED
VWAIT
RTS
SAVE BITS TO BE STORED CONTROL PORT FOR CB2 RESET HI BITS TO 0
TEST VERTICAL RETRACE
WAIT FOR RETRACE
.EQU
*
.BYTE ØFØ,0l,82,18,10,84,81,2F,58,44,81,29,02,1E,01,91,7C,1F,49,30
.BYTE 8A,08,43,14,31,2A,22,13,0E3,0F7,0C4,91,48,0A2,0DA,24,0C6,4A
.BYTE 62,8C,24,0C6,0F8,63,8C,ØC1,46,17,52,8A,ØAF,16.i4,0E3,33,31 I
Apple Computer Inc · 1982
Page 0675 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
/ 10/31/89 10:04
HD:Apple i/:ROM - Monitor
Page 13'
FEF2 Cl 46 17 52 8A M' 16
FEF 9 14 03 33 31
FEFD C6 F8 DC 73 3F 46 17 FF01 62 BC 21 E6 18 LA 8D
.BYTE 0C6,0F8,ØDC,73,3F,46,17,62,8C,21,0E6,18,6A,8D,61,ØCF,18,62
FF00 61 CF 18 62
FF0F 74 Dl B9 1.8 49 4C 91 FF16 C0 F3 09 2C 91 C0 14
.BYTE 74,ØD1,0B9,18,49,4C,91,ØCØ,0F3,09,2C,91,ØCØ,14,1D,8C,ØEF,Ø7
FF1D 1D BC EF 07
FF21 17 43 88 31 84 lE DF
BYTE 17,43,88,31,84,1E,ØDF,ØB,31,84,0F8,ØFE,77,391,3E,17,62,8C,ØFD
FF28 00 31 84 F8 FE 77 3E
FF2F 3E 17 62 BC ED
FF34 C7 50 E3 OB 51 C5 E8
.BYTE 0C7,50,0E3,ØB,51,0C5,0E8,0C8,73,18,ØC,42,3E,01,02,20,42,3E
FF3B CS 73 18 OC 42 3E 01
FF42 02 20 42 3E
FF46 41 18 8C 08 00 70 0E FF4D 00 11 11 21 11 02 00
BYTE 41,18,8C,08,00,70,ØEE,00,11,11,21,11,02,0E0,3C,21,31,02,ØEØ
FF54 3C 21 31 02 E0
FF59 1C 00 CS B9 80 62 14 FF60 1F 46 A2 DE 43 2C 04 FF67 88 BE FF CE
BYTE IC,00,0C8,ØB9,8Ø,62,14,1F,46,0A2,ØDE,43,2C,Ø4,88,ØBE,ØF9',ØCE
FF60 7D 37 49 88 95 18 98 FF72 09 62 Dl 44 Ea 88 F0
.BYTE 7D,37,49,88,95,18,98,09,62,ØDÎ,44,0E8,88,ØFB4O2,90,40,00,10
FF79 02 90 40 00 10 FF70 E0 03 02 00 40 00 00
FF85 08 00 00 28 10 42 44
.BYTE ØEØ,03,02,00,40,00,00,08,00,00,28,10,42,44,25,82,0B8,2F,48
FF 8C 25 82 B8 2F 48
FF91 25 44 10 82 02 00 2F
.BYTE 25,44,10,82,02,00,2F,5A,40,45,02,8E,64,50,90,01,3E,26,42,80
FF98 5A 40 45 02 8E 64 50
FF9F 90 01 3E 26 42 80 FFA5 21 80 00 05 00 F8 80 FFAC 00 05 08 F8 80 28 05
.BYTE 21,80,ØO,05,ØO,ØF8,8Ø,Ø0,Ø5,Ø8,ØF8,8Ø,28,Ø5,88
FFB 3 88
FFB4
FFB4 FFB4
H000S
EQU
*
FFB4 FFB6
FFB 8 FFB 8
FFBC
Ø6FC 0FFD FF08 00 50 00 18
VBOUNDS
.WORD .WORD .000 BYTE
COUT2 KEYIN
*
00,50,00,18
FFBC 4C 86F6 FFBF 40
MIRQ
JMP
RECON
PT I
; IN DIAGNOSTICS
FFCØ
FFCØ 43 4F 50 59 52 49 47 FFC7 48 54 20 4A 41 4E 55
.ASCII 'COPYRIGHT JANUARY, 1980 APPLE COMPUTER INC.. JEH"
FFCE 41 52 59 2C 20 31 39
FFD5 38 30 20 20 41 50 50
FFDC 4C 45 20 43 4F 4D 50
FFE3 55 54 45 52 20 49 4E
FFEA 43 2E 2E 4A 52 48
FFFØ
FFFØ CC D0 03 B4 B8 88 95 ESCTABL
.BYTE 0CC,ØDØ,0D3,0B4,0B8,88,95,8A,8B4O0
FFF7 8A 80 00
FFFA FFFA FFFC FFFE 0000 000g
CAFF
EEF4 CDFF
SYMBOL TABLE DUMP
MI RESET 1RO
.NORD .WORD .WORD
END
ØFFCA DIAGN 0FFCD
NOTHING
(4so or"'
«i,
AB - Absolute PF - Ref PB - Public
LB - Label DF - Def PV - Private
UD - Undefined PR - Proc CS - Consts
MC - Macro FC - Func
AlP
AB 0075 AlL
AB 0074
A1PC
LB F906 A1PC1 LB F9D9 A20
AB 0077
A2L
AB 0076 A3H
AB 0079 A3L
AB 0078 A4H
AB 0070 A4L
AB 007A
ADR
AB 00A0 ALTC1
LB FE8A ALTCHR LB FE88
ASC1
LB F040 ASC2
LB FB4C
ASC3
LB FB5A
ASCDONE LB FAØ8
ASCII
LB FAlB
ASCII0 LB FA1D
ASCII1 LB F901
ASCII2 LB F9E3
ASCII3 LB F9F4
BAS4H
AB 005F
BAS4L
AB 005E
BAS8H
AB 0061
BAS8L AB 0060 BASCALC LB FBC7 BASCALC1 LB FC19 BELL
LB FC4E BITOFF LB FA29
BITON LB FA25 BKGND AB 0067 BKSPCE LB FCDE BL1
LB FAB4 BLOCKIO AB F479
BSCLC2 LB FC2D CANCEL LB FCCD CARRAGE LB FEAR CB2CTRL AB FFEC CB2INT AB FFED
CBYTES LB FEØ1 CCOLMS LB F005 CH
AB ØØSC
CHRSET LB FEC5
CONDE
LB lAiE
CLDSTRT LB FD98
CLEOL
LB FBA2
CLEOLI LB FC89
CLEOL2 LB FC91
CLEOP
LB FB85
CLEOP1 LB FB8E
CLSCRN LB FB7D
CMDSRCH LB F91C
CMDTAB LB F96C
CMDVEC LB F97D
COL4Ø
LB F063
C0L80
LB FB5D
CONTROL LB FBA7
COUT
LB FC39
COUT1
LB FC47
COUT2
LB FCØ6
CPORTH AB ØØA1
CPORTL AB 00A0 CRCHK
LB F9FD
CRMON
LB FA3A
CROUT
LB FCEF
CSHFT
LB FE07
CSWH
AB 006F CSWL
AB 006E CTEMP AB 00A2
CTEMP1 AB 00A3 CTRLRET LB FC3B CURDN1 LB FBC7 CURDOWN LB FOOD CURIGHT LB FBCB
CURLEFT LB FBED
CURSOR AB 0069
CURUP
LB FBB8
CURUI'l LB FBC2
CV
AB 005D
CWRTOFF AB CODA CWRTON AB CODO DEST
LB FAA5
DIAGN AB F400
DIGIT
LB F941
DIGRET LB F96B
DISPLAY LB FC9D
DISPLAYX LB FC1Ø
DONE
LB FE28 DSPBKGND LB FCAA
DSPL80 LB FCAD
DUMMY
LB FACB
DUMP
LB FBØD
DUMPØ LB F010
DUMP1
LB F011I
DUMP2
LB F020
DUMP3
LB F030 DUMP8
LB FAFD
DUMPASC LB F035
ENTRY
LB F901
ERROR
LB FAA2
ERRORi LB FB0B
ERROR2 LB FA9F
ESCi
LB FD53 ESC2
LB FD58
ESC3
LB F048 ESCAPE LB FD4B ESCTABL LB FFFO ESCVECT LB FD7F FORGND AB 0066
GASCI1 LB FDE3
GASCl2 LB FIlES
GASCII LB FDE7
GASCI4 LB FDF4
GENl
LB FE48
,/
Apple Computer Inc · 1982
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GEN2
LB FE75
GETLNZ LB FCD5
IBBUFP AB 0085
INSUFLEN AB 0050
KBDSTRB AB COlO
KEYIN4 LB F031
KWAIT2 LB F042
LMARGIN AB 0058
MON
LB F904
NMI
LB FFFA
NOVER LB FAF3
NXTBAS LB F94F
NXTINP LB F915
PCL
AB 0072
PRBYCOL LB F9C4
PRHEX2 LB F9C1
RDCHAR LB FD6Ø
REPERTi LB FA35
RETAl
LB F9AD
RWLOOP LB FADB
SCRL3
LB FC7A
SET8Ø LB F067
SETCVH LB FBDB
SHFTCNT LB FE1A
STOPLST LB F002
STORSET LB FE2A
TBAS8L AB 0064
TST8ØWID LB F9CB
TSTDUMP LB FBØA
VRETRCE LB FEAT
WINBTM AB 005B
ZIPTEMPS LB F005
GENASC GETNUM IBCMD INCHORZ KEYIN KEYRET LASTLN LNFD MONITOR NMIRQ NXTA1 NXTBIT NXTLIN PICK PRBYTE PRHEXZ RDKEY RESET RIGHT1 SAVCMO SCRNLOC SET8ØA SETMOZ SPCE STOR SVMASK TEMP TSTA1 UNDER VRFY WINTOP ZSTATE
LB FDE1 LB F92C AB 0087 LB FC13 LB F0ØF LB F047 LB FC87 LB FC52 PR ---LB FFBC LB F994 LB F947
LB FC16 LB F088 LB F9AE LB F9B9 LB FDØC LB FFFC LB FBD1 LB FAD9 AB 0058 LB FB6F
LB FAD1 LB FAB8 LB FABF LB F903 AB 0080 LB F99D
LB FE79 LB FA4F AB 005A LB F967
Assembly complete:
1129 lines
0 Errors flagged on this Assembly
HD:Apple ///:ROM - Monitor
GENDONE GO IBDRVN
1RO KEYIN1 KEYWAIT LEFT8Ø MASK MONZ NOBIGH NXTA4 NXTBS2 NXTPORT PICK4Ø PRBYTSP PRINTA1 READ RETi RMARGIN SCAN SCROLL SET8ØB SETMODE
SRCH1 STOR1 TBAS4H TEMPX TSTBACK USER VRFY1 WRTE
LB FE44 LB FA91 AB 0082 LB FFFE LB F016 LB F035 LB FBF3 AB 0069 LB F908 LB FEA3 LB F98E LB F959 LB FE99 LB F095 LB FA84 LB FA75 LB FAD4 LB F7FE AB 0059 LB F912 LB FC5B LB FB7B LB FACC LB FA15 LB FAC3 AB 0063 AB 006C LB FBE9 LB FA8C LB FA54 LB FA07
GENENTR LB FDC6
GOESC LB F077
IBSLOT AB 0081
JUMP
LB FA8F
KEYIN2 LB F024
KSWH
AB 0071
LEFTUP LB FBFD
MISMATCH LB FA66
MOVE
LB FA4Ø
NOSTOP LB F007
NXTASC2 LB FE65
NXTCHAR LB FCE4
OLDPC LB F9EØ
PORTDN LB FEAD
PRCOLON LB F9C7
PROMPT AB 006B
RECON AB F686
RET2
LB F900
ROWTEMP AB 0000
SCRL1
LB FC61
SEARCH LB FAØ9
SETC}IZ LB FB07
SETUP LB F090
STACK AB 006A
STORCHRS LB FE28
TBAS4L AB 0058
TEMPY AB 006D
TSTBFILL LB FC4A
USERADR AB 0358
VRFY2 LB FA6Ø
YSAV
AB 0070
GETLN
LB FCD5
HOOKS LB FFBI
INBUF AB 007E
KBD
AB C000
KEYIN3 LB F025
KSWL
AB 0070
LFA36
LB FA36
MODES AB 0068
MOVNXT LB FA45
NOTCR LB FCB8
NXTASCI LB FE63
NXTCHR LB F932
PCH
AS 0073
PRA1BYTE LB FA82
PRHEX LB F9B7
PRSPC LB FA87
REPEAT LB FA2O
RET3
LB F882
RWERROR LB FA97
SCRL2
LB FC63
SEP
LB FASE
SETCV LB FBC5
SETUP1 LB FDA2
STATE AB 007C
STOROW LB FE2C
TBAS8H AB 0065
TOSUB LB F95E
TSTCR LB FRAB
VBOUNDS LB FFB8
VWAIT LB FESE
YTEMP
AB 00A4
-'A
Page 14
6502 OPCODE STATIC FREQUENCIES
ADC: 5
*AA
AND :
14
ASL :
12
BCC : 21
BCS: 20
AA ** AA *A AA At
BEQ: 82
BIT :
12
AttA Att
BMI :
7
BNE :
41
AA At AttA **tA ** AA ** AA AA At At
BPL :
18
BVC: 2
BVS: 3
CLC:
7
CLO: 2
CMP: 35
A*AAA* AA AA** AA
AA
CPX: 1
CPY: 2
DEC: 7
DEX: 7
DEY :
9
EOR: 6
INC :
18
**A** AtA
AA At At AA Akt
INX:
3
INY:
3
JMP: 18
JSR : 79
LOA : 117
LOX :
12
LOY: 20
******A***********AAAA*****AAAAAAAAAAA*A*tttt***** **A**AAA***AAAAA*AAAAAAAAAAA*AA*AAAAA*AtAttttttttttt**A*A**t****AA****tt*A*
AA At AA A
AA AA A A AA Akt A
LSR :
li
ORA: 10
AA AA AAA
PElA: 16
PHP: 4
PLA :
14
PLP: 3
ROL: 4
At
RTI : RTS :
im
34
AA AA AA AA AA AttA AA **
SSC :
67
SEC: 5
SEI :
STA :
STX: STY:
im
72
*****AAA**AAA*A**AAAA****AAAAAAAAAA**AA*A****A
7
AAAA
5
AA*
TAX: 2
TAY : TSX
5im
TXA TXS
2i1m
TYA
31
I
Apple Computer Inc · 1982
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Minimum frequency = Maximum frequency = 117 Average frequency = 17 Unused opcodes: BRX CLI CLV NOP ROR SED Program opcode usage: 89 %
(1.00) Thats all, Folks -
HD:Apple i/:ROM - Monitor
Page 15"
I
Apple Computer Inc · 1982
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g
Apple III Computer Information
'E
Inside the Apple III ROM
Document Table of Contents
Revision 2 Revision i
04 Dec 1997 30 Nov 1997
Apple Computer Inc · 1982
Page 0679 of 0730
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g
Apple III Computer Information
Inside the Apple III ROM
Revision 2
04 Dec 1997
Apple Computer Inc · 1982
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Inside the Apple III Computer ROM
David T. Craig 04 December 1997 71533. 606@compuserve. corn
TABLE OF CONTENTS
i INTRODUCTION
2 ROM SECTIONS 3 IMPORTANT ROM ROUTINES 4 ROM TABLES 5 ROM USAGE BY SOS
MONITOR COMMANDS 7 A FEW COMMENTS 8 REFERENCES 9 DOCUMENT MODIFICATION HISTORY
I INTRODUCTION
This document provides a general overview of the contents of the Apple i/I
computer ROM revision 1. This information should be used in conjunction with a copy of the ROM source code listing. The audience of this document is anyone with an interest in the technology of the Apple ¡/1 computer's hardware and software
NOTE
There were two revisions of the Apple /1/ ROM, revision O and revision 1. Revision O ROMs had at address F1B9 the value 60. Revision I ROMs had at
address F1B9 the value AO.
This ROM contains 4 KB of 6502 programming and several data tables. The ROM occupies memory addresses F000-FFFF. The basic purpose of the ROM is to test
the Apple /1/ computer hardware and boot an operating system from the I/I's
built-in floppy disic. drive. The ROM also contains a simple Monitor program whose
purpose is to allow the user to interact with the /1/ at the hexadecimal level.
Apple planned from an architectural perspective to support two 4K ROMs. But only one ROM was ever created. The Environment Register let you control which ROM was active. Both ROMs shared the same address space so you could only have one ROM active at a time. This feature would have doubled the ROM's
effective size providing Apple with more room for ROM-based features that higherlevel /1/ software (e. g. sos) could have used.
When the Apple /1/ computer is turned on the ROM's flow of execution is as
follows:
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i) The ROM starts execution at the address contained in FFFC-FFFD (RESET) which is
address F4EE (DIAGN).
Diagnostics (DIAGN/F4EE) starts. The diagnostic first initializes sorne memory for the ROM's use. If the Open Apple and the Control keys are held down then enter the ROM Monitor. Otherwise run several diagnostic checks of the /1/ hardware (tests zero page, sizes memory, initializes screen text buffer, tests stack memory, tests ROM checksum, tests VIA chip, tests ACIA chip, tests A/D circuitry, tests keyboard connection). Any diagnostic failures display an error message and the user has to reset the computer.
Read block 0 (512 bytes) to address A000 from the floppy disk in the built-in disk drive
(BO0T/F6A1). If no disk is found or block O cannot be read then display "RETRY" and wait for the user to reset the computer. If the block is successfully read then execute the block contents (this is called the SOS Bootstrap Loader: see section ROM USAGE BY
sos).
2 ROM SECTIONS
Section Address Purpose Disk I/o F000-F4C4 Read and write floppy disk blocks (512 bytes each)
Diagnostics F4C5-F7FE Diagnose the /1/ hardware Monitor F7FF-FFFF Interacts with user so user can do simple things
3 IMPORTANT ROM ROUTINES
BLOCKIO / F479
Reads or write a disk block (512 bytes), calls routine REGRWTS (F000) which reads a sector (256 bytes) from the disk.
BOOT f F6A1
ENTRY / F901
I DIAGN F4EE
USRENTRY/F6E6
Read floppy disk block 0 into address A000, execute the block.
Monitor entry point.
Diagnostic entry point.
Tests RAM and displays a table showing chip failures (users may execute this routine from the Monitor). This test is aimed at Apple I//s with 126K of RAM that exists on the older 12-Volt RAM boards. Though this routine will work with the newer 5-Volt RAM boards (256K) this test shows wrong information when RAM errors occur since the two RAM boards contain a different number of RAM chips. You can identify the different RAM boards as follows: The SV boards have a large gray ceramic resistor near the edge and the 12V boards have a small blue tubular capacitor. To test the ///'s RAM you really should use Apple's ¡/1 Diagnostics Disk which lets you specify which RAM board you have.
4 ROM TABLES
Here's a list of the important data tables in the ROM. This list does not include disk I/O tables.
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Table Name f Address Contents
CHRSET / FEC5-FFB3
Default character set (overridden when SOS loads the character
set from SOS. DRIVER)
Copyright / FFCO-FFEF
Copyright message (contains the initials "JRH" for J. R. "Dick"
Huston who was a key player behind the f/f and Sos)
NMI / FFFA-FFFB
Jump address for the Non-Maskable Interrupt signal
RESET / FFFC-FFFD
Jump address when the /// is powered on
IRQ / FFFE-FFFF
Jump address for the Interrupt Request signal
5 ROM USAGE BY SOS
The Apple ¡/1 operating system (Sos = Sophisticated Operating System or Sara's os) uses several ROM routines. These routines seem to all be related to disk block I/O. The following discussion is based on SOS version 1.3.
When the ROM loads block O from a SOS disk the ROM is loading the SOS Bootstrap
Loader program. This program, which is at most 512 bytes in length, uses the ROM routine REGRWTS (F000) to read the SOS Loader into memory. This program does not test the ROM revision. It is interesting to note that ROM routine BLOCKLO is not used, instead a lower-level routine (REGRWTS) is used.
The SOS Loader determines if the ROM is revision I by comparing address F1B9's contents against AO (reference: SOS source file SOSLDR. D. SRC). If this comparison
fails then SOS displays on the screen the error «ROM ERROR: PLEASE NOTIFY YOUR DEALER." I! the ROM revision is correct then the SOS loader uses the ROM's disk 1/O routines to read more of SOS into memory.
The disk /1/ driver that is built into SOS also uses the ROM to perform disk block I/O (reference: DISK3. SRC). It is interesting to note that when the disk driver is initialized the driver checks if the ROM revision is O or 1. A revision of O is detected lt address F1B9 contains 60. 1f neither revision is found then the disk driver returns an error to SOS (I don't think this will ever happen since the SOS loader has already determined that the ROM is revision i). For a valid ROM revision the disk driver sets up several jump vectors which point to the appropriate addresses in the ROM for the various ROM routines needed by the disk
driver. Therefore, the disk driver seems compatible with either ROM revision whereas the SOS loader likes only revision 1.
The
CONSOLE driver source listing appears to not use any ROM routines even
.
though the ROM contains 40 and 80 column text routines and keyboard input
routines. I assume the console driver was much more sophisticated than the
ROM's text features and so using the ROM routines would not have worked well for
this driver. I also assume that if the console driver used the ROM that when ROM
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revision I was built the console driver would have had to be changed and Apple (smartly) did not want to do this.
6 MONITOR COMMANDS
Holding down the Open Apple and Control keys when the /1/ starts or when you press the Reset Key activates the i/I ROM Monitor. The screen will display in the upper left corner a small right-facing arrow with a blinking underscore character as the cursor. The Monitor's commands are based on the Apple J ['s Monitor commands but some commands have changed slightly and others are new for the
(newer) /1/.
The Monitor supports the following commands:
addrl. addr2
Dump memory data to screen from address i to address 2 and display ASCII character at the right of the screen.
CARRIAGE RETURN Dump next line of addresses to the screen.
SPACE
Pause current memory dump. Press again to continue.
addr:byte..Jist
Store starting at the address the list of bytes.
addr: 'text'
Store text starting at address with high bit clear.
addr: "text"
Store text starting at address with high bit set.
addr3<addrl.addr2M Move data in addresses 1-2 to address 3.
addr3<addrl.addr2V Verify data in addresses 1-2 is the same as data starting at address 3.
byte<addrl.addr2S Search memory in address range 1-2 for the byte.
block<addrl.addr2W Write address range to disk starting at the disk block.
block<addrl.addr2R Read disk starting at block to the address range.
addrG
Call subroutine at the address.
addrJ
Jump to the address.
U
Call user routine starting at address $03F8.
X
Repeat last command line until you press the SPACE BAR.
ESC-8
Display 80 columns of text.
ESC-4
Display 40 columns of text.
/
Seperate multiple commands on the same line.
CTRL-I
Interrupt current operation, return to Monitor command line.
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Note: See Wells' Apple 47Entry Points article for a great overview of the ROM
MonItor, its commands (with some syntax errors), and the memory locations that need setting up for the key ROM routines to work. Apple's ///Se.rvice Reference Manual (p. 13.57) has a list of Monitor commands.
Anderson's The Apple Nobody Knows also has good Monitor command info.
To obtain a binary dump of the /1/ ROM you can do the following:
Initialize a disk on either the /// or an Apple ][ computer. Insert the new disk in the f/I. Start the /// and hold down the Open Apple and Control keys. You should be In the /// Monitor. Type 0<F000.FFFW to write the ROM to disk blocks O to 7 Use a disk block reader on the /1/ or the ] [to read the ROM blocks and save them to a real file.
This disk writing is needed since the ROM does not provide a command for redirecting screen output to the f/f's serial port. But, I've read that you can output the ROM contents to the ///'s serial port but this involves using the Monitor to write a small program. If anyone has such a program please send a copy my way.
7 A FEW COMMENTS
I find it interesting, at least from a software engineering perspective, to note that in my opinion the /1/ ROM is missing several key features which I thought any system ROM would need. The ROM is missing two features which I think would have been useful to Apple and outside ¡/1 programmers:
i) The ROM does not have an explicit version number which exists at a specific ROM address. This version number could be used to validate the ROM in case there were several different ROMs (as there were). Apple uses a pseudo ROM version number (called the revision number) during the loading of SOS but this is somewhat lame In
my opinion.
The ROM does not have a dispatch routine for use by the OS or applications that want to use ROM routines. This dispatch routine would reside at a specific address (e.g., F000) and it would take as input a command number and a set of parameters. These parameters could be passed via registers or on the stack. This routine would allow Apple to change the ROM and ROM "users" would not need to change their programming as long as they used the selector routine. The Apple ][ ROM did not have such a routine which caused Apple many headaches when it wanted to change the Apple ][ ROM and had to keep lots of routines in their same place.
The ROM source code is rather sparse concerning comments. It would be nice if the ROM contained detailed information about what each routine did and how to call the routines. Obviously, Apple did not expect anyone but Apple's own programmers to ever see the ROM source or use the ROM routines. (I've seen the Lisa computer's ROM listing which is much better documented than the ///'s and both are comparable in terms of age).
Inside the Apple /// Computer ROM David T Craig 04 Dec 1997 5 / 6
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8 REFERENCES
Apple /// ROM Listing - Reviion O This can be found in the Apple /1/ patent (#4,383,296) dated May 1983. Note that in places this ROM listing is not always readable.
Apple /// ROM Listing - Revision f
I have a very readable listing of the revision I ROM that was printed on a laser printer.
Apple /// Service Reference Manual (Level 2)
This almost 500 page document by Apple has everything you would want to know about the f/I's hardware, low-level software, and how to service a broken /1/. Includes descriptions of the System Monitor (a.k.a. Development Monitor) [page
17.3] and the built-in RAM test routine [page 13.51].
Apple /// L5t?S Bootstrap Loader Listing
Shows how 512 bytes of code are used to load SOS from disk into the f/f's memory.
The following articles provide good ROM information:
Apple///A'ntry Points; Andy Wells, Call-APPLE, October 1981
Apple///Dabbith& Rick Smith, Apple Orchard, Summer 1981
,7/ Bits: John Jeppsons Cuided Tour of Ihghway/// John Jeppson, Softalk, May 1983
The Apple Nobody Knows; Alan Anderson, Apple Orchard, Fall 1981
Unlocking the Apple /// - Part Alan Anderson, Apple Orchard, September 1982
Apple /// 12- Volt 128K Internal Diagnostics; Apple Technical Information Library
9 DOCUMENT MODIFICATION HISTORY
30 Nov 1997
Created this document.
04 Dec 1997
Corrected a few problems, extended the Reference section to include more /1/ articles pertaining to the I/f ROM, added this
section, added section MONITOR COMMANDS.
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g
Apple III Computer Information
., /1,.
t
k.
Inside the Apple III ROM
Revision I
30 Nov 1997
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Inside the Apple ¡II Computer ROM
David T. Craig 30 November 1997 71533. 606@compuserve. corn
TABLE OF CONTENTS
i
INTRODUCTION
2 ROM SECTIONS
3
IMPORTANT ROM ROUTINES
4
ROM TABLES
5 ROM USAGE BY SOS
6 A FEW COMMENTS
7
REFERENCES
I INTRODUCTION This document provides a general overview of the contents of the Apple /1/ computer ROM revision 1. This information should be used in conjunction with a copy of the ROM source code listing. The audience of this document is anyone with an interest in the technology of the Apple /1/ computer's hardware and software.
NOTE
There were two revisions of the Apple
I/I
ROM, revision O and
revision 1. Revision O ROMs had at address F1B9 the value 60.
Revision i ROMs had at address F1B9 the value AO.
This ROM contains 4 KB of 6502 programming and several data tables. The ROM occupies memory addresses F000-FFFF. The basic purpose of the ROM is to test
the Apple /1/ computer hardware and boot an operating system from the I/I's built-in floppy disk drive. The ROM also contains a simple Monitor program whose purpose is to allow the user to interact with the /1/ at the hexadecimal
level.
When the Apple /// computer is turned on the ROM's flow of execution is as
follows:
i) The ROM starts execution at the address contained in FFFC-FFFD (RESET)
which is address F4EE (DIAGN).
2) Diagnostics (DIAGN/F4EE) starts. The diagnostic first initializes some memory for the ROM'S use. If the Open Apple Key is held down then enter
the ROM Monitor. Otherwise run several diagnostic checks of the /1/ hardware (tests zero page, sizes memory, initializes screen text buffer,
Inside the Apple /1/ Computer ROM David T Craig 30 Nov 1997 1 / 4
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tests stack memory, tests ROM checksum, tests VIA chip, tests ACIA chip, tests A/D circuitry, tests keyboard connection). Any diagnostic failures display an error message and the user has to reset the computer.
3) Read block O (512 bytes) to address A000 from the floppy disk in the builtin disk drive (BOOT/F6AI). If no disk is found or block O cannot be read then display RETRY" and wait for the user to reset the computer. If the block is successfully read then execute the block contents (this is called the SOS Bootstrap Loader: see section ROM USAGE BY Sos).
2 ROM SECTIONS
Section Address Purpose Disk i/o F000-F4C4 Read and write floppy disk blocks (512 bytes each) Diagnostics F4C5-F7FE Diagnose the I/i hardware
Monitor F7FF-FFFF Interacts with user so user can do simple things
3 IMPORTANT ROM ROUTINES
BLOCKIO / F479 Reads or write a disk blocK (512 bytes), calls routine REGRWTS (F000) which reads a sector (256 bytes) from the disk
BOOT / F6A1 Read floppy disk block #0 into address A000, execute the block
ENTRY / F901 Monitor entry point
DIAGN / F4EE Diagnostic entry point
USRENTRY/F6E6 Tests RAM and displays a table showing chip failures (users may execute this routine from the Monitor)
4 ROM TABLES
Here's a list of the important data tables in the ROM. This list does not include disk 1/0 tables.
'rable Name / Address Contents
CI-IRSET / FEC5-FFB3 Default character set (overridden when SOS loads the character set from SOS. DRIVER)
Copyright / FFCO-FFEF Copyright message (contains the initials "JRH" for J. R. Huston who was a key player behind the /1/ and sos)
NMI / FFFA-FFFB
Jump address for the Non-Maskable Interrupt signal
RESET / FFFC-FFFD Jump address when the /// is powered on
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IRQ / FFFE-FFFF
Jump address for the Interrupt Request signal
5 ROM USAGE BY SOS
The Apple /1/ operating system (Sos) uses several ROM routines. These routines seem to all be related to disk block I/O. The following discussion is based on SOS version 1.3.
When the ROM loads block O from a SOS disk the ROM is loading the SOS Bootstrap Loader program. This program, which is at most 512 bytes in length, uses the ROM routine REGRWTS (F000) to read the SOS Loader into memory. This program does not test the ROM revision. It is interesting to note that ROM
routine BLOCKLO is not used, instead a lower-level routine (REGRWTS) is used.
The SOS Loader determines if the ROM is revision i by comparing address F1B9's contents against AO (reference: SOS source file SOSLDR.D.SRC). If this comparison fails then SOS displays on the screen the error "ROM ERROR: PLEASE NOTIFY YOUR DEALER." If the ROM revision is correct then the SOS loader uses the ROM'S disk I/o routines to read more of SOS into memory.
The disk /1/ driver that is built into SOS also uses the ROM to perform disk block I/O (reference: DISK3.SRC). It is interesting to note that when the disk driver is initialized the driver checks 1f the ROM revision Is O or 1. A revision of O is detected if address FIB9 contains 60. If neither revision is found then the disk driver returns an error to SOS (I don't think this will ever happen since the SOS loader has already determined that the ROM is revision i). For a valid ROM revision the disk driver sets up several Jump vectors which point to the
appropriate addresses in the ROM for the various ROM routines needed by the disk driver. Therefore, the disk driver seems compatible with either ROM revision whereas the SOS loader likes only revision 1.
6 A FEW COMMENTS
I find it interesting, at least from a software engineering perspective, that the ROM Is missing some key features which I thought any system ROM would need. The ROM is missing two features which I think would have been useful to Apple and outside ¡/1 programmers:
i) The ROM does not have an explicit version number which exists at a specific ROM address. This version number could be used to validate the ROM in case there were several different ROMs (as there were). Apple uses a pseudo ROM version number (called the revision number) during the loading of SOS but this is somewhat lame in my opinion.
2) The ROM does not have a selector routine for use by the OS or applications that want to use ROM routines. This selector would reside at a specific address (e.g., F000) and it would take as input a command number and a
set of parameters. These parameters could be passed via registers or on
the stack. This routine would allow Apple to change the ROM and ROM
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
"users" would not need to change their programming as long as they used the selector routine. The Apple J [ ROM did not have such a routine which caused Apple many headaches when lt wanted to change the Apple J [ ROM and had to keep lots of routines in their same place.
7 REFERENCES
Apple /// ROM Listing
I have a very nice listing of revision I ROM. A listing (that is somewhat readable) for the earlier revision O ROM may be found in the Apple I/I patent.
Apple /4' Service Reference Manual (Level )
This almost 500 page book by Apple has everything you would want to know about the ///'s hardware, low-level software, and how to service a broken ¡/1. Includes descriptions of the System Monitor (a.k.a. Development Monitor) [page 17.3] and the built-in RAM test routine [page 13.51].
Apple /// SOS Bootstrap Loader Listing
Shows how 512 bytes of code is used to load SOS from disk into the ill's memory.
Inside the Apple /// Computer ROM David T Craig 30 Nov 1997 4 / 4
Apple Computer Inc · 1982
Page 0691 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
I
Apple I/I Computer Technical Information
SOME COMMENTS ABOUT THE APPLE III COMPUTER BOOT ROM
David T Craig -- 27 February 2004
BACKGROU ND
The Apple / I / computer was introduced by Apple Computer in 1980 and was discontinued in 1985.
This computer was a microcomputer with orginally 128 KB of RAM memory expandable to 256 KB of RAM. It featured a 4 KB ROM (addressed from $F000 to $FFFF hexadecimal) which housed the initial programming that executed when the user turned on the computer. This ROM contained programming for the following functions:
+ diagnose hardware circuitry and memory + load and run a disk operating system (i.e. "boot") + provide an interface to a simple monitor program
The author wrote these comments after looking at the Apple I/I ROM listing as found in Apple Computers patent number 4,383,296 dated 10 May 1983. This analysis occured during a scanning of the Apple I/I patent.
ROM COMMENTS
The Apple III patent's ROM program Listing is terrible in terms of printed quality. Many parts are very faint and impossible to read. I assume this was done on purpose by Apple's legal department so that Apple's competitors would not be able to duplicate this ROM programming easily.
Some Comments about the Apple III Computer Boot ROM David T Craig -- 27 February 2004 -- i of 3
Apple Computer Inc · 1982
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The ROM programming does not seem to have been built for expansion. By this I mean the programming seems to have been written to just make it work and no tong term thought was given to the ROM programmings organization.
There were two versions of the ROM. The AppLe I / / operating system (OS) programming needed to differentiate between the ROM versions since the ROM contained several routines which the OS used. This version determination was not done in a logical way. A memory Location was chosen at random (at least it seems this way to me) to serve as the RONVs "version number". The OS had to test this "version numbe( when it needed to use specific ROM services.
The ROM version also determined the location of several ROM routines which the Apple I/I OS used.
The ROM's organization could have been improved greatly in my opinion if it was organized differently. At the beginning of the ROM address space (SF000) include a short header containing the following:
$F000 - ROM version number $F001 - ROM size (K bytes) SF002 - ROM checksum (2 bytes) SF003 - ROM routine dispatch jump vector (3 bytes) SF006 - ROM copyright notice (e.g. "(c) Apple Computer 1980")
The remainder of the ROM would have contained whatever programming and table data was needed.
The routine dispatch jump vector would be a standard jump instruction to a routine in the ROM whose purpose would be to let outside programs such as the operating system, device drivers, or even application programs access ROM routines in a ROM version independent manner. The dispatch routine would take as input a command number (in say the CPU's A register) and return result information in the CPUs X and Y registers. The A register on return would contain an error result with O meaning no error. Or, some fixed memory area could be use to handle ROM routine parameters. This dispatch mechanism could be seen as a BIOS (basic input output system).
Some Comments about the Apple I/I Computer Boot ROM David T Craig -- 27 February 2004 -- 2 of 3
Apple Computer Inc · 1982
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Possible dispatch routines could be:
+ Restart or Cold start or Warm start the computer + Read a block from a disk drive
* Write a block to a disk drive
Return size in blocks of a disk drive Checksum the ROM for diagnostic purposes + Test computers RAM memory for diagnostic purposes + Enter the Apple I/I Monitor program
This dispatch mechanism would have simplified the Apple I/I OS use of the ROM services since the ROM would always be accessed from just one address ($F003). If the OS requested a ROM service which was unavailable (e.g. an old ROM was installed) then the ROM would tell the OS that the service did not exist via a dispatch error result.
CONCLUSION
Hopefully this little commentary provides some useful information to its reader. If you are interested in the Apple I/f computer you should see its patents (one is for the Apple I/I, the other is for the Apple I/I Plus). The first patent contains the full ROM listing, but the author has a real digital copy which is much more readable.
Enjoy.
Some Comments about the Apple I/I Computer Boot ROM David T Craig -- 27 February 2004 -- 3 of 3
Apple Computer Inc · 1982
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i Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple I/I Computer Inormahon
APPLE 1/!
SOS BOOTSTRAP
LOADER SOURCE
ADDED BY DAVID T CRAIG 2006
Apple Computer Inc · 1982
Page 0695 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
a :::
IR
Apple f/i
Apple ///+
Apple /1/ sos Technical Information
SOS 1.3 Floppy Bootstrap Loader
Source Code Listing
This listing shows the code which is found at the beginning of a SOS boot disk. When the Apple I/I computer starts the computer's ROM loads this code from the floppy disk and executes the code. This code loads the Apple Ill's operating system, SOS.
Apple Computer Inc · 1982
Page 0696 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
OQQ0000000000000000000
'r-4
Cl) I_4
oo
Q
o
J
©j
0000000000000000000000
rç
o
[TI r
o
Apple Computer Inc · 1982
Page 0697 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
10/31/89 9:45
0000 0000 0000 0000 0000 0000 0000 0000
A000 A000 A000 A000 A000 A000 A000 A000 A000 A000
A000 A000 Aø0ø A000 A000 A000 A000 A000
A000 A0ø0 A000 A00ø A000 A000 A000 A000 A000 A000 A000 A000
A0ø0 A000
A000
A000
A000 A000 A000 A000
A000 A000 A0ø0 A000 Aøø0 A000 A000 A000 A000 A000 A000 A001 A002 A004 A007
A007
A00 7
A007
A00 9
AØØA
AØØD AØ0F
Aol 2
AOl 4
AOl 7
AOl 9
AØ1C
Aol F
A022 A024 A024
A024 A024 A024 A024
A02 6
A028 AØ2A
A02 C
A02 E
A030
A03 2
A03 4
O36
0082
0083 0084
0085 0087 00E3 00E5 00E7 00E8
0628 C010 C040
0040
0000
0000 1EOO 1EOB 2000 A 200
F000
F4AØ FFCA FFDF FFEF
78 D8 A9 77 8D DFFF
A2 FF SA 2C lOCO AS 40 BD CAFF AS 07 BD EFFF AS 00 CE EFFF 80 0020 AE 0020 OØF5
AS 00
85 85 A2 A2
86 86
A2 02
M 85
84 E3 A4 86 84 El
20 bAl
HD:Apple i/:SOS Floppy Bootstrap Loader
g APPLE I/I BOOTSTRAP LOADER FOR FLOPPY DISK
;úg-gDIigsgasdse*mgbgleÍddlg0d-Mgadrcgh-g1g98I8db Scúo*tgt gSgtigngsodndggdgdedgggddggg
ABSOLUTE PROC BOOT STRAPLOADER ORG 0A000
EQUATES
Page 1
ZERO PAGE LOCATIONS
IBDRVN
.EQU
82
IBTRX
EQU
83
IBSECT
.EQU
84
IBBUFP
.EQU
85
IBCMD
.EQU
87
IBBUFPTMP .EQU
0E3
FILECNT
.EQU
0ES
INDXBLKCNT .EQIJ
0E7
SOSJMPADR .EQU 0E8
DRIVE NUMBER TRACK NUMBER SECTOR NUMBER BUFFER POINTER COMMAND NUMBER BUFFER POINTER TEMPORARY FILE COUNT
INDEX BLOCK COUNT SOS JUMP ADDRESS
HARDWARE I/O ADDRESSES
SCREENLOC .EQU
KBDSTROBE .EQLJ
IOBEEP
.EQU
0628 ØCØ1Ø ØCØ4Ø
GENERAL EQUATES
SCREEN LOCATION KEYBOARD STROBE ; I/O BEEP
RETINT IDXBLK1 IOXBLK2 LOADADR OFFSET FIRSTPAGE MAINBUFF
SECTABL NMIVECTOR EREG
[REBGRRAGWTS
.510(1
.EQU
EQU
.EQU
EQU EQU
.EQU
EQU
.EQU
EQU
.EQU
EQU
ENTRY POINT
40 0000 ØDØØ SEØØ ÌEØ8 2000 0A200 ØFØØØ ØF4AØ ØFFCA ØFFDF 0FFEF
RETURN FROM INTERRUPT
;
INDEX BLOCK i
;
INDEX BLOCK 2
;
LOADING ADDRESS
;
OFFSET
;
; FIRST PAGE MAIN BUFFER
¡
READ/WRITE SECTOR ROUTINE
¡
SECTOR TABLE
;
NON-MASKABLE INTERRUPT VECTOR
¡
ENVIRONMENT REGISTER
; BANK REGISTER
ENTRY $010
SEI CLD LDA STA
#77 EREG
¡ SET INTERRUPT DISABLE ; CLEAR DECIMAL FLAG ; LDAD ACCUMULATOR WITH $77
STORE IN ENVIRONMENT REGISTER
;
SET 2 MHZ, I/O SPACE ENABLED, SCREEN ENABLED,
RESET ENABLED, WRITE PROTECT NOT ENABLED,
PRIMARY STACK, AND RDM SELECTED
LDX
#ØFF
TXS
; LDAD ACCUMULATOR WITH $FF TRANSFER X-REGISTER TO STACK POINTER
BIT
KBOSTROBE
CLEAR KEYBOARD
LOA
#RETINT
LOAD ACCUMULATOR WITH RETURN FROM INTERRUPT
;
STA
NMIVECTOR
STORE IN NON-MASKABLE INTERRUPT VECTOR
¡
LDA
#07
¡ LOAD ACCUMULATOR WITH $07
STA
BREG
STORE IN BANK REGISTER
;
LDA
#00
LOAD ACCUMULATOR WITH $00
¡
DEC
BREG
DECREMENT BANK REGISTER
;
STA
FIRSTPAGE
STORE IN FIRST PAGE OF BANK
LOX
FIRSTPAGE ; LOAD X-HEGISTER WITH FIRST PAGE BYTE
BNE
$010
BRANCH IF BYTE IS NOT EQUAL TO $00
This section reads in the SOS directory.
READSOSDIR LOA
#00
¡ LOAD ACCUMULATOR WITH $00-BLOCK HIGH BYTE
STA
IBBUFU
¡ STORE IN BUFFER POINTER LOW BYTE
LOX
#0A2
¡ LOAD X-REGISTER WITH $A2
STX
IBBUFP-fl
¡ STORE IN BUFFER POINTER HIGH BYTE
LOX
#02
¡ LOAD X-REGISTER WITH $02-BLOCK LOW BYTE
RDSOSDIRLP LDY
IBBUFF
LOAD Y-REGISTER WITH BUFFER POINTER LDW BYTE
STY
TBBUFPTMP
; STORE IN BUFFER POINTER TEMPORARY LOW BYTE
LDY
IBBUFP+1
LOAD Y-REGISTER WITH BUFFER POINTER HIGH BYTE
STY
IBBUFPTMP1 STORE IN BUFFER POINTER TEMPORARY HIGH BYTE
JSR
READBLK
JUMP TO READ A BLOCK FROM FLOPPY DISK DRIVE
i
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
I-
10/3 1/9 9:45
A039
AO3B
A03 D
A03 D A03E A03F A041 A041
A043 A043 A045 A04 5 A04 7 A04 7 A04 7 A04 7 A04 7 A04 7 A04 7
A04 A A04C AØ4F A051
A053 A055 A058 A058
AO5A AØ5C A05 E 11060 A062 A064 11066 11068 AØ6B AO6C 1106E 11070 11070 A072 11074 11077 11079
AO 711 1107C
1107F 11081 A082 11081 11086 11086 11088 AØ8A
1108 C AØ8D
A08 E AO 90 11091 A093 11096 A098 AØ9A 1109 C AØ9E
110110
110112
110111
110116
110119
A0AA AØAC
110110
AOAF
AØB1
AØB 3
A0B 5 11087
A0B 9 A0BB AOBE AØBE A0BE AØBE AØBE
10BE
ABBE AØCO
AØC 2 10C3
AO 02
Bi E3
AA CB
Bi E3
DOER
E0 00
DØE7
AD 25112
85 55
AD 26A2 85 E6 05 E5 D003 4C 56111
A5 55 0002 06 E6 06 E5 A9 2B 85 85 A9 A2 85 86 AR 24A2
CA
110 00
Bl 85
F0111
29 OF
CD 92111
0013
118
Bl 85
D9 92A1
DØOB 88 DØF6
111 85
29 F0 C9 20 F032 08
CA
F010
18
AS 85 60 23A2 85 85 A5 86 69 00 85 86 0009 119 04 85 85 E6 86
11E 24A2 28 FØCØ 38 115 ES
59 01 85 E5 A5 E6 E9 00 85 E6
BØB1
IC 56111
AØ 11
Bl 85
AA
HD:Apple ///:SOS Floppy Bootstrap Loader
Page 2
LDY
#02
LOAD Y-REGISTER WITH $02
LOA
@IBBUFPTMP,Y LOAD ACCUMULATOR WITH NEXT BLOCK TO READ LOW
BYTE
TAX
TRANSFER ACCUMULATOR TO X-REGISTER
INY
INCREMENT Y-REGISTER
LDA
@IBBUFPTMP,Y LOAD ACCUMULATOR WITH NEXT BLOCK TO READ HIGH
BYTE
BNE
RDSOSDIRLP
BRANCH IF NEXT BLOCK TO READ HIGH BYTE IS NOT
EQUAL TO ZERO
CPX
#00
CHECK TO SEE IF NEXT BLOCK TO READ LOW BYTE IS
ZERO
BNE
RDSOSDTRLP
BRANCH IF NEXT BLOCK TO READ LOW BYTE IS NOT
EQUAL TO ZERO
This section searches the SOS directory for the SOS.KERNEL file.
SRCHSOSKER LDA STA
LDA STA
ORA REE JMP
$010
LDA
BNE
DEC
$020
DEC
LDA
STA
LOA
STA
LDX
DEX
SRCHLP
LDY
LDA
$010
BEQ AND CMP BNE TAY LDA CMP BNE DEY RNE LDA
AND
CMP
BEQ
$020
PUP
DEX
REQ
CLC
LDA
ADO
STA
LDA
ADC
STA
BNE
$030
LDA
STA INC
LDX
$040
PLU
REQ
SEC
LOA
SBC
STA
LDA
SBC
STA
ROS
JMP
MAINBUFF+25 FILECNT MAINBUFF+2$ FILECNT+1 FILECNT
$010
WRNTFNDERR
FILECNT
$020 FILECNT+1
FILECNT #2B IBBUFP #0A2 IBBUFP+1 MAINBUFF+24
#00
@IBBUFP,Y
$020 #0F
FLNMELEN
$020
@IBBUFP,Y FLNME-1,Y
$020
$030
@IBBUFP,Y
#0F0 #20
READIDXBLK
$030
IBBUFP MAINBUFF+23 IBBUFP IBBUFP+1
#00
IRBUFP+1
$040 #04
IBBOFP IBBOFP+1 MAINBUFF+24
SRCHLP
FILECNT #01 FILECNT FILECNT+1 #00 FILECNT+1 SRCHLP WRNTFNDERR
LOAD ACCUMULATOR WITH FILE COUNT LOW BYTE STORE IN FILE COUNT LOW BYTE
LOAD ACCUMULATOR WITH FILE COUNT HIGH BYTE STORE IN FILE COUNT HIGH BYTE OR ACCUMULATOR WITH FILE COUNT LOW BYTE BRANCH IF FILE COUNT IS NOT EQUAL TO ZERO JUMP TO WRITE NOT FOUND ERROR MESSAGE TO
SCREEN
LOAD ACCUMULATOR WITH FILE COUNT LOW BYTE BRANCH IF NOT EQUAL TO $00 DECREMENT FILE COUNT HIGH BYTE
DECREMENT FILE COUNT LOW BYTE LOAD ACCUMULATOR WITH $28 STORE IN BUFFER POINTER LOW BYTE
LOAD ACCUMULATOR WITH $112 STORE IN BUFFER POINTER HIGH BYTE LOAD X-REGISTER WITH ENTRIES PER BLOCK DECREMENT X-REGISTER LOAD Y-REGISTER WITH $00 LOAD ACCUMULATOR WITH STORAGE TYPE AND NAME
LENGTH BYTE BRANCH IF EQUAL TO ZERO
MASK OFF BITS 4,5,6,7
COMPARE WITH FILE NAME LENGTH BRANCH IF NOT EQUAL TO ZERO TRANSFER NAME LENGTH TO Y-REG ISTER LOAD ACCUMULATOR WITH FILE NAME BYTE COMPARE WITH FILE NAME BYTE BRANCH IF NOT EQUAL
; DECREMENT NANE LENGTH BRANCH IF NAME LENGTH NOT EQUAL TO ZERO LOAD ACCUMULATOR WITH STORAGE TYPE AND NAME
LENGTH BYTE
MASK OFF BITS 0,1,2,3 COMPARE WITH $20 FOR SAPLING FILE
BRANCH IF EQUAL TO READ INDEX BLOCK ; POSH PROCESSOR STATUS ON STACK
DECREMENT ENTRIES PER BLOCK ; BRANCH IF ENTRIES PER BLOCK IS EQUAL TO ZERO
CLEAR CARRY
; LOAD ACCUMULATOR WITH BUFFER POINTER LOW BYTE
ADD ENTRY LENGTH LOW BYTE STORE IN BUFFER POINTER LOW BYTE LOAD ACCUMULATOR WITH BUFFER POINTER HIGH BYTE ADD $00 ; SPORE IN BUFFER POINTER HIGH BYTE BRANCH ALWAYS
LOAD ACCUMULATOR WITH $04 STORE IN BUFFER POINTER LOW BYTE INCREMENT BUFFER POINTER HIGH BYTE LOAD X-REGISTER WITH ENTRIES PER BLOCK PULL PROCESSOR STATUS FROM STACK BRANCH IF NOT EQUAL TO ZERO
SET CARRY
LOAD ACCUMULATOR WITH FILE COUNT LOW BYTE
SUBTRACT $01 STORE IN FILE COUNT LOW BYTE LOAD ACCUMULATOR WITH FILE COUNT HIGH BYTE
SUBTRACT $00 STORE IN FILE COUNT HIGH BYTE BRANCH IF MORE FILE ENTRIES ; JUMP TO WRITE NOT FOUND ERROR MESSAGE TO SCREEN
This section reads in the index block of the SOS.KERNEL file.
READIDXBLK LDY
#11
LOAD Y-REGISTER WITH $11
LOA
@IBBUFP,Y
; LOAD KEY POINTER LOW BYTE
TAX
TRANSFER ACCUMULATOR TO X-REGISTER-BLOCK LOW
BYTE
1
Apple Computer Inc · 1982
Page 0699 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
'10/31/89 9:45
A0C3 AØC4
ABC 6
AØC8 AØCA AØCC AØCE ABD1 ABD1
ABO i
AØD i
AØD i
AØD i
AØD4
AØD 7
AØD 9
AØDB AØDD
ARDE'
A0E2 AØE2 AØE2
AØE 2
ABE 2
AØE 2
AØE 2
AØE 2
AØE 4
ABE 7
AØEA AØEC AØEF AØEF AØFØ
AØF 2
AØF 2
AØF 2
AØF 2
ABF 2
A0F2 AØF2
ABF i ABF 6
ABF B
AØFB AØFE
Al 00
A102 A102 Aloi Al07 Al09
AbB Abs AbB
Al OB
A1BB
Al OB
Al ØB
A1ØC
A 10E
All i
A113 A115 Alls AllA A11D A11D A11D Allo Allo A11D Allo Allo
Al 1F
Al20 Al22 Al23 Al25 Al26 Al28 Al29 Al29 Al2B Al2C Al2F A13l A133 A135 A137
C8 Bi 85 AO 00 84 85 A0 OC 84 86 20 111A1
AE 000C AD 0000 AO 00 84 85 AO lE 84 86 20 1OA1
A0 08 B9 FF1D D9 BCA1 F003 40 6AA1
88 DØE'2
A9 01 85 E7 A4 E7 5E 0000 B9 0000 0004 EØ 00
F007 20 1DA1 E6 E7 DØEB
18
AB 0E 60 081E 85 E8 A9 lE 60 091E 85 E9 6C E800
86 83 4A 66 83 4A 66 83 4A 66 83 BA
29 07 AA BD AØF4 85 84 A9 01 85 87 A9 OB 85 82
HD:Apple ///:SOS Floppy Bootstrap Loader
Page 3
INY
INCREMENT YREGISTER
LOA
@IBBUFP,Y
LOAD KEY POINTER HIGH BYTE
LDY
#00
LOAD YREGISTER WITH $00
STY
IBBUFP
STORE IN BUFFER POINTER LOW BYTE
LDY
#ØC
; LOAD YREGISTER WITH $ØC
STY
IBBUFP+i
STORE IN BUFFER POINTER HIGH BYTE
JSR
READBLK
JUMP TO READ A BLOCK FROM FLOPPY DISK DRIVE
This section reads in the first block of the SOS.KERNEL file.
RD1SOSKER LOX LDA LDY STY LDY STY JSR
IDXBLK1 IDXBLK2 #00 IBBUFP #1E IBBUFP+i PEADBLK
LOAD XRESISTER WITH INDEX BLOCK LOW BYTE LOAD ACCUMULATOR WITH INDEX BLOCK HIGH BYTE LOAD YREGISTER WITH $00 STORE IN BUFFER POINTER LOW BYTE LOAD YREGISTER WITH $1E
STORE IN BUFFER POINTER HIGH BYTE JUMP TO READ A BLOCK FROM FLOPPY DISK DRIVE
This section does a verification of the SDS.KERNEL file to make sure it is the proper SOS.KERNEL file. It checks for "SOS KRNL" in the first 8 bytes of the file.
FLVRFY
LDY
FLVRFYLP LDA
CM?
BEQ
JMP
$010
DEY
BNE
#08
LOAD YREGISTER WITH $08
LDADADRi,Y LOAD ACCUMULATOR WITH BYTE FROM SOS.KERNEL
FLVERIFYi,Y COMPARE WITH VERIFICATION BYTE
$010
BRANCH IF EQUAL
BRINKEHERE ; JUMP TO WRITE INVALID KERNEL ERROR MESSAGE TO SCREEN
DECREMENT YREGISTER
FLVRFYLP
BRANCH IF NOT EQUAL TO ZERO TO CHECK REST OF 8
SOS.KERNEL BYTES
This section reads In the SOS.KERNEL file.
RDSOSKER LOA STA
RDSOSKELP toy LOX LOA BNE CPX
BEQ
$010
JSR
INC
BNE
#01 INDXBLKCNT INDXBLKCNT IDXBLK1,Y IDXHLK2,Y $010 #00
JUMPSOSKER READHLK INDXBLKCNT RDSOSKELP
LOAD ACCUMULATDR WITH $01 ; STORE IN INDEX BLOCK COUNT
LOAD YREGISTER WITH INDEX BLOCK COUNT LOAD XREGISTER WITH BLOCK LOW BYTE LOAD ACCUMULATOR WITH BLOCK HIGH BYTE BRANCH IF BLOCK HIGH BYTE IS NOT EQUAL TO ZERO
;
CHECK TO SEE IF BLOCK LOW BYTE IS NOT EQUAL TO ZERO
; BRANCH IF BLOCK LOW BYTE IS NOT EQUAL TO ZERO ; JUMP TO READ A BLOCK FROM FLOPPY DISK DRIVE
INCREMENT INDEX BLOCK COUNT BRANCH IF INDEX BLOCK COUNT IS NOT EQUAL TO ZERO TO READ MORE OF THE SOS.KERNEL
This section jumps to the SOS.KERNEL loader.
JUMPSOSKER CLC LOA AOC STA LOA ADC STA JMP
#05 OFFSET SOSJMPADR #1E
OFFSET-4-1
SOSJMPADR+1 @SOSJMPADR
CLEAR CARRY LOAD ACCUMULATOR WITH $ØE ADD OFFSET LOW BYTE STORE IN SOS JUMP ADDRESS LOW BYTE
LOAD ACCUMULATOR WITH $1E ; ADO OFFSET HIGH BYTE
STORE IN SOS JUMP ADDRESS HIGH BYTE JUMP TO SOS.KERHEL LOADER
This section reads a block of data from the floppy disk drive. On entry the x-register contains the block low byte and the accumulator contains the block high byte.
READBLK
STX
IBTRK
STORE BLOCK LOW BYTE IN TRACK NUMBER
LSR
A
DIVIDE BLOCK BY 8 TO GET TRACK NUMBER
ROR
IBTRK
LSR
A
ROR
IBTRK
LSR
A
ROR
IBTRK
TXA
; TRANSFER XREGISTER WHICH CONTAINS THE BLOCK
LOW BYTE TO ACCUMULATOR
AND
#07
MASK OFF BITS 3,4,5,6,7
TAX
TRANSFER ACCUMULATOR TO XREGISTER
LOA
SECTABL,X
LOAD ACCUMULATOR WITH PROPER SECTOR TO READ
STA
IBSECT
STORE IN SECTOR NUMBER
LOA
#01
LOAD ACCUMULATOR WITH $01
STA
IBCMD
STORE IN COMMAND NUMBER
LOA
#00
LOAD ACCUMULATOR WITH $00
STA
IBDRVH
STORE IN DRIVE NUMBER
J
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
10/31/89 9:45
HD:Apple i/:SOS Floppy Bootstrap Loader
Page 4'
A139 AL3C A13E A140
Al4 1
A143 A145 A147
A14 9
A14C A14E A150 Al51 A153 A155 A156 Al56 A156 A156 Al56 A156 Al58
Al LA
A15D A15D
Al 60
Al 61
Al 62
Al 64
Al 67
Al 6A Al 6A
Al 6A Al 6A
Al 6A
Al 6A
Al 6C
Al 6E
A171 A171 A174 A175 A176 A178 A17B A17E A17E A17E A17E A17E A17E AlS0 A182 Al85 Al88 A189
Al SA
A18C A18F
Al 92
Al 92
Al 92
Al 92
Al 92
Al 92
A193 A19A A190
A 1A4
A1A5
A lAC
A1B3 ALBA A1CØ A1C7
Al CE
A1D3 AlDA A1DD ALDD
20 ØØFØ 9005 A2 FF SA 003B 56 86 E6 84 E6 84 20 ØØFØ 9005 A2 FF 9A
B02 B
E6 86 60
rea
kt
A2 lB AO 21 BD MAI
99 2806
88
CA
DOF 6
AD 4000 IC SiAl
A2 13 A0 lO BD REAl
99 2806
88
CA DØF6 AD 1000 IC 7BA1
A2 ØA A0 18 BD 02A1 99 2806
88 CA DOF6 AD 4000 4C 8FA1
ØA 53 4F 53 2E 4B 45 52 4E 45 4C 53 4F 53 20 IB 52 4E 4C 46 49 4C 45 20 27 53 4F 53 2E 4B 45 52 4E 45 IC 27 20 4E 4F 54 20 46 4F 55 4E 44 49 4E 56 41 IC 49 44 20 4B 45 52 4E 45 4C 20 46 49 4C 45 44 49 53 40 20 45 52 52 4F 52
søiø
$020
JSP.
OEGRWTS
BCC
$010
LOX
80FF
TXS
BCS
WRDLSKERR
INC
IBBUFP+1
INC
IBSECT
INC
IBSECT
JSR
REGRWTS
BCC
$020
LOX
80FF
TXS
BCS
WRDISKERR
INC
IBBUFP+l
RTS
JUMP TO READ A SECTOR FROM FLOPPY DISK BRANCH IF NO DISK ERRORS OCCORED LOAD ACCUMULATOR WITH $FF TRANSFER X-REGISTER TO STACK POINTER BRANCH TO WRITE DISK ERROR MESSAGE TO SCREEN INCREMENT BUFFER POINTER HIGH BYTE INCREMENT SECTOR NUMBER INCREMENT SECTOR NUMBER JUMP TO READ A SECTOR FROM FLOPPY DISK BRANCH IF NO DISK ERRORS OCCURED LOAD ACCUMULATOR WITH $FF TRANSFER X-REGISTRE TO STACK POINTER BRANCH TO WRITE DISK ERROR MESSAGE TO SCREEN INCREMENT BUFFER POINTER HIGH BYTE RETURN TO CALLER
This section writes the not found error message to the screen.
WRNTFNOERR LOX
LDY
$010
LDA
STA
DEY
DEX
ONE
LDA
$020
JMP
#10
; LOAD X-REGISTER WITH $LB
#21
; LOAD Y-REGISTER WITH $21
NTFNDERR-1,X ; LOAD ACCUMULATOR WITH NOT FOUND ERROR MESSAGE
BYTE
SCREENLOC,Y ; WRITE IT TO THE SCREEN
DECREMENT Y-REGISTER
DECREMENT X-REGISTER
$010
; BRANCH IF MORE CHARACTERS TO WRITE ON SCREEN
IOBEEP
BEEP SPEEKER
$020
; HANG FOREVER
This section writes the invalid kernel error message to the screen.
WRINKERERR LOX
LDY
$010
IDA
$020
STA
DEY DEX BNE LOA JMP
#13
; LOAD X-REGISTER WITH $13
#10
LOAD Y-REGISTER WITH $10
INVKEERR-1,X LOAD ACCUMULATOR WITH INVALID KERNEL ERROR
¡ MESSAGE BYTE
SCPEENLOC,Y ¡ WRITE IT TO THE SCREEN
¡ DECREMENT Y-REGISTER DECREMENT X-REGISTER
$010 IOBEEP $020
BRANCH IF MORE CHARACTERS TO WRITE ON SCREEN
¡
BEEP SPEEKER
;
HAND FOREVER
;
This section writes the disk error message to the screen.
WRDISKERR LOX
LDY
$010
LOA
STA
DEY
DEX
BNE
LDA
$020
JMP
#0A #18 DISKERR-1,X SCREENLOC,Y
$010 IOBEEP $020
¡ LOAD K-REGISTER WITH $ØA ¡ LOAD Y-PEGISTER WITH $18
LOAD ACCUMULATOR WITH DISK ERROR MESSAGE BYTE WRITE IT TO THE SCREEN DECREMENT Y-REGISTER DECREMENT X-REGISTER BRANCH IF MORE CHARACTERS TO WRITE ON SCREEN BEEP SPEEKER HANG FOREVER
STORAGE FOR THE ERROR MESSAGE AND FILE VERIFICATION ROUTINES
FLNMELEN FLNME
FLVERIFY
NTFNDERR
.BYTE ØA .ASCII "SOS.KERNEL"
.ASCII "SOS KRNL"
.ASCII "FILE 'SOS.KERNEL' NOT FOUND"
INVKEERR .ASCII "INVALID KERNEL FILE" DISKERR .ASCII "DISK ERROR"
.END
SYMBOL TABLE DUMP
AB - Absolute RF - Ref PB - Public
LB - Label DF - Def PV - Private
UD - Undefined PR - Proc CS - Consta
MC - Macro FC - Func
BOOTSTRA PR ---- BREG I
AB FFEF OISKERR LB A1D3 ENTRY
I
I
LB A000 EREG I
Apple Computer Inc · 1982
AB FFDF
I
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
10/31/89 9:45
HD:Apple iI:SOS Floppy Bootstrap Loader
FILECNT AB 00ES FLVRFY LB A0E2 IBDRVN AB 0082 INDXBLKC AB 00E7 LOADADR AB 1EØ0 RD1SOSKE LB AØD1 READIDXB LB ABBE SECTABL AB F4AØ WRINKERE LB A16A
FIRSTPAG AB 2000 FLVRFYLP LB AØE4 INSECT AB 0084 INVREERR LB A1C0 MAINBUFF AB A200 RDSOSDIR LB AØ2E READSOSD LB A024 SOSJMPAD AB 00E8 WRNTFNDE LB A156
FLNME LB A193 IBBUFP AB 0085 IBTRK AB 0083 IOBEEP AB C040 NMIVECTO AB FFCA RDSOSKEL LB AØF6 REGRNTS AB F000 SRCHLP LB AØ6C
FLNMELEN LB A192 IBBUFPTM AB 00E3 IDXBLK1 AB 0000 JUMPSOSK LB A10B NTFNDERR LB A1A5 RDSOSKER LB A0F2 RETINT AB 0040 SRCHSOSK LB A047
FLVERIFY LB A19D IBCMD AB 0087 IDXBLK2 AB 0D00 KBDSTROB AB C010 OFFSET AB 1E08 READBLX LB A11D SCREENLO AB 0628 WRDISKER LB A17E
Assembly complete:
363 lines
0 Errors flagged on this Assembly
6502 DPCODE STATIC FREQUENCIES
ABC AND NCC BCS BEQ BIT NNE CLC CLD CMP : CUE DEC DEE DEY INC INY JMP JSR LDA LDX bOY LSR ORA PEP PLP ROR RTS SRC SEC
SEI STA STX STY TAX TAY TXA TXS
4
I
3
2
I
3
I
1m 6
I
15 I
1m 2
I
4 2
3
5
5
****
**
*
2 7
37 M 12 14
31111mmm 1m 3
I
1m 2 I
1m
23 I 2 6 I 1m 3 I 1m 3 I
**** ************ ** ******************* **************
* * *
*
**
* *
**
* *
Minimum frequency = 1
Maximum frequency
37
Average frequency = 5
Unused opcodes:
ASL BMI BPL BRK BVC BVS CLI CLV CUY EOR INX NOP PEA PLA ROL RTI SEO TSX TYA
Program opcode usage: 66 %
(1.00) That's all, Folks
Page 5
I
Apple Computer Inc · 1982
Page 0702 of 0730
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
5eem'
I Apple III Computer Information
APPLE Ill SOS BOOTSTRAP LOADER
HEXADECIMAL DUMP
Source DISK1 .dofile as found with Chris Smolinskis Macintosh SARA emulator application
Printed by David T. Craig December 1997
This hex dump, which was produced by the Apple Macintosh MPW DumpFile tool, lists the Apple I/I SOS Bootstrap Loader. This 512 byte loader exists at block O of SOS disks and is loaded by the Apple I/I ROM into memory addresses $A000-$A1FF. This code's purpose is to begin the loading of SOS from the floppy disk into the I//s memory.
O: 4C 6E AO 53 4F 53 20 42 4F 4F 54 20 20 31 2E 31 LntSOS.BOOT. .1.1
10: 20 OA 53 4F 53 2E 4E 45 52 4E 45 4C 20 20 20 20 . .SOS.KERNEL.
20: 20 53 4F 53 20 4B 52 4E 4C 49 2F 4F 20 45 52 52 .SOS.KRNLI/O.ERR
30: 4F 52 08 00 46 49 4C 45 20 27 53 4F 53 2E 4B 45 OR. .FILE. 'SOS.KE
40: 52 4E 45 4C 27 20 4E 4F 54 20 46 4F 55 4E 44 25 RNEL'.NOT.FOUND%
50: 00 49 4E 56 41 4C 49 44 20 4E 45 52 4E 45 4C 20 .INVALID.KERNEL.
60: 46 49 4C 45 3A 00 oo oc oo lE 0E lE 04 A4 78 08 FILE 70: A9 77 8D DF FF A2 FE 9A 2C 10 CO A9 40 8D CA FF ©wçfF'ö, .©@ç
80: A9 07 8D EF FF A2 00 CE EF FF 8E 00 20 AD 00 20 C.çÔ.Ô"é. ...
90: DO F5 A9 01 85 EO A9 00 85 El A9 00 85 85 A9 A2 -i©.Ö4©.Ö©.ÖÖ©
AO: 85 86 20 BE Al E6 EQ A9 00 85 E6 E6 86 E6 86 E6 ÖÜ.°Êt©.ÖÊÊÜÊÜÊ
BO: E6 20 BE Al AO 02 Bl 85 85 EO C8 Bl 85 85 El DO Ê.°t.±ÖÖt»±ÖÖ
CO: EA A5 EO DO E6 AD 6C AO 85 E2 AD 6D AO 85 E3 18 ±.1-ÊltÖ,mtÖ,,.
DO: A5 E3 69 02 85 E5 38 AS E2 ED 23 A4 85 E4 A5 E5 ,,i.ÖÂ8.,±#Öo.Â
EO: E9 00 85 E5 AO 00 Bl E2 29 0F CD 11 AO DO 21 A8 È.ÖAt.±,).O.t-!®
FO: Bl E2 09 11 AO DO 19 88 DO F6 AO 00 El E2 29 FO ±,Y.t-.à-"t.±,)I
100: 53 4F 53 20 4B 52 4E 4C 62 00 01 00 0E 2E 44 31 SOS.KENLb
Dl
110: 2F 53 4F 53 2E 49 4E 54 45 52 50 AA A5 AO F9 AO /SOS.INTERPtt
120: AO A5 AO AO A5 AO AO 05 AO AO 98 AO FO Al AO CC t.tt.ttttòtI°tA
130: AO AO C5 AO AO AO AO AO EE AO AO C4 0E 2E 44 31 tftttttÓttf. .Dl
140: 2F 53 4F 53 2E 44 52 49 56 45 52 FF 9A AO FF 9A /SOS.DRIVER'öt"ö
150: AO AO AO AO DO AO AO Cl AO AO 8A AO AO F9 AO Cl tttt-ttjttätttj
160: E9 AO 9E Al AO F5 AO AO A5 AO AO 88 00 00 88 OC Ètûotltt.ftà. .à.
170: A9 00 AA 9D 00 lA 90 00 16 9D 00 lB 9D 00 18 90 ©.TMÙ. .ù. .©ù.oç.flùv.Ç.ù
180: 00 14 9D 00 01 CA DO EB A9 30 8D DF FF A2 FE 9A . .ù..
190: lAO:
A9 DF
lA FF
8D A2
DO FF
FF 9A
20 A9
D4 lA
1F 8D
AD DO
DF FF
FF AD
29 01
lO 19
09 8D
28 EF
8D FF
©fl.'äç-©. .'ç.-f"V.).ç.Ô. ("ç
ÍBO: 6C 02 00 AA AD EF FF 48 8E EF FF A5 27 05 26 FO l..TÔ'HéÔ.&I
lCO: 33 AS 26 DO 02 C6 27 C6 26 18 A5 23 65 27 85 23 3.&-.A'A&..*eÖ#
iDO: A5 25 65 27 85 25 E6 27 A4 26 FO 07 Bl 22 91 24 %e'Ö%Ê'&I.±"ê$
lEO: 88 DO F9 Bl 22 91 24 88 C6 23 C6 25 C6 27 DO EC à-±'e$à.%%A'-I
lFO: E6 23 E6 25 68 80 EF FF 60 18 A5 24 65 10 85 10 Ê#%hçÔ'' . .$e.Ö.
APPLE I/I SOS BOOTSTRAP LOADER HEXADECIMAL DUMP Smolinskis Macintosh SARA emulator 1/1
Apple Computer Inc · 1982
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i Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple I/I Computer Inormotion
APPLE I/I
EMULATOR IDEAS
ADDED BY DAVID T CRAIG e 2006
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
g
Apple III Computer Information
Apple III Emulator Ideas
Version 4
12 Dec 1997
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
/1/ SOME IDEAS ABOUT AN * APPLE COMPUTER EMULATOR
David T. Craig - - 12 December 1997 - - Version 4
941 Calle Mejia #1006, Santa Fe, NM 87501 USA
e-mail: 71533.606@compuserve.com
TABLE OF CONTENTS
1.0
PURPOSE
2.0
4
«ñPF/ LI'
'IL4
(PPCJ -e( 'i"
17
3.0
4.0
5.0
6.0
7.0
8.0 9.0
// fx ;e c
10.0 11.0
7/ 4/, 17fr
12.0
13.0
14.0
15.0
16.0
17.0
18.0 19.0
WHAT'S NEXT? REFERENCES
/
(L
MODIFICATIØNHISTORY
28 Nov 1997 - - Version 1 Created by David T. Craig.
Sc- .5j
lE, j'Ct&''
eiI
i- 3v
04 Dec 1997 - - Version 2
Z!
New sections: MONITOR SUPPORT, EMULATOR DEBUGGING FACILITIES.
Updated sections: DISK IMAGES, MEMORY BANK SWITCHING EMULATOR, SOS SYSTEM CALL
EMULATION, REFERENCES. Added several good comments by Chris Smolineki (he's writing a /// emulator called
SARA).
09 Dec 1997 - - Version 3 DISK IMAGES: Updated info about DTCMake3///Disklmage Mac application, made disk image
file an all-text file. SOS SYSTEM CALL EMULATION: typo Silentypr - -> Silentype. WHAT TARGET MACHINES SHOULD BE SUPPORTED: More pre-68040 Mac corriments. EMULATOR DEBUGGING FACILITIES: typo affects - -> affect, added info about enabling/disabling SOS ERK disassembly, same for Pr0DOS, added list of emulator
debugging commands. EMULATOR MEMORY STRUCTURE: New section.
12 Dec 1997 - - Version 4 EMULATOR DEBUGGING FACILITIES: Added examples to every debugging command. Added
commands SNAPSHOTW, SNAPSHOTR, ZPAGE, SPAGE, EPAGE, DRIVERS, macro commands.
Some Ideas about an I Apple /7/ Computer Emulator -- Version 4 David T Craig.. 12 Dec 1997 -- 1 / 23
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
1.0
PURPOSE
This document describes some ideas about implementing a software emulator for the Apple /// computer. These ideas are based on my experiences with the Apple /// computer and its software programming. No specific target machine is mentioned in this document since these ideas should be non-target machine specific. These ideas are submitted to stimulate thought about such an emulator and hopefully inspire
someone to produce a working Apple /1/ emulator.
I/, The technical details behind the Apple /// computer, its operating system (SOS), and
/1/ programs (e.g. Applewriter /1/) are based on my extensive collection of technical manuals, specification sheets, and many /1/ technical articles (Dr. John Jeppeon's articles are very exhaustive and full of lots of neat /// techoid stuff). I have around 15 Apple manuals, the majority of which were published by Apple, which include user manuals and the technical programming manuals.
For those people seriously interested in implementing an Apple /// emulator program I highly recommend that they have at least the Apple /// Service Reference Manual. This manual, which is almost 500 pages long, is the definitive reference for how the Apple /// computer works. Most of its contents describe theory of operation even though its title suggests service-type information only. The important features of this manual for a /// emulator writer are the /// memory map and the /// memory mapped I/O locations.
I also own an Apple /// computer which still today works very well. I programmed the /// many moons ago and have worked professionally as an Apple Macintosh computer programmer since 1984.
Note: All comments are welcome. If you have anything to add or correct please let me know and I will update the master copy of this document.
2.0
EMULATORGOALS
The ¡// emulator should provide a complete emulation environment for the faithful execution of Apple /// and /// Plus programs. As far as the emulator user is concerned when they run the emulator program their computer should work just like an Apple /// computer and all /// visual fidelity should be maintained. Emulation of
the Apple /// Plus computer may also be supported (this means the /// Plus' interlaced screen) . If the /// Plus is supported by the emulator you may want to let
the user specify if they want to run a /7/ or a ¡/7 Plus.
I think it would be beyond neat if the emulator could run Apples running horses demo and the other /// demos.
The /// emulator should support an Apple /// computer with at least 256K of memory and four floppy 140K disks (.Dl, .D2, .D3, .D4). Support for 512K of memory may also exist since the 7//s operating system (SOS) supports up to 512K of memory. Memory size, if variable, should always be a multiple of 32K. I believe the lowest memory size supported by the ¡/7 (ROM?) is 96K. Support for a ProFile disk may also exist (for this disk there would need to be a disk image with a size of 5M). The first
floppy disk (.Dl) would correspond to the floppy disk drive that is built into the
Apple ///. The other disks correspond to external disks and should exist as image files with specific file names (e.g. "Apple 3 Dl", "Apple 3 DV', etc). The ProFile
disk image file should also have a specific file name (e.g. "Apple 3 ProFile").
Image file names should have an extension (e.g. ".D31") since this is needed by PCa.
3.0
EMULATOR USER INTERFACE
When the user runs the Apple ¡/7 emulator program the user should see on their computer screen a screen (or a window representing the screen on GUI systems) corresponding to the //7's screen which the user would see if they were in front of a real Apple /// computer. All /// text and graphic modes should be supported by the
Some Ideas about an d Apple /1/ Computer Emulator -- Version 4 David T Craig -- 12 Dec 1997 -- 2/23
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
/7/ emulator (this includes the special modes supported by the /// Plus and its interlaced screen architecture).
I recommend that the emulator also support a screen dump facility that writes the current /7/ screen to either a text file (for text modes) or to a graphic file (for graphic modes) or always just creates a graphic file. The screen dump graphic file should be a standard graphic file for whatever target machine your support (e.g. on the IBM PC running Windows produce .BMP files, on the Apple Macintosh produce PICT files). Since the /// supports custom character sets dumping the screen to a PICT file (or to the target computer's clipboard) may be the best solution.
The emulator screen if implemented in a GUI window may also display a status area at the bottom of the window. This status area would display at least two lines of text and would keep the user informed of what the emulator was doing internally.
4.0
DISK IMAGES
The /1/ emulator should read disk image files which correspond directly to real /// 140K disks. When the /// emulator starts it should look in its folder and if there exists a /// disk image file the emulator should boot this image. If there are multiple disk image files then the emulator may want to display a list of these images and have the user select an image to boot.
The disk images should be exact copies of real ¡/7 disks. To make copies of these disks there should exist an utility program that runs on the ¡7/ computer and which
outputs disk block data to the ¡/7 serial port (I plan to make this utility and call it DTCDumpIt) . This utility's output should be a hex/ascii dump that specifies block numbers and has a checksum for each line of data. This utility should ask the user if it should dump a file or a disk.
On the target machine there should exist a similar utility that inputs the disk block
data and creates a disk image file. I recommend that the transmitted disk block data consist of a hex dump with block number and checksum information in a human readable fashion. The receiving program (on the target computer) would read this human readable information, verify that the data was sent correctly, and produce binary
disk image file images (I plan to create this utility for the Apple Macintosh and
call it DTCMake///Disklmage).
There should also exist a disk image file for the I//s Boot ROM (recommended file name: "Apple 3 Boot ROM). This image should contain the 4K ROM image. This ROM should be the Revision 1 ROM (not Revision 0) since this was the last ROM produced
and SOS 1.3 (the last SOS) requires this ROM.
Users should also be able to format a disk image by specifying the disk drive device name (e.g. .D2) . Users should then be able to name the disk image so that they can use it later. Users should be able to assign specific disk images to specific disk
drives.
I recommend that all disk image files have a very specific internal format. This format should support the verification of disk image files so that if a disk image file becomes corrupted in some fashion the /7/ emulator can detect this corruption, not use the image, and alert the user.
Note: Support for existing Apple ] [ disk image files may be feasible but I recommend against this since the format of these images could change.
The proposed image format:
The disk image file contains two parts, a header part and a data part. The header part appears first followed by the data part. The header part contains identification and verification information. The data part contains the actual disk blocks for the ¡// disk. This file contains only text, no binary data appears here in any fashion. The only non-text information that can appear in these files is the Carriage Return (CR) and the Line Feed (LF) characters. The emulator should ignore
Some Ideas about an d Apple /7/ Computer Emulator -- Version 4
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Apple Computer Inc · 1982
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LFs if appropriate. All information appears in lines with a maximum length of 255 characters. Character case is immaterial. Blank lines are ignored. The reason for this format is so these image files can be transferred over the internet without the need for any binary-to-text conversion. Also, text-only files can easily be viewed
by people using a word processor.
The header part contains:
Line
Comments
Signature Version Image Name
Creation Date Created by Naine
Coromen t
Data Size Data Checksum Reserved 1 Reserved 2 Reserved 3 Reserved 4 Tech Comment Header Checksum
"APPLE /// DISK IMAGE" 'VERSION' version number (e.g. "1") "IMAGE NAME" name of image, anything the user wants, most likely the name of the interpreter on the disk,
e.g. "Apple Writer ¡7/"
"CREATED" date image file created, "YYYY-MM-DD" "CREATED BY" name of person or company who created this image "COMMENT" comment for anything user wants "DATA SIZE" size of data part (decimal, e.g. 14336011) "DATA CHECKSUM" hexadecimal checksum (e.g. "FA7C3188")
"RESERVED"
"RESERVED" "RESERVED"
"RESERVED" "TECH COMMENT" name of program that this is for "HEADER CHECKSUM" hexadecimal checksum (e.g. "B97C31D5")
Notes:
The checksum should be calculated as the exclusive-OR of each byte followed by a left rotation of 1 bit. Checksum starts with zero. Checksums should always be 4 bytes in size and be stored in the header as an 8 character string.
The Tech Comment's purpose is to allow people who obtain an image file to be able to contact someone about the file's purpose.
The data part contains lines representing 16 bytes from the original disk Each line has a specific format which begins with the starting disk address for the line, 16 bytes, the ASCII equivalent of the 16 bytes, and a checksum for the bytes of the line
with the format:
[00000000] 0123 4567 89ab cdef 0123 4567 89ab cdef [1234567890123456] 12345678
The last line of the file must be the word "FINIS".
Sample disk image file:
APPLE /1/ DISK IMAGE VERSION 1
IMAGE NAME Apple Writer ¡/7
CREATED 1997-10-11 CREATED BY David T. Craig COMMENT Thanks to Paul Lutus DATA SIZE 16
DATA CHECKSUM FA7C3 188 RESERVED RESERVED RESERVED RESERVED TECH COMMENT For David Craig's /// Emulator - 71533.606@compuserve.com HEADER CHECKSUM B97C31D5
[00000000] 0123 4567 89ab cdef 0123 4567 89ab cdef [Apple.///.Emul. .] FA7C3188
Some Ideas about an Í Apple I/I Computer Emulator -- Version 4 David T Craig-- 12 Dec 1997 -. 4 / 23
Apple Computer Inc · 1982
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FINIS
5.0
6502 CPU EMULATION
The heart of the ¡/1 emulator should be the emulation of the 6502 CPU. The heart may be referred to as the "6502 engine." The emulator should support all of the 6502 instructions, the 6502 registers, and the special Apple /// registers (e.g. the bank switch register, the environment register, and the zero-page register). Special register descriptions and usage can be found in the Apple /// SOS Reference Manual.
The 6502 engine must be smart about accessing memory and use the bank switch and environment registers correctly.
If this level of the /1/ emulation is complete and robust the rest of the I/I
emulator should work much more easily.
Support for special ¡/1 features may also exist at this level of the /// emulator. For example, the ¡/1 emulator may not want to emulate all of the ///'s memory-mapped I/O features, but instead intercept access to special areas or routines and call the target machine's operating system to handle these features. See sections ROM EMULATION and MEMORY-MAPPED I/O EMULATION for more details.
6.0
ROM EMULATION
The /// emulator should also support as much as possible the ///'s Boot ROM. This means the Boot ROM's routines should work for the most part as-is.
Note: I have a listing of the Boot ROM which could be useful for this emulation discussion.
For the Boot ROM's floppy disk I/O support I recommend that all the gory details here not be supported directly at the memory-mapped I/O level but instead the /// emulator should emulate this I/O. Specifically, the /// emulator should intercept any access to the Boot ROM routines which read or write disk blocks and use the appropriate target machine operating system routines to accomplish this feature.
The /// emulator should also initialize the ROM's character set which the ROM normally loads into a special RAM chip that is not accessible to the ///s 6502 processor. See section MEMORY BANK SWITCHING EMULATION for more details.
7 .0
MEMORY-MAPPED I/O EMULATION
All memory-mapped I/O locations that in some way deal with the physical world need to be handled by the /// emulator. These areas include such addresses as the speaker addresses. The Apple /1/ Service Reference Manual provides detailed information about these addresses.
All accesses to memory by the /1/ emulator must respect the bank switch and environment register settings so that the emulator does not try to access a memorymapped address when that address is not mapped into the 6502 address space.
Programs which access low-level I/O locations such as the disk I/O addresses should not be supported. I assume most /// programs will access hardware components using SOS or device drivers.
Note: Chris Smolinski says that emulating the low-level stuff on a Power PC-based Macintosh is not very difficult and works rather fast (he's implemented in his SARA emulator the i/i's floppy disk I/O).
8.0
MEMORY BANK SWITCHING EMULATION
The ¡// emulator must also fully support the ///'s bank switched and enhanced indirect addressing memory architecture. Detailed descriptions and usage of ¡/1 memory handling can be found in the Apple /// SOS Reference Manual.
Some Ideas about an I Apple I/I Computer Emulator -- Version 4
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The /// emulator should also support the I/f's character set RAM chip. This holds
the bitmap descriptions of each of the 128 characters in the /// character. This RAN
area, which is not accessible to the i/i's 6502 CPU, holds 1024 bytes. See the Apple
/1/ Standard Device Drivers Manual (Console Character Sets section) for more
information.
Note: I believe the storage of the Boot ROM character set is different than the storage of the character set in the SOS.DRIVER file. I believe the ROM character set has bits that are reversed compared to the SOS.DRIVER character set.
The storage of text and graphics in memory should be supported also. Phis should happen automatically when a /// program writes to the text/graphic memory buffers. The emulator needs to detect such writes and update its screen as appropriate.
9.0
sos SYSTEM CALL EMULATION
The majority of system calls to SOS and its drivers should most likely not be intercepted by the ¡// emulator. But certain calls may need to be intercepted unless a lower level of the /1/ emulator intercepts these feature already. System calls to
SOS or drivers that may need intercepting by the /1/ emulator could be:
o Disk I/O o Keyboard I/O o Screen I/O o Sound generation o Serial port I/O o Silentype Printer o Clock I/O
(.D[l-4] and .PROFILE drivers) (.CONSOLE driver) (CONSOLE and .GRAPHIC drivers) (.AtJDIO driver) (.RS232 driver) (.SILENTYPE) [I'm not sure about support for this] (Y2K dates may be a problem)
I recommend that the /1/ emulator intercept all activity dealing with the above and have the target machine perform the equivalent features. For example, to read or write a disk block the ¡/1 emulator should have a routine that accesses the appropriate location in the disk image file.
The /// emulator may also provide the user with some type of setup options so that the user can specify specific properties of some of the above drivers. For example, if the target machine supports several output ports the emulator may let the user specify which port to use (e.g. for the .PRINTER driver the user could assign it to a specific serial or parallel port on the target machine).
Note: The ///'s clock does not support the year 2000 or greater. I think the emulator should support Y2K dates but I'm not sure if SOS's file system date stamps
will support this easily.
10.0
DEVICE DRIVER EMULATION
This section is for the most part handled by my comments in section SOS SYSTEM CALL EMULATION. I suspect the programming within the /// emulator for this area could be the most work since there are lots of device drivers that make up a simple Apple ///
configuration.
One area of device drivers that the /1/ emulator may not want to emulate is interrupt handling. Since the emulator does not have physical devices connected to it in any direct fashion I dont think interrupts exist as tar as the emulator is concerned. Interrupts dealing with disks or the keyboard can be handled at a lower level by having the /// emulator call the appropriate system call in the target machine. These low-level I/O handlers should set up the appropriate driver data areas so that the rest of the I/I's software (SOS and the interpreter) will work correctly. For example, keyboard I/O should be setup in the /7/ emulator so that when the keyboard input memory-mapped I/O location is accessed the target machine OS really reads the
keyboard and sets up the memory-mapped location as appropriate.
11.0
KEYBOARD SUPPORT
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11.1
User interface support
The /// computer's keyboard layout is basically compatible with modern keyboards.
The /1/ keyboard does have two extra keys, Open Apple and Closed Apple which are positioned to the left of the Apple /1/ keyboard. Also present on the keyboard are
I//s four arrow keys. The emulator should support these keys either directly (i.e., the
target machine has similar keys) or associate other keys with the
special keys
(e.g., the Macintosh computer's two Option keys could be used to simulate the special
Open and Closed Apple keys). The emulator's associated keys need not physically be
in the same location as the ///'s special keys but having them in the general area
will be beneficial.
I/I Note: The /// Plus keyboard contains an extra key, Delete, compared to the
keyboard.
11.2
Low-level access
The /// emulator should handle low-level access to the keyboard memory-mapped I/O locations as detailed in section DEVICE DRIVER EMULATION.
12.0
MONITOR SUPPORT
The emulator should support the Apple's built-in ROM Monitor. Entry to the Monitor
should be similar to how this is done on a real ¡/1 (at startup if Open Apple and
Control keys are pressed). The code in the ROM which tests for Monitor entry should work.
13 .0
APPLE ] ( EMULATION DISK SUPPORT
It would be nice if the /// emulator supported the Apple ] [ Emulation Disk. I'm not sure of what would be involved here but suspect that if the I/I's 6502 CPU and the memory-mapped I/O locations are robustly supported that the [ emulation should work
]
also without any special additional /1/ emulation features.
Special consideration may need to be given to Apple /// keyboard keys which do not
exist in the Apple ] [ world.
[ emulation details can be found in the Apple ///
]
Owner's Guide and the Apple /// Service Reference Manual.
Note: I have a disassembled listing of the Apple ] [ Emulation Disk ROM source listing which could prove useful in this area.
Further analysis of the ] emulation disk's boot sequence needs to be done since I'm
[
unknowledgable about this area.
Also, I've heard that the [ emulation accesses an ]
I/O location which disables some /// features.
14.0
WHAT LANGUAGE SHOULD THE /// EMULATOR BE WRITTEN IN?
I highly recommend that the /// emulator be written in a high level language such as Pascal or C. This should make the emulator more compatible with different target computers and make development and maintenance of the emulator much easier. I recommend avoiding low-level languages such as assembly.
15 .0
WHAT TARGET MACHINES SHOULD BE SUPPORTED?
I recommend that the target machine (or machines) for the emulator be machines that
are commonly used today by most computer users. This means either the IBM PC or the
I/I Apple Macintosh machine family. For the PC world I recommend the
emulator run
under Windows 95 and Windows NT. For the Macintosh world I recommend the emulator
run on most Macintosh models which means support the Macintosh 512 and above. Color
display should also be supported by the /1/ emulator (for the Macintosh this means
use Color QuickDraw if the machine supports CQD and if CQD is not supported by a
Macintosh model use the Classic B/W QD and maybe use patterns as "colors").
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Any of these machines should be fast enough to emulate the /// and most likely will be too fast in many areas. I recommend some type of speed control be built into the emulator so that users can control how fast the emulator works. For many /// programs (e.g. Applewriter /// and VisiCalc /11) emulation speed will be immaterial
since these programs typically wait for the user to enter data and then do their thing. But for programs such as games the user will want to control the emulator speed otherwise the game's actions will be super fast and unplayable.
Some people say that the older machines such as pre-68040 Macintoshs will be too slow
for a reasonable /1/ emulator. I would like to see this /// emulator run on a Mac
512 machine an onwards. Running on a Mac 128 machine seems a problem due to this machine's small memory size and should not be supported (if a virtual memory scheme was used by the emulator the Mac 128 could be supported but I think having this extra level of support in the emulator would not be worth it). I disagree and am willing
to wager a small sum that I'm right.
16.0
EMULATOR DEBUGGING FACILITIES
The emulator should support a comprehensive built-in debugger. This debugger's purpose should be to let the sophisticated emulator user access any part of the emulator's /// address space. This should include all of the memory that is allocated to the /// as its memory. This memory would encompass the 256K (or 512K) of /// RAM, the /// ROM (4K), the character set RPM (1K), the 6502 registers, and the
special /// registers (e.g. bank register).
This debugger will prove invaluable in diagnosing emulator bugs. Not only will the user be able to type commands for the debugger but the emulator will be able to send messages to the debugger.
Logging of all debugger sessions should be stored to a text file for possible analysis. This text file would be created when the emulator starts. The log file should be appended to by the emulator. Only the user can delete the file.
The debugger should exist as a separate window that does not in any way affect the emulator's main window. This window should display only commands that the user enters or replies returned by the debugger. There should not exist a separate window area showing things such as the 6502 registers since all such information should appear in the debugger log file. The window should support at least 80 columns of text and 24 rows.
The emulator user interface should be based on a simple command line control scheme. All commands and command outputs should be text-based. This scheme could be based on the I//s Monitor's commands or on a little more readable command scheme such as in Apple's MacsBug debugger. There should be full on-line help that discusses the debugger commands in general and each command should also have on-line help available. The debugger should show at the beginning of each line a prompt character to indicate when it is waiting for a command. I recommend the prompt be the ">" character. The debugger should also show a cursor which I recommend to be a black square.
The debugger should support the standard debugging commands such as displaying/setting memory, displaying/setting registers, and disassembling 6502 instructions. This disassembly should support the special SOS BRK call by listing the word "BRK/SOS" instead of just "ERK" and following this with the SOS command
nuniber/nanie and the parameter list address:
SOS CO/CREATE 345A
The user should be able to enable or disable this feature. Note: It may be good to also support the Apple ] [ Pr0DOS command calling scheme in case this emulator ever becomes an Apple J [ emulator. The debugger should support break points, single stepping, and timing buckets. The
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timing buckets would be used in conjunction with break points to record how long a sequence of 6502 instructions took to execute. This can be very useful in locating emulator bottlenecks. The debugger supports many break point commands since I have a feeling that this facility will be very powerful and useful during the emulator's development.
The debugger should support the collection of statistics about the emulator. I recommend tracking how many times specific 6502 opcodes are executed (obviously, the debugger would need commands to display and clear this information). I would also track memory accesses on at least a page (256 bytes) basis.
The debugger should be accessible at any time that the emulator is running. I recommend some type of key press combination that the emulator would detect and display the debugger window. Once the debugger window is active it should remain on the screen until the user closes the window.
The emulator should also support a special key press combination at emulator startup time that activates the debugger just before the /1/ ROM is run. This can give the emulator developer a good way of tracing ROM execution.
The emulator should activate the debugger if any fatal emulation errors are detected and the debugger should show a message detailing the reason for the activation. All of these errors display a dump of the 6502 and SOS control registers. Reasons for debugger activation from the emulator are:
A program writes to write-protected memory (e.g. SOS's address space). The displayed message is 'EMULATOR EXCEPTION: WRITING TO WRITE-PROTECTED MEMORY".
A program executes an undefined 6502 instruction (e.g. 6502 opcode $02). The displayed message is 'EMULATOR EXCEPTION: UNDEFINED 6502 OPCODE".
When the debugger is initialized (which should be when the emulator starts) the debugger should check if a text file named "DDT.TXT" exists. If so, the debugger should read each line from this file and execute it. Obviously, this file should contain debugger instructions. This can be very useful for setting up commonly used break points which if you use many would be tedious to type everytime you wanted to use the emulator.
A memory snapshot facility should also exist. When activated by a debugger command this facility would write to the host computer's disk a binary file containing a copy of all the /// memory areas. This snapshot should also be readable by the debugger so that the user could restart a specific emulation session from the snapshot.
I recommend the following emulator debugger commands which are based on the /// Monitor commands so that these debugger commands will be familiar to Monitor users. These commands for the most part have the general syntax of address-command. See my document "Inside the Apple /// Computer ROM" for a list of the I/I Monitor commands.
For information about the Apple I E Monitor commands, which the /1/ Monitor commands
are based upon, see "Apple ] [ Reference Manual" (Chapter 3: The System Monitor, dated
1981)
Addresses appearing in debugger commands may be prefaced by "N/" where N is a bank number. For example, to reference address 2000 of bank 4 use 4/2000. If no bank number precedes an address the current bank is used. To reference a ROM address use a bank "number' of "R', for example "R/FOOO". To reference a character set address use a bank "number" of 'C, for example 'C/OOOO". To reference the SOS system bank use "S", e.g. 'S/1400".
Commands should be case-insensitive (none of the UNIX case-sensitivity gobbly-gook).
Commands that display more than a screen full of information should either automatically pause when the screen is full, or the user can use the SPACE key.
Note: Commands using ":" may also use ";" which is easier to type since this
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character does not need the user of the shift key. Same for "<" and 1/11.
Most debugger command numeric arguments must be specified in hexadecimal. The exception is the X command which supports hexadecimal, decimal, and binary.
The debugger command parser should be very liberal. This means that users should be able to include extra spaces (or no spaces) and the command should be parsable. For example, if a command needs a list of bytes the user should be able to enter any of
the following: "AABBCC", 'AA BB CC", " A ABEC C " and the debugger will see these
as "AABBCC".
The debugger should also support a command macro facility. This facility allows you to define a macro consisting of other debugger commands. Typing the name of the macro will then type the commands as if you entered them manually.
/ HELP or ?) CtJ tO4-
Display debugger on-line help for all commands. Help info should be stored in an
i f.' ' external text file for easier modification. I reconimend that this section of this
document be the help file. (
Example: HELP
£ --
A 1? C «-.-'t
f
BYE
l'-11L,c
Return to the emulator.
Example: BYE
CARRIAGE RETURN keypress
--j
Repeat last command.
Example: If the last command was HELP and you press the CARRIAGE RETURN key then HELP will be displayed and executed again.
SPACE keypress
L
Z S
Pause current command's output. Press again to continue.
Example: If a command is executing and you press the SPACE key the comand's output will be paused, pressing SPACE again resumes the command's output. Pausing/Resuming are done on an output line basis only.
DELETE keypress
L-
Stop current command's output.
Example: If a command is executing and you press this key then the command will stop
executing and you will be returned to the debugger's prompt.
RD Display 6502 registers and /1/ system control registers.
eI"'i .tL*.J
j,, f)
&
Example: RD A=04 X=0l Y=D8
Nrt 1211 n&
P=30/000000ll
S=F8 PC=034A :
O r 1-
hh ).,:1 E=77/0111011l
Z=lA
B=03
Some Ideas about an U Apple I/I Computer Emulator -- Version 4
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I
$'L-j-.
1b-'ji. kL. David T Craig -- 12 Dec 1997 -- 10/23
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byte: SA Set 6502 A register to byte. Example: 45:SA
byte:SX
Set 6502 X register to byte.
Example: 7B:SX
-
byte:SY Set 6502 Y register to byte. Example: FF:SY
byte: SP Set 6502 p register to byte. Example: 56:SP
byte:SS Set 6502 S register to byte. Example: AA:SS
word:SPC Set 6502 Pc register to word.
Example: 2000:SPC --
byte: SE
Set 11/ E system control register to byte.
Example: 34:SE
byte: SZ Set /// Z system control register to byte. Example: l9:SZ
byte:SB Set /// B system control register to byte. Example: 06:SB
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addrl . addr2
Dump memory data to screen from address i to address 2 and display ASCII character at
the right of the screen.
Example
es current bank is baí 300.30F
-- -S---
-j 9ij
O 2. T '--------
('i'-
4/0300- B900 080A OAOA 9900 OBCB DOF4 A62B A909 [F. .d.uy%&90@. .G]
Z PAGE
Dump the contents of the current interpreter's Zero Page (256 bytes). Also supported are commands for the Stack Page and the Extend Page:
S PAGE
EPAGE
stack page extend page
To dump the pages for SOS (and drivers) use the following commands:
SZ PAGE SS PAGE SE PAGE
zero page stack page extend page
Example: ZPAGE
Zero Page (interpreter)
-
't' I
1400- 0123456789ABCDEF 0123456789ABCDEF 0123456789AECDEF 0123456789ABCDEF
1420- 0123456789ABCDEF 0123456789ABCDEF 0123456789ABCDEF 0123456789ABCDEF
i4EO- 0123456789ABCDEF 0123456789ABCDEF 0123456789ABCDEF 0123456789ABCDEF
addr:bytea
Store starting at the address the bytes.
Example: 2000:AA BB CC OD EE FF 2000 :AABBCCDDEEFF
addr: 'text'
Store text starting at address (high bit clear).
Example: 2000:'Hello World' 2000:'David''s Dog'
his storesDavid's Dog
addr: "text"
Store text starting at address (high bit set)
Example: 2000:"Hello World"
2000:"David's Dog"
,2 2o "11-
n ¿rjj,. n n n
addr3 <addrl . addr2M
(t4IJf j
Move data in address range to address 3.
Example: 2000<3000.3lOOM
)A,"e/J-'
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addr3 <addrl . addr2V Verify data in address range equals data starting at address 3.
Example: 2000<3000.3100V Displays either "OK" if the verification suceeds, or "MISMATCH" if the verification fails.
bytes<addrl . addr2S
Search memory in address range for the bytes.
Example: AA<3000.3100S AABBCC<3000.3lOOS
-- searches for byte AA - - searches for bytes AA BB CC
If a search finds a match then the starting address of the match is displayed,
otherwise "PATTERN NOT FOUND" is displayed.
/
1'X1iJJKí!J F° jL/ /f T
'<addrl . addr2S
Search memory in address range for text (high bit clear).
Example: 'D'<3000.3100S 'David' <3000.3lOOS
"text"<addrl .addr2S
Search memory in address range for text (high bit set).
Example: "D"<3000.3100S "David" <3000. 3100S
disk. block<addrl . addr2W
Write address range to disk # disk starting at disk block. If disk * is not present then uses disk .Dl. Disk should equal 1, 2, 3, or 4. The address range always ends on a block boundary no matter what you type.
Example: l.117<2000.21FFW - - write 512 bytes to disk i block $117
Note: Disk /1/ disks contain 280 blocks ($118) sot he block range is 0-117 (hexadecimal).
disk.block<addrl .addr2R
Read from disk # disk starting at block to the address range. If disk * is not present then uses disk .Dl. See the W conmand for more info.
Example: l.l17<2000.21FFR
read 512 bytes from disk 1 block $117
disk .block -block: DISK
Read block range from disk # disk to a special debugger 4K buffer which is not used by the emulator. If the typed block range is greater than 4K then only the first 4K will be read. You can then examine this buffer's contents either with a hex/ascii
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dump or with a disassembly (command L). This command is useful when you want to examine a disks contents. For disassembly purposes, you can specify the logical starting address for the buffer. See the DISKBtJFFER command.
To disassemble the special disk buffer (see the L command) use bank X (stands for "extra') as part of the disassembly address parameter (e.g. "X/lOO") . Same for dumping memory or whatever commands you want to use with this special buffer.
Example: 1.0-7:1115K
-- read 8 blocks (0 to 7) from disk i
addr : DISKBUFFER
Set disk buffer starting logical address. command.
Example: A000 :DISKBUFFER
-
Default address is 2000. See the DISK
(
9_,1ÇF)
¡.
addrl . addr2L
Disassemble instructions in address range. If only addrl appears then disassemble 20 instructions. Disassembly includes the opcode cycle count.
Example: 300L
assumes bank 4 is current
4/03004/03024/03054/03064/03084/030A4/030C-
A9 Cl 20 ED FD
18
69 DA C9 DB DO F6
60
'X.1
'...'
'.
'T.
'.»
'
.
.
'U'
(2) LDA #$Cl (5) LJSR $FDED (2) CLC (4) ADC #$0l (3) CMP #$DB (3) BNE $0302 (4) RTS
1
2
3
4
5
6 (see Note)
Note:
Column 1 = bank register/address Column 2 = memory bytes Column 3 = ASCII for the memory bytes Column 4 = opcode cycle count Column 5 = disassembled instructions Column 6 = remark character ";" (optional, see DISASMREM)
L by itself disassembles the next 20 instructions.
DISASMREM
Display '; after each disassembly line that is produced by the L command. Default is to not display the remark. Useful if you plan to add comments to a disassembly. See also DISASMREMOFF.
Example: DISASMREM
DISASMREMOFF Turn off DISASMREM. See also DISASMREM. Example: DISASMREMOFF
addrG
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Call subroutine at the address.
Example: A000G
-
addrJ Jump to the address. Example: A000J
wordX
Convert word (or up to 4 hex digits) to hexadecimal, decimal, and binary (X stands
for translate') . Prefix character for byte determines its base: no prefix = hex,
= dec. t = binary.
I1-fl1 11-t&y-
Example: AX
->
A(16)
10(10) 0000 0000 0000 1010 (2) ecsie1- V'Li
.1OX
->
A(l6)
10(10) 0000 0000 0000 1010 (2)
tiOlO FFFFX
->
A(16)
10(10) 0000 0000 0000 1010 (2)
-> FFFF(16) 65535(10) 1111 1111 1111 1111(2)
addrl . addr2 : Cs
Calculate and display a checksum for address range. Checksum is a 4 byte quantity which is calculated the same as the disk image file checksums.
Example: 300.500:CS CHECKSUM=AF897 CEE
addrT
Trace instructions starting at the address. Each traced instruction displays register contents. Press the SPACE to pause the trace, press DELETE to stop the trace. The displayed registers contain values _after_ the previously listed command
executes.
Example: A000T -- assuming bank 4 is current
4/A000- A9 Cl
'X.'
(2)
A=Cl X=0l Y=D8 P=30/000000ll
4/A002- 20 ED FD '...' (5)
A=Cl X=Ol Y=D8 P=30/00000011
LDA #$Cl S=F8 PC=A002 : E=77/0111011l JSR $FDED S=F6 PC=FDED : E=77/0111011l
Z=lA Z=lA
B=04 B=04
Note: Press the DELETE key to stop the trace, SPACE to pause/resume.
addrSS
Single step trace starting at the address. After each step pause and wait for user to press SPACE to continue or DELETE to stop the single step.
Example: A000( -- assuming bank 4 is current
4/A000- A9 Cl
'x» (2) LDA #$Cl
A=Cl X=0l Y=D8 P=30/000000ll SF8 PC=A002 : E=77/0111011l Z=lA B=04
t y0
1M414j
Note: Press SS by itself to single step the next instruction, or press CARRIAGE
RETURN to repeat the SS.
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addr:BP
Set a break point at address. When address is accessed the debugger is entered and displays the registers. Up to 100 break points should be supported.
Example: A000:BP
addr:BPC Clear break point at address. Example: A000:BPC
SOS:BP
Set a break point when a SOS call is made. This means when the BRK opcode is executed. Same as M00:BP.
Example: SOS:BP
Mopcode: BP Set a break point when opcode is executed. Example: M60:BP - - set break point when the RTS instruction (60) is executed.
ROM:BP Set a break point when a call is made to the ROM. Example: ROM:BP
addrl . addr2 : BPW
Set a break point when any address within address range is written to. BPW = Break Point Write.
Example: 300.123AR:BPW
addrl . addr2 : BPR
Set a break point when any address within address range is read from. BPR = Break Point Read.
Example: 300.123A:BPR
addr . byte: BPE
1' It: ( t-tU Set a break point when the address contents equal the byte value. BPE = Break Point
Equals.
1
Example: 300.AA:BPE
addr.bytel-byte2 :BPE Set a break point when the address contents equal a byte value in the byte range. BPE
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= Break Point Equals. Example: 300.AA-BB:BPE
Li Ck-I
iP
5'c,jt. j-7-(
eC4f5
4
addr.bytelbyte2 ... :BPEA -.E_
Set a break point when the address contents equal byte 1 value, or equals byte 2 value, etc. Supports up to 16 byte values. BPEA = Break Point Equals Any.
Example: 300 .AABBCCDD:BPEA 300.AA BB CC DD:BPEA
addrl.addr2.bytelbyte2 ... :BPEA
Set a break point when the address range contains any bytes equalling the byte values. BPEA = Break Point Equals Any.
Example: 300.400.AABECCDD:BPEA
addrl . addr2 . bytel - byte2 : BPEA
Set a break point when the address range contents equal the byte range. BPEA Point Equals Any.
Example: 300.400.AA-BB:BPEA
Break
BPD Display break point table. Example: BPD
# Address Range EP Setting 1 4/2000-4/21FF BPEA AA-BE
BPC Clear break point table. Example: BPC
addrl . addr2 : TB
Set timing bucket for address range. When address 1 is accessed timing starts. When address 2 is accessed timing stops. Up to 100 timing buckets should be supported.
Example: A000.A1FF:TB
TBD Display timing bucket table. Shows all set timing buckets and the time in 1/60th of a second and in seconds spent in each bucket.
Example: TBD
# Address Range Time (1/60s) Time (secs>
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1 4/A000-4/A1FF 2 4/A300-4/A310
34
0.567
5
0.083
39
0.650
addr:TBC
Clear timing bucket starting at address. Example: A000:TBC
TBC Clear timing bucket table. Example: TBC
error: SOSE
List SOS general error message for the error number. If no error number is present then list all general errors. Error info should be stored in an external text file for easier modification. See the SOS Reference Manual for a list of these errors. Example: 0l:SOSE BADSCNUM - Invalid SOS call number
error: SOSFE
Display SOS fatal error message for the error number. If no error number is present then list all fatal errors. See the SOS Reference Manual for a list of these errors. Example: 0l:SOSFE BADBRK - Invalid BRK
coniinand: SOS
Display SOS command name and SOS command area (e.g. file system) for the command number. If no command number present then list all SOS command numbers and their names. Command info should be stored in an external text file for easier modification. See the SOS Reference Manual for a list of these commands.
Example: C0:SOS
CREATE (File System)
SOSON
Turn on disassembly of SOS calls which displays SOS followed by the command number and parameter address. The emulator defaults to this.
Example: SOSON
SOSOFF
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Turns off SOSON. Example: SOSOFF
disk:CAT
Display catalog of SOS disk stored in disk # disk. Includes recursive list of all subdirectories. Should show saine file info as Apples System Utilities program.
Note: Other comands that may be supported include CATPASCAL for Apple ] [ Pascal disks and CATDOS for Apple ] [ DOS disks. This may come in handy if you want to see what these disks contain if you have them as disk image files.
Example: l:CAT
disk. file_name: INFO
Displays information about the specified file in the disk. Information includes standard SOS file information but also block list of all index blocks (if any) associated with the file and block list of all data blocks for the file.
Example: 1 . APPLE3 . TEXT: INFO
disk .block : DUMP
Display contents of specified disk block in the standard hex/ascii dump format. Example: l.O:DUMP
disk:DRIVERS
Display list of contents of the SOS.DRIVER file stored on the disk. List includes driver names, driver information, and other items that are in the driver file (e.g. character sets)
Example: l:DRIVERS
disk: CHECKIMAGE
Check validity of disk image in disk # disk. Computes header and data part checksums and compares against the image files listed checksums.
Example: 1: CHECKIMAGE
DIT
Display Driver Information Table (DIT), a data structure maintained by this debugger. Contains list of all loaded drivers, their names, sizes, and entry point addresses.
Example: DIT
MIT
Display Memory Information Table (MIT), a data structure maintained by this debugger. See section EMULATOR MEMORY STRUCTURE for what this structure contains.
Example: MIT
Some Ideas about an I Apple /// Computer Emulator -- Version 4 David T Craig - 12 Dec 1997 -- 19/23
Apple Computer Inc · 1982
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OPCODES
Display a histogram of opcode execution counts. Includes the actual number of the counts. Sorted by frequency. Opcodes not executed are listed below the histogram.
Example: OPCODES
LDA 2,188,973 ***********************************************
STA
12,123 ******************************
CMP
467 **************
2,201,563
Unexecuted opcodes: TXS NOP
OPCODESCLR Reset opcode histogram table. Example: OPCODESCLR
pagel .page2 :MEMORYR
Display memory write access table. This table lists on a 256 byte page basis counts for each time the page was read. If pagel.page2 specified then lists only those pages. If a single page is specified then display only that page's access count.
Example: 0.5 :MEMORYR
pagel .page2 :MEMORYW
Display memory read access table. This table lists on a 256 byte page basis counts for each time the page was written. See MEMORYW for page options.
Example: 0.5 :MEMORYW
MEMORYCLR Reset both memory access tables. Example: MEMORYCLR
value:SCROLL
o -±L-
Set debugger display scrolling rate interline delay. Value is in 1/10th of a second. Default is no delay (value = 0). Useful if you want to for example dump lots of memory and don't want to mess with the SPACE key to read what is displayed. Set the scrolling delay to a comfortable value, sit back, and enjoy the show.
Example: lO:SCROLL -- sets scrolling delay to 1 second
filename: LOG
Close log file, create a new one with filename, and output all debugger displays to this new file. Useful if youtre running the emulator from a write-protected disk and you want to re-direct the output to a writable disk file.
Some Ideas about an I Apple I/I Computer Emulator - Version 4
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Apple Computer Inc · 1982
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Example: MyDiary: LOG
SNAPSHOTW
Write the contents of all of the emulator's memory to binary file on the host computer's hard disk. This snapshot could prove useful in diagnosing an emulator problem. The binary file should be named "Snapshot_YYYYIMDD_HHMMSS.BIN".
Example: SNAPSHOTW
SNAPSHOPRfi1e -name Read a snapshot file into the emulator's memory. Example: SNAPSHOTR Snapshot_19971225_l23456.BIN
MACRO name commands
Define a macro naine and commands for this macro. You can use any name containing alphnumeric characters or periods with a maximum length of 31 characters. Up to 25 macros may be defined. All commands are verified and if any syntax errors occur you will be told and the macro will not be defined. Macro commands cannot include other macro commands.
Example: MACRO my.dump 300.400 A000.A1FF A000L
MACROL List all defined macros. Example: MACROL
# Name / Contents i my.dump
300.400 A000.A1FF A000L
imacro-name
Execute a macro with the name "macro-name". Each command within the macro is displayed followed by the conunands' display.
Example: !my.dump
300.400
.A1FF
A000L
)f/( C
ÒA
-:#
VERS ION
Display debugger version information. Includes version number and creation date/time.
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17 . O
EMULATOR MEMORY STRUCTURE
I recommend that the emulator's internal memory structure for the Apple /// memory resources be structured as follows:
o Memory block containing the size of memory and references to each I/I memory bank (the references can be whatever is appropriate -- on the Mac these could be Mac memory pointers or handles)
- number of switchable banks (1. .15)
- reference to bank S
(32K: 0000-1FFF, A000-FFFF) *
- reference to bank 0/$0 - switchable - reference to bank l/$l - switchable
(32k: 2000-9FFF) (32k: 2000-9FFF)
- reference to bank 14/$E - switchable
(32k: 2000-9FFF)
- reference to Boot ROM ROM address space - reference to Boot ROM RAN address space
(4k: F000-FFFF) (4k: F000-FFFF)
- reference to I/O RAN address space
(4k: C000-CFFF)
* The system (S) bank is always on-line and is never bank switched. SOS and part of the interpreter reside here.
o Memory block containing the 6502 registers:
- Accumulator - X index - Y index - Status Register - Stack Pointer - Program Counter
(A) (X) (Y) (P) (S) (PC)
8 bits 8 bits 8 bits 8 bits 8 bits 16 bits
o Memory block containing the special /// System Control Registers:
- E: Environment Register (FFDF)
- Z: Zero Page Register (FFDO)
- B: Bank Register
(FFEF)
8 bits 8 bits 8 bits
18.0
WHAT'SNEXT?
Persons seriously interested in creating an Apple /// emulator program should try to obtain as much ¡/1 technical information as possible. The author has lots of info which he can copy at minimal charge (10 cents per page plus postage). These persons should also have access to a working Apple /// computer with a fair nuniber of ///
programs.
Other areas of compatibility should also be investigated that this document does not address. This includes support for other input devices such as the mouse which does have a 3rd party driver available.
19.0
REFERENCES
Apple /// Owner's Guide, Apple Computer, 1981
Apple /// Plus Owner's Guide, Apple Computer, 1982
Apple /// System Data Sheet, Apple Computer, July 1983
Apple /// Plus System Data Sheet, Apple Computer, October 1983
Apple /// Standard Device Drivers Manual, Apple Computer, 1981
Some Ideas about an Í Apple /1/ Computer Emulator -- Version 4
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Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
Apple /// SOS Reference Manual, Apple Computer, 1982
Apple /// sos Device Driver Writer's Guide, Apple Computer, 1982
/7/ Apple
Service Reference Manual (Level 2), Apple Computer, 1983
/7/ Bits: John Jeppson's Guided Tour of Highway ///, Sof talk magazine, May 1983
Bank Switch Razzle-Dazzle, Sof talk magazine, August 1982
The Apple Nobody Knows, Apple Orchard magazine, Fall 1981
Apple /// Entry Points, Andy Wells, Call-APPLE, October 1981
Inside the Apple /// Computer ROM, David Craig, Noveiriber 1997
Some Ideas about an S Apple /1/ Computer Emulator -- Version 4
David T Craig -- 12 Dec 1997 -- 23 / 23
Apple Computer Inc · 1982
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Apple /// Computer Information · Apple /// Level 2 Service Reference Manual
i
Apple /// Computer Information
Apple ///
Service Reference Manual
THE END
Written by Apple Computer . 1982
Apple Computer Inc · 1982
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