ADC HDC-2001 Hard Disk Controller Technical Manual 1984

Google Docs
Google Drive
Download [pdf]

File Info : application/pdf, 105 Pages, 5.21MB

ADC HDC-2001 Hard Disk Controller Technical Manual 1984

HDC-2001 Hard Disk Controller
Technical Manual

~ ADVANCED DIGITAL
CORPORATION

USA OFFICE 5432 PRODUCTION DRIVE HUNTINGTON BEACH , CA 92649 TELEPHONE : (714) 891 -4004 . TELEX: 183210 ADVANCED HTBH

UNITED KINGDOM OFFICE 27 PRINCESS " STREET
HANOVER SQUARE . LONDON W1 R8NQ UNITED KINGDOM 409-0077 / 409-3351 TLX 265840 FINEST

ADVANCED DIGITAL CORP. is proud to i ntt"'oduce its HOC-2001 hard disk controller board. The HDC-2001 is a single board controller with ECC(error correction) and CRe all on one board. It follows the IEEE-69G standards and will fit it to any 8-100 Motherboard.

HDC-2001 HARD DISK CONTROLLER Technical Manual

1. I NTRODUCT I ON·············· ...................................· Page 1

..... 1. 1. General Descr i pt i Or'I.
1.2. Features·······

...............

. ........... .

· Page 1 .Page 2

1. 3. Speci ficat ions··

·· Page 3

1. 4. Simplified System Block Diagram.

· Page 4

2. I NTERFACE CONNECTORS." ··· " ··· "." ········· " ·· " ················· Page 5

2. 1. Organization·········· 2.2. Drive Control Signals····

. .

· Page S · Page 5

2. 2. 1. RWC- ··········· "

···· Page 5

2. 2.2. Write Gate-····· 2. 2.3. Seek Complete-.

· Page 5 · ············ Page S

2. 2.4. Track000-·····

·· Page 5

2. 2. 5. Write Fault-.

.Page 5

2. 2.6. H80-HS2-.

········· Page 5

2. 2. 7. Sector-.

.Page 6

2. 2. B. Index-.

······· Page 6

2. 2. 9. Ready-··

· ··· Page 6

2. 2. 10. Step-·· 2. 2. 11. Direction In-·· 2.2.12. D81-0S4-··

.... · Page 6 · Page 6 · Page 6

2.2.13. Control Driver/Receiver·· 2. 2. 14. 50 Pin Drive Control Connector. 2. 2. 15. 34 Pin Drive Control Connector.

. . . . . . . . . . .

·· Page 7
· Page a

· ·· Page 9

2. 3. Drive Data Signals···

· ·· Page 9

2.3. 1. D1'''ive Selected-·· 2. 3.2. Timing Clock+.

. ....

· Page 9 ·· Page 9

2. 3. 3. 2. 3. 4. 2. 3. 5.

TimiY'lg Clock-···
MFM Write Data +-········ MFM Read Data +- ···

· Page 9 · ·· Page 9
· Page 10

2. 3. 6. Drive Data Connectors·······

·· Page 10

2. 3. 7. Differential Data Driver/Receiver··

· Page 10

3. INTERFACE TIMING···· ..........................................Page 11

3. 1. D1'''i ve Control Timing. 3.2. O1''''i ve Data Timing · · · · ·

...........

· Page 11 ·· Page 12

4. TASK FILE········ ~ ............................................Page 13

4. 1. 4.2. 4. 3.

Task Fi Ie Basics.
..... Register Array ··· ..... Register Oefi Y'li t ions ··

." .

4. 3. 1. Cc,mmand Reg ister··

4. 3.2. 4. 3. 3. 4. 3. 4. 4. 3. 5.
4. 3.6. 4. 3. 7.

Statl.,s Register··
... SOH Register ·····
..... Cylinder N'.lmber ··
..... Sector N'.lMber·· ...... Secto1''' Count ··
..... Error Reg ister··

.......

· Page 13 · Page 13 · Page 13 · Page 13 · Page 13 ·· Page 13
· Page 14 · Page 14
..· Page 15 · P4ilg e 15

HDC-2001 HARD DISK CONTROLLER Technical Manual

4.4. 4.5.
4. 6.

.... 4. 3. 8.

..... 4. 3. 9.

·.... ·..·... Stat I.'S ..... ... ·.. status

.....·.. ..... 4. 5. 1.

... ... ·.. 4.

.::.
!;;;..

·... ....·.. 4. 5. 3.

Write Preccmlp ···
Data Reg ister.
Registers·· " ··· Registers Bits··
El~r()t~ · · · · · · · · Corrected ····· Data Request ··

· Page 15
· Page 15
· Page 16 1 6 ··~age
· ·· Page 16 · Page 16 · Page 16

4. 5. 4. See~ Cornplete ··
4. 5. 5. Write Fault ··

4. 5. 6. Ready·······
..... 4. 5. 7. Busy ········· ... E'1'''l'''CI1''' Register Bits ··

a· · · ·

4. 6. 1. DAM NClt Found. 4. 6 · .c-,:. TR000 Error ·····

. . . .

4.6. 3. Aborted Comnland.

4. 6. 4. ID Not F clurld ··

4. 6. 5. CRC El'''ror 10. 4. 6. 6. UnCClt"l'''ect a b 1e.

.....

·..··.........·.

·· Page 16 ·· Page 16 · ·· Page 17
· Page 17

..·.... ·. . ..·.. ... ·......

....

· Page 17 · Page 17 ·· Page 17
· Page 17
. · Page 17 .....· · Page 17

· Page 18

4. 6. 7. Bad Block Detect ··

· Page 18

5. .

COMMANDS · · · · · · · · · · · · · · · · · Page 1 9 II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. ... .. 5. 1. Command Summary ··

..... ...

· Page 20

. ...... 5. 1. 1. Steppirlg Rates.
5. 1. 2. DMA Read.

. . . . . .

· · Page 20 · Page c~0

5.2.

5. 1. 3.

..... Ty . ..... 5.

.pe
c~:.

I .

. . . .. 5. 10:>-. 2.

Lorlg Read Cc,mmands.
Restor'e · S e e k. · · · ·

arid

Write ··

· . . . · ....

· ....

Page 21
· Page 21 · Page 21
· Page 22

5. 3. 5. 4.

Type II C,:·rnmands ·· 5. 3. 1. Read Sect 1;)'1''''.

.. . .. . · ....

5 .. 3.2. Multiple Sectot" Reads ···

Type I I I CI:lmma Y'ld s ·····

· Page 22
·.. · Page .22 Page 24 ' · Page 24

5. 4. 1. 5. 4. 2.

Write Sect I:;'''''' ·· FClrmat T,,"'ack.·

· ....

·..... · Page 25 · Page 25

6. PROGRAMMING. ....................................·............. Page 27

6. 1.
. 6. ,--::-0
6.3.
5.4.

.. ·.... . . . . . . Sett irlg Up Task Fi lese

6. 1. 1. Type I
. 6 . .~ ::. 1.
. 6 · 2. :;. 1;;;..
. 3. 6 · :;. I.···

Cy 1 i rldet"s arId Track.s. Comrl1arld Pl''''cigramm i ng ··
Steppi rig Rates ·· Use elf B'Jsy Bit. Use of I nt e""l'''upt s ··

· ....

6. 2. 4. Use of the Err';)r Bi t ·.

....... 6.

.....
L-:' ·

~
.:J.

Use of the Cl::.rrected Bi t ··

Type II Commarld Prc,grammi ng ···

6. 3. 1. DMA MI:lde ····

6. 3. 2. Block Moves ··

6. 3. 3. Usi rIg DMA ···

6. 3. 4. Multiple Sectcll"" Tl""'ans fers.

6. 3. 5. Simulated Camp 1 £?t i e'YIS ··

Type I I I CC'fIlmarld P""'I:rg,."amm i ng ···

6. 4. 1. ForrnattiYlg ···········

·.... · · · · II ·

· Page 28

... ·.... .. .

· Page 28 · Page 28

· · · 110 ·

·· Page 29

· Page 29

......

·· Page 29
· Page 29 .Page 30

· Page 30

. . . . .

Page 30
Page 31

Page 31

·· Page 31

· Page 33

·· Page 33

· Page 34

HDC-2001 HARD DISK CONTROLLER Technical Manual

b.5.

6.4.2. Intet"leavi rig ·········.
Bad Bloc~. Mappirlg ...·········· 6.5.1. Sector Pre-allocation·· 6.5.2. Alternate Tracks. 6.5.3. Spare Sectors. 6.5.4. Bad Block Bit.

· Page 34
Page 35 · Page 35 · Page 36 · Page 36 · · Page 36

7. THEORY OF OPE RAT ION ··········· '·················

Page 38

7. 1. 7.2.
7.3.
7.4. 7.5. 7. 6.

General ···

Processor Functions.

7.2" 1. Fast 10 Select ··

7. 2. 2. Internal Bus Control.

7. 2.3. Reset Circuit ········

7. 2. 4. Processor Power Supply.

7" 2. 5. Read and Write Ports ··

7. 2. 6. Read/Write MeMory···· 7" 2. 7" Miscellaneous Control Ports·· Serial Oat a Separat ion···.······

7. 3. 1. IncoMing Data Selection··

7. 3. 2. Reference Clock···

7. 3. 3. CI,::.cK Gat ing .···

7. 3. 4. High Frequenc~ Detector.

7. 3. 5. Sample on Phase Detection··

7. 3. 6. Et"'t',::.t"' AMP 1 if i et".

7. 3. 7. veo.·.

7.3.S. Window Extension..

7. 3. 9. Cl.:.c~. Detect i.:.n ···.

Data Conversion and Checking ..

7.4.1. AM Detect ic'n.........

· ···.

7.4.2. Error Detection and Correction·.

7.4.3. Seri~l to Parallel Conversion.

Sel'"' i aiDa t _~ Genel'"'a t ion . . . . . . . . · . · . . . · .

7.5. 1. ~ilrallel to Serial Conversion.

7.5.2. CRC/ECC Generation··

7~5.3. MFM Generation . . .

Host Interface....·.

7.6.1. Wait Enable.

7.6.2. Bus Gating .·

7. 6. 3. Register Selection......··

7. 6. 4. Interrupts and DRQs ··

7. 6.5. Addl'''ess Select.

7.6.6.

Pl'"'C'M . . . . . . ·

· · Page 38 · ·· Page 38
· · Page 39 · Page 39 Page 40
· Page 40 · · Page 40
· Page 40 · · Page 41
· · " Page 42
· Page 42
· Page 43 · Page 43
Page 43 · Page 44 · Page 44 · Page 44 · · Page 45
Page 46
· · Page 46 · Page 46 · Page 47 · Page 48 · Page 49
··· Page 49
· Page 50 · Page 50 · ·· Page 52 · Page 52
Page 53
· · Page 53
· Page 53 · Page 53 · Page 54

8. MA I NTENANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 55

8. 1. 8. 2. 8.3.

DRUN Adjustments ...·· Oscillator Frequency. Balance Adjustment.

· Page 56
· · Page 56 Page 57

A. DISK DRIVER EXAMPLE .·....··..··..·········· ~ ······.··········. Page 59

A. 1. Polled Status Driver··. A.l.1. Initializatiorl.

. .' ..

Page 60
. .· PaQe 51

-01 HARD DISK CONTROLLER Technical Manual

A. 1. 2. Read Sector·· A. 1. 3. Write Sect.:.r··

................

... · · Page 62 · ·· Page 63

A. 1. 4. Task File Updating ··

· Page 64

. . . . .... . . . .. .... B. INTERLEAVE CALCULATING UTILITY··.

.. ..... .. · Page 65

................... B.. 1. BASIC Interleave Calculating Program.

Page 66

. . . . ... .. .. . . .......... . c;. SECTOR CALCULATING UTILITy·.·······

Page 67

....................... C. 1. BASIC Sector"s per Track Ut iIi ty.

· Page 68

. . . D. PROGRAMMERS QUICK . REFERENCE·.· ................. .. ........· Page 69

.D. 1.
D · : '~.
D.3. D. 4.

Task Fi 1e ·······
.... . Val id Cc.mrnands ··
SDH Register Format. Status ay,d Err'or Register Bits.

. . . . . . ....

· ·· Page 69 · Page 69
· ·· Page 70 · Page 70

OPERATING SYSTEMS·················

· Page 71

E. 1. Operating Systems Available.

Page 71

F. DRAW I NGS.....·.. ............................................. .Page 72

F. 1.

Schematic ···················
F. 1. 1. Microcontroller······ F. 1 · .c-:,:. Bus Iy,te .."'face/Dri ve Coy,trc.l ··
F. 1. 3. Data Separator········· F. 1.4. Se""'ial Data Iy,terface·· F. 1. 5. 8100 I Ylt er" face ·········

... · Page 72

· ·· Page 73
... · Page 74 ..... ···· Page 75

. . . . .

· ·· Page 76 · ·· Page 77

APJ:tE"'DIX . . . · . . P a g e 7 8 II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

G. 1. G.2. G.3.

8X300 CPU. ST506 ···.··
SA1000 or Q2000 Series··

·· Page 78
· Page 79 · Page 80

HDC-2001 HARD DISK CONTROLLER Technical Manuel

I~IBggY~I!gt::l

1. I N T ROD U C TID N

The HDC-2001 is an 8-100 bus Winchester Controller board with error
correction (ECC) capabilities. It is designed to interface up to four Winchester disk irives. There are two versions of the board, the HDC-10015/B. The HDC-2001-B can operate B" drive9. The HDC- 001-5 is used with most 5-1/4" dt"ives.

The dr"ive signals are based upon the floppy look-alike interface available

on the Shugart Associates' SA1000, the 8eagate Technology 8T506, and other

compatible drives.

All necessary buffers and receivers/drivers are

included on the board to allow direct connection to the drive. Four 20 pin

radial connectors are provided for data. Either a 34 pin (5-1/4" drive) or

a 50 pirl (B" dt"ive) connector is provided for drive control.

All data to be written to or read from the disk, status information, and macro COMmands are transferred via the 8-100 bus. An on board sector buffer allows data transfers to the host computer independent of the actual
data transfer rate of the drive.

*NOTE: Irl this marlLlal the 9-100 irlterface is called the "Host. II

HOC-2001 HARD DISK CONTROLLER Technical Manual

8-100 IEEE 696

Single BV Supply

Built-in Data Separator

Built-in Write Precompensation logic

Data rates up to 5 Mbits/sec

Control for up to 4 drives

Control for up to B R/W heads

* *

1024 cylinder addressing range 256- sector addressing range

CRC generation/verification

AutoMatic forMatting

128, 256, or 512 bytes per sector (User selectable)

UnliMited sector interleave capability

Multiple sector reads and writes

Overlap seek capability

Implied seek on all commands

AutoMatic retries on all errors

Automatic restore and re-seek on seek error

Error correction on data field errors

Diagnostic reads and writes for checking error correction

Power Consumption +5V @ 2.5 amps

HDC-2001 HARD DISK CONTROLLER Technical Manual

Encoding method: Cylinders per Head: Sectors per Track: Heads: 01" i ve Se 1 ect s : Step 1'''ate: Data Transfer Rate:
Write Precomp Time: eRC Polyrlomial: ECC Polyrlomial:
Reciprocal ECC Polynomial:
Miscorrection Probability:
Non-detection Probability: CO ..... l'..ect i .::arl Sparl: Sect '::at" i rIg: Host I Y'lt el'''face: Drive Capability: Drive Cable Length: Power Requirements: Ambient Operating Temperature: Relative Humidity: MTBF: MTTR: .

MFM
Up to 1024 Up to 256 (512 byte sec)
8
4 35 uS to 7.5 mS (0.5 mS increments)
4.34 Mbits/sec (SA1000) 5.000 Mbits/sec (ST506) 12 rlanoseconds X**16+X**12+X**5+1 X**32+X**28+X**26+X**19+X**17+X**10+ X**6+X**2+1 X**32+X**30+X**26+X**22+X**15+X**13+ X**6+X**:4+1 256 byte sector - (8.121 E-6 512 byte sector - <1.5 E-5
-2.3 E-10 5 bits S.::.ft
8 Bit bi-directional Bus 1121 LS Loads 10 ft. (3 M) max.
+8V, ,3.IZIA Max (2.5A typ.) OCto 50 C (32 F to 122 F)
2121" t '::. 80" 10,1210121 POH 30 minutes

HDC-2001 HARD DISK CONTROLLER Technical Manual

!~!BQQy~!!g~

S-100 BUS

r8.000 MHZ O .,
"
IQ2) CI'U.
D

I CONT~ 1

)-~ I ~

INST,I'C)tI.

; f
I

r O ""

CONTItQ4 I
SU""O"T LOCiIC

WQt1r»01

~ SV~"01fT SlGN"LS
r-e-- CONTI'O\. SIClHAU
I--t- Tt..NQ ~""LS

l!tnAN"&' IUS.

OI'IIVI CONTROl. LATCH

11
, I
· I
I

,.!.J ,
~ coo.T1'IO\. LATCH

...
0 S T
, · I ~
Co

OAT" LATCH

3
~ CAll. INTJIIQ. Wiil.
-

t12111
ISUlCT".O""

W(WOAY "00f\l.SS
~TlA

W011QG41

51"'''&'' .... ItALLlL ':01'1\1

'NOllQ04l
UlOIT

-- ~~lIU4.llL· c5o1"..".". " "'Oll'»-~

ICC'C1IC

CIN .c"'ICK,III

lIWOI'QG47

SIMPLIFIED SYSTEM BLOCK DIAGRAM - HDC- 001

r---
0
-"
" E
C
,0..
T'
~
---"l.

N011t»<11

r---

O"T .. S(Jt"""TOIIII

II
I
f ~

...,...
GENERATO"

I 0
I,~
"L

"'0' ,OI)'Z

HDC-2~01 HHRU DISK CONTROLLER Technical Manual
2. I N T E R F ACE CON NEe TOR S
The HDC~001 has SiK on board connectors. These connectors consist of a two drive control connector, and four high speed data connectors. The drive control cable is daisy-chained to each of the four drives. The dl'''ive data connectors carry differential signals and are radially connected. Up to four drives can be accommodated by the HDC- 001.

The Drive Control connector (J5 and J6) is a (relatively) low speed bus that is daisy chain connected to each of up to four drives in the system. To properly terminate each TTL level output signal from the HDC- 001, the last drive in the daisy chain should have a 220/330 ohm line termination resistor pack installed. All other drives should have no termination.
Drive Control Signals are as follows:

2. 2. 1. RWC-

When the Reduce Write Current line is activated with Write Gate, a lower write current is used to compensate for greater bit packing density on the inner cylinders.
The RWC- line is activated when the cylinder number is greater than or equal to four times the contents of the Wt'i t e Pt~c(:.mp Reg i st et....

2.2.2.

Write BateThis output
d i s k.·

signal allows dat~ to be written to the

2. 2. 3.

Seek Complete-
I Y"lf·:.t'rtls the HDC-2001 that the head of the selected dt"ive has reached the desired cylinder and has stabllized. Seek CC'fllplete is not checked a fter a SEEK
command, thus allowing overlapped seeks.

2. 2.4.

Traek 000-

Indicates that t"~ R/W heads are positioned on the ,:,utet'r.lost cyl iY"ldet~. This I iY"le is sampled imMediately before each step. is issued.

2. 2.5.

Write FaultInforms the HDC-2001 that ~1:lme faul t has occut~red on
the sleeted drive. The HDC-2001 will not execute commands

2.2.6. HS0-HS2-

Head Select lines are used by the HDC-2001 to select a speci fic R/W he,3d C''('I the selected dt'ive.

HDC-2001 HARD DISK CONTROLLER Technical Manual

2.2.7. Sector-
2.2. s. Index-

For hard sectored drives, this line is used to indicate the sector boundries during formatting. Note that this line is not used unless special PROMs are installed to handle hard sectored drives.
Is used to indicate the index point for synchronization during formatting and as a time out mechanism for retries. This signal should pulse once each rotation clf the disk.

2.2.9. Ready-

Informs the HDC-2001 that the desired drive is selected and that its motor is up to speed. The HDC- 001 will
not execute commands unless this line is true.

2.2. 10. 9tep-

This I iY'.e is pulsed I::'Y',ce for each cyl inder 'to be stepped. The direction of the step will be determined by the Direction In- line. The step pulse period is
determined by the internal stepping rate register during implied seek operations or explicitly during Seek and Restore commands. During auto restore, the step pulse period is determined by the Seek Complet~
time from the drive.

2. 2. 11.

Oi t"ect ion InDetermines the direction of motion of the R/W head when the step line is pulsed. A high on this line defines
the direction as out and a low defines direction as in.

2.2. 12. 091-094-

These four Drive Select lines are used to select one of four possible drives.

HDC-2001 HARD DISK CONTROLLER Technical Manual
2.2.13. Control Driver/Receiver The c':'Y'lt,,""::al lines have the f,:.l·lowiYlg electrical specificatioYls:
= Tt"'l_le= 0. III V to 0.4 V at lin 40 rna. (max.) = False= 2.5 V to 5.25 V at I in -0 fila. (,:.pen)
7

HDC-2001 HARD DISK CONTROLLER Te~hni~al Manual

2.2.14. S0 Pin Drive Control Conne~tor

This Drive Control Connector (J5) is a 50 pin vertical header on tenth-inch
centers that mates with Burndy *FRS50BS. The cable used should be flat ribbon cable or twisted pair with a length of less than 10 feet. The cable pin-outs are as follows:

+---------------------------------------------------------~---------+

Signal Ground

Signal Pin

I/O

Signal Name

+-----------------+--------------+-------+-~---------------~--------+

RWC-

Head Select 2-

Seek Complete-

140

Head Select 0-

Sector-

Head Select 1-

Index-

. I

Ready-

Dl'''ive Select 1-

Dl'~i ve Select 2-

Drive Select 3-

Dl'~i ve Select 4-

o i t~ect i .;:.n 1rl-

Step-

Wt~ i t e Gate-

TR000-

Wl'~i te Fault-

+--------4-9--------+--------5-0-----+-------+---N-C----------------------+

HDC-2001 HRRD DISK CONTROLLER Technical Manual

2.2.15. 34 Pin Drive Control Connector

This Drive Control connector (JG) is a 34 pin vertical header on tenth-inch
centers that mates with Burndy #FRS34BS. The cable used should be flat ribbon cable or twisted pair with a length of less than 10 feet. The cable pin-outs are as follows:

+------------------------------------------------------------------+

I Signal Ground

Signal Pin

1\0

Signal Name

+-----------------+--------------+-------+-------------------------+

a I RWC-

Head Select 2-

Write Gate-

Seek Complete-

TR000-

Write Fault-

Head Select 0-

Sector-

Head Select 1-

Index-

Ready-

Step-

Drive Select 1-

Drive Select 2-

Drive Select 3-

Drive Select 4-

Direction In-

+-----------------+--------------+-------+-------------------------+

The Drive Data Connectors carry the high speed differential MFM data between the drive and the HDC-2001. Due to the loading characteristics of these differential lines, each of the drives have their own data connector. Drive Data Signals are as follows:

2.3.1. Drive SelectedThis signal is not used on the HDC-1001.

2.3.2.

Timing Clock+ One half of the differential Timing Clock signal. This line contains a square wave signal equal to 1/64 the
frequency of the write clock crystal.

2.3.3. Timing ClockThis is the compliMentary version of Timing Clock+.

2.3.4. MFM Write Data+Differential MFM data from the controller to the disk.

HDC-2001 HARD DISK CONTROLLER Technical Manual

2.3.5. MFM Read Data+-
Differential MFM data froM the disk to the controller.
2.3.6. Drive Data Connectors
Four Data connectors (Jl~4) are provided for clock signals and data between the HDC-2001 and each drive. All lines associated with the transfer of data between the drive and the HDC~001 system are differential in nature and May not be Multiplexed. The Data connectors are 20 pin vertical headers on tenth-inch centers that mate with Burndy #FRS20BS. The cable used should be flat ribbon cable or twisted pair with a length of less than 10 feet. The cable pin-outs are as follows:

+-----------------+--------------+-------+--------------------------+
I Signal Ground I Signal Pin I 1/0 I Signal Name

+-----------------+--------------+--~----+--------------------------+

I I Dr i ve Se 1ect ed

I NC

I I Write Pl'''otect-

I NC

0 I : Timing Clock+

Timil"lg Cl':'ck-

GND

MFM Wl'"'ite Data+

MFfYl Wl'''ite Data-

GND

MFM Read Data+

MFM Read Data-

GND

.+--------2-0--------+--------------+-------+--G-N-D----------------------+

2.3.7. Differential Data Driver/Receiver

HIGH _ ..... TRUe
AMD 26LS31
or 75110A
NOTE: ANY AS 422 ORIVERJRECEIVER PAIR WILL INTERFACE

">-_._ HIGH
TRUE
- AMD 26LS32
FLAT RIBBON OR TWISTED PAIR
MAX 10 FT.
10

HDC-2001 HARD DISK CONTROLLER Tachnical Manual

3. I N T E R F ACE TIM I N a

+------------------------------------------------------- -----------+

SYMBOL

CHARACTERISTIC

MIN' MAX

JNITS

+------------------------------------------------------ -----------+

twa

Write gate pulse width 1 sector 2 rot3~lon

tDS

Direction to step delay

250

tSW

Step pulse width

5 (typical'

tSP

Programmed Step pulse period 0.01 7.5

tSS

Step to Seek Complete false

tSC

Last Step to seek Complete

128

Index

+----------------------------------------_._------------------t-im --e-s---+

Notes:

1. Write gate pulse width will vary depending on the sector size and the rotation rate of the disk.

2. Step pulse period will be equal to seek complete time during au. t"est.::.re.

x::: -DRSE~HOSEL:x______~______________~_____________

- AWe 1/11/11;71111 VALID ~)!IlI/I/UZ!lZllZZZZZlZIZI/I I ,' - t W G - - - ' "
-WRITE GATE

, 1

tDS-:

- DIRECTION 1jj?!@liZiZi]
I

1 _ . _1_ _- tSP

~---~J j~---
.,

-STEP---,--------I---~'ItSW~!I- ------------~~~J

!
tSS--' I-
I
- SEEK COMPLETE - - - - - - - - - -....

1 ·

L tSC ----4 jJ

HDC-2001 HARD DISK CONTROLLER Technical Manual

. 1~I~BE8g~ !l~l~§

+-------------------------------------------------------------------+

+I --S-Y-M-B-O-L-------C-H-A--R-A-C-T-E-R-I-S-T-IC-------------M-I-N--------M-A-X-------U-N--IT-S----+I

tTC

Timing clock period

WCLK/16 (typical)

tWD

Write data pulse width 60

120

+--tR--D----------R-e-a-d--d-a--ta--p--u-l-se---w-i-d-th------2-5------------------n-S-------+

ClOC~ + TIMING

:.... tTC-of

- TIMING CLOC~..._ ...

+ MFM WRITE DATJ

- II

~ tWO
I

-MFM WRITE DATl__

I.'..._ _I

+MFM READ DATJ

---,I

- MFM READ DATA

,
~ tRD
I

4. T ASK F I L E
The HDC-2001 performs all disk functions through a set of registers ca.lled the Task File. These register are loaded with parameters such as Secto~ Number, Cylinder Number, etc., prior to issuing a command. Individual t~egisters are selected via A0-2. The following registers are available.

+------------------------------------------------------------------------+

+I -C-S----I--A-2--I--A-1--I--A-0---I --R--E------------------------W-E------------------------+

I 1 I X I X I X I Deselected

I Deselected

01 0 I 0

Data Register

0 I0 I1

Error Register

Write Precomp

0 I1 I0

Sector Count

o 0

Sector Number

Cylinder Low

Cylinder High

Si%e/Drive/Head

Size/Drive/Head

+--o-----1-----1-----1------S--ta--tu--s--R-e-g-i-s-t-e-r----------C-o-m-m-a-n-d--R--e-g-i-s-te-r---------+

4.3.1.

Command Register All commands are loaded into this register after the
task reg'isters have been set. Writing to this register will cause the INTRQ Line to be reset. The COMmand register is a write-only register.

4.3.2.

Status Register After execution of a COMMand, the Status register is internally loaded with status information pertaining to the command executed. The host Must read this register to deterMine successful execution of the COMMand. The Status register is a read-only register; it cannot be written to by the host. If the busy bit is set, no
other bits in this regist~r are valid. Accessing this register will cause the INTRQ line to be reset.

4.3.3.

SOH Register
This register contains the ECC Mode, sector Size, Drive select, and Head select bits. The SDH.register is a

HDC-2001 HARD DISK CONTROLLER Technical Manual

·!8§~ E!bE

read/write register organized as ~ollows:

+------------------------------+ +1 -7--1--6---5----I -4----3---I--2---1--·-0--+
lEI Sec I Drive I Head I
+---1---S-i-z-e---1-S--e-l-e-c-t-!---S-e-l-e-c-t--+
E=O eRC in data field E=l ECC in data field

+---------------------------------+

Bit

Sector Size

+-----------------------------~---+

256 Bytes

512 Bytes

12S Bytes

+---------------------------------+

+--------------------------------+

Bit

Drive Selected

+---4-------3----------------------+

Drive Sel 1

Drive Sel 2

Drive Sel 3

+---1-------1-------D-t-"i-v-e--S-e-l--4-----+

+--------------------------------------------+

Bit

Head Selected

+-----2-------1-------0-------------------------+

Head 0

Head 1

Head 2

Head 3

Head 4

Head 5

Head 6

+-----1-------1--------1 ----------H-e-a-d--7---------+

4.3.4.

Cylinder Number These two read/write registers form the cylinder number where the head is to bL positioned on a Seek, Read,
Write, or Format command. Internally, a separate set of cylinder register values are maintained for each drive. The two least significant bits of the Cylinder
High register form the most significant bits of the cylinder number as illustrated below:

Registet" bits: Cy I i rid et" bit s :

g~!inQ§r: t:!iab
17J61514/3121110~
I 1 1 1 19151

g~!ing§r: bQ~
17161514131211101 17161514131211101

4. 3. 5.

Sector number

This register is loaded with the desired sector number

Pl""' i Cit" to a Read or Write command.

The Sector Number

4.3.6.

Sector Count This read/write register is loaded with the number of sectors to be processed. On Read or Write multiple
commands, the number of sectors to be transferred is loaded into this register. During a Fo~mat command, this register is loaded with the number of sectors to
be formatted. During the course of a command, the Sector Count register is decremented towards zero and should be re-loaded for each command.

4.3.7.

Error Register This register contains specific fault information pertaining to the last command executed. This register is valid only if the Error bit in the Status register is set. The Error register is read only.

4.3.8.

Write Precomp The Write Precompensation register holds the cylinder number where the RWC line will be asserted and Write Precompensation logic is to be turned on. This wrlteonly register is loaded with the cylinder number divided-by-4 to achieve a range of 1024 cylinders. For example, if write precompensation is desired for cylinder 128 (80 Hex) and higher, this register must be loaded with 32 (20 Hex). The Write Precompensation delay is fixed at 12 nanoseconds from nominal. On drives that require separate write precompensation anrl reduce write current cylinders, set the Write Precomp
register to the cylinder where write current reduction is desired.

4.3.9.

Data Register This register is the user's window to the on-board full
sector buffer. It contains the next byte of data to be written to or read from the internal sector buffer. The Data register is accessed once for each byte in the sector. When the DRQ (Data ReQuest) line is asserted, the sector buffer contains data in a read command, or is awaiting data to be written during a write command
into the Data register. If the HDC- 001 is interfaced using programmed I/O, data transfers to this register can be implemented using block moves. This register may not be read from or written to except in the conte~" of a valid command.

HOC-2001 HARD DISK CONTROLLER Technical Manual

I8§~ E!b~

There are two registers in the HDC-2001 that are used to Monitor the execution
of commands. They are the Status register and the Error register. Each bit of these registers is used to define a particular type of status or error condition.

+--~------------------------------------------------------------+

I Bit

Status Register

Error Register

+-------+-------------------------+----------~-~----------------+

Busy

Bad Block Detect

I 6

Ready

Uncorre~table

I 5 :'

o I

Write Fault Seek Complete Data Request Corrected
Error

CRe Ert"or - IU Field

10 Not ~ound

Aborted Command

TR000 Error

DAM Not Found

+---------------------------------~-----------------------------+

4.5.1. Error

When set, indicates that a bit is set in the Error register. It provides an efficient means of checking for an error condition by the host. This bit is reset
on receipt of a new COMmand.

4. 5. 2. Corrected

Indicates that there was a read error condition either in the data field or the ECC check bits themselves, and
that the controller was able to correct the condition.

4. 5. 3.

Data Request Functions almost identically to the hardware DRQ ~ine. When set, it indicates that the sector buffer is ready to accept data or contains data to be read out by the host. The Data Request bit is reset when the sector buffer has been fully read from or written to.
Normally, the host need not consult this bit to determine if a byte should be transferred.

4. 5. 4.

Seek C':lmplete Indicates the condition of the Seek Complete line on
the selected drive.

4. 5. 5. Write Fault Indicates the conjition of the Write Fault line on a

HDC-l001 HARD DISK CONTROLLER Technical Manual

4.5.6.
4.5.7. Busy

selected drive. The HDC-2001 will not execute any command if this bit is sat.
Indicates the condition of th~ Ready line of the selected drive. The HDC-2001 will not execute any commands unless this bit is set.
After issuing a command, this bit will be set, indicating that the HDC-2001 is busy executing a command. No other bits or registers are valid when this bit is set.

4.6.1.

DAM Not Found Will be set during a Read Sector command if, after
successfully identifying the ID field, the Data Address mark was not detected within 16 bytes of ID field.

4.6.2.

TR000 Error Will be set during a ,Restore command if,
1024 stepping pulses, the Track 000 asserted by the drive.

after issuing line was not

4.6.3.

Aborted Command Indicates that a valid command has been received that
cannot be executed, based on status information from the drive. For example, if a write sector command has been issued while the Write Fault line is set, the
Aborted Command bit will be set. Interrogation of the Status and/or Error registers by the host can be performed to determine the cause of failure.

4.6.4.

ID Not Found When set, this bit indicates that an ID field containing a specified cylinder, head, sector number or sector size was not found.

4.6.5. CRC Error ID Indicates that a eRC error was encountered in an 10
field.

HDC-2001 HARD DISK CONTROLLER T.ch~ical Manual

I8§~ ElbE

4.6.6.

Uncorractable
Indicates that an error was detected while reading the data field or ECC check bits and the error was so severe that the controller was not able to correct the condition.

4.6.7.

Bad Block Detect Indicates that a Bad Block Mark has been detected in the specified 10 field. If the command issued was a
write sector command, no writing will be performed. If generated from a read sector command, the data field will not be read. Note that bad block will not be detected if the flaw is in the 10 field unless Multiple ID fields were written.

HDC-2001 HARD DISK CONTROLLER Technical Manual
3. COM MAN D S
The HDC-2001 executes five easy to use macro commands. Most commands feature automatic 'implied' seek, which means the host system need not tell the HDC-2001 where the R/W heads of each drive are or when to move them. The controller automatically performs all needed retries on all errors encountered including data field e~rors. If the data field contains an error, the controller will perform a correction, if possible. If the R/W head mispositions, the HDC-2001 will automatically perform a restore and a re-seek. If the error is completely unrecoverable, the HDC-2001 will simulate a normal completion to simplify the host system's software. Commands are executed by loading a command byte into the Command ~egister while the controller is not busy. (Controller will not be busy if it has completed the previous command.> The task file must be loaded prior to issuing a command. No command will execute if the Seek Complete or Ready lines are false or if the Write Fault line is true. Normally it is not necessary to poll these signals before issuing a cOMmand. If the HDC-2001 receives a command that is not defined in the following table, undefined results will occur.
19

HDC-2001 HARD DISK CONTROLLER Technical Manual

~~!~ ~gmm~ng EYmm~~~
For ease of discussion, commands are divided into three types which are
summarized in the following table:

+------------------------------------------B-I-T-S-------------+,
+--T-Y-P-E---+--CO-M--M-A-N-D---------+--7----6----5 ---4 ---3 ------2----1----o-+1

1--I------+--R-e-s-t-o-r-e---------+--0----0----0---1-----r3----r-2---r-l---r-0+1

, I·

'Seek

, 0 1 1 1 r3 t"2 r 1 r0 ,

I--------+-----------------+--------------~----------------+

1I --I-I-----1+--R-e-a-d--S-e-c-t-o-r-----+'0 ------0----1---0-----D----M----L----0-+I

1I --I-I--I ---+1---W_,,"'0i_t-e--S-e-c-t-o-r----+, --0----0----1---1 ---0 ---M -------L----0-+I

1 III I Format Track I 0 1 0 1 0 0 0 0 I
+----------------------------------------------------------+

L=Long Read/Write M=Multiple Sector

D=DMA Read Interrupt rX=Stepping Rate

5.1.1.

Stepping+-R-a-t-e-s-----------------------------------------+

11 ---0-0-0-0--=--3-5-r-3u-S--r-0---- --S-t-e+p1p-i-n-g--1R-0-0a-0t-e-=--4-.-0--m-S-----+1I

1 0001 =0.5 mS
= 0010 1.0 mS
0011 = 1.5 mS 0100 = 2.0 mS

' 1 0 0 1 = 4.5 mS

= ' 1 0 1 0 5.0 mS

1011 = 5.5 mS

' 1 1 0 0 = 6.0 mS

0101 = 2.5 mS

1101 = 6.5 mS

0110 = 3.0 mS

1110 = 7.0 mS

+---0-1-1-1--=--3--.5--M--S-------+-----1-1-1-1--=--7-.-5--m-S-----+

5.1.2. DMA Read

Q - Q~8 B~2Q ~Qg§
o = Programmed I/O Mode
1 - DMA MClde
The DMA bit is used to position INTRQ in relation to DRQs during the read sector command. If the DMA bit is reset (0=0), the interrupt will occur before the first DRQ. This allows the programmed I/O host to intervene and transfer the data from the sector buffer. If the DMA bit is set (0=1), then the interrupt will occur only after th~ system DMA controller has transferred the entire buffer of data.

HDC-2001 HARD DISK CONTROLLER Technical Manual
s. 1. 3. Long Read and Write
If the Long bit is set, a special diagnostic read or write will be performed. During normal reads or writes, the ECC check bytes are not visible to the user. The Long bit allows the user to read and write these normally invisible bytes.
During a Read Long, the HDC-2001 will return a sector that is four bytes longer than the selected sector size. These four bytes will be the ECC check bits as recorded on the disk. During a Write Long, the host give the HDC-2001 a sector that is four bytes longer than normal. These four extra bytes are recorded in place 1:lf the ECC bytes that are nor"mally wt"itten aftel''' each sector.
The Read and Write Long option may only be used when the HDC-·2001 is in ECC mod9.

These commands simply positlon the R/W heads of the selected drive.

Both

COMmands have expliCIt stepping rate fields. The lower four bits of these

commands form the stepping rate which 15 stored for later Read, Write or

format operations.

5. 2. 1. Restore

The Restore command is used to calibrate the pcsition of the R/W head on

each drive by stepping the head outward untll the TR000 line goes true.

Upon receipt of the Restore command, the Busy bit in the Sta~us Register is

set. Cy 1 i ndet.. High arid Cy 1 i rider" LI:JW l'''eg i st ers at"'e cleared.

The lowet'

four bits of the command byte are stored in the stepping rate register for

subsequent implied seeks. The state of Seek Complete, Ready and Wrlte

Fault are sampled, and if an error condition exists, the Aborted COMMand

bit in the Error register is set, the Error bit in the Status register is

set, an intet""t"upt is gerler"'ated, arid the Busy bit is t""eset.

If no errors are encountered thus far, the internal head position register

for the selected drive is cleared. The TR000 line is sampled. If TR000 is

true, an interrupt is generated and the 8u~y bit is reset. If TR000 is not

true, stepping pulses at a rate determined by the stepping rate field are

issued until the TR000 line is activated. When TR000 is activated, the

BllSY bit is t"'eset and an irltet"r"'upt is issued.

If the TR000 1 ine is nClt

activated within 1024 stepping pulses, the TR000 Error bit in the Error

reset, and an interrupt is issued.

HDC-2001 H~RD DISK CONTROLLER Technical Manu.l
s. 2.2. Seek
The Seek command positions the R/W head to a certain cylinder. It is pt"imari ly used to-~>start two or more coY'tc1Jrt"'ent seeks on drlves that support buffered stepping: Upon receipt of the Seek eommand, the Busy bit in the Status Register is set. The lower four bits of the command byte are stored in the stepping rate register for subsequent implied seeks. T~e state of Seek complete, Ready and Write Fault are sampled, and if an error condition exists, the Aborted command bit in the Error registe~ 1S set, the Error bit in the Status register is set, an interrupt i9 gene~atPd, and the Busy bit is ,,"eset.
If no errors are encountered thus far, the lnternal head position register for the selected drive is updated, the dlrection llre 1S set to the proper direction and a step pulse is issued for each cyllnder to be stepped. When all stepping pulses have been lssued, the 9usy blt is reset and an interrupt is Issued. Note that the Seek Complete line is not sampled after the Seek command, allowing multiple seek operatl0ns to be started using drives with buffered seek capability.

This type clf cClll1mand is chat"acterlzed by a tt'ansrer OT- a blOcK or data rt"(.Iht

the HDC-2001 buf~er t~ the host.

~hlS commana has an lmplicit stepping

rate as se~ ~y the las~ Mestore or Seek ccmmanu.

5. 3. 1. Read Sector

The Read Sectct- r.:-':·:-1m~rld is used t,~ "r'ead a :;)ector of data ft"'om the disk to

the host C·:tfnOI.l1:e,"".

UFt::'Y, ';"ece1Dl; of t.he Reao c!:::rMnano" the Busy bit in the

S-: at I.i= l''''eg 1 st e~- 1 s '~et. The s't at e c· f Seek Corro 1 e-r-: e, Ready and W""i t e F au 1 t

ar"'e sampied, and l'f an et"t"'or cl:)ndltlon eXlsts. ;···,e Aborted CC,Imrnand bit In

the Error reglster is set, the Error blt 1n tre Status register is set~ and

a normal completion is slmulated.

Inlp 1 i ed Seek
If no errors are encountered so far, a Seek command is executed. The S~ek Complete line is sampled. If the Seek Complete line does not go true within 128 Index pulses, then the Aborted cOMmand bit in the Error register is set, the Error bit in the Status register is set. and a normal completion is simulated.

Retries

Once the head has settled over the desired cylinder, the HDC-2001 will

attempt to read thE sector. The ~DC-2001 ~erforms all rett"'les necessary to

l''''eCClVer the cata dUl'"'ing the t"'ead CClfflrnano. The controller attempt45

t"ead t re des It''ed sect I:""" I.lp t I) t 5 times. It will at tempt a Y's:t t"Y if 1 t

,-:'~

HDC-2001 HARD DISK CONTROLLER Technical Manual
not find an 10, if the 10 of that sector has a bad CRC, 1f the Data Address Mark (DAM) couldn't be found, or even i¥ the data was actually read from the disk but was in error.
El''''r''or COl'"'rect ion
If an error was detected while readinQ the data field, the controller will attempt to correct the error, If the error was correctable, ·the Corrected bit in the status register will be set and the command resumed. :f it was uncorrectable, the Uncorrectable Error bit will be set, the Error bit tn the Status register is set, and a normal completion is SImulated.

Every time the cl;:)Yltl'''ollel''' erlC=ounters 'an error, 1 t l'"'ecol'''ds the OCCUl'''l'''enC'e cof that error in an internal register. If. after 16 retries~ the controllRr was not able to get a match on the ID field, It assumes that the head was possibly mis-positioned and executes an auto-restore. During the autorestore, the stepping rate is lmplied to oe equal to the See~ Complete period. If the TRK000 does not go true withln 1024 steps, ehe TRK000 Err~r bit in the Error register is set, the Error bi~ 1n the Status regIster is set and a normal completion is simulated.
After the auto-restore has been successfully comple~ed, the controller reseeks and attempts to read the sector once again. An auto-restore wlll be performed only once per read or write sector ccmmand.

Hat"d Et"'l'"'()""s

If the controller encounters a non-recoverable error. the controller

examines its internal error history register. It then sets the bit in tM~

Error Register of the highest severlty error inc ,rred.

If the

Uncorrectable bit is set, the data that last produced that error will be

avai I abl e in 'the sect at'" buffer. The Er"'ror bl t i r. t he Stat us Ree i ster 1. s

set and a normal completion is simulated.

HDC-2001 HARD DISK CONTROLLER Teehnieal Manual

Error Severity Levels
Although the HDC-~001 might encounter any number of errors in the course of executing a command, it only reports the most severe error. Errors ~re ranked from most severe to least severe as follows.

1. Aborted Command 2. TR000 Error 3. Bad Block* ~ Uncorrectable 5. Data Address Mark Not Found 6. ID CRe Error 7. ID Not Found

Bad Block will only be detected if there is no ID CRC Error or ID Not

Found Error in the sector with the Bad Block bit set.

Normal Completion
If the HDC-2001 encountered no errors, it is considered a normal completion. The busy bit is reset. The status of the DMA bit in the command byte is examined. If this bit is reset (D=O; programmed I/O Mode) then an interrupt is issued at this time. DRQs are then generated for each byte to be read from the buffer. (Note: It is recommended that programmed I/O transfers should take place as a block move without consulting the DRQ bit in the Status Register.) After all the data has been moved from the buffer, the DMA bit in the command byte is consulted again. If this bit lS set (D=l; DMA mode) then an interrupt will be issued.

5.3.2. Multiple Sector Reads
If the M bit in the command byte is set, the~ th~ HDC-2001 WIll attempt to read multiple sectors. After all th~ data has been transferred from the sector buffer to the host on a read, tne Sector Number register is incremented, the Sector Count register is decremented, and if the Sector Count reaches zero or if a fatal error is encountgred, the HDC- 001 will stop and interrupt the host.
, When a Correctable error is encountered during a multlple sector read, the occurance of the error is logged, but no interrupts are generated. After the whole multiple transfer is complete, the host can read the Corrected bit of the Status register to determine if any automatic corrections have taken place.

This type of command is characterized by a tr~nsfer of a block of data from the host to the HDC- 001 bufferr These command~ have lmplicit stepping ratee AS set by the last Restore or Seek command.
24

HDC-2001 HARD DISK CONTROLLER TechnicAl Manual
3. 4. 1. Write Sector
The Write Sector command is used to write a sector of data from the host computer to the disk. Upon receipt of the Write command, the controller generates DRQs for each byte to be written to the buffer. (Notel It is l'''ecommended that pl'''ogrammed 1/0 transfers should take place'.as a block move without consulting the DRQ bit in the Status register.)
After all data has been sent to the sector buffer, the Busy bit in the Status register is set. The state of Seek Complete, Ready and Write Fault are sampled, and if an error condition exists, the Aborted Command bit in the Error register is set, the Error bit in the Status register is set, an interrupt is generated and the Busy bit is reset.
Retries
Once the head has settled over the desired cylinder, it will attempt to read the 10 of the sector. The HOC-2001.performs all retries necessary to recover the Id during the write command. The controller attempts to read the 10 of the desired sector up to 16 times. It will attempt a retry if it d~esn't find an 10 or if the ID of that sector has a bad CRe.
Aut.:;) Restore
Every tiMe the controller encounters an error, it records the occurrence of that error in an internal register. If, after 16 retries, the controller was not able to get a·match on the ID field, it assumes that the head was possibly mis-positioned and executes an auto-restore. During the autorestore, the stepping rate is implied to be equal to the Seek Complete period. After the auto-restore has been successf~lly completed, the controller re-seeks and attempts to Write the sector once again.
If the controller encounters a non-recoverable error, the controller examines its internal error history register. It then sets the bit in the Error register of t~e highest severity error incurred. The Error bit in the Status register is set, an interrupt is generated and the Busy bit is \'''eset.
If the proper sector is located, the sector buffer is written to the disk, an interrupt is generated and the Busy bit is reset~
cr ··· 2 . . Format Track
Format Command is used for initializing the 10 and data fields on a
25

particular disk. Upon receipt of the Format command, the controller

generates DRQs for each byte of the interleave t~ble to be written to the

buffer.

Information on settinq up an interleave table c~n be f~urd in

Section 7.

In all cases, the number 0"': t-f~e9 " rpil ..... ~ .... erl'·l!!d tl-) t:,e ;_~I.. ffeY'

must correspond to the curY'ent sector size.

AfteY' all data has been set to the buffer, the Busy bl~ in t~~ Statue

l'''egister is set.

The 48tate of Seek Complet~, Ready ::.. r~::l Wt"'i.i;~ F:u.;l'.: : :y,es

are sampled. If an error condition exists, the AboY'ted Command bl~ ~ the

Err,:,}''' register is set, the Error bit in the Status l"eqlster is S2t~ an

int~rrupt is generated and the Busy bit is rese~.

Implied Seek.

If no errors are encountered so far, a Seek command is executed. \10

verification of track. positioning accuracy lS performed because the t ck

May not have any ID fields present. After the Seek oper~~ion has
performed, the Seek. Complete line is samplec. If the Seek C~Mpl~t~

, - t:~erl : ....

is not asserted within 128 Index pulses, the Aborted Command bit in t.he Error register is set, the Error bit 1n ~~e Status register is set, ~n
interrupt is generated and the Busy blt is reset.

Once the head has settled over the deSIred cylinder, the controller walts urltil the Index line is asserted. Jrlee 1;he Index i~ f·"',uy,d · .:a Yllirniler r:lf TI') fields and nulled data fields are wr1tten to the disk. The number of sectors written 1~ equal ~0 ~~e c~n~en~s of the Sector Cwun~ leqlst~r. ~~
-E'ach sectol"~ is wt"'ltten tl1e Sec'tl:'t"' C' ......,nt .Reglstet"' !.s ~.ec:,rement~r"', ~",tj
:cnsequently, must be ~~ca1;ed before each format operation.

After the last sector l~ written, the con~roller back-fills the track With

4E's.

When the next lndex pulse after the last sector 1S wrlt~en IS

encountered, the format operation is terminated, an i~t~rruct is gererated

and the Busy bit is reset.

The

,FCIl'''rnat command fOt"rnats the track Hsing the f'Jllowir,g fc..t-'rnat: , . . - - - - - - - - - - - - - - - - - - - ;:;EPEATEON TI~es - - - - - - - - - - - - - -

7 .

111

I G:P

GAP3

I t I.e)

(.-e)

, -;. r 1,-___ ----'t . L- " ,

14 BYTES (00)

! (At) loeNT CYl. l.OW

SEC

CRC 3B:·B~'2TES
-2- (001; (00)

IAt)

iF9'

b i , ..
F,.l,'.;-LrAO

(

RCi21
'~"'A II

BYTeS ·OO)! !

jEC041

10 FIELD _ _

OATAFIELO..-l

H ,--- 200 nS. MIN. I.NOeX PUl.Se

WRIT£ GAT£ - - - - - ' "

NOTE:
1) When MSa of SH t:7tte - 1. bad blOCk is detected.
2) Write Gate tum-on is 3 bytes after the to fiekj's CRe t1tte.
3) Write Gate tum-otf Is 3 bytes after tna Data
Fl!kfs check bytM. 4) , 2 t1ttes of zeroes are re-written on a Data Field
update.

5)
26

The 2 LSS's Of the 'CE~n :~I!~ ;tf'" !J~;~ 'r;
:ylinder high.
These values are:
FE O!() 255 '-,-1ir'r!'!rs
FF - 256 to 511 '=-(lIf'lCef'5 ::'C - 5~2 ~o i67 r:",.hnder.s
cD- 'r;"', 'a "23 c-llir'lC'1en

HDC-2001 HARD DISK CONTROLLER Technical Manual
6. PRO a RAM MIN B
Users familiar with floppy disk systems wIll find programming the HDC-2001 a pleasant surprise. A substantial amount of lntelligence that was required by the host computer has been incorporated Into the HDC-2001. The HDC- 001 pe,,"forn1s all needed retries, even on head posi t ionL-.g s,"rors. ~ f there is an error in the data field~ the HDC-2001 will attempt to correct it. Most commands feature automatic 'implt~d' seek whi~h means that seek commands need not be issued to perform basic read/write functions. The HDC-2001 keeps track of the position of up to four reac/wY'lte head assemblies, so the host system does not have to maintain track tables. All transfers to and from the disk are through an on-board fulL sector cuffer. This means that data transfers are fully interruptable and can take place at a~y speed that is convenient to the system designer. In the event of an unrecoverable error~ the HDC~001 simulates a normal completion so that special el ......';:)1'.. 1'''ecovery softwa,,"e is Y"IOt needed. This secticn assumes that the user has read sections five (Task File) and six (Commancs).
27

HDC-Z'001 HARD DISK CONTROLLER Technical Manual

Before any of the five commands may be executed, a set of parameter registers called the Task File must be set up. For most commands, this informs the HDC~001 of the exact location on the disk that the transfer should take place. For a normal read or write sector operatlon, the Sector Number, the Size/Drive/Head, Cylinder Number and Command register (usually in that order) will be written.
Note that most of these registers are readable as well as writable. These registers normally are not read frOM, but this feature is provided so that error reporting routines can determine physically where an error occu,,"red without recalculating the sector, head and cylinder parameters.
Since the HDC-2001 can recall all the Task File parameters sent to It,' it is recommended that Task Fi Ie parameters be st.::.,,"ed in the HDC-.2001 as :they are calculated. This will save the programmer a few instructions and microseconds by not maintaining two copies of the same information.

6. 1. 1. Cylinders and Tracks

Since most hard disk drives contain more than one head per positioner, it
is more efficient to step the R/W head assemblies of most disk drives by cylinders, not tracks. In other words, the disk driver software should be design~d to read or write all data that is directly accessible by all the heads 'on a positioner before stepplng to a new cylinder. The following example illustrates a cylinder-by-cylinder sequential file read on a four head, two platter disk drive:

+------------------------------------------------------+

Physical

L':lgical

I PhyS tc.:ll I Physical

Cy I i rlde,.~

Head N llrn bel'"'

He~ Side I Plat t e,,"

+----------,--+.__._------------+----_... _..._---....-_..:..:_--------...

T~p

Bottom I

Top

Bottom

Top

Bottom

+------------------------------------------------------+

·Restore and Seek are Type I commands. These commands position the R/W heads of the selected drlve ane set the lmplied stepPing rate register. No dat a is t t"ansferl"ed t: c· Ol'" f"t'om the Pa.t a Reg i ster. T::. exeCI_lt e a Type I command, the syste~ software m~gt d~ the following functions in this order:
28

HDC-2001 HARD DISK CONTROLLER Technical Manual

(HDC-2001 will attempt to execute Type I command) 2. Wait for interrupt or for Busy bit in Status Register to be reset 3. Check Error bit in Status Register for proper completion.

6. 2. 1. Stepping Rates
Most drives that use the HDC~001's 35 uS stepping rate require a slower rate (usually 3 mS or more) for Restore operations. This is why the HDC2001 allows you to have explicit stepping rates on both Restore and Seek. Upon power up, it is good practice to issue a Restore command with a slower stepping rate to recalibrate the head assembly. After waiting for that operation to COMplete, issue a Seek command with the faster stepping rate to set the stepping rate for subsequent implied seeks.

6. 2.2. Use of Busy bit

There are two different ways to sense the completion of a command. The first way, for smaller single user systems, is to poll the Busy bit of the Status Register. The Bus bit (bit 7) is set whenever the controller starts a disk operation and is reset whenever the controller is ready to communicate with the host COMputer.

The HDC-2001 busy bit is located in the same place a the sign bit of many computers to simplify the polling process.

This is one way to poll this bit using 8080 code:

WAIT:

IN STATUS ANA A JM 'WAIT

;Input HDC-2001, update sign flag
;Update 8080 sign flag ;Wait if busy (sign) bit set

6.2. 3. Use of Interrupts
Another more efficient way of notifying the CPU that the HDC~001 has completed a command is through interrupts. The INTRQ line on the HDC~001 makes a low to high transition whenever the disk controller requires CPU intervention. This allows the host CPU to run other tasks while the HDC2001 is reading or writing data to the disk.

6. 2. 4. Use of the Error bit
Since the HDC-2001 simUlates normal COMpletions, it acts the saMe whether or not errors are encountered. The only way to check error status is to check the Er"'\'"'or" bit in the status register. The HDC-2001 Err"'o\''' bit is located so that it can be easily tested by rotating it into the carry bit of Many processors. The conte~ts of the Error register are not valid unless the Error bit is set.

HDC-Z001 HARD DISK CONTROLLER T.chnicAl Manual

This is one way to check the Error bit using 8080 code:

IN STATUS
RAR JC ERROR

;Get status <if not already in A) ;Rotate error bit into C ;Jump 1f error found

6.2. s. Use of the Corrected bit

Correctable errors are usually quite benign and can almost always be
ignored. However, some systems designers may wish to log their occurence. The Corrected bit is positioned in the Status register to facilitate error l.::;.g,*ng. Cot"rectable and fatal el'''rors can be detected with the following 8080 code:

IN STATUS ANI 5 JNZ SOMERR

;Get HDC-2001 status ;Mask off Error and Correct bits ;Jump if we have either a correct;able or fatal error

The Read Sector command is the only Type II command. This command is
characterized by the transfer of a block of data from the HDC-2001 buffer
to the host. This command features implied seek with an implicit stepping
rate. To execute a Type II single sector command in programmed I/O mode,
the system software must do the following functions in this order:

1. Set up Task File and issue command with OMA bit reset (HOC-2001 will attempt to read sector)
2. Wait for interrupt or for Busy bit in Status Register to be reset 3. Do block move from HOC-2001 buffer to system memory 4. Check Error bit in Status Register for proper completion

Note:

Steps 3 and 4 above can be reversed.

T.::;. execute a Type II single or multiple sector command in DMA mode with i rlt et"t"'upt s, the system software does the following:

1. Set up Task File and issue command with DMA bit set

2. Set up OMA controller

(HDC-Z001 will attempt to t"ead single Cit" multiple sectors)

COMA controller will move data from HOC-2001 to memory)

3. Wait for interrupt from HOC-2001

4. Check Error bit in Status register for proper completion

The aboVe sequence is preferred but steps 1 and 2 above can be l''''evel'''sed.

6. 3. 1. DMA Mode The DMA Mode bit (0) in the above read sector examples is a speCial bit in

HDC-2001 HARD DISK CONTROLLER Technical Manual

the command byte that is used to optimize the HOC-2001's interrupts during
prograMmed I/O and DMA operations. If the DMA bit is reset (0=0) the interrupt will come before the buffer is transferred. This ~llows a programmed lID host to intervene and transfer ~he buffer of data. If the
OMA bit ·is set (0=1) then the interrupt will happen only after the data has been transferred. This allows the host to go uninterrupted until the entire buffer has been transferred.

6.3.2. Block Moves

The HDC-2001 performs all transfers between it and the disk drive through
an on-board full sector buffer. Once the disk has been read, the data is available to the host at any rate from DC to as high as a byte every 1.75 uS. In programmed 1/0 applications there is no nee~ to consult the DRG bit in the status register to determine if another byte is ready t~ be processed. Once an interrupt occurs or the busy bit is reset on a read, the host computer should do a block move of all the bytes in the se~tor.

The following 8080 code demonstrates a transfer from the HOC~001 to system memory. The transfer address is in HL and the byte count is in B:

READIT: IN
MOV
INX OCR JNZ

DATA M,A H
B
READIT

;Get data from HOC-2001 sector buffer ;Store it in memory
;Increment memory pointer ;Decrement byte counter ;00 it again if whole sector not xfered

The following Z-80 instruction does it all. The transfer address is in HL, byte count is in Band HDC-2001 data register address in C:

READIT: INIR

;Transfer buffer from HDC-2001 to memory

6.3.3. Using DMA
There are several features in the HDC-2001 which simplify the use of DMA. Of course, there's the DRQ line that makes a low to high transition for each byte to be transferred. As mentioned earlier, there is a special bit in the Read Sector command which optimizes the HDC-2001 interrupts for DMA operation.

6.3.4. Multiple Sector Transfers

The HDC-2001 can,.transfer ~ore than one sector per command if interfaced

using DMA ~n~ interrupts. Transfers as large as an entire track can be

executed. The Sector Count register holds the number of records to be

transferred.

(If Sector Count is zero then 256 records will be

transferred.> The Sector Number register holds the starting sector of the

transfer. When a multiple sector transfer is successfully completed, the

Sector Count register will be equal to zero and the Sector Number reglster

will be equal to th~ last sector transferred plus one.

HDC-2001 HARD DISK CONTROLLER Technical Manual
If a fatal error is encountered during a multiple sector transfer, the Sector Number register will be left pointing to the sector that contained the fatal error and the Sector Count register will hold the number of sectors that were not transferred.
If a correctable error is encountered during a multiple sector read, the corrected bit in the Status register will be set but the operation will not be terminated because 60rrectable errors are not considered fatal.
Partial Sector Transfers
The HDC-2001 allows partial sector transfers on read operations. This allows the user to read the f~rst part of a sector and then discard the rest. During programmed lID, the byte counter in the block move routine is set to the number of bytes to be read. Dur~n~ DMA operations, the DMA controller is set with the number of bytes to be transfe~red.
Normally the HDC~.001 wi~l interrupt, th~ host after the sector has been transferred during a DMA~read ope~~tion, but if a partial sector has been read, the HDC-2001 will not kn6w that the operation has been completed. For this reason, the 'transfer complete' interrupt must come from the DMA controller. There is, still, a problem.' During write sector operations, the DMA controller will interrupt the system after the buffer has been transferred to the HDC-2001 but before the data has been written. Some systems with advanced interrupt handling capabilities can easily mask off the spurious DMA interrupt. For those that can't, the HDC~001 has a provision built into its command structure to 'detect read operations.
Interrupt Source Selection
Bit 4 of all commands determines whether the operation will be a re~d sector operation or something else., Those commands that require the interrupt from the HDC-2001 have this bit set to a 1. The read sector command (the only one that might need the DMA controller's interrupt) has this bit set to a 0.
Clearing Hardware DRQ
During partial sector re~ds, the DMA controller will stop the DMA transfer before the HDC-2001 has a chance to issue its last data request. Because of this, the DRQ line may be set tne next time transfer parameters are sent to the DMA controlle~. To avoid spurious ,(and often fatal) DRQ's, the user must do a hardware clear of the DRQ line. This is accomplished by reading or writing the Cylinder Low register. (This will only clear the DRQ line. The DRQ bit in the Status Register will be indeterminate.) This action is typically done before a subsequent read or write sector command in the normal course of updating the Task File. Care should be exercised to insure that the DMA controller has passed its parameters only after the Task File is updated.
32

HDC-2001 HARD DISK CONTROLLER Teehnieal Manual

6.3.5. Simulated Completions
All HDC-2001 commands (except multiple sector transfers> act in pre6isely the same manner, whether or not an error was encountered. The only way to detect that an error has occurred is to sample the Error bit in the Status Regi~ter. Simul~ted Completions offer the system designer several tangible benefits.

Simplifies masking and generation of interrupts

Simplifies non-error handling portions of the system software

EliMinates the software overhead of handling different types of errors

Simplifies system software error handling validation (any' error is

handled the same as any other error)

Prevents system failure in the event of some obscure error condition

th~t the system programmer did not anticipate

Write Sector and 'Format are Type III commands. These commands are characterized by the transfer of a block of data from the host to the HDC2001 buffer. Like Type II commands, these commands feature implied seek with an implicit stepping rate. To execute a single s~ctor Type III command in programmed lID mode, the system software must do the following functions in this order:
1. Set up Task File and issue command 2. Do block move from syst~m memory to HDC-2001 buffer
(HDC-2001 will attempt to write a sector or format) 3. Wait for interrupt or for Busy bit in Status Registe~ to be reset 4. Check Error bit in Status Register for proper completion
To execute a single or multiple sector Type III command in DMA mode with lnterrupts, the systeM software does the following:
1. Set tip Task File and issue command 2. Set up DMA controller 3. Wait For interrupt from HDC-2001 4. Check Error bit in Status Register for proper completion
Steps 1 and 2 above can be reversed.

HDC-2001 HRRD DISK CONTROLLER Technical Manual

6. 4. 1. FoV'miltting

The forMat command is ve~y similaV' to the write sector cOMMand, except instead of· fillihg th~ sector buffer with user data, it is filled with
inte.... leave ay,d- bad block informatioYI. Two bytes will be writteYI to the buffer for each '·i;~·ctor to be formatted.

, ~...... , ·,1
The fir"st (lower") byte will be either a 00 or caYI 80 iYI hex.

1f the lower

byte is a 00, the sector is marked as good. If the lower byte is an 80,

the sector will set the Bad Block bit in the Status Register 1f there is

any attempt to read or write to it. Please see cautions in section on bad

blc.ck mapping.

The second (upper) byte is the logical sector number of the next sector to
be formatted. This number will be recorded on the disk. The Sector Number registel''' is rIot used dUl'''ing For"mat.

On a 32 sector per track disk, 32 paiV's of formatting information must be supplied to the drive during each for~~t operation. To start the format operation ~he buffer Must be completely filled, even if the sector table is not as long as t~e buffer. On a 32 sector per track disk, 64 bytes of formatting inform~tion are supplied. If the sector size is 256 bytes then
192 bytes of garbage must be passed to tho controller to start the format operat ic.r,.

Since the contents of the sector buffer do not imply how many sectors are
to be formatted, a dedicated register is provided. This Sector Count register must be loaded with the number of sectors to be f~rmatted before
each and every fo~mat operation. To calculate the maximuM number of sectors per track, see Appendix C.

6. 4. 2. Interleaving
If we try to read physically sequential sectors on the disk, there lS not enough time for us to set up to read or write the~eKt sector before it has passed by the read/write head. This means that the disk will have to make a complete rotation to pick up the nQHt sectorr If we ~ere to read all 32 sectors on ~ particular t~ack it would take 32 rotations, or about a half a second per 8K bytes. ' This performance can be tremendously improved by allowing the system to ,,"ead C'l'~ write mC'l'''e thar. cine: sect 0"'" per rotat iClrl. This can be accomplished with interleaving.
Suppose our system takes less th~n thre~ sector tiMes. (3/32 rotational period with 256 byte sectors) to digest the data that It has read and to set up the next read operation. That M~ans that if we can arrange to have the second logical sector placed physically only four sectors away from the first one, the controller will be able to read it without Much delay. This four to one interleave factor will allow us to potentially read the entire track in only four rotations. In our particular example, this will increase the throughput be a factor of eight.
The siMplest way to determine th~ optimUM interleave for any particular systeM is through experimentation. If the system mdinta+ns its directories

HDC-2001 HARD DISK CONTROLLER Technical Manual

P-R-O_A1R~- -~-t-N-(-3-

or virtual memory swapping areas in a certain place on the disk, it sometimes makes sense to have mQ~~ tb~n QD~ interleave.

To simplify driver software, the HOC-2001 will automatically map loglcal to

physical sectors to achieve interleave. This logical to physical map is

recorded on each track of the disk in the ID fields of the sectors.

This

Map is recorded on the disk during the format cperatlon. Here is ~n

example of an interleave table for a 32'sector- tr~ck wl~h ~:t interleave

and no bad ~locks:

Interleave table with 32 sectors and 4:1 interleave

121121 121121 121121 1218 121121 10 121121 18 ~~ ~! 0121 09 1210 11 00 19 121121 1212 1210 121A 1210 12 121121 1A 121121 1213 121121 1218 1210 13 121121 lB 0121 1214 121121 0C 121121 14 0121 1C 121121 1215 121121 1210 00 15 1210 1D
0121 1216 121121 0E 121121 16 121121 lE 1210 1217 121121 0F 121121 17 121121 iF

Rernem bel''' : The balance of the buffet" must be filled wi th someth 1 rig to stal''''t the format operation.

The first byte in each byte pair in the preceding example is set to 00

This' marks each block as a 'good' block. The second byte of each byte palr

is the logical sector number.

The first byte pair ~bove represe~ts th~

first logical sector of the track. The underlined byte pair represents the

second logical sector.

The Winchester and thin film technology drives that interface to the HDC2001 often do not have perfect media. Imperfections 1n the media allow much more latitude in what the media manufacturers can ship, slgnlf1cantly bringing down the cost of the medla and, consequently, the drives.
The user is required to map out these iMperfections.. There are many ways it can be done, some of which are highly operating system dependent. ~ere at""e a few ideas =
6. 5. 1. Sector Pre-allocation
If the operating system supports random sector or group allocation, the bad blocks can sometimes be Mapped out b~ recording an un-deletable file using all the bad sectors on the disk. When the operating system tries to write to the bad block, it will see that the sector or grouo that contains the error has already been allocated. The operating system wlil automatlcally map over the bad s~ctor.
There are a couple of minor restrictions associated wlth this form of bad block mapping. The file that contains the bad sector Must never be moved to another section of the disk. The bad sector file may not =e read (f~t~ obvious reasons) and reads or writ~ to the disK~ that do not =onslJlt ~~e disk allocation map (physical reads/writes~. are not allowed.
35

~ '"'11 0 #1 '.... "i': ". c ........... .., .....

~ ·. __

HDC-2001 HARD DISK CONTROLLER Technical Manual

6.5. 2. Alter'nate Tracks
This method works on most operating systems but, it requires More software overhead. Whenever a read or wr'ite is attempted, the track number (cylinder' and head select) is checked against a table maintained by the operating system or driver. If the track number matches the table, the driver knows that there is a flaw somewhere on that track. The driver wlil look up the alternate track for that flawed track and the read or write will be performed elsewhere.
The primary disadvantages of this type of bad block mapping is its rather high software overhead. When the system is brought up, the alternate track table has to be read from some flawless areas of the disk. After it has been read, every read or write oper'ation must check the alternate track table before performing its respective operation.
The HDC-2001 bad block marking and detection facility is useful for eliminating the software overhead of looking up each track number before each write is performed. During format, all the sectors of the bad track should be written redundantly with the bad block bit set (See section on Bad Block bit below). When any read or write is attempted on the bad track, the HDC-2001 will interrupt with the Error bit in the Status register and the Bad Block bit in the Error register set. The driver can then look up the alternate track in its internal table and resume the '='perat iorl.

6. 5. 3. Spare Sectors
This method is, probably the simplest to implement 1n most systems. Its primary disadvantage is that at least one sector must be set aside as a spare for each track. Durlng format, the physical sector that contains the flaw is written with some illegal sect~r number. The physical sector following it contains the real logical sector and its data. In the following interleave table, the user mapped out the fifth physical sector by telling the HDC-21Z101 to write a logical sector number of FF to it.

Interleave table with 32 sectors and 4:1 interleav~ with physical ~ector f·ive mapped out:

,',121121 0121 0121 1218 121121 1121 1210 18 ~~ EE 121121 1211 0121 09 100 11
121121 19 121121 02 0121 121A 121121 12 00 lA 1210 1213 00 08 1210 j3 '.00 18 0121 1214 00 0C 1210 14 00 lC 00 05 1210 00 00 15
121121 1D 00 1216 00 IZIE 1210 16 121121 lE 00 1217 00 0F 0!Z\ 17

P.lease note that when for"mat t i ng the disk in tnls mc~'··$rle)-". at least one

sect,:.\,,, rI1l.tst have aY" illegal sector'" Y'.urnbet".

Also, S 1rice WI'::' have allocated

oY'I'e ':sector tel bad block mapping, we YI':) lC'Y'lger have a sect.: IF.

6. 5. 4. Bad Block Bit

HDC-2001 HARD DISK CONTROLLER Technical Manual

The HDC-2001 Allows the user to set a marker that is recorded into the 10 field. When the HDC-Z001 attempts to read or write a sector with a bad block mark set, the operation will be aborted and the Error bit in the Status register and the Bad Block bit in the Error register will be set. The Size, Head, Cylinder, Sector and 10 eRC fields of the selected sector must be correct in order to detect the bad block ma~k.

To insure that the Bad Block bit can be ~ead even though some 10 fields may be defective, the ID fields Must be recorded redundantly. In order to make
this possible, the HOC-2001 includes a special variation of the Format command. When a Bad Block bit in the interleave table is set during format, the HOC-2001 records only the ID field of that s~ctor. No data field is .."ecl:)..~ded. This helps tel make room felt' red'.ly,day,t 10 fields.

In the following interleave table the user has marked all the sectors with
a bad block mark and recorded all sectors redundantly. The interleave is not very important here because the driver (hopefully) will not attempt to read bad sectors sequentially.

Iy,terleave table with .."'ed u y.d ant sectOt~s, mat"k.ed as bad blocks:

YII:'t 1 y",t er leave,

arl all

sectOt~s

8121 00 8121 1211 8121 02 8121 1213 8121 1214 80 12'5 '3121 06 80 1217

80 08 80 09 80 0A 80 08 80 0C 8 III 0D 80 0E 80 0F 80 10 80 11 8121 1·.C..o, 80 13 80 14 8121 15 8121 16 8121 17

80 18 8121 19 80 lA 80 1B 8121 lC &:3121 1D 8121 IE 80 IF

80 1210 80 1211 8121 1212 9121 ~3 80 04 80 05 80 05 80 1217

80 1218 80 09 8121 etA 80 1218 80 IZIC 80 Q'!O 8 ill IZIE 80 0F

80 1121 8121 11 8121 12 8121 13 8121 14 80 15 8121 15 8121 17

1
80

81ZJ

~DC·2~01 HARD DISK CONTROLLER Taehnical Manual
7. THE 0 R V o F OPE RAT ION

The HDC-2001 hard disk controller is a discrete implementation of all

functions required to control SA1000/ST506 compatible Wincne9te~ hard disk

drives via the S-100 bus. The controller is fabricated using a mix of

high-speed bipolar and NMOS devices contained on a single, 2-sided PC

board.

The design of the circuitry makes use of a high-speed

Microcontroller, the 8X300, newly developed NMOS support devices, Schottky,

and low power Schottky devices to achieve low component count and low cost

while maintaining high performance and reliability. All I/O connections are

made using standard ribbon cable connectors.

Standard pin-out

configurations for disk interface connectors are provided to pe~mit direct

pin-for-pin connection to SA1000 compatible 8" drives and STS06 compatible

5-1/4" dt"ives. All power ,fc,r the board can be supplied from a single +8

Volt power supply. All host to disk data transfers are buffered 'by an

onboard RAM to achieve totally asynchronous transfet"s to and from the disk

by the host. Irl addit iorl, the HDC-2001 has the abi I ity to perform error

correction (ECC) using firmware and a custom designed NMOS device.

The HDC-2001 is available irl two different formats - a 5-1/4" or Sit board.

The disk controller is built around 5 basic sections:

1. Processor functions
2. Serial data separation 3. Data conversion, checking and correcting
4. Serial data generation 5. Host interface functions (S-100)

Ril functions of the HDC-2001 controller are ultimately controlled by the onboard processor. Due to the high data rates associated wi~h hard disk drives, processing of data and control of machine functions within the circuitry requires a processor capable of ext~emely fast eKecution speed.
The processor used is the aX300, a bipolar microcontroller, particularly
well suited for handling data efficiently at' high rates.
The aX3~0 is opel'''ated at a basic clock rate of a MHz and perforh.~ all
opet'ations within 2 clock cycles, giving, it a speed of 4 MIPS (Million Instructi6ns Per Second) or one instruction executed every 250 nS. The architecture of the processor is different frOM most popula~ microprocessors 'i~ that no common data or address bus is provided to be shar~d by RRM, ROM or peripheral devices.
Instruct iOYIS are fetched from ROM via a dedicated instruction address and data bus. The instruction address bus (IA13-IA0) is capable of directly
38

HDC-2001 HARD D1SK CONTROLLER Technical Manual

accessing SK words of program storage. The HDC-20el, however, uses only the first 10 address lines, limiting onboard program storage to lK words. Program data is input to the BX300 on the Instruction Data Bus (1015-100) as 16 bit words whieh are decoded to perform the desired operation. All bus designations utilized by the aX300 are reversed from the traditional LSB to MSe weighting. On the HDC-2001 these lines have been renAmed on the schematic, using traditional weighting to provide a more conventional designation system for the board.
Data is transferred between the processor and it ports on a separate a-bit bus called the II 10" bus. This bus is act iVt' low. It must be noted that this bus is irl no way related to the in5tr~.tct ion data b'.(s and should be thought of as simply an a-bit bi-dlrectional 10 bus for the 8X300. In fact, it has been renaMed as 100-107 to reflect this deflnition.

7. 2. 1. Fast 10 Select
An extension byte has been added onto the instruction data memory to provide port access decoding on an instruction by instruction basis. This "Fast 10 Select" byte is riot pt"ocessed by the aX30~; l'''athet'' it is decoded by auxiliary hardware to provide Bread stro~es, B write strobes, and 8 single bit output ports which route data to the various devices distrlbuted along the 10 bus.
The write part of the Fast 10 byte is latched i~to a 4-bit latch and the input of a decoder/latch on the trailing edge of MCLK. This ensures that data remains stable during the entire instructlon. The read strobe and write strobe are selected through a pair of 1-of-8 decoders which are alternately enabled by the SC- control strobe produced by the aX300.
It also provides latch-address data to the ~ddressable latch for drive and ECC control signals. To provide edges O~ read strobes during sequential read 'operations from varlOUS ports, the read strobe decoder is always disqualified at the end of instruction by MCLK-. Because each decoder has a unique input and the latch is directly addressable, it is possible to select any read port with any write port, dur-ing each instruction.

7. 2. 2. Internal Bus Control

Several bus control signals are produced by the AX300 to identify and

st t"I::.be the data on the 10 b 1.l5. SC- is a s i g~la 1 wh ich determi nes the

directicln of the data to and fl''''om pet"ipher·a.lg. WIlen !3C- is false, (dl,.tt"ing

the fit"st half cycle) the BX300 lY'lpUts data ft"OM I;he in bus.

When UC- is

true (only during the second half cycle), the 8X300 outputs data to the IO

bus. The HDC-2001 allows 8-tit lmmediat~ d~ta moves from the 8X300 to any

output P':'It"t withiY', one instruct ion, iYlsteaci of tt)e n.:)~"rnal 5-bit immediate

r'Ill::.ves pt"ovided f.::.r by the inst:-"'\Jcti':Il~1 set.

All instruction fetches occur late in the second cyc1e of the instruction. This time is m~rked by the generation of a 65 nS act i ve high pu I se ca 11 ed MCLh., YJt'll ch CICCUl'''~') (;:?\/I.-:Y':.1 j nst l'''lJct 1 01'"1. PC1t"ts, MCLK is also used t.::> ia-t.c:h data ~ri(,:.t~ t'~1 bE-b,g input on

preceding (nominal) On some the IO bus

HDC-2001 HARD DISK CONTRDLLER TQchnical Manual
to insu~e stability du~ing ~eads, and to disqualify ~ead st~obes which would othe~wise ~emain t~ue into the second clock cycle of any inst~uction which does not w~ite to a po~t.
All I/O po~ts on the aX300 a~a logically divided into two add~e.s spaces. This add~ess space is qualified with RIGHT BANK SELECT (RB-). All HDC-2 001 I/O ports, eKcept RAM, appea~ in the left bank add~e.s space. The RAM is placed in the ~ight bank and the ~ight bank signal is run di~ectly to the CS- inputs of the RAMs to avoid the p~opagation delays associated with the F~st I/O Select logic. This allows slowe~ RAMs to be used and p~ovides bette~ access margins on read ope~ations.
7.2.3. Reset Ci~cuit
The 8X300 is held ~eset for approKimately 40 mS afte~ initial powe~-on. This is accomplished by an RC network (R24:R5, C24:C16 and CR1=CR1) which drives a Schmitt trigger to provide a proper rise/fall time on the RESETline of the BX300 and various po~t latches. Alte~nate ~eset of the HDC2001 can be 'accomplished by asse~ting MR- whenever the host wishes to reset the controller. A Schmitt trigger is provided with a 4.7K pull-up to buffer the MR- input frOM the host. RESET- also propagates to the drive control latches, the host interface Support Logic Chip, and the INTRQ and DRQ latches.
7.2.4. Procasso~ Powe~ Supply
Powe~ is su~plied to the aX300 f~om the +5 Volt (Vcc) powe~ bus. Due to the internal ope~ation of the aX300, an on-chip voltage refe~ence is provided, to produce bias to an external pass transistor which drops Vcc to the aX300 to approKimately +3.0 Volts. This supply is used internally by th~ aX300 logic and all signals of the aX300 are internally level shifted to be TTL compatible.
7.2.5. Read and Writ. Po~ts
Throughout the circuit, output ports consist of D type latches using write strobes (WR0-7) to latch data into the ports. Reading of ports is accomplished ,by using read strobes RD0, RD2, and RD4-6. The ~ead strobes individually enable selected tri-state output devices on the 10 bus. Additionally, two read strobes are used to clock the host DRQ and INTRQ latches for instructions not requiring data from a port. This ensures glitchless operati6n of the Fast 10 port decoders.
7.2.6. Read/W~ite Memo~y
Since the 8X300 does not permit data to be saved or retrieved from dedicated program storage, RAM must be installed on the 10 bus and it must be accessed via the 10 bus by I/O instructions like all other port I accesses. To provide for addressing the RAM, three latch/counters are connected to the 10 bus to receive and store addresses required to access
40

HDC-2001 HARD DISK CONTROLLER TechnicAl Manu&f
the RAM.
RAM Addressing
The RAM address bus (RA0-RA9) uniquely addresses 1024 memory locations. As each counte~ chip ~eaches a count of 0, it will sst a bo~row condition to the neHt higher counter which will be decremented at the end of the next access to RAM. When all bits of the address have been reset, the ROVF- bit Dn the last counter will be reset, providing an overflow status which can be read by the processor. By setting various beginning address values, ROVF- can be used to mark the end of any RAM access loop from" 1 to 1034 bytes in length. In the HDC-2001 this fUnction is used for setting sector buffer lengths of 128, 256 and 512 bytes in the normal mode and 132, 260, 516 in the long mode.
Sector Buffering
All data read from the disk or written to the disk is passed through the RAM to provide buffering required for asynchronous data transfer between the host and disk. The counters are post-dect'emented so that addresses are stable to the RAM by at least one instruction prior to the actual access. This preselection feature effectively reduces RAM access time to the output enable and propagation time of the RAM for read operations and the width of the minimum WR- strobe pulse for write operations.
RAM Accessing
RAM access is initiated by RB- which is output by the aX300. Data to be read from RAM will be placed on the IO bus whenever RB- is low and SC- is
high. Data is written into a selected RAM cellon the trailing edge of se-
if RB- is low. During writes, RB- will be low for at least 120 nS so that data setup time requirements are met~
Scratchpad Operations
Because the RAM address counters are presettable direct reads and writes to a specific .address are possible. However, resolution of the address is limited to the nearest fourth address location. this limitation is imposed so that a full ten bit address can be specified with a single eight bit output. The least significant two bits are implied to be 10 (binary).
7.2.7. Miscellaneous Control Ports Control of the various functional sections of the HDC-2001 is accomplished by a dedicated 6-bit control port called the MAC CNTRL and an addressable latch. MAC eNTRL enables the functions of the WAIT control circuitry (WAEN-), ECC generation (ECCIZ-), gating of read data into data separation circuitry (RGATE), selection of read or write functions (WRITE-), control of ECC check word output (lBLA-), and AM detection (SRCH). MAC CNTRL output states are latched into the port by a write strobe (WR7).
41

HDC-2001 HRRD DISK CONTROLLER T.ch~ical Manual'
The addressable latch controls drive functions and CRC/ECC selection. This latch enables direction of the drive (DIRIN-), stepping pulses to the drive (STEP-), reduced write current (RWC-), write ~recomp (WPC-), write enable (WRITE GATE-), and switching the enable between CRC and ECC (CRC-/EeC).
All remaining ports are distributed among the basic functional sections of the HDC-· 001 and will be described in detail within the discussion of those functions.
The HDC-2001 controller utilizes an NMOS device (WD1100-09) especially designed to process incoming MFM data from the drive by a process called data separation. Here, some background information may be helpful:
In order to provide maximum data recording density and storage efficiency, data is recorded on the disk using a Modified Frequency Modulation (MFM) technique. This technique requires clock bits to be recorded only when· two successive data bits are missing in the serial data stream. This reduces the total number of bits required to record a given amount of information on the disk. This results in an effective doubling of the amount of data capacity, . hence the tel'''m "double density."
Because clock bits are not recorded with every data bit cell, circuitry is required that can remain in sync with data during the absence of clock bits. Synchronous decoding of MFM data streams requires the decoder circuitry to synthesize clock bit timing when clocks are missing and synchronize to clock bits when they are present. This is accomplished by using a phase locked oscillator employing an error amplifier/filter to sync onto and hold a specific phase relationship to the data and clock bits in the data stream. The synthesized clock called RCLK can then be used to separate data bits from clock bits and·to shift the resultant serial data into registers for byte parallelization.
7. 3. 1. Incoming Data Selection
In the HDC- 2 001, serial data is input from up to 4 radially connected drives via a quad RS-422 differential receiver. The receiver converts differential input data to TTL levels for use by the controller. The data from the selected drive is then routed to the data separation circuitry by a 4-section AND/OR/INVERT gate. Due to the fact that different drives produce varying data pulse widths, the data is first ro~ted through a oneshot to provide a'consistent data pulse width. At this point data and clocks are still combined and appear as 50 nS nominal active high pulses spaced at intervals of 1, 1.5 or 2 times the RCLK period. This data is presented to the Data Separator chip (U6:U34) which will then gate either MFM data or a reference clock into the first stage of the VCO error amplifier circuitry.
4?

HDC-2001 HARD DISK CONTROLLER Technical Manual

7. 3. 2. Raference Clock
The reference clock is derived from the write clock crystal oscillator (and associated circuitry). This oscillator uses ~ fund~mental crystal cut to oscillate at 4 times the RCLK frequency. The 4X output is then divided by U4 to produce both a 2X clock (2XDR) wJ;?ich is used as a refe.,"ence and a 1X
clock (WCLK) which is used to produce MFM write data for the disk. The
crystal (Yl) frequency is 20.000 MHz for ST506 com pat ible dl'''ives or 17.360 MHz for SA1000 compatible drives.

7. 3. 3. Clock Gating
The gating of the reference and MFM data into the data separator is dependent on the condition of the read gate (RGATE) signal and the spacing of the data on the serial stream after RGATE is brought true. Due to the techniques which are employed to separate data from clocks, it is necessary to run the VCO at a rate twice the data clock (RCLK) rate. The VCO is set to a open loop frequency of 2X RCLK. Any variations in this rate' due to variations in disk rotational speed must be compensated for by the VCO, but instantaneous shifts in data due to the effects of adJacent bit cells on the disk and minor noise must be ignored. Also, the response of the VCO must be adJusted to effectively ride over missing clock bits which occur as a result of the MFM recording technique. The resultant compromise between response and reJect requirements of the VCO cause the VCO to have a tendency to become locked onto harmonics of the data rate rather easily. This is likely to occur if the VCO is connected to a data stream over a field of data which has data bits spaced at 1.5 or 2 times the actual RCLK time irltel'''vals.
To provide protection against this undesirable condition, the VCO is always held locked onto a stable clock running at 2X RCLK frequency whenever the controller is not actually reading data. Care is taken to switch in read "data to the VCO error detector only when it is known that the data stream frequency is equal to the RCLK frequency. This can occur only when the data is a solid stream of all ones or all zeros.

7. 3. 4. High Frequency Detector

The switch from refer"erlce clOCk tel live data is .initiated immediately after

the RGATE goes true and will only occur after l~"qonsecutive ones or zeros

(high frequency) are detected on the raw MFM.

This detection is

accompl ished by a I::.ne-shot arid the data separatl~t". The one-shot is

adjusted for a pulse width of 1.25 times the RCLK period (250 +/-10 nS for

ST506 compatible drives and 287 +/-10 nS for SA1000 compatible drives).

The adjustment of the one-shot provides tolerance of up to 1/4 RCLK period

in Jitter on the MFM data bits while still being able to distinguish MFM

zeros or ones froM other data patterns.

Each clock or data bit on the serial stream triggers th2 one-shot. If the time between sucqessive triggers is less than the one-shot time constant, the one-shot remains retriggered. As the one-shot is triggered,by data

HDC-2001 HARD DISK CONTROLLER Technical Manual

streaM bits, so is a counter in the Data Separator Device), whose reset is controlled by the state of the one-shot outputs. While the one-shot is being retriggered the counter counts up. When ~ny data bit fails to reach the one-shot before its time constant is over, the one-shot resets and in turn clears the counter. Only when 16 successive ratriggers occur can the counter reach its terminal count. At this time, the counter overflow goes true and sets a latched. DRUN- output low, which switches read data in the reference clock out. DRUN- is read by the 8X300 to determine the condition of the MFM data stream.
At this point data and clocks have finally been connected to the first
stage of the data separator. The heart of the data separator is the veo,
th~ error amplifier, filter and the Data SeRarator Support Logic Chip (WD1100-09).

7.3.5. Sample on Ph.s. Detection
When an input signal is applied to the system, its phase relationship is detected within the Data Separator Device. The function of this phase detector is to provide windows, during which the leading edge of the incoming MFM data can be compared to the leading edges of the vca clock. The windows are approximately 50 nS in length. The windows are initiated by the leading edge of any data bit as it enters the detector. They are terminated by that same data bit, edge delayed by 60 nS or the VCO output (OSe-). When both the delayed data bit (delayed by DLl) and the nearest veo edge arrive at the detector, the detector is reset until the next data bit arrives on the MFM data stream. The delayed data bit sets its half of the detector latches to produce a pump up condition at the error amplifier. The VCO clock edge set its half of the detector to produce a pump-down condition. When the circuit is balanced, both pumps are on or off, producing no net pump-up or pump-down.

7.3.6. Er~or Amplifier
Contr61 of the VCO is accomplished by the error amplifier, filter, and Data Separator Chip. The error amplifier is a balanced current mirror, whose output sources or sinks current to the filter stage. Whenever the VCO is running too slow, the error amplifier ~eceives pulses frOM data bits before pulses from· the VCO clock. This causes the error amplifier to produce pump-up pulses to the filter. The filter in~egrates these pulses, producing an average increase in the voltage to the~VeO. Whenever the veo is running too fast", the error amplifier produces pump-down pulses to the filter. It must be noted, however, that some slight error will always be present because, without pumps, the filter will float and the veo will drift. The overall gai~ of the error amplifier ~nd the veo will maintain this error very small, resulting in very close tracking between the VCO output phase and the incoming data phase.

7.3.7. veo
The HDC-2001

uses a single chip VC~,

which simplifies circuitry and

HDC-2001 HARD DISK CONTROLLER Technical Manual
adJustments. The operating point of the VCO is initially set by adJusting the variable capacitor for a 10 Mhz (when running on 5 Mhz drives) output center frequency and the frequency control voltage input to 2.5A +/-0.5V. It should be noted here that the frequency range voltage and the frequency output are adjusted to the 'locked' center frequency with the same variable capacitor adjuster.
The output of the error amplifier and filter is fed to the VCD and represents how far the VCO frequency is from that of the incoming signal. ,The error signal, which is proportional to the difference, allows the VCO frequency to shift from center frequency and become the same frequency as the input signal. When the loop is in lock, the difference frequency component (error voltage) is DC and will be passed by the low pass filter. Thus, the lock range is limited by the range of the error voltage that can be generated. The lock range is essentially a DC parameter and is not effected by the band edge of the low pass filter. It can be defined as the frequency range, usually centered about the VCO initial free running frequency, over which the loop can track the input signal once lock has been acquired.
Frequency control is actually a matter of frequency range. The difference component may fall outside the band edge of the low pass filter and be removed along with the sum frequency component. If this is the case, no
information is transmitted around the loop and the veo remains at its
initial free running frequency. As the input frequency approaches that of
the veo, the frequency of the difference component decreases and approaches
the band edge of the low pass filter. Now, some of the difference component is passed, which tends to drive the VCO towards the frequency of the input signal. This, in turn, decreases the frequency of the difference component and allows more information to be transmitted through the low pass filter to the VCD. This is essentially a positive feed-back, which
causes the veo to snap into 'lock' with the input signal. With this in
mind, the term 'capture range' can be defined as the frequency range centered about the VCO initial free running frequency over which the loop can acquire lock with the input signal.
As previously stated, the VeD runs at a frequency twice that of the RCLK
rate. By setting the center frequency equal to twice the data rate, the
VCO will lock to the data and give an exact synchronized clock.
7.3.8. Window Extension
Once the VCO has been locked onto the phase of the incoming data, the actual separation of data and clocks can occur using a technique called window extension. This technique causes data bits to first have their leading edges shifted into the center of the RCLk half cycles and then to be latched or extended until the next rising edge of the RCLK. The delayed data clocks a pair of latches. The 'data' latch has its D input and CLEAR connected to +RCLK and the 'clock' latch has its D input connected to RCLK-.
If an MFM data bit enters the latches while RCLK+ is high, it will be extended as a data bit. If RCLK- is high, it will be extended as a clock
45·

HDC-2001 HRRD DISK CONTROLLER Technical Manual

QE !~EgBY

ge5B8Ilg~

bit. Due to this extension technique, bits can JItter approximately 1/4 the

RCLK period without being lost. The output of each latch is then further

extet.':ted by feeding directly into another stage of latches and clocked on

alternate edges of RCLK.

The final" outputs of the data

extension/separatiol~ stage are two separate signals, one con9isting solely

of NRZ data, and the other NRZ clocks. NRZ data and clocks are finally in

a form suitable for processing by subsequent circuitry within the HDC-2001.

7.3.9. Clock Detection
Due to the nature of MFM data encoding, it is impossible to know exactly if MFM bits are data or clocks. This ambiguity results in having to assume
that bits on RCLK- are actually data bits until the veo is locked on and a
unique data/clock pattern is detected. This is accomplished by holding the VCO to RCLK divider reset until it is fairly certain that bits on the data stream are actually clocks belonging to a field of zero data.
Once this assessment has been made, the processor releases the AM detector by raising the SEARCH signal. This signal releases a latch which will remove DHOLD- from the RCLK divider on the next rising edge of a MFM data bit so that CLOCKS will be on the RCLK- phase and DATA will be on the RCLK+ phase. The processor makes its assessment of the state of the data stream solely on the one-shot in the DRUN circuit. Once released, the phase of RCLK versus data and clocks will remain stable throughout the read of an ID or data field. Whenever SEARCH is dropped, the VCO to RCLK divider is once again reset and no RCLKS are produced.

MFM data which has been separated to form NRZ data and clocks are processed through specialized circuitry to prepare it for parallel processing by the 8X300. This processing consists of 3 functional circuits.
1) AM detection 2) ECC/CRC checking circuit 3) Serial to Parallel Conversion
Each function will be discussed separately but bear in mind that many interdependencies exist.
7. 4. 1. AM Detection
As previously stated, it is impossible to know whether serial data bits are actl..lally data 01''' clock bits by Just looking at the data stt"eam. Also, it is equally impossible to determine byte boundaries of the data stream. This problem is solved by a uniquely recorded data/clock pattern called an Address Mark (AM). The AM consists of a data pattern of hexadecimal 'Al' with a missing clock pattern of hex 'OA'. Normally a data byte of hex 'Al' requires a clocking patt~rn of hex 'DE'.
The AM is used tl:) uniquely idey,tify the stal'''t of a field of information

HDC-2001 HARD DISK CONTROLLER TechnicAl Manual
(Data or 10 field) within each sector. Preceding each AM on the disk there is always a long r~n of 'zero' data. Zeros have a clock bit for every RCLK. When attempting to read information from the disk, the HOC-2001 first acquires phase lock over a field of zeros. After this acquisition is ac~ieved, the processor releases the AM detector by raising the SEARCH control line (SRCH) on the MAC CNTRL port. Due to the circuitry associated
with the veo to RCLK divider the R~AT- output of the data separator will be
high and the CLKS- output will be low. RCLK- will be the shifting clock for RDAT- and RCLK+ will be the shifting clock for CLKS-. These 4 signals are routed into the AM detector.
Inside the AM detector, the RDAT- is shifted into an a-bit synchronous set~ial ~hift register and clocked on the falling edge of RCLK-. CLKS- are shifted into a similar shift register on the falling edge of RCLK+. The output stage of the ROAT- register is dumped into an 'A1' comparator and the output stage of the CLKS- register is dumped into a 'OR' comparator. AM detection occurs when both detectors are true, setting the AMOET latch. At the instant AM occurs~ th~ exact relationship between data and clocks is known. It is also known that data is being clocked by RCLK- so CLKS- can actually be discarded; its only purpose was in detecting AM. The AMDETsignal is used as a synchronization signal to start subsequent conversion circuitry· . The AMDET- signal remains true until the processor again deasserts the SEARCH control line.
The AMOET- signal is processed by a D latch, located in the Support Logic device (WDl100-07), to precisely time the leading edge of AMOET- to the rising edge of RCLK. This synchronization relaxes timing requirements on the data and clock inputs of the serial to parallel converter. Also, a orle-bit delay is placed in the AMOET path within the Support Logic Device to compensate for correct timing with the ECC architecture.
7.4.2. Error Detection and Correction
Data recorded on magnetic media is prone to several types of errors which could render data unusabl~ if some form or error detection were not employed.
On the HOC-2001, error detection is performed on all data transfers frOM the disk. The ID fields use a 16 bit Cyclic Redundancy Check (CRC) and the data fields use either the same CRC or a special 32 bit Error Correction Code (ECC). The CRC and ECC fields are appended to the data field that they are to protect.
The HDC-2001 uses the same device to generate and check CRCs ~nd ECCs. Normally, the HDC-2001 uses CRCs in 10 fields and ECCs in data fields. Also, as a software selectable option, the HDC-2001 may be used in a CRC only mode by appending eRC check bytes to both ID and Data fields. Although either polynomial could be used for both fields, the use of the ECC polynomial is limited to data only. On-the-fly correction of ID fields cannot be done a~d CRC provides' adequate checking for the 10 fields. The ECC and CRe polynomials used are as follows:
47

HDC-2001 HRRD DISK CONTROLLER Teehnieal Manual
(Also known as CRC-CCITT)
As data is being read froM the disk, the CRC/ECC generator re-eomputes the original eheck bits. After all the data are read the value in the CRC/ECC generator is exclusive ORed with the check bits recorded on the disk. The result is called the syndrome. If the syndrome was zero, the data was correctly read. Otherwise, an error occured. If the field was proteeted by a CRC, the data can often be recovered by a retry which the HDC- 001 performs automatically. If the field was protected by an ECC, the non-zero syndrome is used by the on board processor to compute the displacement and the error vector within the sector. This information is then used to correct the data if a single burst of no more than five bits in error occured.
The CRC/ECC generator is initialized by setting ECCIZ- low for at least 250 nS during the search for the AM. ECCIZ- is originated on the MAC CNTRL port. Upon receiving the ECCIZ- Signal, the ECC generator will preset all 32 of its internal polynomial division shift registers to logic ones and arm an internal latch which will start the CRC/ECC generator on the leading edge of the first non-zero bit (hopefully an AM) to enter the device.
Once enabled by the first non-zero data bit, the ECC device will shift succeeding data bits into a feedback shift register strin~ with exclusive OR gates tied to the feedback nodes of the register. As each RCLK occurs, the registers will divide the incoming data and a unique pattern of ones and zeros will appear across the registers. The ECCEN input line is set low, indicating that the internal circuitry is ready to begin the computation of the ECC/CRC check bytes.
Sometime before the last byte of data and after the next to the last byte of data is transferred through the device, the DCSS line is set low. When the last bit of an ID or data field is processed, the pattern in the registers should be equivalent to the 16 or 32 check bits appended to the fields during original recording. The check bits on the disk are exclusive ORedwith the check bits in the CRC/ECC device to produce the syndrome.
Data is deserialized after being processed by the ECC/CRC device and ByteSync boundries are marked by byte-sync pulses obtained frOM the Data Support logic device on the RBS input. The byte-sync pulses are internally ANDed with the RWCP line to insure the smooth transition of check/syndrome bytes on the DOUT output line, after the last bit of data has been entered into the device. A one-bit time delay occurs on the DOUT line because an internal latch is used to deglitch the output line.
7.4.3. Sarial to Parallel Conversion
After data has been processed by the ECC device, the Serial to Parallel Converter takes over. NRZ data and RCLK are used to shift data bits into an a-bit serial to parallel shift register. As each bit is shifted, divide-by-8 counter circuit is incremented. After every eighth bit of data is shifted, the counter produces an overflow pulse, marking byte boundaries
48

HDC-2001 HARD DISK CONTROLLER Technical Manual
in the serial data stream. The overflow bit from the counter resets the counter, clocks the data froM the shift register into an a-bit parallel latch, and sets a tri-state flag register called BOONE. The flag can be read by the processor to see if any converted data is ready to be read from the latches.
When the processor sees BDONE in the true state, it services the device by gating data onto the 10 bus using read strobe 4 (R04-) in conjunction with a tri-state buffer. The act of reading the latches also clears the BOONE flag. As successive bytes are processed, BDONE is serviced by the processor as data becomes available.
The HDC-2001 records data on the disk in MFM format. In order to produce the proper data format, the HDC- 001 uses several specialized devices to process the parallel data supplied by the host into a serial MFM data stream. The data supplied by the host is temporarily stored in the buffer RAM until the correct sector is located for the data to be written.
The process of writing is essentially the opposite of reading except that the data separator circuitry is not required and the generation of the MFM data stream is produced by synchronous clocking techniques.
The functional sections of the serial data generation section are listed below:
1. Para 11 e 1 to Sel''' i a 1 convers i.or'. 2. ECC/CRC generation 3. MFM and precompensation
7.5.1. Parallel to Serial Conversion
Parallel data is converted into a serial NRZ data stream by the Parallel to Serial device. The processor enables this conversion by lowering the WRITE- signal on MAC CNTRL. WRITE- causes the tri-state buffers present on the parallel to serial device to become active, supplying the ECC device with data, clocks, and BDONE strobes.
The processor presents parallel data on the to bus along with the WR4write strobe which latches the data into the para~lel port on the trailing edge of the strobe. The write strobe also resets any pending BOONE. Inside the parallel to serial device, the parallel latches are loaded into a serial shift register on every eighth WCLK transition. As the data is transferred to the shift registers, the BOONE status flag is set. The processor reads this flag to determine when to write the next parallel byte to the device. The timing of the parallel accesses is at a rate 1/8 that of the bit rate of the NRZ data stream. For 8T506 compatible drives the byte timing is 1.6 uS and for SA1000 drives it is 1.84 uS.
The output of the last register {n the shift string is brought out of the device as NTZ serial data.
49

HDC-2001 HRRD DISK CONTROLLER T.chnical Manual

!~EQB~ QE QeEB8!lg~

Whenever it is desired to write a repetitive string of identical data bytes, the processor can simply ignore the BDONE flag and permit the device
to reload the data from its latches over and over again for .s long as
required to generate the field. This feature of the device is used in writing certain fields used in formatting.
7.5.2. CRC/ECC Generation
The CRC/ECC generator/checker is used to generate the CRC/ECC bits and to append them to the end of the data being written to the disk. The operation of the polynomial generator is identical to read operations except that at the end of the data field the processor sets a signal which causes the device to output the computed CRC/ECC after the data instead of producing the syndrome.
The initial states of the shift registers within the device are forced to all ones by the process6r pulsing ECCIZ- for at least 250 nS while the parallel to serial device is outputting all zeros on the NRZ data line. At that time, a latch is set which holds the registers at ones until the first non-zero data bit enters the device.
The first non-zero bit will be the MSB of the AM (hexadecimal Al) of the data field to be written. When the processor decides that enough zeros have been written to satisfy the sync field requirements, it will store a hex Al in the parallel to serial device. At the proper time (in sync with BDONE) the parallel to serial device will begin to send the MSB of the AM to the CRC/ECC device. This will start the CRC or ECC polynomial generator and the ECC will be computed.
To write the ECC/eRe check bits, the processor will assert the One Byte Look-Ahead (lBLA-) signal on MAC CNTRL port Just after the last data byte was sent to the parallel to serial converter. The internal switch over from data to check bits is synchronized to the neMt byte time by the WCPsignal. Once the switch takes place, the CRC/ECC.generator will begin dumping the computed CRC or ECC onto the NRZ data stream. The net effect of this is to append the proper CRC or ECC information to the end of a field of data. lBLA- is maintained true for the duration of the unloading process which lasts for up to four byte times.
During the unloading process, the ECC registers bs~k-fill with zeros. This feature is handy because by leaving lBLA- low for ~dditional time, zeros will always be written after the CRC or ECC which is a requirement of the format of the disk. The NRZ data from the CRC/ECC device is sent to the MFM generator device.
7.5.3. MFM Generation
The conversion from NRZ wrlte data to MFM write data takes place in the MFM/Precomp device. This device accepts NRZ data and a complimentary WCLK and produces MFM data and clocks by sending the data through circuitry which deQides when-and where to writ~ clocks on the data stream under the
50

HDC-2001 HARD DISK CONTROLLER T.Qhnical Manual
MFM encoding rules. The proper encoding of the data into MFM requires the device to apply three rules to the data.
1) If the current data cell Qontains a data bit then no clock bit will be generated:
2) If the previous data cell Qontainad a data bit then no clock bit will be generated.
3) If the previous data cell and the present data cell are vacant then produce a clock bit in the current clock cell.
The terms 'data cell' and 'clock cell' are defined by the state of the WCLK. While WCLK is low it is a data cell and while high it is a clock cell. It can be seen then, that both clock and data cells are 1/2 the period of WCLK or 100 nS for ST506 compatible drives and 115 nS for SA1000 drives. Also, note that ,by the rules stated above, a clock and data bit can never occur within the same WCLK period and legal spacings for bits can be 1, 1.5, or 2 times the WCLK period only. The ~ules are implemented within the device by shift registers that hold the next two, last and present data bits and combinatorial logic. The state of WCLK is considered and the appropriate bit cells are filled and combined on the MFMW output line of the device.
Write Precompensation
The MFM data stream is now totally compatible with the recording rules and may be sent to suitable line drivers for transmission to the drive except for one modification. Due to the decreasing radius on the physical surface of the disk, the inside tracks have less circumference and therefore exhibit an increase in recording flux denSity over the outside tracks. This increase in flux density aggravates a problem in magnetic recording know as 'dynamic bit shift.'
Dynamic bit shift comes about as the result of one bit on the disk (a flux reversal) influencing an adJacent bit. The effect is to shift the leading edge of both bits closer together or further apart than recorded. The net result is that enough Jitter is added to the data recorded on the inside
tracks to make them harder to recover without er.ror · '
Write precompensation is used to reduce the eff~ct of dynami~ bit shift. It is a way of predicting which direction a particular bit will be shifted and intentionally writing that bit out of position in the OPPOSite direction to the expected shift. This done by examining the next two data bits, the last ahd the present bits to be written and producing three signals depending on what these bits are. The three signals are EARLY: LATE and NORMAL. . They are used in conJunction with a delay line to cause the leading edge of a data or clock bit to be written earlier, later or on time.
The processor can enable or disable the generation of these signals by controlling the Write Pre-Comp (WPC) line from the addressable lat6h. When
51

HDC-2001 HARD DISK CONTROLLER Technical Manual

WPC is high, precomp is in effect. When WPC is low, no precomp is generated and the nominal output of the device is held true.

The delay line actually performs the precomp with the help of an

AND/OR/INVERT gate. MFMW pulses are applied to the input of the delay

line and depending on which of the three precomp signals is present the

AND/OR/INVERT gate selects a different tap on the delay line. Nominal data

is actually tapped from the second tap. Early data from the first and late

data from the third. From the AND/OR/INVERT gate the MFMW data is sent to

the input of an RS-422 driver where it is converted to a differential form

~nd then is sent to the drive.

The source or destination register inside the HDC-2001 is selected by accessing the addt~ess of the desired register. Since the access time for any particular read or write operation will vary, the HDC-20~1 provides a not ready signal (WAIT-). For systems using interrupts and/or DMA, the
HDC-1001 provides INTerrupt ReQuest (INTRQ) and Data ReQuest (DRQ).

7. 6. 1. Wait Enable

Since most of the registers in the HDC-2001 are not implemented in
hardware, it takes the 8X300 a finite amount of time to actually fetch the requested data on a read or store data on a write. This time varies depending on the amount of processing the 8X300 must do to access the
desired register. After the data has been written or ,read, the HDC-2001 de-asserts the WAIT- line, allowing the host to terminate the current bus cycle.

The generation of the WAIT- signal is controlled by a bit in the MAC latch

called WAit ENable (WAEN-).

If the HDC-2001 is ready to accept

random accesses to its task file, WAEN- will be asserted. The leading edge

of CS- clocks the wait line (Support Logic Chip) transferring the WAEN-

state· through the chip. This clocking action is required to insure that

WAIT- will not be asserted in the middle of any bus access already in

progress. After the wait latch has been clocked, CS- causes WAIT- to be

asserted to the host.

The WAIT- li~e is released on the trailing edge o~ any read or write strobe to the comMunications latch. This rele~se is caused by the logical OR of
RD6- and WR6- which presets the wait latch to a non-wait request condition. The WAIT- signal is stretched to the trailing edge of the RD6- or WR6-.

If WAEN- is de-asserted, the HDC-2001 generates no waits at all. In this case~ the host will read the dumMY status written to the communications latch by the 8X300. This feature is used by the microcode to simUlate a busy condition when the host reads the status register in non-interrupt driven systems. When the HDC-2001 becomes un-busy, the WAEN- line will be asserted and operations on the host interface bus will be monitored once
aga in.

HDC-~001 HARD DISK CONTROLLER Technical Manual

QE I~~QBY

QEsBaI!Q~

The S-100 pin that receives the wait- line is selected by the Jumpet~ at location G. 61-2 is for selecting XRDY-, 82-3 is for selecting PRDY-.

7.6.2. Bus Gating
During all accesses by the host, one of two signals will be produced to gate the bus. During read operations, CS- and RE- are ANDed, producing Bus Output Control (BOC-). This signal gates the contents of the communication latch onto the DAL bus. During write operations, CS- and WE- produce Bus Input COY'ltt~ol (BIC). This signal latches the state of the DAL lines irttl:) an internal RIS latch.

7 .. 6. 3a Register Selection
The combination of a host read or write operation along with the WAENsignal being asserted, causes a signal, Card Select ACcess (CSAC), to be generated. The 8X300 samples this signal every 250 nS, and if asserted, reads the status of A0-2 and WE-. The state of A0-2 and WE- determine which register is to be accessed (A0-2) and in what direction that access will take place.

7 .. 6.4. Inter~upto and DRQs

The HDC- 001 produces INTerrupt ReQuests (INTRQ) to signal the end of all
disk operations and Data ReQuests (DRQ) to signal data ready to DMA controllers. INTRQ and DRQ originate on the MFM generator as an auxiliary function of the chip. Interrupts are cleared by HSAC- (Host Select Access) and A0, Ai when the host reads the Status register, issues a cOMmand, or
accesses the Sector Number register. DRQs are cleared when the host accesses the Data or Cylinder Low registers. DRQs will be re-issued for each byte to be transferred. HSAC- is a 200 nS version of the CSAC--
Signal, which is produced by the Data Separator Support Device (WD1100-08). During Power-On Reset or Master Reset (MR-), INTRQ and ORQ are reset.

The destination of INTRQ- is selected by Jumper area H as shown in tabl~ below:

lrrt~~!:.!:!et bin~
VI0 VI1 VI2 VI3 VI4 VI5 VI~ VI7 INT

p.:)s i t i or.

7. 6.5. Address Seloct
The address at which the HDC-2001 board responds on the 8-100 bus ia determined by the address switches (U16.) Switches 1 through 5 select the upper 5 bits of the address (A7-A3) which the HDC-1001 acknoledges. A closed switch equals a 1 and an open switch equals a 0 for that addres~ 1 i nee

I~sgB~ QE QEEB8IIQ~
\'~ I
54

HDC-2001 HARD DISK CONTROLLER TechnicAl Manual
.'.,
8. M A I N TEN A NeE
The HDC- 001 ~aquires no scheduled preventative maintenanc.. The~e are three adJustments associated with the data .epa~ation circuitry that may· need to be adJusted i~ a drive with a different data rate is installed. The HDC- 001 is available in two different ways, the HDC- 001-8 fo~ 8" drives and the HDC- 001-5 for 51/4 11 drives.
55

HDC-2001 HARD DISK CONTROLLER T.chnical Manual

To facilitate the process of acquiring ph~s. lock on data being re~d from a
disk, a hardware detector is utilized to indicate when the reali/write head of the drive is over a recorded field of all ones or all zeros. The detector dapend9 on the timing of a one-shot (U4) which is adJustable by the DRUN pot (R14). DRUN Must be adJusted according to the following procedures:

Th~ DRUN adJustment is made with the HDC- 001 in an operating test configuration with a host, drive and power source.
Monitor DRUN- (U4 pin 7:) with a 10X oscilloscope probe while attempting to read a sector of data from the drive. The scope should be set to trigger on a high to low transition. While observing DRUN-, adJust R14. The period of the DRUN single shot should be adJusted to 1.25 times the per i od o'f RCLK.-
Disconnect all test equipment.

+------------------------------------------------------------------------+

Yl:&2 Frequency

DRUN Period

Freq. Range

Final Setting

+-------------------+---------------+---------------+--------------------+

+--2-0-.-0-0-0--M--h-z-------+-----2-5-0---n-S----+--9--.0---1--1-.0---M-H-z-+I ---1-0-.-0--M-h-z--+-/---1--K-H-z-+I

+--1-7-.-3-6-0--M-h-z--------------2-8-0--n-S---------7-.-5----9-.-5--M-H-z--I----8-.-6-8--M--h-z-+-/--1--K-H-z-+t

OSCILLATOR FREQUENCY
Data separation circuitry on the HOC 2001 uses a voltage controlled oscillator (YeO) which phase locks onto incoming data & provices a lock suitable for separating dat.a lock bits or an MFM erroded data stream. The VCO must be adjusted using the following procedures:
-Disconnect jumper J: Then make all connections to the board, including the host & drive. Connect a frequency counter t.o the VCO buffered output on TP8 (U14 PIN 10). Adjust the variable capacitor C15 until the frequency output locks onto the desired center frequency fo~ the drive being used which is 10.000 r4Hz for ST 506 or 8.68 MHz for SA 1000. Once this "locked on" frequency is achieved an input voltage of U14 pin 1 of 3.00 +/- 0.5 volts will automatically occur.
BALANCE ADJUSTMENT:
Tbe balance adjustment fine tunes the relationship of delayed data
(DLYDAT) to read clock (ReLK). Attach channel 1 of a dual trace oscilloscope to U23 pin 1 (ReLK) set scope for 20 NS/DIV with a positive
slope. Attach the other channel to TP7 (DLYDAT). While the controller is doing constant reads t.o single sector, adjust C15 (if needed) so that the edge of DLYDAT is roving to the right or left with respect
to REm until we have the "right capture value".

Right Capture Value

/--------1-------1-----\

IIRCLK- II I

______1 I

\ , __________________

Left Capture Value--) I
I _______________---------

IIDLVDAT II

----------______1 I

REMOVE ALL TEST EQUIPMENT.

HDC-Z.001 HARD DISK CONTROLLER Technical Manual
A. DIS K D R I V E R E X A P M L E
Sometimes an example is worth a thousand words. Hopefully, these saMple disk drivers will be the catalyst to get your first driver running. Note that even though these drivers are very simplistic, they represent everything needed to satisfy the HDC- 001 operating requirements. As you Might notice, there is no retry software included in these examples. That is because the HDC-2001 does all needed retries. Two examples are presented. The first is a programmed I/O, prograMmed status driv~r using the eight bit Intel 8085 microprocessor. The second example' is prograMmed I/O and interrupt driven and is written for the sixteen bit Western Digital WD16 microprocessor.
59

HDC-2001 HARD DISK CONTROLLER TechnicAl Manual

;*********************************************;

HDC~001 Hard Disk Controller Driver

;

Example for 8085 Microprocessor

;

with programmed lID and polled status

;*********************************************,

rThis driver is intended to demonstrate one simple approach to writing a
;driver for the HDC-~01. It assumes that the HDC-2001 is interfaced using ;progra~med lID without interrupts.

;The specifications of the imaginary demonstration drive are:

;Sector size:
;Sector per Track:
;Surfaces per drive: ;Cylinders per drive: ;Stepping rate:
STRATE = 2

256 bytes
33
4 (two platters) 512 2 milliseconds ;Define stepping rate for assembler

;Since we're allowing the HDC-2001 to map around the bad blocks for us, we
;have to sacrifice one sector per track. This brings down the logical ;sector per track count to 32.

;Experienced systems programmers will note that we are not making our
;drive as flexible as it should be. Since HDC-2001 compatible drives will ;be introduced in the future and present manufacturers will be increasing ;the density of their current drives, the driver that you write should be ;built with plenty of equates and conditional assemblies.

;Our imaginary operating system can access up to 65536 logical records of
;256 bytes each. It has three types of calls: Initialize, Read and Write. ;Three numerical parameters are passed in the following registers:

Drive number

Logical record number

Transfer address

;Upon completion of all commands, the carry. bit ~f the 8085 will be reset
;if the operation terminated properly, and set if there was an error. If ;there was an error during read or write, the error handling routine will ;decode it and print it out on the user console.

HDC-2001 HARD DISK CONTROLLER Technical Manu~l

gl§~ ~Bl~&B g!8~eb&§

., ;***********************;

;

Equates

;***********************;

;*** Port Definition ***

BASADD

= DCa

DATA

= BASADD .

·ERROR

= BASADD+l

WPC

= BASADD+l

SECNT

== BASADD+2

SECNO

BASADD+3

CYLLD CYLHI SOH

BASADD+4

BASADD+5

= BASADD+6

STATUS = BASADD+7

CDMND

= BASADD+7

;Base address of HDC-2001 ;Data register ;Error Register ; Wl"i te Precomp ;Sector Count ; Sect 01''' Number
,Cylinder Number ;Cylindel" High ;Size/Head/Drive
;Status register ;Command register

;*** REST READ
WRITE

Command Definition

10'

= 20

= 30

*** ;Restore command ;Read command (programmed I/O mode)
;Write command

A. 1. 1. Ini t ial i zat ion

;*************************;

;

INITIALIZATION

;

;*************************;

;This routine is called once whenever the system is powered up or reset. ;It sets the stepping rate and restores the head on the selected drive.

RESTOR: RSWAIT:

CALL
MVI OUT
IN ANA JM
RAR RET

UPTASK

;Select drive, don't care about record

A,REST+(STRATE*2) ;Get stepping rate and restore

COMND

;Output command to HDC-2001

STATUS

;Wait 'till restore done

;by updating sign flag in 8085

RSWAIT

;and wait 'till bit 7 (Busy) goes low

;Put error bit in carry

;Return to operating system

HDC-2001 HARD DISK· CONTROLL·ER T·eehnical Manual

A. 1.2. Read Sector'

i******************;

;

READ

;******************;

;This is the read routine for our imaginary operating system.

READIT: CALL UPTASK

;Update HDC-2001 task file

MVI A,READ

;Get READ COMMand

OUT COMND

;Output command to HDC- 001

; Wa i t· f Cit.. HOC- 2001 to t"ead i Y. a sect or

RWAIT: IN STATUS

;Check Busy bit

ANA A

;by updating sign flag in 8085

RWAIT

;and wait 'till bit 7 goes low

;Transfer sector from HDC- 001 to system memory

; (Transfer address in HL) .

MVI B, a

;Init byte counter to 256 bytes

READLP: IN

DATA

;Get a byte of data from HDC-2001

MOV M,A

;Move it to memory

INX H

;Increment memory pOinter

DCR B

;DecreM~nt byte counter and continue

JNZ READLP

;if we haven't transferred 256 yet

STATUS

iRe-read status for errors

JMP DONE

;Now check the completion status

HDC-2001 HARD DISK CONTROLLER Technic~l ManuAl

A.l.3. Write Sector

;*******************;

;

WRITE

;

;*******************;

;This is the write routine for the driver

WRITIT: CALL

UPTASK

;Update HDC-2001 task file

MVI

A,WRITE

;Get WRITE command

OUT

COMND

;Output command to HDC-2001

;Transfer sector from system memory to HDC-2001

; (Transfer address in HL)

MVI

B,O

;.Irlit byte CCIUYlte.,,, to 256 bytes

WRITLP: MOV

A,M

;Get a byte of data from memory

OUT

DATA

;Move it to HDC-2001

INX

;Increment memory pointer

OCR

;Decrement byte counter and continue

JNZ

WRITLP

;if we haven't transferred 256 yet

;Wait for HDC- 001 to write the sector

WWA IT;

I N

STATUS

; Check B'Jsy bit

ANA

;by updating sign flag in 8085

WWAIT

;and wait 'till bit 7 goes low

;******************;

;

DONE

;

;******~***********;

;Both READ and WRITE commands finish here to check for errors

DONE:

RA~

;Rotate Error bit to carry

RNC

;and return to OS 'is no error

ERROR

;Get HDC-2001 error ~ode

;«( Place error reporting routine here»)

STC

;Set carry to flag an error

RET

;and return ~o OS with error

HDC-2001 HARD DISK CONTROLLER Technical Manual

A.1.4. Task Fila Updating

.;**********************************;

;

UPTASK SUBROUTINE

;

;******~*******~*******************;

;This subroutine sets up the task file registers

.; Sect ell''' Y"IIJmber
UPTASf:{: MOV ANI OUT

A,E
31. SECNO

;Get lower 7 bits of record number ;Mask off lower 5 bits (bits 1-4)
land send to sector number register

; 8i ze/O""i ve/Head

MOV

A,E

RLC

ANI

MOV

e,A

MOV

A,e

ADD

ORA

ORI

OUT

SDH

;Get lower 8 bits again ;Rotate remaining 3 bits ito get an effective right shift of 5 ;Mask off next two bits (5-6) ito make head number ~and store it away momentarily ;Get drive nUMber land left shift it by 3
tOR in head number and lOR in ECC flag and size field ;send it to Size/Drive/Head register

;Cyllnde)''' low MOV RAL MOV RAL OUT

A,E A,D CYLLO

;Get last bit of lower record number land put it in carry ;Get.upper half of record number ;Left shift it and merge in carry ;Send it to lower cylinder register

; Cy 1 i.nge)''' high
MVI
RAL OUT RET
END

A,O CYLHI

;Clear all bits except for the ;the least significant and send Ito the upper cyli~der register

HDC-2001 HARD DISK CONTROLLER TechnicAl Manual
B. I N T E R LEA V E CAL C U L A TIN G UTI LIT V
This BASIC program simplified the process of generating interleave tables. It is written in a fairly standard subset of the BASIC language and should run on Many BASIC interpreters and compilers. Some implementations of BASIC may require the variable names to be converted to single letter names and the IF THEN ELSE constructs may have to be re-written. The two questions at the beginning of the program should be answered in decimal. The interleave is printed in hexadecimal.
65

HDC-2001 HARD DISK CONTROLLER T.ch~ical Ma~ual

~~!~ ~8§!~ ln~g~!~~~g ~~!£y!~ting E~2g~~m

10 20 30 40
50
60 70
80
90
100
110 115
12121 13121
140
15121
16121 170
18121 190 20121
210
220
23121 24121 250

PRINT"HDC- 2001 Interleave calculat i~g Pl'''ogl'''am"

INPUT" Number" of sect or"s? II ; COUN1

INPUT" Ir.ter"leave Factor?"; INTE~

DIMHEX$(16),SECTOR(COUNT)

FOR INDEX=l TO 16

READ HEX$(INDEX)

NEXT
FOR INDEX=l TO COUNT

SECTORCINDEX)=l

RES=0

FOR INDEX=0 TO COUNT-1

IF RES}=COUNT THEN RES=RES-CQUNT IF SECTORCRES+l)=-l THEN SECTORCRES+l)~INDEX ELSE RES=RES+l:GOTO 130

RES=INTER+RES NEXT

PRINT PRINTllly.tel'''leave table with";COUNT;"sectors andll;INTER;II: 1 interleave ll

FOR INDEX=l TO COUNT

X=INTCSECTOR(INDEX)/16)

PRINT HEX$CX+1);HEX$CSECTORCINDEX)-X*16+1),

NEXT'

DATA O,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F

END

HDC-2001 HRRD DISK CONTROLLER Technical Manual
c. S· E C TOR C R L C U L R TIN G UTI LIT V
HDC-2001 compatible disk drives are constantly changing. Higher bit packing densities and higher accuracy spindle motors help to increase the amount of data that can be put on a track. This appendix will help you to determine the maximum number of sectors that can be recorded on your disk drive. The unformatted byte capacity can be figured·from this formula:
Capacity=Bits per sec6nd 1 Revolutions per second x (i-Error) I 8
We'll take a hypothetical drive (the same one as in the disk driver examples) with a data rate of 5M bits per second and revolution rate of 3600 RPM. Our drive has a spindle speed accuracy of 3~. These numbers applied to our formula yield:
10, 104=5, 000, 000/60x (1-9.03)/8 To be on the safe side, we will always round down when we come up with a fractional value. The unformatted capacity of this drive is 10,104 bytes. To figure the number of sectors per some number of bytes apply this formula.
Sectors=Capacity 1 (Data field size+Gap3+Check bytes+Other overhead) Using 512 byte sectors with a Gap3 size of 30 bytes, running ECC w~ end up with:
17=10,104/(512+30+4+41) The BASIC program on the next page can be used ~o automate the sector per track calculations presented here.
67

HDC-2001 HARD DISK CONTROLLER Technical Manual

§g~IgB ~8b~Yb8I!~§

10 20 30
40 50 ' 60 70 80 90 100 110 120
130 140 150
160 17121 18121

PRINT "HDC- 2001 Sectors per Tl'''ack Calculat ing Ut i 1 ity" PRINT ,INPUT"Data l'''ate of drive iYI bits per second: ";DATARATE
INPUT"Rev,::.lutions per minute: ";RPM I NPUT II Rot at i ona 1 speed el'''ror in pel'''cent: "; RE RRO R
CAPACITV=INT(DATARATE/RPM*G0*(1-RERROR/100) IS)
PRINT"Unformatted capacity is "CAPACITY"bytes." PRINT INPUTIfData field size iYI bytes (128, 256, etc.) :";SIZE INPUT"F,:I)'"'matted wi th CRC 0)'"' ECC: II ;ECCMODE$ ECCMODE$LEFT$(USC(ECCMODES),l) IF ECCMODE$() If Elf AND ECCMODE$()"C" THEN 100
IF ECCMODE$="E" THEN CHECKBYTES=4 ELSE CHECKBYTES=2 IF SIZE>256 THEN GAP3=30 ELSE GAP3=15 SECTORS=INT(CAPACITV/(SIZE+GAP3+CHECKBVTES+41»
PRINT "Formatted capacity is";SECTORS*SIZE;"bytes per track PRINT SECTORS; IfsectCll'''S pel''' tl'''ack.'' END

IJsing";

HDC-2001 HARD DISK CONTROLLER Technical Manual ~BQ§Be~~gB§ QY!~~ BEEgBs~~5

D. PRO G RAM MER S QUI C K REF ERE NeE

+-----------------------------------------------~------------------------+

11--C-IS-----+1--AX-2---1+--AX-l---I+-A-X-0---1+-DR-E-e--s-e-l-e-c-t-e-d-----------+1--WD--Ee--s-e-l-e-c-te-d---------+I

1 0

Data Register

Error Register

Sector Count

Data Register Write PrecoMp Sector Count

Sector Number

Cylinder Low

Sector Number Cylinder Low

Cylinder High

Size/Drive/Head

Status Register

COMMand Register

+------------------------------------------------------------------------+

+---------------------------------------------------+

BITS

TYPE

COMMAND

765 4 321 0

---------+--------------+--------------------------

Restore

I 0 0 0 1 r3 r2 rl r0

---------+--------------+--------------------------

Seek

0 1 1 1 r3 r2 rl r0

---------+---------------+--------------------------

Read Sector I 0 0 1 0 D M L 0

---------+--------------+--------------------------

III

Write Sector I 0 0 t 10M L 0

---------+--------------+--------------------------

III

I Format Track I 0 1 0 1 0 0 0 0

+----------------------------------------------------+

L=Long Read/Write

D=DMA Read Interrupt

M=Multiple Sector

rX=Stepping Rate

HDC-2001 HARD DISK CONTROLLER Teehnical Manual eBg§B8~~&Be QYl~~ BEEEBE~~E

Bit Function

+-----------------------------------+ 1--7---+--6---5---+--4----3--+--2 ---1 ---0 ---1 +II --E---1I---SS-ei-zc-e----II---SD-er-li-ve-ec-t-11---S-He-el-ea-dc-t---+tI
E=ECC Mode

+--------------------------------+

1 Bit

Bit

Sector Size

J E,

1--------------------------------1

1 0

256 Bytes

1 0

512 Bytes

I 1

128 Bytes

+--------------------------------+

1 Bit

Bit

Drive Selected 1

1 1---4 -----3 ------------------------11

I 0

Drive Sel 1 I

I 0

Drive Sel 2 1

Drive Sel 3 I

+---1--------1 --------D-r-i-v-e--S-e-l--4---+

+---------------------------~--------------+

Bit

BIt

Head Selected

12101

1------------------------------------------1

Head 0

Head 1

Head 2

Head 3

Head 4

Head 5

Hsad 6

Head 7

+------------------------------------------+

+--------------------------------------------------------------+

Bit

Status Register

Error Register

1-------+-----------------------+-------------------------------+

I 7 I Busy

Bad Block Detect

1 6 I Ready

Uncorr~ctable

Wr i t e Fa J.l .l t

CRC E t"r6t" - I D Fie I d

I 4

Seek Complete

tD Not Found

Da_ta Request

Corrected

Aborted Command

TR000

Error

DAM not found

+-----------_._----_._--------------------------------' ---------------+

JUMPER MODIFICATIONS ON HOC-2001

JUMPER A: Located between U9 & U15 - These jumpers are designed to select TI~LR. If we are using SA1001 drive, you must jumper 2 to 3.

JUMPER B:

Located below U13 on the left hand side of Jumper C. This jumper area is desi.gned to send a ready wait signal to extend the processor eyc Ie. Depending on how the rraster processor is designed to look at either XRDY or PRDY. If you are using ADVANCED DIGITAL I S Super Quad or Super Six you must jumper 2 to 1.

JUMPER C: Located between jumper B & D. This jumper area is designed to select slave CLR, POE (power on clear) or reset mode.

JL~ER 0: Located on the top left corner of U20. These jumpers are designed to se lect DRQ (DMA-request; Other 2 jumpers reserved for future use.

JUMPER E, F, G, & H These jumpers are designed to select drive 1,2,3 & 4.
With the new 8X305 processor on board, it is not required to jumper these pins because the 8X305 will generate drive select inside automatically.

INTERRUPT JUMPER: Located on the left hand side of U20. 'rhese jumpers will
depend on master configuration.

SI POSITION: The Sl on HOC 2002 is to determine the port addressing. ADVANCED DIGITAL software is set up to look at port E0 which is the hard disk controller base address (SQHOC.MAC). SO the position of the switch must be:
123 4 56 7 8 ON ON ON ON ON OFF OFF OFF

Switches 4 through 8 select the upper 5 bits of the address (A3 - A7). A closed switch (ON position) equals a 0 and an opened switch (OFF- position) equals a 1. To select a 0E - 00H address (1110 - 0XXX) address A3 & A4 will have to be low and address A5, A6, A7, wi 11 have to be high. So the switch 4 & 5 have to be in the ON position (equal 0) and the switch 6, 7 & 8 have to be in the OFF postion (equal 1).

HDC-2001 HARD DISK CONTROLLER Technical Manual
E. 0 PER A TIN 8 8 Y 8 T E M 9
1. CP/M on 8 11 or 5 1/4" versioYI 2. Turbo-Dos on 8" or 5 1/4 " version
71

HDC-2001 HARD DISK CONTROLLER Technical Manual F. D RAW I N G B
72

PART NUMBER
741S74' 7l.LS191
~C3487
74LS54 WDII00-12 WDII00-06 74LS174
A.\.f2149-70DC
745124 74574 wl)1100-03 10.1)1100-05 74LSOO 74LS14 74LS367 LP411 WOll00-01 74LS244 74LS688 . TPQ6700 WOI100-08 74LS08 . 8T31 74LS241 AM26LS32 74S64 A.\.f26S02 h1H 100-07 DM7406 74LS273 74LS374 74L138 74LS137 74LS32 74LS259 74500 74LS175 82S181(FIV) 82S181(MSB) 32S181(L5B) DL6710 7438 74S04 8X305
..

PARTS LIST

HDC 2001
Rev. C

QTY

REFERENCE DESIGNATOR

MFG

DESCRIPTION

NOTE

U3, U4, US

U6, U7

UI0

Ull

U12, U13

U14

U15, U22, U23

U16

.1
U17

U18

U19, U44

U20, U27

U21

U24

U25, U31

U.f 6

U28

U29

U30

U33

U33, U45

U34

U35

U36

U37

U38, U46

U39

U40

U41

U42

U43

U47

U48

U49

U50

U51

U52

U53

U54

U55

U56

TOTAL IC SOCKET:59 (58 HAVE BEEN US! 14 PINS: 20 16 PINS: 16 20 PINS: 15 18 PINS: .2 24 PINS: 4 50 PINS: 1 8 PINS: 1
·· ·· NOTE: U2 DO NOT USE

PART NUMBER

QTY

.1·.MF

10 MF

.22 MF

22. ~F

220 PF

150 PF

68 PF

47 PF

33 MF

IN4148

OSC 20.000 Mhz

OSC 8.000 Mhz

10K SIP

220/330 SIP

2N 3904

2N 5320

4.7 Mh

4-20 PF POT

LM 323(78L05)

79L05

1K OHM

1.5K

4.7K

5.6K

150 OHM

2.4K

1.6K

110K

330 OHM

680 OHM

220 OHM ~W-1%

51 OHM

499 OHM ~W-l%

3.3K

5K POT

200 OHM

10K

PARTS LIST

HDC 2001 Rev. C

REFERENCE DESIGNATOR

C1, C2, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C17, C18, C19, C20, C21, C23, C24, C26, C27, C28, C29, C31, C32, C33, C35, C36, C37, C38, C39, C40, C42, C43, C44, C45, C47, C48, C49, CsO, C52

C14

C16, C51

C25

C22

C30, C34

C41

C46

GR1, CR2, C43, CRu,

CR5, CR6, CR7, CR8,

CR9, CRI0, CR11, CR12,

CRI3,

RPl

RP2

Ll, L2

CIS

VR1

VR2

Rl, RIO, R27, R35, R37,

R42

R2, R39

R3, R33, R41

R5, R12

R6, R7

R11

R13

R14

R15, R16, R17, R18

R19, R20, $21, R22

R23, R24, R25, R26

R28

R29

R30

R31

R32

R34

MFG DESCRIPTION

NOTE

CAPACITOR
" " " " " " " " "
" " " " " " " "
DIODE
IJ
" "
OSCILLATOR OSCILLATOR SIP RESISTOR SIP RESISTOR TRANSISTOR TRANSISTOR COIL VARIABLE CAP VOLTAGE REGULATOR VOLTAGE REGULATOR RESISTOR RESISTOR RESISTOR
" " ",_,
"

CRYSTAL CRYSTAL
N~TWORK
NETWORK NPN NPN

VARIABLE RESISTOR
RESISTOR
" "

PART NUMBER
27K 10K IISK 820 OHM

PARTS LIST

QTY

REFERENCE DESIGNATOR

R36

R38

, R39

R40

HDC 2001 Rev. C

MFG

DESCRIPTION

RESISTOR
" " "

NOTE
I

A2.. 81
31 82.
33

~4 '3p

Ii(>

A'5 29 I-..___---=G.'-!

)

?F'V{
':.,L~\J E e.G\.
\<ESEi
poe

\lI¢

\Jr I \Jr. 2-

)

vI,

\)T 4

\JI. 5'

\Jr~

-.J!.7

INT

2..

REV'S'ON~ .

LTR

DESCRIPTION

DATE

APPROVED

TOLERANCES UNLESS OTHERWISE SPECIFIED FRACTIONS DEC ANGLES

c,c~·f1-tta-·-.· .:t.t..~.{

:t:

'SbcL , ±

~--------~----~~~--t~M-·-~:4-t.~r. -----

APPROVALS

DATE

DRAWN ~
:..---
CHECMID

SCALE
NO

SIZE DRA~NO.
B \( r ~-)".-': i'\ . - "-.-

00 NOT SCALE DRAWING

4 SHEET IIJ~

12.

-t5V

c..2.b .IJ-lr;
eRe
+5V

U2B

TPQ fo7¢¢

t-t:)v

I I

'TP2 -;

Ilf '-( UI

B Yl
CKy~TAL

1 L~/~
3~ Q C

?eJ.rJ>0tt

J: l'~ PllP'

VR 2 f--....--I_rJ-I

1-0_"'.'...._ _ _ _ _ _ _ __

79Lq'>S

(_T-_P"~3_.J'

I I

12-

REVISIONS

0 PUPI~ T-+------------~~--------~

O\¢

.12- D Q 9

12. D

~~ fPf_)

-'"'( LJ

~74
> ~ U2.~

sl S7~
U\S"
~> Q

RDA1(B\ 9)

113

L'~

--..

_0 4

114 ,PUP 1ft>

ZD ~ 5

S7Lf
>U2."b

>U G] 2- D

574

3
~

I 5_

~ ~'pj]p~. _ c:Li?:!.

y, " RCLI<

(~19) L-.( RC.L\<. (e.lq)

(e.19)

--J... RGATE (B9)

IDATA SEPARATOR I
05(, (BIQ'»

NOT~

~ CRt) CR2) c..R~} c..R4 ,(R.5

GR.". C.R7, GR8, ("R9, C.R I¢

= o,..d. C.R \ I

I N 4 , 4 E>

/0 ~ OS (. = Up M \1 Z ±. .¢ r/J I

, I
OL~71¢1--- pe$ <. OS")

RI?>
c.2L! 3~¢ PF

14
~-----------~

ul4
74S124

let>

TOLERANCES UNLESS OTHERWISE SPECIFIED

fRACTIONS DEC ANGLES

APPROVALS

DATE

DC- 2..00\

SCALE
NO

B \-, ,.- SIZE DRAWING NO. \J r~ . ,,,", l--= ¥ . -

DO NOT SCALE DRAWING

/2.

IM \ C.RD (ONTROLLEK.\

(DI8) \)J R7 '

I'=-

REVISIONS

LTR

DESCRIPTION

I DATE

APPROVED

PuP "3 5)'----+11-8-...1.19

q IO(/) 28

::rD'

_=I;...;;A=2..._._~_

_? 1'0 "

1\., TAo ~

~.
LSB

" JA ~

"- ~A?

'S' :105

r'"
I'"

~7A~7b

(

Ib IDE.

I B'2sISI/191 ,7 ;rD7

!LJ

t'--- . ~ .lA. ~ 8 -~

u52
1\.._1;..A_/~rf;__2_J~

..... It:. I

MsB

13 ID II

14 :rOIL. Ib

f-!U.!?I3>:.-_...:.'S_1

J" ID 14

82S ISI/ 191 17 :tD ,;:

"LA'" ../

";8 ]:04 ~9 1.05 lj¢ I.06
~I 107

C.E 11+

X v
RESFT (E 14)

~_1-''"''r-.-f-.Ic4'

U4
LCSl91

II 51

.....\ , _ _ - _. _____ .._ _ .

+'5V "IOJi 1'5

__---+--+--..-------..-~oS... \
[.;..-._ _+-_+-_ _ _--.::!:I~06~I~¢1
1'07 q

I~ 12 11
UI~ 21~91-\-

:rO\

\1-

t - - + - - - - - - : . . ! . . .1.4'"I'

u3
L~f91

__ ~----1I--1---------~--5--V_~ ___-±r~o~¢~I~
~----_r--_r-------------- --~r~O~/-U1
II ....

RA3 17
~'-_+_RA-4~7~
'3 RA8./ r-...._... -+R-_A_S_6-J
t-2_ . _~_f.>.;.,;...9__/ ·...._...-+--K.A_"~5_1

12.. 106 \\ :107

RA7 4

---~ wR.2.

(\) 18)

U~ LSl91
51

RAe ,(, P.A9 15

U\2.
21~ 9~ wt
~¢

I/~~~-==-----------------------------------------------------~~------======j~~

l',lA9
[\.. IA I cD i I

u5J

u55

)

430

~~ _ MtL'-CD I7)

L"'" · \..AD
,-''''

II '>--_~

, .....

(5.2.) ,

. .J5i'';)--'''-.......:...--....j~~ MO..\<. (B4 I D' 6)

II S~

u'55

~-~'5-n
(~5>A\~, 5)17,C.'5)

2N39¢4 .J.._..-..:..I=-I' u54
'1 7438 QI

APPROVALS
DRAWN ~
CHICKID

DATE
loJ-;q/~~
SCALE
NO

SIZE DRAWING NO.
B ~r=\1 C~

RlORO£R NO 20621

I!>

15"

DO NOT SCALE DRAWING

4 SHEET 3 OF

c.:'.,..

2 2

2 ~.

2Lt

~J}>~)

- ( A4) IO rp -IO 7

REVISIONS

LTR

DESCRIPTION

DATE

APPROVED

( DI7)R04
- 119

01-S"--e>____-c> ,\ t-'\ 0 G1
GC>\l,- ~ N.(.

ODd> 17 DOl _ 2-
VOO2.. 15
Vpo~ "
VOO48
VOO5"
~/00(0 l~

C>
uz..5""
LS244

~ roq, .-I I\...
n~ IOI ./ i\...
5 102. ./ ~ 14- ~o?, . / I\..
12- I04 ..,Ir-...
9 1.05 ...,Ir-..
7 IO~../

I,. ocj 2.1'\ DI
3 CZ"
4,.. D?> 5 ':)4 .
~,... 05
7 0"-

- WBS(c. 19)

BOONE (A 4)

/007 4
V

__ I{" 107..,1

8", 07

(P18) WP-If

I'~
>--;-::-0

WOU\lI 7~-S"

(c...I/J)\1KL\(' " 1 12----.

.. ...,

-- ~5V
Ifl 12..1
~'JT f..+ ~

_ ~---------------------- ___________~____________________________~~19

)vT A· '5'

tRD4 CDI1)

3 4

1'S------......----.;,8--<", N R'l.. I-II'-'-_-+_--...:.''V~ c.u..

5 DO~./
(p 001./

r1- N.t

7 J)Ol.../

111;:;C.~1~ -;u:p;El

(~s) C.RC./ ~ CL .....>---11-----61 lA,I?) ~cc. I c >.-...-~----7;
(A 15) If! LIII ~)----lf-----:"\"7:~ l<..b) Rf:JS ~)----lf-----:I;~~ <J>l.~) \NBS >>-~I------='\-9i

~N.c..
r!1- LJlrP ~ N.t. N.(.
WOII~1-rpf, ~NC.
~NC.

18 Co~./

9 D04../

WDII~-~I

11 OOS../
2.. DOra""';

UZ lt 13 007

!=:lR. <;",. 1:j¢1 I
I1 _ _O_ NL_ Y _ -I

IS:;

~N.C. (e,9) "'nj; ,.,,>--,,::;z-:-IFL -- --:

--l ---------~-----~91~j~
r-(_B_\_¢)_T_'_2.._~_-....;.I-=-~':~-;1 /

r-I:TP4~
_ : ~

0'J"rC +

U" '"c.- J·.),T

Z JIJT ~,,,

:)UlO- 3

}\lTD 4 14

Q\)T 0- l?

DUPI

~~1 ~--~------~~

\, NOM
,'2.. LATE'

(~\¢)Tl4 ,,>----:I~~.:..I-I
r-_I",;;;~.;-I....J.
I ~I 2. 1

UBI

LS5't I
,I

!_ - - - - - - __ I

+5'-1
~

R?>'5
_AA VV'"

- puP ~5

_P.!"!~ {'UP 27

,..-.-..'R-vTviv----o PIJP\9

Pol
. AvAvA

J'O puP \

'34
I~
9 ~
' - - - I~

"\~

I...!..J
'.:
.~
~
.z:..r.

2+
~~

:)
II

0Ni

1-:

I:..

2/>

ifJTRQ. COb) MFMW CPJ9)

I I SI;'R I Al DATA 'tJT(R~A.(E

TOLERANCES UNLESS OTHERWISE SPECIFIED FMCTIONS DEC

-"-

APPROVALS

DATE·

DRAWN ~ JO/l'l/91.(

CHICKED

SCALE
NO

SIZE DRAWING NO.
B fe\ c,-yr'-'

22.

DO NOT SCALE DRAWING

SHEET lJ ~- 4-

I 24

BIPOLAR LSI DIVISiON
USERS MANUAL

JUNE 1982
8X30S

Chapter 1

INTRODUCTION

This manual provides the system designer with a complete technical discussion of the S'gnetics 8X305 Bipolar MicroController. The first two chapters address the functional operation of the 8X305, Chapter 3 is a reference for the device instruction set, Chapter 4 discusses timing considerations, and the final two chapters deal with ap· plication of the device.
The 8X305 Data Sheet provides complementary data to this manual, fncluding detailed timing and electrical characteristics. The 8X300 Family Product Capabilities Manual discusses the 8X305 in the context of the many compatible support devices available from Signetics. Together, the three documents provide the information necessary to design and implement a system that takes full advantage of the powerful features of the 8X305.
The Signetics 8X305 Bipolar MicroControlier provides a real alternative to the complexity ot bit-sljce designs and the relatively slow speed of MOS microprocessors in high performance, cost effective control systems.

1.1 DEVICE DESCRIPT!ON
The 8X305 MicroController (Figure 1·1) is a monolithic Central Processir1g Unit implemented in bipolar Schottky technology. It is designed to operate at a speed of 200 nsec for each 16-bit instruction, fetched on a dedicated bus for higher throughput. It controls a series of peripheral devices which are attached to it by means of a standard a·bit bus known as the Interface Vector bus and its associated control signals. The 8X305 can be easily integrated into most support systems using 8X300 Family support devices.
The 8X305 is upward-compatible with its predecessor, the 8X300, allowing enhancement of existing MicroController systems. Software written for the 8X300 will function correctly on an 8X305. but the expansion of the instruction set and ~nterna! working storage allows more flexible manipulaiion of data, higher throughput. and simplification of code. Care should be taken, however, in analyzing signal a:1d Hming requirements for each application where the MicroController is to be updated.

Figure 1·1 Archlh ctural Overview of IJX305 Mlcjot;ontroller
Signetics

· BIPOLAR LSI DIVISION -
USERS MANUAL

aX30S

The 8X30S is designed to provide the optimum combination of features for controller design:
· Powerful, simple instruction set · Eight instruction classes · Single chip package · Bipolar speed · Family of compatible peripheral devices · Flexible bit manipulation in a single instruction
· Single + S volt supply
· TTL three-state bus operation

-1.3 PIN DESCRIPTION
The 8X30S MicroControlier is housed in a O.g-inch wide, SO-pin Dual In-Line (DIP) package, with pin assignments and designated functions as indicated in Figure 1-2.
1.4 THE INTERFACE VECTOR BUS
The 8X30S communicates with peripheral devices by means or a bidirectional, 8-bit TTL bus known as the Interface Vector, or IV bus. Five control signals generated by the 8X30S indicate the direction in which the bus is being driven and the configuration of the data or address on the bus.

1.2 DEVICE ARCHITECTURE
An understanding of the internal architecture of the 8X30S is required to maximize the efficiency of a design. Figure 1-1 illustrates the logical structure, but does not necessarily represent exact physical connections within the device.

Devices connected to the IV bus are commonly refen-ed to as I/O Ports. Anyone of up to 2S6 such devices can be selected in a single cycle when the 8X30S places the I/O Port's unique address on the bus and asserts th'e.Select Command (SC) Signal. Once selected, an I/O Port normally remains selected until the SC Signal is again asserted with a different address on the bus.

The instruction arrives at the Instruction Register from ~he Instruction Bus (1 0-1 15), It is interpreted on the basis of the Op Code which defines the significance of the other bits in the instruction. Data paths within the chip are set up by the Decc;>de and Control logic. External control signals are dlso generated by this logic. At a later point in the cycle, the Program Counter, Increment Logic, and Address Multiplexer generate the address of the next instruction to be executed and place it in the Address Register. The address is then placed on the Instruction Address Bus (Ao-A1~ to fetch the next instruction.
All timing is generated by an on-Chip oscillator running at twice the actual instruction cycle speed.
Source data can be accessed from three locations:

The direction of data flow is indicated by the Write Command (WC) signal. This signal is asserted when data is being placed on the bus by the 8X30S, and is not asserted when data is being read from the bus. The data will normally be read from or written into whatever 1/0 Port was last selected.
To optimize the 8X30S's capabilities in data manipulation and device selection, two control signals knoyvn as Left Bank (LB) and Right Bank (RB) are provided. These signals are asserted concurrently with other control signals based on the contents of the instruction word. They can be used in conjunction with the other signals to determine which I/O Port will be enabled at any given time. They can be used in a variety of ways, but the two most significant are as follows:

· 16 internal registers · The IV bus · Absolute or modified constant speCifications from the
current instruction word
Data from external sources can be manipulated by means of the Rotate and Mask Logic before becoming the first operand for an ALU operation. The implied second operand is the Auxiliary Register (AUX or RO). The result of the operation is stored- in an Internal Register or transmitted to the IV bus.
The sixteen 8-bit registers contained in the 8X30S are used as temporary storage of data and pointers. Three of these registers have special applications for IV bus address transmission and flag storage, leaving thirteen available as general-purpose storage.

1. The optimum performance of the MicroControlier can be achieved by connecting the input I/O Port to one bank and the output port to the other. The two ports can then be selected concurrently and data can pass between them in a single cycle, resulting in a transfer rate of five megabytes per second.
2. Since the bank select signal (LB or RB) must be asserted for a port to be enabled, two ports may share the same address provided that they are connected to opposite banks. This expands the number of I/O Ports that can be addresC3ed in a single cycle to S12.
Timing on the bus is synchronizbd with the Master Clock (MCLK) signal. Together with the other control Signals, it enables the 110 Ports to access the IV bus at the correct points in the MicroController's instruction cycle.

78 - B

BIPOLAR LSI DIVISION
USERS MANUAL

JUNE 1982
aX305

YCIIIT
A, IT At IT
At!!
a.e!: AlE!:
AlIT
A,E!
""IT
.,~
X2E!
ONC@
Io@
11E! lIE!
I,E!
I.@
11f!! leE!
,,~
leI!! IelE
I,.§
lu[E
IIJ~

a:
W ..J ..J
It)a0:
CX0CO"")oZo-
0a:::
0
~

~v" ~a. ~At
~AIO ~A" ~AU ~Hm ~mft
~"CLK
~IV-O
~IV;
:!!liVl
~jVl
~VCr.
~jv. ~IVI
g,vi
~IV7
§J'"
Eli
~wc ~sc ~IU
~ ...
~IU

PIN NO. 1
2-9,45-49 10, 11 12 13-28 29 30 31 32 33-36, 38-41 37 42 43
44
50

IDENTIFIER

FUNCTION

VCR

Regulated voltage input from series·pass transistor (2N5320 or equivalent).

Ao-A,,;

Program Address Lines: These active·high outputs permit direct addressing of up to 8192 words of program storage; A12 is least significant bit.

Xl, X2

Timing generator connections for a capacitor, a series resonant crystal, or an external clock source with complementary outputs.

GND

Ground.

10- 115

Instruction lines: These active·hlgh Input lines receive 16·bit instructions from program storage; 115 is least significant bit.

Soloct Command: When high (binary 1), an address is being output on pins IVa through IV7.

Write Command: When high (binary 1), data is being output on pins IVa through IV7.

Left Bank Control: When low (binary..Qb devices connected to the Left Bank are accessed. (Note.

Typically, the LB signal is tied to the ME input pin of 110 peripherals.)

Right Bank Control: When low (binary a), devices connected to the Right Bank are accessed (Note.

Typically, the RB signal is tied to the ME input pin 01//0 peripherals.)

IVO-IV7

Interface Vector (Input/Output Bus) - these bidirectional active·low three-state lines communicate data andlor addresses to 1/0 devices and memory locations. A low voltage level equals a binary "1"; IV7 is Least Significant Bit.

Vee MCLK

+ 5V power supply.
Master Clock: This active·high output signal is used for clocking I/O devices andlor synchronization of external logic.

RESET

When RESET input is low (binary 0), the 8X305 is initialized - sets Program Counter/Address I Register to zero and inhibits MCLK. For the period of time RESET is low, the Left BanklRight Bank
(LB/RS) signals are forced high asynchronously.

HALT

When HALT input is low (binary a), internal operation of the 8X305 stops at the start of next instruction; MCLK is not inhibited nor is any internal register affected; however, both the Left Bankl Right Bank (LB/AB) signals are synchronously driven high during the first quarter of the instruction cycle time and remain high during the time HALT is low.

InternallY'generated reference output voltage for external series·pass regulator transistor.

Figure 1·2. 8X30S Pin Designations and Functions

Signetics
78 - C

1j1~v\I< L~I UIVI~IUI~
USERS MANUAL

8X305

The I/O Ports must be capable of performing the address select operation, determining the direction of the bus, analyzing the bank control signals, and presenting or receiving data. Signetics offers numerous circuits that perform these functions for specific applications. Refer to the 8X300 Family Product Capabilities Manual for information on these devices.
1.5 SYSTEM ENVIRONMENT
A generalized system configuration consisting of program storage (ROM/PROM), working storage (RAM), 1/0 devices, and the IV bus interface (IVO-IV7) is shown in Figure 1-3. Except for the off-chip timing crystal, the 'regulator transistor, and any user-generated logic associated with the HALT and RESET lines, no external parts are required for implementation. The TTLcompatible bus, simple interface logic, and bitmanipulation features optimize the 8X305 MicroController for almost any system where high-speed operation, flexibility, and minimum board space are required.
The program storage can consist of any ROM or PROM with sufficient access speed. It can be configured ,to the

size of program required by the application, up to a maximum of 8,192 instruction words.
An Interrupt Control Coprocessor, the 8X310, is available.' This device connects to the Instruction Bus and Instruction Address Bus, providing a single-chip interrupt handler and an enhanced ability for subroutine processing.
Ports on the IV bus must be tailored to the application. Some additional high-speed working storage may also be required. This is implemented by assigning contiguous memory locations in a small byte-wide RAM to a series of contiguous port addresses. It is good practice to pair peripherals which transfer a good deal of data between each other on opposite banks, which enables singleinstruction processing and transfer of data.
Since they have been designed specifically for the IV bus, the 8X300 Family of parts provide the simplest solution to most requirements encountered in an 8X305 system. The family includes an array of I/O Ports, working storage RAM, and single-chip'solutions to problems such as floppy disk control and computer bus interfacing.

SigletIcs
78 - D

1.0 Introduction
1.1 General Description:
The ST·506/412 disc drive is a random access storage device utilizing two non· removable 5',4 Inch discs as storage media. Each disc surface employs one movable head to service 153/306 data tracks. The total 'ormaned capacity of the four he.ds and surfaces is 5/10 megabytes (32 sectors per track, 256 bytes per sector. 61211224 tracks).
Low cost and unit reli.bility are achieved through the un of a band aetuator and open loop stepper he.d poSitioning mechanilm. The inherent simplicity of. mech.nia.1 construction and electronic controls allows maintenance free operation throughout the life of the drive. Both elecronic PCB's are mounted outside the he.d disc assembly, allowing field serviceability.
Mechanlc.1 and contlmination protection for the heads, aetullor, and discs is provided by an impact resistant aluminum enclosure. A self-contained recirculating system Iupplies clean air through a 0.3 micron filter. A second port in the f.her auembly allows pressure equalizllion with ambient air without chance of contamination. A patented spindfe pump alsures adequate air flow and uniform temperature dilttibution throughout the head and disc area. Thermal isolation of the stepper and spindle motor assemblies from the disc .nclosure results in a very low temperature rise within the enclosure. This provides significantly grNter off track margin and the ability to immedillely perform raad and write oper.tionl aher power up with no thermal stabilization delay.
The ST -506/412 electrical interface is similar to Shugart Associates' SA1000. f.mily of 8 inch fixed disc drives. ST·506/412 Si18 and mounting are identical to the industry standard minifloppy disc drives, and they use the same DC voltages and connector. No AC power is required.
Key Features:
* Storage Capacity of 6.38/12.76 megabytes unformaned, 5.0/10.0 mega-
bytes forma ned as shipped.
* Same physical size and mounting as the minifloppy.
* Same DC voltages as the minifloppy.
* Band actuator and stepper motor head positioning.
* 5.0 megabit/second transfer rate. * Simple floppy-like interface. * Same track capacity as a double density 8 inch floppy.

1.2 Specification Summitry:
1.2.1 Physical Specifications:
Environmental limits:
Ambi.nt Temperature Operating: 40° to 122°F (40 to SOOC) Non-Operating: -14° to 140°F (-10° to 600C)
Max Temperature Gradient Operating: leoF/hr. (100C) Non·operating: Below Condensation
Relative Humidity: B to 80% non-condensing
Maximum Elevation Operating: 10,000 h. Non-operating: -1000 to 12,000 h.

Shock Operating: 10G'I Non-operating: 40G's (on box side frames)

DC Power Requirements
+12VtS%. 1,8A typical, 4.6A maximum (It power on) +5V t 5%·.7A typical, 1.0A maximum
+12V/+5V Maximum Ripple = SOmV pop

Mechanical Dimensions: Height .··......·.·..·..........··.· 3.25 Inch·· Width ..·.·.........·.........·..··· 5.76 inch.s Depth .·..·.......·..·........·.·..· 8.00 inch·· Weight ·....................··.· 4.8 lb·. (2.1 kg) Shipping Weight ...·.....··..... 7.0 lb·. (3.2 kg)

Heat Dissipation 25 wans typical 29 wans maximum

1.2.2

Reliability Specifications: MTBF ................ 11,000 POH, typical usage PM ···.········.····..······ ,.... Not Required MTTR ···············.····.········· 30 minute. Component DeSign life ···.···.·········· 6 yel,.

Error Rates:
Soh read errors .···.······.· 1 per 10'0 bit. re.d Hard read errors· ····..·..·· 1 per 1012 bit. read Seek errors ...................... 1 per 10' seek · Not recoverable within 16 retries

1.2.3 Performance Specifications:
Capacity Unformatted

5T·608

Per Drive Per Surface Per Track Formatted Per Drive Per Surface Per Track Per Sector Sectors Per Track

6.38 Megabytes 1.59 Megabytes 10416 Bytes
5.0 Megabytes 1.25 Megabytes 8192 Bytes 256 Bytes 32

Transfer Rate

5.0 Mbits/aec

Access Time

Track to Track

3m,

Average-

85ms

Maximum-

205ms

Setting Time

15ma

·using fast seek algorithm (including setting)

5T·412
12.76 Megabytes 3.19 Megabytes 10416 Bytes
10.0 Megabytes 2.5 Megabytes 8192 Bytes 256 Bytes 32
5.0Mbita/sec
3ms 85ms 205ms 15ma

Average Latency

8.33m.

1.2.4

Functional Specifications: Rotational speed Recording density Flux density Track density Cylinders Tracks R/W Heads Discs

2.0 Fu~ctlonel CfJ,erecteriatlc.

3600 rpm±l% 7690 bpi max 7690 fci 255 tpi 153 612 4 2

3600 rpm ±1% 9074 bpi max 9074 fci 345 tpi 306 1224 4 2

2.1 General Operation:

The ST-506/412 disc drive consists of read/write and control electronics, read/ write heads, track positioning actuator, media, and air filtration system. The components perform' the following functions:

1. Interpret and generate control signals.

2. Position the heads over the desired track.

3. Read and write data.

4. Provide a contamination free environment.

2.2 Read/Write and Control Electronics

Electronics are packaged on two printed circuit boards. The primary Iloard to which power, control and data signals are connected includes:

1. Index detection circuit.

2. Head position/actuator circuit.

3. Read/write circuits.

4. Drive up to speed circuit.

5. Head select circuit.

6. Write fault detection circuit.

7. Step motor drive circuit.

8. Drive select circuit.

9. Track zero detector circuit.

The second PCB, mounted to the sideframe under the primary board derives its power from the primary board and provides power and speed controltothe spindle drive motor.

2.3 Drive Mechanism

A brushloss DC drrve motor rotatos the spindle at 3600 rpm. The spindle is driven

directly with no belt or pulley being used. The motor is thermally isolated

from tlla htlsd/disc assembly to minimize temperature rise in the sealed

chamber containing the heads and discs. The motor and spindle are dynamically

balanced to insure a low vibration Jevel. A brake is used to quickly stop the

spindle motor when power is removed. The head/disc assembly is shock

mounted to minimize transmission 01 vibration through the chassis or frarna.

2.4 Air Filtration System (Figures 1A & 1B)

The discs and read/write heads are fully enclosed in 8 module using an integral recirculation air system and absolute filter to maintain a clean onviror.ment. Integral to the filter is a port whict: also permits ambient pressure equalization without contaminate entry.

2.5 Positioning Mechanism (Figure 2)

The read/write heads are mounted on a ball bearing supported carri8ge which is poSitioned by a band actuator connected to the stepper motor shaft. The stepper motor is thermally isolated from the head/div.. assemblY to minimize temperatura rise in the sealed chamber.

1.0 INTRODUCTION 1.1 GENERAL DESCRIPTION The Shugart Model 1000 series disk drive is a random access storage device with one or two non-removable 8" disks as storage media. Each disk surface employs one movable head to service 256 data tracks. The two models of tbe SA1000 series are the 1002 and the 1004 with single.and double platters respectively. The SA1002 provides 5 megabytes accessed by 2 movable heads and the SA1004 provides 10 megabytes accessed by 4 movable heads. Low cost and unit reliability are achieved through the use of a unique band actuator design. The inherent simplicity of mechanical construction and electronic controls allows maintenance free operation throughout the life of the drive. Mechanical and contamination protection for the head, actuator and disks are provided bv an impact resistant plastic and aluminum enclosure. A self contained recirculating system supplies clean air through a 0.3 micron filter. Another absolute filter allows pressure equalization with ambient air. The optional SA1200 Data Separator PCB or equivalent circuitry is necessary to provide MFM encoding/decoding. write precompensation. a crystal write oscillator and address mark writing and detection. These functions are also provided by the optional SA1400 controller. The SA1000 fixed disk drive's interface is similar* to the Shugart 8" family of floppy disk drives.'The SA1000 is designed to fit into the same physical space as the 8" floppies. Key Features: · Storage Capacity of 5.33 or 10.67megabytes. · .Winchester design reliability. · Same physical size and identical mounting configuration as the SA800/850 floppies. · Uses the same D.C. voltages as the SA800/850 floppies. · Proprietary Fas Flex III band actuator. · 4.34 Mbits/second transfer rate. · Simple floppy like interface. *Existing floppy controllers are not compatible with the SA1000 due to differences in the data transfer rates.
80 - A

1.2 Specification Summary 1.2.1 Physical Specifications

Environmental Limits
Ambient Temperature =
Relative Humidity =
Maximum Wet Bulb =
AC Power Requirements 50160 Hz ± 0.5Hz 100/115 VAC Installations 200/230 VAG Installations
DC Voltage Requirements

DC Voltage

Ripple MV P-P

+5 ± V

50° to 115°F (10° to 46°C) BO/o to BO% 7Bo non-condensing
=90-127V at 1.1 A typical =1BO-253V at O.6A typical
Stepping Steady State

- 5 ± 0.5 V ( - 7 to - 16V optional)
± 24 ± 3.6 V

50 (N/A)
1000

Stepping Steady State

Mechanical Dimensions

Height = Width = Depth =
Weight =

Rack Mount 4.62 in. (117.3mm) 8.55 in. (217.2mm) 14.25 in. (362.0mm)
17 Ibs. (7.7Kg)

Standard Mount 4.62 in. (117.3mm) 9.50 in. (241 .3mm) 14.25 in. (362.0mm)
17 Ibs. (7.7Kg)

Heat Dissipation = 511 BTU/Hr. typical (150 Watts)

1.2.2 Reliability Specifications

MTBF: 8,000 POH typical usage PM: None Required MTIR: 30 minutes Component Life: 5 years

Error Rates:
Soft Read Errors: Hard Read Errors: Seek Errors: .

1 per 1010 bits read 1 per 1012 bits read 1 per 106 seeks

2.0 amp typfcal 2.5 amp max.. 3.6 amp typical 4.1 amp max.
0.20 amp typical 0.25 amp max.
2.8 amp typical 3.3 amp max. 0.20 amp typical 0.25 amp max.

80 - B

1.2.3 Performance Specifications

Capacity
Unformatted
Per Drive Per Surface Per Track Formatted Per Drive Per Surface Per Track Per Sector Sectors/Track Transfer Rate Access Time
Track to Track
Average
Maximum
Average Latency

SA1002
5.33 Mbytes 2.67 Mbytes 10.4 Kbytes
4.2 Mbytes 2.1 Mbytes 8.2 Kbytes 256 bytes
32 4.34 Mbits/sec
19 msec 70 msec 150 msec 9.6 msec

1.2.4 Functional Specifications

Rotational Speed Recording Density
Flux Density Track Density Cylinders Tracks R/W Heads Disks

3125 rpm 6270 bpi
6270 fci 172 tpi
256 512
2 1

SA1004
10.67 ·Mbytes 2.67 Mbytes 10.4 Kbytes
8.4 Mbytes 2.1 Mbytes 8.2 Kbytes 256 bytes
32 4.34 Mbits/sec
19 msec 70 msec 150 msec 9.6 msec
3125 rpm 6270 bpi 6270 fci 172 tpi
256 1024
4 2

80 ....: c

QUAnTUm CO RPO RATION
PRODUCT SPECIFICNrION Q2000 FIXED DISK DRIVE
The Q2000 fixed disk drive interface J simil,~,r to the'
Shugart 8" floppy driv,e and a superset of Shugart's
SAIOOO series Jisk drive in interface rhe Q2000 serles
disk drive is designed with the same form factor and power supply voltage requirements as 8" floppy drives.
Key Feature s: o Storage Capacity of 10, 20, 30, or 40 ~egabytes
o Winchester design reliability
o Same physical size and mounting as 8" floPPJ drives
o Uses the same D.C. voltages as 8" floppy.
o Proprietary, rotarj, high resolution, quiet head position actuator
o 4.34M bits/se~ond transfer rate o Hicroprocessor controlled ter.lperature cOJlpensation
s~rvo
80 - D

QUnnTUm CORPORATION
PBQplK+ SPECIFICATIQN
Q2000 FIXED DISK DRIVE

1.2

SPECI~ICATION SUMMARY

1.2.1

PHYSICAL SPEeIFICATIO~S ENVIRONME~TAL LIMITS

NON OPERATIONAL

Storage temperature 50°1 to 150°F (IOoe to 6S.S o C)

Shipping temperature
6S.S o C)

-400~ to 150°2 ~-400C to

Storage anJ shipping altitude 1000 to 40,000 fee~

OPERATING Max Operating Altitude 10,000 feet
Ambient temperature = 50° to 115°F (10° to 46°C)
Relacive humiditj 8% to 80%

Maximum wet bulb 78° non-condensing

80 - E

QUAnTum CO RPO RATION
PRODUCT SPECIFICA'I'ION
Q2000 FIXED DISK DRIVE

AC PO~lER REQU I RE·:1E NTS

50/60Hz+O.5Hz lOO/115VAC Installations = 90-l~7V at 1.OA Typical 200/230VAC Installations l80-253V at O.5A Typical
DC VOLTAGE RZQUIREaENTS

+24VDC+10% 1.25A Typical (1.5 A max) +5VDC+5% 1.OA Typical ~1.5 A max)
-5VDC+5% (-7 to -16VDC optional) O.2A TypicaL (0.25 A
raax) MECHANICAL DIMENSIO~S

Height =·4.50 in. (114.3mm)

~-l i d t h

8.55 in. ~217.2mm)

Depth = 14.25 in. (362.0mm)

1 7 1 b s. (7. 7 ~{6 )

80 - F

QUnnTUm CORPORATION
PRODUcr SPECIFICA'rION
Q2000 FIXED DISK DRIVE

V I BRA 'f I a~~

Th~

t-
specified for

to thr~e mutual1!

perpendicular c.lirections.

~ P t' i. n c i pIc Cd:' i ~ 2 t ;1 xes ) · Equipment

s hal .!. b 2 0 per a b 1 e d uri n g a n J a f t ~ r i:. hem a x i t:l U In 'J i ~ rat ion 1 eVe 1 s

in th~ following table.

~REQUENCY

PEAK TO PEAK
A~lP L I TUD E

Ope ra t i n3

Hz
5 - 25
25 - 55 55 - 300

In .0014 .0007

G's
o. 3

~on-Operatin6

5 - 25
25 - 55
55 - 300

.008 .004
2.0

TRAC K GEO:,1::: 7 RY

T r a c k '.J i d t £1 = . 0 0 2 2 5 + - . 0 0 0 l S i n c h e s
Track spaci~g = .00287 inches av~rag~ T r a c !.~ Z \3 1" 0 r ~l diu s == 3. 6 3 7 i. n C !l c s no In ina 1
Tra=k 511 radius = 2.155 inches nOillinal S hip pin .5 and 1 and i n6 Z 0 net 1" a c ~'- = 2. 0 5 0 inc h e s
nominal

80 - G

QUAnTUm CORPORATION
PRODUCT SPECIFICATION
Q2000 FIXED DISK DRIVE

HEAT DISSIPATION 239 BTU/HR. TYP (70 Watts) No~~nal

1.2.2 RELIABILITY SPECI~ICATluN

MTaF:8,000 POH typical usage PH:not required MTTR:30 minutes Component Life: 5 years

ERROR ·RATES
,

Soft read errors: 1 per 1010 bits read

Hard read errors: 1 per 1012 bits read

Seek e r ro r s :

1 per 106 seeks

These error rates assume that the drive is being operated. within its sPecified limits. Errors caused by illedia defects are excluded.

1.2.3 PERFORMANCE SPECI~ICATIONS

Capacity Unformatted Per driVe Per surface Per t r :1 c~"

Q2010

Q2020

Q2030.

Q2040

lO.66Mb 5033Hb
lO.40Kb

21.33Mb 5. 33:1 b
lO.40Kb

32000:1b 5033Mb 1·0. 40K~)

420 66 :'lb 5.33Hb 10.40K0

80 - H

QUnnTUm CORPORATION
PRODUCT SPECIFlCA'l'l()tJ

Q2000 FIXED DISK DRIVE

.? 0 r mat ted : ~1l: 1) P~r drive Per surface Pt!r track Per sector Scctors/TK Transfer Rate

8. 40~'1b

16.80Hb 2.J.20~lb

3J.GOilb

4.20Hb

4. 2 0 ~'1 !:> 4.20."

',. · 20:1 b

8.20Kb

8.20tzb 8.2iJKo

3.20Kb

256 B] t (' 256 Bytes 2 5·6 Bytes 256 Bytes

4.34i1bits/ 4.34:-1Jits/ 4.34Mbits/ 4.34Mbits

sec

sec.

sec

Access Ti.lle (Nominal voltages, 25°C

TK to TK(max)

15 ms

15 rns

15 [Us

Average~max)

55 IUS

60 ms

65 ms

Full S t r 01<. e ~ t y p ) 115 IDS

115 IDS

115 ms

Avg. Latencj

10 ;:ns

10 ms

10 os

10 r.1S

1.2. 4 FUNCTIONAL SPECI~ICATIO~S

Nom Rotational Speed Hax Rotational Speed Min Rocational. S?C eu Recording Density llux Density Trac'r<. Density
Cj.lind~rs
Tracks R / '\J HeaJs Disks InJ2x

3000 RP:1 3083 RPi1 2904 RPI1 6600 bpi 6600 fci
345 tpi 512 1024
2 1 1

3000 RP:·1 3083 RP~J 2904 RP :1 6600 bp i 6600 fci
345 tpi 512 2048
~
2
1

30)00 ~ P.l 3083 t), PM 2904 ~~) r·1 6600 ~p i 6600 fci
34) ~ pi 512 3072
6
3 1

3000 qP'J 3083 R P:·1 2904 R P ~1 . 6600 bpi 6600 f c i
345 tpi 512 4096
8 4 1

Quantum guarantees a t rac k capacity of a minLnuID of 10102

bJ t es

when written

usinJ

timing

1 · 8 !l

microseconds/byte.

;;<00 - I

QUnnTUm CORPORATION
,I PRODucr SPECIFICATION
Q2000 FIXED DISK DRIVE

2.0

~UNCTIONAL CHARACTERISTIC~

2.1

GE~ERA~ OPERATION

The Series 2000 fixed disk drive consists of

read/write and control electronics, ceacl/write

heads, head positioning mechanism, meJia, air

filtration, and disk rotation sjsteQ. (See 1ig

I-A for functional block diagram)

These

components perform the following functions:

Spin the signa'ls

disk~s)

and

generate

control

Position the ~3ads over the selected track with appropriate corrections in position to compensate for thermal effects on track location

Read an~ write d3ta

Provide a contamination free environment
a r 0 un d t 11 e me J i a a n j ne ads

P~rfor~

dia3nostic3

p0sitioning aad servo sfs:ems

t h~

heaJ

2 · 2

READ/WR!~E A~D CO~TROL ELECTRONICS

'The electronics for ~he drive are packaged on two print~J circuit boarJs, th~ control PCB and th~ Transducer PCB.

80 - J

QUnnTUm CORPORATION
PRODUCT SPECIFICATION
Q2000 FIXED DISK DRIVE
2.2.1 TRANSDUCER PCB
Th2 Transducer PCB contains the followin~ ~ircuits:
Optical posttion encoder detector circuits Raw track 0 detector circuit AGC circuit for position sensors Head select diode matrix Actuator motor connections Drive capacity option jumpers 2.2.2 CONTROL PCB The main PCB contains the following circuits: Index detector circuit Head positioning ~~tuator clrcuits Hic rop roces so r (with ROM Prbgram*) fo r Jlagnosti.::s and head positioning con,rol Read/write amplifier/drivers Head select circuits Drive select circuit Drive ready circuit Writ~ f a u l t J~tection cir~uit Power on reset circuit Track 0 detection circuit 2.3 DRIVE ~1ECHA~IS;1 The spindle rotates at 3000 r~m through a ~elt drive from an AC motor. Either 50 or 60Qz power is a C c 0 J1 0 d J. ted 0 y c h ~ n 3 i n 3 c he In 0 tor d r t ve p u 1 1 e J a n d belc. 220/230VAC operation can h~ utilized bj a .n 0 tor '::::1 J n g e . : See Ap pen d i x (;)
* © Quantum Corp. 1981
80 - K

QUAnTUm CORPORATION I PRODucr SPECIFICATION
Q2000 FIXED DISK DRIVE

2 · 4

REA D/ ~J H. I T E HE AD AL~ D DIS KS

The recording media is a lubricated thin magnetic oxide
coated on an 8 inch :200mm) diameter aluminum substrate.
This lubricated coating formulation, together with the low load force/low mass Winchestdr type flying heads permit reliable contact start/stop operation. To protect recorded data, heads are positioned in :1 landing zone
inside of cylinder 511 when the disks are not up to·speed.

2.5

HEAD POSITIONING SYSTEM

The head positioning system consists of three major elements: rotarj torque motor actuator, optical track position encoder, and temperature compensation servo.

2.5'.1

ROTARY TORQUE XOTOR ACTUATOR ~FIG. 3)

The read/write heads are ~ountcj on counterbalanced arms attached to the hub of the rotary torque motor. This configuration applies a pure torque to the rotor. The
-/
balanced system maximizes bearin~ life and leads to high mechanical stabilitJ and maximum vibration resistance.

The motor is of simple construction consisting of a ring

magnet, two flat plate pole pieces, a single plane moving

coil and t 'l.J 0 b ear i n 3 s ·

This system is faster than

s t e p per mot 0 r s a n d its per for .n a nee mat c he sma n y v 0 t c ~

coil actuator systems.

80 - L

QUAnTUm CO RPO RA TlON
PRODUCT SPECIFICATION
Q2000 FIXED DISK DRIVE

2.5.2 OPTICAL TRACK POSITIJJ E~CODER

The optical track position encoder is a proven technology

uti liz i n g a h i g 11 1 y r eli a b 1 e p ho t o e t c he d s cal e, a n LSD

light source and photodiode sensors.

The encoder

com p 0 n e n t s are 1 0 cat e din sid e the bub b 1 e \J i t h the s cal e

attached to the lowermost actuator arm.

2.5.3 TEMPERATURE COMPENSATION SERVO
The temperature compensation (fin~) servo obtains position feedback directly fro~ the disk surface once per revolution. This track location coding is eubedded between the last inter-r~cord g.:lp and the index pulse. Uriting is inhibited by the jrive during this ti:ne but reading is not. The 12 or 2F 3~rvo signal ~ill appear on t he ~·1 '?H read data lines. Compatibility is maincaincJ with like drives by reducing the disk rotatlonal speed by 4%. This s~rvo method places no restricians on format and a 11 0 ..,7 s the same Jata rate and tra~k c~pac~tf as other comparable ca~petltive units.

80 - M

Adobe Acrobat 9.53 Paper Capture Plug-in