LINEAR TECHNOLOGY LT4250L Negative 48V Hot Swap Controller Instruction Manual

A: Yes, components like R1, R2, C1, C2, Q1, etc., are
application-specific and must be selected based on operating
conditions and desired performance.

“`

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FEATURES
n Allows Safe Board Insertion and Removal from a Live 48V Backplane
n Circuit Breaker Immunity to Voltage Steps and Current Spikes
n Programmable Inrush and Short-Circuit Current Limits
n Pin Compatible With LT1640L/LT1640H n Operates from 18V to 80V n Programmable Overvoltage Protection n Programmable Undervoltage Lockout n Power Good Control Output n Bell-Core Compatible ON/OFF Threshold
APPLICATIONS
n Central Office Switching n 48V Distributed Power Systems n Negative Power Supply Control

LT4250L/LT4250H
Negative 48V Hot Swap Controller
DESCRIPTION
The LT®4250L/LT4250H are 8-pin, negative 48V Hot SwapTM controllers that allow a board to be safely inserted and removed from a live backplane. Inrush current is limited to a programmable value by controlling the gate voltage of an external N-channel pass transistor. The pass transistor is turned off if the input voltage is less than the programmable undervoltage threshold or greater than the overvoltage threshold. A programmable current limit protects the system against shorts. After a 500s timeout the current limit activates the electronic circuit breaker. The PWRGD (LT4250L) or PWRGD (LT4250H) signal can be used to directly enable a power module. The LT4250L is designed for modules with a low enable input and the LT4250H for modules with a high enable input.
The LT4250L/LT4250H are available in 8-pin PDIP and SO packages
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation.

TYPICAL APPLICATION

48V RTN (SHORT PIN)
48V RTN R4 549k 1%

UV = 38.5V
UV RELEASE AT 43V
OV = 71V

R5 6.49k
1%
R6 10k 1%

3 UV
2 OV VEE 4

SENSE 5

*
48V INPUT 1

0.1F 10V

R1 0.02
5%

48V INPUT 2
* DIODES INC. SMAT70A THESE COMPONENTS ARE APPLICATION SPECIFIC AND MUST BE SELECTED BASED UPON OPERATING CONDITIONS AND DESIRED PERFORMANCE. SEE APPLICATIONS INFORMATION.

8 VDD
LT4250L

1 PWRGD

VEE AND DRAIN
20V/DIV

GATE

DRAIN

1k, 5%

470nF 10

25V

C2 15nF 100V

ID (Q1) 5A/DIV

Q1 IRF530

C3 +
0.1F 100V

C4 100F 100V

ON/OFF

VIN+

VOUT+

SENSE+

9 8

TRIM 7

SENSE 6

4 VIN

VOUT 5

5V
C5 100F 16V

LUCENT JW050A1-E

4250 TA01a

Downloaded from Arrow.com.

Voltage Step on Input Supply

500s/DIV

4250 TA01b

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LT4250L/LT4250H

ABSOLUTE MAXIMUM RATINGS
(Note 1), All Voltages Referred to VEE
Supply Voltage (VDD VEE)…………………. 0.3V to 100V PWRGD, PWRGD Pins ……………………….. 0.3V to 100V SENSE, GATE Pins ………………………………. 0.3V to 20V UV, OV Pins ………………………………………… 0.3V to 60V DRAIN Pin…………………………………………… 2V to 100V Maximum Junction Temperature……………………… 125°C

Operating Temperature Range LT4250LC/LT4250HC …………………………. 0°C to 70°C LT4250LI/LT4250HI………………………… 40°C to 85°C
Storage Temperature Range………………. 65°C to 150°C Lead Temperature (Soldering, 10 sec) ……………… 300°C

PIN CONFIGURATION

TOP VIEW

PWRGD 1 OV 2 UV 3 VEE 4

8 VDD 7 DRAIN 6 GATE 5 SENSE

N8 PACKAGE 8-LEAD PDIP

S8 PACKAGE 8-LEAD PLASTIC SO

TJMAX = 125°C, JA = 120°C/W (N8) TJMAX = 125°C, JA = 150°C/W (S8)

TOP VIEW

PWRGD 1 OV 2 UV 3 VEE 4

8 VDD 7 DRAIN 6 GATE 5 SENSE

N8 PACKAGE 8-LEAD PDIP

S8 PACKAGE 8-LEAD PLASTIC SO

TJMAX = 125°C, JA = 120°C/W (N8) TJMAX = 125°C, JA = 150°C/W (S8)

ORDER INFORMATION

LEAD FREE FINISH

TAPE AND REEL

PART MARKING

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LT4250LCN8#PBF

LT4250LCN8#TRPBF

4250L

8-Lead PDIP

0°C to 70°C

LT4250LCS8#PBF

LT4250LCS8#TRPBF

4250L

8-Lead PLASTIC SO

0°C to 70°C

LT4250LIN8#PBF

LT4250LIN8#TRPBF

4250LI

8-Lead PDIP

40°C to 85°C

LT4250LIS8#PBF

LT4250LIS8#TRPBF

4250LI

8-Lead PLASTIC SO

40°C to 85°C

LT4250HCN8#PBF

LT4250HCN8#TRPBF 4250H

8-Lead PDIP

0°C to 70°C

LT4250HCS8#PBF

LT4250HCS8#TRPBF

4250H

8-Lead PLASTIC SO

0°C to 70°C

LT4250HIN8#PBF

LT4250HIN8#TRPBF

4250HI

8-Lead PDIP

40°C to 85°C

LT4250HIS8#PBF

LT4250HIS8#TRPBF

4250HI

8-Lead PLASTIC SO

40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

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LT4250L/LT4250H

ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2), VDD = 48V, VEE = 0V unless otherwise noted.

SYMBOL PARAMETER

CONDITIONS

MIN TYP MAX UNITS

VDD

Supply Voltage Operating Range

l 18

IDD

Supply Current

UV = 3V, OV = VEE, SENSE = VEE

1.6

VUVL

Undervoltage Lockout

15.4

VCL

Current Limit Trip Voltage

VCL = (VSENSE VEE)

l 40

IPU

GATE Pin Pull-Up Current

Gate Drive On, VGATE = VEE

l 30

IPD

GATE Pin Pull-Down Current

Gate Drive OFF

ISENSE

SENSE Pin Current

VSENSE = 50mV

VGATE External Gate Drive

(VGATE VEE), 18V VDD 80V

l 10

13.5

VUVH

UV Pin High Threshold Voltage

UV Increasing

l 1.24 1.255 1.27

VUVL

UV Pin Low Threshold Voltage

UV Decreasing

l 1.105 1.125 1.145

VUVHY

UV Pin Hysteresis

130

IINUV

UV Pin Input Current

VUV = VEE

0.02 0.5

VOVH

OV Pin High Threshold Voltage

OV Increasing

l 1.235 1.255 1.275

VOVL

OV Pin Low Threshold Voltage

OV Decreasing

l 1.21 1.235 1.255

VOVHY

OV Pin Hysteresis

IINOV

OV Pin Input Current

VOV = VEE

0.03 0.5

VDL

DRAIN Low Threshold

VDRAIN VEE, DRAIN Decreasing

1.1

1.6

2.3

VGH

GATE High Threshold

VGATE VGATE Decreasing

1.3

IDRAIN

Drain Input Bias Current

VDRAIN = 48V

l 10

500

VOL

PWRGD Output Low Voltage

PWRGD (LT4250L), (VDRAIN VEE) < VDL

IOUT = 1mA

0.48

0.8

IOUT = 5mA

1.2

PWRGD Output Low Voltage (PWRGD DRAIN)

IOH

Output Leakage

PWRGD (LT4250H), VDRAIN = 5V

IOUT = 1mA

PWRGD (LT4250L), VDRAIN = 48V, VPWRGD = 80V

PWRGD (LT4250H), VDRAIN = 0V, VPWRGD = 80V

0.75

0.05

tPHLOV tPHLUV tPLHOV tPLHUV tPHLSENSE tPHLCB tPHLDL
tPHLGH

OV High to GATE Low

Figures 1a, 2

UV Low to GATE Low

Figures 1a, 3

OV Low to GATE High

Figures 1a, 2

UV High to GATE High

Figures 1a, 3

SENSE High to Gate Low

Figures 1a, 4a

Current Limit to GATE Low

Figures 1b, 4b

DRAIN Low to PWRGD Low

(LT4250L) Figures 1a, 5a

DRAIN Low to (PWRGD DRAIN) High (LT4250H) Figures 1a, 5a

GATE High to PWRGD Low

(LT4250L) Figures 1a, 5b

GATE High to (PWRGD DRAIN) High (LT4250H) Figures 1a, 5b

1.7

1.5

5.5

6.5

500

1.5

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.

Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to VEE unless otherwise specified.

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LT4250L/LT4250H TYPICAL PERFORMANCE CHARACTERISTICS

SUPPLY CURRENT (mA)

GATE VOLTAGE (V)

Supply Current vs Supply Voltage
1.8 TA = 25°C
1.7

1.6 1.5

1.4 1.3

1.2

1.1

80 100

SUPPLY VOLTAGE (V)

4250 G01

Gate Voltage vs Temperature
15.0 VDD = 48V
14.5

14.0

13.5

13.0 12.5

12.0 50 25 0 25 50 TEMPERATURE (°C)

75 100
4250 G04

Gate Pull-Down Current vs Temperature
55 VGATE = 2V
52

40 50 25 0

25 50 75 100

TEMPERATURE (°C)

4250 G07

PWRGD OUTPUT LOW VOLTAGE (V)

TRIP VOLTAGE (mV)

SUPPLY CURRENT (mA)

Supply Current vs Temperature
1.6 VDD = 48V
1.5

1.4

1.3

1.2

1.1

1.0 50 25

0 25 50 TEMPERATURE (°C)

75 100
4250 G02

Current Limit Trip Voltage vs Temperature
55
54

52 51 50

48 50 25

0 25 50 TEMPERATURE (°C)

75 100
4250 G05

PWRGD Output Low Voltage vs Temperature (LT4250L)
0.5 IOUT = 1mA
0.4

0.3

0.2

0.1

0 50 25 0 25 50 75 100
TEMPERATURE (°C)
4250 G08

OUTPUT IMPEDANCE (k)

GATE PULL-UP CURRENT (A)

GATE VOLTAGE (V)

Gate Voltage vs Supply Voltage
15 TA = 25°C
14

80 100

SUPPLY VOLTAGE (V)

4250 G03

Gate Pull-Up Current vs Temperature
48
47 VGATE = 0V

40 50 25 0

25 50 75 100

TEMPERATURE (°C)

4250 G06

PWRGD Output Impedance vs Temperature (LT4250H)
8
VDRAIN VEE > 2.4V 7

2 50 25 0 25 50
TEMPERATURE (°C)

75 100
4250 G09

GATE PULL-DOWN CURRENT (mA)

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LT4250L/LT4250H

PIN FUNCTIONS
PWRGD/PWRGD (Pin 1): Power Good Output Pin. This pin will latch a power good indication when VDRAIN is within VDL of VEE and VGATE is within VGH of VGATE. This pin can be connected directly to the enable pin of a power module.
When the DRAIN pin of the LT4250L is above VEE by more than VDL or VGATE is more than VGH from VGATE, the PWRGD pin will be high impedance, allowing the pull-up current of the module’s enable pin to pull the pin high and turn the module off. When VDRAIN drops below VDL and VGATE rises above VGH, the PWRGD pin sinks current to VEE, pulling the enable pin low and turning on the module. This condition is latched until the GATE pin is turned off via the UV, OV, UVLO or the electronic circuit breaker.
When the DRAIN pin of the LT4250H is above VEE by more than VDL or VGATE is more than VGH from VGATE, the PWRGD pin will sink current to the DRAIN pin which pulls the module’s enable pin low, forcing it off. When VDRAIN drops below VDL and VGATE rises above VGH, the PWRGD sink current is turned off, allowing the module’s pull-up current to pull the enable pin high and turn on the module. This condition is latched until the GATE pin is turned off via the UV, OV, UVLO or the electronic circuit breaker.
OV (Pin 2): Analog Overvoltage Input. When OV is pulled above the 1.255V threshold, an overvoltage condition is detected and the GATE pin will be immediately pulled low. The GATE pin will remain low until OV drops below the 1.235V threshold.
UV (Pin 3): Analog Undervoltage Input. When UV is pulled below the 1.125V threshold, an undervoltage condition is detected and the GATE pin will be immediately pulled low. The GATE pin will remain low until UV rises above the 1.255 threshold.
The UV pin is also used to reset the electronic circuit breaker. If the UV pin is cycled low and high following the trip of the circuit breaker, the circuit breaker is reset and a normal power-up sequence will occur. The response time

for this pin is 1.5s. Add an external capacitor to this pin for additional filtering.
VEE (Pin 4): Negative Supply Voltage Input. Connect to the lower potential of the power supply.
SENSE (Pin 5): Circuit Breaker Sense Pin. With a sense resistor placed in the supply path between VEE and SENSE, the overcurrent condition will pull down the GATE pin and regulate the voltage across the resistor to be 50mV. If the overcurrent condition exists for more than 500s the electronic circuit breaker will trip and turnoff the external MOSFET.
If the current limit value is set to twice the normal operating current, only 25mV is dropped across the sense resistor during normal operation. To disable the current limit feature, VEE and SENSE can be shorted together.
GATE (Pin 6): Gate Drive Output for the External N-channel MOSFET. The GATE pin will go high when the following start-up conditions are met: the UV pin is high, the OV pin is low, (VSENSE VEE) < 50mV and the VDD pin is greater than VUVLOH. The GATE pin is pulled high by a 45A current source and pulled low with a 50mA current source. During current limit the GATE pin is pulled low using a 100mA current source.
DRAIN (Pin 7): Analog Drain Sense Input. Connect this pin to the drain of the external N-channel MOSFET and the V pin of the power module. When the DRAIN pin is below VDL, the PWRGD/PWRGD pin will latch to indicate the switch is on.
VDD (Pin 8): Positive Supply Voltage Input. Connect this pin to the higher potential of the power supply inputs and the V+ pin of the power module. An undervoltage lockout circuit disables the chip until the VDD pin is greater than the 16V VUVLOH threshold.

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LT4250L/LT4250H BLOCK DIAGRAM

UV
+
REF

+
OV

UVLO

50mV
+

VEE SENSE

VDD

VCC AND

VCC

REFERENCE

GENERATOR

REF

LOGIC

OUTPUT DRIVE

PWRGD/PWRGD

500s DELAY

GATE DRIVER

+ + VDL
VEE

GATE

DRAIN

+ + VGH
VGATE
4250 BD

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TEST CIRCUIT

V+

VOV

PWRGD/PWRGD VDD

DRAIN

LT4250L/LT4250H

GATE

VUV

VEE

SENSE

+ 48V
VDRAIN
VSENSE
4250 F01a

Figure 1a. Test Circuit 1

TIMING DIAGRAM

2V OV
0V
GATE
100mV SENSE
VEE
GATE

1.255V

1.235V

tPHLOV

tPLHOV

1V
Figure 2. OV to GATE Timing

1V 4250 F02

60mV

tPHLSENSE

1V
4250 F04a
Figure 4a. SENSE to GATE Timing

DRAIN PWRGD

1.4V VEE
tPHLDL
1V VEE

DRAIN

1.4V
VEE tPHLDL

PWRGD VPWRGD VDRAIN = 0V

1V 4250 F05a

Figure 5a. DRAIN to PWRGD/PWRGD Timing

Downloaded from Arrow.com.

LT4250L/LT4250H

PWRGD/PWRGD VDD

DRAIN

+ 48V

+ 20V

LT4250L/LT4250H

10k

GATE

10 IRF530

VUV

VEE

SENSE

0.1F

4250 F01b
Figure 1b. Test Circuit 2

2V UV
0V
GATE

1.125V

1.255V

tPHLUV

tPLHUV

1V
Figure 3. UV to GATE Timing

1V 4250 F03

tPHLCB

GATE 1V

1V
4250 F04b

Figure 4b. Active Current Limit Timeout

1.4V
VGATE VGATE = 0 GATE

tPHLGH
PWRGD 1V VEE
1.4V
VGATE VGATE = 0 GATE

tPHLGH

PWRGD VPWRGD VDRAIN = 0

1V
4250 F05b

Figure 5b. GATE to PWRGD/PWRGD Timing

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LT4250L/LT4250H

APPLICATIONS INFORMATION
Hot Circuit Insertion
When circuit boards are inserted into a live 48V backplane, the bypass capacitors at the input of the board’s power module or switching power supply can draw huge transient currents as they charge up. The transient currents can cause permanent damage to the board’s components and cause glitches on the system power supply.
The LT4250 is designed to turn on a board’s supply voltage in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. The chip also provides undervoltage, overvoltage and overcurrent protection while keeping the power module off until its input voltage is stable and within tolerance.
Power Supply Ramping
The input to the power module on a board is controlled by placing an external N-channel pass transistor (Q1) in the power path (Figure 6a). R1 provides current fault detection and R2 prevents high frequency oscillations. Resistors R4, R5 and R6 provide undervoltage and over-voltage sensing. By ramping the gate of Q1 up at a slow rate, the inrush current charging load capacitors C3 and C4 can be limited to a safe value when the board makes connection.
Resistor R3 and capacitor C2 act as a feedback network to accurately control the inrush current. The C2 capacitor can be calculated with the following equation:
C2 = (45A · CL)/IINRUSH

where CL is the total load capacitance = C3 + C4 + module input capacitance.
Capacitor C1 and resistor R3 prevent Q1 from momentarily turning on when the power pins first make contact. Without C1 and R3, capacitor C2 would pull the gate of Q1 up to a voltage roughly equal to VEE · C2/CGS(Q1) before the LT4250 could power up and actively pull the gate low. By placing capacitor C1 in parallel with the gate capacitance of Q1 and isolating them from C2 using resistor R3 the problem is solved. The value of C1 is given by:

C1=

VINMAX VTH

VTH

(C2

CGD)

C1 35 · C2 for VINMAX = 72V
where VTH is the MOSFET’s minimum gate threshold and VINMAX is the maximum operating input voltage.
R3 should not exceed a value that produces an R3 · C2 time-constant of 150s. A 1k value for R3 will ensure this for C2 values up to 150nF.
The waveforms are shown in Figure 6b. When the power pins make contact, they bounce several times. While the contacts are bouncing, the LT4250 senses an undervoltage condition and the GATE is immediately pulled low when the power pins are disconnected.
Once the power pins stop bouncing, the GATE pin starts to ramp up. When Q1 turns on, the GATE voltage is held constant by the feedback network of R3 and C2. When the

48V RTN (SHORT PIN)

48V RTN

UV = 38.5V OV = 71V

R4 549k
1%
R5 6.49k
1%
R6 10k 1%

3 UV
2 OV VEE 4

8 VDD
LT4250H

PWRGD

C3 0.1F 100V
C4 +
100F 1 100V

SENSE 5

GATE

DRAIN

6 R3

1k, 5%

VICOR VI-J30-CY

VIN+ VOUT+

GATE IN

+ C5
100F
16V

VIN VOUT

0.02 3 5% 4

48V

* DIODES INC. SMAT70A

470nF 10 C2

25V 5% 15nF

100V

Q1 IRF530

4250 F06a

Figure 6a. Inrush Control Circuitry

8
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INRUSH CURRENT 500mA/DIV
GATE VEE 10V/DIV

MODULE TURN-ON MODULE TURN-ON

DRAIN 50V/DIV
VEE 50V/DIV
CONTACT BBOOUUNNCCEE

25ms/DIV

4250 F06b

Figure 6b. Inrush Control Waveforms

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LT4250L/LT4250H

APPLICATIONS INFORMATION
DRAIN voltage has finished ramping, the GATE pin then ramps to its final value.

Current Limit/Electronic Circuit Breaker
The LT4250 features a current limit function that protects against short circuits or excessive supply currents. If the current limit is active for more than 500s the electronic circuit breaker will trip. By placing a sense resistor between the VEE and SENSE pin, the current limit will be activated whenever the voltage across the sense resistor is greater than 50mV.

Note that the current limit threshold should be set sufficiently high to account for the sum of the load current and the inrush current. The maximum value of the inrush current is given by:

IINRUSH

0.8

40mV

RSENSE

ILOAD,

where the 0.8 factor is used as a worst case margin combined with the minimum trip voltage (40mV).
In the case of a short circuit, the current limit circuitry activates and immediately pulls the GATE low, servos the SENSE voltage to 50mV, and starts a 500s timer. The MOSFET current is limited to 50mV/RSENSE (see Figure 7). If the short circuit persists for more than 500s, the circuit breaker trips and pulls the GATE pin low, shutting off the MOSFET. The circuit breaker is reset by pulling UV low, or by cycling power to the part. If the short circuit clears before the 500s timing interval the current limit will deactivate and release the GATE.

DRAIN 50V/DIV
GATE 10V/DIV

The LT4250 guards against voltage steps on the input supply. A positive voltage step (increasing in magnitude) on the input supply causes an inrush current that is proportional to the voltage slew rate I = CL · V/T. If the inrush exceeds 50mV/RSENSE, the current limit will activate as shown in Figure 8. The GATE pin pulls low, limiting the current to 50mV/RSENSE. At this level the MOSFET drain will not follow the source as the input voltage rapidly changes, but instead remains at the voltage stored on the load capacitance. The load capacitance begins to charge at a current of 50mV/RSENSE, but not for long. As the load capacitance charges, C2 pushes back on the gate and limits the MOSFET current in a manner identical to the initial startup condition which is less than the short circuit limiting value of 50mV/RSENSE. Thus the circuit breaker does not trip. To ensure correct operation under input voltage step conditions, RSENSE must be chosen to provide a current limit value greater than the sum of the load current and the dynamic current in the load capacitance.
For C2 values less than 10nF a positive voltage step increasing in magnitude on the input supply can result in the Q1 turning off momentarily due to current limit overshoot which can shut down the output. By adding an additional resistor and diode, Q1 remains on during the voltage step. This is shown as D1 and R7 in Figure 9. The purpose of D1 is to shunt current around R7 when the power pins first make contact and allow C1 to hold the GATE low. The value of R7 should be sized to generate an R7 · C1 time constant of 33s.
Under some conditions, a short circuit at the output can cause the input supply to dip below the UV threshold. The LT4250 turns off once and then turns on until the electronic circuit breaker is tripped. This can be minimized by adding a deglitching delay to the UV pin with a capacitor from UV to VEE. This capacitor forms an RC time constant with the resistors at UV, allowing the input supply to recover before the UV pin resets the circuit breaker.

ID (Q1) 5A/DIV

1ms/DIV
Figure 7. Short-Circuit Protection Waveforms
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LT4250L/LT4250H

APPLICATIONS INFORMATION
A circuit that automatically resets the circuit breaker after a current fault is shown in Figure 10. Transistors Q2 and Q3 along with R7, R8, C4 and D1 form a programmable one-shot circuit. Before a short occurs, the GATE pin is pulled high and Q3 is turned on, pulling node 2 to VEE. Resistor R8 turns off Q2. When a short occurs, the GATE pin is pulled low and Q3 turns off. Node 2 starts to charge

C4 and Q2 turns on, pulling the UV pin low and resetting
the circuit breaker. As soon as C4 is fully charged, R8 turns
off Q2, UV goes high and the GATE starts to ramp up. Q3
turns back on and quickly pulls node 2 back to VEE. Diode D1 clamps node 3 one diode drop below VEE. The duty cycle is set to 10% to prevent Q1 from overheating.

VEE AND DRAIN
20V/DIV
ID (Q1) 5A/DIV

500s/DIV

4250 08

Figure 8. Voltage Step on Input Supply Waveforms

48V RTN (SHORT PIN)
48V RTN

R4 549k
1%
R5 6.49k
1%
R6 10k 1%

3 UV
2 OV VEE 4

8 VDD LT4250H

1 PWRGD

SENSE 5

GATE
6 R3 1k 5%

DRAIN 7

*
3 48V * DIODES INC. SMAT70A

R1 0.02
5%

220 5%

D1 BAT85

R2 10

150nF

25V

Q1 IRF530

C2 3.3nF 100V

C3 0.1F 100V
+ C4
22F 100V
4250 F09

Figure 9. Circuit for Input Steps with Small C2 (<10nF)

48V RTN

R7 1M 5%
C4 1F 100V

48V RTN (SHORT PIN)

549k 549k

* 48V

Q2 2N2222 3

Q3 ZVN3310

D1 1N4148

R8 510k 5%

R9 R5 10k 16.5k 1% 1%

* DIODES INC. SMAT70A

3 UV
2 OV VEE 4

SENSE 5

0.02

8 VDD

LT4250L

1 PWRGD
+

GATE

DRAIN

1k, 5%

470nF 10

25V

C2 15nF 100V

C3 100F 100V

Q1 IRF530

4250 F10a

NODE 2 50V/DIV

10
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GATE 2V/DIV

1s/DIV

4250 F10

Figure 10. Automatic Restart After Current Fault

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LT4250L/LT4250H

APPLICATIONS INFORMATION
Undervoltage and Overvoltage Detection
The UV (Pin 3) and OV (Pin 2) pins can be used to detect undervoltage and overvoltage conditions at the power supply input. The UV and OV pins are internally connected to analog comparators with 130mV and 20mV of hysteresis respectively. When the UV pin falls below its threshold or the OV pin rises above its threshold, the GATE pin is immediately pulled low. The GATE pin will be held low until UV is high and OV is low.
The undervoltage and overvoltage trip voltages can be programmed using a three resistor divider as shown in Figure 11. With R4 = 549k, R5 = 6.49k and R6 = 10K, the undervoltage threshold is set to 38.5V (with a 43V release from undervoltage) and the overvoltage threshold is set to 71V. The resistor divider will also gain up the hysteresis at the UV pin and OV pin to 4.5V and 1.2V at the input respectively.
PWRGD/PWRGD Output
The PWRGD/PWRGD output can be used to directly enable a power module when the input voltage to the module is within tolerance. The LT4250L has a PWRGD output for modules with an active low enable input, and the LT4250H has a PWRGD output for modules with an active high enable input.
When the DRAIN voltage of the LT4250H is high with respect to VEE (Figure 12) or the GATE voltage is low, the

internal transistor Q3 is turned off and I1 and Q2 clamp the PWRGD pin one SAT drop (0.3V) above the DRAIN pin.Transistor Q2 sinks the module’s pull-up current and the module turns off.
When the DRAIN voltage drops below VDL and the GATE voltage is high, Q3 will turn on, shorting the bottom of I1 to DRAIN and turning Q2 off. The pull-up current in the module pulls the PWRGD pin high and enables the module.
When the DRAIN voltage of the LT4250L is high with respect to VEE or the GATE voltage is low, the internal pull-down transistor Q2 is off and the PWRGD pin is in a high impedance state (Figure 13). The PWRGD pin will be pulled high by the module’s internal pull-up current source, turning the module off. When the DRAIN voltage drops below VDL and the GATE voltage is high, Q2 will turn on and the PWRGD pin will pull low, enabling the module.
The PWRGD signal can also be used to turn on an LED oroptoisolator to indicate that the power is good as shown in Figure 14.
Gate Pin Voltage Regulation
When the supply voltage to the chip is more than 18V, the GATE pin voltage is regulated at 13.5V above VEE. The gate voltage will be no greater than 18V for supply voltages up to 80V.

48V RTN (SHORT PIN)
48V RTN

( ) VUV =

1.255

R4 + R5+ R6 R5 + R6

( ) VOV =

1.255

R4 + R5+ R6 R6

48V

8
VDD 3
UV LT4250L/LT4250H 2 OV
VEE
4
4250 F11

Figure 11. Undervoltage and Overvoltage Sensing

Downloaded from Arrow.com.

48V RTN (SHORT PIN)
48V RTN

LT4250H R4

GATE +

R5 2

+ VGH

+ VDL

VGATE VEE

SENSE

48V

* DIODES INC. SMAT70A 1

VDD PWRGD 1

ACTIVE HIGH ENABLE MODULE
VIN+ VOUT+
ON/OFF

VEE
GATE 6

DRAIN 7

VIN VOUT

C1 R2

4250 F12
Q1

Figure 12. Active High Enable Module

4250lhfa
11

LT4250L/LT4250H APPLICATIONS INFORMATION

48V RTN (SHORT PIN)
48V RTN

LT4250L

3 UV

GATE +

R5 2

+ VGH

OV R6

+ VDL

VGATE VEE

SENSE

48V

* DIODES INC. SMAT70A 1

8 VDD PWRGD
Q2

1
+
C3

ACTIVE LOW ENABLE MODULE
VIN+ VOUT+
ON/OFF

VEE

GATE 6

DRAIN 7

C1 R2

VIN VOUT

4250 F13

Figure 13. Active Low Enable Module

48V RTN (SHORT PIN)
48V RTN
R4 549k
1%
R5 6.49k
1%
R6 10k 1%

3 UV
2 OV VEE 4

SENSE 5

0.02 5%

48V

* DIODES INC. SMAT70A

PWRGD

R7 51k

VDD

LT4250L

PWRGD 1 MOC207

GATE

DRAIN

6 R3

1k, 5%

470nF 10

25V

C2 15nF 100V

C3 +
100F
100V

Q1 IRF530

4250 F14

Figure 14. Using PWRGD to Drive an Optoisolator

12
Downloaded from Arrow.com.

4250lhfa

PACKAGE DESCRIPTION

N8 Package 8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)

.300 .325 (7.620 8.255)

.045 .065 (1.143 1.651)

.008 .015 (0.203 0.381)

.065 (1.651)
TYP

.325

+.035 .015

( ) 8.255

+0.889 0.381

.100 (2.54) BSC

NOTE: 1. DIMENSIONS

ARE

INCHES MILLIMETERS

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)

.130 ± .005 (3.302 ± 0.127)

.120 (3.048)
MIN
.018 ± .003 (0.457 ± 0.076)

.020 (0.508)
MIN
N8 1002

LT4250L/LT4250H

.400*
(10.160) MAX

.255 ± .015* (6.477 ± 0.381)

S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)

.050 BSC

.045 ±.005

.189 .197
(4.801 5.004) NOTE 3

.245

MIN

.160 ±.005

.228 .244

(5.791 6.197)

.150 .157 (3.810 3.988)
NOTE 3

.030 ±.005 TYP
RECOMMENDED SOLDER PAD LAYOUT

.010 (0.254

.020 0.508)

45°

.008 .010 (0.203 0.254)

0° 8° TYP

.053 .069 (1.346 1.752)

.016 .050

(0.406 1.270)

NOTE: 1. DIMENSIONS

INCHES (MILLIMETERS)

.014 .019
(0.355 0.483) TYP

2. DRAWING NOT TO SCALE

3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006″ (0.15mm)

34
.004 .010 (0.101 0.254)
.050 (1.270)
BSC
SO8 0303

Downloaded from Arrow.com.

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

4250lhfa
13

LT4250L/LT4250H

TYPICAL APPLICATION
Using an EMI Filter Module
Many applications place an EMI filter module in the powerpath to prevent switching noise of the module from being injected back onto the power supply. A typical

application using the Lucent FLTR100V10 filter module is
shown in Figure 15. When using a filter, an optoisolator
is required to prevent common mode transients from destroying the PWRGD and ON/OFF pins.

48V RTN (SHORT PIN)
48V RTN

VDD

R4 549k
1%
R5 6.49k
1%

PWRGD 1

3 UV

7 DRAIN

LT4250L

2 OV

6 GATE

R6 10k

VEE

SENSE

* 48V

R1 0.02 3 5% 4

* DIODES INC. SMAT70A

C2 15nF 100V
C1 470nF 25V

R3 1k 5%
R2 1N4003 10 5%

Q1 IRF530

R7 51k 5%

MOC207

C3 0.1F 100V

VIN+ VOUT+
LUCENT FLTR100V10
VIN VOUT CASE

C4 +
0.1F
100V

C5 100F 100V

Figure 15. Typical Application Using a Filter Module

LUCENT JW050A1-E

1 VIN+

VOUT+ SENSE+

9 8

2 ON/OFF TRIM 7

C6 0.1F 100V
4 VIN

SENSE 6 VOUT 5

CASE

4250 F15

5V
C7 100F 16V

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14 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 408-432-1900 FAX: 408-434-0507 www.linear.com
Downloaded from Arrow.com.

Documents / Resources

LINEAR TECHNOLOGY LT4250L Negative 48V Hot Swap Controller [pdf] Instruction Manual
LT4250L, LT4250H, LT4250L Negative 48V Hot Swap Controller, LT4250L, Negative 48V Hot Swap Controller, Hot Swap Controller, Swap Controller

References

User Manual

LINEAR TECHNOLOGY LT4250L Negative 48V Hot Swap Controller Instruction Manual

LT4250L Negative 48V Hot Swap Controller

Specifications:

Product Usage Instructions:

Description:

Typical Application:

Pin Configuration:

Order Information:

FAQ:

Q: What are the typical applications of LT4250L/LT4250H?

Q: Are the components application-specific?

Documents / Resources

References

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