MICROCHIP SLVS-EC Receiver IP User Guide

User Guide for MICROCHIP models including: SLVS-EC Receiver IP, SLVS-EC, Receiver IP, IP

PolarFire SLVS-EC Receiver IP User Guide (Earlier UG0877)

Microchip Technology Inc.

PolarFire SLVS-EC Receiver IP User Guide (Earlier UG0877)

Nov 11, 2024 — This standard is tolerant of lane-to-lane skew because of embedded clock technology. It makes a board-level design easy in terms of high-speed and long-distance ...

PolarFire Mid-Range FPGAs | Microchip Technology

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polarfire fpga slvs ec user guide

PolarFire SLVS-EC Receiver IP User Guide

Introduction (Ask a Question)

SLVS-EC is Sony's high-speed interface for next-generation high-resolution CMOS image sensors. This standard is tolerant of lane-to-lane skew because of embedded clock technology. It makes a board-level design easy in terms of high-speed and long-distance transmission.

SLVS-EC Rx IP core provides SLVS-EC interface for PolarFire® FPGA to receive image sensor data. The IP supports speed up to 4.752 Gbps. The IP core supports two, four, and eight lanes for RAW 8, RAW 10, and RAW 12 configurations.

SLVS_EC Receiver Summary

Core Version

This document applies to SLVS_EC Receiver v4.2.

Supported Device Families · PolarFire® SoC

· PolarFire

Supported Tool Flow Supported Interfaces

Requires Libero® SoC v12.0 or later releases. · Native Interface

· AXI4 Stream Interface

Licensing

The core is license-locked for clear text RTL. It supports the generation of Encrypted RTL for the Verilog version of the core with no license.

Installation Instructions

SLVS_EC Receiver must be installed in the IP Catalog automatically through the IP Catalog update function. Alternatively, SLVS_EC Receiver could be manually downloaded from the catalog. Once the IP core is installed, it is configured, generated, and instantiated for inclusion in the project.

Device Utilization and Performance

A summary of utilization and performance information for SLVS_EC Receiver is listed in Resource Utilization.

Supported Features
SLVS-EC Specification Version Baud Grades
Pixel Formats Lanes Embedded Data

SLVS-EC v2.0 1:1188 2:2376 3:4752
Raw 8, Raw 10, and Raw 12 2, 4, and 8 Supports embedded packet decoding for 2, 4, and 8 lanes

Unsupported Features
Baud Grades Lanes CRC and ECC

4:9216 to 10000 1 Not supported

The following figure shows the system diagram for the SLVS-EC camera solution.

User Guide
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Figure 1. SLVS-EC IP Block Diagram

LANE#_RXD_P LANE#_RXD_N

Transceiver
LANE#_RX_CLK_R LANE#_RX_READY

LANE#_RX_VAL

LANE#_RX_DATA[31:0]

SLVS-EC Rx IP
LANE#_RX_CLK LANE#_RX_READY LANE#_RX_VALID LANE#_RX_DATA[31:0]

LANE_VALID_O FRAME_VALID_O DATA_OUT_O

PolarFire transceiver is used as the PHY interface for the SLVS-EC sensor since the SLVS-EC interface uses embedded clock technology. It also uses 8b10b encoding, which can be recovered using the PolarFire transceiver. PolarFire FPGA has up to 24 low-power 12.7 Gbps transceiver lanes. These transceiver lanes can be configured as the SLVS-EC PHY receiver lanes. As shown in the preceding figure, the transceiver outputs are connected to SLVS-EC Rx IP core.

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Table of Contents
Introduction........................................................................................................................................................................... 1
1. SLVS-EC Receiver Solution............................................................................................................................................ 4
2. Transceiver Configuration............................................................................................................................................ 5 2.1. PLL for Pixel Clock Generation......................................................................................................................... 6
3. Design Description........................................................................................................................................................ 7 3.1. SLVS-EC RX IP Core.............................................................................................................................................8 3.2. FSM with Data Decoding States....................................................................................................................... 9 3.3. Configuration Parameters.............................................................................................................................. 10 3.4. Inputs and Outputs..........................................................................................................................................11
4. Timing Diagram........................................................................................................................................................... 12
5. Resource Utilization.................................................................................................................................................... 13
6. Revision History........................................................................................................................................................... 14
Microchip FPGA Support....................................................................................................................................................15
Microchip Information....................................................................................................................................................... 15 The Microchip Website............................................................................................................................................... 15 Product Change Notification Service........................................................................................................................ 15 Customer Support.......................................................................................................................................................15 Microchip Devices Code Protection Feature............................................................................................................15 Legal Notice..................................................................................................................................................................16 Trademarks.................................................................................................................................................................. 16 Quality Management System.....................................................................................................................................17 Worldwide Sales and Service..................................................................................................................................... 18

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SLVS-EC Receiver Solution

SLVS-EC Receiver Solution (Ask a Question)

The following figure shows the Libero SoC software top level design implementation of SLVS-EC IP and the required components for the SLVS-EC receiver solution.

Figure 1-1. SLVS-EC IP SmartDesign

LANE3_RXD_N LANE3_RXD_P LANE2_RXD_N LANE2_RXD_P LANE1_RXD_N LANE1_RXD_P LANE0_RXD_N LANE0_RXD_P
ARST_N
REF_CLK_PAD_P REF_CLK_PAD_N

PF_XCVR_REF_CLK_C0_0

REF_CLK_PAD_P REF_CLK_PAD_N

REF_CLK

PF_XCVR_REF_CLK_C0

PF_XCVR_ERM_C2_0

PADs_IN LANE3_RXD_N LANE3_RXD_P LANE2_RXD_N LANE2_RXD_P LANE1_RXD_N LANE1_RXD_P LANE0_RXD_N LANE0_RXD_P
LANE0_IN LANE0_CDR_REF_CLK_0 LANE0_PCS_ARST_N LANE0_PMA_ARST_N
LANE1_IN LANE1_CDR_REF_CLK_0 LANE1_PCS_ARST_N LANE1_PMA_ARST_N
LANE2_IN LANE2_CDR_REF_CLK_0 LANE2_PCS_ARST_N LANE2_PMA_ARST_N
LANE3_IN LANE3_CDR_REF_CLK_0 LANE3_PCS_ARST_N LANE3_PMA_ARST_N

LANE0_OUT LANE0_8B10B_RX_K[3:0]
LANE0_RX_CLK_R LANE0_RX_CODE_VIOLATION[3:0]
LANE0_RX_DATA[31:0] LANE0_RX_DISPARITY_ERROR[3:0]
LANE0_RX_IDLE LANE0_RX_READY
LANE0_RX_VAL LANE1_OUT
LANE1_8B10B_RX_K[3:0] LANE1_RX_CLK_R
LANE1_RX_CODE_VIOLATION[3:0] LANE1_RX_DATA[31:0]
LANE1_RX_DISPARITY_ERROR[3:0] LANE1_RX_IDLE
LANE1_RX_READY LANE1_RX_VAL LANE2_OUT
LANE2_8B10B_RX_K[3:0] LANE2_RX_CLK_R
LANE2_RX_CODE_VIOLATION[3:0] LANE2_RX_DATA[31:0]
LANE2_RX_DISPARITY_ERROR[3:0] LANE2_RX_IDLE
LANE2_RX_READY LANE2_RX_VAL LANE3_OUT
LANE3_8B10B_RX_K[3:0] LANE3_RX_CLK_R
LANE3_RX_CODE_VIOLATION[3:0] LANE3_RX_DATA[31:0]
LANE3_RX_DISPARITY_ERROR[3:0] LANE3_RX_IDLE
LANE3_RX_READY LANE3_RX_VAL

PF_XCVR_ERM_C2

PF_CCC_C3_0

REF_CLK_0

OUT0_FABCLK_0 PLL_LOCK_0

PF_CCC_C3

SLVS_EC_RX_C1_0

ARST_N pixel_clock_i lane0_rx_clk_i lane1_rx_clk_i lane0_rx_ready_i lane1_rx_ready_i lane0_rx_valid_i lane1_rx_valid_i lane2_rx_clk_i lane3_rx_clk_i lane2_rx_ready_i lane3_rx_ready_i lane2_rx_valid_i lane3_rx_valid_i lane0_rx_data_i[31:0] lane1_rx_data_i[31:0] lane2_rx_data_i[31:0] lane3_rx_data_i[31:0]

frame_valid_o line_valid_o
header_o[63:0] pixel_data_o[127:0]

SLVS_EC_RX_C1

LANE0_RX_READY OUT0_FABCLK_0
LANE0_RX_VAL LANE0_RX_CLK_R
frame_valid_o line_valid_o header_o[63:0] pixel_data_o[127:0]

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2. Transceiver Configuration (Ask a Question)
The following figure shows the transceiver interface configuration.
Figure 2-1. Transceiver Interface Configurator

Transceiver Configuration

The transceiver can be configured for either two or four lanes. The speed of the transceiver is set using the 'Transceiver Data Rate.' The following table shows the SLVS-EC interface, which supports two baud rates.

Table 2-1. SLVS-EC Baud Rate
Baud Grade 1 2 3

Baud Rate in Mbps 1188 2376 4752

Set the reference clock frequency as per the clock source connected to the transceiver.

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Transceiver Configuration
2.1 PLL for Pixel Clock Generation (Ask a Question)
A PLL is required to generate pixel clock from the Transceiver generated Fabric clock that is, LANE0_RX_CLOCK. Following is the formula to generate pixel clock. Pixel clock = (LANE0_RX_CLOCK × 8)/DATA_WIDTH Configure the PF_CCC for RAW 8 as shown in the following figure.
Figure 2-2. Clock Conditioning Circuitry

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Design Description (Ask a Question)

The following figure shows the SLVS-EC Frame Format structure.

Figure 3-1. SLVS-EC Frame Format Structure

Design Description

The Packet header contains information about the frame start and end signals along with the valid lines. PHY control codes are added above the packet header to form the SLVS-EC packet. The following table lists the different PHY control codes used in the SLVS-EC protocol.

Table 3-1. PHY Control Code
PHY Control Code Start Code End Code Pad Code Sync Code Idle Code

8b10b Symbol Combination K.28.5 - K.27.7 - K.28.2 - K.27.7 K.28.5 - K.29.7 - K.30.7 - K.29.7 K.23.7 - K.28.4 - K.28.6 - K.28.3 K.28.5 - D.10.5 - D.10.5 - D.10.5 D.00.0 - D.00.0 - D.00.0 - D.00.0

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Design Description
3.1 SLVS-EC RX IP Core (Ask a Question)
This section describes the hardware implementation details of SLVS-EC Receiver IP. The following figure shows the Sony SLVS-EC receiver solution that contains the PolarFire SLVS-EC RX IP. This IP is used in conjunction with the PolarFire transceiver interface block. The following figure shows the internal blocks of the SLVS-EC Rx IP.
Figure 3-2. Internal Blocks of the SLVS-EC RX IP

aligner aligner

slvsec_phy_rx

slvsrx_decoder

3.1.1

aligner (Ask a Question)
This module receives the data from the PolarFire transceiver blocks and aligns to the sync code. This module looks for the sync code in the bytes received from the transceiver and locks to the byte boundary.

3.1.1.1

slvsec_phy_rx (Ask a Question)
This module receives the data from the aligner and decodes the incoming SLVS PHY packets. This module passes through the synchronization sequence and then, generates the pkt_en signal starting from Start code and ends at the end code. It also removes the PAD code from the data packets and sends the data to the next module that is slvsrx_decoder.

3.1.1.2

slvsrx_decoder (Ask a Question)
This module receives the data from the slvsec_phy_rx module and extracts the pixel data from the payload. This module extracts four pixels per clock per lane and sends to the output. It generates the line valid signal for the active lines validating the active video data. It also generates the Frame valid signal by looking at the frame start and frame end bits in the packet header of the SLVS-EC packets.

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3.2 FSM with Data Decoding States (Ask a Question)
The following figure shows the FSM for SLVS-EC RX IP.
Figure 3-3. FSM for SLVS-EC RX IP

Design Description

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3.2.1

SLVS-EC Receiver IP Configuration (Ask a Question)
The following figure shows the SLVS-EC receiver IP configurator.
Figure 3-4. SLVS-EC Receiver IP Configurator

Design Description

3.3 Configuration Parameters (Ask a Question)
The following table lists the description of the configuration parameters used in the hardware implementation of SLVS-EC receiver IP block. These are generic parameters and can vary based on the application requirements.

Table 3-2. Configuration Parameters

Name

Description

DATA_WIDTH

Input pixel data width. Supports RAW 8, RAW 10, and RAW 12.

LANE_WIDTH

Number of SLVS-EC lanes. Supports two, four, and eight lanes.

BUFF_DEPTH

Depth of the buffer. Number of active pixels in active video line.

Video Interface

Native and AXI4 Stream

Buffer depth can be calculated by using the following equation: BUFF_DEPTH = Ceil ((Horizontal Resolution × RAW width) / (32 × Lane width)) Example: RAW width = 8, Lane width = 4, and Horizontal Resolution = 1920 pixels BUFF_DEPTH = Ceil ((1920 × 8)/ (32 × 4)) = 120

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3.4

Design Description
Inputs and Outputs (Ask a Question)
The following table lists the input and output ports of the SLVS-EC RX IP configuration parameters for the native video interface.

Table 3-3. Input and Output Ports For Native Video Interface

Signal Name

Direction Width

Description

LANE#_RX_CLK_I

Input 1-bit

Recovered clock from the transceiver for that particular Lane

LANE#_RX_READY_I Input 1-bit

Data ready signal for Lane

LANE#_RX_VALID_I Input 1-bit

Data Valid signal for Lane

LANE#_RX_DATA_I Input 32-bit

Lane recovered data from transceiver

LINE_VALID_O

Output 1-bit

Data valid signal for active pixels in a line

FRAME_VALID_O

Output 1-bit

Valid signal for Active lines in a frame

DATA_OUT_O

Output DATA_WIDTH × LANE_WIDTH Pixel data output × 4

HEADER_O

Output 64-bits

Packet Header

EBD_VALID_O

Output 1-bit

Embedded Data Valid Signal

LANE#_FSM_STATE_O Output 4-bits

Current FSM state

Value 0 1 2 3

FSM State IDLE SYNC_CODE IDLE_CODE SLVS_PACKET

The following table lists the input and output ports of the SLVS-EC RX IP configuration parameters for the AXI4 stream video interface.

Table 3-4. Input and Output Ports for AXI4 Stream Video Interface

Port Name

Type Width

Description

ARST_N

Input 1-bit

Active low asynchronous reset signal to design.

PIXEL_CLOCK_I Input 1-bit

System clock

TDATA_O

Output 4 × g_LANE_WIDTH × g_DATAWIDTH bit

Output Video Data

TVALID_O

Output 1-bit

Output Video Valid

TUSER_O

Output 4-bit

Bit 0 = unused Bit 1 = unused

Bit 2 = unused

Bit 3 = frame valid

TLAST_O TSTRB_O TKEEP_O

Output 1-bit Output g_DATAWIDTH / 8 Output g_DATAWIDTH / 8

Output Video End of Frame Output Video Data strobe Output Video Data Keep

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Timing Diagram (Ask a Question)

The following figure shows the SLVS-EC IP timing diagram.

Figure 4-1. SLVS-EC IP Timing Diagram

Timing Diagram

SLVS-EC IP output is placed from LSB to MSB, and the most recent data is in MSB.

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Resource Utilization

Resource Utilization (Ask a Question)

The following table shows the resource utilization of a sample SLVS-EC Receiver Core implemented in a PolarFire FPGA (MPF300TS-1FCG1152I package), for RAW 8 and four lanes and 1920 horizontal resolution configuration.

Table 5-1. Resource Utilization
Element DFFs 4-input LUTs LSRAMs

Usage 3218 2155 16

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Revision History

Revision History (Ask a Question)

The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication.

Table 6-1. Revision History

Revision Date

Description

10/2024 The following is the list of changes in revision A of the document:

· The document was converted to Microchip template.

· The document number was changed to DS50003779 from UG0877.

5.0

4.0

Added Table 3-4
· Replaced Figure 1-1, Figure 2-1, and Figure 4-1 · Removed section Transmit PLL · Updated Table 2-1, Table 3-2, Table 3-3, and Table 5-1 · Updated section PLL for Pixel Clock Generation · Updated section Configuration Parameters

3.0

· Introduction · Table 3-2

2.0

· Introduction · Transceiver Configuration · Table 3-2

1.0

Initial release

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EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4485-5910 Fax: 45-4485-2829 Finland - Espoo Tel: 358-9-4520-820 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Garching Tel: 49-8931-9700 Germany - Haan Tel: 49-2129-3766400 Germany - Heilbronn Tel: 49-7131-72400 Germany - Karlsruhe Tel: 49-721-625370 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Germany - Rosenheim Tel: 49-8031-354-560 Israel - Hod Hasharon Tel: 972-9-775-5100 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Italy - Padova Tel: 39-049-7625286 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Norway - Trondheim Tel: 47-72884388 Poland - Warsaw Tel: 48-22-3325737 Romania - Bucharest Tel: 40-21-407-87-50 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Sweden - Gothenberg Tel: 46-31-704-60-40 Sweden - Stockholm Tel: 46-8-5090-4654 UK - Wokingham Tel: 44-118-921-5800 Fax: 44-118-921-5820

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References

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