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User Guide for ANALOG DEVICES models including: EVAL-LT8418-BZ 100V Half-Bridge GaN Driver with Smart Integrated Bootstrap Switch, EVAL-LT8418-BZ, 100V Half-Bridge GaN Driver with Smart Integrated Bootstrap Switch, Smart Integrated Bootstrap Switch, Bootstrap Switch
il y a 7 heures — Evaluation Board User Guide. EVAL-LT8418-BZ analog.com. Rev 0. 2 of 11. Quick Start Procedure. The EVAL-LT8418-BZ evaluation circuit is an power stage used to ...
19 hours ago — Evaluation Board User Guide. EVAL-LT8418-BZ analog.com. Rev 0. 2 of 11. Quick Start Procedure. The EVAL-LT8418-BZ evaluation circuit is an power stage used to ...
LT8418 Datasheet and Product Info | Analog Devices
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DocumentDocumentEvaluation Board User Guide EVAL-LT8418-BZ 100V Half-Bridge GaN Driver with Smart Integrated Bootstrap Switch General Description The EVAL-LT8418-BZ evaluation circuit features the LT8418 driving two 100V enhanced Gallium Nitride (eGaN) FETs in a half-bridge configuration. The circuit is optimized as a buck converter, but it can be used as a boost converter or other converter topologies consisting of a half-bridge. The evaluation circuit can deliver up to 10A with good thermal management. An external single or two PWM signals are required to drive the board, depending on the configuration. In the single-input setup, the dead time circuitry on the board is utilized to generate the complement signal and set the dead time. The dead time circuitry is bypassed in the dualinput setup. The LT8418 driver has powerful 0.2 pull-down and 0.6 pull-up drivers driving two 100V GaN FETs. It also integrates a smart integrated bootstrap switch to generate a balanced bootstrap voltage from VCC with a minimum dropout voltage. The LT8418 provides split gate drivers to adjust the turn-on and turn-off slew rates of GaN FETs to suppress ringing and optimize EMI performance. Design files for this circuit board are available. Performance Summary (TA = 25C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Voltage1 Output Voltage Output Current2 Auxiliary Supply Voltage Gate Driver Supply Voltage VIN 80 V VOUT 80 V IOUT 10 A VAUX 5.5 80 V VCC VAUX = 6V, R1 = 604k, R4 = 200k 5 V PWM Logic Input Voltage Threshold VPWM_TH PWM Logic Input Minimum Width Switching Frequency3 Dead Time from BG Falling to TG Rising Dead Time from TG Falling to BG Rising Efficiency tPWM_MIN fSW td(BG_TG) td(TG_BG) VCC = 5V High PWM input Low PWM input Open VIN, single PWM input signal, R3 = 30, R6 = 47 VOUT = 24V, 500kHz 2.1 3.4 1.2 2.2 11 0.1 1 10 5.4 9.3 97.5 V ns MHz ns ns % VIN = 48V, VOUT = 24V, 1MHz 97.4 % IOUT = 10A VOUT = 12V, 500kHz 96.2 % VOUT = 12V, 1MHz 95.5 % 1 Maximum input voltage depends on inductive loading. Maximum switch node ringing must be kept under 100V for EPC2204. 2 Maximum output current depends on EPC2204 FET temperature, affected by switching frequency, input voltage, output voltage, and thermal management. Make sure to monitor the die temperature when setting the output current. 3 At high switching frequencies, switching loss is dominant. Input voltage and output current should be reduced to prevent overheating of the GaN FETs. Rev 0 One Analog Way, Wilmington, MA 01887-2356, U.S.A. DOCUMENT FEEDBACK Tel: 781.329.4700 TECHNICAL SUPPORT ©2023 Analog Devices, Inc. All rights reserved. Evaluation Board User Guide EVAL-LT8418-BZ Quick Start Procedure The EVAL-LT8418-BZ evaluation circuit is an power stage used to evaluate the performance of the LT8418. See Figure 1 for proper measurement equipment setup and use the following procedure: 1. With power off, connect the input power supply to the board through the VIN and GND terminals. Connect the auxiliary power supply to the AUX INPUT and GND terminals. Connect the load to the VOUT and GND terminals. Connect the function generator output to the INT and GND pins of header J1. 2. Turn on the auxiliary power supply at 6V. 3. Set the function generator to output a 5V, 1MHz, 50% duty cycle, high-Z output pulse waveform. 4. Turn on the input power supply at 0V, 7A limit. Increase the voltage slowly to 48V. 5. Check for the proper output voltage, which should be 24V (±5%). 6. Once the proper output voltage is established, adjust the input voltage and load current within the operating range, and observe the gate signals, switch node voltage, voltage ripple, efficiency, and other parameters. NOTE: When probing the gate signals or switch node, it is recommended to use the ground spring to avoid parasitic inductance in the long ground lead. Measure the input or output voltage ripple by touching the probe tip directly across the VIN (J2) and GND (J3), or VOUT (J4) and GND (J5) terminals. 001 Figure 1. EVAL-LT8418-BZ Board Connections in Single-PWM-Input Control Mode analog.com Rev 0 2 of 11 Evaluation Board User Guide EVAL-LT8418-BZ Output Voltage and Power The EVAL-LT8418-BZ can be configured as either a buck or a boost converter, or other converter topologies consisting of a half-bridge with maximum input and output voltages of 80V. However, the converter is optimally designed to convert 48VIN to 24VOUT at 1MHZ, delivering up to 10A with a heat sink or forced airflow. At full load with forced airflow, although the board can deliver 240W, the top FET heats up significantly. Therefore, a heat sink is recommended if this operating condition is expected over an extended period. Please see the "thermal considerations" section for more details on using a heat sink. The conversion ratio can be adjusted by changing the duty cycle of the PWM input signal(s), while the switching frequency is set by the PWM input signal frequency. To optimize the converter efficiency at a different power specification, passive power components inductors and input/output capacitors should be resized appropriately. The dead times must also be adjusted to minimize the loss during the dead time. Figure 3 and Figure 4 show the converter efficiency versus the load current at different operating conditions. LDO Setting An LDO (U3) is used to supply power to the LT8418 and dead time circuitry. The output voltage VCC of the LDO is set to 5V in the default configuration, but it can be adjusted by changing R2 and R4 values. The input power of U3 comes from either a default auxiliary power supply, AUX INPUT, ranging from 5.5V to 80V, or directly from the board's input power supply, which can be selected by changing the position of jumper JP1. Control Mode The EVAL-LT8418-BZ circuit is an open-loop half-bridge converter without a feedback network and control loop. Hence, the board requires two complementary PWM signals to drive the INT and INB pins of the LT8418. These signals come from either one (in single-PWM-input mode) or two (in dual-PWM-input mode) external PWM signals provided by a function generator or microcontroller. The single-PWM-input mode is the default control scheme of this evaluation board. In this mode, only a single PWM output of the function generator is connected to header J1, as shown in Figure 1. The positive terminal is tied to the leftmost pin (labeled INT), while the negative terminal is tied to the middle pin (labeled GND). Alternatively, two separate PWM signals can be applied to header J1 to control INT and INB pins independently in the dual-PWM-input mode. To enable this control mode, some component-level modifications are required to bypass the RC filters. Specifically, R5 must be removed and R7, R3, and R6 must be shorted with 0 resistors. The positive sides of INT and INB inputs are applied at the leftmost pin (labeled INT) and rightmost pin (labeled INB) of header J1, respectively. As the dead time circuitry no longer generates dead times between INT and INB input signals, careful control must be taken in this control mode to prevent a shoot-through incident. Table 1 lists the circuit configurations of two control modes. Table 1. Circuit Configurations For Control Modes Control Mode Single PWM Input1 Dual PWM Inputs 1 Default configuration 2 Resistance value can be changed to adjust the dead time R5 Shorted Open R7 Open Shorted R3 30 2 Shorted R6 47 2 Shorted Dead Time In the single-PWM-input control mode, the dead times of gate signals are set by the dead-time circuitry consisting of two inverters and RC filters. The input PWM signal is first inverted and split into two complementary signals by the Schmitttrigger inverter U2. The two signals are then delayed by the RC filters, setting the dead times before being inverted again by another inverter U4. These two resulting signals are applied to the INT and INB pins driving the LT8418. The default dead times on the board are optimized for 48VIN, 24VOUT, 1MHz fSW, and 10A IOUT operating conditions. However, the dead times can be adjusted by changing R3 and R6 values to evaluate the impact of dead time on efficiency. When analog.com Rev 0 3 of 11 Evaluation Board User Guide EVAL-LT8418-BZ changing the dead times, careful design must be taken to avoid a shoot-through condition. Figure 2 shows the relationship between the resistor values and dead times between INT and INB signals. 16 R6 vs INT FALLING TO INB RISING DEAD TIME 14 R3 vs INB FALLING TO INT RISING DEAD TIME 12 DEAD TIME (ns) 10 8 6 4 2 0 10 20 30 40 50 60 70 80 90 100 RESISTANCE () Thermal Considerations Figure 2. Dead Times vs. Resistor Values At high switching frequencies and high output power, care must be taken to prevent overheating on the GaN FETs. For better thermal management, the EVAL-LT8418-BZ is equipped with four mechanical spacers that can be used to attach a heat sink (527-45AB) to the bottom layer. Since all the high-profile components are placed on the top layer, the heat sink is easily placed on the bottom layer against the surface of GaN FETs and the LT8418. A thermal pad and a thermal spreader (4051100100017) should be inserted under the heat sink to ensure good contact, improving thermal dissipation. Measurement Considerations A high-speed differential probe such as the IsoVu probe from Tektronix is recommended for measuring the high-side gate voltage at header TP10. It has low parasitic elements, suitable for measuring high-frequency waveforms. Low parasitic capacitance passive probes with ground springs are recommended for measuring voltage at other nodes. The surfacemount sockets (TP1-TP7) are equipped on the top layer for easy probing. analog.com Rev 0 4 of 11 Evaluation Board User Guide EVAL-LT8418-BZ EFFICIENCY (%) EFFICIENCY (%) Performance (VIN = 48V, TA = 25C, unless otherwise noted.) 100 99 98 97 96 95 94 93 92 91 500kHz 1MHz 90 0 1 2 3 4 5 6 7 8 9 10 LOAD CURRENT (A) Figure 3. Efficiency vs. Load Current at 24VOUT (Forced Airflow) 100 99 98 97 96 95 94 93 92 91 90 89 88 500kHz 87 1MHz 86 0 1 2 3 4 5 6 7 8 9 10 LOAD CURRENT (A) Figure 4. Efficiency vs. Load Current at 12VOUT (Forced Airflow) INB 5V/DIV INT 5V/DIV BG 5V/DIV TGSW 5V/DIV SW 5V/DIV 100ns/DIV Figure 5. Steady-State Waveform at Open VIN, 1MHz INB 5V/DIV INT 5V/DIV BG 5V/DIV TGSW 5V/DIV SW 20V/DIV 100ns/DIV Figure 6. Steady-State Waveform at 24VOUT, 0A IOUT, 1MHz 006 INB 5V/DIV INT 5V/DIV BG 5V/DIV TGSW 5V/DIV INB 5V/DIV INT 5V/DIV BG 5V/DIV TGSW 5V/DIV 005 007 SW 20V/DIV 100ns/DIV Figure 7. Steady-State Waveform at 24VOUT, 10A IOUT, 1MHz (Forced Airflow) analog.com SW 20V/DIV 100ns/DIV Figure 8. Steady-State Waveform at 12VOUT, 10A IOUT, 1MHz (Forced Airflow) Rev 0 5 of 11 008 Evaluation Board User Guide EVAL-LT8418-BZ 120 110 100 90 80 70 60 50 40 30 20 °C Figure 9. Thermal Image of Top Layer at 24VOUT, 5A IOUT, 500kHz. (Thermal Values are on L1) 009 120 110 100 90 80 70 60 50 40 30 20 °C Figure 10. Thermal Image of Bottom Layer at 24VOUT, 5A IOUT, 500kHz. (Thermal Values are on Q1) 010 120 110 100 90 80 70 60 50 40 30 20 °C Figure 11. Thermal Image of Top Layer at 24VOUT, 5A IOUT, 1MHz. (Thermal Values are on L1) 011 120 110 100 90 80 70 60 50 40 30 20 °C Figure 12. Thermal Image of Bottom Layer at 24VOUT, 5A IOUT, 1MHz. (Thermal Values are on Q1) 012 120 110 100 90 80 70 60 50 40 30 20 °C Figure 13. Thermal Image of Top Layer at 24VOUT, 10A IOUT, 1MHz (Forced Airflow, Thermal Values are on L1) 013 120 110 100 90 80 70 60 50 40 30 20 °C Figure 14. Thermal Image of Bottom Layer at 24VOUT, 10A IOUT, 1MHz (Forced Airflow, Thermal Values are on Q1) 014 analog.com Rev 0 6 of 11 Evaluation Board User Guide EVAL-LT8418-BZ 120 110 100 90 80 70 60 50 40 30 20 °C Figure 15. Thermal Image of Top Layer at 24VOUT, 10A IOUT, 1MHz (with Heat Sink, Thermal Values are on L1) 015 016 120 110 100 90 80 70 60 50 40 30 20 °C Figure 16. Thermal Image of Bottom Layer at 24VOUT, 10A IOUT, 1MHz (with Heat Sink, Thermal Values are on Heat Sink) analog.com Rev 0 7 of 11 Evaluation Board User Guide EVAL-LT8418-BZ Bill of Materials ITEM QTY DESIGNATOR 1 2 C1, C7 2 1 C2 3 3 C3, C16, C22 4 2 C4, C20 5 3 C5, C6, C18 6 4 C8, C9, C10, C11 C12, C13, C26, 7 4 C27 C14, C15, C23, 8 5 C24, C25 9 2 C17, C21 10 2 C19, C28 11 2 D1, D2 12 1 L1 13 2 Q1, Q2 14 1 R1 15 2 R2, R8 16 1 R3 17 1 R4 18 3 R5, R10, R13 19 1 R6 20 1 R9 21 1 R11 23 1 R12 24 2 R16, R17 25 1 U1 26 1 U2 27 1 U3 28 1 U4 1 0 C29 2 2 D3, D4 3 1 R14 4 1 R15 5 0 R7 1 8 E1 to E8 2 1 J1 3 4 J2 to J5 4 1 JP1 5 4 MP1 to MP4 6 4 MP5 to MP8 DESCRIPTION REQUIRED CIRCUIT COMPONENTS CAP., 100pF, C0G, 50V, 5%, 0402 CAP., 1µF, X7S, 100V, 10%, 0805, AEC-Q200 CAP., 0.1µF, X7R, 100V, 10%, 0805 CAP., 4.7µF, X7R, 16V, 10%, 0805 CAP., 0.1µF, X7R, 16V, 10%, 0603 CAP., 4.7µF, X7S, 100V, 20%, 1206 CAP., 47µF, ALUM ELECT, 100V, 20%, SMD, RADIAL, 1012, 150 CRZ Series, AEC-Q200 CAP., 4.7µF, X7S, 100V, 10%, 1210 CAP., 0.1µF, X7R, 16V, 10%, 0402 CAP., 10pF, C0G, 50V, 5%, 0402 DIODE, SCHOTTKY, 40V, 30mA, SOD-523 IND., 4.7µH, PWR, 20%, 24A, 5.7m, SMD, 11.8mm x 10.5mm x 10mm, AEC-Q200 XSTR., ENHANCEMENT-MODE GaN FET, 100V, 29A, 2.5mm x 1.5mm RES., 604k, 1%, 1/10W, 0603, AEC-Q200 RES., 10k, 1%, 1/16W, 0402, AEC-Q200 RES., 30, 1%, 1/16W, 0402 RES.,200k,1%,1/10W,0603 RES., 0, 1/16W, 0402 RES., 47, 1%, 1/16W, 0402 RES., 5.6,1%, 1/16W, 0402, AEC-Q200 RES., 0.005, 1%, 2W, 2512, LONG-SIDE TERM, METAL, SENSE RES., 2, 1%, 1/16W, 0402, AEC-Q200 RES., 0, 1/10W, 0603, AEC-Q200 IC, 100V Half-Bridge GaN Driver, WLCSP-12 IC, 3CH Schmitt-Trigger Inverter, VSSOP-8 IC, 250mA, 4V to 80V LDO Linear Reg, DFN-12 IC, Dual Schmitt-Trigger Inverter, SOT23-6 OPTIONAL CIRCUIT COMPONENTS CAP., OPTION, 0603 LED, GREEN, WATER-CLEAR, 0805 RES.,1k, 5%, 1/10W,0603, AEC-Q200 RES., 100k, 5%, 1/4W, 1206, AEC-Q200 RES., 0, 1/16W, 0402 HARDWARE FOR DEMO BOARD ONLY TEST POINT, TURRET, 0.064" MTG. HOLE, PCB 0.062" THK CONN., HDR., MALE, 1 x 4, 2.54mm, VERT, STR, THT CONN., BANANA JACK, FEMALE, THT, NONINSULATED, SWAGE, 0.218" CONN., HDR,MALE, 1 x 3, 2mm, VERT, ST, THT STANDOFF, NYLON, SNAP-ON, 0.625 (5/8"), 15.9mm STANDOFF, STEEL, ROUND, 5.1mm OD, 3.5mm ID, 1mm BODY LENGTH, 2.4mm OVERALL LENGTH, FEMALE, M2.5, THREADED, SMT MANUFACTURER PART NUMBER MURATA, GRM1555C1H101JA01D MURATA, GCM21BC72A105KE36L TDK, C2012X7R2A104K125AA AVX, 0805YC475KAT2A WURTH ELEKTRONIK, 885012206046 MURATA, GRM31CC72A475ME11L VISHAY, MAL215099905E3 MURATA, GRM32DC72A475KE01L MURATA, GRM155R71C104KA88D MURATA, GJM1555C1H100JB01D DIODES INC., SDM03U40-7 COILCRAFT, XAL1010-472MEB EFFICIENT POWER CONVERSION, EPC2204 VISHAY, CRCW0603604KFKEA VISHAY, CRCW040210K0FKED YAGEO, RC0402FR-0730RL VISHAY, CRCW0603200KFKEA VISHAY, CRCW04020000Z0ED VISHAY, CRCW040247R0FKED VISHAY, CRCW04025R60FNED Ohmite, FCSL64R005FER VISHAY, CRCW04022R00FKED VISHAY, CRCW06030000Z0EA ANALOG DEVICES, LT8418ACBZ-R7 TEXAS INSTRUMENTS, SN74LVC3G14DCUR ANALOG DEVICES, LT3012EDE#PBF TEXAS INSTRUMENTS, SN74LVC2G14DBVR LITE-ON, LTST-C170KGKT VISHAY, CRCW06031K00JNEA VISHAY, CRCW1206100KJNEA VISHAY, CRCW04020000Z0ED MILL-MAX, 2308-2-00-80-00-00-07-0 SAMTEC, TSW-104-07-L-S KEYSTONE, 575-4 Wurth Elektronik, 62000311121 KEYSTONE, 8834 WURTH ELEKTRONIK, 9774010151R analog.com Rev 0 8 of 11 Evaluation Board User Guide EVAL-LT8418-BZ HEATSINK, EXTRUDED, 1/2 BRICK DC/DC CVRTR, 2.28" x 2.40" x 0.45", HORZ, RECT, 11-FIN, ALUM, 7 0 MP9 BLK ANODIZE Wakefield-Vette, 527-45AB 8 0 MP10 HEAT SPREADER 100MMX100MM W/ADH Wurth Elektronik, 4051100100017 CONN., HDR, SOCKET, RCPT, FEMALE, 1 x 2, 9 7 TP1 to TP7 2.54mm, VERT, ST, SMD Mill-Max, 310-43-102-41-105000 10 3 TP8,TP9,TP10 CONN., HDR,MALE, 1 x 2, 2.54mm, VERT, ST, SMD SAMTEC, TSM-102-01-L-SV 11 1 XJP1 CONN., SHUNT, FEMALE, 2-POS, 2mm Wurth Elektronik, 60800213421 analog.com Rev 0 9 of 11 Evaluation Board User Guide Schematic analog.com VIN 6V 36V N E1 C2 C1 100u 50V EE E1 101P C3 C4 C5 10u 50V 1210 E2 Figure 17. EVAL-LT8418-BZ Schematic J1 INT 1 GND 2 GND 3 INB 4 PWM INPUT U2B SN74LVC3G14DCUR VCC 8 3 5 4 R2 10k C6 0.1uF 0603 1 R8 10k 4 8 6 U2A SN74LVC3G14DCUR 7 4 8 U2C SN74LVC3G14DCUR 2 R5 0 R7 0 DNP DEAD TIME CIRCUIT R3 30 D1 2 1 SDM03U40 R6 47 D2 2 1 SDM03U40 INT_IN C1 100pF INB_IN C7 100pF AUX INPUT 5.5V-80V E1 GND E2 JP1 1 VAUX=/VIN 2 VAUX=VIN 3 C2 1uF 100V 0805 C3 0.1uF 100V 0805 U3 LT3012EDE 10 IN 11 IN 8 SHDN 1 6 7 9 12 NC NC NC NC NC OUT 2 OUT 3 ADJ 4 GND 5 13 GND VCC REGULATOR C R1 604k 0603 R4 200k 0603 VCC C4 4.7uF 16V 0805 C5 0.1uF 16V TP1 0603 1 VCC GND 2 VCC U4A SN74LVC2G14DBVR 5 INT_IN 1 6 C18 0.1uF 0603 R10 0 2 U4B SN74LVC2G14DBVR 5 INB_IN 3 4 R13 0 2 VCC R14 1k 0603 VCC 2 D3 GREEN VCC C19 10pF INT INT 2 1 TP5 C20 4.7uF 16V 0805 INB C28 10pF INB 2 1 TP7 VIN R15 100k 2 1206 VIN D4 GREEN U1 A3 C4 VCC VCC B4 INT C21 0.1uF A4 INB BST D3 TGP D2 TGN D1 SW SW C1 D4 BGP B1 A1 BGN GND A2 LT8418ACBZ-R7 BST 1 2 TP2 TG 2 1 TP3 BST R9 5.6 C17 0.1uF TG 1 TG TP10 SW R12 2 BG 1 TP4 2 1 BG TP6 1 2 SW 2 3 4 5 2 3 6 4 5 VIN MAL215099905E3 E3 VIN VIN MAX : 80V, 10A C8 4.7uF 100V 1206 C9 4.7uF 100V 1206 C10 4.7uF 100V 1206 C11 4.7uF 100V 1206 C12 C13 +47uF +47uF 100V 100V C14 4.7uF 1210 100V C15 4.7uF 1210 100V C16 0.1uF 100V 0805 J2 GND J3 E4 Q1 EPC2204 6 L1 4.7uH SW 1 2 XAL1010-472MEB Q2 EPC2204 TP9 D R11 0.005 FCSL64R005FER R16 R17 0 0 C29 VOUT C22 0.1uF 100V 0805 C23 4.7uF 1210 100V C24 4.7uF 1210 100V GND VOUT E5 C25 4.7uF 1210 100V VOUT MAX : 80V, 10A MAL215099905E3 J4 A C26 C27 +47uF +47uF 100V 100V GND J5 OPT S IOUT+ IOUT- E8 GND E6 TP8 E7 IOUT+ IOUT- 1 1 NOTES: UNLESS OTHERWISE SPECIFIED 1. ALL RESISTORS ARE 0402. ALL CAPACITORS ARE 0402. P1 1 S N 2 EN 3 N TE UNLESS T ERWIS 1. ALL RESIST RS ARE 0603 ALL CAPACIT RS ARE 06 5 017 EVAL-LT8418-BZ Rev 0 10 of 11 Evaluation Board User Guide EVAL-LT8418-BZ ASSUMED BY ANALOG DEVICES FOR ITS USE, NOR FOR ANY INFRINGEMENTS OF PATENTS OR OTHER RIGHTS OF THIRD PARTIES THAT MAY RESULT FROM ITS USE. SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. NO LICENCE, EITHER EXPRESSED OR IMPLIED, IS GRANTED UNDER ANY ADI PATENT RIGHT, COPYRIGHT, MASK WORK RIGHT, OR ANY OTHER ADI INTELLECTUAL PROPERTY RIGHT RELATING TO ANY COMBINATION, MACHINE, OR PROCESS WHICH ADI PRODUCTS ALL INFORMATION CONTAINED HEREIN IS PROVIDED "AS IS" WITHOUT REPRESENTATION OR WARRANTY. NO RESPONSIBILITY IS OR SERVICES ARE USED. TRADEMARKS AND REGISTERED TRADEMARKS ARE THE PROPERTY OF THEIR RESPECTIVE OWNERS. analog.com Rev 0 11 of 11