User Manual for STMicroelectronics models including: UM3198 Dual Active Bridge Bidirectional Power Converter, UM3198, Dual Active Bridge Bidirectional Power Converter, Bridge Bidirectional Power Converter, Bidirectional Power Converter, Power Converter
4 dic 2023 — The equivalent average model of the DAB can be described by the following schematic and equivalent controlled source mathematical representation. UM3198. DAB ...
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DocumentDocumentUM3198
User manual
25 kW, dual active bridge bidirectional power converter for EV charging and battery energy storage systems
Introduction
This reference design represents a complete solution for high power bidirectional DC-DC power converter in dual active bridge topology based on ACEPACK2 SiC power modules. An STM32G474 MCU Mixed-Signal digital platform optimized for Digital Power is used to control the power converter. The latest generation SiC power modules and high-frequency operation (100 kHz) ensure very high performance and design optimization. Soft switching DAB behavior is managed by modulation techniques according to load/voltage variation. This reference design consists of the following separate modules: · STDES-DABBIDIRP: main power board with ACEPACK 2 SiC power modules, a full bridge A2F12M12W2-F1 and two
A2H6M12W3-F for primary HV side and secondary LV side, respectively. The power board design also includes bulk capacitors, sensing sections, and auxiliary power supply. · STDES-DABBIDIRDF: driver board for full bridge ACEPACK 2 A2F12M12W2-F1 SiC power modules based on STGAP2SiCS Galvanically isolated 4 A single gate driver for SiC MOSFETs · STDES-DABBIDIRDH: two driver boards for half bridges ACEPACK2 A2H6M12W3-F SiC power modules based on STGAP2SiCS galvanically isolated 4 A single gate driver for SiC MOSFETs · STDES-PFCBIDIRC: control board based on the STM32G4 series microcontroller with connectors for communication and programming, and test-points and status indicators for testing and monitoring.
Figure 1. STDES-DABBIDIR reference design board
The latest technology SiC MOSFETs power modules used at high switching frequency (100 kHz) and the topology structure allow nearly 98% efficiency and the use of smaller and more cost-effective passive power components.
This high efficiency bidirectional isolated DC-DC converter is designed for several end applications such as electric vehicles (EV) and industrial battery chargers, and industrial equipment requiring very high efficiency and reliability.
UM3198 - Rev 1 - December 2023 For further information contact your local STMicroelectronics sales office.
www.st.com
UM3198
Safety and compliance information
1
Safety and compliance information
Important:
·
The reference design uses voltage levels that can cause serious injury and even death.
·
Due to the high-power density, the components on the board as well as the heat sink can be heated to a
very high temperature, which can cause a burning risk when touched directly.
·
This board is intended for use by experienced power electronics professionals who understand the
necessary precautions against potential dangers and risks while operating this board, even when it is not
powered.
The STDES-DABBIDIR evaluation board is designed for demonstration purposes only and is not intended for domestic or industrial installations.
Danger:
The high voltage levels used to operate the STDES-DABBIDIR evaluation board may provoke a serious electrical shock. This evaluation board must be used in a suitable laboratory by qualified personnel only, familiar with the installation, use, and maintenance of power electrical systems. During operation, do not touch the board as some of its components may reach very high temperatures.
UM3198 - Rev 1
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2
Overview
UM3198
Overview
2.1
Features
·
Reference design modular kit:
Main power board
Driving board (1xHV side 2xLV side)
STM32G474RET3 control board
·
Dual active bridge DC-DC power converter:
Nominal DC input voltage 800 V
Nominal DC output voltage 400 V
Nominal power 25 kW
Switching frequency 100 kHz
Peak efficiency 98.4%
·
Main features:
ACEPACK 2 SiC power module to optimize power section integration and thermal dissipation
Bidirectional capability
Extended soft switching behavior enabled by enhanced modulation techniques management
Isolated SiC gate driver
STM32G4 family MCU for customizable full digital solution
Inrush current control and soft startup
·
High frequency operation with SiC MOSFETs:
High efficiency ~99%
Smaller and lighter passive elements
UM3198 - Rev 1
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Figure 2. STDES-DABBIDIR reference design overview
UM3198
Overview
Figure 3. STDES-DC2DCDAB block diagram
2.2
Main characteristics
Description HV DC Voltage
Table 1. Main characteristics
Symbol VDCHV
Min. Typ. Max. Unit
720
800
880
V
Comments
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UM3198
Overview
Description LV DC Voltage Maximum output power Switching frequency Peak efficiency
Symbol VDCLV PoutMAX fSW
n
Min. Typ. Max. Unit
400
V
25
kW
70
kHz
>98
%
Comments At nominal voltages At nominal voltages
2.3
Dual active bridge topology
The dual active bridge is a bidirectional, dc-dc converter that includes two full bridges, a high frequency transformer, energy transfer inductor, and dc-link capacitors. Due to the symmetry of this converter, with identical primary and secondary bridges, it is capable of bidirectional power flow control.
Each full-bridge consists of two totem-poled switching devices configuration, driven with complimentary signals. The switching frequency of these complimentary devices is referred to as the switching frequency of the converter.
The topology is shown in Figure 3, where Vin and Vout are the dc-link voltages and Lk is the actual resonance inductance, which includes leakage inductance of the transformer plus any additional auxiliary energy transfer inductance. Equivalent AC primary and secondary voltages are controlled by the actual configuration of semiconductor switches M1-M8.
With insulated gate bipolar transistor (IGBT) implementations, switching cells are traditionally implemented with antiparallel diodes and snubber capacitors to direct current commutation on switching events and to allow zero voltage switching (ZVS) through the snubber capacitor and energy transfer inductance resonance.
Now, high-voltage MOSFETs are selected for DAB designs because their intrinsic body diode and drain-to-source output capacitance take the place of external components and help reduce the part count of the converter.
Wide bandgap power MOSFETs such as silicon carbide (SiC) are commonly used for high-power DABs to increase switching frequency operation of the converter and increase power density in DAB applications.
2.4
Typical application
A typical application of DAB power converter is the EV battery DC charger. A three phase system suitable for the proposed power level is shown in the following figure.
Figure 4. Typical DC battery charger architecture
The DC fast charger consists of a three-phase active front end (AFE) rectifier that provides a regulated DC link from a universal three-phase AC input. The current from the grid must be high quality current to fulfill the power quality requirements. The DAB operation ensures isolation and bidirectional operation required by the downstream DC-DC converter.
The full-bridge A2F12M12W2-F and half-bridge A2H6M12W3 ACEPACK 2 SiC power modules selected for primary and secondary side, respectively, ensure very high integration for this topology.
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Figure 5. SiC power module assembly
UM3198
Overview
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UM3198
DAB converter operation
3
DAB converter operation
The DAB converter contains two voltage sourced full bridge circuits that are connected to the inductor L and the high frequency transformer. To transfer power, time varying voltages vAC1 t = vDAB1 t and vAC2 t = vDAB2 t must be provided by the full bridge circuits to both, the high frequency transformer, and the converter inductor L.
Figure 6. DAB topology
+V1 I T1, T4on&T2, T3off
vDAB1 t =
0
II T1, T4on&T2, T3off III T1, T4off&T2, T3on
(1)
-V1 IV T1, T4on&T2, T3off
+V2 I T5, T8on&T6, T7off
vDAB2 t =
0
II T5, T8on&T6, T7off III T5, T8off&T6, T7on
(2)
-V2 IV T5, T8on&T6, T7off
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Figure 7. DAB operation (combo)
UM3198
DAB converter operation
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UM3198
DAB converter operation The HV and LV side full-bridge circuits can therefore be replaced by the respective voltage sources vAC1 t = vDAB1 t and vAC2 t = vDAB2 t to simplify the analysis of the DAB converter.
Figure 8. Simplified diagram of DAB
The primary side referred equivalent circuit diagram is shown below. Figure 9. Primary side referred simplified diagram of DAB
According to the simplified circuit, the inductance voltage depends on the AC voltage of the full bridges.
vLk t = vDAB1 t - nvDAB2 t
(3)
Then we obtain the inductor current.
Ts
iL t
= iL t0
+
1 L
2
0
vLk
t
dt t0
<
t1
(4)
We now consider the instantaneous power for both sides.
(5) p1 t = vDAB1 t iL t
p2 t = nvDAB2 t iL t
The average power over one switching cycle Ts , Ts = 1/fs , is finally calculated.
P1
=
1 Ts
t0 +
t0
Ts
p1
t
dt
P2
=
1 Ts
t0 +
t0
Ts
p2
t
dt
(6)
As equivalent AC bridge voltages can be represented by two sinusoidal waveforms with phase shift :
V1 t = V1cos t V2 t = V2cos t -
(7)
For inductor current, the equivalent phasor is:
IL
=
V 1 - V 2 jLlk
=
V10 - nV2 jLlk
(8)
That
for
time
and
considering
cos j
=
sin
becomes:
iL t
=
V1 Llk
sin
t
-
nV2 Llk
sin
t
-
(9)
Next we obtain instantaneous output power:
p2 t
=
nV1V2 Llk
cos
t -
sin
t
(10)
Which averaged over the switching period T becomes:
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UM3198
DAB converter operation
P2 = p2 t
1 T
=
1 T
0Tp2
t
dt
=
nV1V2 2fsLlk
sin
(11)
As shown by the equation, the DAB allows power flow in both directions according to the sign of the phase shift.
Power transfer is modulated according to the amplitude of
the phase
shift, with maximum
at =
±
2
.
Figure 10. Power transfer vs phase shift in DAB
In addition, according to this relation, the power level of the DAB converter is thus typically adjusted using one or more of the following control parameters.
1. The phase shift, , between vDAB1 t and vDAB2 t , with - < <
2. The duty cycle, D1, of vDAB1 t , with 0 < D1 < 1/2
3. The duty cycle, D2, of vDAB2 t , with 0 < D2 < 1/2
4. The switching frequency fs
Defining
the
phase
shift
duty
ratio
D
=
rad
,
the
actual
power
transfer
can
be
derived
from
the
following
equation.
Pout
=
nVDC1VDC2 2Lfs
D
1-D
To define the control strategy of the DAB converter and the control parameters, knowledge of the equivalent dynamic model of the converter must be considered.
The equivalent average model of the DAB can be described by the following schematic and equivalent controlled source mathematical representation.
UM3198 - Rev 1
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Figure 11. Average model of the DAB
UM3198
DAB converter operation
I2
=
nVi 2Lfs
D
1
-
D
Ii, avg
=
nVo 2Lfs
D
1-D
To obtain the small-signal model, perturbation is injected to define the effects of the parameters on the equation.
ii, avg = Ii, avg + ii, avg
i2 = I2 + i2
ii, avg
=
ii, avg d
Qd +
ii, avg vo
Qvo
=
F1d + F2vo
i2 =
i2 d
Qd +
i2 vi
Qvo = F3d + F4vo
F1 =
ii, avg d
Q=
nVo 2Lfs
1-2 d
F2 =
ii, avg vo
Q=
nVo 2Lfs
d
1-
d
F3 =
i2 d
Q=
nVi 2Lfs
1-2 d
F4 =
i2 vi
Q=
nVi 2Lfs
d
1-
d
Thanks to input capacitance and PFC stage regulation, input voltage perturbation may be neglected.
F4 =
i2 vi
Q=
nVi 2Lfs
d
1-
d
0
The output capacitor ripple voltage is now included through the following equation.
C2
dvo dt
=
i2
-
ii, avg
The final equivalent small signal circuit is then obtained.
ii, avg = F1d + F2vo =
nVo 2Lfs
1-2 d
d
+
nVo 2Lfs
d
1-
d
vo
i2 = F3d =
nVi 2Lfs
1-2 d
d
C2
dvo dt
=
i2
-
ii, avg
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UM3198
DAB converter operation
Figure 12. Simplified small signal equivalent circuit of DAB converter
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UM3198
STDES-DABBIDIR reference design overview
4
STDES-DABBIDIR reference design overview
4.1
Power stage of the STDES-DABBIDIR reference design
STDES-DABBIDIRP consists of a dual active bridge converter topology implementing ACEPACK 2 SiC power modules in the power section.
The driving section is based on two different PCB modules to optimize the driving path of each module. Fan cooling is used to simplify the evaluation of the reference design platform.
Figure 13. Power stage blocks
4.2
Driving stage of the STDES-DABBIDIR reference design
Two different driving boards are proposed to feed the driving signal to ACEPACK 2 SiC power modules. Both solutions are based on STGAP2SICS gate drivers for SiC technology.
The STGAP2SICS single gate driver provides galvanic isolation between the gate driving channel and the low voltage control and interface circuitry. The gate driver is characterized by 4 A capability and rail-to-rail outputs, making the device also suitable for mid and high-power applications such as power conversion and motor driver inverters in industrial applications. The configuration featuring a single output pin and Miller clamp function prevents gate spikes during fast commutations in half-bridge topologies.
The device integrates UVLO protection with optimized value for SiC MOSFETs and thermal shutdown to facilitate the design of highly reliable systems. Dual input pins allow the selection of signal polarity control and implementation of hardware interlocking protection to avoid cross-conduction in case of controller malfunction.
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UM3198
STDES-DABBIDIR reference design overview
Figure 14. STDES-DABBIDIRDF driver board based on 4xSTGAP2SIC
Figure 15. STDES-DABBIDIRDH driver board based on 2xSTGAP2SIC
4.3
Control stage of the STDES-DABBIDIR reference design
The control stage is based on STM32G474RE MCU devices with high-performance Arm® Cortex®-M4 32-bit RISC core. The Cortex-M4 core features a single-precision floating-point unit (FPU), which supports all the Arm single-precision data-processing instructions and all the data types. It also implements a full set of digital signal processing (DSP) instructions and a memory protection unit (MPU) to enhance application security.
Reference design firmware is provided to help evaluate the full functionality of this power platform. The digital power converter architecture and STM32Cube environments help optimize the implementation and use of the source code.
The hardware abstraction and middleware layers contain the peripheral and application-related functions to manage and extend the functionality.
The application layer allows us to manage operation features such as startup procedure load management, control, and protection, as well as the finite state machine.
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UM3198
STDES-DABBIDIR reference design overview Figure 16. STDES-DABBIDIR FW architecture
The general purpose STDES-PFCBIDIR control board based on the STM32G474 MCU is suitable for various high-power applications. This control board supports additional communication and debugging features such as I2C, UART, status LEDs, and analog monitoring, to extend the usage of the MCU peripherals.
Figure 17. Control stage blocks
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UM3198
STDES-DABBIDIR hardware implementation
5
STDES-DABBIDIR hardware implementation
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5 5.1.6 5.1.7
5.2
5.2.1
Input/output requirements
Maximum input power
The maximum input power related to high voltage is obtained according to maximum output (low-voltage side) and worst-case efficiency considered.
Pin_max
=
Pout_max w
=
28kW 95%
=
29,4kW
(12)
Maximum DC input current
The maximum DC input current with the variation of the Vin value is now considered. When Vin is minimal, the maximum DC input current is obtained.
Iin_max
=
Pin Vin_min
=
29,4kW 720V
=
40.93A
(13)
Nominal DC input current
The maximum DC input current with the variation of the Vin value is now considered. When Vin is minimal, the maximum DC input current is obtained.
Iin
=
Pin Vin_nom
=
29,4kW 800
=
36.84A
(14)
Minimum DC input current
The mean input current changes with the variation of the Vin value. When Vin is minimal, the maximum average current is obtained.
Iin
=
Pin Vin_max
=
29,4kW 880
=
33,49A
(15)
Maximum DC output current
The maximum DC output current is obtained from the typical output voltage at maximum output power.
Iout
=
Pmax Vout_nom
=
28000 450
=
62.22A
(16)
Minimum DC output current
The minimum DC output current is obtained from the maximum output voltage at maximum output power.
Iout
=
Pout_max Vout_max
=
28000 500
=
56A
(17)
Nominal DC output current
The nominal DC output current is obtained for the typical output voltage at nominal output power.
Iout
=
Pout Vout_nom
=
25000 450
=
55.55A
(18)
Sensing circuitry
HV voltage sensing
The high-voltage-side voltage is obtained using a two-stage sensor circuit isolated architecture. The first stage represents an isolated op amp that allows measurement of the HV through a voltage divider with an isolation barrier.
Isol-Op-AMP output is limited in volts and is scaled with a second stage of op amps with appropriate gain and bias.
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UM3198
STDES-DABBIDIR hardware implementation
Figure 18. HV voltage sensing equivalent circuit.
Figure 19. STDES-DABBIDIR HV sensing circuit
To define the maximum high-voltage-side measurement, the maximum voltage range is considered.
Parameters Vin_nom Vin_min Vin_max
Table 2. HV-side input voltages
Value 800 V 720 V 880 V
Description Nominal input Voltage
Min. input voltage Max. input voltage
High voltage maximum voltage range is considered with +20% margin.
VSDeCn1seMax = VMDCa1x + 20%VMDCa1x = 880*1.2 = 1056 1050V
The maximum voltage of the isolated op amp must be guaranteed at HV max sense voltage.
VMisoalxOA = 2V
From this, voltage divider transfer function is obtained.
kdDiCv1
=
VMisoalxOA VMDCa1x
=
2 1050
=
1.905e-3
The resistor values of voltage divider are now calculated.
RB = 22k
RA
=
1
- kdDiCv1 kdDiCv1
RB
=
11.53M
3x3.90k
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Note: 5.2.2
UM3198
STDES-DABBIDIR hardware implementation
Isolated op amp unity and voltage gain must be followed by proper signal conditioning to fulfill ADC range requirements.
Parameters Vout_max Vin_max
Table 3. HV sensing input and output voltage range
Value
Description
3.3 V Maximum value of the voltage range of the microcontroller ADC
2 V Op amp maximum input voltage | maximum output voltage of ISO op amp
According to these input and output values, the voltage gain of signal conditioning is defined.
K
=
Vout_max Vin_max
=
3.3V 2V
=
1.65
The differential amplifier configuration is designed according to the voltage gain requirement.
Parameters VHV_range VADC_range GTv_HVDC
GADC_Bits BTv_HVDC BADC_Bits GTv_HVDC_tot BTv_HVDC_tot invGTv_HVDC_tot
Table 4. STDES-DABBIDIR effective value of HV sensing
Value
0V - 1050V
0V - 3.3V
3.13e-3
V V
1240
Bits V
0V
0Bits
3.881
Bits V
0Bits
0.2576
V Bits
Description HV voltage range ADC signal range keq conditioning circuit gain ADC peripheral digital gain factor with 12-bit precision and VDDA=3.3V Bias term of conditioning circuit gain Offset term of ADC peripheral Overall conditioning circuit gain Overall offset term Reciprocal overall conditioning circuit gain
LV voltage sensing
The low-voltage-side voltage is obtained using a two-stage sensor circuit isolated architecture. The first stage represents an isolated op amp that allows measurement of the HV through a voltage divider with an isolation barrier.
Isol-Op-AMP output is limited in volts and is scaled with a second stage of op amps with appropriate gain and bias.
Figure 20. LV sensing equivalent circuit
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UM3198
STDES-DABBIDIR hardware implementation
Figure 21. STDES-DABBIDIR LV sensing circuit
Note:
To define the maximum high voltage side measurement, the maximum voltage range is considered.
Parameters Vout_nom Vout_min Vout_max
Table 5. HV-side output voltages
Value 450 V 250 V 500 V
Description Nominal output Voltage
Min. output voltage Max. output voltage
The high voltage maximum voltage range is considered with +20% margin. VSDeCnLsVeMax = VMDCaLxV + 30%VMDCaLxV = 500*1.3 = 650 660V
The isolated op amp maximum voltage must be guaranteed at LV max sense voltage. VMAMaxC1311 = 2V
From this voltage, the divider transfer function is derived.
kdDiCvLV
=
VMAMaxC1311 VMDCaLxV
=
2 660
=
3.03e-3
The resistor values of the voltage divider are calculated.
RB = 33k
RA
=
1
- kdDiCv1 kdDiCv1
RB
=
10.86M
3x3.60k
Isolated op amp unity and voltage gain must be followed by proper signal conditioning to fulfill ADC range requirements.
Parameters Vout_max Vin_max
Table 6. LV sensing input and output voltage range
Value
Description
3.3 V Maximum value of the voltage range of the microcontroller ADC
2 V Op amp maximum input voltage | maximum output voltage of ISO op amp
From the input and output values, the voltage gain for signal conditioning is defined.
K
=
Vout_max Vin_max
=
3.3V 2V
=
1.65
The differential amplifier configuration is designed according to the voltage gain requirement.
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5.2.3
UM3198
STDES-DABBIDIR hardware implementation
Parameters VLV_range VADC_range GTv_LVDC
GADC_Bits BTv_LVDC BADC_Bits GTv_LVDC_tot BTv_LVDC_tot invGTv_LVDC_tot
Table 7. STDES-DABBIDIR effective value of LV sensing
Value
0V - 660V
0V - 3.3V
5.07e-3
V V
1240
Bits V
0V
0Bits
6.296
Bits V
0Bits
0.1688
V Bits
Description LV voltage range ADC signal range keq conditioning circuit gain ADC peripheral digital gain factor with 12-bit precision and VDDA=3.3V Bias term of conditioning circuit gain Offset term of ADC peripheral Overall conditioning circuit gain Overall offset term Reciprocal overall conditioning circuit gain
HV current sensing HV-side current measurement is obtained through an isolated Hall effect current transducer. The equivalent circuit is shown below.
Figure 22. HV current sensing equivalent circuit
Figure 23. STDES-DABBIDIR HV current sensing circuit
To define the maximum high-voltage-side current measurement range, the maximum current range is considered.
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UM3198
STDES-DABBIDIR hardware implementation
Parameters Iin_max
Value ±40.93A
Table 8. HV-side current Description
Max. input current at Vin_min = 720V and Pin_max = ± 29,4kW
The HV-side maximum voltage range is considered with +15% margin. ISDeCnHsVeMax = IMDCaHxV + 15%VMDCaIxV = ± 40.93A*1.15 = ± 47.07 ± 48A
We check this against the sensor limitation. IPCAMSR15NP > ISDeCnHsVeMax ± 51A > ± 48A PASSED
The internal voltage reference of the Hall effect sensor is used. According to this, the sensor output voltage is shifted by Vref=2.5V.
The equivalent transfer function is given.
BIASHall = 2.5V
GAINHall
=
0.625 IPNCASR15NP
=
0.625 15
=
41.66e-3
V A
VLHEVMout = BIASHall + GAINHallISDeCnHsVeMax =
41.66e-
3
V A
± 48A
+ 2.5V =
4.5V 0.5V
To adapt sensor the output voltage to the ADC range, op amp conditioning is required.
Parameter IHV_range VLHEVMout_range VOA_out_range
Table 9. Parameters for HV-side op amp conditioning
Value ±48A
Description HV-side current measurement range required
0.5Vto4.5V Op amp input voltage range/output voltage range of hall sensor
0-3.3 V
Maximum value of the voltage range of the microcontroller ADC
According to the input output specs, voltage gain and offset of signal conditioning is defined.
Vout =
R4 R2 + R4
1
+
R3 R1
Vin
-
R3 R1
Vbias
Finally, the transfer function is obtained.
GAINopamp =
R4 R2 + R4
1
+
R3 R1
=
10k 4.12k + 10k
1
+
1.65k 10k
=
0.8251
V V
GAINeq
=
GAINopamp
GAINHall
=
0.8251
V V
41.66e-3
V A
=
0.03437
V A
BIASopamp =
-
R3 R1
Vbias
=
- 0.165 2.5V =
- 0.4125V
BIASeq = BIASHall GAINopamp + BIASopamp = 2.5V 0.8251 - 0.4125V = 1.65V
VODACHouVt = ISDeCnHsVe GAINeq + BIASeq
VBits
=
K12bits
VADC
=
212 - 1 3.3
VADC
=
1240
VADC
GTi_HVDC_tot
=
GAINeq
K12bits
=
42.65
Bits A
The digital transducer transfer function becomes: VODACHouVt = ISDeCnHsVe GAINeq + BIASeq
Sensing specifications are collected.
Parameters IHV_range VADC_range
Table 10. Theoretical overall parameters of HV current sensing
Value ±48A 0V - 3.3V
Description LV Voltage range ADC signal range
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5.2.4
UM3198
STDES-DABBIDIR hardware implementation
Parameters GTi_HVDC
GADC_Bits BTi_HVDC BADC_Bits GTi_HVDC_tot BTi_HVDC_tot invGTi_HVDC_tot
Value
0.03437
V A
1240
Bits V
1.65V
2047Bits
42.65
Bits A
2047Bits
0.0234
A Bits
Description keq conditioning circuit gain ADC peripheral digital gain factor with 12-bit precision and VDDA=3.3V Bias term of conditioning circuit gain Offset term of ADC peripheral Overall conditioning circuit gain
Overall offset term Reciprocal overall conditioning circuit gain
The design overview is also included.
R1 = 10k0.1% R2 = 4.12k0.1% R3 = 1.65k0.1% R4 = 10k0.1%
AINopamp =
R4 R2 + R4
1
+
R3 R1
=
0.8251
V V
Geq
=
Gopamp
GHall
=
0.8251
V V
41.66e-3
V A
=
0.03437
V A
7
GTv
=
GAINeq
K12bits
=
42.65
Bits A
LV current sensing LV-side current measurement is obtained through an isolated Hall effect current transducer. The equivalent circuit is shown below.
Figure 24. LV Current sensing equivalent circuit
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UM3198
STDES-DABBIDIR hardware implementation
Figure 25. STDES-DABBIDIR LV current sensing circuit
To define the maximum low-voltage-side current measurement range, the maximum current range is considered.
Parameters Iout_max
Value ±62.22A
Table 11. LV-side current Description
Max. LV-side current at Vin_min = 450V and Pin_max = ± 28kW
The low voltage maximum current range is considered with +30% margin. ISDeCnLsVeMax = IMDCaLxV + 15%VMDCaLxV = ± 62.22A*1.3 = ± 80.88 ± 82A
This value is checked against the sensor limitation. IPCMASR50NP > ISDeCnHsVeMax
± 150A > ± 82A
The internal voltage reference of Hall effect sensor is used. According to this, the sensor output voltage is shifted by Vref=2.5V.
The equivalent transfer function is given.
BIASHall = 2.5V
GAINHall
=
0.625 IPNCASR15NP
=
0.625 50
=
12.5e-3
V A
VLLEVMout = BIASHall + GAINHallISDeCnLsVeMax =
12.5e-3
V A
± 82A
+ 2.5V =
3.525V 1.475V
To adapt the sensor output voltage to ADC range, op amp conditioning is required.
Parameter IHV_range VLHEVMout_range VOA_out_range
Table 12. Parameters for LV-side op amp conditioning
Value ±82A
Description HV side Current measurement range required
1.475Vto3.525V
Op amp input voltage range/output voltage range of hall sensor
0-3.3 V
Maximum value of the voltage range of the microcontroller ADC
According to the input and output values, the voltage gain and offset for signal conditioning are defined.
Vout =
R4 R2 + R4
1
+
R3 R1
Vin
-
R3 R1
Vbias
The differential amplifier configuration is designed according to the voltage gain and bias requirements.
By setting R1 , it is possible to calculate R2, R3 and R4 with the following relationships:
R1 = 13.7k
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R2 = 4.22k
R3 = R1 Y = 13.7k 0.9498 = 13.01k
R4 = R2
X 1-X
= 19.98k
Finally, the transfer function is obtained
GAINopamp =
R4 R2 + R4
1
+
R3 R1
=
19.98k 4.22k + 19.98k
1
+
13.01k 13.7k
=
1.6096
V V
GAINeq
=
GAINopamp
GAINHall
=
1.6096
V V
12.5e-3
V A
=
0.02012
V A
BIASopamp =
-
R3 R1
Vbias
=
- 0.9498 2.5V = 2.3745V
BIASeq = BIASHall GAINopamp + BIASopamp = 2.5V 1.6096 - 2.3745V = 1.6495V
VODACHouVt = ISDeCnHsVe GAINeq + BIASeq
We now take digital conversion into account.
VBits
=
K12bits
VADC
=
212 - 1 3.3
VADC
=
1240
VADC
GTv_LVDC_tot
=
GAINeq
K12bits
=
24.9488
Bits A
The digital transducer transfer function becomes. VODACHouVt = ISDeCnHsVe GAINeq + BIASeq
The sensing specifications are collected.
Parameters ILV_range VADC_range GTi_LVDC
GADC_Bits BTi_LVDC BADC_Bits GTi_LVDC_tot BTi_LVDC_tot invGTi_LVDC_tot
Table 13. Theoretical overall parameters of HV current sensing
Value
±82A
0V - 3.3V
0.02012
V A
1240
Bits V
1.65V
2047Bits
24.9488
Bits A
2047Bits
0.0401
A Bits
Description LV voltage range ADC signal range keq conditioning circuit gain ADC peripheral digital gain factor with 12-bit precision and VDDA=3.3V Bias term of conditioning circuit gain Offset term of ADC peripheral Overall conditioning circuit gain Overall offset term Reciprocal overall conditioning circuit gain
Magnetics design requirements
From the power converter specifications, the magnetic parameters are calculated.
Parameters Vin_nom Vout_nom Pout_nom Pout_max fsw
Table 14. Parameters for magnetic design
Value 800 450 25 28 100
Dimension V V kW kW
kHz
Description Nominal HV-side input voltage Nominal LV-side output voltage
Nominal power Maximum power Switching frequency
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5.3.1 5.3.2
5.3.3
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STDES-DABBIDIR hardware implementation
Transformer turn ratio
In order to optimize the operation of the high frequency transformer, transformer ratio is obtained from the primary and secondary nominal voltages.
n
=
N1 N2
=
Vin_nom Vout_nom
=
800 450
=
1.78
(19)
Total resonance inductance
To design DAB resonance inductance, nominal power is considered. According to the DAB theoretical aspects section, to manage full power operation, a single phase shift modulation technique is now considered. Ignoring the detrimental effects of efficiency parameters, the power flow equation is proposed.
P
=
P1
=
P2
=
N*Vin_nom*Vout_nom** 2*2*Fsw*LK
-
(20)
To
obtain
the
max
power
transfer
P
=
0
is
imposed,
then
=
2
allow
to
manage
maximum
power.
Pmax
=
N*Vin_nom*Vout_nom 8*Fsw*LK
(21)
Then:
LK
=
n*Vin_nom*Vout_nom 8*Fsw*Pmax
=
1,78*800*450 8*100k*28k
=
28,6uF
The max leakage inductor current ( = /2 ) is:
(22)
ILkmax
=
*
n*Vout_nom - Vin_nom - 2**n*Vout_nom 4**Fsw*Lk
=
= *
1.78*450
- 800
-
2*
2
*1.78*450
4**100000*28.61*10-6
= 69.90A
(23)
The max input current is:
Iprim_max = ILkmax
(24)
The MAX output current is:
Isec_max = n*Iprim_max = 124.43A
(25)
Transformer peak magnetic field estimation To define the magnetic structure and core loss estimations, the magnetic field amplitude must be calculated.
Parameters NP Ae
Ncore Ae, tot
fsw
Table 15. Parameters for transformer peak magnetic field estimation
Value 800 392
Dimension V
mm2
Description Nominal LV-side output voltage Effective area of single ferrite
5 1960(1960e-6)
100
mm2 m2
kHz
Number of stacked core elements Total effective area of ferrite block
Switching frequency
Bmax
=
1 NPAe
nVout
1/2 fsw
=
=
1 9*1960*10-6
*1.79*450
1/2 100*103
=
228mT
Bmax
=
228mT 2
=
114mT
(26) (27)
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5.3.6
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STDES-DABBIDIR hardware implementation
Auxiliary inductance - peak magnetic field estimation
Bmax =
1 NLAe
Vlk
1/2 fsw
=
1 7*1960*10-6
*800
1/2 100*103
=
= 72.88*
350*5*10-6 = 2*92.9mT
1250*5*10-6 +
(28)
Transformer Magnetizing inductance
The magnetizing inductance of HFT does not participate in the active power transfer, so it is designed with a
magnetizing current <2% of the rated current.
Im
2%Iin
=
2%
Pin Vin_nom
=
2%
29kW 800V
=
2%36.84
A
Im 0.7A
We now consider the inductance current.
Impp
=
1 Lm
Tsw
0 2
Vindt
=
Vin Lm
Tsw
0 2
dt
=
Vin Lm
Tsw 2
=
Vin 2fswLm
Impp
=
Vin 2fswLm
2Im
=
Vin 2fswLm
Im
=
Vin 4fswLm
The actual magnetizing inductance can now be calculated.
Lm
Vin 4fswIm
=
800 4100kHz0.73A
Lm 2.739mH
Magnetics section design proposal According to the design requirements, the actual design details are shown below.
Figure 26. Frenetic 32011-04-Design-Report (design requirements section)
Considering the specifications, Frenetic has a design based on 5 stacked cores of E80/38/20.
To maximize the performance of the converter, a sandwich interleaving arrangement is selected as the best solution to reduce AC proximity losses and to improve the coupling between the windings of the transformer.
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Figure 27. Frenetic 32011-04 Transformer winding
Figure 28. Frenetic 32011-04 Auxiliary inductor windings
The following figure provides a 3D view. Figure 29. 3D image of transformer
Unique magnetic core elements were considered to reduce the volume and weight.
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Figure 30. 3D model of transformer
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STDES-DABBIDIR hardware implementation
Figure 31. 3D model of auxiliary inductor
5.4
5.4.1
Power section
Power device current stress The conduction losses are calculated using the rms switch currents IQ1rms and IQ5rms for the HV-side switches, PScHoVnd , and the LV-side switches, PScLoVnd , respectively. As every switch conducts current during half of the cycle time Tsw = 1/fsw in steady state operation, the rms switch currents are easily obtained from the rms inductor current ILkrms
Figure 32. Switch RMS current equivalent circuit
5.4.2
According to the selected modulation techniques, each half bridge operates at 50% duty cycle, so the rms currents are equal.
Hp . LegDuty50% IQ1rms = IQ2rms
By LKC, the relation between inductor and switch currents can be identified. ILkrms = IQ1rms2 + IQ2rms2 = 2IQrms2 = 2IQrms
ILkrms = 2IQrms
By LKC, the relation between inductor and switch currents can be identified.
IQ1rms = IQ3rms =
ILkrms 2
IQ5rms = IQ7rms =
ILkrms/n 2
IQ2rms = IQ4rms =
ILkrms 2
IQ6rms = IQ8rms =
ILkrms/n 2
Power switches conduction losses High-voltage-side conduction losses are obtained from each contribution.
PScHoVnd = 4*RDS on *IQ1rms2 Secondary low-voltage estimation is also obtained.
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5.4.3
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STDES-DABBIDIR hardware implementation
PScLoVnd = 4*RDS on *IQ5rms2 The total switches conduction losses are obtained.
PScToOnTd = PScHoVnd + PScLoVnd
Power switch switching losses The calculation of the switching losses is more demanding as they do not only depend on the selected power MOSFETs themselves. Surrounding parasitic components like PCB stray inductances may also influence the switching losses considerably. Only power switching power losses are considered here. Very low switching losses are obtained when ZVS/ZCS is achieved. In contrast, hard switching operation leads to excessive semiconductor losses and must be avoided when using advanced modulation methods or additional circuitry.
PSWHV = 4fswEOn, QHV I, V + 4fswEOff, QHV I, V PSWLV = 4fswEOn, QLV I, V + 4fswEOff, QHV I, V The total switches switching losses are obtained.
PSTWOT = PSWHV + PSWLV
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STDES-DABBIDIR control implementation
6
STDES-DABBIDIR control implementation
A typical EV charger control platform consists of two different control implementations to fulfill battery charging requirements: current control is used during the first part of charging profile, and voltage control is typically required to complete the charging profile. Both control solutions are therefore proposed for the STDES-DABBIDIR reference design control implementation.
An easy and robust proportional integrator (PI) regulator is considered to follow the reference value. Comparing references and feedback for voltages and currents, control variables are obtained to address the requirements.
According to the theoretical description of the DAB converter model, the actual control terms are represented by the phase shift, so phase shifting is obtained from each control block to manage the modulator blocks adopted to configure the high-resolution timer of the STM32G474 according to the phase shifting demand. In addition, "DAB Supervisor" blocks are proposed to manage other features such as protections, monitoring, and modulations techniques.
Figure 33. Control block diagram
6.1
Software implementation
The STDES-DABBIDIR is controlled by the STM32G474RE MCU. The firmware package is based on the STM32Cube ecosystem shown in Figure 34.
Starting from STM32CUBEMX all used peripherals and pins are activated and configured according to the basic project. The application firmware is supported and tested using STM32CubeIDE IAR and KEIL development environment.
After the development, the MCU can be programmer with IDE or with STM32CubeProgrammer. To monitor and control the application, a GUI based on STM32CubeMonitor can be used.
The firmware described in this documentation development is based on STM32CubeG4 Firmware Package V1.4.0.
Figure 34. CUBE ecosystem development flow
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STDES-DABBIDIR control implementation
An extensive range of generic and specific firmware modules are available to support digital power conversion. Figure 35 shows the general development flow to obtain power conversion used for STDES-PFCBIDIR firmware development. This workflow allows us to start from power conversion requirements. This information is reinterpreted in application specifications that contain information linked to the MCU peripheral and DPC application configuration. According to the previous information, a CubeMX project with appropriate "config" and "init" are provided. Then the required DPC module is included and configured. CubeMX generated the IDE project for development. The MCU is flashed directly with IDE or using STM32CubeProgrammer. Finally, the DPC application is tested and debugged with appropriate instrumentation and STM32CubeMonitor. Digital Power converter firmware is released if compliant, and DPC is adapted.
Figure 35. DPC development flow
6.2
Peripheral configuration STM32CubeMX
STM32CubeMX is a graphical tool that is used to configure STM32 microcontrollers and to generate the corresponding initialization C code for the chosen development tools. The overall pinout configuration of the STM32G474RE is shown. The STM32CubeMX configuration tool simplifies pin association and functionality to avoid any peripheral conflicts.
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Figure 36. STM32G474 MCU pinout configuration for STDES-DABBIDIR
6.2.1
High-resolution timer
A brief representation of the high-resolution timer configuration is shown below. Accurate parameter configuration is visible in the STM32CubeMX project files.
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Figure 37. Generic phase shift - HRTIM block diagram
Figure 38. HRTIM pin assignment
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An example of the switching pattern managed according to HRTIM peripheral of the STM32G474 is shown below, with primary and secondary legs of the DAB topology synchronized to the phase shifting requirements of the Master Timer Compare Unit. Dead time insertion and nominal 50% duty cycle of each leg is also managed through hardware configuration of the A-B-C-D channels of the HRTIM.
Figure 39. HRTIM modulation pattern
6.2.2
ADC configuration and triggering Additional details about the peripheral are also proposed for the ADC.
Figure 40. ADC clock scheme
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6.2.2.1
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STDES-DABBIDIR control implementation
ADC timing - actual configuration We use STM32CubeMX to select the clock sources for the ADC peripherals.
Figure 41. ADC clock source selection (STM32CubeMX)
fsysclk = 170MHz
fclk
=
fsysclk AHBpsc
=
170MHz 1
=
170MHz
(29)
ADC 1 and ADC2 are requested for this application. Both are configured as shown below.
Figure 42. CubeMX ADC Settings
Clock Prescaler Configuration related to CKMODE[1:0] and PRESC[3:0]
Table 16. Clock Prescaler settings
Register PRESC[3:0] CKMODE[1:0]: ADC clock mode
Value 0010 (input ADC clock divided by 4) 11: adc_hclk/4 (Synchronous clock mode)
fadcclk
=
fclk PRESC 3: 0
=
170MHz 4
=
42.5MHz
Tadcclk
=
1 fadcclk
=
1 42.5MHz
=
23,529nSec
(30)
Resolution
RES[1:0]= 12 -> 12.5 ADC clock cycles is considered for each channel and the ADC peripherals.
Tsar
=
RESclkcycleTadc_clk
=
12.5
1 42.5MHz
=
294,1nSec
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6.2.2.2
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STDES-DABBIDIR control implementation
Trigger and sampling Considering the "clean" area available in single phase shift modulation (SPS), the total conversion time must be lower than a quarter of the switching period.
Figure 43. SPS ADC sampling requirement
tadctrigger
>
1
fPWM 4
7,5uSec
(31)
tadcclean
<
1 fPWM 4
=
2,5uSec
(32)
According to the PWM frequency and modulation technique, a specific trigger time is selected.
Figure 44. STM32CubeMX ADC1 Regular conversion configuration
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STDES-DABBIDIR control implementation
Figure 45. STM32CubeMX ADC2 regular conversion configuration
Figure 46. HRTIM ADC trigger CubeMX configuration
Figure 47. HRTIM compare unit enabled for ADC triggering
To guarantee the proposed tadctrigger timed conversion request, an external trigger conversion is configured.
ADC
N° of conversion
ADC1
1
ADC2
5
Table 17. ADC and timer configuration
ADC Configuration
Regular Conversion
Regular Oversampling
Enable
Disable
Enable
Disable
Ext Trig. Source
HRTIM Trigger1
event
HRTIM Trigger1
event
Ext Trig. Edge
Rising
HRTIM Configuration
Update Trigger Source
Trigger Source Selection
Trigger Source
Master Timer
1
Master Compare 4
Rising
Master Timer
1
Master Compare 4
The converter signals are connected to the ADCs according to the following table.
Phase VDAB1 IDAB1 VDAB2 IDAB2
Ilk
PORT PC1 PC4 PC0 PA7 PC2
Table 18. Converter signal connections
ADC ADC2 ADC2 ADC2 ADC2 ADC1
CH CH7 CH5 CH6 CH4 CH8
DMA DMA1CH4 DMA1CH4 DMA1CH4 DMA1CH4 DMA1CH3
RANK 4 2 3 1 1
FUNCTION ADC2 IN7 ADC2 IN4 ADC2 IN6 ADC2 IN4 ADC1 IN8
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6.2.3
UM3198
STDES-DABBIDIR control implementation
Phase TEMP Temp-INT
PORT PB2 INT
ADC ADC2 ADC1
CH CH12 TEMP
DMA DMA1CH4 DMA1CH3
RANK 5 8
FUNCTION ADC2 IN12 ADC1-TEMP
Configuration files
STDES-DABBIDIR power converter configuration is based on two main configuration files, shown in the figure below:
·
"DPC_application_conf.h" contains the application-specific DEFINE (i.e., ADC gain factor PI regulator gain,
FSM configuration, control reference value, etc.
·
"DPC_Lib_conf.h" contains the configuration parameters associated with MCU peripheral configuration
Figure 48. STDES-DABBIDIR configuration file
After the "MX" initialization function, the DPC initialization function are called to configure each specific application struct, as shown in the figure below.
Figure 49. Application Init functions
6.2.4
Finite state machine
The STDES-DABBIDIR control supervisor is developed by a passthrough implementation of the finite state machine with event and status shown in the following figure.
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UM3198
STDES-DABBIDIR control implementation Figure 50. Finite state machine bubble representation
The FSM firmware modules provide a specific "weak" function for any state. The weak function provides a simple change of state to the following state. If any state is not used, the FSM main function allows a bypass to move forward automatically (Figure 51). The STDES-DABBIDIR provides a typical FSM execution to obtain a typical startup procedure of the converter. The nominal operation is managed with the FSM and the ERROR and FAULT states are supported.
Figure 51. STDES-DABBIDIR FSM application service execution
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How to manage the STDES-DABBIDIR reference design
7
How to manage the STDES-DABBIDIR reference design
This section describes how to configure and evaluate the power platform. Preliminary information regarding the typical test bench and testing procedures are provided in the following sections.
7.1
System setup requirement
To perform functions of the STDES-DABBIDIR, the following equipment is needed:
·
Programmable DC source
·
DC electronic load
·
Power analyzer
·
Digital oscilloscope
In addition to the hardware equipment, additional software tools are suggested to fully evaluate the reference environment.
A fully integrated design environment like STM32CUBEIDE allows evaluation and management of software source code and STM32G474 peripheral configuration. In addition, thanks to STM32CubeMX, support for other IDEs such as EWARM and AMR Keil is available as well.
Tools STM32CubeMX STM32CubeIDE
IAR EWARM Arm Keil
Table 19. Software compatibility Version
v.6.6 or above v.1.8 or above v.9.20.2 or above v5.36 or above
7.2
Important:
Safety precautions and protective equipment
The STDES-DABBIDIR evaluation board is designed for demonstration purposes only and is not intended for domestic or industrial installations.
Danger:
The high voltage levels used to operate the STDES-DABBIDIR evaluation board may provoke a serious electrical shock. This evaluation board must be used in a suitable laboratory by qualified personnel only, familiar with the installation, use, and maintenance of power electrical systems. During operation, do not touch the board as some of its components could reach very high temperatures.
7.3
How to use the STDES-DABBIDIR
STDES-DABBIDIR is a high-power, high-voltage application and an appropriate testbench is required for safety operation.
A typical configuration of test bench is proposed here.
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Figure 52. Power equipment connection example
7.4
How to connect the STDES-DABBIDIR
Before testing the reference design, the following actions and checks must be considered.
Step 1. Connect or verify the proper connection of HF transformer as described into the specific section.
Step 2. Insert or verify the STDES-DABBIDIRDF into the driving board connectors located into left side.
Step 3. Insert or verify the two STDES-DABBIDIRDH into the driving board connectors located into right side.
Step 4. Insert or verify the STDES-PFCBIDIR into the control board connector located on the bottom-right side.
Step 5. Connect 12V external power supply into the "12V" connector located in the bottom-left corner.
Step 6. Connect 7V external power supply into the "7V" connector located in the bottom-left corner.
Step 7. Connect the Programmable DC power supply in the top-left corner connectors. Polarity must be checked according to the image description.
Step 8. Connect the Programmable DC e-Load in the top-right corner connectors. Polarity must be checked according to the image description.
The control card based on STM32G474 MCU is directly powered by the main board. The required MCU 3.3V is provided by internal LDO.
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How to manage the STDES-DABBIDIR reference design
Figure 53. Connecting the STDES-DABBIDIR
7.5
How to set up the STDES-DABBIDIR
The MCU could be programmed, monitored, and debugged using different SW/HW tools. ST-Link V2/isol and a typical 20 to10-pin JTAG adapter is used to connect the platform with a PC.
The following procedure shows how to flash and debug the reference platform from a generic configuration; referr to dedicated sections to configure the actual configuration for specific tests.
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Figure 54. ST-LINK/V2 ISOL + adapter
UM3198
How to manage the STDES-DABBIDIR reference design
Figure 55. ST-LINK/V2 ISOL connection
Step 1. Step 2. Step 3. Step 4. Step 5. Step 6.
Step 7. Step 8.
Install and configure the preferred IDEs Apply 7V and 12V external supply voltage Connect STlink hardware debugger Open project according to IDE selection The "main.c" file is in project/Application/User path. "Download and debug" button performs programming procedure and start-up the debugging connection. "Run button" to start the code execution.
Figure 56. IAR EWARM program procedure
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How to manage the STDES-DABBIDIR reference design
Figure 57. IAR EWARM debug procedure
Example 1 :
Several parameters can be adapted in order to evaluate and customize the application operating condition. The main parameters are depicted in the next table showing the default configuration proposed in the source code firmware example.
Some examples are proposed in this chapter, and specific configuration of these parameters are proposed to emulate the same behavior described for each.
Table 20. Control section firmware configuration defines
Parameters
Value type
Min
Default
Max Unit
Comments
DPC_CTRL_INIT
DAB_OPEN_LOOP DAB_CURRENT_LOOP -
DAB_OPEN_LOOP
- enum
DAB_VOLTAGE_LOOP
DPC_PWM_INIT
PWM_Armed 400
PWM_Safe
enum
StartUpCheck_INIT
StartUpCheck_Disabled StartUpCheck_Enabled
StartUpCheck_Disabled
enum Startup management
DPC_INRS_EN
SET RESET
RESET
DPC_BURST_EN
SET RESET
RESET
DPC_DAB_VDC_OUT
float
0
50
880 V Target DC output voltage
DPC_DAB_IDC_OUT
float
0
1
60 A Target DC output current
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7.6
7.6.1
UM3198
How to manage the STDES-DABBIDIR reference design
In addition to the operating mode parameters, a dedicated parameter section is proposed for the protection feature configuration. The default configuration is also given.
Table 21. Hardware protection firmware configuration defines
Parameters DPC_VDCHV_OVP DPC_VDCHV_UV DPC_VDCHV_UVLO DPC_VDCHV_MIN DPC_IDCHV_OCP DPC_IDCLV_OCP DPC_VDCLV_OVP
Value type float float float float float float float
Min
Default
Max
Unit
-
900
-
V
-
40
-
V
-
30
-
V
-
20
-
V
-
50
-
A
-
550
-
A
-
100
-
V
The STSW-DABBIDIR source code firmware package represents the control section of STDES-DABBIDIR. By using hardware section configuration of the FW, different hardware configuration proposed by the CTMs can also be supported. The main parameters such as switching frequency, dead time, sensing parameters, and magnetics section can be customized.
Table 22. Hardware parameters firmware configuration defines
Parameters
Value type Min Default Max Unit
TRAFO_TURN_RATIO
float
-
1.78
- N1/N2
INDUCTANCE
float
- 28e-6 -
PWM_FREQ
Uint16_t - 100000 -
DPC_DT_DAB1
float
- 0.4e-6 -
DPC_DT_DAB2
float
- 0.4e-6 -
G_VDC1
float
- 3.901 -
B_VDC1
float
-
0
-
G_IDC1
float
- 42.67 -
B_IDC1
float
- 2048 -
G_VDC2
float
- 6.296 -
B_VDC2
float
-
0
-
G_IDC2
float
- 24.948 -
B_IDC2
float
- 2048 -
Comments Transformer turn ratio Auxiliary inductance Switching Frequency of converter expressed in [Hz] Dead Time [Expressed in sec] Dead Time [Expressed in sec] Gain terms of the DC input voltage sensing Bias terms of the DC input voltage sensing Gain terms of the DC input current sensing Bias terms of the DC input current sensing Gain terms of the DC output voltage sensing Bias terms of the DC output voltage sensing Gain terms of the DC output current sensing Bias terms of the DC output current sensing
How to operate the STDES-DABBIDIR
This section provides examples of operating modes. Several setups are proposed to help evaluate and become familiar with the various features of the reference design.
Mode 1 open loop, driving check
This test is for the driving section of the application. PWM signals are generated by HRTIM according to the STM32CubeMX peripheral configuration. Dead time and switching frequency are managed by "PWM_FREQ", "DPC_DT_DAB1" and "DPC_DT_DAB2" of "DPC_Appplication_Conf.h" file. No high-power equipment is required during this test. MCU and gate driver section phase shift between primary and secondary can be verified during this test.
UM3198 - Rev 1
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UM3198
How to manage the STDES-DABBIDIR reference design
Figure 58. Mode 1 test configuration
An example of the default configuration is given. Swathing frequency and dead time are configured in "DPC_Application_Conf.h" and the expected waveforms are provided.
Step 1. Configure the firmware parameters and flash the MCU.
Table 23. Mode 1 test parameters
Parameters DPC_CTRL_INIT DPC_PWM_INIT StartUpCheck_INIT DPC_INRS_EN DPC_BURST_EN PhSh_CTRL_MAN_norm
Location DPC_Application_Conf.h DPC_Application_Conf.h DPC_Application_Conf.h DPC_Application_Conf.h DPC_Application_Conf.h DAB. pDAB_CTRL.PhSh_CTRL_MAN_norm
Value DAB_OPEN_LOOP
PWM_Armed StartUpCheck_Disabled
RESET RESET
0.25
Step 2. Go to the debugging mode in the preferred IDE software.
Step 3. If emergency shoot down is required, DPC_FSM_NEW_State can be set to "DPC_FSM_FAULT" to disable PWM as well as phase shifting and energy transfer.
Example 1 :
UM3198 - Rev 1
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UM3198
How to manage the STDES-DABBIDIR reference design
Table 24. Example of frequency and dead time configuration
Parameters PWM_FREQ DPC_DT_DAB1 DPC_DT_DAB2
Location DPC_Application_Conf.h DPC_Application_Conf.h DPC_Application_Conf.h
Value 100000 0.4e-6 0.4e-6
Figure 59. Typical PWM and driving voltages
7.6.2
Mode 2 open loop, phase shift power operation.
This test is for the power and sensing section of the application. Power equipment (programmable DC power supply and DC eDLoad) is required for this test. DPI and protection shields are mandatory to prevent injury. Power analyzer can be connected during this test to evaluate efficiency in specific operating points. The PWM signals are generated by HRTIM according to the STM32CubeMX peripheral configuration. Dead time and switching frequency are managed by "PWM_FREQ", "DPC_DT_DAB1" and "DPC_DT_DAB2" of "DPC_Appplication_Conf.h" file. MCU and gate driver sections phase shift between primary and secondary can be verified during this test.
Step 1. Configure firmware parameters and flash the MCU.
Table 25. Mode 2 test parameters
Parametrs DPC_CTRL_INIT DPC_PWM_INIT StartUpCheck_INIT DPC_INRS_EN DPC_BURST_EN PhSh_CTRL_MAN_norm
Location DPC_Application_Conf.h DPC_Application_Conf.h DPC_Application_Conf.h DPC_Application_Conf.h DPC_Application_Conf.h DAB. pDAB_CTRL.PhSh_CTRL_MAN_norm
Value DAB_OPEN_LOOP
PWM_Armed StartUpCheck_Disabled
RESET RESET Variable during this test
Step 2. Select and enable Constant Current mode "CC" in the High Power eLoad. Step 3. Set current reference to 9A.
UM3198 - Rev 1
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UM3198
How to manage the STDES-DABBIDIR reference design
Step 4. Go to the debugging mode in the preferred IDE software. Step 5. Set to 0.06 in DAB. pDAB_CTRL.PhSh_CTRL_MAN_norm. Step 6. Slowly increase the DC power supply up to 400V.
The eLoad voltage will also increase up to 210V. Step 7. Slowly increase the eLoad up to 16A.
The eLoad voltage will decrease. Step 8. Slowly increase the DC power supply up to 800V.
The eLoad voltage will also increase up to 420V. Step 9. By slowly changing phase shifting and the eLoad current requirements, the actual power level
configuration can be adjusted to evaluate several configurations. Step 10. Decrease the DC power supply until 0V is reached.
The eLoad voltage will decrease. Step 11. If emergency shoot down is required, DPC_FSM_NEW_State can be set to "DPC_FSM_FAULT" to
disable PWM as well as phase shifting and energy transfer.
Figure 60. Open loop, phase shift power operation Vin=400V Vout=210V PS=0.06 Iload=9A
UM3198 - Rev 1
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UM3198
How to manage the STDES-DABBIDIR reference design
Figure 61. Open loop, phase shift power operation Vin=800V Vout=420V PS=0.06 Iload=16A
7.6.3
Mode 3 closed loop, voltage control
This test allows evaluation of the overall performance in voltage control mode of the application. Power equipment (Programmable DC Power Supply and DC eDLoad) is required for this test. DPI and protection shields are mandatory to prevent any injury. Power analyzer can be connected during this test to evaluate efficiency into specific operating points. PWM signals are generated by HRTIM according to the STM32CubeMX peripheral configuration. Dead time and switching frequency are managed by "PWM_FREQ", "DPC_DT_DAB1" and "DPC_DT_DAB2" of "DPC_Appplication_Conf.h" file.
Step 1. Configure the firmware parameters and flash the MCU.
Parametrs DPC_CTRL_INIT DPC_PWM_INIT StartUpCheck_INIT DPC_INRS_EN DPC_BURST_EN
fDAB_VDC_RefNext_V
Table 26. Mode 3 test parameters
Location DPC_Application_Conf.h DPC_Application_Conf.h DPC_Application_Conf.h DPC_Application_Conf.h DPC_Application_Conf.h DAB.pDAB_CTRL.pDAB_VCTRL_SlewRate. fDAB_VDC_RefNext_V
Value DAB_VOLTAGE_LOOP
PWM_Armed StartUpCheck_Disabled
RESET RESET
Variable during this test
Step 2. Step 3. Step 4. Step 5. Step 6.
Step 7.
Select and enable Constant Current mode "CC" in the High Power eLoad Set current reference to 1A. Go to the debugging mode by using the preferred IDE tool ("Live mode"). Set to 250 in DAB.pDAB_CTRL.pDAB_VCTRL_SlewRate. fDAB_VDC_RefNext_V Slowly increase the DC power supply up to 800V The eLoad power will also increase. Adapt the current reference of the eLoad to evaluate the operating mode at different power level.
UM3198 - Rev 1
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UM3198
How to manage the STDES-DABBIDIR reference design Step 8. The DC output voltage can also be adapted by changing "fDAB_VDC_RefNext_V".
The actual output voltage reference changes linearly according to the slew rate configuration. Step 9. If emergency shoot down is required, DPC_FSM_NEW_State can be set to "DPC_FSM_FAULT" to
disable PWM as well as phase shifting and energy transfer. Some operating examples are shown below:
Figure 62. Open loop, phase shift power operation Vin=800V Vout=330V(VCTRL) Iload=17A
Figure 63. Open loop, phase shift power operation Vin=800V Vout=410V(VCTRL) Iload=15A
UM3198 - Rev 1
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UM3198
How to manage the STDES-DABBIDIR reference design
Figure 64. Open loop, phase shift power operation Vin=800V Vout=410V(VCTRL) Iload=31A
7.6.4
Mode 4 closed loop, current control
This test allows evaluation of the overall performance of the application in current control mode. Power equipment (Programmable DC Power Supply and DC eDLoad) is required for this test. DPI and protection shields are mandatory to prevent injury. Power analyzer can be connected during this test to evaluate efficiency in specific operating points. PWM signals are generated by HRTIM according to the STM32CubeMX peripheral configuration. Dead time and switching frequency are managed by "PWM_FREQ", "DPC_DT_DAB1" and "DPC_DT_DAB2" of "DPC_Appplication_Conf.h" file.
Step 1. Configure the firmware parameters and flash the MCU.
Table 27. Mode 4 test parameters
Parameters DPC_CTRL_INIT DPC_PWM_INIT StartUpCheck_INIT DPC_INRS_EN DPC_BURST_EN
fDAB_IDC_RefNext_V
Location DPC_Application_Conf.h DPC_Application_Conf.h DPC_Application_Conf.h DPC_Application_Conf.h DPC_Application_Conf.h DAB.pDAB_CTRL.pDAB_ICTRL_SlewRate.
fDAB_IDC_RefNext_A
Value DAB_CURRENT_LOOP
PWM_Armed StartUpCheck_Disabled
RESET RESET
Variable during this test
Step 2. Step 3. Step 4. Step 5. Step 6. Step 7. Step 8.
Select and enable Constant Current mode "CC" in the High Power eLoad Set current reference to 250V. Go to the debugging mode by using the preferred IDE tool. Set to 2 in DAB.pDAB_CTRL.pDAB_ICTRL_SlewRate. fDAB_IDC_RefNext_A Slowly increase the DC power supply up to 800V; the eLoad power will also increase. Adapt the voltage reference of the eLoad to evaluate the operating mode at different power levels. The DC output current can also be adapted by changing "fDAB_IDC_RefNext_A". The actual output current reference changes linearly according to the slew rate configuration.
UM3198 - Rev 1
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UM3198
How to manage the STDES-DABBIDIR reference design
Step 9. If emergency shoot down is required, DPC_FSM_NEW_State can be set to "DPC_FSM_FAULT" to disable PWM as well as phase shifting and energy transfer.
UM3198 - Rev 1
page 52/83
UM3198
STDES-DABBIDIR results
8
STDES-DABBIDIR results
This section provides an additional overview of the reference design.
8.1
Charging mode waveforms
Waveforms analysis at:
·
Vin=800V
·
Vout=400V
·
fsw=100kHz
·
IDCload=40Amps
·
Voltage regulation operating mode
Figure 65. Switching waveform C1=DC load current C2=VDAB1 C3=VDAB2 C4=IDM7 C5=VDSM7 C6=VDSM8 C7=VGSM7 C8=ILsec
Waveforms analysis at:
·
Vin=830V
·
Vout=440V
·
fsw=100kHz
·
IDCload=56.3A
·
Voltage regulation operating mode
UM3198 - Rev 1
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UM3198
STDES-DABBIDIR results
Figure 66. Maximum power waveforms C1=DC load current C2=VDAB1 C3=VDAB2 C4=VDS_LV_HS C5= VDS_LV_LS C6=Iprim C7=VREFL C8=ILsec F3=VL
8.2
Efficiency
Efficiency characterization at:
·
Vin=800V
·
Vout=440V
·
fsw=100kHz
·
Voltage regulation operating mode
·
Iload=4.5-56.3 A (Constant current)
Figure 67. STDESDABBIDIR Efficiency
UM3198 - Rev 1
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UM3198 - Rev 1
9
Schematic diagrams
Figure 68. STDES-DABBIDIR - main board circuit schematic (1 of 6)
2
JP1
1 2
1 2
Con2
1
VDD_7V_EXT
J1 De v3
1
+ C1 33uF/25V
C3 1uF/25V
2 3
VDD_7V_EXT
R1 5.6k
VDD_7V
VDD_7V R2 5.6k
A
A
D1 Led Green
D2 Led Green
F1
2
1
0
0
30Ohm@ 100MHz
U1
LD29080DT50R
1 VIN
VOUT 3
4 GND
C5 470nF/25V
2
1
VDD_5V
+ C6 33uF/25V
A
VDD_5V
R3 5.6k
F2
VDD_5V 2
1
0
0
30Ohm@ 100MHz
D3 Led Green
U2
LDL1117S 33R
3 VIN
VOUT VOUT1
2 4
1 GND
C2 470nF/25V
2
1
VDD_3.3V
+ C4 33uF/25V
A
VDD_3.3V
R4 5.6k
D4 Led Green
VDD_7V_EXT
VDD_7V
C
C
C
C
2
JP2
1 2
1 2
Con2
1
VDD_12V_EXT
+ C7 33uF/25V
C8 1uF/25V
J2 De v3
1
2 3
VDD_12V_EXT
R6 5.6k
VDD_12V
VDD_12V
R7 5.6k
F3
2
1
0
0
30Ohm@ 100MHz
A
A
D5 LE D_ Ye llow
D6 LE D_ Ye llow
U3
LDL1117S 33R
3 VIN
VOUT VOUT1
2 4
1 GND
C10 470nF/25V
2
1
VDD_DRIVER VDD_3.3V_DRIVER
VDD_DRIVER
R5 5.6k
+ C9 33uF/25V
A
D7 Led Green
VDD_12V_EXT
VDD_12V
C
C
C
TW 1
TW 2
TW 3
TW 4
TW 5
TW 11
TW 13
M3 HOLE NOT P LATED TW 6
M3 HOLE NOT P LATED
M3 HOLE NOT P LATED M3 HOLE NOT P LATED M3 HOLE NOT P LATED M3 HOLE NOT P LATED
M3 HOLE NOT P LATED
TW 7
TW 8
TW 9
TW 10
TW 12
TW 14
TW 15
TW 16
M3 HOLE NOT P LATED
M3 HOLE NOT P LATED
M3 HOLE NOT P LATED M3 HOLE NOT P LATED M3 HOLE NOT P LATED M3 HOLE NOT P LATED M3 HOLE NOT P LATED M3 HOLE NOT P LATEMD3 HOLE NOT P LATED
TW 17
TW 18
TW 19
M3 HOLE NOT P LMA3THEDOLE NOT P LATEMD3 HOLE NOT P LATED
UM3198
Schematic diagrams
page 55/83
page 56/83
UM3198 - Rev 1
VDD_5V
P W M_S X_LS _1 P W M_S X_HS _1 P W M_DX_LS _1
P W M_DX_HS _1 P W M_S X_LS _2 P W M_S X_HS _2 FAN
I_ C T_ a d c I_ C T_ a d c
Id c 1 _ LE M Id c 2 _ LE M
NTC _ LV1 _ Te m p NTC _ LV2 _ Te m p NTC _ HV_ Te m p
TEMP I_ C T_ a d c V_bus _DC1 V_bus _DC2
Figure 69. STDES-DABBIDIR - main board circuit schematic (2 of 6)
J3 S OLDER J UMP ER3
J4 S OLDER J UMP ER3
J5 S OLDER J UMP ER3
3
2
1
P1
1A 2A 3A 4A 5A 6A 7A 8A 9A 10A 11A 12A 13A 14A 15A 16A 17A 18A 19A 20A 21A 22A 23A 24A 25A 26A 27A 28A 29A 30A 31A 32A
1A 2A 3A 4A 5A 6A 7A 8A 9A 10A 11A 12A 13A 14A 15A 16A 17A 18A 19A 20A 21A 22A 23A 24A 25A 26A 27A 28A 29A 30A 31A 32A
1B 2B 3B 4B 5B 6B 7B 8B 9B 10B 11B 12B 13B 14B 15B 16B 17B 18B 19B 20B 21B 22B 23B 24B 25B 26B 27B 28B 29B 30B 31B 32B
1B 2B 3B 4B 5B 6B 7B 8B 9B 10B 11B 12B 13B 14B 15B 16B 17B 18B 19B 20B 21B 22B 23B 24B 25B 26B 27B 28B 29B 30B 31B 32B
Digital P ower Connector
VDD_3.3V
P W M_DX_LS _2 P W M_DX_HS _2
1
2
3
P W M_S X_LS _1 GND_S X_HS _1
P W M_S X_HS _1
P W M_DX_LS _1
GND_S X_LS _1
GND_DX_HS _1
1
2
3
J7 S OLDER J UMP ER3
P W M_S X_LS _2
GND_S X_HS _2
J8 S OLDER J UMP ER3
J9 S OLDER J UMP ER3
3
2
1
3
2
1
P W M_S X_HS _2
P W M_DX_LS _2
GND_S X_LS _2
GND_DX_HS _2
1
2
3
1
1
2
2
3
3
J6 S OLDER J UMP ER3
P W M_DX_HS _1 GND_DX_LS _1
J 10 S OLDER J UMP ER3
P W M_DX_HS _2 GND_DX_LS _2
UM3198
Schematic diagrams
UM3198 - Rev 1
Figure 70. STDES-DABBIDIR - main board circuit schematic (3 of 6)
G_S X_HS _1 S _S X_HS _1
1
J17
1 J50
6 0 6 1 -0 -0 0 -1 5 -0 0 -0 0 -0 3 -0
G_DX_HS _1 S _DX_HS _1
1
J18
1
J51
6 0 6 1 -0 -0 0 -1 5 -0 0 -0 0 -0 3 -0
G_S X_LS _1 S _S X_LS _1
1
J21
1
J52
6 0 6 1 -0 -0 0 -1 5 -0 0 -0 0 -0 3 -0
G_DX_LS _1 S _DX_LS _1
1
J22
1
J53
6 0 6 1 -0 -0 0 -1 5 -0 0 -0 0 -0 3 -0
P WM_S X_HS _1 GND_S X_HS _1
1
J25
1
J54
6 0 6 1 -0 -0 0 -1 5 -0 0 -0 0 -0 3 -0
P WM_DX_HS _1 GND_DX_HS _1
1
J26
1
J55
6 0 6 1 -0 -0 0 -1 5 -0 0 -0 0 -0 3 -0
P WM_S X_LS _1 GND_S X_LS _1
1
J29
1
J56
6 0 6 1 -0 -0 0 -1 5 -0 0 -0 0 -0 3 -0
P WM_DX_LS _1 GND_DX_LS _1
1
J30
1
J57
6 0 6 1 -0 -0 0 -1 5 -0 0 -0 0 -0 3 -0
VDD_DRIVER
1
J31
1
J59
6 0 6 1 -0 -0 0 -1 5 -0 0 -0 0 -0 3 -0
VDD_12V
1
J34
1
J58
6 0 6 1 -0 -0 0 -1 5 -0 0 -0 0 -0 3 -0
G_S X_HS _2A S _S X_HS _2A
G_S X_HS _2B S _S X_HS _2B
G_S X_LS _2A S _S X_LS _2A
G_S X_LS _2B S _S X_LS _2B
P WM_S X_HS _2 GND_S X_HS _2
P WM_S X_LS _2 GND_S X_LS _2
1
J11
1 J60
6 0 6 1 -0 -0 0 -1 5 -0 0 -0 0 -0 3 -0
1
J13
1
J62
6 0 6 1 -0 -0 0 -1 5 -0 0 -0 0 -0 3 -0
1
J15
1
J64
6 0 6 1 -0 -0 0 -1 5 -0 0 -0 0 -0 3 -0
1
J19
1
J66
6 0 6 1 -0 -0 0 -1 5 -0 0 -0 0 -0 3 -0
1
J23
1
J68
6 0 6 1 -0 -0 0 -1 5 -0 0 -0 0 -0 3 -0
1
J27
1
J70
6 0 6 1 -0 -0 0 -1 5 -0 0 -0 0 -0 3 -0
G_DX_HS _2A S _DX_HS _2A
G_DX_HS _2B S _DX_HS _2B
G_DX_LS _2A S _DX_LS _2A
G_DX_LS _2B S _DX_LS _2B
P WM_DX_HS _2 GND_DX_HS _2
P WM_DX_LS _2 GND_DX_LS _2
1
J12
1
J61
6 0 6 1 -0 -0 0 -1 5 -0 0 -0 0 -0 3 -0
1
J14
1
J63
6 0 6 1 -0 -0 0 -1 5 -0 0 -0 0 -0 3 -0
1
J16
1
J65
6 0 6 1 -0 -0 0 -1 5 -0 0 -0 0 -0 3 -0
1
J20
1
J67
6 0 6 1 -0 -0 0 -1 5 -0 0 -0 0 -0 3 -0
1
J24
1
J69
6 0 6 1 -0 -0 0 -1 5 -0 0 -0 0 -0 3 -0
1
J28
1
J71
6 0 6 1 -0 -0 0 -1 5 -0 0 -0 0 -0 3 -0
VDD_DRIVER
1
J32
1
J72
VDD_12V
6 0 6 1 -0 -0 0 -1 5 -0 0 -0 0 -0 3 -0
1
J35
1
J74
6 0 6 1 -0 -0 0 -1 5 -0 0 -0 0 -0 3 -0
VDD_DRIVER
1
J33
1
J73
6 0 6 1 -0 -0 0 -1 5 -0 0 -0 0 -0 3 -0
VDD_12V
1
J36
1
J75
6 0 6 1 -0 -0 0 -1 5 -0 0 -0 0 -0 3 -0
UM3198
Schematic diagrams
page 57/83
UM3198 - Rev 1
BUS _LEM_DC1+
BUS _LEM_DC1-
J39
74651195 J45
TP 70 TES T P OINT
74651195
TP 71 TES T P OINT
3
2
4
1
Figure 71. STDES-DABBIDIR - main board circuit schematic (4 of 6)
C11 25uF
3
2
4
1
C12 25uF
POWER_P_1
C183 100nF
C184 100nF
C185 100nF
C186 100nF
P OW ER _N_1
TP 66 TES T P OINJT37
O UTA_ D AB1
O UTB_ D AB1
74651195 J41
1
2
T1 Coilcra ft-CS T3015-100E
74651195 TP 69
TES T P OINT
TP 67
J38
TES T P OINT
O UTA_ D AB2
74651195 J42
O UTB_ D AB2
74651195 TP 68
TES T P OINT
POWER_P_2
4
3
I_CT- I_CT+
P OW ER _N_2
1
2
A
T2
C
B
D
C177 1uF
C178 1uF
C179 1uF
C180 1uF
C181 1uF
C182 1uF
C187 1uF
3
2
4
1
C14 40uF
3
2
4
1
C15 40uF
3
2
4
1
BUS _LEM_DC2+ BUS _LEM_DC2J40
C16 40uF
TP 72
74651195
TES T P OINT
J46
TP 73
74651195
TES T P OINT
NTC _ HV+
U4
G_S X_LS _1 S _S X_LS _1
P OW ER _N_1
G2 S2
N2A N2B
N2C N2D
G2 S2
N2A N2B
N2C N2D
POWER_P_1
TP 48
TES T P OINT
TP 52 TES T P OINT
P1 P2
P1
P3 P2
P4 P3
P5 P4
P6 P7
P5 P6
P8 P7
P8
T1 T1 T2 T2
NTC _ HV-
G4 S4 N4A N4B N4C N4D
S1 G1 OUT1A OUT1B OUT1C OUT1D
S3 G3 OUT2A OUT2B OUT2C OUT2D
G4 S4 N4A N4B N4C N4D
S1 G1 OUT1A OUT1B OUT1C OUT1D
S3 G3 OUT2A OUT2B OUT2C OUT2D
G_DX_LS _1 S _DX_LS _1
P OW ER _N_1
S _S X_HS _1 G_S X_HS _1
TP 49 TES T P OINT
O UTA_ D AB1
S _DX_HS _1 G_DX_HS _1 TP 50
TES T P OINT
G_S X_HS _2A G_S X_HS _2B
S _S X_HS _2A S _S X_HS _2B
G_S X_LS _2A G_S X_LS _2B
S _S X_LS _2A S _S X_LS _2B
O UTB_ D AB1
TP 51 TES T P OINT
TP 27
TES TP OINT_1MM
1
TP 28
TES TP OINT_1MM
1
TP 29
TES TP OINT_1MM
1
TP 30
TES TP OINT_1MM
1
P OW ER _N_1 POWER_P_1 O UTA_ D AB1 O UTB_ D AB1
TP 31
TES TP OINT_1MM
1
TP 32
TES TP OINT_1MM
1
TP 33
TES TP OINT_1MM
1
TP 34
TES TP OINT_1MM
1
P OW ER _N_2 POWER_P_2 O UTA_ D AB2 O UTB_ D AB2
POWER_P_2
P_8
P_7
P_6
P_5
P_4
P_3
P_2
P_1
GH_1 GH_2
S H_1 S H_2
GL_1 GL_2
S L_1 S L_2
N_1
N_2
N_3
N_4
N_5
N_6
N_7
N_8
U5
T1 T2
NTC _ LV1 + NTC _ LV1 -
OUT_1 OUT_2
OUT_3 OUT_4
OUT_5 OUT_6 OUT_7
OUT_8 OUT_9
OUT_10
O UTA_ D AB2
POWER_P_2
P_8
P_7
P_6
P_5
P_4
P_3
P_2
P_1
G_DX_HS _2A G_DX_HS _2B
S _DX_HS _2A S _DX_HS _2B
G_DX_LS _2A G_DX_LS _2B
S _DX_LS _2A S _DX_LS _2B
GH_1 GH_2
S H_1 S H_2
GL_1 GL_2
S L_1 S L_2
N_1
N_2
N_3
N_4
N_5
N_6
N_7
N_8
U6
T1 T2
NTC _ LV2 + NTC _ LV2 -
OUT_1 OUT_2 OUT_3
OUT_4 OUT_5
OUT_6 OUT_7 OUT_8
OUT_9 OUT_10
O UTB_ D AB2
P OW ER _N_2
TP60 TP59 TP58 TP57
TP56 TP55 TP74 TP75
TP61 TP54 TP53 TP62
TES TTPEOS TINPTOINTETS TTPEOS TINPTOINT TES TTPEOS TINTPETOS TINTPETOS TINPTOINT TES TTPEOS TINTPETOS TINTPETOS TINPTOINT
P OW ER _N_2
OUTB_DAB2 OUTA_DAB2
POWER_P_2
P OW ER _N_2
W41 HEX NUT M3
W42 HEX NUT M3
W38 HEX NUT M3
W35 HEX NUT M3
W39 HEX NUT M3
W36 HEX NUT M3
W40 HEX NUT M3
W37 HEX NUT M3
W53
W54
W55
W50
HEX NUT M5 HEX NUT M5 HEX NUT M5 HEX NUT M5
W43 HEX S TANDOFF M3
W57 HEX S TANDOFF M3
W59 HEX S TANDOFF M3
W60 HEX S TANDOFF M3
W45
W46
W47
W48
HEX NUT M5 HEX NUT M5 HEX NUT M5 HEX NUT M5
W56 HEX S TANDOFF M3
W58 HEX S TANDOFF M3
W61 HEX S TANDOFF M3
W62 HEX S TANDOFF M3
UM3198
Schematic diagrams
page 58/83
page 59/83
UM3198 - Rev 1
P OWER_P _1
R11 3.9M
TP 8 Te s tP oint_Ring
R13 3.9M
R16 3.9M
R24 22K C36 1 nF /1 6 V
P OWER_N_1
GND_DC1
P OWER_P _2
R34 3.6M
TP 17 Te s tP oint_Ring
R37 3.6M
R39 3.6M
R44 33K C54 1 nF /1 6 V
P OWER_N_2
GND_DC2
Figure 72. STDES-DABBIDIR - main board circuit schematic (5 of 6)
5 V_ DC 1
VDD_5V
1
1
2
TP 5 F6
0
3 0 Ohm@ 1 0 0 MHz
Te s tP oint_Ring
F7
0
3 0 Ohm@ 1 0 0 MHz
2
C30 1 uF /2 5 V
C31 1 0 0 nF /2 5 V
GND_DC1
GND_DC1
U8
1
8
2 VDD1 VDD2 7
3 VIN VOUTP 6
4 S HTDN VOUTN 5
GND1 GND2
AMC 1 3 1 1 QDWVRQ1
GND_DC1
C33
C32
4.7uF/25V 100nF/25V
R20 0
R25 0
R21 1.8K
R26 1.8K
VDD_5V
F8 30Ohm@100MHz 0
1
TP 4 Te s tP oint_Ring
2
C28
C29
100nF/25V 1uF/25V
R17
3K
8
U9A
3 + V+ 1
R22
C35
2 - V-
N.M.
4
TS V912IDT 0
R27
TP 9
8
C37 N.M.
5+ 6-
4
U9B Te s tP oint_Ring V+
7
VTS V912IDT
V_bus _DC1
3K
VDD_5V
F5
2
1
LE M1 CAS R 15-NP
R8
14 Vc
Ref 11
3 0 Ohm@ 100 0 MHz
13
12
GND
OUT
N.M.
C25
C26
1uF/25V 100nF/25V
N.M.
OUT-1 OUT-2 OUT-3
8 IN-3
IN-1 IN-2
9 10
1 2 3
BUS _LEM_DC1+
BUS _LEM_DC1R14
VDD_5V
100
1
VDD_5V
F4
0
3 0 Ohm@ 1 0 0 MHz
2
TP 1 Te s tP oint_Ring
C34 N.M.
R10 4.12K-0.1%
TP 6 Te s tP oint_Ring
R15
R9 10K-0.1%
3+ 4-
2
5
C23
C24
1uF/25V 100nF/25V
TP 2
U7 Te s tP oint_Ring R12
1
TP 7
0
TS V911ILT
R0 18TL431UA1C0L3T
10K-0.1%
R19 1.65K-0.1%
Te s tP oint_Ring
R23 N.M.
2 REF 3A K1
N.M.
TP 3
Te s tP oint_Ring Id c 1 _ LE M
C27 N.M.
VDD_5V
1
F9
0
3 0 Ohm@ 1 0 0 MHz
U11 1779205141
C38 1 uF /2 5 V
1
C39 1 0 0 nF /2 5 V2
+VIN -VIN
+V0 7 -VO 5
5 V_ DC 1
C40 1 uF /2 5 V
2
GND_DC1
5 V_ DC 2
1
30Ohm@100MHz 0
2
TP 16 F14
Te s tP oint_Ring
VDD_5V
1
0
F13
30Ohm@100MHz 0
2
C49 1 uF /2 5 V
C50 1 0 0 nF /2 5 V
GND_DC2
GND_DC2
U14
1
8
2 VDD1 VDD2 7
3 VIN VOUTP 6
4 S HTDN VOUTN 5
GND1 GND2
AMC 1 3 1 1 QDWVRQ1
GND_DC2
C51 4 .7 uF /2 5 V
C52 1 0 0 nF /2 5 V
R41
R42
0
1.8K
R45
R46
0
1.8K
VDD_5V
1
0
F12
3 0 Ohm@ 1 0 0 MHz
2
TP 15 Te s tP oint_Ring
C46
C47
100nF/25V 1uF/25V
C53 N.M.
R40 3K
8
U15A
3 + V+
1
R43
2 - V-
4
TS V912IDT 0
R47 3K
TP 18
8
C55 N.M.
5+ 6-
4
U15B Te s tP oint_Ring
V+
7
V_bus _DC2
V-
TS V912IDT
VDD_5V
1
0
0
F16
0
0
3 0 Ohm@ 1 0 0 MHz
U20 1779205141
5 V_ DC 2
2
1 +VIN
C58
C59
1uF/25V 100nF/2 5V -VIN
+V0 7 -VO 5
C60 1 uF /2 5 V
GND_DC2
VDD_5V
F11
2
1
0
LE M2 CAS R 50-NP
R28
14 Vc
11 Re f
3 0 Ohm@ 1 0 0 MHz
13 GND
OUT 12
N.M.
C43
C44
1uF/25V 100nF/25V
N.M.
OUT-2 OUT-3
9 OUT-1
IN-2 IN-3
2 IN-1
10
3 8
1
BUS _LEM_DC2+
BUS _LEM_DC2R32
VDD_5V
100
1
VDD_5V
F10 0 30Ohm@100MHz
2
TP 10 Te s tP oint_Ring
C48 N.M.
R30
4.22K-0.1% TP 13 Te s tP oint_Ring
R33
R29 20K-0.1%
3+ 4-
2
5
C41
C42
1uF/25V 100nF/25V
TP 11
U12 1
Te s tP oint_Ring R31
TP 14
0
TS V911ILT
R0 35TL431UA1C3L3T
13.7K-0.1%
R36 13K-0.1%
Te s tP oint_Ring
R38 N.M.
2 REF 3A K1
N.M.
TP 12
Te s tP oint_Ring Id c 2 _ LE M
C45 N.M.
R49 VDD_5V
100
I_ C T+ I_ C T-
TP 22
Te s tP oint_RinRg50
2 REF 3A K1
U18
0
R54 TLVH431AIL3T 0
C63 N.M.
R55 N.M.
N.M.
TP 20
Te s tP oint_Ring R48
R66
TP 19
0
1
CT7e6s tP oint_Ring
N.M.
R58
N.M. N.M.
VDD_5V
1
0
F15
30Ohm@100MHz 0
2
8
3+ 2-
4
U17A V+
1
VTS V912IDT
R56
C56 1 uF /2 5 V
C57 1 0 0 nF /2 5 V
R51 0
N.M. N.M. C65
N.M.
R52 0
C61 N.M.
C62 N.M.
8
5+ 6-
4
U17B V+
7
VTS V912IDT
R57 0
TP 21 Te s tP oint_Ring
R53 I_CT_a dc
0
C64 N.M.
UM3198
Schematic diagrams
UM3198 - Rev 1
R60
5.6k D8 LED_Ye llow
J76 1 21
2 Con2
J47
1
2
1 2
Con2
A
C
TP 24
Te s tP oint_Ring
Q1 S TS 6NF 20V
6
1
5
2
8
3
7
TP 23
Te s tP oint_Ring
R62
4
F AN
22
R64 33k
Figure 73. STDES-DABBIDIR - main board circuit schematic (6 of 6)
R59
C66
470
1 0 0 n F /2 5 V
U19
1
5
NC GND1
2 GND
3
4
VOUT VCC
R5 .611kTPS2T5LM2 0 W 8 7 F
C67 1 0 0 n F /2 5 V VDD_5V
Te s tP oint_Ring
TP 26
TEMP Te s tP oint_Ring
R63
10k
C68
1 0 0 n F /2 5 V
VDD_5V
R108 1k
R110 1.07k-0.1%
R114 5.76k-0.1%
TP 42 Te s tP oint_Ring
VDD_re f_NTC_HV NTC_HV+
NTC _ HV-
U29 TLVH431AIL3T
R 1 3 1VDD_ 5 VVDD_ 5 V
L30
2
1
0 0
R132 0
22Ohm @ 100MHz
5
R111 910R-0.1%
3+ 4-
U27 1
2
TS V911IYLT
2 REF 3A K1
VDD_re f_NTC_HV
R117 1.5k-0.1%
R118 680-0.1%
C171 100nF 25V
C172 1uF 25V
Te s tP oint_Ring TP 43
NTC_HV_Te m p TP 63 Te s tP oint_Ring
HS 1 S K_56_100_AL
F AN1
F AN2
F AN3
F AN4
F AN5
F AN6
FAN
FAN
FAN
FAN
FAN
FAN
109P0412G3013 109P0412G3013 109P0412G3013 109P0412G3013 109P0412G3013 109P0412G3013
VDD_5V
R119 1k
R120 1.07k-0.1%
R122 5.76k-0.1%
TP 44 Te s tP oint_Ring
VDD_re f_NTC_LV2 NTC _ LV2 +
NTC _ LV2 -
U31 TLVH431AIL3T
R134
0 R133 0
VDD_5VVDD_5V L31
2
1
0
22Ohm@ 100MHz
5
R121 910R-0.1%
3+ 4-
U30 1
2
TS V911IYLT
2 REF 3A K1
VDD_re f_NTC_LV2
R123 1.5k-0.1%
R124 680-0.1%
C173 100nF 25V
C174 1uF 25V
Te s tP oint_Ring TP 45
NTC_LV2_Te m p TP 64 Te s tP oint_Ring
VDD_5V
R125 1k
R126 1.07k-0.1%
R128 5.76k-0.1%
TP 46 Te s tP oint_Ring
VDD_re f_NTC_LV1 NTC _ LV1 +
NTC _ LV1 -
U33 TLVH431AIL3T
R135 0
VDD_5VVDD_5V L32
2
1
0
22Ohm @ 100MHz
R136 0
R127 910R-0.1%
5
3+ 4-
U32 1
2
TS V911IYLT
2 REF 3A K1
VDD_re f_NTC_LV1
R129 1.5k-0.1%
R130 680-0.1%
C175 100nF 25V
C176 1uF 25V
Te s tP oint_Ring TP 47
NTC_LV1_Te m p TP 65 Te s tP oint_Ring
UM3198
Schematic diagrams
page 60/83
UM3198 - Rev 1
VDD_ 1 2 V
C9 2 .2 u F
2
FB2
1
2
03 0 Oh m @ 1 0 0 MHz
1
2
1
2
1
2 1
L1 22uH C13 4 7 0 n F/5 0 V
DC1 7
+VOUT 6 COM 5
-VO UT
VINVIN+
R12P22005D
VDD_ 1 2 V
DC2 7
+VOUT 6 COM 5
-VO UT 2 1 VIN-
VIN+
R12P22005D
1
1
1
C25 2 .2 u F
2
FB4
10
2
3 0 Oh m @ 1 0 0 MHz 0
2
2
L2
C26
22uH
4 7 0 n F/5 0 V
2
1
2
1
2
1
2
1
C4 2 .2 u F
C5 2 .2 u F
2
1
C10 2 .2 u F
C11 2 .2 u F
2
1
2
1
2
1
Figure 74. STDES-DABBIDIR - driver board for full bridge circuit schematic
TP 1 Te s tP o in t
VH_ S X_ HS
C6 100nF C12 100nF
TP 4 Te s tP o in t
S _ S X_ HS
TP 7 Te s tP o in t
VL_ S X_ HS
TP 5 Te s tP o in t
VDD_ DR IVER
FB1
1
2
1
0 3 00Oh m @ 1 0 0 MHz C1
1uF
1
1
C2 100nF
C3 1 n F/5 0 V
2
2
2
P WM_ S X_ HS S IG+_ S X_ HS
S IG-_ S X_ HS GND_ S X_ HS
2
R2 100
R6 100
2
1
TP 2 Te s tP o in t
C7 2 2 0 p F/5 0 V
TP 6 Te s tP o in t
1
C8 2 2 0 p F/5 0 V
U1
1
8
2 VDD GNDISO 7
3 IN+ CLAMP 6
4 IN- GOUT 5
GND VH
S TGAP 2 S iC S C
VL_ S X_ HS
R1 0
R3 22
G_ S X_ HS
VH_ S X_ HS
R5 22
TP 8 Te s tP o in t
VH_ S X_ LS
VH_ S X_ HS
Q1 2 S TF1 3 6 0
R4
1
2
12
6 .8 /2 W
R7
1
2
12
4 .7 /2 W
3
1
2 S TF2 5 5 0
Q2
4
2
VL_ S X_ HS
TP 3 Te s tP o in t
R8 N.M.
R9
N.M.
R10
D1
47k
TZMB2 0 -GS 0 8
C14
D2
N.M.
TZMB3 V3 -GS 0 8
G_ S X_ HS
G_ S X_ HS
S _ S X_ HS S _ S X_ HS
VDD_ DR IVER VDD_ 1 2 V
JP1 1
1
N.M. JP2
1 1
N.M. JP3
1 1
N.M. JP4
1 1
N.M.
S IG+_ S X_ HS S IG-_ S X_ HS
S IG+_ S X_ LS S IG-_ S X_ LS
S IG+_ DX_ LS S IG-_ DX_ LS
S IG+_ DX_ HS S IG-_ DX_ HS
1
C15 2 .2 u F
C16 2 .2 u F
C17 100nF
2
2
1
1
C24 2 .2 u F
2
C23 2 .2 u F
2
C22 100nF
1
TP 9 Te s tP o in t
S _ S X_ LS
TP 1 4 Te s tP o in t
VL_ S X_ LS
TP 1 1 Te s tP o in t
2
S IG+_ S X_ LS P WM_ S X_ LS GND_ S X_ LS S IG-_ S X_ LS
VDD_ DR IVER
FB3
1
2
0
3 0 Oh m @ 1 0 0 MHz
1
C19
1uF
2
1
2
1
C18 100nF
C20 1 n F/5 0 V
2
TP 1 0 Te s tP o in t R12
1
100 R18
2
C21 2 2 0 p F/5 0 V
TP 1 3 Te s tP o in t
U2
1
8
2 VDD GNDISO 7
3 IN+ CLAMP 6
4 IN- GOUT 5
GND VH
S TGAP 2 S iC S C
1
100
C27
2 2 0 p F/5 0 V
VL_ S X_ LS R11
1
2
12
0 R13 22
G_ S X_ LS
R15 22 VH_ S X_ LS
VH_ S X_ LS
Q3 2 S TF1 3 6 0
R14
1
2
12
6 .8 /2 W
R16
1
2
12
4 .7 /2 W
3
1
2 S TF2 5 5 0
Q4
4
2
VL_ S X_ LS
TP 1 2 Te s tP o in t
R17 N.M.
R19
N.M.
R20
D3
47k
TZMB2 0 -GS 0 8
C28
D4
N.M.
TZMB3 V3 -GS 0 8
G_ S X_ LS G_ S X_ LS
S _ S X_ LS
S _ S X_ LS
VDD_ DR IVER VDD_ 1 2 V
GND
VDD_ DR IVER VDD_ 1 2 V
P WM_ S X_ HS GND_ S X_ HS
P WM_ S X_ LS GND_ S X_ LS P WM_ DX_ LS GND_ DX_ LS P WM_ DX_ HS GND_ DX_ HS
JP5 1
1 N.M.
JP6 1
1 N.M.
JP7 1
1 N.M.
JP8 1
1 N.M.
JP9 1
1 N.M.
JP10 1
1 N.M.
JP11 1
1 N.M.
JP12 1
1 N.M.
JP13 1
1
N.M. JP14
1 1
N.M.
JP15 1
1
N.M. JP16
1 1
N.M.
JP17 1
1
N.M. JP18
1 1
N.M.
JP19 1
1
N.M. JP20
1 1
N.M.
G_ S X_ HS S _ S X_ HS
G_ DX_ HS S _ DX_ HS G_ S X_ LS S _ S X_ LS G_ DX_ LS S _ DX_ LS
TP 1 5 Te s tP o in t
VH_ DX_ HS
1
1
1
VDD_ 1 2 V
C36 2 .2 u F
1
C40 4 7 0 n F/5 0 V
1
DC3 7
+VOUT 6 COM 5
-VO UT 2 1 VIN-
VIN+
R12P22005D
L3 22uH
1
2
2
2
FB6
1
2
0 3 0 Oh m @ 1 0 0 MHz
2
1
2
C29 2 .2 u F
2
C30 2 .2 u F
2
C31 100nF
TP 1 6 Te s tP o in t
S _ DX_ HS
1
1
C37 2 .2 u F
2
C39 2 .2 u F
2
C38 100nF
TP 2 1 Te s tP o in t
VL_ DX_ HS
TP 1 8 Te s tP o in t
VDD_ DR IVER
FB5
1
2
0
0
3 0 Oh m @ 1 0 0 MHz
1
0
0
C32
1uF
1
1
C33 100nF
C34 1 n F/5 0 V
2
2
2
P WM_ DX_ HS S IG+_ DX_ HS
S IG-_ DX_ HS GND_ DX_ HS
2
R22 100
R27 100
2
1
TP 1 7 Te s tP o in t
C35 2 2 0 p F/5 0 V
TP 2 0 Te s tP o in t
1
C41 2 2 0 p F/5 0 V
U3
1
8
2 VDD GNDISO 7
3 IN+ CLAMP 6
4 IN- GOUT 5
GND VH
S TGAP 2 S iC S C
VL_ DX_ HS R21 0 G_ DX_ HS R23 22
R25 22
VH_ DX_ HS
VH_ DX_ HS
Q5 2 S TF1 3 6 0
R24
1
2
12
6 .8 /2 W
R26
1
2
12
4 .7 /2 W
3
1
2 S TF2 5 5 0
Q6
4
2
VL_ DX_ HS
TP 1 9 Te s tP o in t
R28 N.M.
R29
N.M.
R30
D5
47k
TZMB2 0 -GS 0 8
D6 TZMB3 V3 -GS 0 8
C42 N.M.
G_ DX_ HS G_ DX_ HS
S _ DX_ HS S _ DX_ HS
TP 2 2 Te s tP o in t
VH_ DX_ LS
1
1
1
VDD_ 1 2 V
C52 2 .2 u F
2
FB8
1
2
0 3 00Oh m @ 1 0 0 MHz
1
2
1
2
1
DC4 7
+VOUT 6 COM 5
-VO UT 2 1 VIN-
VIN+
R12P22005D
L4 22uH
C54 4 7 0 n F/5 0 V
2
1
2
C43 2 .2 u F
C44 2 .2 u F
C45 100nF
2
2
TP 2 3 Te s tP o in t
S _ DX_ LS
1
1
C50 2 .2 u F
2
C51 2 .2 u F
2
C53 100nF
TP 2 8 Te s tP o in t
VL_ DX_ LS
2
TP 2 6 Te s tP o in t
S IG+_ DX_ LS P WM_ DX_ LS
GND_ DX_ LS S IG-_ DX_ LS
VDD_ DR IVER
FB7
1
2
0
3 0 Oh m @ 1 0 0 MHz
1
0
C46
1uF
1
C47 100nF
1
C48 1 n F/5 0 V
2
2
2
R32 100
R40 100
1
1
2
TP 2 4 Te s tP o in t
C49 2 2 0 p F/5 0 V
U4
1
8
2 VDD GNDISO 7
3 IN+ CLAMP 6
4 IN- GOUT 5
GND VH
S TGAP 2 S iC S C
TP 2 7 Te s tP o in t
C55 2 2 0 p F/5 0 V
VL_ DX_ LS R31 0 G_ DX_ LS R33 22
R35 22
VH_ DX_ LS
VH_ DX_ LS
Q7 2 S TF1 3 6 0
R34
1
2
12
6 .8 /2 W
R36
1
2
12
4 .7 /2 W
3
1
2 S TF2 5 5 0
Q8
4
2
VL_ DX_ LS
TP 2 5 Te s tP o in t
R37 N.M.
R38
N.M.
R39
D7
47k
TZMB2 0 -GS 0 8
C56
D8
N.M.
TZMB3 V3 -GS 0 8
G_ DX_ LS G_ DX_ LS
S _ DX_ LS
S _ DX_ LS
UM3198
Schematic diagrams
page 61/83
UM3198 - Rev 1
Figure 75. STDES-DABBIDIR - driver board for half bridge circuit schematic (1 of 2)
VDD_ DRIVE R VDD_12V
GND
VDD_ DRIVE R VDD_12V
VDD_12V
F2
1
2
0
3 0 Ohm@ 1 0 0 MHz
2
C12 2.2uF
1
2
1
2
DC1
2 1
VINVIN+
7
+VOUT COM
6 5
-VOUT
R12P 22005D
1
L1
C13 22uH 470nF
TP 1 5000
VH_LS
1
1
C6 22uF
2
2
C5 2.2uF
C4 0.1uF
TP 4 5000
S _LS
1
1
C11 22uF
C9 2.2uF
C10 0.1uF
2
2
TP 7 5000
VL_LS
TP 8 5000
VH_HS
1
1
VDD_12V
C26 2.2uF
1
DC2
2
1
VINVIN+
7
+VOUT 6
COM -VOUT
5
R12P 22005D
1
L2
C27 22uH 470nF
1
2
2
2
F4
1
2
0
3 0 Ohm@ 1 0 0 MHz
C17 22uF
2
C16 2.2uF
C18 0.1uF
2
TP 9 5000
S _HS
1
1
C23 22uF
2
C24 2.2uF
C25 0.1uF
2
TP 14 5000
VL_HS
TP 5 5000
TP 11 5000
P WM_LS S IG+_LS
S IG-_LS GND_LS
VDD_ DRIVE R
3 0 Ohm@ 1 0 0 MHz
1
2
F1 0
100nF
1
1nF
C1
C2
C3
2
1 uF /2 5 V
TP 2 5000 R2
100 R6 100
C7 220pF
TP 6 5000
C8 220pF
U1
1
8
2 3
VDD IN+
GNDIS O CLAMP
7 6
4
INGND
GOUT VH
5
S TGAP 2S iCS C
VL_LS R1 0
VH_LS
G_LS
R3 22 R5
22
VH_LS
Q1 2S TF1360
R4 1 12 2
8.2/2W
R7
1
2
12
6.8/2W
3
1
2S TF2550
Q2
4
2
VL_LS
GND_HS S IG-_HS
S IG+_HS P WM_HS
VDD_ DRIVE R R15
3 0 Ohm@ 1 0 0 MHz
1
2
F 30
100nF
C19
C20
1 uF /2 5 V
TP 10 5000
100 R19 100
C22 220pF
TP 13 5000
C28 220pF
2
1
1nF C21
U2
1
8
2 VDD GNDIS O 7
3 4
IN+ IN-
CLAMP GOUT
6 5
GND
VH
S TGAP 2S iCS C
VL_HS R14 0
G_HS
R16 22 R18 22
VH_HS
VH_HS
Q3 2S TF1360
R17 1 12 2
8.2/2W
R20 1 12 2
6.8/2W
3
1
2S TF2550
Q4
4
2
VL_HS
TP 3 5000
R8 N.M.
R9
R10
D1
N.M.
47k
TZMB20-GS 08
D2 TZMB3V3-GS 08
C14 N.M.
G_LS
G_LS
S _LS S _LS
R11 N.M.
R12
R13
D3
N.M.
47k
TZMB20-GS 08
D4 TZMB3V3-GS 08
C15 N.M.
TP 12 5000
R21 N.M.
R22
R23
D5
N.M.
47k
TZMB20-GS 08
D6 TZMB3V3-GS 08
C29 N.M.
VDD_ DRIVE R
GND
VDD_12V
GND
G_HS
G_HS
JP1 1
1
NM JP2
11
NM JP3
1 1
NM JP4
1 1
NM
S _HS
S _HS
R24 N.M.
R25
R26
D7
N.M.
47k
TZMB20-GS 08
D8 TZMB3V3-GS 08
C30 N.M.
S IG+_LS S IG-_LS S IG+_HS S IG-_HS
JP5 1
1
NM JP6
11
NM JP7
1 1
NM JP8
1 1
NM
JP9 1
1 J P 10 NM
11 NM
JP11 1
1 J P 12NM
1 1
NM JP13
1 1 J P 14NM
1 1
NM JP15
11 J P 16NM
1 1
NM
G_HS S _HS
G_LS S _LS
Figure 76. STDES-DABBIDIR - driver board for half bridge circuit schematic (1 of 1)
VDD_ DRIVE R VDD_12V
GND
VDD_ DRIVE R VDD_12V
VDD_12V
F2
1
2
0
3 0 Ohm@ 1 0 0 MHz
2
C12 2.2uF
1
2
1
2
DC1
2 1
VINVIN+
7
+VOUT
COM -VOUT
6 5
R12P 22005D
1
L1
C13 22uH 470nF
TP 1 5000
VH_LS
1
1
C6 22uF
2
2
C5 2.2uF
C4 0.1uF
TP 4 5000
S _LS
1
1
C11 22uF
C9 2.2uF
C10 0.1uF
2
2
TP 7 5000
VL_LS
TP 8 5000
VH_HS
1
1
VDD_12V
C26 2.2uF
1
DC2
2
1
VINVIN+
7
+VOUT 6
COM -VOUT
5
R12P 22005D
1
L2
C27 22uH 470nF
1
2
2
2
F4
1
2
0
3 0 Ohm@ 1 0 0 MHz
C17 22uF
2
C16 2.2uF
C18 0.1uF
2
TP 9 5000
S _HS
1
1
C23 22uF
2
C24 2.2uF
C25 0.1uF
2
TP 14 5000
VL_HS
TP 5 5000
TP 11 5000
P WM_LS S IG+_LS
S IG-_LS GND_LS
VDD_ DRIVE R
3 0 Ohm@ 1 0 0 MHz
1
2
F1 0
100nF
1
1nF
C1
C2
C3
2
1 uF /2 5 V
TP 2 5000 R2
100 R6 100
C7 220pF
TP 6 5000
C8 220pF
U1
1
8
2 3
VDD IN+
GNDIS O CLAMP
7 6
4
INGND
GOUT VH
5
S TGAP 2S iCS C
VL_LS R1 0
VH_LS
G_LS
R3 22 R5
22
VH_LS
Q1 2S TF1360
R4
1
2
12
8.2/2W
R7
1
2
12
6.8/2W
3
1
2S TF2550
Q2
4
2
VL_LS
GND_HS S IG-_HS
S IG+_HS P WM_HS
VDD_ DRIVE R R15
3 0 Ohm@ 1 0 0 MHz
1
2
F 30
100nF
C19
C20
1 uF /2 5 V
TP 10 5000
100 R19 100
C22 220pF
TP 13 5000
C28 220pF
2
1
1nF C21
U2
1
8
2 VDD GNDIS O 7
3 4
IN+ IN-
CLAMP GOUT
6 5
GND
VH
S TGAP 2S iCS C
VL_HS R14 0
G_HS
R16 22 R18 22
VH_HS
VH_HS
Q3 2S TF1360
R17 1 12 2
8.2/2W
R20 1 12 2
6.8/2W
3
1
2S TF2550
Q4
4
2
VL_HS
TP 3 5000
R8 N.M.
R9
R10
D1
N.M.
47k
TZMB20-GS 08
D2 TZMB3V3-GS 08
C14 N.M.
G_LS
G_LS
S _LS S _LS
R11 N.M.
R12
R13
D3
N.M.
47k
TZMB20-GS 08
D4 TZMB3V3-GS 08
C15 N.M.
TP 12 5000
R21 N.M.
R22
R23
D5
N.M.
47k
TZMB20-GS 08
D6 TZMB3V3-GS 08
C29 N.M.
VDD_ DRIVE R
GND
VDD_12V
GND
G_HS
G_HS
JP1 1
1
NM JP2
11
NM JP3
1 1
NM JP4
1 1
NM
S _HS
S _HS
R24 N.M.
R25
R26
D7
N.M.
47k
TZMB20-GS 08
D8 TZMB3V3-GS 08
C30 N.M.
S IG+_LS S IG-_LS S IG+_HS S IG-_HS
JP5 1
1
NM JP6
11
NM JP7
1 1
NM JP8
1 1
NM
JP9 1
1 J P 10 NM
1 1
NM JP11
11 J P 12NM
1 1
NM JP13
1 1 J P 14NM
1 1
NM JP15
11 J P 16NM
1 1
NM
G_HS S _HS
G_LS S _LS
UM3198
Schematic diagrams
page 62/83
UM3198 - Rev 1
Figure 77. STDES-DABBIDIR - control board circuit schematic
TP 1 Te s tP o in t
VH_ S X_ HS
1
1
1
VDD_ 1 2 V
C9 2 .2 u F
2
FB2
1
2
3 0 Oh m @ 1 0 0 MHz
1
2
1
1
2 1
L1 22uH C13 4 7 0 n F/5 0 V
DC1 7
+VOUT 6 COM 5
-VO UT
VINVIN+
R12P22005D
2
0
2
1
2
C4 2 .2 u F
C5 2 .2 u F
2
1
C10 2 .2 u F
C11 2 .2 u F
2
2
1
2
C6 100nF C12 100nF
TP 4 Te s tP o in t
S _ S X_ HS
TP 7 Te s tP o in t
VL_ S X_ HS
TP 8 Te s tP o in t
VH_ S X_ LS
1
1
1
VDD_ 1 2 V
DC2
7 +VOUT 6
COM 5 -VO UT
2
1
VIN0 VIN+
0
R12P22005D
1
1
1
C25 2 .2 u F
2
FB4
1
2
3 0 Oh m @ 1 0 0 MHz
2
2
L2
C26
22uH
4 7 0 n F/5 0 V
2
1
2
C15 2 .2 u F
C16 2 .2 u F
C17 100nF
2
2
1
1
C24 2 .2 u F
2
C23 2 .2 u F
2
C22 100nF
TP 9 Te s tP o in t
S _ S X_ LS
TP 1 4 Te s tP o in t
VL_ S X_ LS
TP 5 Te s tP o in t
VDD_ DR IVER
FB1
1
2
1
3 0 Oh m @ 1 0 0 MHz C1
1uF
1
1
C2 100nF
C3 1 n F/5 0 V
2
2
2
P WM_ S X_ HS S IG+_ S X0_ HS0
S IG-_ S X_ HS GND_ S X_ HS
2
R2 100
R6 100
2
1
TP 2 Te s tP o in t
C7 2 2 0 p F/5 0 V
TP 6 Te s tP o in t
1
C8 2 2 0 p F/5 0 V
U1
1
8
2 VDD GNDISO 7
3 IN+ CLAMP 6
4 IN- GOUT 5
GND VH
S TGAP 2 S iC S C
VL_ S X_ HS
R1 0
R3 22
G_ S X_ HS
VH_ S X_ HS
R5 22
VH_ S X_ HS
Q1 2 S TF1 3 6 0
R4
1
2
12
6 .8 /2 W
R7
1
2
12
4 .7 /2 W
3
1
2 S TF2 5 5 0
Q2
4
2
VL_ S X_ HS
TP 3 Te s tP o in t
R8 N.M.
R9
N.M.
R10
D1
47k
TZMB2 0 -GS 0 8
D2 TZMB3 V3 -GS 0 8
C14 N.M.
G_ S X_ HS
G_ S X_ HS
S _ S X_ HS S _ S X_ HS
TP 1 1 Te s tP o in t
2
0
S IG+_ S X_ LS P WM_ S X_ LS GND_ S X_ LS S IG-_ S X_ LS
VDD_ DR IVER
FB3
1
2
3 0 Oh m @ 1 0 0 MHz
1
C19
1uF
2
1
2
1
C18 100nF
C20 1 n F/5 0 V
2
TP 1 0 Te s tP o in t R12
1
100 R18
2
C21 2 2 0 p F/5 0 V
TP 1 3 Te s tP o in t
U2
1
8
2 VDD GNDISO 7
3 IN+ CLAMP 6
4 IN- GOUT 5
GND VH
S TGAP 2 S iC S C
1
100
C27
2 2 0 p F/5 0 V
VL_ S X_ LS R11
1
2
12
0 R13 22
G_ S X_ LS
R15 22 VH_ S X_ LS
VH_ S X_ LS
Q3 2 S TF1 3 6 0
R14
1
2
12
6 .8 /2 W
R16
1
2
12
4 .7 /2 W
3
1
2 S TF2 5 5 0
Q4
4
2
VL_ S X_ LS
TP 1 2 Te s tP o in t
R17 N.M.
R19
N.M.
R20
D3
47k
TZMB2 0 -GS 0 8
D4 TZMB3 V3 -GS 0 8
C28 N.M.
G_ S X_ LS G_ S X_ LS
S _ S X_ LS
S _ S X_ LS
VDD_ DR IVER VDD_ 1 2 V
JP1 1
1
N.M. JP2
1 1
N.M. JP3
1 1
N.M. JP4
1 1
N.M.
S IG+_ S X_ HS S IG-_ S X_ HS
S IG+_ S X_ LS S IG-_ S X_ LS
S IG+_ DX_ LS S IG-_ DX_ LS
S IG+_ DX_ HS S IG-_ DX_ HS
P WM_ S X_ HS GND_ S X_ HS
P WM_ S X_ LS GND_ S X_ LS P WM_ DX_ LS GND_ DX_ LS P WM_ DX_ HS GND_ DX_ HS
JP5 1
1 N.M.
JP6 1
1 N.M.
JP7 1
1 N.M.
JP8 1
1 N.M.
JP9 1
1 N.M.
JP10 1
1 N.M.
JP11 1
1 N.M.
JP12 1
1 N.M.
JP13 1
1
N.M. JP14
1 1
N.M.
JP15 1
1
N.M. JP16
1 1
N.M.
JP17 1
1
N.M. JP18
1 1
N.M.
JP19 1
1
N.M. JP20
1 1
N.M.
G_ S X_ HS S _ S X_ HS
G_ DX_ HS S _ DX_ HS G_ S X_ LS S _ S X_ LS G_ DX_ LS S _ DX_ LS
VDD_ DR IVER VDD_ 1 2 V
GND
VDD_ DR IVER VDD_ 1 2 V
TP 1 5 Te s tP o in t
VH_ DX_ HS
0
VDD_ 1 2 V
C36 2 .2 u F
1
C40 4 7 0 n F/5 0 V
1
DC3 7
+VOUT 6 COM 5
-VO UT 2 1 VIN-
VIN+
R12P22005D
L3 22uH
1
2
2
2
FB6
1
2
3 0 Oh m @ 1 0 0 MHz
2
1
2
1
1
1
C29 2 .2 u F
2
C30 2 .2 u F
2
C31 100nF
TP 1 6 Te s tP o in t
S _ DX_ HS
1
1
C37 2 .2 u F
2
C39 2 .2 u F
2
C38 100nF
TP 2 1 Te s tP o in t
VL_ DX_ HS
0
0
TP 2 2 Te s tP o in t
VH_ DX_ LS
1
1
1
VDD_ 1 2 V
C52 2 .2 u F
2
FB8
1
2
3 0 Oh m @ 1 0 0 MHz
1
2
1
2
1
DC4 7
+VOUT 6 COM 5
-VO UT 2 1 VIN-
VIN+
R12P22005D
L4 22uH
C54 4 7 0 n F/5 0 V
2
1
2
C43 2 .2 u F
C44 2 .2 u F
C45 100nF
2
2
TP 2 3 Te s tP o in t
S _ DX_ LS
1
1
C50 2 .2 u F
2
C51 2 .2 u F
2
C53 100nF
TP 2 8 Te s tP o in t
VL_ DX_ LS
TP 1 8 Te s tP o in t
VDD_ DR IVER
FB5
1
2
0
0
3 0 Oh m @ 1 0 0 MHz
1
0
0
C32
1uF
1
1
C33 100nF
C34 1 n F/5 0 V
2
2
2
P WM_ DX_ HS S IG+_ DX_ HS
S IG-_ DX_ HS GND_ DX_ HS
0 0
2
R22 100
R27 100
2
1
TP 1 7 Te s tP o in t
C35 2 2 0 p F/5 0 V
TP 2 0 Te s tP o in t
1
C41 2 2 0 p F/5 0 V
U3
1
8
2 VDD GNDISO 7
3 IN+ CLAMP 6
4 IN- GOUT 5
GND VH
S TGAP 2 S iC S C
VL_ DX_ HS R21 0 G_ DX_ HS R23 22
R25 22
VH_ DX_ HS
VH_ DX_ HS
Q5 2 S TF1 3 6 0
R24
1
2
12
6 .8 /2 W
R26
1
2
12
4 .7 /2 W
3
1
2 S TF2 5 5 0
Q6
4
2
VL_ DX_ HS
TP 1 9 Te s tP o in t
R28 N.M.
R29
N.M.
R30
D5
47k
TZMB2 0 -GS 0 8
C42
D6
N.M.
TZMB3 V3 -GS 0 8
G_ DX_ HS G_ DX_ HS
S _ DX_ HS S _ DX_ HS
2
TP 2 6 Te s tP o in t
S IG+_ DX_ LS P WM_ DX_ LS
GND_ DX_ LS S IG-_ DX_ LS
VDD_ DR IVER
FB7
1
2
1
3 0 Oh m @ 1 0 0 MHz C46
1uF
1
C47 100nF
1
C48 1 n F/5 0 V
2
2
2
R32 100
R40 100
1
1
2
TP 2 4 Te s tP o in t
C49 2 2 0 p F/5 0 V
U4
1
8
2 VDD GNDISO 7
3 IN+ CLAMP 6
4 IN- GOUT 5
GND VH
S TGAP 2 S iC S C
TP 2 7 Te s tP o in t
C55 2 2 0 p F/5 0 V
VL_ DX_ LS R31 0 G_ DX_ LS R33 22
R35 22
VH_ DX_ LS
VH_ DX_ LS
Q7 2 S TF1 3 6 0
R34
1
2
12
6 .8 /2 W
R36
1
2
12
4 .7 /2 W
3
1
2 S TF2 5 5 0
Q8
4
2
VL_ DX_ LS
TP 2 5 Te s tP o in t
R37 N.M.
R38
N.M.
R39
D7
47k
TZMB2 0 -GS 0 8
D8 TZMB3 V3 -GS 0 8
C56 N.M.
G_ DX_ LS G_ DX_ LS
S _ DX_ LS
S _ DX_ LS
UM3198
Schematic diagrams
page 63/83
UM3198
Bill of materials
10
Bill of materials
Item 1 2 3 4
Q.ty 1 1 2 1
Table 28. STDES-DABBIDIR bill of materials
Ref.
Part/value
Table 29. Main
board bill of
-
materials
Table 30. Driver
board for full bridge bill of
-
materials
Table 31. Driver
board for half bridge bill of
-
materials
Table 32. STDE S-DABBIDIR control board
Description Manufacturer
Order code
Main board
ST
Not available for separate sale
Driver board for full bridge
ST
Not available for separate sale
Driver board for half bridge
ST
Control board ST
Not available for separate sale
Not available for separate sale
Item 1 2 3 4 5 6
7 8
Q.ty 5 3 15 2 3 16
14 2
Table 29. Main board bill of materials
Ref.
Part/value
C1 C4 C6 C7 C9
33uF/25V
C2 C5 C10
470nF/25V
C3 C8 C23 C25 C29 C30 C38 C40 C41 C43 C47 C49 C56 C58 C60
1uF/25V
C11 C12
25uF
C14 C15 C16 40uF
C24 C26 C28 C31 C32 C39 C42 C44 C46 C50 C52 C57 C59 C66 C67 C68
C27 C34 C35 C37 C45 C48 C53 C55 C61 C62 C63 C64 C65 C76
100nF/25V N.M.
C33 C51
4.7uF/25V
Description Manufacturer
Order code
Cap Pol Radial (Electrolytic); 6.60 mm X 6.60 mm X 5.50 mm H body
WURTH
865230443004
CAPACITOR CERAMIC SMD WURTH 0603
885012206075
CAPACITOR CERAMIC SMD WURTH 0603
885012206076
WCAP-FTDB
DC-Link Capacitor,32.5m
WURTH
m,25uF
WCAP-FTDB
DC-Link Capacitor,32.5m
WURTH
m,40uF
890744428006CS 890764428004CS
CAPACITOR CERAMIC SMD WURTH 0603
885012206071
CAPACITOR CERAMIC SMD ANY 0603
CAPACITOR CERAMIC SMD WURTH 0603
ANY 885012106012
UM3198 - Rev 1
page 64/83
UM3198
Bill of materials
Item 9 10 11 12 13 14 15 16
17
18 19 20
21
Q.ty 2 3 3 7 4 5 3 16
6
1 2 8
52
Ref.
Part/value
Description Manufacturer
Order code
C36 C54
1nF/16V
CAPACITOR CERAMIC SMD WURTH 0603
885012006029
C171 C173 C175
100nF 25V
CAPACITOR CERAMIC SMD 0603
Würth Elektronik
885012206071R
C172 C174 C176
1uF 25V
CAPACITOR CERAMIC SMD 0603
Würth Elektronik
885012206076
C177 C178
C179 C180 C181 C182
1uF
C187
CAPACITOR CERAMIC SMD WURTH 2220
885342214001
C183 C184 C185 C186
100nF
CAPACITOR CERAMIC SMD WURTH 2220
885342214173
D1 D2 D3 D4 D7
Led Green
LED GREEN CLEAR 0805 SMD
Wurth
150080YS75000
D5 D6 D8
LED_Yellow
LED YELLOW CLEAR 0805 SMD
Wurth
150080GS75000
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16
30Ohm@100M Hz
FERRITE BEAD 30 OHM 0805 WURTH 1LN
742792030
FAN1 FAN2 FAN3 FAN4 FAN5 FAN6
109P0412G301 3
Sanyo Denki 109P Series Axial Fan, 12 V dc, DC Operation, 25.1m³/h, 3.72W, 40 x 40 x 28mm
Sanyo Denki
109P0412G3013
SK 56 100 AL |
HS1
SK_56_100_AL FISCHER
fischerelektronik SK 56 100 AL
ELEKTRONIK
J1 J2
Dev3
SWITCH SLIDE SPDT 500MA WURTH 12V
450301014042
J3 J4 J5 J6 J7 SOLDER
J8 J9 J10
JUMPER3
TIN DROP JUMPER 0603 3pin
J11 J12 J13 J14
J15 J16 J17 J18
J19 J20 J21 J22
J23 J24 J25 J26
J27 J28 J29 J30
J31 J32 J33 J34 J35 J36 J50 J51 J52 J53 J54 J55
6061-0-00-15-0 0-00-03-0
J56 J57 J58 J59
J60 J61 J62 J63
J64 J65 J66 J67
J68 J69 J70 J71
J72 J73 J74 J75
Circuit Board Hardware - PCB RECPT. GOLD/ Mill-Max NICKEL .106 IN. PRESSFIT
6061-0-00-15-00-00-03-0
UM3198 - Rev 1
page 65/83
UM3198
Bill of materials
Item 22 23 24 25 26 27 28 29 30 31 32 33 34
35
36 37
Q.ty 8 2 2 3 1 1 1 1 7 7 2 1 3
14
3 4
Ref.
Part/value
Description Manufacturer
Order code
J37 J38 J39 J40 J41 J42 J45 J46
74651195
Power to the Board 10MM 40A SOLDER SCREW M4
WURTH
74651195
J47 J76
Con2
CONN TERM BLOCK 2POS 5.08MM PCB
Wurth
691213510002
JP1 JP2
Con2
CONN TERM BLOCK 2POS 5.08MM PCB
Wurth
691213510002
L30 L31 L32
22Ohm@100M Hz
Würth Elektronik
742792021
LEM1
CASR 15-NP
SENSOR CURRENT HALL 15A AC/DC
LEM USA Inc. CASR 15-NP
LEM2
CASR 50-NP
SENSOR CURRENT HALL 15A AC/DC
LEM USA Inc. CASR 50-NP
Connector Erni
P1
CON64AB
284166 32X2 ERNI
284166
female
Q1
STS6NF20V, SO-8
MOSFET N-CH 20V 6A 8SOIC
ST
STS6NF20V
R1 R2 R3 R4 R5 R6 R7
5.6k
CHIP RESISTOR SMD 1% 1/4W 1206
ANY
ANY
R8 R23 R28 R38 R55 R56 R58
N.M.
CHIP RESISTOR SMD 1% 1/10W 0603
ANY
ANY
R9 R15
10K-0.1%
CHIP RESISTOR SMD 1% 1/10W 0603
ANY
ANY
CHIP
R10
4.12K-0.1%
RESISTOR SMD 1% 1/10W
ANY
ANY
0603
R11 R13 R16 3.9M
CHIP RESISTOR SMD 1% 1/4W 1206
ANY
ANY
R12 R18 R20 R22 R25 R31 R35 R41 R43 0 R45 R48 R50 R53 R54
CHIP RESISTOR SMD 1% 1/10W 0603
ANY
ANY
R14 R32 R49 100
CHIP RESISTOR SMD 1% 1/10W 0603
ANY
ANY
R17 R27 R40 R47
3K
CHIP RESISTOR SMD 1% 1/10W 0603
ANY
ANY
UM3198 - Rev 1
page 66/83
UM3198
Bill of materials
Item 38 39 40 41 42 43 44 45 46 47 48 49 50 51
Q.ty 1 4 1 1 1 1 3 1 2 3 1 1 1 1
Ref. R19 R21 R26 R42 R46 R24 R29 R30 R33 R34 R37 R39 R36 R44 R64 R51 R52 R57 R59 R60 R61 R62
Part/value 1.65K-0.1% 1.8K 22K 20K-0.1% 4.22K-0.1% 13.7K-0.1% 3.6M 13K-0.1% 33K 0 470 5.6k 5.1k 22
Description Manufacturer
CHIP RESISTOR SMD 1% 1/10W 0603
ANY
ANY
CHIP RESISTOR SMD 1% 1/10W 0603
ANY
ANY
CHIP RESISTOR SMD 1% 1/10W 0603
ANY
ANY
CHIP RESISTOR SMD 1% 1/10W 0603
ANY
ANY
CHIP RESISTOR SMD 1% 1/10W 0603
ANY
ANY
CHIP RESISTOR SMD 1% 1/10W 0603
ANY
ANY
CHIP RESISTOR SMD 1% 1/4W 1206
ANY
ANY
CHIP RESISTOR SMD 1% 1/10W 0603
ANY
ANY
CHIP RESISTOR SMD 1% 1/10W 0603
ANY
ANY
CHIP RESISTOR SMD 1% 1/10W 0603
ANY
ANY
CHIP RESISTOR SMD 1% 1/10W 0603
ANY
ANY
CHIP RESISTOR SMD 1% 1/10W 0603
ANY
ANY
CHIP RESISTOR SMD 1% 1/10W 0603
ANY
ANY
CHIP RESISTOR SMD 1% 1/10W 0603
ANY
ANY
Order code
UM3198 - Rev 1
page 67/83
UM3198
Bill of materials
Item 52 53 54 55 56 57 58 59 60 61 62
63
64 65
Q.ty 1 1 3 3 3 3 3 3 6 1 1
22
4 8
Ref.
R63
R66
R108 R119 R125
R110 R120 R126
R111 R121 R127
R114 R122 R128
R117 R123 R129
R118 R124 R130
R131 R132 R133 R134 R135 R136
T1
T2
TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20 TP21 TP22 TP23 TP24 TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34
Part/value
Description Manufacturer
Order code
CHIP
10k
RESISTOR SMD 1% 1/10W
ANY
ANY
0603
CHIP
1
RESISTOR
ANY
ANY
SMD 2512
CHIP
1k
RESISTOR SMD 1% 1/10W
0603
1.07k-0.1%
CHIP RESISTOR SMD 1% 1/10W 0603
910R-0.1%
CHIP RESISTOR SMD 0.1% 1/10W 0603
5.76k-0.1%
CHIP RESISTOR SMD 1% 1/10W 0603
1.5k-0.1%
CHIP RESISTOR SMD 0.1% 1/10W 0603
680-0.1%
CHIP RESISTOR SMD 0.1% 1/10W 0603
CHIP
0
RESISTOR SMD 0.1%
1/10W 0603
Coilcraft-
Tranf,Radio
CST3015-100E 1:100,80A
Coilcraft
CST3015-100E
Frenetic_3201104
TestPoint_Ring TestPoint RIng ANY
ANY
TestPoint_Ring TestPoint RIng ANY
TESTPOINT_1 MM
ANY
UM3198 - Rev 1
page 68/83
UM3198
Bill of materials
Item 66
67
68
69 70 71 72 73 74 75 76 77 78
Q.ty 9
25
19
1 2 2 2 2 3 2 1 2 1
Ref.
Part/value
Description Manufacturer
Order code
TP42 TP43 TP44 TP45 TP46 TP47 TP63 TP64 TP65
TestPoint_Ring
Polo terminale RS Pro, diam. foro 1mm, Bronzo fosforoso
ANY
ANY
TP48 TP49 TP50 TP51 TP52 TP53 TP54 TP55 TP56 TP57 TP58 TP59 TP60 TP61 TP62 TP66 TP67 TP68 TP69 TP70 TP71 TP72 TP73 TP74 TP75
TEST POINT
PC TEST POINT NATURAL
Harwin Inc.
S1751-46R
TW1 TW2 TW3 TW4 TW5 TW6 TW7 TW8 TW9 TW10 TW11 TW12 TW13 TW14 TW15 TW16 TW17 TW18 TW19
M3 HOLE NOT PLATED
Mounting Hole M3 not plated Pan Head
U1
LD29080DT50R , DPAK
IC REG LINEAR 5V 800MA DPAK
ST
LD29080DT50R
U10 U13
TL431ACL3T, SOT23
IC VREF SHUNT ADJ SOT23-3
ST
TL431ACL3T
U11 U20
1779205141
DC DC CONVERTER 5V 1W
WURTH
1779205141
U12 U7
TSV911ILT, SOT23-5L
IC OPAMP GP
8MHZ RRO
ST
SOT23-5
TSV911ILT
U14 U8
AMC1311QDW IC ISOLATION Texas
VRQ1
8SOIC
Instruments
AMC1311QDWVRQ1
U15 U17 U9
TSV912IDT, SO-8
IC OPAMP GP
8MHZ RRO
ST
8SO
TSV912IDT
U2 U3
LDL1117S33R, SOT-223
IC REG LINEAR 3.3V ST 800MA SOT223
LDL1117S33R
ACEPACKTM 2
U4
A2F12M12W2- Full-bridge F1, ACEPACK 2 1200V, 12mO
ST
A2F12M12W2-F1
SiC
U5 U6
A2H6M12W3
ACEPACKTM 2 -
Half-bridge -
1200V, 6mO
ST
SiC MOSFET
Gen2 and NTC
A2H6M12W3
U18
TLVH431AIL3T, SOT23
IC VREF SHUNT ADJ SOT23-3
ST
TLVH431AIL3T
UM3198 - Rev 1
page 69/83
UM3198
Bill of materials
Item 79 80 81 82 83 84
Q.ty 1 3 3 8 8 8
Ref.
U19
U27 U30 U32
U29 U31 U33
W35 W36 W37 W38 W39 W40 W41 W42 W43 W56 W57 W58 W59 W60 W61 W62 W45 W46 W47 W48 W50 W53 W54 W55
Part/value
Description
STLM20W87F, SOT323-5L
SENS TEMP ANLG VOLT SOT-323-5
TSV911IYLT, SOT23-5L
IC OPAMP GP 8MHZ RRO SOT23-5
TLVH431AIL3T, SOT23
IC VREF SHUNT ADJ SOT23-3
HEX NUT M3 HEX NUT M3
HEX STANDOFF M3
HEX STANDOFF M3X0.5 STEEL 50MM
HEX NUT M5 HEX NUT M5
Manufacturer ST ST ST ANY WURTH ANY
Order code STLM20W87F TSV911IYLT TLVH431AIL3T
971500321
Item 1 2 3
4
5 6 7 8 9
Q.ty 4 12 4
20
8 4 4 4 4
Table 30. Driver board for full bridge bill of materials
Ref.
Part/value
C1 C19 C32 C46
0603 (1608 Metric)
C2 C6 C12 C17 C18 C22 C31 C33 C38 C45 C47 C53
0603 (1608 Metric)
C3 C20 C34 C48
0603 (1608 Metric)
C4 C5 C9 C10 C11 C15 C16 C23 C24 C25 C29 C30 C36 C37 C39 C43 C44 C50 C51 C52
0805 (2012 Metric)
C7 C8 C21 C27 C35 C41 C49 C55
0603 (1608 Metric)
C13 C26 C40 C54
0805 (2012 Metric)
C14 C28 C42 C56 D1 D3 D5 D7
D2 D4 D6 D8
DO-213AC, MINI-MELF, SOD-80
DO-213AC, MINI-MELF, SOD-80
Description Manufacturer
Order code
CAPACITOR CERAMIC SMD 0603
Wurth Electronics Inc.
885012206076
CAPACITOR CERAMIC SMD 0603
Wurth Electronics Inc.
885012206095
CAPACITOR CERAMIC SMD 0603
Wurth Electronics Inc.
885012006063
CAPACITOR CERAMIC SMD 0805
Wurth Electronics Inc.
885012207079
CAPACITOR CERAMIC SMD 0603
Wurth Electronics Inc.
CAPACITOR CERAMIC SMD 0805
Wurth Electronics Inc.
885012006059 885012207102
N.M.
ANY
DIODE ZENER Vishay
20V 500MW
Semiconductor TZMB20-GS08
SOD80
Diodes Division
DIODE ZENER Vishay
3.3V 500MW Semiconductor TZMB3V3-GS08
SOD80
Diodes Division
UM3198 - Rev 1
page 70/83
UM3198
Bill of materials
Item 10 11
12
13 14 15 16 17 18 19 20 21 22 23
Q.ty 4 8
20
4 4 4 3 8 8 4 4 8 4 1
Ref.
DC1 DC2 DC3 DC4
FB1 FB2 FB3 FB4 FB5 FB6 FB7 FB8
JP1 JP2 JP3 JP4 JP5 JP6 JP7 JP8 JP9 JP10 JP11 JP12 JP13 JP14 JP15 JP16 JP17 JP18 JP19 JP20
Part/value
0.77" L x 0.39" W x 0.49" H (19.5mm x 9.8mm x 12.5mm)
0805 (2012 Metric)
L1 L2 L3 L4
0805 (2012 Metric)
Q1 Q3 Q5 Q7 Q2 Q4 Q6 Q8
TO-243AA, SOT-89
TO-243AA, SOT-89
R1 R21 R31
1210 (3225 Metric)
R2 R6 R12 R18 R22 R27 R32 R40
0603 (1608 Metric)
R3 R5 R13 R15 R23 R25 R33 R35
1210 (3225 Metric)
R4 R14 R24 R34
2512 (6332 metric)
R7 R16 R26 R36
2512 (6332 metric)
R8 R9 R17 R19 R28 R29 R37 R38
0603 (1608 Metric)
R10 R20 R30 R39
0603 (1608 Metric)
R11
1206 (3216 Metric)
Description Manufacturer
Order code
CONV DC/DC 2W 12VIN +20/-5VOUT T
Recom Power
R12P22005D
FERRITE BEAD 30 OHM 0805 1LN
Wurth Electronics Inc.
74279206
IC & Component Sockets .060" Dia St Pins
Mill-Max
3560-1-00-15-00-00-03-0
FIXED IND 22UH 130MA 3.7 OHM SMD
Taiyo Yuden
TRANS NPN 60V 3A SOT-89
ST
TRANS PNP 50V 5A SOT 89
ST
CHIP RESISTOR SMD
ANY
CHIP RESISTOR SMD 1% 1/10W 0603
ANY
CHIP RESISTOR SMD
ANY
CHIP RESISTOR SMD
ANY
CHIP RESISTOR SMD
ANY
CHIP RESISTOR SMD 1% 1/10W 0603
ANY
CHIP RESISTOR SMD 1% 1/10W 0603
ANY
CHIP RESISTOR SMD 5% 1/4W 1206
ANY
LBC2012T220M 2STF1360 2STF2550 ANY ANY ANY ANY ANY ANY
ANY
ANY
UM3198 - Rev 1
page 71/83
UM3198
Bill of materials
Item 24 25
Q.ty 28 4
Ref.
TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20 TP21 TP22 TP23 TP24 TP25 TP26 TP27 TP28
U1 U2 U3 U4
Part/value
Description Manufacturer
Order code
0.100" Dia x 0.180" L (2.54mm x 4.57mm)
TEST POINT PC MINI .040"D ANY RED
ANY
Galvanically
8-SOIC (0.295", isolated 4 A
7.50mm Width), single gate
ST
SO 8 WIDE 300 driver for SiC
MOSFETs
STGAP2SICSC
Item 1
2
3 4 5 6 7 8 9
Q.ty 2
2
1 4 6 4 4 2 4
Table 31. Driver board for half bridge bill of materials
Ref.
Part/value
C1 C19
0603 (1608 Metric)
C2 C20
0603 (1608 Metric)
C3
0603 (1608 Metric)
C4 C10 C18 C25
0603 (1608 Metric)
C5 C9 C12 C16 0805 (2012
C24 C26
Metric)
C6 C11 C17 C23
1210 (3225 Metric)
C7 C8 C22 C28
0603 (1608 Metric)
C13 C27
C14 C15 C29 C30
0805 (2012 Metric)
Description Manufacturer
Order code
CAPACITOR CERAMIC SMD 0603 (MLCC) GRM 1µF, ±10%, 25V cc, SMD
Wurth Electronics Inc.
885012206076
CAPACITOR CERAMIC SMD 0603 (MLCC) GRM 100nF, ±10%, 25V cc, SMD
Wurth Electronics Inc.
885012206071
CAPACITOR CERAMIC SMD 0603 (MLCC) C 1nF, ±10%, 25V cc, SMD
Wurth Electronics Inc.
885012006044
CAP CER 0.1UF 50V X7R 0603
Wurth Electronics Inc.
885012206095
CAP CER 2.2UF 50V X7R 0805
Wurth Electronics Inc.
885012207079
CAP CER 22UF Würth 25V X5R 1210 Elektronik
885012109014
CAPACITOR CERAMIC SMD 0603 (MLCC) C 220pF, ±5%, 1kV cc, SMD
Wurth Electronics Inc.
885012006059
CAPACITOR CERAMIC SMD 0805
Wurth Electronics Inc.
885012207102
N.M.
ANY
UM3198 - Rev 1
page 72/83
UM3198
Bill of materials
Item 10
12 13 14
15
16 17 18 19 20 21 22 23 24 25
Q.ty 1 4 4 2 4
16
2 2 2 2 4 4 2 2 8 4
Ref.
Part/value
C21
0603 (1608 Metric)
D1 D3 D5 D7
D2 D4 D6 D8
DC1 DC2
F1 F2 F3 F4 JP1 JP2 JP3 JP4 JP5 JP6 JP7 JP8 JP9 JP10 JP11 JP12 JP13 JP14 JP15 JP16 L1 L2
Q1 Q3 Q2 Q4
R1 R14
DO-213AC, MINI-MELF, SOD-80 DO-213AC, MINI-MELF, SOD-80 0.77" L x 0.39" W x 0.49" H (19.5mm x 9.8mm x 12.5mm)
0805 (2012 Metric)
0805 (2012 Metric)
TO-243AA, SOT-89 TO-243AA, SOT-89
1210 (3225 Metric)
R2 R6 R15 R19
R3 R5 R16 R18
1210 (3225 Metric)
R4 R17
2512 (6332 metric)
R7 R20
2512 (6332 metric)
R8 R9 R11 R12 R21 R22 R24 R25
R10 R13 R23 R26
0603 (1608 Metric)
Description Manufacturer
Order code
CAPACITOR CERAMIC SMD 0603 (MLCC) C 1nF, ±10%, 25V cc, SMD
Wurth Electronics Inc.
885012006044
DIODE ZENER Vishay
20V 500MW
Semiconductor TZMB20-GS08
SOD80
Diodes Division
DIODE ZENER Vishay
3.3V 500MW Semiconductor TZMB3V3-GS08
SOD80
Diodes Division
CONV DC/DC 2W 12VIN +20/-5VOUT T
RECOM
R12P22005D
FERRITE BEAD 30 OHM 0805 1LN
Wurth Electronics Inc.
742792030
IC & Component Sockets .060" Dia St Pins
Mill-Max
3560-1-00-15-00-00-03-0
FIXED IND 22UH 130MA 3.7 OHM SMD
Taiyo Yuden
TRANS NPN 60V 3A SOT-89
ST
TRANS PNP 50V 5A SOT 89
ST
CHIP RESISTOR SMD
Resistore SMD Bourns 100O ±1%, 0,1W, 0603, serie CR0603
ANY
CHIP RESISTOR SMD
CHIP RESISTOR SMD
CHIP RESISTOR SMD
N.M.
N.M.
CHIP RESISTOR SMD 1% 1/10W 0603
LBC2012T220M 2STF1360 2STF2550 ANY
N.M.
UM3198 - Rev 1
page 73/83
UM3198
Bill of materials
Item 26 27
Q.ty 14 2
Ref.
TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14
U1 U2
Part/value
Description Manufacturer
Order code
0.100" Dia x 0.180" L (2.54mm x 4.57mm)
TEST POINT PC MINI .040"D ANY RED
ANY
Galvanically
8-SOIC (0.295", isolated 4 A
7.50mm Width), single gate
ST
SO 8 WIDE 300 driver for SiC
MOSFETs
STGAP2SICSC
Item 1
2
3
4
5 6 7 8 9 10 11 12
Q.ty 1
20
7
17
1 1 3 1 7 2 1 5
Table 32. STDES-DABBIDIR control board
Ref.
Value
Description Manufacturer
Order code
CN56
Jtag_SWD_Ada pter
10 Way, 2 Row, Vertical Pin Header
Wurth
62201021121
C3,C6,C7,C28, C34,C36,C37,C 45,C48,C49,C5 1,C52,C53,C55, C59,C61,C62,C 65,C66,C134
100nF
Multilayer Ceramic Capacitor MLCC
Wurth
885012206046
C2,C27,C35,C4 7,C50,C58,C64
1uF
Multilayer Ceramic Capacitor MLCC
Wurth
885012206076
C11,C12,C13,C 14,C20,C21,C2 2,C24,C30,C31, C32,C33,C38,C 40,C42,C43,C1 40
100pF
Multilayer Ceramic Capacitor MLCC
Wurth
885012006057
C135
220nF
Multilayer Ceramic Capacitor MLCC
ANY
ANY
Multilayer
C18
470nF
Ceramic Capacitor
Wurth
885012207102
MLCC
C15,C23,C29 2.2nF
Multilayer Ceramic Capacitor MLCC
KEMET
C0603C222J5GACTU
C133
10uF
Multilayer Ceramic Capacitor MLCC
ANY
ANY
D2,D4,D5,D9,D 12,D13,D15
GREEN
Green LED
Wurth
150080GS75000
D3,D10
SMAJ5.0A-TR, SMA
Uni-Directional TVS Diode,
ST
SMAJ5.0A-TR
D7
RED
Red LED
Wurth
150080RS75000
F1,F2,F3,F4,F5
22Ohm@100M Hz
Ferrite Beads
Wurth
742792021
UM3198 - Rev 1
page 74/83
UM3198
Bill of materials
Item 13 14 15 16 17 18 19 20
21
22 23 24
25
26 27
Q.ty 2 1 1 2 1 1 1 13
36
10 7 2
26
1 5
Ref. JP1,JP7 JP2
J1
Value 3JP_pcb STRIP_2X3
i2C
J2,J3
CON4
LED1
SMTL4-SBC
L1
WE-CBF
P1
CON 64 male
R2,R4,R5,R8,R
10,R13,R16,R1 9,R44,R125,R1
10k
28,R129,R130
R6,R7,R9,R12, R14,R15,R20,R 21,R22,R24,R2 5,R26,R27,R28, R29,R31,R33,R 34,R36,R38,R4 0,R41,R42,R43, R47,R48,R49,R 52,R54,R55,R5 7,R58,R59,R60, R61,R62
N.M.
R17,R39,R45,R
46,R50,R51,R5 3,R56,R131,R1
1k
33
R23,R30,R35,R 126,R127,R134, 0 R135
S1,S2
te_fsm4jsma
TP1,TP2,TP3,T P4,TP5,TP6,TP 7,TP8,TP9,TP1 0,TP11,TP12,T P13,TP14,TP15 ,TP16,TP17,TP 18,TP19,TP20, TP21,TP22,TP2 4,TP25,TP26,T P27
TestPoint
USB2
microUSB
U2,U5,U6,U9,U TSV912IDT,
10
SO-8
Description
Solder Jumper Selector
Solder Jumper Selector
4 Way, 1 Row, Straight Pin Header
4 Way, 1 Row, Straight Pin Header
LED Bivar, Verde, rosso, SMD, 2,4 V, 2 Led, PLCC 4
Ferrite Bead
Multipole plug
Manufacturer
Order code
Solder Jumper Selector
Solder Jumper Selector
Solder Jumper Selector
Solder Jumper Selector
Wurth
61300411121
Wurth
61300411121
BIVAR
WE ERNI
SMTL4-SBC
74279262 533406
Thick Film SMD Resistor
ANY
ANY
RESISTOR
ANY
ANY
Thick Film SMD ANY
ANY
Thick Film SMD Resistor
ANY
ANY
Button Tactile Switch, Single Pole Single Throw (SPST)
TE Connectivity FSM4JSMATR
Test Terminal ANY
ANY
Micro USB Connector Receptacle
Op Amp
MOLEX ST
47346-0001 TSV912IDT
UM3198 - Rev 1
page 75/83
UM3198
Bill of materials
Item 28
Q.ty 1
Ref. U3
29
1
U23
30
1
31
1
U22 PCB
Value
Description Manufacturer
Order code
LD29080S33R, LDO Voltage
PPACK 5
Regulators
ST
LD29080S33R
STM32G474RE
Tx_3TTC_EVAL , LQFP 64
STM32G474RE T3
ST
10x10x1.4 mm
STM32G474RE
ESDAL, SOT23-3L
Dual-Element Uni-Directional ST TVS Diode
ESDA6V1L
FR4 4 LAYER
PCB FR4- 4 Layer size 98x48x1.6mm
UM3198 - Rev 1
page 76/83
Revision history
Date 04-Dec-2023
Table 33. Document revision history
Version 1
Changes Initial release.
UM3198
UM3198 - Rev 1
page 77/83
UM3198
Contents
Contents
1 Safety and compliance information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.2 Main characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 Dual active bridge topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.4 Typical application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 DAB converter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 STDES-DABBIDIR reference design overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.1 Power stage of the STDES-DABBIDIR reference design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 Driving stage of the STDES-DABBIDIR reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 Control stage of the STDES-DABBIDIR reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 STDES-DABBIDIR hardware implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 5.1 Input/output requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.1 Maximum input power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.2 Maximum DC input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.3 Nominal DC input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.4 Minimum DC input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.5 Maximum DC output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.6 Minimum DC output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.7 Nominal DC output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 Sensing circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2.1 HV voltage sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2.2 LV voltage sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2.3 HV current sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2.4 LV current sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.3 Magnetics design requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3.1 Transformer turn ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3.2 Total resonance inductance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3.3 Transformer peak magnetic field estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3.4 Auxiliary inductance - peak magnetic field estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3.5 Transformer Magnetizing inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3.6 Magnetics section design proposal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.4 Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.4.1 Power device current stress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.4.2 Power switches conduction losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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5.4.3 Power switch switching losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6 STDES-DABBIDIR control implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 6.1 Software implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.2 Peripheral configuration STM32CubeMX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.2.1 High-resolution timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.2.2 ADC configuration and triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2.3 Configuration files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.2.4 Finite state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7 How to manage the STDES-DABBIDIR reference design . . . . . . . . . . . . . . . . . . . . . . . . . . .40 7.1 System setup requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.2 Safety precautions and protective equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.3 How to use the STDES-DABBIDIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.4 How to connect the STDES-DABBIDIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.5 How to set up the STDES-DABBIDIR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.6 How to operate the STDES-DABBIDIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.6.1 Mode 1 open loop, driving check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.6.2 Mode 2 open loop, phase shift power operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.6.3 Mode 3 closed loop, voltage control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.6.4 Mode 4 closed loop, current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8 STDES-DABBIDIR results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 8.1 Charging mode waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.2 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9 Schematic diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 10 Bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
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List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53.
STDES-DABBIDIR reference design board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STDES-DABBIDIR reference design overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 STDES-DC2DCDAB block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Typical DC battery charger architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SiC power module assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DAB topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 DAB operation (combo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Simplified diagram of DAB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Primary side referred simplified diagram of DAB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power transfer vs phase shift in DAB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Average model of the DAB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Simplified small signal equivalent circuit of DAB converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power stage blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 STDES-DABBIDIRDF driver board based on 4xSTGAP2SIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 STDES-DABBIDIRDH driver board based on 2xSTGAP2SIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 STDES-DABBIDIR FW architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Control stage blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 HV voltage sensing equivalent circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 STDES-DABBIDIR HV sensing circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 LV sensing equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 STDES-DABBIDIR LV sensing circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 HV current sensing equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 STDES-DABBIDIR HV current sensing circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 LV Current sensing equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 STDES-DABBIDIR LV current sensing circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Frenetic 32011-04-Design-Report (design requirements section). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Frenetic 32011-04 Transformer winding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Frenetic 32011-04 Auxiliary inductor windings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3D image of transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3D model of transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3D model of auxiliary inductor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Switch RMS current equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Control block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 CUBE ecosystem development flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DPC development flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 STM32G474 MCU pinout configuration for STDES-DABBIDIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Generic phase shift - HRTIM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 HRTIM pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 HRTIM modulation pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 ADC clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 ADC clock source selection (STM32CubeMX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 CubeMX ADC Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 SPS ADC sampling requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 STM32CubeMX ADC1 Regular conversion configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 STM32CubeMX ADC2 regular conversion configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 HRTIM ADC trigger CubeMX configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 HRTIM compare unit enabled for ADC triggering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 STDES-DABBIDIR configuration file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Application Init functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Finite state machine bubble representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 STDES-DABBIDIR FSM application service execution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Power equipment connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Connecting the STDES-DABBIDIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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List of figures
Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77.
ST-LINK/V2 ISOL + adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 ST-LINK/V2 ISOL connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 IAR EWARM program procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 IAR EWARM debug procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Mode 1 test configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Typical PWM and driving voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Open loop, phase shift power operation Vin=400V Vout=210V PS=0.06 Iload=9A . . . . . . . . . . . . . . . . . . . . . 48 Open loop, phase shift power operation Vin=800V Vout=420V PS=0.06 Iload=16A . . . . . . . . . . . . . . . . . . . . 49 Open loop, phase shift power operation Vin=800V Vout=330V(VCTRL) Iload=17A . . . . . . . . . . . . . . . . . . . . 50 Open loop, phase shift power operation Vin=800V Vout=410V(VCTRL) Iload=15A . . . . . . . . . . . . . . . . . . . . 50 Open loop, phase shift power operation Vin=800V Vout=410V(VCTRL) Iload=31A . . . . . . . . . . . . . . . . . . . . 51 Switching waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Maximum power waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 STDESDABBIDIR Efficiency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 STDES-DABBIDIR - main board circuit schematic (1 of 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 STDES-DABBIDIR - main board circuit schematic (2 of 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 STDES-DABBIDIR - main board circuit schematic (3 of 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 STDES-DABBIDIR - main board circuit schematic (4 of 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 STDES-DABBIDIR - main board circuit schematic (5 of 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 STDES-DABBIDIR - main board circuit schematic (6 of 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 STDES-DABBIDIR - driver board for full bridge circuit schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 STDES-DABBIDIR - driver board for half bridge circuit schematic (1 of 2). . . . . . . . . . . . . . . . . . . . . . . . . . . 62 STDES-DABBIDIR - driver board for half bridge circuit schematic (1 of 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 62 STDES-DABBIDIR - control board circuit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
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List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33.
Main characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 HV-side input voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 HV sensing input and output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 STDES-DABBIDIR effective value of HV sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 HV-side output voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 LV sensing input and output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 STDES-DABBIDIR effective value of LV sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 HV-side current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Parameters for HV-side op amp conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Theoretical overall parameters of HV current sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 LV-side current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Parameters for LV-side op amp conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Theoretical overall parameters of HV current sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Parameters for magnetic design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Parameters for transformer peak magnetic field estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Clock Prescaler settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 ADC and timer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Converter signal connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Software compatibility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Control section firmware configuration defines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Hardware protection firmware configuration defines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Hardware parameters firmware configuration defines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Mode 1 test parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Example of frequency and dead time configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Mode 2 test parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Mode 3 test parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Mode 4 test parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 STDES-DABBIDIR bill of materials. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Main board bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Driver board for full bridge bill of materials. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Driver board for half bridge bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 STDES-DABBIDIR control board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
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IMPORTANT NOTICE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
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