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ESP32-S2 技术参考手册
technical specification for models including:
PDF 通用异步接收器/发送器 (UART) - ESP32-S2 - — ESP-IDF 编程指南 v5.4.1 文档
数字签名 (DS) - ESP32-S2 - — ESP-IDF 编程指南 v5.4.1 文档
SPI 主机驱动程序 - ESP32-S2 - — ESP-IDF 编程指南 v5.4.1 文档
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esp32-s2 technical reference manual cn #spi ESP32-S2
1.3
www.espressif.com
ESP32-S2 ESP32-S2 ESP32-S2 aaaab
· cb · b PDF b PDF PDF PDF b · PDF acaaa aab · GoBack cb Acrobat PDF c Acrobat Reader Adobe DC Acrobat PDF c Firefoxb
No. I
1 (ULP) 2 DMA (DMA)
II 3 4 eFuse (eFuse)
III 5 IO MUX GPIO 6 7 Boot (BOOTCTRL) 8 9 10 (SYSTIMER) 11 (TIMG) 12 (WDT) 13 XTAL32K (XTWDT) 14 (PMS) 15
IV 16 SHA (SHA) 17 AES (AES) 18 RSA (AES) 19 HMAC (HMAC) 20 (DSA) 21 (XTS_AES) 22 (RNG)
V 23 UART (UART) 24 SPI (SPI) 25 I2C (I2C) 26 I2S (I2S) 27 (PCNT) 28 USB OTG 29 (TWAI) 30 LED PWM (LEDC) 31 (RMT)
VI 32
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3
ESP32-S2 TRM ( 1.3)
https://www.espressif.com/documentation/esp32-s2_technical_reference_manual_cn.pdf
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4
ESP32-S2 TRM ( 1.3)
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I
31
1 (ULP)
32
1.1
32
1.2
32
1.3
34
1.4
34
1.5 ULP-FSM
36
1.5.1 ULP-FSM
36
1.5.2 ULP-FSM
36
1.5.2.1 ALU -
37
1.5.2.2 ST -
39
1.5.2.3 LD -
41
1.5.2.4 JUMP -
42
1.5.2.5 JUMPR - c R0
43
1.5.2.6 JUMPS - c
44
1.5.2.7 HALT -
44
1.5.2.8 WAKE -
44
1.5.2.9 WAIT -
45
1.5.2.10 TSENS -
45
1.5.2.11 ADC - ADC
45
1.5.2.12 REG_RD -
46
1.5.2.13 REG_WR -
47
1.6 ULP-RISC-V
47
1.6.1 ULP-RISC-V
47
1.6.2
48
1.6.3 ULP-RISC-V
48
1.7 RTC I2C
49
1.7.1 RTC I2C
49
1.7.2 RTC I2C
49
1.7.3 RTC I2C
49
1.7.3.1 I2C
50
1.7.3.2 I2C_RD - I2C
50
1.7.3.3 I2C_WR - I2C
51
1.7.3.4
51
1.7.4 RTC I2C
51
1.8
52
1.8.1
52
1.8.2 RTC I2C
52
1.9
53
1.10
53
1.10.1 ULP (ALWAYS_ON)
53
5
ESP32-S2 TRM ( 1.3)
1.10.2 ULP (RTC_PERI) 1.10.3 RTC I2C (RTC_PERI) 1.10.4 RTC I2C (I2C) 1.11 1.11.1 ULP (ALWAYS_ON) 1.11.2 ULP (RTC_PERI) 1.11.3 RTC I2C (RTC_PERI) 1.11.4 RTC I2C (I2C)
2 DMA (DMA)
2.1 2.2 2.3
2.3.1 DMA 2.3.2 2.3.3 DMA 2.3.4 2.3.5 2.3.6 Internal DMA 2.3.7 EDMA
2.3.7.1 RAM 2.3.8 RAM 2.4 Copy DMA 2.5 UART DMA (UDMA) 2.6 SPI DMA 2.7 I2S DMA 2.8 DMA 2.9 Copy DMA 2.10 DMA 2.11 2.12 2.13
II
3
3.1 3.2 3.3
3.3.1 3.3.2
3.3.2.1 Internal ROM 0 3.3.2.2 Internal ROM 1 3.3.2.3 Internal SRAM 0 3.3.2.4 Internal SRAM 1 3.3.2.5 RTC FAST Memory
6
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53 54 54 55 55 58 62 64
78 78 78 79 79 79 80 81 81 81 81 82 82 82 83 84 85 85 86 86 86 87 89
111
112 112 112 113 113 114 115 115 115 115 115
ESP32-S2 TRM ( 1.3)
3.3.3
3.3.4 3.3.5
3.3.2.6 RTC SLOW Memory 3.3.3.1 3.3.3.2 3.3.3.3 Cache DMA / 3.3.5.1 3.3.5.2 3.3.5.3 / 3.3.5.4 PeriBus1
4 eFuse (eFuse)
4.1 4.2 4.3
4.3.1 4.3.1.1 EFUSE_WR_DIS 4.3.1.2 EFUSE_RD_DIS 4.3.1.3
4.3.2 4.3.3 4.3.4
4.3.4.1 eFuse 4.3.4.2 eFuse VDDQ 4.3.4.3 eFuse 4.3.5 4.3.6 4.4 4.5 4.6
III
5 IO MUX GPIO
5.1 5.2 GPIO
5.2.1 5.2.2 5.2.3 5.2.4 GPIO 5.3 GPIO 5.3.1 5.3.2 5.3.3 GPIO 5.3.4 Sigma Delta (SDM)
7
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115 116 116 116 117 117 118 118 118 118 120
121 121 121 121 121 124 125 125 126 127 128 128 129 129 130 130 130 131 134
156
157 157 158 158 158 159 160 160 160 160 161 161
ESP32-S2 TRM ( 1.3)
5.3.4.1 5.3.4.2 5.4 GPIO 5.4.1 5.4.2 5.4.3 5.4.3.1 GPIO 5.4.3.2 CPU GPIO 5.5 IO MUX I/O 5.5.1 5.5.2 5.6 RTC IO MUX I/O 5.6.1 5.6.2 5.7 Light-sleep 5.8 Pad Hold 5.9 I/O Pad 5.9.1 5.10 5.11 IO MUX Pad 5.12 RTC IO MUX 5.13 5.14 5.14.1 GPIO 5.14.2 IO MUX 5.14.3 SDM 5.14.4 GPIO 5.14.5 RTC IO MUX 5.15 5.15.1 GPIO 5.15.2 IO MUX 5.15.3 SDM 5.15.4 GPIO 5.15.5 RTC IO MUX
6
6.1 6.1.1 6.1.2
6.2 6.2.1 6.2.2 6.2.3 CPU 6.2.4 6.2.4.1 APB_CLK 6.2.4.2 REF_TICK
8
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161 162 162 162 162 163 163 164 165 165 165 165 165 165 166 166 166 166 167 171 172 173 174 174 175 176 177 177 178 178 190 191 193 201
215 215 215 216 216 216 217 218 219 219 220
ESP32-S2 TRM ( 1.3)
6.2.4.3 LEDC_PWM_CLK 6.2.4.4 APLL_SCLK 6.2.4.5 PLL_F160M_CLK 6.2.4.6 6.2.5 Wi-Fi 6.2.6 RTC 6.2.7 PLL 6.3 6.4
7 Boot (BOOTCTRL)
7.1 7.2 Boot 7.3 ROM 7.4 VDD_SPI
8
8.1 8.2 8.3
8.3.1 8.3.2 CPU 8.3.3 CPU
8.3.3.1 Source_X CPU 8.3.3.2 Source_Xn CPU 8.3.3.3 CPU Source_X 8.3.4 CPU NMI 8.3.5 8.4 8.5 8.6
9
9.1 9.2 9.3
9.3.1 9.3.2 9.3.3 9.3.4
9.3.4.1 9.3.4.2 9.3.4.3 Flash 9.3.4.4 9.4 9.4.1
9
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220 220 220 220 220 221 221 221 222
223 223 223 224 225
226 226 226 226 226 230 231 231 231 231 231 232 232 232 236
265 265 265 265 267 268 270 271 271 272 272 273 274 274
ESP32-S2 TRM ( 1.3)
9.4.2 RTC 9.4.3 9.4.4 9.4.5 9.5 RTC Boot 9.6 9.7 9.8
10 (SYSTIMER)
10.1 10.2 10.3 10.4
10.4.1 10.4.2 10.4.3 10.4.4 10.5 10.6 10.7
11 (TIMG)
11.1 11.2
11.2.1 16 11.2.2 64 11.2.3 11.2.4 11.2.5 11.3 11.3.1 11.3.2 11.3.3 11.4 11.5 11.6
12 (WDT)
12.1 12.2 12.3
12.3.1 32 12.3.2 12.3.3 12.3.4 Flash
10
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275 276 277 278 278 279 280 282
316 316 316 316 316 317 317 317 317 318 318 319
327 327 328 328 328 328 328 329 329 329 330 330 330 331 333
346 346 346 346 346 347 347 348
ESP32-S2 TRM ( 1.3)
12.4 12.4.1 12.4.2 SWD 12.4.2.1 12.4.2.2
12.5
13 XTAL32K (XTWDT)
13.1 13.2
13.2.1 XTAL32K 13.2.2 BACKUP32K_CLK 13.3 13.3.1 13.3.2 BACKUP32K_CLK
14 (PMS)
14.1 14.2 14.3
14.3.1 14.3.1.1 IBUS 14.3.1.2 DBUS0 14.3.1.3 DMA 14.3.1.4 PeriBus1 14.3.1.5 PeriBus2 14.3.1.6 Cache 14.3.1.7
14.3.2 14.3.2.1 Cache MMU 14.3.2.2
14.3.3 14.4 14.5 14.6
15
15.1 15.2 15.3
15.3.1 15.3.2 15.3.3 15.3.4 JTAG 15.3.5 15.3.6
11
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348 348 348 348 349 349
350 350 350 350 350 351 351 351
352 352 352 352 352 353 354 356 356 358 358 359 359 359 360 360 361 361 363
391 391 391 391 391 393 393 393 394 394
ESP32-S2 TRM ( 1.3)
15.4 15.5 15.6
IV
16 SHA (SHA)
16.1 16.2 16.3 16.4
16.4.1 16.4.2 16.4.3 16.4.4 (Initial Hash Value) 16.4.5 16.4.6 Typical SHA 16.4.7 DMA-SHA 16.4.8 16.4.9 16.5 16.6 16.7
17 AES (AES)
17.1 17.2 17.3 17.4 Typical AES
17.4.1 aa 17.4.2 17.4.3 Typical AES 17.5 DMA-AES 17.5.1 aa 17.5.2 17.5.3 17.5.4 17.5.5 17.5.6 17.5.7 GCM 17.6 GCM 17.6.1 cHash subkey 17.6.2 J0 17.6.3 cAuthenticated Tag 17.6.4 cAAD Block Number 17.6.5 (Remainder Bit Number)
12
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395 396 397
412
413 413 413 413 414 414 414 415 416 417 417 419 420 421 421 421 423
427 427 427 427 428 428 429 433 433 434 434 435 435 435 435 436 437 438 438 438 438 438
ESP32-S2 TRM ( 1.3)
17.7 17.8 17.9 17.10
18 RSA (AES)
18.1 18.2 18.3
18.3.1 18.3.2 18.3.3 18.3.4 18.4 18.5 18.6 18.7
19 HMAC (HMAC)
19.1 19.2 19.3
19.3.1 19.3.2 JTAG 19.3.3 19.3.4 HMAC eFuse 19.3.5 HMAC c 19.4 HMAC 19.4.1 19.4.2 HMAC 19.5 19.6 19.7
20 (DSA)
20.1 20.2 20.3
20.3.1 20.3.2 20.3.3 20.3.4 20.3.5 20.3.6 DS 20.4 20.5
13
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439 439 439 440
445 445 445 445 445 447 447 448 449 449 449 450
454 454 454 454 454 455 455 456 456 458 458 459 459 460 461
466 466 466 466 466 466 467 467 468 469 469 470
ESP32-S2 TRM ( 1.3)
20.6 20.7
21 (XTS_AES)
21.1 21.2 21.3
21.3.1 XTS 21.3.2 Key 21.3.3 21.3.4 21.3.5 21.3.6 21.3.7 21.4 21.5 21.6
22 (RNG)
22.1 22.2 22.3 22.4 22.5 22.6 22.7
V
23 UART (UART)
23.1 23.2 23.3
23.3.1 UART 23.3.2 UART 23.3.3 UART RAM 23.3.4
23.3.4.1 23.3.4.2 23.3.5 UART 23.3.6 AT_CMD 23.3.7 RS485 23.3.7.1 23.3.7.2 23.3.7.3 23.3.8 IrDA
14
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470 471
473 473 473 473 474 474 475 475 476 477 477 478 478 479
483 483 483 483 484 484 484 484
486
487 487 487 487 487 488 489 489 490 490 491 492 492 492 493 493 493
ESP32-S2 TRM ( 1.3)
23.3.9 23.3.10
23.3.10.1 23.3.10.2 23.3.11 UDMA 23.3.12 UART 23.3.13 UCHI 23.4 23.5 23.6
24 SPI (SPI)
24.1 24.2
24.2.1 GP-SPI2 24.2.1.1 GP-SPI2 24.2.1.2 GP-SPI2 24.2.1.3 GP-SPI2
24.2.2 GP-SPI3 24.2.2.1 GP-SPI3 24.2.2.2 GP-SPI3 24.2.2.3 GP-SPI3
24.2.3 SPI 24.3 SPI 24.4 GP-SPI2
24.4.1 24.4.2 24.4.3 c 1-bit 24.4.4 c 1/2/4/8-bit 24.4.5 Flash RAM 24.4.6 8-bit I8080/MT6800 LCD 24.4.7 DMA 24.4.8 8-bit RGB LCD 24.4.9 CS 24.5 GP-SPI2 24.5.1 24.5.2 CMD 24.5.3 24.5.4 24.6 GP-SPI2 GP-SPI3 24.7 CPU 24.7.1 CPU 24.7.2 CPU 24.8 DMA 24.9 GP-SPI 24.9.1 GP-SPI
15
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494 494 495 496 496 496 497 498 498 501
543 543 544 544 544 545 545 545 545 546 546 546 546 548 548 550 553 553 554 555 556 559 561 562 562 563 565 565 566 568 568 569 569 570 571
ESP32-S2 TRM ( 1.3)
24.9.2 GP-SPI 24.9.3 GP-SPI 24.9.4 GP-SPI 24.10 SPI 24.11 GP-SPI 24.11.1 GP-SPI 24.11.2 GP-SPI DMA 24.12 24.13 24.14
25 I2C (I2C)
25.1 25.2 I2C
25.2.1 I2C 25.2.2 I2C
25.2.2.1 TX/RX RAM 25.2.2.1.1 CMD_Controller 25.2.2.2 SCL_FSM 25.2.2.3 SCL_MAIN_FSM 25.2.2.4 DATA_Shifter 25.2.2.5 SCL_Filter SDA_Filter 25.2.3 I2C 25.3 25.3.1 I2C 7-bit 25.3.2 I2C 10-bit 25.3.3 I2C 7-bit 25.3.4 I2C 7-bit 25.3.5 I2C 7-bit 25.3.6 I2C 10-bit 25.3.7 I2C 7-bit 25.3.8 I2C 7-bit 25.3.9 SCL 25.4 25.5 25.6 25.7
26 I2S (I2S)
26.1 26.2 26.3 26.4 I2S
26.4.1 Philips 26.4.2 MSB 26.4.3 PCM
16
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571 572 573 573 573 575 575 576 576 578
616 616 616 616 617 618 618 619 619 620 620 620 621 621 623 623 624 625 625 626 627 627 628 628 629 630
651 651 651 653 654 654 654 655
ESP32-S2 TRM ( 1.3)
26.5 I2S 26.6 I2S 26.7 I2S /
26.7.1 / 26.7.2 / 26.8 26.8.1 I2S_TX_DMA_EQUAL = 0 26.8.2 I2S_TX_DMA_EQUAL = 1 26.8.3 I2S 26.9 26.9.1 I2S_RX_DMA_EQUAL = 0 26.9.2 I2S_RX_DMA_EQUAL = 1 26.9.3 I2S 26.10 LCD 26.10.1 26.10.2 LCD 26.11 Camera 26.11.1 26.11.2 Camera 26.12 I2S 26.12.1 FIFO 26.12.2 DMA 26.13 26.14 26.15
27 (PCNT)
27.1 27.2 27.3
27.3.1 0 27.3.2 0 27.3.3 0 1 27.4 27.5 27.6
28 USB OTG
28.1 28.2
28.2.1 28.2.2 (Device) 28.2.3 (Host) 28.3 28.3.1 28.3.2
17
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655 656 657 657 657 658 658 661 663 663 664 665 666 667 667 668 669 669 669 670 670 671 671 671 673
694 694 695 697 697 698 698 699 699 701
707 707 707 707 707 707 708 708 709
ESP32-S2 TRM ( 1.3)
28.3.2.1 & (CSR) 28.3.2.2 FIFO 28.3.3 FIFO 28.3.3.1 FIFO 28.3.3.2 FIFO 28.3.4 28.3.5 DMA Slave 28.3.5.1 Slave 28.3.5.2 DMA 28.3.5.3 Scatter/Gather DMA 28.3.6 28.3.6.1 DMA 28.3.6.2 Slave 28.4 OTG 28.4.1 ID 28.4.2 OTG 28.4.3 (SRP) 28.4.3.1 A SRP 28.4.3.2 B SRP 28.4.4 (HNP) 28.4.4.1 A HNP 28.4.4.2 B HNP 28.5 28.6
29 (TWAI)
29.1 29.2
29.2.1 TWAI 29.2.2 TWAI
29.2.2.1 29.2.2.2 29.2.2.3 29.2.3 TWAI 29.2.3.1 29.2.3.2 29.2.3.3 29.2.4 TWAI 29.2.4.1 29.2.4.2 29.3 29.3.1 29.3.2 29.3.3 29.3.4 29.3.5
18
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709 710 710 710 711 712 713 713 713 713 714 714 714 715 715 715 716 716 717 718 718 719 720 720
721 721 721 722 722 723 724 726 726 726 727 727 728 728 728 729 730 730 730 731 731
ESP32-S2 TRM ( 1.3)
29.3.6 FIFO 29.4
29.4.1 29.4.1.1 29.4.1.2
29.4.2 29.4.3
29.4.3.1 (RXI) 29.4.3.2 (TXI) 29.4.3.3 (EWI) 29.4.3.4 (DOI) 29.4.3.5 (TXI) 29.4.3.6 (ALI) 29.4.3.7 (BEI) 29.4.4 29.4.4.1 29.4.4.2 29.4.4.3 29.4.4.4 29.4.5 FIFO 29.4.6 29.4.6.1 29.4.6.2 29.4.7 29.4.7.1 29.4.7.2 29.4.7.3 29.4.8 29.4.9 29.5 29.6 29.7
30 LED PWM (LEDC)
30.1 30.2 30.3
30.3.1 30.3.2 30.3.3 PWM 30.3.4 30.3.5 30.4 30.5 30.6
19
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731 731 731 731 731 732 732 733 733 733 733 733 734 734 734 734 735 735 736 736 737 737 737 738 738 740 740 740 741 742 742 743
755 755 755 755 755 755 757 758 759 759 759 761
ESP32-S2 TRM ( 1.3)
31 (RMT)
31.1 31.2
31.2.1 RMT 31.2.2 RMT RAM 31.2.3 31.2.4 31.2.5 31.2.6 31.3 31.4 31.5
VI
32
32.1 32.2
32.2.1 32.2.2 32.2.3
32.2.3.1 32.2.3.2 ADC 32.2.4 RTC ADC 32.2.5 DIG ADC 32.2.5.1 DIG ADC 32.2.5.2 DMA 32.2.5.3 ADC 32.2.5.4 32.2.6 SAR ADC2 32.3 32.3.1 32.3.2 32.3.3 DAC 32.3.4 32.3.5 DMA 32.4 32.4.1 32.4.2 32.4.3 32.4.4 32.5 32.6 32.7 32.7.1 SENSOR (RTC_PERI) 32.7.2 SENSOR (DIG_PERI)
20
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767 767 767 767 768 769 769 770 770 770 770 772
781
782 782 782 782 783 784 784 785 785 786 786 788 788 788 789 790 790 790 790 790 791 792 792 792 792 793 793 793 794 794 794
ESP32-S2 TRM ( 1.3)
32.8
32.8.1 SENSOR (RTC_PERI) 32.8.2 SENSOR (DIG_PERI)
VII
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796 796 803
814
815
816 816 816 817
819 819 819
820
821
21
ESP32-S2 TRM ( 1.3)
1.2-1 1.5-1 1.5-2 1.5-3 1.5-4 1.5-5 1.5-6 1.6-1 1.6-2 1.8-1 1.8-2 1.9-1 1.9-2
ALU ALU ALU - - ADC ULP-RISC-V RTC I2C ULP
2.3-1 2.11-1
ablock size Copy DMA DMA
3.3-1 3.3-2 3.3-3 3.3-4 3.3-5 3.3-6
DMA / /
4.3-1 4.3-2 4.3-3 4.3-4 4.3-5 4.3-6 4.3-7 4.4-1
BLOCK0 BLOCK1-10 eFuse VDDQ eFuse eFuse
5.7-1 5.10-1 5.11-1 5.12-1 5.13-1
IO MUX Light-sleep GPIO IO MUX Pad RTC IO MUX
6.1-1 6.2-1 6.2-2 6.2-3 6.2-4 6.2-5
CPU_CLK CPU_CLK APB_CLK REF_TICK
22
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33 38 38 39 40 42 46 48 48 52 52 53 53
82 87
114 114 116 118 119 120
121 123 124 127 129 129 130 131
166 167 171 172 173
216 218 218 219 219 220
ESP32-S2 TRM ( 1.3)
6.2-6 LEDC_PWM_CLK
7.1-1 Strapping / 7.2-1 7.3-1 UART ROM
8.3-1 8.3-2 8.4-1
CPU aa CPU
9.3-1 9.3-2 9.3-3 9.4-1 9.4-2 9.4-3 9.6-1
RTC RTC
10.5-1
11.4-1 64
14.3-1 SRAM Block 14.3-2 IBUS SRAM 14.3-3 IBUS RTC FAST 14.3-4 DBUS0 SRAM 14.3-5 DBUS0 RTC FAST 14.3-6 DMA SRAM 14.3-7 FIFO 14.3-8 PeriBus1 14.3-9 PeriBus2 RTC SLOW 14.3-10 PMS_PRO_CACHE_1_REG 14.3-11 MMU 14.3-12 14.4-1
15.3-1 15.3-2 15.3-3 15.4-1
ROM SRAM
16.3-1 16.3-2 16.4-4 16.5-1
SHA
17.3-1 17.4-1 17.4-2
23
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220
223 223 224
227 230 232
270 270 274 276 276 277 280
318
331
352 353 354 355 355 356 357 357 358 359 360 361 361
392 392 394 396
414 414 420 421
428 428 428
ESP32-S2 TRM ( 1.3)
17.4-3 17.4-4 17.4-5 17.4-6 17.5-1 17.5-2 17.5-3 17.5-4 17.7-1 17.8-1
Typical AES AES-128 AES-192 AES-256 TEXT-PADDING DMA AES AES AES
18.3-1 18.4-1 18.5-1
RSA RSA
19.3-1 HMAC 19.5-1 HMAC
20.4-1 DS 20.5-1 DS
21.3-1 21.3-2 21.4-1
Key
22.5-1
23.4-1 UART0aUART1 UHCI
24.3-1 24.4-1 24.4-2 24.4-2 24.4-3 24.4-4 24.4-5 24.5-1 24.5-1 24.5-2 24.6-1 24.6-1 24.9-1 24.9-2 24.10-1 24.11-1 24.11-2 24.12-1
GP-SPI2 GP-SPI3 1/2-bit 4/8-bit 4/8-bit CONF GP-SPI CONF bufferi VS GP-SPI2 SPI CMD GP-SPI2 SPI CMD GP-SPI2 QPI CMD GP-SPI3 GP-SPI3 GP-SPI GP-SPI SPI GP-SPI GP-SPI SPI0aSPI1aGP-SPI2 GP-SPI3
25.5-1 I2C
24
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429 431 431 432 433 433 434 435 439 439
449 449 449
456 459
470 470
474 476 478
484
498
547 550 550 551 557 558 559 564 565 565 567 568 572 572 573 574 574 576
629
ESP32-S2 TRM ( 1.3)
26.2-1 26.8-1 26.8-2 26.8-3 26.9-1 26.9-2 26.13-1
I2S_TX_DMA_EQUAL = 0 I2S_TX_DMA_EQUAL = 1 I2S_RX_DMA_EQUAL = 0 I2S_RX_DMA_EQUAL = 1 ESP32-S2 I2S
27.2-1 27.2-2 27.2-3 27.2-4 27.4-1
PCNT
28.3-1 28.4-1 28.5-1
Slave IN OUT UTMI OTG USB
29.2-1 SFF EFF 29.2-2 29.2-3 29.2-4 29.2-5 29.4-1 TWAI_CLOCK_DIVIDER_REG bit ; TWAI 0x18 29.4-2 TWAI_BUS_TIMING_1_REG bit ; TWAI 0x1c 29.4-3 SFF EFF 29.4-4 TX/RX (SFF/EFF)TWAI 0x40 29.4-5 TX/RX 1 (SFF); TWAI 0x44 29.4-6 TX/RX 2 (SFF); TWAI 0x48 29.4-7 TX/RX 1 (EFF); TWAI 0x44 29.4-8 TX/RX 2 (EFF); TWAI 0x48 29.4-9 TX/RX 3 (EFF); TWAI 0x4c 29.4-10 TX/RX 4 (EFF); TWAI 0x50 29.4-11 TWAI_ERR_CODE_CAP_REG bit ; TWAI 0x30 29.4-12 SEG.4 - SEG.0 29.4-13 TWAI_ARB LOST CAP_REG ; TWAI 0x2c 29.5-1 TWAI
30.3-1 30.4-1 LED PWM
31.3-1 RMT
32.2-1 32.2-2 32.2-3 32.2-4 32.2-5
ADC SAR ADC I DMA II DMA
25
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652 660 661 662 665 666 671
696 696 696 696 699
714 715 720
724 725 725 726 728 732 732 734 735 735 735 735 735 736 736 740 741 741 742
757 759
770
784 784 787 788 788
ESP32-S2 TRM ( 1.3)
32.4-1 32.6-1 32.8-4 ENA/RAW/ST
GoBack
793 793 820
26
ESP32-S2 TRM ( 1.3)
1.1-1 1.2-1 1.3-1 1.4-1 1.4-2 1.5-1 1.5-2 1.5-3 1.5-4 1.5-5 1.5-6 1.5-7 1.5-8 1.5-9 1.5-10 1.5-11 1.5-12 1.5-13 1.5-14 1.5-15 1.5-16 1.5-17 1.5-18 1.5-19 1.5-20 1.7-1 1.7-2
ULP ULP ULP-FSM - ALU - ALU - ALU - ST - (ST-OFFSET) - (ST-AUTO-DATA) MEM[Rdst + Offset] - - LD - JUMP - JUMPR - JUMPS - HALT - WAKE - WAIT - TSENS - ADC - REG_RD - REG_WR I2C I2C
2.1-1 2.3-1 2.3-2 2.3-3 2.3-4 2.4-1 2.5-1 2.6-1
DMA DMA EDMA RAM Copy DMA UDMA SPI DMA
3.2-1 3.3-1
Cache
4.3-1 4.3-2 4.3-3 4.3-4
c 32 c 12 eFuse eFuse
27
GoBack
32 33 34 35 36 37 37 38 39 39 40 40 41 41 42 42 43 44 44 44 45 45 45 46 47 50 51
78 79 79 81 82 83 83 84
113 117
125 125 129 130
ESP32-S2 TRM ( 1.3)
5.1-1 5.2-1 5.2-2 5.4-1
IO MUXaRTC IO MUX GPIO GPIO clock GPIO GPIO
6.1-1 6.2-1
8.2-1
9.3-1 9.3-2 9.3-3 9.3-4 9.3-5 9.3-6 9.3-7 9.3-8 9.4-1 9.5-1
RTC RTC Flash RTC ESP32-S2
10.4-1
11.1-1
12.4-1
13.1-1 XTAL32K
17.6-1 GCM
19.4-1 HMAC 19.4-2 HMAC
20.3-1
21.3-1
22.3-1
23.3-1 UART 23.3-2 UART RAM 23.3-3 UART 23.3-4 UART 23.3-5 UART 23.3-6 AT_CMD 23.3-7 RS485 23.3-8 SIR 23.3-9 IrDA 23.3-10
28
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157 158 159 163
215 217
226
267 268 269 269 271 272 273 274 275 279
317
327
348
350
437
458 459
467
473
483
488 489 490 491 491 492 493 494 494 495
ESP32-S2 TRM ( 1.3)
GoBack
23.3-11
495
24.1-1 SPI
543
24.3-1 GP-SPI2/GP-SPI3
547
24.4-1 GP-SPI2
549
24.4-2 GP-SPI2 SPI
553
24.4-3 4-bit GP-SPI2 Flash RAM
554
24.4-4 GP-SPI2 Flash SPI Quad
555
24.4-5 GP-SPI2 8-bit LCD
555
24.4-6 8-bit LCD
556
24.4-7 DMA
556
24.4-8 RGB 8-bit LCD
560
24.4-9 RGB 8-bit LCD
560
24.4-10 GP-SPI2 RAM CS
561
24.4-11 GP-SPI2 Flash CS
562
24.7-1 CPU Buffer
568
24.9-1 SPI 0 2
571
24.9-2 SPI 1 3
572
25.2-1 I2C Master
617
25.2-2 I2C Slave
617
25.2-3 I2C
618
25.2-4 I2C
620
25.3-1 I2C Master 7-bit Slave
621
25.3-2 I2C Master 10-bit Slave
623
25.3-3 I2C Master 7-bit Slave M RAM
623
25.3-4 I2C Master 7-bit Slave
624
25.3-5 I2C Master 7-bit Slave
625
25.3-6 I2C Master 10-bit Slave
625
25.3-7 I2C Master 7-bit Slave M N
626
25.3-8 I2C Master 7-bit Slave
627
26.2-1 ESP32-S2 I2S
651
26.4-1 Philips
654
26.4-2 MSB
654
26.4-3 PCM
655
26.5-1 I2S
655
26.8-1 I2S_TX_DMA_EQUAL ESP32-S2 I2S
659
26.8-2 I2S_TX_CHAN_MOD[2:0] = 0 I2S_TX_DMA_EQUAL = 0 ESP32-S2 I2S
660
26.8-3 I2S_TX_DMA_EQUAL = 1 ESP32-S2 I2S
662
26.9-1 I2S_RX_DMA_EQUAL = 0 ESP32-S2 I2S
664
26.9-2 I2S_RX_DMA_EQUAL = 0 ESP32-S2 I2S
665
26.9-3 I2S_RX_DMA_EQUAL = 1 ESP32-S2 I2S
666
26.10-1 LCD
668
26.10-2 LCD 1
668
26.10-3 LCD 2
669
29
ESP32-S2 TRM ( 1.3)
26.11-1 Camera
27.0-1 27.2-1 27.3-1 27.3-2 27.3-3
PCNT PCNT 0 0
28.3-1 28.3-2 28.3-3 28.3-4 28.3-5 28.3-6 28.4-1 28.4-2 28.4-3 28.4-4
OTG_FS FIFO FIFO OTG_FS Scatter/Gather DMA A SRP B SRP A HNP B HNP
29.2-1 29.2-2 29.2-3 29.2-4 29.2-5 29.3-1 29.4-1 29.4-2 29.4-3 29.4-4 29.4-5
TWAI bit
30.3-1 30.3-2 30.3-3 30.3-4 30.3-5
LED_PWM LED_PWM LED_PWM LED_PWM
31.2-1 31.2-2 31.2-3
RMT RMT RAM
32.2-1 32.2-2 32.2-3 32.2-4 32.3-1 32.3-2 32.4-1
SAR ADC SAR ADC RTC ADC DIG ADC DAC
30
GoBack
669
694 695 697 698 698
708 709 711 711 712 713 716 717 718 719
723 725 725 726 728 729 737 738 739 739 742
756 756 757 758 758
767 768 768
783 784 785 787 791 791 792
ESP32-S2 TRM ( 1.3)
GoBack
I
a (DMA) b
31
ESP32-S2 TRM ( 1.3)
1 (ULP)
GoBack
1 (ULP)
1.1
(ULP, Ultra-Low-Power coprocessor) Deep-sleep c RTC RTC a RTC b CPU RTCIOaRTC I2CaSAR ADCa (TSENS) CPUb
Enable by ULP or Main CPU
ESP32-S2
Enable with RTC GPIO
ULP Timer
Wakeup
ULP
Wakeup
Main CPU
TSENS
RTC GPIO TOUCH ADC RTC I2C
Monitor / Control
1.1-1.
ESP32-S2 (FSM) ULP c ULP-FSM RISC-V ULP c ULP-RISC-Vb
1.2
· 8 KB SRAM RTC · 8 MHz RTC_FAST_CLK · Monitor
32
ESP32-S2 TRM ( 1.3)
1 (ULP)
GoBack
· CPU CPU · a RTC ULP-FSM ULP-RISC-V ESP32-S2 b ULP-FSM ULP-RISC-V
cRTC
Monitor
ULP-FSM
ULP-RISC-V
8 KB
8 MHz
ULP
CPU
ADC1/ADC2
DAC1/DAC2
RTC I2C
RTC GPIO
RISC-V
C
1.2-1.
ESP32-S2 RTC RTC b CPU CPU CPUbESP32-S2 1.2-1b
1.2-1.
33
ESP32-S2 TRM ( 1.3)
1 (ULP)
GoBack
1.3
ULP-RISC-V C RV32IMC bULP-RISC-V RV32IMC bULP-FSM ULP-FSM 1.5.2b
1.3-1.
1.4
ESP32-S2 CPU CPU b Deep-sleep b
1. RTC 2. RTC_CNTL_COCPU_SEL
· 0 ULP-RISC-V · 1 ULP-FSM 3. ULP-RISC-V RTC_CNTL_COCPU_CLK_FO 4. RTC_CNTL_ULP_CP_TIMER_1_REG 5. · RTC_CNTL_ULP_CP_SLP_TIMER_EN · RTC GPIO RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA RTC GPIO
b 9 b 6. CPU b Deep-sleep 1. Monitor
34
ESP32-S2 TRM ( 1.3)
1 (ULP)
2. b 3. Deep-sleep 4. b Monitor 1.4-1
GoBack
1.4-1. ULP
1. 2. b Run 3. HALT HALT b
· ULP-RISC-V HALT RTC_CNTL_COCPU_DONE · ULP-FSM HALT HALT b
4. Monitor b · RTC_CNTL_ULP_CP_SLP_TIMER_EN · RTC GPIO RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLRb b
ULP-RISC-V HALT RTC_CNTL_COCPU_DONE
· RTC_CNTL_COCPU_DONE ULP-RISC-V ULP-RISC-V · RTC_CNTL_COCPU_SHUT_RESET_EN ULP-RISC-Vb
ULP-RISC-V b 1.4-2b
35
ESP32-S2 TRM ( 1.3)
1 (ULP)
GoBack
1.4-2. ULP
1.5 ULP-FSM
1.5.1 ULP-FSM
ULP-FSM CPU Deep-sleep b CPU bULP-FSM RTC bULP-FSM 8 KB SRAM RTC cCPU b CPU bULP-FSM HALT b ULP-FSM
· 4 16 (R0 ~ R3)b · 1 8 Stage_cnt ALU JUMP b · SAR ADCb
1.5.2 ULP-FSM
ULP-FSM · ALU - · LDaSTaREG_RD REG_WR - · JUMP - · WAIT HALT - · WAKE - CPU CPU
36
ESP32-S2 TRM ( 1.3)
1 (ULP)
· TSENS ADC -
ULP-FSM 1.5-1b
OpCode
31
28 27
Operands
GoBack
0
1.5-1. ULP-FSM
Operands OpCode bALU 10 JUMP aab
ULP-FSM 32 bb 32 b 1 0x5000_0000 0x5000_1FFF (8 KB) CPU b
1.5.2.1 ALU -
(ALU) b
· - (ADD) (SUB)
· - (AND) (OR)
· - (LSH) (RSH)
· - (MOVE)
· - STAGE_RSTaSTAGE_INC STAGE_DEC
OpCode 7 [27:21] b
31
28 27 26 25 24
7
0
ALU_sel
21 20
Rsrc2 Rsrc1 Rdst
65
43
21
0
1.5-2. - ALU
1.5-2 [27:26] 0 ALU R[0-3] ALU_sel [24:21] 1.5-1b
Operand Rdst Rsrc1 Rsrc2 ALU_sel
- 1.5-2 R[0-3] R[0-3] R[0-3] ALU 1.5-1
37
ESP32-S2 TRM ( 1.3)
1 (ULP)
ALU_sel 0 1 2 3 4 5 6
ADD SUB AND OR MOVE LSH RSH
Rdst = Rsrc1 + Rsrc2 Rdst = Rsrc1 - Rsrc2 Rdst = Rsrc1 & Rsrc2 Rdst = Rsrc1 | Rsrc2 Rdst = Rsrc1 Rdst = Rsrc1 « Rsrc2 Rdst = Rsrc1 » Rsrc2
1.5-1. ALU
GoBack
· ADD SUB ALU b
· ALU ALU b
ALU_sel
Imm
31
28 27 26 25 24
21 20 19
7
1
1.5-3. - ALU
Rsrc1 Rdst
43
21
0
1.5-3 [27:26] 1 ALU R[0-3] [19:4] b ALU_sel [24:21] 1.5-2b
Operand Rdst Rsrc1 Imm ALU_sel
- 1.5-3 R[0-3] R[0-3] 16 ALU 1.5-2
ALU_sel 0 1 2 3 4 5 6
ADD SUB AND OR MOVE LSH RSH
Rdst = Rsrc1 + Imm Rdst = Rsrc1 - Imm Rdst = Rsrc1 & Imm Rdst = Rsrc1 | Imm Rdst = Imm Rdst = Rsrc1 « Imm Rdst = Rsrc1 » Imm
1.5-2. ALU
· ADD SUB ALU b · ALU ALU b
38
ESP32-S2 TRM ( 1.3)
1 (ULP)
ALU_sel
31
28 27 26 25 24
21 20
7
2
12 11
Imm
43
1.5-4. - ALU
GoBack
0
1.5-4 [27:26] 2 ALU 8 Stage_cnt a ALU_sel [24:21] 1.5-4bStage_cnt 1.5-4 b
Operand Imm ALU_sel Stage_cnt
- 1.5-4 8 ALU 1.5-4 8
ALU_sel 0 1 2
STAGE_INC STAGE_DEC STAGE_RST
Stage_cnt = Stage_cnt + Imm Stage_cnt = Stage_cnt - Imm Stage_cnt = 0
1.5-3. ALU
JUMPS for b
STAGE_RST
//
STAGE_INC
// ++
{...}
// n
JUMPS (step = n, cond = 0, threshold = m) // m STAGE_INC
m for b
1.5.2.2 ST -
manulo_fefsnetw_sr_eatuto
31
28 27 26 25 24
6
21 20
offset
wr_way upper label
Rsrc
Rdst
10 9 8
765
43
21
0
1.5-5. - ST
39
ESP32-S2 TRM ( 1.3)
1 (ULP)
GoBack
Operand Rdst Rsrc label upper wr_way offset wr_auto offset_set manul_en
- 1.5-5 R[0-3] 32 R[0-3] 16 2 01 01 label3 label 11 32 offset b01b
offset
31
28 27
25 24
21 20
10 9
0
6
3
1.5-6. - (ST-OFFSET)
Operand - 1.5-6 offset 11 32 b
31
28 27
25 24
6
1
wr_way
label
Rsrc
Rdst
98
765
43
21
0
1.5-7. - (ST-AUTO-DATA)
Operand Rdst Rsrc label wr_way
- 1.5-7 R[0-3] 32 R[0-3] 16 2 01 label3 label
ST-OFFSET ST-AUTO-DATA Rsrc 16 Rdst + Offset 1.5-4b ST-AUTO-DATA write_cnt b
wr_way 0 1 1 3 3
write_cnt *
Mem [Rdst + Offset]{31:0} ={PC[10:0], 3'b0, Label[1:0], Rsrc[15:0]} Mem [Rdst + Offset]{15:0} = {Label[1:0],Rscr[13:0]} Mem [Rdst + Offset]{31:16} = {Label[1:0],Rscr[13:0]} Mem [Rdst + Offset]{15:0} = Rscr[15:0] Mem [Rdst + Offset]{31:16} = Rscr[15:0]
label label label label
1.5-4. -
40
ESP32-S2 TRM ( 1.3)
1 (ULP)
GoBack
PC
31
21 20
label
18 17 16 15
0
Rsrc
0
1.5-8. MEM[Rdst + Offset]
[15:0] [17:16] [20:18] [31:21]
- 1.5-8 Rsrc 2 3'b0 PC 32
· ST-AUTO-DATAOffset 1b
· ST-AUTO-DATAOffset 1 b
· 32 b
· Mem RTC_SLOW_MEM ULP 0 CPU 0x50000000b
31
28 27
25 24
6
4
21 20
offset
wr_way upper label
Rsrc
Rdst
10 9 8
765
43
21
0
1.5-9. -
Operand Rdst Rsrc label upper wr_way offset
- 1.5-9 R[0-3] 32 R[0-3] 16 2 01 01 label3 label 11 32
b 1.5-5b
1.5.2.3 LD -
rd_upper
31
28 27 26
13
21 20
offset
10 9
Rsrc
Rdst
43
21
0
41
ESP32-S2 TRM ( 1.3)
1 (ULP)
GoBack
wr_way 0 1 1 3 3
upper * 0 1 0 1
Mem [ Rdst + Offset ]{31:0} ={PC[10:0], 3'b0, Label[1:0], Rsrc[15:0]} Mem [ Rdst + Offset ]{15:0} = {Label[1:0],Rscr[13:0]} Mem [ Rdst + Offset ]{31:16} = {Label[1:0],Rscr[13:0]} Mem [ Rdst + Offset ]{15:0} = Rsrc[15:0] Mem [ Rdst + Offset ]{31:16} = Rsrc[15:0]
label label label label
1.5-5. -
1.5-10. - LD
Operand Rdst Rsrc Offset rd_upper
- 1.5-10 R[0-3] R[0-3] 32 11 32 1 - 0 -
rd_upper Rsrc + Offset Rdst
Rdst[15:0] = Mem[Rsrc + Offset]
· 32 b · Mem RTC_SLOW_MEM ULP 0 CPU
0x50000000b
1.5.2.4 JUMP -
Type
Sel
31
28 27 26 25 24
22 21 20
8
1
13 12
1.5-11. - JUMP
ImmAddr
Rdst
21
0
42
ESP32-S2 TRM ( 1.3)
1 (ULP)
Operand Rdst ImmAddr Sel
Type
- 1.5-11 R[0-3] 11 32 0 - ImmAddr 1 - Rdst 0 - 1 - ALU 2 - ALU
32 b
ULP-FSM b
1.5.2.5 JUMPR - c R0
31
28 27 26 25
8
0
Step
Cond
18 17 16 15
Threshold
1.5-12. - JUMPR
GoBack
0
Operand Threshold Cond
Step
- 1.5-12 c Cond 0 - R0 < Threshold 1 - R0 > Threshold 2 - R0 = Threshold 32 Step[7] = 0 PC = PC + Step[6:0] Step[7] = 1 PC = PC - Step[6:0]
32 b
c R0 Threshold 1 b
43
ESP32-S2 TRM ( 1.3)
1 (ULP)
1.5.2.6 JUMPS - c
31
28 27 26 25
8
2
Step
Cond
18 17 16 15
Threshold
1.5-13. - JUMPS
GoBack
0
Operand Threshold Cond
Step
- 1.5-13 c Cond 1X - Stage_cnt <= Threshold 00 - Stage_cnt < Threshold 01 - Stage_cnt >= Threshold 32 Step[7] = 0 PC = PC + Step[6:0] Step[7] = 1 PC = PC - Step[6:0]
· 1.5.2.1 ALU b
· 32 b
c Stage_cnt Threshold 1 b
1.5.2.7 HALT -
31
28 27
0
11
1.5-14. - HALT
ULP-FSM b
ULP b
1.5.2.8 WAKE -
31
28 27 26 25
9
0
1.5-15. - WAKE
10
1'b1
44
ESP32-S2 TRM ( 1.3)
1 (ULP)
ULP-FSM RTC b
· Deep-sleep b
· Deep-sleep RTC_CNTL_INT_ENA_REG RTC_CNTL_ULP_CP_INT_ENA RTC b
1.5.2.9 WAIT -
31
28 27
4
16 15
Cycles
1.5-16. - WAIT
GoBack
0
Operand - 1.5-16 Cycles ULP-FSM b
1.5.2.10 TSENS -
31
28 27
10
16 15
Wait_Delay
1.5-17. - TSENS
Rdst
21
0
Operand Rdst Wait_Delay
- 1.5-17 R[0-3]
Wait_Delay b 1 b
1.5.2.11 ADC - ADC
31
28 27
5
1.5-18. - ADC
Sel
765
Sar_Mux
Rdst
21
0
45
ESP32-S2 TRM ( 1.3)
1 (ULP)
Operand Rdst Sar_Mux Sel
- 1.5-18 R[0-3]b SAR ADC [Sar_Mux - 1] 1.5-6b ADCb0 SAR ADC11 SAR ADC2 1.5-6b
1.5-6. ADC
/ / GPIO GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 XTAL_32k_P XTAL_32k_N DAC1 DAC2 GPIO19 GPIO20
Sar_Mux 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10
ADC cSel Sel = 0 SAR ADC1
Sel = 1 SAR ADC2
1.5.2.12 REG_RD -
31
28 27
2
High
23 22
Low
18 17
Addr
10 9
1.5-19. - REG_RD
GoBack
0
Operand Addr Low High
- 1.5-19 32
16 b
R0 = REG[Addr][High:Low]
46
ESP32-S2 TRM ( 1.3)
1 (ULP)
GoBack
16 High - Low + 1 > 16 [Low+15:Low] b
· RTC_CNTLaRTC_IOaSENS RTC_I2C bULP (addr_peribus1) addr_ulp = (addr_peribus1 - DR_REG_RTCCNTL_BASE) / 4
· addr_ulp 32 c0 DR_REG_RTCCNTL_BASEc CPU b 10 ULP 4096 DR_REG_RTCCNTL_BASEa DR_REG_RTCIO_BASEaDR_REG_SENS_BASE DR_REG_RTC_I2C_BASE b
1.5.2.13 REG_WR -
31
28 27
1
High
23 22
Low
18 17
Data
10 9
1.5-20. - REG_WR
Addr
0
Operand Addr Data Low High
- 1.5-20 32 8
8 (Data)b
REG[Addr][High:Low] = Data
8 High - Low + 1 > 8 8 0b addr_ulp 1.5.2.12 b
1.6 ULP-RISC-V
1.6.1 ULP-RISC-V
· RV32IMC · 32 32 · 32 ·
47
ESP32-S2 TRM ( 1.3)
1 (ULP)
GoBack
1.6.2
ULP-RISC-V 1.6-1.
MUL MULH MULHU MULHSU DIV DIVU REM REMU
34 66 66 66 34 34 34 34
32 32 32 32 32 32 32 32 32 32 32 32
1.6.3 ULP-RISC-V
ESP32-S2 a RTC I2C ULP-RISC-Vb SENS_SAR_COCPU_INT_ENA_REG 1.6-2
0 1 2 3 4 5 6 7 8
TOUCH_DONE_INT TOUCH_INACTIVE_INT TOUCH_ACTIVE_INT SARADC1_DONE_INT SARADC2_DONE_INT TSENS_DONE_INT RISCV_START_INT SW_INT SWD_INT
SAR ADC1 SAR ADC2 ULP-RISC-V
1.6-2. ULP-RISC-V
· ULP-RISC-V RTC_IO RTC_IO b RTCIO_GPIO_PINn_INT_TYPE b RTC_IO IO MUX GPIO b
· RTC_IO RTCIO_RTC_GPIO_STATUS_INT RTC_IO b
· RTC_CNTL_COCPU_SW_INT_TRIGGER b · RTC I2C 1.7.4b · 0x10 0x0b ULP-RISC-V 1. PC Q0
48
ESP32-S2 TRM ( 1.3)
1 (ULP)
GoBack
2. Q1
3. (0x10)
Q2 Q3 b retirq Q0bULP retirq b
1.7 RTC I2C
ULP RTC I2C I2C b
1.7.1 RTC I2C
SDA SCL RTCIO_SAR_I2C_IO_REG 2 GPIO c4 IO MUX GPIO RTC_MUX b
1.7.2 RTC I2C
ULP I2C RTC I2C RTC I2C b CPU ULP b
1. RTC_I2C_SCL_LOW_PERIOD_REG RTC_I2C_SCL_HIGH_PERIOD_REG RTC_FAST_CLK SCL c 100 kHz RTC_I2C_SCL_LOW_PERIOD_REG = 40aRTC_I2C_SCL_HIGH_PERIOD_REG = 40b
2. RTC_FAST_CLK RTC_I2C_SDA_DUTY_REG SDA c RTC_I2C_SDA_DUTY_REG = 16b
3. RTC_I2C_SCL_START_PERIOD_REG c RTC_I2C_SCL_START_PERIOD_REG = 30b
4. RTC_I2C_SCL_STOP_PERIOD_REG c RTC_I2C_SCL_STOP_PERIOD_REG = 44b
5. RTC_I2C_TIME_OUT_REG cRTC_I2C_TIME_OUT_REG = 200b 6. RTC_I2C_CTRL_REG RTC_I2C_MS_MODE b 7.
· CPU ULP-RISC-V SENS_SAR_I2C_SLAVE_ADDRb · ULP-FSM SENS_I2C_SLAVE_ADDRn (n: 0-7)b 8 b 1 I2C b RTC I2C CPU I2C b
1.7.3 RTC I2C
49
ESP32-S2 TRM ( 1.3)
1 (ULP)
GoBack
1.7.3.1 I2C
RTC I2C I2C0/I2C1 c I2C CMD_Controllerb RTC I2C
· 0 ~ 1I2C · 2 ~ 6I2C 7 b
1.7.3.2 I2C_RD - I2C
I2C · I2C a (byte_num) b I2C I2C0/I2C1 b · SENS_SAR_I2C_REG_ADDR b · SENS_SAR_I2C_START_FORCE SENS_SAR_I2C_START I2C b · RTC_I2C_RX_DATA_INT (RTC_I2C_RDATA) SRAM RTC b
I2C_RD 1.7-1 1. (START) 2. /c/ 0opb SENS_I2C_SLAVE_ADDRn 3. (ACK) 4. 5. 6. (RSTART) 7. / 1op 8. 1 9. b b 8b
10. (STOP) b
START ACK ACK
RSTRT NACK STOP
Master Slave
1
2
3
4
56
7
Slave Address W
Reg Address
Slave Address R
1.7-1. I2C
8
9 10
Data(n)
RTC I2C SCL SDA b SDA 0.38 ms b
50
ESP32-S2 TRM ( 1.3)
1 (ULP)
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1.7.3.3 I2C_WR - I2C
I2C · I2C a (byte_num) b I2C I2C0/I2C1 · SENS_SAR_I2C_REG_ADDR · hyperref[fielddesc:SENSSARI2CWDATA]SENS_SAR_I2C_WDATA · SENS_SAR_I2C_START_FORCE SENS_SAR_I2C_START I2C · RTC_I2C_TX_DATA_INT (SENS_SAR_I2C_WDATA)b
I2C_WR 1.7-2 1. 2. /c/ 0opb SENS_I2C_SLAVE_ADDRn 3. 4. 5. 6. 7. / 0op 8. 1 9. b 8
10. b
START ACK ACK
RSTRT ACK
STOP
Master Slave
1
2
3
4
56
7
Slave Address W
Reg Address
Slave Address W
8 Data(n)
9 10
1.7-2. I2C
1.7.3.4
RTC_I2C_INT_ST_REG b RTC_I2C_INT_ENA_REG b 1b RTC_I2C_INT_ST_REG RTC_I2C_INT_CLR_REG b
1.7.4 RTC I2C
· RTC_I2C_SLAVE_TRAN_COMP_INTb · RTC_I2C_ARBITRATION_LOST_INTb
51
ESP32-S2 TRM ( 1.3)
1 (ULP)
· RTC_I2C_MASTER_TRAN_COMP_INTb · RTC_I2C_TRANS_COMPLETE_INT STOP b · RTC_I2C_TIME_OUT_INTb · RTC_I2C_ACK_ERR_INT ACK b · RTC_I2C_RX_DATA_INTb · RTC_I2C_TX_DATA_INTb · RTC_I2C_DETECT_START_INTb
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1.8
1.8.1
1.8-1 b 3 b
1.8-1.
ULP (ALWAYS_ON) ULP (RTC_PERI)
PeriBUS1 PeriBUS2 PeriBUS1 PeriBUS2
0x3F408000 0x60008000 0x3F408800 0x60008800
· ULP(ALWAYS_ON) RTC_PERI c 9 b
· ULP(RTC_PERI) RTC_PERI RTC_PERI c 9 b
1.8.2 RTC I2C
RTC I2C RTC_PERI I2C RTC_PERI b 1.8-2 b 3 b
1.8-2. RTC I2C
RTC I2C (RTC_PERI) RTC I2C (I2C)
PeriBUS1 PeriBUS2 PeriBUS1 PeriBUS2
0x3F408800 0x60008800 0x3F408C00 0x60008C00
52
ESP32-S2 TRM ( 1.3)
1 (ULP)
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1.9
1.9-1 ULP b
1.9-1.
RTC Control RTC GPIO ADC, Touch, TSENS RTC I2C
DR_REG_RTCCNTL_BASE DR_REG_RTC_IO_BASE DR_REG_SENS_BASE DR_REG_RTC_I2C_BASE
0x3F408000 0x3F408400 0x3F408800 0x3F408C00
ULP-FSM 0x8000 0x8400 0x8800 0x8C00
ULP-RISC-V 0x8000 0xA400 0xC800 0xEC00
1.9-2 ULP b
1.9-2. ULP
RTC CNTL RTC GPIO ARCaTouchaTSENS RTC I2C
9 5 IO MUX GPIO 32 1.10
1.10
cb 1.8 b
1.10.1 ULP (ALWAYS_ON)
ULP RTC_CNTL_ULP_CP_TIMER_REG RTC_CNTL_ULP_CP_TIMER_1_REG ULP-FSM RTC_CNTL_ULP_CP_CTRL_REG ULP-RISC-V RTC_CNTL_COCPU_CTRL_REG
ULP-FSM ULP-RISC-V
0x00F8 0x0130 /
0x00FC /
0x0100
1.10.2 ULP (RTC_PERI)
ULP-RISC-V SENS_ SAR_COCPU_INT_RAW_REG SENS_SAR_COCPU_INT_ENA_REG
ULP-RISC-V ULP-RISC-V
0x0128 0x012C /
53
ESP32-S2 TRM ( 1.3)
1 (ULP)
SENS_SAR_COCPU_INT_ST_REG SENS_SAR_COCPU_INT_CLR_REG
ULP-RISC-V ULP-RISC-V
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0x0130 0x0134
1.10.3 RTC I2C (RTC_PERI)
RTC I2C SENS_SAR_I2C_CTRL_REG RTC I2C SENS_SAR_SLAVE_ADDR1_REG SENS_SAR_SLAVE_ADDR2_REG SENS_SAR_SLAVE_ADDR3_REG SENS_SAR_SLAVE_ADDR4_REG
RTC I2C
RTC I2C 0-1 RTC I2C 2-3 RTC I2C 4-5 RTC I2C 6-7
0x0058 /
0x0040 0x0044 0x0048 0x004C
/ / / /
1.10.4 RTC I2C (I2C)
RTC I2C RTC_I2C_SCL_LOW_REG RTC_I2C_SCL_HIGH_REG RTC_I2C_SDA_DUTY_REG RTC_I2C_SCL_START_PERIOD_REG
RTC_I2C_SCL_STOP_PERIOD_REG
RTC I2C RTC_I2C_CTRL_REG RTC_I2C_STATUS_REG RTC_I2C_TO_REG RTC_I2C_SLAVE_ADDR_REG RTC I2C RTC_I2C_INT_CLR_REG RTC_I2C_INT_RAW_REG RTC_I2C_INT_ST_REG RTC_I2C_INT_ENA_REG RTC I2C RTC_I2C_DATA_REG RTC I2C RTC_I2C_CMD0_REG RTC_I2C_CMD1_REG RTC_I2C_CMD2_REG RTC_I2C_CMD3_REG
SCL SCL SCL SDA SDA SCL SDA SCL
0x0000 0x0014 0x0018 0x001C
0x0020
/ / / /
/
RTC I2C RTC I2C
0x0004 0x0008 0x000C 0x0010
/ / /
RTC I2C RTC I2C RTC I2C RTC I2C
0x0024 0x0028 0x002C 0x0030
/
RTC I2C (RDDATA)
0x0034
RTC I2C 0 RTC I2C 1 RTC I2C 2 RTC I2C 3
0x0038 0x003C 0x0040 0x0044
54
ESP32-S2 TRM ( 1.3)
1 (ULP)
RTC_I2C_CMD4_REG RTC_I2C_CMD5_REG RTC_I2C_CMD6_REG RTC_I2C_CMD7_REG RTC_I2C_CMD8_REG RTC_I2C_CMD9_REG RTC_I2C_CMD10_REG RTC_I2C_CMD11_REG RTC_I2C_CMD12_REG RTC_I2C_CMD13_REG RTC_I2C_CMD14_REG RTC_I2C_CMD15_REG RTC_I2C_DATE_REG
RTC I2C 4 RTC I2C 5 RTC I2C 6 RTC I2C 7 RTC I2C 8 RTC I2C 9 RTC I2C 10 RTC I2C 11 RTC I2C 12 RTC I2C 13 RTC I2C 14 RTC I2C 15
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0x0048 0x004C 0x0050 0x0054 0x0058 0x005C 0x0060 0x0064 0x0068 0x006C 0x0070 0x0074
0x00FC /
1.11
cb 1.8 b
1.11.1 ULP (ALWAYS_ON)
Register 1.1. RTC_CNTL_ULP_CP_TIMER_REG (0x00F8)
RTC_CRNTCT_L_CRUNTLCTP_L__CCUNPLTP_LS__CLUPPL_P_TG_IMCPPIEO_R_G_WPEAINOK_EWUPA_KCEULRP_ENA
31 30 29 28
(reserved)
11 10
0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RTC_CNTL_ULP_CP_PC_INIT
0
0
Reset
RTC_CNTL_ULP_CP_PC_INIT ULP PC bc/ RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA RTC GPIO ULP bc/
RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR RTC GPIO ULP bc
RTC_CNTL_ULP_CP_SLP_TIMER_EN ULP b01 bc/
55
ESP32-S2 TRM ( 1.3)
1 (ULP)
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Register 1.2. RTC_CNTL_ULP_CP_TIMER_1_REG (0x0130)
RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE
(reserved)
31
87
0
200
0 0 0 0 0 0 0 0 Reset
RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE ULP bc/
Register 1.3. RTC_CNTL_ULP_CP_CTRL_REG (0x00FC)
RTC_CRNTCT_L_CRUNTLCTP_L__CRCUNTPLCTP__LS__CTCUNAPLTRP_LT_F__OCUTPRLOPC_P_REC_ESSPTE_ATCRLTK__TFOOP
(reserved)
31 30 29 28 27
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_CNTL_ULP_CP_CLK_FO ULP-FSM bc/ RTC_CNTL_ULP_CP_RESET ULP-FSM bc/ RTC_CNTL_ULP_CP_FORCE_START_TOP 1 ULP-FSM bc/ RTC_CNTL_ULP_CP_START_TOP 1 ULP-FSMbc/
56
ESP32-S2 TRM ( 1.3)
1 (ULP)
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Register 1.4. RTC_CNTL_COCPU_CTRL_REG (0x0100)
(reserved)
RTC_CRNTCT_L_CRCNTOCT_CL_CRPCNTUOCT__CLS_CRPWCNTU_OCT_IN_CLD_CTPOC_NUNTOT_ERCLDI_GPOCUGNO_EECRS_PEFLUO_RSCHEURTT_CR_ECSNETT_L_ECNOCPU_SHURTT_C2__CCNLKT_L_DCISOCPUR_TSCH_UCTNTL_COCPU_START_2_INRTTRC__ECNNTL_COCPUR_TSCTA_RCTN_T2L__RCEOSCEPTU__DCISLK_FO
31
27 26 25 24 23 22 21
14 13 12
76
10
0 0 0 0 00 0 0 1 0
40
0
16
8
0 Reset
RTC_CNTL_COCPU_CLK_FO ULP-RISC-V bc/ RTC_CNTL_COCPU_START_2_RESET_DIS ULP-RISC-V bc/ RTC_CNTL_COCPU_START_2_INTR_EN ULP-RISC-V RISCV_START_INT
bc/ RTC_CNTL_COCPU_SHUT ULP-RISC-Vbc/ RTC_CNTL_COCPU_SHUT_2_CLK_DIS ULP-RISC-V bc/ RTC_CNTL_COCPU_SHUT_RESET_EN ULP-RISC-Vbc/ RTC_CNTL_COCPU_SEL b0 ULP-RISC-V1 ULP-
FSMbc/ RTC_CNTL_COCPU_DONE_FORCE 0 ULP-FSM 1 ULP-RISC-V
bc/ RTC_CNTL_COCPU_DONE DONE 1 ULP-RISC-V HALT
bc/ RTC_CNTL_COCPU_SW_INT_TRIGGER ULP-RISC-V bc
57
ESP32-S2 TRM ( 1.3)
1 (ULP)
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1.11.2 ULP (RTC_PERI)
Register 1.5. SENS_ SAR_COCPU_INT_RAW_REG (0x0128)
(reserved)
SENS_SCENOSC_SPCEUNO_SCS_SPWCEUDNO__SCSI_SNPWCETU_NO__INSCRS_STATPCAEW_URNOR_TSTAC_WS_SPICEEUNNNO_TSSCS___PARSCIRUAENONAW_TSCDS__CPARSCRU2EAONA__WCTSDIPNO_CUCTU1_O__TCCRIOHNPAU_TUWCA__HTCR_OTAIUNIWVCAECH_T_IIDVNOET_N_IENR_TAI_NWRTA_WRAW
31
98 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SENS_COCPU_TOUCH_DONE_INT_RAW TOUCH_DONE_INT bc SENS_COCPU_TOUCH_INACTIVE_INT_RAW TOUCH_INACTIVE_INT bc SENS_COCPU_TOUCH_ACTIVE_INT_RAW TOUCH_ACTIVE_INT bc SENS_COCPU_SARADC1_INT_RAW SARADC1_DONE_INT bc SENS_COCPU_SARADC2_INT_RAW SARADC2_DONE_INT bc SENS_COCPU_TSENS_INT_RAW TSENS_DONE_INT bc SENS_COCPU_START_INT_RAW RISCV_START_INT bc SENS_COCPU_SW_INT_RAW SW_INT bc SENS_COCPU_SWD_INT_RAW SWD_INT bc
58
ESP32-S2 TRM ( 1.3)
1 (ULP)
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Register 1.6. SENS_SAR_COCPU_INT_ENA_REG (0x012C)
(reserved)
SENS_SCENOSC_SPCEUNO_SCS_SPWCEUDNO__SCSI_SNPWCETU_NO__INSCES_SNTTPCAE_AURNOE_TNSTC_S_SAPICEEUNNNO_TSSCS___PAESCIRUNENONA_ATSCDS__PCAESCRU2ENONA__ACTSDIPNO_CUCTU1_O__TCCEIOHNPNU_TUACA__HTCE_ONTIUNIAVCAECH_T_IIDVNOET_N_IENE_TNI_NAETN_AENA
31
98 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SENS_COCPU_TOUCH_DONE_INT_ENA TOUCH_DONE_INT bc/ SENS_COCPU_TOUCH_INACTIVE_INT_ENA TOUCH_INACTIVE_INT bc/ SENS_COCPU_TOUCH_ACTIVE_INT_ENA TOUCH_ACTIVE_INT bc/ SENS_COCPU_SARADC1_INT_ENA SARADC1_DONE_INT bc/ SENS_COCPU_SARADC2_INT_ENA SARADC2_DONE_INT bc/ SENS_COCPU_TSENS_INT_ENA TSENS_DONE_INT bc/ SENS_COCPU_START_INT_ENA RISCV_START_INT bc/ SENS_COCPU_SW_INT_ENA SW_INT bc/ SENS_COCPU_SWD_INT_ENA SWD_INT bc/
59
ESP32-S2 TRM ( 1.3)
1 (ULP)
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Register 1.7. SENS_SAR_COCPU_INT_ST_REG (0x0130)
(reserved)
SENS_SCENOSC_SPCEUNO_SCS_SPWCEUDNO__SCSI_SNPWCETU_NO__INSSCS_TSTTPCAE_URNOS_TTSTC_S_SPICEEUNNNO_TSSCS___SPASCIETRUNNOA_TSCDS__PCASSCRU2TEONA__TSCDINO_CPCTUU1O__C_SCITHNTPO_TUUA__TCCSOTHTUI_VCIENH__AIDCNOTTNI_VESE_T_ININT_TS_TST
31
98 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SENS_COCPU_TOUCH_DONE_INT_ST TOUCH_DONE_INT c SENS_COCPU_TOUCH_INACTIVE_INT_ST TOUCH_INACTIVE_INT c SENS_COCPU_TOUCH_ACTIVE_INT_ST TOUCH_ACTIVE_INT c SENS_COCPU_SARADC1_INT_ST SARADC1_DONE_INT c SENS_COCPU_SARADC2_INT_ST SARADC2_DONE_INT c SENS_COCPU_TSENS_INT_ST TSENS_DONE_INT c SENS_COCPU_START_INT_ST RISCV_START_INT c SENS_COCPU_SW_INT_ST SW_INT c SENS_COCPU_SWD_INT_ST SWD_INT c
60
ESP32-S2 TRM ( 1.3)
1 (ULP)
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Register 1.8. SENS_SAR_COCPU_INT_CLR_REG (0x0134)
(reserved)
SENS_SCENOSC_SPCEUNO_SCS_SPWCEUDNO__SCSI_SNPWCETU_NO__INSCCS_STLTPCARE_URNCO_TSTLC_RS_SPICEEUNNNO_TSSCS___PCASCIRULENORNA_TSCDS__PCACSCRU2ELONA_R_CTSDIPNO_CUCTU1_O__TCCCIOHNPLU_TURCA__HTCC_OTLIUNRIVCAECH_T_IIDVNOET_N_IENC_TLI_NRCTL_RCLR
31
98 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SENS_COCPU_TOUCH_DONE_INT_CLR TOUCH_DONE_INT c SENS_COCPU_TOUCH_INACTIVE_INT_CLR TOUCH_INACTIVE_INT c SENS_COCPU_TOUCH_ACTIVE_INT_CLR TOUCH_ACTIVE_INT c SENS_COCPU_SARADC1_INT_CLR SARADC1_DONE_INT c SENS_COCPU_SARADC2_INT_CLR SARADC2_DONE_INT c SENS_COCPU_TSENS_INT_CLR TSENS_DONE_INT c SENS_COCPU_START_INT_CLR RISCV_START_INT c SENS_COCPU_SW_INT_CLR SW_INT c SENS_COCPU_SWD_INT_CLR SWD_INT c
61
ESP32-S2 TRM ( 1.3)
1 (ULP)
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1.11.3 RTC I2C (RTC_PERI)
Register 1.9. SENS_SAR_I2C_CTRL_REG (0x0058)
(reservedS)ENS_SSEANRS__SISE2ANCRS___SIST2AACRR__TS_IT2FACOR_RTWCRE_EN SENS_SAR_I2C_WDATA
31 30 29 28 27 26
19 18
0 00 0 0
0
SENS_SAR_I2C_REG_ADSDERNS_SAR_I2C_SLAVE_ADDRS_1E0NBSIT__SAENR_I2C_SLAVE_ADDR
11 10 9
0
0
0
0
Reset
SENS_SAR_I2C_SLAVE_ADDR bc/
SENS_SAR_I2C_SLAVE_ADDR_10BIT_EN 10 b 0 1
c/
SENS_SAR_I2C_REG_ADDR bc/
SENS_SAR_I2C_WDATA bc/
SENS_SAR_I2C_WR_EN b 0 1
c/
SENS_SAR_I2C_START RTC I2C SENS_SAR_I2C_START_FORCE = 1 bc/
SENS_SAR_I2C_START_FORCE RTC I2C b0 FSM 1bc/
Register 1.10. SENS_SAR_SLAVE_ADDR1_REG (0x0040)
(reserved)
31
22 21
0000000000
SENS_I2C_SLAVE_ADDR0
11 10
0x0
SENS_I2C_SLAVE_ADDR1
0
0x0
Reset
SENS_I2C_SLAVE_ADDR1 RTC I2C 1bc/ SENS_I2C_SLAVE_ADDR0 RTC I2C 0bc/
62
ESP32-S2 TRM ( 1.3)
1 (ULP)
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Register 1.11. SENS_SAR_SLAVE_ADDR2_REG (0x0044)
(reserved)
31
22 21
0000000000
SENS_I2C_SLAVE_ADDR2
11 10
0x0
SENS_I2C_SLAVE_ADDR3
0
0x0
Reset
SENS_I2C_SLAVE_ADDR3 RTC I2C 3bc/ SENS_I2C_SLAVE_ADDR2 RTC I2C 2bc/
Register 1.12. SENS_SAR_SLAVE_ADDR3_REG (0x0048)
(reserved)
31
22 21
0000000000
SENS_I2C_SLAVE_ADDR4
11 10
0x0
SENS_I2C_SLAVE_ADDR5
0
0x0
Reset
SENS_I2C_SLAVE_ADDR5 RTC I2C 5bc/ SENS_I2C_SLAVE_ADDR4 RTC I2C 4bc/
Register 1.13. SENS_SAR_SLAVE_ADDR4_REG (0x004C)
(reserved)
31
22 21
0000000000
SENS_I2C_SLAVE_ADDR6
11 10
0x0
SENS_I2C_SLAVE_ADDR7
0
0x0
Reset
SENS_I2C_SLAVE_ADDR7 RTC I2C 7bc/ SENS_I2C_SLAVE_ADDR6 RTC I2C 6bc/
63
ESP32-S2 TRM ( 1.3)
1 (ULP)
1.11.4 RTC I2C (I2C)
Register 1.14. RTC_I2C_SCL_LOW_REG (0x0000)
(reserved)
31
20 19
000000000000
RTC_I2C_SCL_LOW_PERIOD_REG 0x100
RTC_I2C_SCL_LOW_PERIOD_REG SCL bc/
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0
Reset
Register 1.15. RTC_I2C_SCL_HIGH_REG (0x0014)
(reserved)
31
20 19
000000000000
RTC_I2C_SCL_HIGH_PERIOD_REG 0x100
RTC_I2C_SCL_HIGH_PERIOD_REG SCL bc/
0
Reset
Register 1.16. RTC_I2C_SDA_DUTY_REG (0x0018)
(reserved)
31
20 19
000000000000
RTC_I2C_SDA_DUTY_NUM 0x010
RTC_I2C_SDA_DUTY_NUM SCL SDA bc/
0
Reset
64
ESP32-S2 TRM ( 1.3)
1 (ULP)
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Register 1.17. RTC_I2C_SCL_START_PERIOD_REG (0x001C)
(reserved)
31
20 19
000000000000
RTC_I2C_SCL_START_PERIOD 8
0
Reset
RTC_I2C_SCL_START_PERIOD RTC I2C START SDA SCL bc/
Register 1.18. RTC_I2C_SCL_STOP_PERIOD_REG (0x0020)
(reserved)
31
20 19
000000000000
RTC_I2C_SCL_STOP_PERIOD 8
0
Reset
RTC_I2C_SCL_STOP_PERIOD RTC I2C STOP SDA SCL bc/
65
ESP32-S2 TRM ( 1.3)
1 (ULP)
GoBack
Register 1.19. RTC_I2C_CTRL_REG (0x0004)
(reserRvTeCd_) IR2TCC__RI2ESCE_TCTRL_CLK_GATE_EN
31 30 29 28
(reserved)
RTC_IR2TCC__RIR2XT_CCL__STIRXB2T__CCLF_S_ITRBIRR2S_TACTCFN_I_SRMIR_S2STTSC_CT_MA_SRIO2CTDCL_E_FSODRAC_EFO_ORUCTE_OUT
65 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_I2C_SDA_FORCE_OUT SDA b01bc/ RTC_I2C_SCL_FORCE_OUT SCL b01bc/ RTC_I2C_MS_MODE RTC I2C b RTC_I2C_TRANS_START RTC I2C bc/ RTC_I2C_TX_LSB_FIRST b01
bc/ RTC_I2C_RX_LSB_FIRST b01
bc/ RTC_I2C_CTRL_CLK_GATE_EN RTC I2C bc/ RTC_I2C_RESET RTC I2C bc/
66
ESP32-S2 TRM ( 1.3)
1 (ULP)
GoBack
Register 1.20. RTC_I2C_STATUS_REG (0x0008)
(reserved)
RTC_I2CR_TOCP__IR2CTCNC_T_BIR2YTTCCE___STIR2LRTACCAV_N_EBSI_R2UTACSCD___DABIRR2RUTECBSCS__Y_SSLIEO2LDACSVT_EA_CRKW_REC
31
87
65 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_I2C_ACK_REC ACK b0ACK1NACKbc RTC_I2C_SLAVE_RW 01bc RTC_I2C_ARB_LOST RTC I2C SCL 1bc RTC_I2C_BUS_BUSY 0RTC I2C 1RTC I2C bc RTC_I2C_SLAVE_ADDRESSED bc RTC_I2C_BYTE_TRANS 1bc RTC_I2C_OP_CNT bc
Register 1.21. RTC_I2C_TO_REG (0x000C)
(reserved)
31
20 19
000000000000
RTC_I2C_TIME_OUT_REG 0x10000
RTC_I2C_TIME_OUT_REG bc/
0
Reset
Register 1.22. RTC_I2C_SLAVE_ADDR_REG (0x0010)
RTC_I2C_ADDR_10BIT_EN
(reserved)
31 30
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_I2C_ADDR_10BIT_EN 10 bc/
67
ESP32-S2 TRM ( 1.3)
1 (ULP)
GoBack
Register 1.23. RTC_I2C_INT_CLR_REG (0x0024)
(reserved)
RTC_IR2TCC__DIR2ETCTCE__TCIRXT2T__CCDS__ATRTAIR2XART_C_TCD_I__NAAIIRTTN2CAT_TCKC_C___I_LCTNERIRILR2TMTRR_CCEC____TILNOIRRR2TUTAC_CTN_C__SMLII_N2RRACTCTSCO__T_MCAEI2LRRPCRB_L_TIETSRTLRAEAANV_TE_IINO_CTTNOR__AMCNLLPO_R_CSIOTNM_TIP_N_CTINL_RTC_LCRLR
31
98 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_I2C_SLAVE_TRAN_COMP_INT_CLR RTC_I2C_SLAVE_TRAN_COMP_INT c RTC_I2C_ARBITRATION_LOST_INT_CLR RTC_I2C_ARBITRATION_LOST_INT c RTC_I2C_MASTER_TRAN_COMP_INT_CLR RTC_I2C_MASTER_TRAN_COMP_INT c
RTC_I2C_TRANS_COMPLETE_INT_CLR RTC_I2C_TRANS_COMPLETE_INT c RTC_I2C_TIME_OUT_INT_CLR RTC_I2C_TIME_OUT_INT c RTC_I2C_ACK_ERR_INT_CLR RTC_I2C_ACK_ERR_INT c RTC_I2C_RX_DATA_INT_CLR RTC_I2C_RX_DATA_INT c RTC_I2C_TX_DATA_INT_CLR RTC_I2C_TX_DATA_INT c RTC_I2C_DETECT_START_INT_CLR RTC_I2C_DETECT_START_INT c
68
ESP32-S2 TRM ( 1.3)
1 (ULP)
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Register 1.24. RTC_I2C_INT_RAW_REG (0x0028)
(reserved)
RTC_IR2TCC__DIR2ETCTCE__TCIRXT2T__CCDS__ATRTAIR2XART_C_TCD_I__NAAIIRTTN2CAT_TCKC_R___I_ATRNEWIRIAR2TMTWR_CCE_R___TIANOIRRW2TUTAC_CTN_R__SMAII_N2RWACTCTSCO__T_MRAEI2ARRPCWB_L_TIETSRTLRAEAANV_TE_IINO_CTTNOR__AMRNLAPO_W_CSIOTNM_TIP_N_RTINA_WTR_ARWAW
31
98 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_I2C_SLAVE_TRAN_COMP_INT_RAW RTC_I2C_SLAVE_TRAN_COMP_INT bc
RTC_I2C_ARBITRATION_LOST_INT_RAW RTC_I2C_ARBITRATION_LOST_INT bc
RTC_I2C_MASTER_TRAN_COMP_INT_RAW RTC_I2C_MASTER_TRAN_COMP_INT bc
RTC_I2C_TRANS_COMPLETE_INT_RAW RTC_I2C_TRANS_COMPLETE_INT bc
RTC_I2C_TIME_OUT_INT_RAW RTC_I2C_TIME_OUT_INT bc
RTC_I2C_ACK_ERR_INT_RAW RTC_I2C_ACK_ERR_INT bc
RTC_I2C_RX_DATA_INT_RAW RTC_I2C_RX_DATA_INT bc
RTC_I2C_TX_DATA_INT_RAW RTC_I2C_TX_DATA_INT bc
RTC_I2C_DETECT_START_INT_RAW RTC_I2C_DETECT_START_INT bc
69
ESP32-S2 TRM ( 1.3)
1 (ULP)
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Register 1.25. RTC_I2C_INT_ST_REG (0x002C)
(reserved)
RTC_IR2TCC__DIR2ETCTCE__TCIRXT2T__CCDS__ATRTAIR2XART_C_TCD_I__NAAIIRTTN2CAT_TCKC_S___IT_STNEIRTIR2TMTR_CCES____TTINOIRR2TUTAC_CTN_S__SMTII_N2RACTCTSCO__T_MSAEIT2RRPCB_L_TIETSRTLRAEAANV_TE_IINO_CTTNOR__AMSNLTPO__CSIOTNM_TIP_N_STITN_TS_TST
31
98 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_I2C_SLAVE_TRAN_COMP_INT_ST RTC_I2C_SLAVE_TRAN_COMP_INT bc RTC_I2C_ARBITRATION_LOST_INT_ST RTC_I2C_ARBITRATION_LOST_INT bc RTC_I2C_MASTER_TRAN_COMP_INT_ST RTC_I2C_MASTER_TRAN_COMP_INT bc
RTC_I2C_TRANS_COMPLETE_INT_ST RTC_I2C_TRANS_COMPLETE_INT bc RTC_I2C_TIME_OUT_INT_ST RTC_I2C_TIME_OUT_INT bc RTC_I2C_ACK_ERR_INT_ST RTC_I2C_ACK_ERR_INT bc RTC_I2C_RX_DATA_INT_ST RTC_I2C_RX_DATA_INT bc RTC_I2C_TX_DATA_INT_ST RTC_I2C_TX_DATA_INT bc RTC_I2C_DETECT_START_INT_ST RTC_I2C_DETECT_START_INT bc
70
ESP32-S2 TRM ( 1.3)
1 (ULP)
GoBack
Register 1.26. RTC_I2C_INT_ENA_REG (0x0030)
(reserved)
RTC_IR2TCC__DIR2ETCTCE__TCIRXT2T__CCDS__ATRTAIR2XART_C_TCD_I__NAAIIRTTN2CAT_TCKC_E___I_NTENEIRANIR2TMTAR_CCE_E___TNINOIRR2ATUTAC_CTN_E__SMNII_N2RAACTCTSCO__T_MEAEI2NRRPCAB_L_TIETSRTLRAEAANV_TE_IINO_CTTNOR__AMENLNPO__ACSIOTNM_TIP_N_ETINN_TAE_NEANA
31
98 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_I2C_SLAVE_TRAN_COMP_INT_ENA RTC_I2C_SLAVE_TRAN_COMP_INT bc/
RTC_I2C_ARBITRATION_LOST_INT_ENA RTC_I2C_ARBITRATION_LOST_INT bc/
RTC_I2C_MASTER_TRAN_COMP_INT_ENA RTC_I2C_MASTER_TRAN_COMP_INT bc/
RTC_I2C_TRANS_COMPLETE_INT_ENA RTC_I2C_TRANS_COMPLETE_INT bc/
RTC_I2C_TIME_OUT_INT_ENA RTC_I2C_TIME_OUT_INT bc/
RTC_I2C_ACK_ERR_INT_ENA RTC_I2C_ACK_ERR_INT bc/
RTC_I2C_RX_DATA_INT_ENA RTC_I2C_RX_DATA_INT bc/
RTC_I2C_TX_DATA_INT_ENA RTC_I2C_TX_DATA_INT bc/
RTC_I2C_DETECT_START_INT_ENA RTC_I2C_DETECT_START_INT bc/
Register 1.27. RTC_I2C_DATA_REG (0x0034)
RTC_I2C_I2C_DONE
31 30
(reserved)
16 15
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RTC_I2C_SLAVE_TX_DATA
87
0x0
RTC_I2C_RDATA RTC I2C bc RTC_I2C_SLAVE_TX_DATA RTC I2C bc/ RTC_I2C_DONE RTC I2C bc
RTC_I2C_I2C_RDATA
0
0x0
Reset
71
ESP32-S2 TRM ( 1.3)
1 (ULP)
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Register 1.28. RTC_I2C_CMD0_REG (0x0038)
RTC_I2C_COMMAND0_DONE
31 30
(reserved)
14 13
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RTC_I2C_COMMAND0 0x903
0
Reset
RTC_I2C_COMMAND0 0 I2C I2C_COMD0_REG bc/
RTC_I2C_COMMAND0_DONE 0 bc
Register 1.29. RTC_I2C_CMD1_REG (0x003C)
RTC_I2C_COMMAND1_DONE
31 30
(reserved)
14 13
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RTC_I2C_COMMAND1 0x1901
0
Reset
RTC_I2C_COMMAND1 1 I2C I2C_COMD1_REG bc/
RTC_I2C_COMMAND1_DONE 1 bc
Register 1.30. RTC_I2C_CMD2_REG (0x0040)
RTC_I2C_COMMAND2_DONE
31 30
(reserved)
14 13
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RTC_I2C_COMMAND2 0x902
0
Reset
RTC_I2C_COMMAND2 2 I2C I2C_COMD2_REG bc/
RTC_I2C_COMMAND2_DONE 2 bc
72
ESP32-S2 TRM ( 1.3)
1 (ULP)
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Register 1.31. RTC_I2C_CMD3_REG (0x0044)
RTC_I2C_COMMAND3_DONE
31 30
(reserved)
14 13
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RTC_I2C_COMMAND3 0x101
0
Reset
RTC_I2C_COMMAND3 3 I2C I2C_COMD3_REG bc/
RTC_I2C_COMMAND3_DONE 3 bc
Register 1.32. RTC_I2C_CMD4_REG (0x0048)
RTC_I2C_COMMAND4_DONE
31 30
(reserved)
14 13
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RTC_I2C_COMMAND4 0x901
0
Reset
RTC_I2C_COMMAND4 4 I2C I2C_COMD4_REG bc/
RTC_I2C_COMMAND4_DONE 4 bc
Register 1.33. RTC_I2C_CMD5_REG (0x004C)
RTC_I2C_COMMAND5_DONE
31 30
(reserved)
14 13
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RTC_I2C_COMMAND5 0x1701
0
Reset
RTC_I2C_COMMAND5 5 I2C I2C_COMD5_REG bc/
RTC_I2C_COMMAND5_DONE 5 bc
73
ESP32-S2 TRM ( 1.3)
1 (ULP)
GoBack
Register 1.34. RTC_I2C_CMD6_REG (0x0050)
RTC_I2C_COMMAND6_DONE
31 30
(reserved)
14 13
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RTC_I2C_COMMAND6 0x1901
0
Reset
RTC_I2C_COMMAND6 6 I2C I2C_COMD6_REG bc/
RTC_I2C_COMMAND6_DONE 6 bc
Register 1.35. RTC_I2C_CMD7_REG (0x0054)
RTC_I2C_COMMAND7_DONE
31 30
(reserved)
14 13
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RTC_I2C_COMMAND7 0x904
0
Reset
RTC_I2C_COMMAND7 7 I2C I2C_COMD7_REG bc/
RTC_I2C_COMMAND7_DONE 7 bc
Register 1.36. RTC_I2C_CMD8_REG (0x0058)
RTC_I2C_COMMAND8_DONE
31 30
(reserved)
14 13
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RTC_I2C_COMMAND8 0x1901
0
Reset
RTC_I2C_COMMAND8 8 I2C I2C_COMD8_REG bc/
RTC_I2C_COMMAND8_DONE 8 bc
74
ESP32-S2 TRM ( 1.3)
1 (ULP)
GoBack
Register 1.37. RTC_I2C_CMD9_REG (0x005C)
RTC_I2C_COMMAND9_DONE
31 30
(reserved)
14 13
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RTC_I2C_COMMAND9 0x903
0
Reset
RTC_I2C_COMMAND9 9 I2C I2C_COMD9_REG bc/
RTC_I2C_COMMAND9_DONE 9 bc
Register 1.38. RTC_I2C_CMD10_REG (0x0060)
RTC_I2C_COMMAND10_DONE
31 30
(reserved)
14 13
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RTC_I2C_COMMAND10 0x101
0
Reset
RTC_I2C_COMMAND10 10 I2C I2C_COMD10_REG bc/
RTC_I2C_COMMAND10_DONE 10 bc
Register 1.39. RTC_I2C_CMD11_REG (0x0064)
RTC_I2C_COMMAND11_DONE
31 30
(reserved)
14 13
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RTC_I2C_COMMAND11 0x901
0
Reset
RTC_I2C_COMMAND11 11 I2C I2C_COMD11_REG bc/
RTC_I2C_COMMAND11_DONE 11 bc
75
ESP32-S2 TRM ( 1.3)
1 (ULP)
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Register 1.40. RTC_I2C_CMD12_REG (0x0068)
RTC_I2C_COMMAND12_DONE
31 30
(reserved)
14 13
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RTC_I2C_COMMAND12 0x1701
0
Reset
RTC_I2C_COMMAND12 12 I2C I2C_COMD12_REG bc/
RTC_I2C_COMMAND12_DONE 12 bc
Register 1.41. RTC_I2C_CMD13_REG (0x006C)
RTC_I2C_COMMAND13_DONE
31 30
(reserved)
14 13
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RTC_I2C_COMMAND13 0x1901
0
Reset
RTC_I2C_COMMAND13 13 I2C I2C_COMD13_REG bc/
RTC_I2C_COMMAND13_DONE 13 bc
Register 1.42. RTC_I2C_CMD14_REG (0x0070)
RTC_I2C_COMMAND14_DONE
31 30
(reserved)
14 13
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RTC_I2C_COMMAND14 0x00
0
Reset
RTC_I2C_COMMAND14 14 I2C I2C_COMD14_REG bc/
RTC_I2C_COMMAND14_DONE 14 bc
76
ESP32-S2 TRM ( 1.3)
1 (ULP)
GoBack
Register 1.43. RTC_I2C_CMD15_REG (0x0074)
RTC_I2C_COMMAND15_DONE
31 30
(reserved)
14 13
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RTC_I2C_COMMAND15 0x00
0
Reset
RTC_I2C_COMMAND15 15 I2C I2C_COMD15_REG bc/
RTC_I2C_COMMAND15_DONE 15 bc
(reserved)
31
28 27
0000
Register 1.44. RTC_I2C_DATE_REG (0x00FC)
RTC_I2C_DATE 0x1905310
RTC_I2C_DATE bc/
0
Reset
77
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
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2
DMA (DMA)
2.1
(Direct Memory Access, DMA) b CPU DMA CPU b ESP32-S2 DMAInternal DMAEDMA Copy DMAbInternal DMA RAM EDMA RAM RAM Copy DMA RAMb ESP32-S2 8 DMA b2.1-1UART0 UART1 Internal DMASPI3 ADC Controller Internal DMAAES SHA EDMA c DMASPI2 I2S0 EDMAbCPU Peripheral Copy DMAb
2.1-1. DMA
2.2
DMA · AHB · · · RAM INCR burst · DMA RAM 320 KB
78
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
· DMA 10.5 MB · DMA
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2.3
ESP32-S2 DMA bDMA CPU RAMb DMA DMA (DMA_ENGINE) b
2.3.1 DMA
2.3-1. DMA
DMA AHB_BUS RAM RAM b 2.3-1 DMA bRAM 3 b DMA bDMA_ENGINE outlink RAM inlink RAM b
2.3.2
2.3-2.
2.3-2 bb 3 b RAM DMA b
· owner (DW0) [31] buffer b
79
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
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1'b0 CPU 1'b1 DMA b DMA buffer bit b PERI_IN_LOOP_TEST b bit 1b
PERI DMA I2SSPIUHCI b
· suc_eof (DW0) [30]b 1'b0 1'b1b bit 0 1 bit 1b bit 1b
· Reserved (DW0) [29]b
· err_eof (DW0) [28]b bit UART DMA b 1 bit 1b
· Reserved (DW0) [27:24]b
· length (DW0) [23:12] buffer b buffer buffer buffer b
· size (DW0) [11:0] buffer b DMA RAM 16/32/64 bytes 2.3.8 RAMb
· buffer address pointer (DW1)buffer b DMA RAM PERI_EXT_MEM_BK_SIZE 2.3.8 RAMb
· next descriptor address (DW2)b (suc_eof = 1) 0b RAMb
DMA buffer buffer b
2.3.3 DMA
DMAb PERI_INLINK_ADDR b PERI_INLINK_START DMAb PERI_OUTLINK_ADDR b PERI_OUTLINK_START DMAbPERI_INLINK_START PERI_OUTLINK_START b
DMA Restart bc Restart b word 2.3-3 PERI_INLINK_RESTART PERI_OUTLINK_RESTARTcb b
80
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
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2.3-3.
2.3.4
DMA DMA RAM b PERI_IN_DSCR_ERR_INT_ENA PERI_OUT_DSCR_ERR_INT_ENA b RAM word 0x3FFB0000 ~ 0x3FFFFFFF RAM word 0x3F500000 ~ 0x3FF7FFFF b word b
2.3.5
DMA EOF b PERI_OUT_TOTAL_EOF_INT_ENA PERI_OUT_TOTAL_EOF_INT EOF buffer DMA b PERI_IN_SUC_EOF_INT_ENA PERI_IN_SUC_EOF_INT b UART DMA UHCI_IN_ERR_EOF_INT UHCI_IN_ERR_EOF_INT_ENA b
PERI_OUT_TOTAL_EOF_INT PERI_IN_SUC_EOF_INT PERI_OUTLINK_DSCR_ADDR PERI_INLINK_DSCR_ADDR b bit b b
EOF suc_eof EOF suc_eof err_eofb
2.3.6 Internal DMA
Internal DMA RAM UART0, UART1SPI3 ADC ControllerbInternal DMA RAM 0x3FFB0000 ~ 0x3FFFFFFFbInternal DMA RAM csizelengthbuffer address pointer word b Internal DMA length length b
2.3.7 EDMA
EDMA RAM RAM I2S0SPI2AES SHAb
81
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
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2.3.7.1 RAM
EDMA RAM Internal DMA 0x3FFB0000 ~ 0x3FFFFFFFb csizelengthbuffer address pointer word bEDMA null cnull EDMA memory null EOF 2.3-4 EOF EOF 3 b EOF suc_eof err_eofb
EDMA PERI_OUT_DATA_BURST_EN b
2.3-4. EDMA RAM
2.3.8 RAM
EDMA RAM 0x3F500000 ~ 0x3FF7FFFFbEDMA block size 16/32/64 16/32/64 b PERI_EXT_MEM_BK_SIZE block size EDMA block sizeb
RAM block size b sizebuffer address pointer 16/32/64 b 16/32/64 EDMA 16/32/64 b PERI_DMA_IN_SUC_EOF_INT length b sizealength buffer address pointer block size b2.3-1 PERI_EXT_MEM_BK_SIZE b
2.3-1. ablock size
PERI_EXT_MEM_BK_SIZE 0 1 2
Block Size 16 32 64
16 32 64
2.4 Copy DMA
Copy DMA RAMb2.4-1 Copy DMA Internal DMA EDMA Copy DMA RAM DMA FIFO FIFO RAMb
Copy DMA
1. CP_DMA_IN_RSTaCP_DMA_OUT_RSTaCP_DMA_FIFO_RST CP_DMA_CMDFIFO_RST 1 0 Copy DMA FIFO
82
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
2. CP_DMA_OUTLINK_ADDR 3. CP_DMA_INLINK_ADDR 4. CP_DMA_OUTLINK_START DMA 5. CP_DMA_INLINK_START DMA b
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2.4-1. Copy DMA
2.5 UART DMA (UDMA)
ESP32-S2 2 UART 1 UDMA bUHCI_UART_CE UDMAb
2.5-1. UDMA
2.5-1 UDMA b UDMA bUHCI_INLINK_ADDR b UHCI_INLINK_START (UHCI) UART Decoderb Decoder UDMA RAM b
UDMA UHCI_OUTLINK_ADDR b UHCI_OUTLINK_START DMA RAM Encoder UART b
83
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
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UDMA c + + bEncoder bDecoder bb UHCI_SEPER_CHAR 0xC0b UHCI_ESC_SEQ0_CHAR0c 0xDB UHCI_ESC_SEQ0_CHAR1c 0xDDb UHCI_OUT_TOTAL_EOF_INT b UHCI_IN_SUC_EOF_INT b
2.6 SPI DMA
2.6-1. SPI DMA
ESP32-S2 SPI CPU DMA b 2.6-1 SPI2 SPI3 DMAb ESP32-S2 SPI DMA / burst / 1 b
SPI_DMA_OUT_LINK_REG SPI_OUTLINK_START SPI_DMA_IN_LINK_REG SPI_INLINK_START DMA b SPI_OUTLINK_START 1 DMA SPI_INLINK_START 1 DMA b
SPI DMA 1. SPI_IN_RSTaSPI_AHBM_FIFO_RST SPI_AHBM_RST 1 0 DMA FIFO
2. SPI_INLINK_ADDR 3. SPI_INLINK_START DMA b SPI DMA 1. SPI_OUT_RSTaSPI_AHBM_FIFO_RST SPI_AHBM_RST 1 0 DMA FIFO
2. SPI_OUTLINK_ADDR 3. SPI_OUTLINK_START DMA b : SPI2 SPI3 DMA RAM RAM SPI_MEM_TRANS_ENb SPI2 SPI3 DMA 24 SPI (SPI)b
84
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
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2.7 I2S DMA
ESP32-S2 I2S DMAb I2S_FIFO_CONF_REG I2S_DSCR_EN I2S DMA bESP32-S2 I2S DMA / burst b I2S_RXEOF_NUM_REG I2S_RX_EOF_NUM[31:0] DMA b
I2S_OUT_LINK_REG I2S_OUTLINK_START I2S_IN_LINK_REG I2S_INLINK_START DMA , b I2S_OUTLINK_START 1 DMA I2S_INLINK_START 1 DMA b
I2S DMA
1. I2S_IN_RSTaI2S_AHBM_FIFO_RST I2S_AHBM_RST 1 0 DMA FIFO
2. I2S_INLINK_ADDR
3. I2S_INLINK_START DMA b
I2S DMA
1. I2S_OUT_RSTaI2S_AHBM_FIFO_RST I2S_AHBM_RST 1 0 DMA FIFO
2. I2S_OUTLINK_ADDR
3. I2S_OUTLINK_START DMA b : I2S DMA RAM RAM I2S_MEM_TRANS_ENb I2S DMA I2S buffer 26 I2S (I2S) I2S I2S DMA LCD buffer 26 I2S (I2S) LCD b I2S DMA 26 I2S (I2S) 26.12.2 DMA b
2.8 DMA
ESP32-S2 AES SHA EDMA DMAb CRYPTO_DMA_AES_SHA_SELECT SHA DMA CRYPTO_DMA_AES_SHA_SELECT AES DMAb DMA DMA
1. CRYPTO_DMA_IN_RST/CRYPTO_DMA_AHBM_FIFO_RST/CRYPTO_DMA_AHBM_RST 1 0 DMA FIFO
2. CRYPTO_DMA_INLINK_ADDR 3. CRYPTO_DMA_INLINK_START DMA b DMA DMA 1. CRYPTO_DMA_OUT_RST/CRYPTO_DMA_AHBM_FIFO_RST/CRYPTO_DMA_AHBM_RST 1
0 DMA FIFO 2. CRYPTO_DMA_OUTLINK_ADDR
85
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
3. CRYPTO_DMA_OUTLINK_START DMA b : DMA RAM RAM CRYPTO_DMA_MEM_TRANS_ENb
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2.9 Copy DMA
· CP_DMA_OUT_TOTAL_EOF_INTc b
· CP_DMA_IN_DSCR_EMPTY_INT buffer b
· CP_DMA_OUT_DSCR_ERR_INTb · CP_DMA_IN_DSCR_ERR_INTb · CP_DMA_OUT_EOF_INT EOF 1b · CP_DMA_OUT_DONE_INTb · CP_DMA_IN_SUC_EOF_INTb · CP_DMA_IN_DONE_INTb
2.10 DMA
· CRYPTO_DMA_INFIFO_FULL_WM_INT DMA FIFO cCRYPTO_DMA_INFIFO_FULL_THRSb · CRYPTO_DMA_OUT_TOTAL_EOF_INTc
b · CRYPTO_DMA_IN_DSCR_EMPTY_INT buffer
b · CRYPTO_DMA_OUT_DSCR_ERR_INTb · CRYPTO_DMA_IN_DSCR_ERR_INTb · CRYPTO_DMA_OUT_EOF_INT EOF 1
b · CRYPTO_DMA_OUT_DONE_INTb · CRYPTO_DMA_IN_ERR_EOF_INTb · CRYPTO_DMA_IN_SUC_EOF_INTb · CRYPTO_DMA_IN_DONE_INTb
2.11
Copy DMA DMA 2.11-1 b DMA b 3 b
86
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
2.11-1. Copy DMA DMA
Copy DMA
CRYPTO DMA
PeriBUS1 PeriBUS1 PeriBUS2
0x3F4C3000 0x3F43F000 0x6003F000
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2.12
Copy DMA c 2.11 Copy DMA b
CP_DMA_INT_RAW_REG CP_DMA_INT_ST_REG CP_DMA_INT_ENA_REG CP_DMA_INT_CLR_REG CP_DMA_OUT_EOF_DES_ADDR_REG CP_DMA_OUT_LINK_REG CP_DMA_IN_LINK_REG CP_DMA_CONF_REG CP_DMA_IN_EOF_DES_ADDR_REG CP_DMA_OUT_EOF_BFR_DES_ADDR _REG CP_DMA_INLINK_DSCR_REG
CP_DMA_INLINK_DSCR_BF0_REG CP_DMA_OUTLINK_DSCR_REG
CP_DMA_OUTLINK_DSCR_BF0_REG CP_DMA_IN_ST_REG CP_DMA_OUT_ST_REG CP_DMA_DATE_REG
EOF
0x0000 0x0004 0x0008 0x000C 0x0018
/
Copy DMA
0x0010 0x0014 0x003C
/
EOF
0x001C 0x0020
Copy DMA
0x0024
0x0028 0x0030
0x0034 0x0040 0x0044 0x00FC
/
DMA c, 2.11 DMA b
CRYPTO_DMA_CONF0_REG CRYPTO_DMA_OUT_LINK_REG
DMA
0x0000 / 0x0024 varies
87
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
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CRYPTO_DMA_IN_LINK_REG CRYPTO_DMA_CONF1_REG CRYPTO_DMA_AHB_TEST_REG CRYPTO_DMA_AES_SHA_SELECT _REG CRYPTO_DMA_PD_CONF_REG CRYPTO_DMA_DATE_REG CRYPTO_DMA_INT_RAW_REG CRYPTO_DMA_INT_ST_REG CRYPTO_DMA_INT_ENA_REG CRYPTO_DMA_INT_CLR_REG CRYPTO_DMA_OUT_STATUS_REG CRYPTO_DMA_IN_STATUS_REG CRYPTO_DMA_STATE0_REG CRYPTO_DMA_STATE1_REG CRYPTO_DMA_OUT_EOF_DES_ADDR _REG CRYPTO_DMA_IN_SUC_EOF_DES _ADDR_REG CRYPTO_DMA_IN_ERR_EOF_DES _ADDR_REG CRYPTO_DMA_OUT_EOF_BFR_DES _ADDR_REG CRYPTO_DMA_IN_DSCR_REG
CRYPTO_DMA_IN_DSCR_BF0_REG CRYPTO_DMA_OUT_DSCR_REG
CRYPTO_DMA_OUT_DSCR_BF0_REG
DMA AHB AES/SHA
0x0028 0x002C 0x0048 0x0064
DMA
0x0068 0x00FC
0x0004 0x0008 0x000C 0x0010
TX FIFO RX FIFO EOF
0x0014 0x001C 0x0030 0x0034 0x0038
EOF
0x003C
EOF
0x0040
0x0044
0x004C
0x0050 0x0058
0x005C
varies / / /
/ /
/
88
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
2.13
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Register 2.1. CP_DMA_INT_RAW_REG (0x0000)
(reserved)
CP_DCMPA__DOCMUPAT___DTINCMO_PTADA__LSDO_CCMUEPRATO____FDEID_NCMMSI_PNPACD_TT_RDS_YO_CCMR_UEPRAIARTN__W__RTDEOE__CRMOUIRNRPAFTA__T___WID_NIIDNNRMTO_TA_AN_SWR_EURAI_NACWIW__NDETOO_FNR_AEIW_NITN_TR_ARWAW
31
87 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
CP_DMA_IN_DONE_INT_RAW b buffer b()
CP_DMA_IN_SUC_EOF_INT_RAW bb ()
CP_DMA_OUT_DONE_INT_RAW b TX FIFO b()
CP_DMA_OUT_EOF_INT_RAW b EOF TX FIFO b()
CP_DMA_IN_DSCR_ERR_INT_RAW b ab()
CP_DMA_OUT_DSCR_ERR_INT_RAW b ab()
CP_DMA_IN_DSCR_EMPTY_INT_RAW ba b()
CP_DMA_OUT_TOTAL_EOF_INT_RAW b EOF a b()
89
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
GoBack
Register 2.2. CP_DMA_INT_ST_REG (0x0004)
(reserved)
CP_DCMPA__DOCMUPAT___DTINCMO_PTADA__LDSO_CCMUEPRATO____FDEID_NCMMSI_PNPACD_TT_RDS_YO_CCMS_UEPTRIARTN____RTDEOE__CRMOUISNRPAFTT__T___ID_NIIDNNSMTOT_T_AN_SS_ESUTI_TNCI__NDETOO_FNS_TEI_NITN_TS_TST
31
87 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
CP_DMA_IN_DONE_INT_ST CP_DMA_IN_DONE_INT_ENA 1 CP_DMA_IN_DONE_INT b()
CP_DMA_IN_SUC_EOF_INT_ST CP_DMA_IN_SUC_EOF_INT_ENA
1
CP_DMA_IN_SUC_EOF_INT b()
CP_DMA_OUT_DONE_INT_ST CP_DMA_OUT_DONE_INT_ENA 1 CP_DMA_OUT_DONE_INT b()
CP_DMA_OUT_EOF_INT_ST CP_DMA_OUT_EOF_INT_ENA 1 CP_DMA_OUT_EOF_INT b()
CP_DMA_IN_DSCR_ERR_INT_ST CP_DMA_IN_DSCR_ERR_INT_ENA
1
CP_DMA_IN_DSCR_ERR_INT b()
CP_DMA_OUT_DSCR_ERR_INT_ST CP_DMA_OUT_DSCR_ERR_INT_ENA
1
CP_DMA_OUT_DSCR_ERR_INT b()
CP_DMA_IN_DSCR_EMPTY_INT_ST CP_DMA_IN_DSCR_EMPTY_INT_ENA 1 CP_DMA_IN_DSCR_EMPTY_INT b()
CP_DMA_OUT_TOTAL_EOF_INT_ST CP_DMA_OUT_TOTAL_EOF_INT_ENA
1
CP_DMA_OUT_TOTAL_EOF_INT b()
90
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
GoBack
Register 2.3. CP_DMA_INT_ENA_REG (0x0008)
(reserved)
CP_DCMPA__DOCMUPAT___DTINCMO_PTADA__LDSO_CCMUEPRATO____FDEID_NCMMSI_PNPACD_TT_RDS_YO_CCME_UEPRNIARTN__A__RTDEOE__CRMOUIENRPAFTN__T___AID_NIIDNNEMTO_NT_AN_SAE_EUENI_NNCAIA__NDETOO_FNE_NEI_ANITN_TE_NEANA
31
87 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
CP_DMA_IN_DONE_INT_ENA CP_DMA_IN_DONE_INT b(/) CP_DMA_IN_SUC_EOF_INT_ENA CP_DMA_IN_SUC_EOF_INT b(/) CP_DMA_OUT_DONE_INT_ENA CP_DMA_OUT_DONE_INT b(/) CP_DMA_OUT_EOF_INT_ENA CP_DMA_OUT_EOF_INT b(/) CP_DMA_IN_DSCR_ERR_INT_ENA CP_DMA_IN_DSCR_ERR_INT b(/) CP_DMA_OUT_DSCR_ERR_INT_ENA CP_DMA_OUT_DSCR_ERR_INT b(/)
CP_DMA_IN_DSCR_EMPTY_INT_ENA CP_DMA_IN_DSCR_EMPTY_INT b (/)
CP_DMA_OUT_TOTAL_EOF_INT_ENA CP_DMA_OUT_TOTAL_EOF_INT b(/)
91
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
GoBack
Register 2.4. CP_DMA_INT_CLR_REG (0x000C)
(reserved)
CP_DCMPA__DOCMUPAT___DTINCMO_PTADA__LDSO_CCMUEPRATO____FDEID_NCMMSI_PNPACD_TT_RDS_YO_CCMC_UEPRLIARTN_R___RTDEOE__CRMOUICNRPAFTL__T___RID_NIIDNNCMTO_TL_ANR_SC_ECULI_NLCRIR__NDETOO_FCN_LEIR_NITN_TC_LCRLR
31
87 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
CP_DMA_IN_DONE_INT_CLR CP_DMA_IN_DONE_INT b() CP_DMA_IN_SUC_EOF_INT_CLR CP_DMA_IN_SUC_EOF_INT b() CP_DMA_OUT_DONE_INT_CLR CP_DMA_OUT_DONE_INT b() CP_DMA_OUT_EOF_INT_CLR CP_DMA_OUT_EOF_INT b() CP_DMA_IN_DSCR_ERR_INT_CLR CP_DMA_IN_DSCR_ERR_INT b() CP_DMA_OUT_DSCR_ERR_INT_CLR CP_DMA_OUT_DSCR_ERR_INT b()
CP_DMA_IN_DSCR_EMPTY_INT_CLR CP_DMA_IN_DSCR_EMPTY_INT b( )
CP_DMA_OUT_TOTAL_EOF_INT_CLR CP_DMA_OUT_TOTAL_EOF_INT b( )
Register 2.5. CP_DMA_OUT_EOF_DES_ADDR_REG (0x0018)
CP_DMA_OUT_EOF_DES_ADDR
31
0
0x000000
Reset
CP_DMA_OUT_EOF_DES_ADDR EOF 1 b()
92
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
GoBack
Register 2.6. CP_DMA_OUT_LINK_REG (0x0010)
CP_DCMPA__DOCMUPAT__LDOINCMUKPAT___LPDOIANMURKATK__LROINEUSKTT_ALSIRTNTAKR_TSTOP(reserved)
31 30 29 28 27
20 19
0 0 0 00 0 0 0 0 0 0 0
CP_DMA_OUTLINK_ADDR 0x000
0
Reset
CP_DMA_OUTLINK_ADDR 20 b(/)
CP_DMA_OUTLINK_STOP DMA b(/)
CP_DMA_OUTLINK_START b(/)
CP_DMA_OUTLINK_RESTART DMA b(/)
CP_DMA_OUTLINK_PARK 1 FSM b0 FSM b ()
Register 2.7. CP_DMA_IN_LINK_REG (0x0014)
CP_DCMPA__DINCMLPAI_N_DKINCM_LPPAI_AN_DRKINMK_LRAINE_SKINT_ALSIRTNTAKR_TSTOP (reserved)
31 30 29 28 27
20 19
0 0 0 00 0 0 0 0 0 0 0
CP_DMA_INLINK_ADDR 0x000
0
Reset
CP_DMA_INLINK_ADDR 20 b(/)
CP_DMA_INLINK_STOP DMA b(/)
CP_DMA_INLINK_START DMA b(/)
CP_DMA_INLINK_RESTART b(/)
CP_DMA_INLINK_PARK 1 FSM b0 FSM b( )
93
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
GoBack
Register 2.8. CP_DMA_CONF_REG (0x003C)
CP_DMA_CLK_EN
31 30
(reserved)
CP_DCMPA__DCCMHPAE_C_DOKCM_UPOAT__W_DIANNCMU_EPATOR_O_WDO_CMNWUPEATR_R__BDFOACMIWCFPAOKN___DECRCRMMSPATD__FDOIMFUOAT___RIRNSS_TTRST
87 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
CP_DMA_IN_RST DMA FSMb(/) CP_DMA_OUT_RST DMA FSMb(/) CP_DMA_CMDFIFO_RST in_cmd FIFO out_cmd FIFOb(/) CP_DMA_FIFO_RST RX FIFO b(/) CP_DMA_OUT_OWNER b
CP_DMA_OUT_AUTO_WRBACK b(/) CP_DMA_IN_OWNER b(/) CP_DMA_OUT_AUTO_WRBACK b(/) CP_DMA_CHECK_OWNER b(/) CP_DMA_CLK_EN 1'b1b1'b0b(/)
Register 2.9. CP_DMA_IN_EOF_DES_ADDR_REG (0x001C)
CP_DMA_IN_SUC_EOF_DES_ADDR
31
0
0x000000
Reset
CP_DMA_IN_SUC_EOF_DES_ADDR suc_eof b()
94
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
Register 2.10. CP_DMA_OUT_EOF_BFR_DES_ADDR_REG (0x0020)
CP_DMA_OUT_EOF_BFR_DES_ADDR
31
0x000000
CP_DMA_OUT_EOF_BFR_DES_ADDR ()
GoBack
0
Reset
Register 2.11. CP_DMA_INLINK_DSCR_REG (0x0024)
CP_DMA_INLINK_DSCR
31
0
0
Reset
CP_DMA_INLINK_DSCR x+1b()
Register 2.12. CP_DMA_INLINK_DSCR_BF0_REG (0x0028)
CP_DMA_INLINK_DSCR_BF0
31
0
CP_DMA_INLINK_DSCR_BF0 xb()
0
Reset
95
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
GoBack
Register 2.13. CP_DMA_OUTLINK_DSCR_REG (0x0030)
CP_DMA_OUTLINK_DSCR
31
0
0
Reset
CP_DMA_OUTLINK_DSCR y+1b()
Register 2.14. CP_DMA_OUTLINK_DSCR_BF0_REG (0x0034)
CP_DMA_OUTLINK_DSCR_BF0
31
0
CP_DMA_OUTLINK_DSCR_BF0 y-1 b()
0
Reset
Register 2.15. CP_DMA_IN_ST_REG (0x0040)
(reserved)
CP_DMA_FCIFPO__DEMMAP_TINY_SCTPA_TDEMA_IN_DSCR_STATE
31
24 23 22
20 19 18 17
0 0 0 0 0 0 0 00
0
0
CP_DMA_INLINK_DSCR_ADDR 0
0
Reset
CP_DMA_INLINK_DSCR_ADDR c 18 b b()
CP_DMA_IN_DSCR_STATE b()
CP_DMA_IN_STATE b()
CP_DMA_FIFO_EMPTY Copy DMA FIFO b()
96
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
GoBack
Register 2.16. CP_DMA_OUT_ST_REG (0x0044)
(reserved)
CP_DMA_FCIFPO__DFMUAL_LOUTC_PS_TDATMEA_OUT_DSCR_STATE
31
24 23 22
20 19 18 17
0 0 0 0 0 0 0 00
0
0
CP_DMA_OUTLINK_DSCR_ADDR 0
0
Reset
CP_DMA_OUTLINK_DSCR_ADDR c 18 b b()
CP_DMA_OUT_DSCR_STATE b()
CP_DMA_OUT_STATE b()
CP_DMA_FIFO_FULL Copy DMA FIFO b()
Register 2.17. CP_DMA_DATE_REG (0x00FC)
CP_DMA_DMA_DATE
31
0x18082000
CP_DMA_DMA_DATE b(/)
0
Reset
97
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
GoBack
Register 2.18. CRYPTO_DMA_CONF0_REG (0x0000)
(reserved)
CRYPTCOR_YPDTCMORA_Y_PDMTCMEORAM_Y_PD_OTTCMURORATA_Y__NPDIDNSTCMA_ODRTAES_YA_NCPD_OTRCMBUO_RUAT_BYR_DPDUSOSTCMTRUCO_RSATR_YTE___PDN_OEBTECMOUUONRAFTR_Y___SPDOMNTTCMUO_OORATE_D_Y__NRPDEOAETCMUUSORATTT_YAO__PDRIL_NTCMTOWO_R_OARL_YC_POBPDLA_AOTCMRTHCOPREABK__YS_MTPDTAE_TMHSORABTS__MTDO_MUFATIF__OIRN_S_RTRSSTT
31
13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Reset
CRYPTO_DMA_IN_RST DMA FSM RX FIFO b(/)
CRYPTO_DMA_OUT_RST DMA FSM TX FIFO b(/)
CRYPTO_DMA_AHBM_FIFO_RST DMA AHB FIFO b(/)
CRYPTO_DMA_AHBM_RST DMA AHB b(/)
CRYPTO_DMA_IN_LOOP_TEST b(/)
CRYPTO_DMA_OUT_LOOP_TEST b(/)
CRYPTO_DMA_OUT_AUTO_WRBACK TX Buffer b(/)
CRYPTO_DMA_OUT_NO_RESTART_CLR b(/)
CRYPTO_DMA_OUT_EOF_MODE TX FIFO EOF b1 DMA FIFO TX EOF 0 DMA FIFO EOF 0(/)
CRYPTO_DMA_OUTDSCR_BURST_EN 1 TX FIFO RAM INCR b(/)
CRYPTO_DMA_INDSCR_BURST_EN 1 RX FIFO RAM INCR b(/)
CRYPTO_DMA_OUT_DATA_BURST_EN 1 TX FIFO RAM INCR b(/)
CRYPTO_DMA_MEM_TRANS_EN 1 DMA b(/)
98
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
GoBack
Register 2.19. CRYPTO_DMA_OUT_LINK_REG (0x0024)
CRYPTCOR_YPDTCMORA_Y_PDOTCMUORAT_Y_LPDOINTMUKOAT___LPDOIANMURKATK__LROINEUSKTT_ALSIRTNTAKR_(TrSeTsOePrved)
31 30 29 28 27
20 19
0 0 0 00 0 0 0 0 0 0 0
CRYPTO_DMA_OUTLINK_ADDR 0x000
0
Reset
CRYPTO_DMA_OUTLINK_ADDR 20 b(/)
CRYPTO_DMA_OUTLINK_STOP DMA b(/)
CRYPTO_DMA_OUTLINK_START DMA b(/)
CRYPTO_DMA_OUTLINK_RESTART DMA b(/)
CRYPTO_DMA_OUTLINK_PARK 1 FSM b0 FSM b()
Register 2.20. CRYPTO_DMA_IN_LINK_REG (0x0028)
CRYPTCOR_YPDTCMORA_Y_PDINTCMOLRAI_YN_PDKINTM_OLPAI_AN_DRKINMK_LRAINE_SKINT_ALSIRTNTAKR(_rTeSsTeOrPved)
31 30 29 28 27
CRYPTO_DMA_INLINK_AUTO_RET
21 20 19
0 0 0 00 0 0 0 0 0 0 1
CRYPTO_DMA_INLINK_ADDR 0x000
0
Reset
CRYPTO_DMA_INLINK_ADDR 20 b(/) CRYPTO_DMA_INLINK_AUTO_RET b(/) CRYPTO_DMA_INLINK_STOP DMA
b(/) CRYPTO_DMA_INLINK_START DMA b(/) CRYPTO_DMA_INLINK_RESTART b(/) CRYPTO_DMA_INLINK_PARK 1 FSM b0 FSM
b()
99
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
GoBack
Register 2.21. CRYPTO_DMA_CONF1_REG (0x002C)
(reserved)
CRYPTO_CDRMYPAT_OE_XDTM_MA_ECMH_EBCKK__SOIZWENER
CRYPTO_DMA_INFIFO_FULL_THRS
31
15 14 13 12 11
0
00000000000000000 0 0
0
Reset
CRYPTO_DMA_INFIFO_FULL_THRS CRYPTO_DMA_INFIFO_FULL_WM_INT b(/)
CRYPTO_DMA_CHECK_OWNER b(/)
CRYPTO_DMA_EXT_MEM_BK_SIZE DMA block sizeb016 132 2 64 3b(/)
Register 2.22. CRYPTO_DMA_AHB_TEST_REG (0x0048)
(reserved)
CRYPTO_(rDesMeArv_eAdH)BC_RTYEPSTTAOD_DDRMA_AHB_TESTMODE
31
65
432
0
00000000000000000000000000 0 0
0
Reset
CRYPTO_DMA_AHB_TESTMODE b(/) CRYPTO_DMA_AHB_TESTADDR b(/)
Register 2.23. CRYPTO_DMA_AES_SHA_SELECT_REG (0x0064)
(reserved)
CRYPTO_DMA_AES_SHA_SELECT
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
CRYPTO_DMA_AES_SHA_SELECT AES SHA DMAb0AESb1SHAb(/)
100
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
GoBack
Register 2.24. CRYPTO_DMA_PD_CONF_REG (0x0068)
(reserved)
CRYPTCOR_YPDTCMORA_Y_PDRTMAOMA___DRCMALMAK(__r_eRFFsAOOeMRrvC_eFEdO_) PRUCE_PD
31
76 5 43
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 Reset
CRYPTO_DMA_RAM_FORCE_PD RAM b0 RAM 1 CRYPTO_DMA_RAM_FORCE_P 0 RAM b(/)
CRYPTO_DMA_RAM_FORCE_PU
RAM
b0
CRYPTO_DMA_RAM_FORCE_PD 1 RAM 1 RAM b(/)
CRYPTO_DMA_RAM_CLK_FO 1 DMA RAM b0 DMA RAM b(/)
Register 2.25. CRYPTO_DMA_DATE_REG (0x00FC)
CRYPTO_DMA_DATE
31
0x19050700
CRYPTO_DMA_DATE b(/)
0
Reset
101
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
GoBack
Register 2.26. CRYPTO_DMA_INT_RAW_REG (0x0004)
(reserved)
CRYPTCOR_YPDTCMORA_Y_PDINTCMOFRAI_YF_PDOOTCM_UORFAT_YU__PDLTINTCMLOO__RTAWDA_Y_LPDSMO_CTCMU_EORRAITON__Y__FPDTEID_NM_TCMSIO_RNRPACDA_YTT_RWPSD_YO_CTCMR_UEORRAIARTN__WY__RTPDEOE__RTCMOUIRONRRAFTA__TY___WIPD_NIIDNNTRMTOO_TA_AN_WE_R_ERRDAI_NRAMWIW__NAEST_OU_INFCR___AIDEWNOOTFN__REI_ANWITN_TR_ARWAW
31
10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
CRYPTO_DMA_IN_DONE_INT_RAW buffer b()
CRYPTO_DMA_IN_SUC_EOF_INT_RAW DMA RX FIFO b()
CRYPTO_DMA_IN_ERR_EOF_INT_RAW b()
CRYPTO_DMA_OUT_DONE_INT_RAW TX FIFO b()
CRYPTO_DMA_OUT_EOF_INT_RAW out EOF b( )
CRYPTO_DMA_IN_DSCR_ERR_INT_RAW ab()
CRYPTO_DMA_OUT_DSCR_ERR_INT_RAW ab()
CRYPTO_DMA_IN_DSCR_EMPTY_INT_RAW a b()
CRYPTO_DMA_OUT_TOTAL_EOF_INT_RAW EOF a b()
CRYPTO_DMA_INFIFO_FULL_WM_INT_RAW RX FIFO CRYPTO_DMA_INFIFO_FULL_THRS b( )
102
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
GoBack
Register 2.27. CRYPTO_DMA_INT_ST_REG (0x0008)
(reserved)
CRYPTCOR_YPDTCMORA_Y_PDINTCMOFRAI_YF_DPOOTCM_UORFAT_YU__PDLTINTCMLOO__RTAWDA_Y_LPSDMO_CTCMU_EORRAITON__Y__FPDTEID_NM_TCMSIO_SNRPACTD_YTT_RPSD_YO_CTCMS_UEOTRRIARTN__Y__RTPDEOE__RTCMOUISONRRAFTT__TY___IPD_NIIDNNSTMTOOT_T_AN_E_S_ERSDTI_TNRMI__NAEST_OU_INFCS___TIDENOOTFN__SEIT_NITN_TS_TST
31
10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
CRYPTO_DMA_IN_DONE_INT_ST CRYPTO_DMA_IN_DONE_INT b()
CRYPTO_DMA_IN_SUC_EOF_INT_ST CRYPTO_DMA_IN_SUC_EOF_INT b ()
CRYPTO_DMA_IN_ERR_EOF_INT_ST b()
CRYPTO_DMA_OUT_DONE_INT_ST CRYPTO_DMA_OUT_DONE_INT b( )
CRYPTO_DMA_OUT_EOF_INT_ST CRYPTO_DMA_OUT_EOF_INT b()
CRYPTO_DMA_IN_DSCR_ERR_INT_ST CRYPTO_DMA_IN_DSCR_ERR_INT b()
CRYPTO_DMA_OUT_DSCR_ERR_INT_ST CRYPTO_DMA_OUT_DSCR_ERR_INT b()
CRYPTO_DMA_IN_DSCR_EMPTY_INT_ST CRYPTO_DMA_IN_DSCR_EMPTY_INT b()
CRYPTO_DMA_OUT_TOTAL_EOF_INT_ST CRYPTO_DMA_OUT_TOTAL_EOF_INT b()
CRYPTO_DMA_INFIFO_FULL_WM_INT_ST CRYPTO_DMA_INFIFO_FULL_WM_INT b()
103
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
GoBack
Register 2.28. CRYPTO_DMA_INT_ENA_REG (0x000C)
(reserved)
CRYPTCOR_YPDTCMORA_Y_PDINTCMOFRAI_YF_PDOOTCM_UORFAT_YU__PDLTINTCMLOO__RTAWDA_Y_LPDSMO_CTCMU_EORRAITON__Y__FPDTEID_NM_TCMSIO_ENRPACND_YTT_RPSDA_YO_CTCME_UEORNRIARTN__YA__RTDPEOE__RTCMOUIEONRRAFTN__TY___AIPD_NIIDNNTEMTOO_NT_AN_E_AE_EREDNI_NNRMAI_A_NAEST_OU_INFCE___NIDENAOOTFN__EEIN_NIATN_TE_NEANA
31
10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
CRYPTO_DMA_IN_DONE_INT_ENA CRYPTO_DMA_IN_DONE_INT b(/) CRYPTO_DMA_IN_SUC_EOF_INT_ENA CRYPTO_DMA_IN_SUC_EOF_INT b
(/) CRYPTO_DMA_IN_ERR_EOF_INT_ENA b(/) CRYPTO_DMA_OUT_DONE_INT_ENA CRYPTO_DMA_OUT_DONE_INT b(/)
CRYPTO_DMA_OUT_EOF_INT_ENA CRYPTO_DMA_OUT_EOF_INT b(/)
CRYPTO_DMA_IN_DSCR_ERR_INT_ENA CRYPTO_DMA_IN_DSCR_ERR_INT b (/)
CRYPTO_DMA_OUT_DSCR_ERR_INT_ENA CRYPTO_DMA_OUT_DSCR_ERR_INT b(/)
CRYPTO_DMA_IN_DSCR_EMPTY_INT_ENA CRYPTO_DMA_IN_DSCR_EMPTY_INT b(/)
CRYPTO_DMA_OUT_TOTAL_EOF_INT_ENA CRYPTO_DMA_OUT_TOTAL_EOF_INT b(/)
CRYPTO_DMA_INFIFO_FULL_WM_INT_ENA CRYPTO_DMA_INFIFO_FULL_WM_INT b(/)
104
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
GoBack
Register 2.29. CRYPTO_DMA_INT_CLR_REG (0x0010)
(reserved)
CRYPTCOR_YPDTCMORA_Y_PDINTCMOFRAI_YF_PDOOTCM_UORFAT_YU__PDLTINTCMLOO__RTAWDA_Y_LPDSMO_CTCMU_EORRAITON__Y__FPDTEID_NM_TCMSIOC_NRPACDL_YTT_RRPSD_YO_CTCMC_UEORRLIARTN_R_Y__RTPDEOE__RTCMOUICONRRAFTL__TY___RIPD_NIIDNNCTMTOO_TL_ANR_E_C_ECRDLI_NRLMRIR__NAEST_OU_INFCC___LIDERNOOTFN__CEI_LNRITN_TC_LCRLR
31
10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
CRYPTO_DMA_IN_DONE_INT_CLR CRYPTO_DMA_IN_DONE_INT b()
CRYPTO_DMA_IN_SUC_EOF_INT_CLR CRYPTO_DMA_IN_SUC_EOF_INT b ()
CRYPTO_DMA_IN_ERR_EOF_INT_CLR b()
CRYPTO_DMA_OUT_DONE_INT_CLR CRYPTO_DMA_OUT_DONE_INT b( )
CRYPTO_DMA_OUT_EOF_INT_CLR CRYPTO_DMA_OUT_EOF_INT b()
CRYPTO_DMA_IN_DSCR_ERR_INT_CLR CRYPTO_DMA_IN_DSCR_ERR_INT b ()
CRYPTO_DMA_OUT_DSCR_ERR_INT_CLR CRYPTO_DMA_OUT_DSCR_ERR_INT b()
CRYPTO_DMA_IN_DSCR_EMPTY_INT_CLR CRYPTO_DMA_IN_DSCR_EMPTY_INT b()
CRYPTO_DMA_OUT_TOTAL_EOF_INT_CLR CRYPTO_DMA_OUT_TOTAL_EOF_INT b()
CRYPTO_DMA_INFIFO_FULL_WM_INT_CLR CRYPTO_DMA_INFIFO_FULL_WM_INT b()
105
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
GoBack
Register 2.30. CRYPTO_DMA_OUT_STATUS_REG (0x0014)
(reserved)
CRYPTCOR_YPDTMOA__DOMUAT__OEMUTP_TFYULL
31
21 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Reset
CRYPTO_DMA_OUT_FULL 1DMA TX FIFO b() CRYPTO_DMA_OUT_EMPTY 1DMA TX FIFO b()
Register 2.31. CRYPTO_DMA_IN_STATUS_REG (0x001C)
(reserved)
CRYPTCOR_YPDTMOA__DINM_AE_MINP_TFYULL
31
21 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Reset
CRYPTO_DMA_IN_FULL 1DMA RX FIFO b() CRYPTO_DMA_IN_EMPTY 1DMA RX FIFO b()
106
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
GoBack
(reserved)
31
27 26
00000
Register 2.32. CRYPTO_DMA_STATE0_REG (0x0030)
CRYPTO_DMA_INFICFORY_PCTNOT__DDMEBACU_RGINY_PSTTOA_TDEMA_IN_DSCR_STATE
23 22
20 19 18 17
0
0
0
CRYPTO_DMA_INLINK_DSCR_ADDR 0
0
Reset
CRYPTO_DMA_INLINK_DSCR_ADDR c 18 b b()
CRYPTO_DMA_IN_DSCR_STATE b()
CRYPTO_DMA_IN_STATE b()
CRYPTO_DMA_INFIFO_CNT_DEBUG FIFO b()
(reserved)
31
28 27
0000
Register 2.33. CRYPTO_DMA_STATE1_REG (0x0034)
CRYPTO_DMA_OUTFIFCOR_YCPNTOT_DMAC_ROYUPTT_OS_TDATMEA_OUT_DSCR_STATE
23 22
20 19 18 17
0
0
0
CRYPTO_DMA_OUTLINK_DSCR_ADDR 0
CRYPTO_DMA_OUTLINK_DSCR_ADDR b() CRYPTO_DMA_OUT_DSCR_STATE b() CRYPTO_DMA_OUT_STATE b() CRYPTO_DMA_OUTFIFO_CNT FIFO b()
0
Reset
107
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
GoBack
Register 2.34. CRYPTO_DMA_OUT_EOF_DES_ADDR_REG (0x0038)
CRYPTO_DMA_OUT_EOF_DES_ADDR
31
0
0x000000
Reset
CRYPTO_DMA_OUT_EOF_DES_ADDR EOF 1 b ()
Register 2.35. CRYPTO_DMA_IN_SUC_EOF_DES_ADDR_REG (0x003C)
CRYPTO_DMA_IN_SUC_EOF_DES_ADDR
31
0
0x000000
Reset
CRYPTO_DMA_IN_SUC_EOF_DES_ADDR suc_eof b()
Register 2.36. CRYPTO_DMA_IN_ERR_EOF_DES_ADDR_REG (0x0040)
CRYPTO_DMA_IN_ERR_EOF_DES_ADDR
31
0
0x000000
Reset
CRYPTO_DMA_IN_ERR_EOF_DES_ADDR b ()
108
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
GoBack
Register 2.37. CRYPTO_DMA_OUT_EOF_BFR_DES_ADDR_REG (0x0044)
CRYPTO_DMA_OUT_EOF_BFR_DES_ADDR
31
0
0x000000
Reset
CRYPTO_DMA_OUT_EOF_BFR_DES_ADDR b()
Register 2.38. CRYPTO_DMA_IN_DSCR_REG (0x004C)
CRYPTO_DMA_INLINK_DSCR
31
0
0
Reset
CRYPTO_DMA_INLINK_DSCR x+1b()
Register 2.39. CRYPTO_DMA_IN_DSCR_BF0_REG (0x0050)
CRYPTO_DMA_INLINK_DSCR_BF0
31
0
0
Reset
CRYPTO_DMA_INLINK_DSCR_BF0 xb()
109
ESP32-S2 TRM ( 1.3)
2 DMA (DMA)
GoBack
Register 2.40. CRYPTO_DMA_OUT_DSCR_REG (0x0058)
CRYPTO_DMA_OUTLINK_DSCR
31
0
0
Reset
CRYPTO_DMA_OUTLINK_DSCR y+1b()
Register 2.41. CRYPTO_DMA_OUT_DSCR_BF0_REG (0x005C)
CRYPTO_DMA_OUTLINK_DSCR_BF0
31
0
0
Reset
CRYPTO_DMA_OUTLINK_DSCR_BF0 yb()
110
ESP32-S2 TRM ( 1.3)
GoBack
II
RAMaROMaeFuse b
111
ESP32-S2 TRM ( 1.3)
3
GoBack
3
3.1
ESP32-S2 Xtensa® LX7 CPU ba CPU b
3.2
· 4 GBc32 464 KB 400 KB 1.77 MB 7.5 MB 14.5 MB 320 KB DMA 10.5 MB DMA
· 128 KB Internal ROM 320 KB Internal SRAM 8 KB RTC FAST Memory 8 KB RTC SLOW Memory
· 1 GB SPI flash 1 GB SPI RAM
· DMA 9 DMA /
3.2-1 b
112
ESP32-S2 TRM ( 1.3)
3
External memory
MMU DMA
Cache
0x0000_0000 0x3EFF_FFFF
0x3F00_0000 0x3F3F_FFFF
0x3F40_0000 0x3F4F_FFFF
0x3F50_0000 0x3FF7_FFFF
0x3FF8_0000 0x3FF9_DFFF
0x3FF9_E000 0x3FFF_FFFF
0x4000_0000 0x4007_1FFF
0x4007_2000 0x4007_FFFF
0x4008_0000 0x407F_FFFF
0x4080_0000 0x4FFF_FFFF
0x5000_0000 0x5000_1FFF
0x5000_2000 0x5FFF_FFFF
0x6000_0000 0x600B_FFFF
0x600C_0000 0x617F_FFFF
0x6180_0000 0x6180_3FFF
0x6180_4000 0xFFFF_FFFF
3.2-1.
Internal memory Peripheral
· b · b
GoBack
DMA
3.3
3.3.1
Xtensa® LX7 CPU CPU 4 GBc32 b 0x4000_0000 0x4000_0000 ~ 0x4FFF_FFFF 0x5000_0000 b CPU bCPU aabCPU CPU b CPU
· · cache · / b
113
ESP32-S2 TRM ( 1.3)
3
GoBack
3.3-1 CPU b
CPU b
3.3-1.
/ / /
0x0000_0000 0x3EFF_FFFF
0x3F00_0000 0x3F3F_FFFF
0x3F40_0000 0x3F4F_FFFF
0x3F50_0000 0x3FF7_FFFF
0x3FF8_0000 0x3FF9_DFFF
0x3FF9_E000 0x3FFF_FFFF
0x4000_0000 0x4007_1FFF
0x4007_2000 0x4007_FFFF
0x4008_0000 0x407F_FFFF
0x4080_0000 0x4FFF_FFFF
0x5000_0000 0x5000_1FFF
0x5000_2000 0x5FFF_FFFF
0x6000_0000 0x600B_FFFF
0x600C_0000 0x617F_FFFF
0x6180_0000 0x6180_3FFF
0x6180_4000 0xFFFF_FFFF
4 MB 1 MB 10.5 MB
392 KB 456 KB
7.5 MB
8 KB
768 KB
16 KB
3.3.2
Internal ROM (128 KB)aInternal SRAM (320 KB)aRTC FAST Memory (8 KB)aRTC SLOW Memory (8 KB)b 128 KB Internal ROM 64 KB Internal ROM 0a64 KB Internal ROM 1 b 320 KB Internal SRAM 32 KB Internal SRAM 0a288 KB Internal SRAM 1 b RTC FAST Memory RTC SLOW Memory SRAMb 3.3-2 b
3.3-2.
0x3FF9_E000 0x3FF9_FFFF
0x3FFA_0000 0x3FFA_FFFF
0x3FFB_0000 0x3FFB_7FFF
0x3FFB_8000 0x3FFF_FFFF
0x4000_0000 0x4000_FFFF
0x4001_0000 0x4001_FFFF
0x4002_0000 0x4002_7FFF
8 KB 64 KB 32 KB 288 KB 64 KB 64 KB 32 KB
RTC FAST Memory Internal ROM 1 Internal SRAM 0 Internal SRAM 1 Internal ROM 0 Internal ROM 1 Internal SRAM 0
YES NO YES YES NO NO YES
114
ESP32-S2 TRM ( 1.3)
3
GoBack
0x4002_8000 0x4006_FFFF
0x4007_0000 0x4007_1FFF
0x5000_0000 0x5000_1FFF
288 KB 8 KB 8 KB
Internal SRAM 1 RTC FAST Memory RTC SLOW Memory
YES YES YES
3.3-2 op YESb / b
3.3.2.1 Internal ROM 0
Internal ROM 0 64 KBb 3.3-2 CPU b
3.3.2.2 Internal ROM 1
Internal ROM 1 64 KBb 3.3-2 CPU b Internal ROM 1 0x3FFA_0000 0x4001_0000 0x3FFA_0004 0x4001_0004 0x3FFA_0008 0x4001_0008 b
3.3.2.3 Internal SRAM 0
Internal SRAM 0 32 KBb 3.3-2 CPU b 8 KBa16 KBa24 KB 32 KB cache b cache CPU cache CPU b
3.3.2.4 Internal SRAM 1
Internal SRAM 1 288 KBb 3.3-2 CPU b Internal SRAM 1 288 KB 18 16 KB cb 1 Trace Memory CPU Trace Trace Memory CPU b
3.3.2.5 RTC FAST Memory
RTC FAST Memory 8 KB SRAMb 3.3-2 CPU b
3.3.2.6 RTC SLOW Memory
RTC SLOW Memory 8 KB SRAMb 3.3-2 CPU b RTC SLOW Memory CPU 0x3F42_1000 ~ 0x3F42_2FFF 0x6002_1000 ~ 0x6002_2FFF b
115
ESP32-S2 TRM ( 1.3)
3
GoBack
3.3.3
ESP32-S2 QSPI / OSPI flash (RAM)bESP32-S2 XTS-AES flash RAM b
3.3.3.1
CPU (cache) bCache MMU CPU flash RAM b 1 GB flash 1 GB RAMb
ESP32-S2
· 7.5 MB (ICache) 64 KB flash RAM aab
· 4 MB (ICache) 64 KB flash RAM aab
· 10.5 MB (DCache) 64 KB RAMa ab flash RAMb
3.3-3 CPU cache b
3.3-3.
0x3F00_0000 0x3F3F_FFFF
0x3F50_0000 0x3FF7_FFFF
0x4008_0000 0x407F_FFFF
4 MB 10.5 MB
7.5 MB
ICache DCache ICache
YES YES YES
3.3-3 op YESb / b
3.3.3.2
3.3-1 ESP32-S2 cache CPU bCache c 3.3.2.3b cache cache ICache DCache bICache DCache 8 KB 16 KB 16 B 32 Bb
116
ESP32-S2 TRM ( 1.3)
3
GoBack
3.3-1. Cache
3.3.3.3 Cache
ESP32-S2 cache 1. (Invalidate) Tag (Valid bit)b CPU bb cache cache bICache DCache b 2. (Clean) Tag (Dirty bit)b CPU cache b DCache b 3. (Write-back) Tag b CPU cache b DCache b 4. (Preload)Preload cache b 1 b / cb 5. / (Lock / Unlock)cache cache memory cache cache memory b cache b , cache cache bbCache ab
3.3.4 DMA
ESP32-S2 (direct memory access, DMA) · / · · / · b
DMA CPU Internal SRAM 0 Internal SRAM 1 0x3FFB_0000 ~ 0x3FFB_7FFF Internal SRAM 0 0x3FFB_8000 ~ 0x3FFF_FFFF Internal SRAM 1b DMA cache b
117
ESP32-S2 TRM ( 1.3)
3
GoBack
DMA CPU DCache (0x3F50_0000 ~ 0x3FF7_FFFF) RAMb DCache DMA b
DMA / 9 3.3-4 b / DMA b DMA 2 DMA b
3.3-4. DMA /
UART0
UART1
SPI2
SPI3
I2S0
ADC Controller
Copy DMA
AES Accelerator SHA Accelerator
3.3.5 /
CPU 0x3F40_0000 ~ 0x3F4F_FFFFa / 0x6000_0000 ~ 0x600B_FFFF 0x6180_0000 ~ 0x6180_3FFF / b
3.3.5.1
· PeriBus1 0x3F40_0000 ~ 0x3F4F_FFFF oPeriBus1 poPeriBus1p 0x3F40_0000b · PeriBus2 0x6000_0000 ~ 0x600B_FFFF 0x6180_0000 ~ 0x6180_3FFF oPeriBus2 poPeriBus2p 0x6000_0000b
oPeriBus1poPeriBus2pb
3.3.5.2
CPU PeriBus2 / CPU PeriBus1 / b PeriBus1 (speculative read) / FIFO PeriBus2 b PeriBus1 volatile PeriBus2 b
3.3.5.3 /
3.3-5 / / bo pb / b
118
ESP32-S2 TRM ( 1.3)
3
GoBack
3.3-5. /
UART0 SPI1 SPI0 GPIO RTC IO MUX I2S0 UART1 I2C0 UHCI0 RMT PCNT LED PWM Controller eFuse Controller Timer Group 0 Timer Group 1 RTC SLOW Memory System Timer SPI2 SPI3 SYSCON I2C1 TWAI Controller USB External Control Registers AES Accelerator SHA Accelerator RSA Accelerator Digital Signature HMAC Crypto DMA
0x0000_0000 0x0000_0FFF
0x0000_1000 0x0000_1FFF
0x0000_2000 0x0000_2FFF
0x0000_3000 0x0000_3FFF
0x0000_4000 0x0000_4FFF
0x0000_5000 0x0000_6FFF
0x0000_7000 0x0000_7FFF
0x0000_8000 0x0000_8FFF
0x0000_9000 0x0000_9FFF
0x0000_A000 0x0000_EFFF
0x0000_F000 0x0000_FFFF
0x0001_0000 0x0001_0FFF
0x0001_1000 0x0001_2FFF
0x0001_3000 0x0001_3FFF
0x0001_4000 0x0001_4FFF
0x0001_5000 0x0001_5FFF
0x0001_6000 0x0001_6FFF
0x0001_7000 0x0001_7FFF
0x0001_8000 0x0001_8FFF
0x0001_9000 0x0001_9FFF
0x0001_A000 0x0001_AFFF
0x0001_B000 0x0001_EFFF
0x0001_F000 0x0001_FFFF
0x0002_0000 0x0002_0FFF
0x0002_1000 0x0002_2FFF
0x0002_3000 0x0002_3FFF
0x0002_4000 0x0002_4FFF
0x0002_5000 0x0002_5FFF
0x0002_6000 0x0002_6FFF
0x0002_7000 0x0002_7FFF
0x0002_8000 0x0002_AFFF
0x0002_B000 0x0002_BFFF
0x0002_C000 0x0003_8FFF
0x0003_9000 0x0003_9FFF
0x0003_A000 0x0003_AFFF
0x0003_B000 0x0003_BFFF
0x0003_C000 0x0003_CFFF
0x0003_D000 0x0003_DFFF
0x0003_E000 0x0003_EFFF
0x0003_F000 0x0003_FFFF
0x0004_4000 0x000C_DFFF
Size 4 KB 1, 2, 3
4 KB 1, 2 4 KB 1, 2 4 KB 1, 2
4 KB 1, 2 4 KB 1, 2
4 KB 1, 2, 3 4 KB 1, 2, 3
4 KB 1, 2, 3 4 KB 1, 2
4 KB 1, 2, 3 4 KB 1, 2
4 KB 1, 2 4 KB 1, 2
4 KB 4 KB 8 KB 4 KB 4 KB 4 KB 4 KB 4 KB
1, 2 1, 2 1, 2, 3 1, 2 1, 2 1, 2 1, 2 1, 2, 3
4 KB 1, 2
4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB
1, 2, 3, 4 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2
119
ESP32-S2 TRM ( 1.3)
3
ADC Controller USB Core Registers System Registers PMS Registers Interrupt Matrix Copy DMA Dedicated GPIO
GoBack
0x0004_0000 0x0004_0FFF
0x0004_1000 0x0007_FFFF
0x0008_0000 0x000B_FFFF
0x000C_0000 0x000C_0FFF
0x000C_1000 0x000C_1FFF
0x000C_2000 0x000C_2FFF
0x000C_3000 0x000C_3FFF
0x000C_4000 0x000C_EFFF
0x000C_F000 0x000C_FFFF
0x000D_1000 0x000F_FFFF
0x0180_0000 0x0180_3FFF
Size 4 KB
256 KB 4 KB 4 KB 4 KB 4 KB
4 KB
1, 2
1, 2, 3, 4 1 1 1 1
1
1. / PeriBus1 b 2. / PeriBus2 b 3. PeriBus1 / c 3.3.5.4 b 4. / b
3.3.5.4 PeriBus1
3.3.5.2 PeriBus1 (speculative read) / FIFO b 3.3-6 PeriBus1 b4 b 14b
3.3-6.
UART0 UART1 I2S0 RMT I2C0 I2C1 USB OTG
/ 0x3F40_0000 0x3F41_0000 0x3F40_F004
0x3F41_6000 ~ 0x3F41_600F 0x3F41_301C 0x3F42_701C
0x3F48_0020, 0x3F48_1000 ~ 0x3F49_0FFF
120
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
GoBack
4 eFuse (eFuse)
4.1
ESP32-S2 4096 eFusebeFuse 1 0beFuse eFuse beFuse eFuse b b eFuse c aHMAC b
4.2
· · · ·
4.3
4.3.1
eFuse 11 (BLOCK0 ~ BLOCK10)b BLOCK0 24 38 b
4.3-1 caaaa b
EFUSE_WR_DIS EFUSE_RD_DIS BLOCK4 ~ BLOCK10b 4.3.1.1a4.3.1.2b
4.3-1. BLOCK0
EFUSE_WR_DIS EFUSE_RD_DIS
EFUSE_WR_DIS
0 32
Y
32 7
Y
N/A
eFuse
eFuse 0
BLOCK4 ~ 10
121
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
GoBack
EFUSE_WR_DIS
EFUSE_DIS_ICACHE
40 1
Y
2
ICache
EFUSE_DIS_DCACHE
41 1
Y
2
DCache
EFUSE_DIS_DOWNLOAD_ ICACHE
42 1
Y
Download 2
ICache
EFUSE_DIS_DOWNLOAD_ DCACHE
43 1
Y
Download 2
DCache
EFUSE_DIS_FORCE_DOWNLOAD 44 1
Y
Down2
load
EFUSE_DIS_USB
45 1
Y
2
USB OTG
EFUSE_DIS_CAN
46 1
Y
2
TWAI
EFUSE_DIS_BOOT_REMAP
47 1
Y
RAM 2
ROM
EFUSE_SOFT_DIS_JTAG
49 1
Y
2
JTAG
EFUSE_HARD_DIS_JTAG
50 1
Y
2
JTAGc
EFUSE_DIS_DOWNLOAD_ MAN-
51 1
Y
UAL_ENCRYPT
download boot
2
flash
EFUSE_USB_EXCHG_PINS
56 1
Y
30
USB D+/D-
EFUSE_EXT_PHY_ENABLE
57 1
N
30
USB PHY
EFUSE_USB_FORCE_NOPERSIST 58 1
N
USB BVALID 30
1
EFUSE_VDD_SPI_XPD
68 1
Y
VDD_SPI_FORCE 1 3
VDD_SPI
EFUSE_VDD_SPI_TIEH
69 1
Y
VDD_SPI_FORCE 1 3
VDD_SPI
EFUSE_VDD_SPI_FORCE
70 1
Y
XPD_VDD_PSI_REG
3
VDD_SPI_TIEH VDD_SPI
LDO
EFUSE_WDT_DELAY_SEL
80 2
Y
3
RTC
EFUSE_SPI_BOOT_CRYPT_CNT 82 3
Y
4
SPI boot
EFUSE_SECURE_BOOT_KEY_
85 1
N
REVOKE0
(Se5
cure Boot)
EFUSE_SECURE_BOOT_KEY_
86 1
N
REVOKE1
6
EFUSE_SECURE_BOOT_KEY_
87 1
N
REVOKE2
7
EFUSE_KEY_PURPOSE_0
88 4
Y
Key0 (purpose) 4.38
2
EFUSE_KEY_PURPOSE_1
92 4
Y
9
Key1 4.3-2
EFUSE_KEY_PURPOSE_2
96 4
Y
10
Key2 4.3-2
EFUSE_KEY_PURPOSE_3
100 4
Y
11
Key3 4.3-2
EFUSE_KEY_PURPOSE_4
104 4
Y
12
Key4 4.3-2
EFUSE_KEY_PURPOSE_5
108 4
Y
13
Key5 4.3-2
EFUSE_SECURE_BOOT_EN
116 1
N
15
122
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
GoBack
EFUSE_WR_DIS
EFUSE_SECURE_BOOT_ AG-
117 1
N
GRESSIVE_REVOKE
16
EFUSE_FLASH_TPUW
124 4
N
18
flash
EFUSE_DIS_DOWNLOAD_MODE 128 1
N
download boot 18
EFUSE_DIS_LEGACY_SPI_BOOT 129 1
N
18
Legacy SPI boot
EFUSE_UART_PRINT_CHANNEL 130 1
N
boot UART 18
EFUSE_DIS_USB_DOWNLOAD_
132 1
N
MODE
UART download boot 18
USB OTG
EFUSE_ENABLE_SECURITY_ DOWNLOAD
133 1
N
18
UART
EFUSE_UART_PRINT_CONTROL 134 2
N
18
UART boot
EFUSE_PIN_POWER_SELECTION 136 1
N
18
GPIO33 ~ GPIO37
EFUSE_FLASH_TYPE
137 1
N
18
flash
EFUSE_FORCE_SEND_RESUME 138 1
N
ROM SPI 18
EFUSE_SECURE_VERSION
139 16
N
18
IDF
4.3-2 b EFUSE_KEY_PURPOSE_n KEYn (n: 0 ~ 5)b
4.3-2.
0 1 2 3 4 5 6 7 8 9 10 11
XTS_AES_256_KEY_1 c flash/SRAM XTS_AES_256_KEY_2 c flash/SRAM XTS_AES_128_KEY c flash/SRAM HMAC Downstreamc HMAC Downstream JTAG HMAC Downstream HMAC Upstreamc SECURE_BOOT_DIGEST0 csecure boot SECURE_BOOT_DIGEST1 csecure boot SECURE_BOOT_DIGEST2 csecure boot
4.3-3 BLOCK1 ~ BLOCK10 b
123
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
GoBack
4.3-3. BLOCK1-10
BLOCK1
BLOCK2 BLOCK3 BLOCK4 BLOCK5 BLOCK6 BLOCK7 BLOCK8 BLOCK9 BLOCK10
EFUSE_MAC EFUSE_SPI_PAD_ CONFIGURE
EFUSE_SYS_DATA_PART0 EFUSE_SYS_DATA_PART1
EFUSE_USR_DATA EFUSE_KEY0_DATA EFUSE_KEY1_DATA EFUSE_KEY2_DATA EFUSE_KEY3_DATA EFUSE_KEY4_DATA EFUSE_KEY5_DATA EFUSE_SYS_DATA_PART2
48 [0:5] [6:11] [12:17] [18:23] [24:29] [30:35] [36:41] [42:47] [48:53] [54:59] [60:65]
78 256 256 256 256 256 256 256 256 256
N N N N N N N N N N N N N N N Y Y Y Y Y Y N
EFUSE_WR_DIS
20 20 20 20 20 20 20 20 20 20 20 20 20 21 22 23 24 25 26 27 28 29
EFUSE_RD_DIS
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
0 1 2 3 4 5 6
MAC CLK Q (D1) D (D0) CS HD (D3) WP (D2) DQS D4 D5 D6 D7 KEY0 KEY1 KEY2 KEY3 KEY4 KEY5
BLOCK4 ~ 9 KEY0~5 eFuse 6 256 b c 4.3-2b HMAC Downstream JTAG KEY3c BLOCK7 6 EFUSE_KEY_PURPOSE_3b
BLOCK1 ~ BLOCK10 RS 4.3.1.3 4.3.2b
4.3.1.1 EFUSE_WR_DIS
EFUSE_WR_DIS eFuse b EFUSE_WR_DIS eFuse c 4.3.3 eFuse b
4.3-1 4.3-3 oEFUSE_WR_DIS p EFUSE_WR_DIS b
0 b
1 0 1b b
124
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
GoBack
4.3.1.2 EFUSE_RD_DIS
BLOCK4 ~ BLOCK10 4.3-3 oEFUSE_RD_DIS poN/Apb EFUSE_RD_DIS eFuse c 4.3.3 eFuse b EFUSE_RD_DIS 0 1 b
BLOCK4 ~ BLOCK10 b BLOCK4 ~ BLOCK10 EFUSE_KEY_PURPOSE_n b
4.3.1.3
eFuse b BLOCK0 4 BLOCK0 c EFUSE_WR_DIS eFuse 4 b4 b BLOCK1 ~ BLOCK10 RS (44, 32) 6 b RS (44, 32) p(x) = x8 + x4 + x3 + x2 + 1b
4.3-1. c 32
4.3-2. c 12
125
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
GoBack
4.3-1 4.3-2 32 RS (44, 32) 32 44
· [0:31] · [32:43] 8 DFF1, DFF2, ..., DFF12 cgf_mul_n GF (28)
n n
44 eFusebeFuse eFuse b
RS 256 eFuse block block b
4.3.2
eFuse bBLOCK0 ~ BLOCK10 b EFUSE_BLK_NUM b BLOCK0 EFUSE_BLK_NUM = 0 BLOCK0bEFUSE_PGM_DATA0_REG EFUSE_WR_DISb EFUSE_PGM_DATA1_REG ~ EFUSE_PGM_DATA5_REG 24 0
· EFUSE_PGM_DATA1_REG[29:31]
· EFUSE_PGM_DATA1_REG[20:23]
· EFUSE_PGM_DATA2_REG[7:15]
· EFUSE_PGM_DATA2_REG[0:3]
· EFUSE_PGM_DATA3_REG[16:19] EFUSE_PGM_DATA6_REG ~ EFUSE_PGM_DATA7_REG EFUSE_PGM_CHECK_VALUE0_REG ~ EFUSE_PGM_CHECK_VALUE2_REG BLOCK0 b BLOCK1 EFUSE_BLK_NUM = 1 EFUSE_PGM_DATA0_REG ~ EFUSE_PGM_DATA5_REG BLOCK1 EFUSE_PGM_CHECK_VALUE0_REG ~ EFUSE_PGM_CHECK_VALUE2_REG RS bEFUSE_PGM_DATA6_REG ~ EFUSE_PGM_DATA7_REG BLOCK1 bRS 0b BLOCK2 ~ 10 EFUSE_BLK_NUM = 2 ~ 10 EFUSE_PGM_DATA0_REG ~ EFUSE_PGM_DATA7_REG EFUSE_PGM_CHECK_VALUE0_REG ~ EFUSE_PGM_CHECK_VALUE2_REG RS b
1. EFUSE_BLK_NUM b 2. EFUSE_PGM_DATA0_REG ~ EFUSE_PGM_DATA7_REG
EFUSE_PGM_CHECK_VALUE0_REG ~ EFUSE_PGM_CHECK_VALUE2_REG b
126
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
GoBack
3. eFuse 4.3.4.1eFuse b 4. eFuse VDDQ 4.3.4.2eFuse VDDQ b 5. EFUSE_CONF_REG EFUSE_OP_CODE 0x5A5Ab 6. EFUSE_CMD_REG EFUSE_PGM_CMD 1b 7. EFUSE_CMD_REG 0x0b/
4.3.3 b 8. b 9. eFuse 4.3.3b
BLOCK0 b bb EFUSE_WR_DIS EFUSE_WR_DIS b EFUSE_WR_DIS EFUSE_WR_DIS b b
BLOCK1 b BLOCK2 ~ 10 BLOCK b
4.3.3
eFuse beFuse EFUSE_RD_ eFuse b 4.3-4 b
4.3-4.
BLOCK 0 0 1 2 3 4-9 10
EFUSE_RD_WR_DIS_REG EFUSE_RD_REPEAT_DATA0 ~ 4_REG EFUSE_RD_MAC_SPI_SYS_0 ~ 5_REG EFUSE_RD_SYS_PART1_0 ~ 7_REG EFUSE_RD_USR_DATA0 ~ 7_REG EFUSE_RD_KEYn_DATA0 ~ 7_REG (n: 0 ~ 5) EFUSE_RD_SYS_PART2_0 ~ 7_REG
EFUSE_PGM_DATA0_REG EFUSE_PGM_DATA1 ~ 5_REG EFUSE_PGM_DATA0 ~ 5_REG EFUSE_PGM_DATA0 ~ 7_REG EFUSE_PGM_DATA0 ~ 7_REG EFUSE_PGM_DATA0 ~ 7_REG EFUSE_PGM_DATA0 ~ 7_REG
eFuse eFuse eFuse b c eFuse b eFuse
1. eFuse 4.3.4.3eFuse b 2. EFUSE_CONF_REG EFUSE_OP_CODE 0x5AA5b 3. EFUSE_CMD_REG EFUSE_READ_CMD 1b
127
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
GoBack
4. EFUSE_CMD_REG 0x0 read_done interruptc /b
5. eFuse b eFuse eFuse b eFuse b EFUSE_RD_REPEAT_ERR0 ~ 3_REG BLOCK0 EFUSE_WR_DIS c 1 0 b EFUSE_RD_RS_ERR0 ~ 1_REG eFuse BLOCK1 ~ BLOCK10 RS b eFuse b / /b 1 0 b
· 1 1. EFUSE_INT_RAW_REG 1/0 1/0 1/b
· 2: 1. EFUSE_INT_ENA_REG 1/0 1 eFuse /b 2. CPU EFUSE b 3. /b 4. EFUSE_INT_CLR_REG 1/0 1 /b
4.3.4
4.3.4.1 eFuse
4.3-3 eFuse b EFUSE_TSUP_AaEFUSE_TPGMaEFUSE_THP_A EFUSE_TPGM_INACTIVE eFuse b CSBaVDDQaPGENB
· CSB · VDDQeFuse · PGENB
128
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
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4.3-3. eFuse
eFuse CLK_APB b CLK_APB 4.3-5beFuse 20 MHz b
4.3-5. eFuse
APB Frequency
80 MHz 40 MHz 20 MHz
EFUSE_TSUP_A (> 6.669 ns)
0x2 0x1 0x1
EFUSE_TPGM (9-11 µs, usually 10 µs)
0x320 0x190 0xC8
EFUSE_THP_A (> 6.166 ns)
0x2 0x1 0x1
EFUSE_TPGM_INACTIVE (> 35.96 ns)
0x4 0x2 0x1
4.3-3 A0 1 A0 eFuse 1A1 A1 eFuse 0b
4.3.4.2 eFuse VDDQ
APB eFuse VDDQ 4.3-6. VDDQ
APB Frequency
80 MHz 40 MHz 20 MHz
EFUSE_DAC_CLK_DIV (> 1 µs)
0xA0 0x50 0x28
EFUSE_PWR_ON_NUM (> EFUSE_DAC_CLK_DIV*255)
0xA200 0x5100 0x2880
EFUSE_PWR_OFF_NUM (> 3 µs)
0x100 0x80 0x40
4.3.4.3 eFuse
4.3-4 eFuse b EFUSE_TSUR_AaEFUSE_TRD EFUSE_THR_A eFuse b
129
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
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4.3-4. eFuse
APB 4.3-7b 4.3-7. eFuse
APB Frequency
80 MHz 40 MHz 20 MHz
EFUSE_TSUR_A (> 6.669 ns) 0x2 0x1 0x1
EFUSE_TRD (> 35.96 ns)
0x4 0x2 0x1
EFUSE_THR_A (> 6.166 ns) 0x2 0x1 0x1
4.3.5
b 4.3-1 4.3-3o poYpb
4.3.6
· eFuse b EFUSE_PGM_DONE_INT_ENA 1b
· eFuse b EFUSE_READ_DONE_INT_ENA 1b
4.4
eFuse 4.4-1 b 3 b
130
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
4.4-1. eFuse
PeriBUS1 PeriBUS2
0x3F41A000 0x6001A000
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4.5
eFuse cb 4.4 eFuse b
EFUSE_PGM_DATA0_REG EFUSE_PGM_DATA1_REG EFUSE_PGM_DATA2_REG EFUSE_PGM_DATA3_REG EFUSE_PGM_DATA4_REG EFUSE_PGM_DATA5_REG EFUSE_PGM_DATA6_REG EFUSE_PGM_DATA7_REG EFUSE_PGM_CHECK_VALUE0_REG EFUSE_PGM_CHECK_VALUE1_REG EFUSE_PGM_CHECK_VALUE2_REG EFUSE_RD_WR_DIS_REG EFUSE_RD_REPEAT_DATA0_REG EFUSE_RD_REPEAT_DATA1_REG EFUSE_RD_REPEAT_DATA2_REG EFUSE_RD_REPEAT_DATA3_REG EFUSE_RD_REPEAT_DATA4_REG EFUSE_RD_MAC_SPI_SYS_0_REG EFUSE_RD_MAC_SPI_SYS_1_REG EFUSE_RD_MAC_SPI_SYS_2_REG EFUSE_RD_MAC_SPI_SYS_3_REG EFUSE_RD_MAC_SPI_SYS_4_REG EFUSE_RD_MAC_SPI_SYS_5_REG EFUSE_RD_SYS_DATA_PART1_0_REG EFUSE_RD_SYS_DATA_PART1_1_REG EFUSE_RD_SYS_DATA_PART1_2_REG EFUSE_RD_SYS_DATA_PART1_3_REG EFUSE_RD_SYS_DATA_PART1_4_REG EFUSE_RD_SYS_DATA_PART1_5_REG EFUSE_RD_SYS_DATA_PART1_6_REG
0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b RS 0 b RS 1 b RS 2 b
BLOCK0 0 b BLOCK0 1 b BLOCK0 2 b BLOCK0 3 b BLOCK0 4 b BLOCK0 5 b BLOCK1 0 b BLOCK1 1 b BLOCK1 2 b BLOCK1 3 b BLOCK1 4 b BLOCK1 5 b BLOCK2 (system) 0 b BLOCK2 (system) 1 b BLOCK2 (system) 2 b BLOCK2 (system) 3 b BLOCK2 (system) 4 b BLOCK2 (system) 5 b BLOCK2 (system) 6 b
0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028
/ / / / / / / / / / /
0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 0x0058 0x005C 0x0060 0x0064 0x0068 0x006C 0x0070 0x0074
131
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
EFUSE_RD_SYS_DATA_PART1_7_REG EFUSE_RD_USR_DATA0_REG EFUSE_RD_USR_DATA1_REG EFUSE_RD_USR_DATA2_REG EFUSE_RD_USR_DATA3_REG EFUSE_RD_USR_DATA4_REG EFUSE_RD_USR_DATA5_REG EFUSE_RD_USR_DATA6_REG EFUSE_RD_USR_DATA7_REG EFUSE_RD_KEY0_DATA0_REG EFUSE_RD_KEY0_DATA1_REG EFUSE_RD_KEY0_DATA2_REG EFUSE_RD_KEY0_DATA3_REG EFUSE_RD_KEY0_DATA4_REG EFUSE_RD_KEY0_DATA5_REG EFUSE_RD_KEY0_DATA6_REG EFUSE_RD_KEY0_DATA7_REG EFUSE_RD_KEY1_DATA0_REG EFUSE_RD_KEY1_DATA1_REG EFUSE_RD_KEY1_DATA2_REG EFUSE_RD_KEY1_DATA3_REG EFUSE_RD_KEY1_DATA4_REG EFUSE_RD_KEY1_DATA5_REG EFUSE_RD_KEY1_DATA6_REG EFUSE_RD_KEY1_DATA7_REG EFUSE_RD_KEY2_DATA0_REG EFUSE_RD_KEY2_DATA1_REG EFUSE_RD_KEY2_DATA2_REG EFUSE_RD_KEY2_DATA3_REG EFUSE_RD_KEY2_DATA4_REG EFUSE_RD_KEY2_DATA5_REG EFUSE_RD_KEY2_DATA6_REG EFUSE_RD_KEY2_DATA7_REG EFUSE_RD_KEY3_DATA0_REG EFUSE_RD_KEY3_DATA1_REG EFUSE_RD_KEY3_DATA2_REG EFUSE_RD_KEY3_DATA3_REG EFUSE_RD_KEY3_DATA4_REG EFUSE_RD_KEY3_DATA5_REG EFUSE_RD_KEY3_DATA6_REG EFUSE_RD_KEY3_DATA7_REG EFUSE_RD_KEY4_DATA0_REG EFUSE_RD_KEY4_DATA1_REG
BLOCK2 (system) 7 b BLOCK3 (user) 0 b BLOCK3 (user) 1 b BLOCK3 (user) 2 b BLOCK3 (user) 3 b BLOCK3 (user) 4 b BLOCK3 (user) 5 b BLOCK3 (user) 6 b BLOCK3 (user) 7 b BLOCK4 (KEY0) 0 b BLOCK4 (KEY0) 1 b BLOCK4 (KEY0) 2 b BLOCK4 (KEY0) 3 b BLOCK4 (KEY0) 4 b BLOCK4 (KEY0) 5 b BLOCK4 (KEY0) 6 b BLOCK4 (KEY0) 7 b BLOCK5 (KEY1) 0 b BLOCK5 (KEY1) 1 b BLOCK5 (KEY1) 2 b BLOCK5 (KEY1) 3 b BLOCK5 (KEY1) 4 b BLOCK5 (KEY1) 5 b BLOCK5 (KEY1) 6 b BLOCK5 (KEY1) 7 b BLOCK6 (KEY2) 0 b BLOCK6 (KEY2) 1 b BLOCK6 (KEY2) 2 b BLOCK6 (KEY2) 3 b BLOCK6 (KEY2) 4 b BLOCK6 (KEY2) 5 b BLOCK6 (KEY2) 6 b BLOCK6 (KEY2) 7 b BLOCK7 (KEY3) 0 b BLOCK7 (KEY3) 1 b BLOCK7 (KEY3) 2 b BLOCK7 (KEY3) 3 b BLOCK7 (KEY3) 4 b BLOCK7 (KEY3) 5 b BLOCK7 (KEY3) 6 b BLOCK7 (KEY3) 7 b BLOCK8 (KEY4) 0 b BLOCK8 (KEY4) 1 b
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0x0078 0x007C 0x0080 0x0084 0x0088 0x008C 0x0090 0x0094 0x0098 0x009C 0x00A0 0x00A4 0x00A8 0x00AC 0x00B0 0x00B4 0x00B8 0x00BC 0x00C0 0x00C4 0x00C8 0x00CC 0x00D0 0x00D4 0x00D8 0x00DC 0x00E0 0x00E4 0x00E8 0x00EC 0x00F0 0x00F4 0x00F8 0x00FC 0x0100 0x0104 0x0108 0x010C 0x0110 0x0114 0x0118 0x011C 0x0120
132
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
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EFUSE_RD_KEY4_DATA2_REG EFUSE_RD_KEY4_DATA3_REG EFUSE_RD_KEY4_DATA4_REG EFUSE_RD_KEY4_DATA5_REG EFUSE_RD_KEY4_DATA6_REG EFUSE_RD_KEY4_DATA7_REG EFUSE_RD_KEY5_DATA0_REG EFUSE_RD_KEY5_DATA1_REG EFUSE_RD_KEY5_DATA2_REG EFUSE_RD_KEY5_DATA3_REG EFUSE_RD_KEY5_DATA4_REG EFUSE_RD_KEY5_DATA5_REG EFUSE_RD_KEY5_DATA6_REG EFUSE_RD_KEY5_DATA7_REG EFUSE_RD_SYS_DATA_PART2_0_REG EFUSE_RD_SYS_DATA_PART2_1_REG EFUSE_RD_SYS_DATA_PART2_2_REG EFUSE_RD_SYS_DATA_PART2_3_REG EFUSE_RD_SYS_DATA_PART2_4_REG EFUSE_RD_SYS_DATA_PART2_5_REG EFUSE_RD_SYS_DATA_PART2_6_REG EFUSE_RD_SYS_DATA_PART2_7_REG EFUSE_RD_REPEAT_ERR0_REG EFUSE_RD_REPEAT_ERR1_REG EFUSE_RD_REPEAT_ERR2_REG EFUSE_RD_REPEAT_ERR3_REG EFUSE_RD_REPEAT_ERR4_REG
EFUSE_RD_RS_ERR0_REG
EFUSE_RD_RS_ERR1_REG
/ EFUSE_CLK_REG EFUSE_CONF_REG EFUSE_CMD_REG EFUSE_DAC_CONF_REG EFUSE_STATUS_REG EFUSE_INT_RAW_REG EFUSE_INT_ST_REG EFUSE_INT_ENA_REG EFUSE_INT_CLR_REG
BLOCK8 (KEY4) 2 b BLOCK8 (KEY4) 3 b BLOCK8 (KEY4) 4 b BLOCK8 (KEY4) 5 b BLOCK8 (KEY4) 6 b BLOCK8 (KEY4) 7 b BLOCK9 (KEY5) 0 b BLOCK9 (KEY5) 1 b BLOCK9 (KEY5) 2 b BLOCK9 (KEY5) 3 b BLOCK9 (KEY5) 4 b BLOCK9 (KEY5) 5 b BLOCK9 (KEY5) 6 b BLOCK9 (KEY5) 7 b BLOCK10 (system) 0 b BLOCK10 (system) 1 b BLOCK10 (system) 2 b BLOCK10 (system) 3 b BLOCK10 (system) 4 b BLOCK10 (system) 5 b BLOCK10 (system) 6 b BLOCK10 (system) 7 b
BLOCK0 0 b BLOCK0 1 b BLOCK0 2 b BLOCK0 3 b BLOCK0 4 b BLOCK1-10 0 b BLOCK1-10 1 b
eFuse b eFuse b eFuse b eFuse b eFuse b
eFuse b eFuse b eFuse b eFuse b
0x0124 0x0128 0x012C 0x0130 0x0134 0x0138 0x013C 0x0140 0x0144 0x0148 0x014C 0x0150 0x0154 0x0158 0x015C 0x0160 0x0164 0x0168 0x016C 0x0170 0x0174 0x0178
0x017C 0x0180 0x0184 0x0188 0x0190
0x01C0
0x01C4
0x01C8 0x01CC 0x01D4 0x01E8 0x01D0
/ / / /
0x01D8 0x01DC 0x01E0 0x01E4
/
133
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
EFUSE_RD_TIM_CONF_REG EFUSE_WR_TIM_CONF0_REG EFUSE_WR_TIM_CONF1_REG EFUSE_WR_TIM_CONF2_REG EFUSE_DATE_REG
eFuse b eFuse 0 b eFuse 1 b eFuse 2 b
b
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0x01EC 0x01F0 0x01F4 0x01F8
/ / / /
0x01FC /
4.6
Register 4.1. EFUSE_PGM_DATAn_REG (n: 0-7) (0x0000+4*n)
EFUSE_PGM_DATA_n
31
0x000000
EFUSE_PGM_DATA_n n 32 bc/
0
Reset
Register 4.2. EFUSE_PGM_CHECK_VALUEn_REG (n: 0-2) (0x0020+4*n)
EFUSE_PGM_RS_DATA_n
31
0x000000
EFUSE_PGM_RS_DATA_n RS n 32 bc/
0
Reset
Register 4.3. EFUSE_RD_WR_DIS_REG (0x002C)
EFUSE_WR_DIS
31
0x000000
EFUSE_WR_DIS eFuse b1: b0: bc
0
Reset
134
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
GoBack
Register 4.4. EFUSE_RD_REPEAT_DATA0_REG (0x0030)
(reserved)
EFUSE_REPFTU4S_EER_FEUUSSSEBEER__FVEUFEOXSDTRE0__CPUEHS_YBN__OEE(PNrXeEACsRBHeSLrGIvSE_eTPdI)NS EFUSEE_FDUISSEE__FDHUOASWREE_NDFSU_LOOSDAFEEISDT_F__RU_JDPMSTTIEEASA4_FG_N_DUJURISTSAEAEE_LSG_F_BEDUEORISNSVOEEC_ET_FCRD_DUYA5RISPNSEEET_M_FUADUSPISBSEE__FFDUOISRSEEC__FDEDU_OISDSWEE_O_NFDWDULOONISSWAELE_OD_NFDDAU_LCODDISSAAEC_CD_AIHCD_CEAIIHCSCE_AHCRETHCE_RAME_FBUOSOET_RD_DIS
31
29 28 27 26 25 24 23
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6
0
0 0 0 0x0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x0
Reset
EFUSE_RD_DIS eFuse BLOCK4 ~ 10 b1b0bc EFUSE_DIS_RTC_RAM_BOOT bc EFUSE_DIS_ICACHE ICacheb1b0bc EFUSE_DIS_DCACHE DCacheb1b0bc EFUSE_DIS_DOWNLOAD_ICACHE ICacheb1b0bc EFUSE_DIS_DOWNLOAD_DCACHE DCacheb1b0bc
EFUSE_DIS_FORCE_DOWNLOAD b1b0bc
EFUSE_DIS_USB USB OTG b1b0bc EFUSE_DIS_CAN TWAI b1b0bc EFUSE_DIS_BOOT_REMAP RAM ROM b1b0bc EFUSE_RPT4_RESERVED5 c 4 bc EFUSE_SOFT_DIS_JTAG JTAG b1b0b
HAMC JTAGbc EFUSE_HARD_DIS_JTAG JTAG b1b0bc EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT download boot flash
b1b0bc EFUSE_USB_EXCHG_PINS USB D+ D- b1b0bc EFUSE_EXT_PHY_ENABLE USB PHYb1b0bc EFUSE_USB_FORCE_NOPERSIST USB BAVLID 1b1b0bc
EFUSE_RPT4_RESERVED0 c 4 bc
135
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
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Register 4.5. EFUSE_RD_REPEAT_DATA1_REG (0x0034)
EFUSE_KEY_PURPOSEE_F1USE_KEY_PEUFRUPSOEE_SFSEU_ESC0EEU_FSRUEESC_EUB_OSREEOC_TEUB_FORUKEEOS_YET_B__ROSKEPEOVIYT_O__BKRKEOEEEFO2VYUTO_S_KRECEE_R1VWYODPKTTE__0DCENLTAY_SEL
(reserved)
31
28 27
24 23 22 21 20
18 17 16 15
EFUSEE_FVUDSDEE__FVSUDPSDIE___FVSODPRDIC__TESI(ErPeHIs_eXrPvDed)
76 5 43
0
0x0
0x0
000
0x0
0x0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
EFUSE_VDD_SPI_XPD VDD_SPI_FORCE 1 VDD_SPI b1b0 bc
EFUSE_VDD_SPI_TIEH VDD_SPI_FORCE 1 VDD_SPI b0VDD_SPI 1.8 V LDOb1VDD_SPI VDD_RTC_IObc
EFUSE_VDD_SPI_FORCE EFUSE_VDD_SPI_XPD EFUSE_VDD_SPI_TIEH VDD_SPIb1b0bc
EFUSE_WDT_DELAY_SEL RTC bb00: 40,000 b01: 80,000 b10: 160,000 b11: 320,000 bc
EFUSE_SPI_BOOT_CRYPT_CNT SPI boot b 1b 1cb
EFUSE_SECURE_BOOT_KEY_REVOKE0 b1b0 bc
EFUSE_SECURE_BOOT_KEY_REVOKE1 b1b0 bc
EFUSE_SECURE_BOOT_KEY_REVOKE2 b1b0 bc
EFUSE_KEY_PURPOSE_0 KEY0 purpose 4.3-2bc
EFUSE_KEY_PURPOSE_1 KEY1 purpose 4.3-2bc
136
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
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Register 4.6. EFUSE_RD_REPEAT_DATA2_REG (0x0038)
EFUSE_FLASH_TPUW
EFUSE_RPT4_RESEERFVUESDEE1_FSUESCEU_SREEC_UBOR(rEOe_TsBe_rOAvGOeGTd_)REENSSIVE_REEVFOUKSEE_KEY_PURPOSEE_F5USE_KEY_PURPOSEE_F4USE_KEY_PURPOSEE_F3USE_KEY_PURPOSE_2
31
28 27
22 21 20 19
16 15
12 11
87
43
0
0x0
0x0
0 00 0 0 0
0x0
0x0
0x0
0x0
Reset
EFUSE_KEY_PURPOSE_2 KEY2 purpose 4.3-2bc EFUSE_KEY_PURPOSE_3 KEY3 purpose 4.3-2bc EFUSE_KEY_PURPOSE_4 KEY4 purpose 4.3-2bc EFUSE_KEY_PURPOSE_5 KEY5 purpose 4.3-2bc EFUSE_SECURE_BOOT_EN b1b0bc EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE b1b0
bc EFUSE_RPT4_RESERVED1 c 4 bc EFUSE_FLASH_TPUW flash bmsb 15
b 15 30 msbc
137
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
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Register 4.7. EFUSE_RD_REPEAT_DATA3_REG (0x003C)
EFUSE_RPT4_RESERVED2
31
27 26
0x0
EFUSE_SECURE_VERSION 0x00
EFUSEE_FFUOSREEC_FFUEL_SASESE_HNPE_DIFNTU_Y_RSPPEEEOS_WUUEAEMFRRUET_S_SEEPE_FLREUEINSNCAEETTB_F_IODULCENISOS_EEN_S_FUTERURSCPSOBUTEE_LR4_FD_IUUTORASYWER_EEST_DNFE_DUOLRPOISWSVRAE_ENI_DNDLLD_ET3OIMG_SACA_ODCHDDYAOE_NWSNNPEILL_OBAODO_TMODE
11 10 9 8 7
65 4 3 2 1 0
0 0 0 0x0 0 0 0 0 0 0 Reset
EFUSE_DIS_DOWNLOAD_MODE b1b0bc
EFUSE_DIS_LEGACY_SPI_BOOT Legacy SPI boot b1b0bc
EFUSE_UART_PRINT_CHANNEL boot UART b0UART0b1UART1bc
EFUSE_RPT4_RESERVED3 c 4 bc
EFUSE_DIS_USB_DOWNLOAD_MODE UART download boot USB b1 b0bc
EFUSE_ENABLE_SECURITY_DOWNLOAD UART c flashb 1b0bc
EFUSE_UART_PRINT_CONTROL UART b00b01 GPIO 46 b10 GPIO 46 b11bc
EFUSE_PIN_POWER_SELECTION SPI flash GPIO33-GPIO37 b0 VDD3P3_CPUb1VDD_SPIbc
EFUSE_FLASH_TYPE flash b04 b18 bc
EFUSE_FORCE_SEND_RESUME ROM SPI b1b 0bc
EFUSE_SECURE_VERSION ESP-IDF bc
EFUSE_RPT4_RESERVED2 c 4 bc
138
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
Register 4.8. EFUSE_RD_REPEAT_DATA4_REG (0x0040)
(reserved)
31
24 23
00000000
EFUSE_RPT4_RESERVED4 0x0000
EFUSE_RPT4_RESERVED4 c 4 bc
Register 4.9. EFUSE_RD_MAC_SPI_SYS_0_REG (0x0044)
EFUSE_MAC_0
31
0x000000
EFUSE_MAC_0 MAC 32 bc
Register 4.10. EFUSE_RD_MAC_SPI_SYS_1_REG (0x0048)
EFUSE_SPI_PAD_CONF_0
EFUSE_MAC_1
31
16 15
0x00
0x00
EFUSE_MAC_1 MAC 16 bc EFUSE_SPI_PAD_CONF_0 SPI_PAD_CONF 0 bc
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0
Reset
0
Reset
0
Reset
139
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
Register 4.11. EFUSE_RD_MAC_SPI_SYS_2_REG (0x004C)
EFUSE_SPI_PAD_CONF_1
31
0x000000
EFUSE_SPI_PAD_CONF_1 SPI_PAD_CONF 1 bc
Register 4.12. EFUSE_RD_MAC_SPI_SYS_3_REG (0x0050)
EFUSE_SYS_DATA_PART0_0
31
18 17
0x00
EFUSE_SPI_PAD_CONF_2 0x000
EFUSE_SPI_PAD_CONF_2 SPI_PAD_CONF 2 bc EFUSE_SYS_DATA_PART0_0 0 0 bc
Register 4.13. EFUSE_RD_MAC_SPI_SYS_4_REG (0x0054)
EFUSE_SYS_DATA_PART0_1
31
0x000000
EFUSE_SYS_DATA_PART0_1 0 1 bc
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0
Reset
0
Reset
0
Reset
140
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
Register 4.14. EFUSE_RD_MAC_SPI_SYS_5_REG (0x0058)
EFUSE_SYS_DATA_PART0_2
31
0x000000
EFUSE_SYS_DATA_PART0_2 0 2 bc
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0
Reset
Register 4.15. EFUSE_RD_SYS_DATA_PART1_n_REG (n: 0-7) (0x005C+4*n)
EFUSE_SYS_DATA_PART1_n
31
0x000000
EFUSE_SYS_DATA_PART1_n 1 n 32 bc
0
Reset
Register 4.16. EFUSE_RD_USR_DATAn_REG (n: 0-7) (0x007C+4*n)
EFUSE_USR_DATAn
31
0x000000
EFUSE_USR_DATAn BLOCK3 (user) n 32 bc
0
Reset
141
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
Register 4.17. EFUSE_RD_KEY0_DATAn_REG (n: 0-7) (0x009C+4*n)
EFUSE_KEY0_DATAn
31
0x000000
EFUSE_KEY0_DATAn KEY0 n 32 bc
Register 4.18. EFUSE_RD_KEY1_DATAn_REG (n: 0-7) (0x00BC+4*n)
EFUSE_KEY1_DATAn
31
0x000000
EFUSE_KEY1_DATAn KEY1 n 32 bc
Register 4.19. EFUSE_RD_KEY2_DATAn_REG (n: 0-7) (0x00DC+4*n)
EFUSE_KEY2_DATAn
31
0x000000
EFUSE_KEY2_DATAn KEY2 n 32 bc
Register 4.20. EFUSE_RD_KEY3_DATAn_REG (n: 0-7) (0x00FC+4*n)
EFUSE_KEY3_DATAn
31
0x000000
EFUSE_KEY3_DATAn KEY3 n 32 bc
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0
Reset
0
Reset
0
Reset
0
Reset
142
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
Register 4.21. EFUSE_RD_KEY4_DATAn_REG (n: 0-7) (0x011C+4*n)
EFUSE_KEY4_DATAn
31
0x000000
EFUSE_KEY4_DATAn KEY4 n 32 bc
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0
Reset
Register 4.22. EFUSE_RD_KEY5_DATAn_REG (n: 0-7) (0x013C+4*n)
EFUSE_KEY5_DATAn
31
0x000000
EFUSE_KEY5_DATAn KEY5 n 32 bc
0
Reset
Register 4.23. EFUSE_RD_SYS_DATA_PART2_n_REG (n: 0-7) (0x015C+4*n)
EFUSE_SYS_DATA_PART2_n
31
0x000000
EFUSE_SYS_DATA_PART2_n 2 n 32 bc
0
Reset
143
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
GoBack
Register 4.24. EFUSE_RD_REPEAT_ERR0_REG (0x017C)
(reserved)
EFUSE_REPFTU4S_EER_FEUUSSSEBEER__FVEUFEOXSDTRE0__C_PUEEHS_RYBNR__OEE(PNrXeEACsRBHeSLrGIvSE_eT_Pd_EI)ENRRRSR_EEFRURSEE_FDUISSEE__FDHUOASWREE_NDFSU_LOOSDAFEEISDT_F__RU_JDPMSTTIEEASA4_FG_N_DU_JURISETSAEAERE_LSG_FR_BEDU_EOREISNSVOREEC_ETR_FCRD_DUYA5RISPNS_EEET_E_M_F_UREADUERRSPISRRBS_ERE__E_FFERDUORRISRRSEEC__FDEDU_OISDSWEE_O_NFDWDULOONISSWAELE_OD_NFDDAU_LCODDISSAA_EC_CD_EAIHCRD_CEARIIHCS_CE_AEH_CRREETRH_RCEER__RRERARMRE_FBUOSOET__REDR_RDIS_ERR
31
29 28 27 26 25 24 23
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6
0
0 0 0 0x0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x0
Reset
EFUSE_RD_DIS_ERR 1 EFUSE_RD_DIS bc
EFUSE_DIS_RTC_RAM_BOOT_ERR
1
EFUSE_DIS_RTC_RAM_BOOT bc
EFUSE_DIS_ICACHE_ERR 1 EFUSE_DIS_ICACHE bc
EFUSE_DIS_DCACHE_ERR 1 EFUSE_DIS_DCACHE bc
EFUSE_DIS_DOWNLOAD_ICACHE_ERR
1
EFUSE_DIS_DOWNLOAD_ICACHE bc
EFUSE_DIS_DOWNLOAD_DCACHE_ERR
1
EFUSE_DIS_DOWNLOAD_DCACHE bc
EFUSE_DIS_FORCE_DOWNLOAD_ERR
1
EFUSE_DIS_FORCE_DOWNLOAD bc
EFUSE_DIS_USB_ERR 1 EFUSE_DIS_USB bc
EFUSE_DIS_CAN_ERR 1 EFUSE_DIS_CAN bc
EFUSE_DIS_BOOT_REMAP_ERR 1 EFUSE_DIS_BOOT_REMAP bc
EFUSE_RPT4_RESERVED5_ERR 1 EFUSE_RPT4_RESERVED5 bc
EFUSE_SOFT_DIS_JTAG_ERR 1 EFUSE_SOFT_DIS_JTAG bc
EFUSE_HARD_DIS_JTAG_ERR 1 EFUSE_HARD_DIS_JTAG bc
b
144
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse) Register 4.24. EFUSE_RD_REPEAT_ERR0_REG (0x017C)
GoBack
b
EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR 1 EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT b c
EFUSE_USB_EXCHG_PINS_ERR 1 EFUSE_USB_EXCHG_PINS bc
EFUSE_EXT_PHY_ENABLE_ERR 1 EFUSE_EXT_PHY_ENABLE bc
EFUSE_USB_FORCE_NOPERSIST_ERR 1 EFUSE_USB_FORCE_B bc
EFUSE_RPT4_RESERVED0_ERR 1 EFUSE_RPT4_RESERVED0 bc
145
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
GoBack
Register 4.25. EFUSE_RD_REPEAT_ERR1_REG (0x0180)
EFUSE_KEY_PURPOSEE_F1U_SEER_RKEY_PEUFRUPSOEE_SFSEU_ESC0EE_U_FESRUREESRC_EUB_OSREEOC_TEUB_FORUKEEOS_YET_B__ROSKEPEOVIYT_O__BKRKEOEEEFO2VYUT_O_S_EKRECREE_RR1VW_YODEPKTRTE_R_0DC_ENELTRA_RYE_RSREL_ERR(reserved)
31
28 27
24 23 22 21 20
18 17 16 15
EFUSEE_FVUDSDEE__FVSUDPSDIE___FVSODPRDIC__TESI(_ErPeEHIsR__eRXErPRvDeRd_)ERR
76 5 43
0
0x0
0x0
000
0x0
0x0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
EFUSE_VDD_SPI_XPD_ERR 1 EFUSE_VDD_SPI_XPD bc
EFUSE_VDD_SPI_TIEH_ERR 1 EFUSE_VDD_SPI_TIEH bc
EFUSE_VDD_SPI_FORCE_ERR 1 EFUSE_VDD_SPI_FORCE bc
EFUSE_WDT_DELAY_SEL_ERR 1 EFUSE_WDT_DELAY_SEL bc
EFUSE_SPI_BOOT_CRYPT_CNT_ERR
1
EFUSE_SPI_BOOT_CRYPT_CNT bc
EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR
1
EFUSE_SECURE_BOOT_KEY_REVOKE0 bc
EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR
1
EFUSE_SECURE_BOOT_KEY_REVOKE1 bc
EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR
1
EFUSE_SECURE_BOOT_KEY_REVOKE2 bc
EFUSE_KEY_PURPOSE_0_ERR 1 EFUSE_KEY_PURPOSE_0 bc
EFUSE_KEY_PURPOSE_1_ERR 1 EFUSE_KEY_PURPOSE_1 bc
146
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
GoBack
Register 4.26. EFUSE_RD_REPEAT_ERR2_REG (0x0184)
EFUSE_FLASH_TPUW_ERR EFUSE_RPT4_RESEERFVUESDEE1_F_SUEERSCREU_SREEC_UBOR(rEOe_TsBe_rOAvGOeGTd_)REENSS_IEVRER_REEVFOUKSEE__EKRERY_PURPOSEE_F5U_SEER_RKEY_PURPOSEE_F4U_SEER_RKEY_PURPOSEE_F3U_SEER_RKEY_PURPOSE_2_ERR
31
28 27
22 21 20 19
16 15
12 11
87
43
0
0x0
0x0
0 00 0 0 0
0x0
0x0
0x0
0x0
Reset
EFUSE_KEY_PURPOSE_2_ERR 1 EFUSE_KEY_PURPOSE_2 bc
EFUSE_KEY_PURPOSE_3_ERR 1 EFUSE_KEY_PURPOSE_3 bc
EFUSE_KEY_PURPOSE_4_ERR 1 EFUSE_KEY_PURPOSE_4 bc
EFUSE_KEY_PURPOSE_5_ERR 1 EFUSE_KEY_PURPOSE_5 bc
EFUSE_SECURE_BOOT_EN_ERR 1 EFUSE_SECURE_BOOT_EN bc
EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR 1 EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE b c
EFUSE_RPT4_RESERVED1_ERR 1 EFUSE_RPT4_RESERVED1 bc
EFUSE_FLASH_TPUW_ERR 1 EFUSE_FLASH_TPUM bc
147
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
GoBack
Register 4.27. EFUSE_RD_REPEAT_ERR3_REG (0x0188)
EFUSE_RPT4_RESERVED2_ERR
31
27 26
0x0
EFUSE_SECURE_VERSION_ERR 0x00
EFUSEE_FFUOSREEC_FFUEL_SASESE_HNPE_DIFNTU_Y_RSPPEEEOS__WUUEEAEMFRRRURET_S__SEEEPE_FRLREUREINSNCAEETTB_F_IODULCENISOS_E_EN_S_FEUTERURRSCPRSOBUTEE_LR4_F_D_IUUTEORASYRWER_EERST_DNFE_DUOLRPOISWSVRAE_ENI_DNDLLD_ET3OIMG_S_ACA_OEDCHRDD_YAROEE_NR_WSNRENPERILL_RO_BAEODRO_RTM_OEDRRE_ERR
11 10 9 8 7
65 4 3 2 1 0
0 0 0 0x0 0 0 0 0 0 0 Reset
EFUSE_DIS_DOWNLOAD_MODE_ERR
1
EFUSE_DIS_DOWNLOAD_MODE bc
EFUSE_DIS_LEGACY_SPI_BOOT_ERR
1
EFUSE_DIS_LEGACY_SPI_BOOT bc
EFUSE_UART_PRINT_CHANNEL_ERR
1
EFUSE_UART_PRINT_CHANNEL bc
EFUSE_RPT4_RESERVED3_ERR 1 EFUSE_RPT4_RESERVED3 bc
EFUSE_DIS_USB_DOWNLOAD_MODE_ERR
1
EFUSE_DIS_USB_DOWNLOAD_MODE bc
EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR 1 EFUSE_ENABLE_SECURITY_DOWNLOAD b c
EFUSE_UART_PRINT_CONTROL_ERR
1
EFUSE_UART_PRINT_CONTROL bc
EFUSE_PIN_POWER_SELECTION_ERR
1
EFUSE_PIN_POWER_SELECTION bc
EFUSE_FLASH_TYPE_ERR 1 EFUSE_FLASH_TYPE bc
EFUSE_FORCE_SEND_RESUME_ERR
1
EFUSE_FORCE_SEND_RESUME bc
EFUSE_SECURE_VERSION_ERR 1 EFUSE_SECURE_VERSION bc
EFUSE_RPT4_RESERVED2_ERR 1 EFUSE_RPT4_RESERVED2 bc
148
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
GoBack
Register 4.28. EFUSE_RD_REPEAT_ERR4_REG (0x0190)
(reserved)
31
24 23
00000000
EFUSE_RPT4_RESERVED4_ERR 0x0000
0
Reset
EFUSE_RPT4_RESERVED4_ERR 1 EFUSE_RPT4_RESERVED4 bc
Register 4.29. EFUSE_RD_RS_ERR0_REG (0x01C0)
EFUSE_KEYE4F_UFSAEIL_KEYE4F_UESRER__KNEUYEM3F_UFSAEIL_KEYE3F_UESRER__KNEUYE2MF_UFSAEIL_KEYE2F_UESRER__KNEUYE1MF_UFSAEIL_KEYE1F_UESRER__KNEUYEM0F_UFSAEI_LKEYE0F_UESRER__UNSUREM_FDUASTEA__UFSAREIL_FDUASTEA__SEYRSER_F_PUNASURETM_1S_YFSAE_IFLPUASRET_1M_NAEUCFM_USSPEI__8MMA_CF_ASILPI_8M_ERR_NUM
31 30
28 27 26
24 23 22
20 19 18
16 15 14
12 11 10
876
432
0
0
0x0
0
0x0
0
0x0
0
0x0
0
0x0
0
0x0
0
0x0
0
0x0 Reset
EFUSE_MAC_SPI_8M_ERR_NUM BLOCK1 bc
EFUSE_MAC_SPI_8M_FAIL 0BLOCK1 1 BLOCK1 5 bc
EFUSE_SYS_PART1_NUM BLOCK2 bc
EFUSE_SYS_PART1_FAIL 0BLOCK2 1 BLOCK2 5 bc
EFUSE_USR_DATA_ERR_NUM BLOCK3 bc
EFUSE_USR_DATA_FAIL 0BLOCK3 1 BLOCK3 5 bc
EFUSE_KEYn_ERR_NUM KEYn bc
EFUSE_KEYn_FAIL 0keyn 1 keyn 5 bc
149
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
GoBack
Register 4.30. EFUSE_RD_RS_ERR1_REG (0x01C4)
(reserved)
EFUSE_SYSE_FPUASRET_2S_YFSEA_FILPUASRET_2K_EEYER5FR_U_FSNAEUIL_MKEY5_ERR_NUM
31
876
432
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00
0x0
0
0x0 Reset
EFUSE_KEY5_ERR_NUM KEY5 bc
EFUSE_KEY5_FAIL 0KEY5 1 KEY5 5 bc
EFUSE_SYS_PART2_ERR_NUM BLOCK10 bc
EFUSE_SYS_PART2_FAIL 0BLOCK10 1 BLOCK10 5 bc
Register 4.31. EFUSE_CLK_REG (0x01C8)
(reserved)
EFUSE_CLK_EN
(reserved)
EFUSEE_FEUFSUEES_FEMU_SEMEM_E_EMCF_LUFKSO_EFR_OCMREEC_MPE_U_OFONRCE_PD
31
17 16 15
32 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Reset
EFUSE_EFUSE_MEM_FORCE_PD eFuse SRAM bc/ EFUSE_MEM_CLK_FORCE_ON eFuse SRAM bc/ EFUSE_EFUSE_MEM_FORCE_PU eFuse SRAM bc/ EFUSE_CLK_EN eFuse memory bc/
150
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
Register 4.32. EFUSE_CONF_REG (0x01CC)
(reserved)
31
16 15
0000000000000000
EFUSE_OP_CODE 0x00
EFUSE_OP_CODE 0x5A5A0x5AA5bc/
GoBack
0
Reset
Register 4.33. EFUSE_CMD_REG (0x01D4)
(reserved)
31
65
00000000000000000000000000
EFUSE_BLK_NEUFUMSEE_FPUGSEM__RCEMADD_CMD
21 0
0x0
0 0 Reset
EFUSE_READ_CMD bc/ EFUSE_PGM_CMD bc/ EFUSE_BLK_NUM 0-10 BLOCK0-10bc/
Register 4.34. EFUSE_DAC_CONF_REG (0x01E8)
(reserved)
EFUSE_OE_CLR
31
18 17 16
0 0 0 0 0 0 0 0 0 0 0 0 0 00
EFUSE_DAC_NUM
EFUSE_DAC_CLK_PAD_SEEFLUSE_DAC_CLK_DIV
987
0
255
0
28
Reset
EFUSE_DAC_CLK_DIV bc/ EFUSE_DAC_CLK_PAD_SEL bc/ EFUSE_DAC_NUM bc/ EFUSE_OE_CLR bc/
151
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
GoBack
Register 4.35. EFUSE_STATUS_REG (0x01D0)
(reserved)
31
18 17
00000000000000
EFUSE_REPEAT_ERR_CNT
10 9
(reserved)
43
0x0
000000
EFUSE_STATE
0
0x0
Reset
EFUSE_STATE eFuse bc EFUSE_REPEAT_ERR_CNT BLOCK0 bc
Register 4.36. EFUSE_INT_RAW_REG (0x01D8)
(reserved)
EFUSEE_FPUGSEM__RDEOANDE__DIONNT_ER_AINWT_RAW
31
21 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
EFUSE_READ_DONE_INT_RAW bc EFUSE_PGM_DONE_INT_RAW bc
Register 4.37. EFUSE_INT_ST_REG (0x01DC)
(reserved)
EFUSEE_FPUGSEM__RDEOANDE__DIONNT_ES_TINT_ST
31
21 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
EFUSE_READ_DONE_INT_ST bc EFUSE_PGM_DONE_INT_ST bc
152
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
GoBack
Register 4.38. EFUSE_INT_ENA_REG (0x01E0)
(reserved)
EFUSEE_FPUGSEM__RDEOANDE__DIONNT_EE_NINAT_ENA
31
21 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
EFUSE_READ_DONE_INT_ENA bc/ EFUSE_PGM_DONE_INT_ENA bc/
Register 4.39. EFUSE_INT_CLR_REG (0x01E4)
(reserved)
EFUSEE_FPUGSEM__RDEOANDE__DIONNT_EC_LINRT_CLR
31
21 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
EFUSE_READ_DONE_INT_CLR bc EFUSE_PGM_DONE_INT_CLR bc
Register 4.40. EFUSE_RD_TIM_CONF_REG (0x01EC)
EFUSE_READ_INIT_NUM
31
24 23
0x12
EFUSE_TSUR_A
16 15
0x1
EFUSE_TRD
87
0x1
EFUSE_THR_A bc/ EFUSE_TRD bc/ EFUSE_TSUR_A bc/ EFUSE_READ_INIT_NUM eFuse bc/
EFUSE_THR_A 0x1
0
Reset
153
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
Register 4.41. EFUSE_WR_TIM_CONF0_REG (0x01F0)
EFUSE_TPGM
EFUSE_TPGM_INACTIVE
31
16 15
87
0xc8
0x1
EFUSE_THP_A bc/ EFUSE_TPGM_INACTIVE eFuse 0 bc/ EFUSE_TPGM eFuse 1 bc/
GoBack
EFUSE_THP_A 0x1
0
Reset
Register 4.42. EFUSE_WR_TIM_CONF1_REG (0x01F4)
(reserved)
31
24 23
00000000
EFUSE_PWR_ON_NUM
87
0x2880
EFUSE_TSUP_A bc/ EFUSE_PWR_ON_NUM VDDQ bc/
EFUSE_TSUP_A
0
0x1
Reset
Register 4.43. EFUSE_WR_TIM_CONF2_REG (0x01F8)
(reserved)
31
16 15
0000000000000000
EFUSE_PWR_OFF_NUM 0x190
EFUSE_PWR_OFF_NUM VDDQ bc/
0
Reset
154
ESP32-S2 TRM ( 1.3)
4 eFuse (eFuse)
Register 4.44. EFUSE_DATE_REG (0x01FC)
EFUSE_DATE
31
0x19081100
EFUSE_DATE bc/
GoBack
0
Reset
155
ESP32-S2 TRM ( 1.3)
GoBack
III
aGPIOaaaa b
156
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
5
IO MUX GPIO
5.1
ESP32-S2 43 GPIO padb pad IObIO MUXa RTC IO MUX GPIO GPIO padb IO b 43 GPIO pad 0 ~ 21, 26 ~ 46b GPIO46 b GPIO aIO MUX RTC IO MUX 43 padcDRVaIEa OEaWPUaWPD
· 116 cSIG_IN_SELaSIG_OUT_SELaIEaOE · 182 cSIG_IN_SELaSIG_OUT_SELaIEaOE · cIEaOE · 22 RTC GPIO
5.1-1. IO MUXaRTC IO MUX GPIO
157
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
5.1-1 IO MUXaRTC IO MUX GPIO b 1. IO MUX GPIO pad IO_MUX_n_REG pad · GPIO GPIO · GPIO b SPIaJTAGaUART GPIO b IO MUX b 5.11 GPIO pad IO MUX b 2. GPIO b · 116 GPIO pad b · GPIO pad 182 b 5.10 GPIO b 3. RTC IO MUX GPIO pad b GPIO pad b 5.12 RTC IO MUX b
5.2 GPIO
5.2.1
GPIO GPIO 43 GPIOc0 ~ 21, 26 ~ 46 5.10-1b GPIO b
5.2.2
5.1-1 pad GPIO SYNC APB GPIO b IO MUX GPIO SYNC b
5.2-1. GPIO clock
158
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
GPIO SYNC 5.2-1 bnegative sync GPIO input APB clock positive sync GPIO input APB clock b
5.2.3
Y GPIO pad X 1. GPIO Y GPIO_FUNCy_IN_SEL_CFG_REG · GPIO_SIGy_IN_SEL GPIO · GPIO_FUNCy_IN_SEL GPIO pad X b : GPIO_SIGy_IN_SEL 5.1-1 MUX c 1 b GPIO b 2. IO_MUX_FILTER_EN pad 5.2-2 b bb
5.2-2. GPIO
3. GPIO pad X GPIO_PINx_REG GPIO input · 5.2-1 , GPIO_PINx_SYNC1_BYPASS b · 5.2-1 , GPIO_PINx_SYNC2_BYPASS b
4. GPIO pad X IO_MUX_x_REG pad · IO_MUX_FUN_IE · IO_MUX_FUN_WPU IO_MUX_FUN_WPD/b
RMT 0 rmt_sig_in0c 83 GPIO40 c GPIO40 MTDO
1. GPIO_FUNC83_IN_SEL_CFG_REG GPIO_SIG83_IN_SEL GPIO
2. GPIO_FUNC83_IN_SEL_CFG_REG GPIO_FUNC83_IN_SEL 40 3. IO_MUX_GPIO40_REG IO_MUX_FUN_IEcb · pad input_signalsb · GPIO_FUNCy_IN_INV_SEL b · pad b
GPIO_FUNCy_IN_SEL GPIO
159
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
GPIO_FUNCy_IN_SEL 0x3C input_signal_X 0 GPIO_FUNCy_IN_SEL 0x38 input_signal_X 1b
5.2.4 GPIO
GPIO_IN_REG/GPIO_IN1_REG GPIO pad b GPIO pad GPIO b pad X IO_MUX_n_REG IO_MUX_FUN_IE 5.2.2 b
5.3 GPIO
5.3.1
GPIO GPIO ( 0 ~ 1114 ~ 18, ...) 42 GPIO (0 ~ 21, 26 ~ 45)b 5.10-1b GPIO IO MUXbIO MUX pad GPIO GPIO padb
223 ~ 227 GPIO GPIO b
5.3.2
5.1-1 182 GPIO IO MUX padb
Y GPIO pad X
1. GPIO GPIO pad X GPIO_FUNCx_OUT_SEL_CFG_REG GPIO_ENABLE_REG[x] b W1TS W1TC GPIO_ENABLE_REG
· GPIO_FUNCx_OUT_SEL_CFG_REG GPIO_FUNCx_OUT_SEL Y (Y)b
· GPIO pad X GPIO_FUNCx_OUT_SEL_CFG_REG GPIO_FUNCx_OEN_SEL GPIO_ENABLE_W1TS_REG GPIO_ENABLE1_W1TS_REG b GPIO_FUNCx_OEN_SEL b 5.10-1 o pb
· GPIO_ENABLE_W1TC_REG GPIO_ENABLE1_W1TC_REG GPIO pad b
2. GPIO pad X GPIO_PINx_REG GPIO_PINx_PAD_DRIVER b
3. IO MUX GPIO b GPIO pad X IO_MUX_x_REG
· IO_MUX_MCU_SEL GPIO pad X IO MUX c Function 1 1b
160
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
· IO_MUX_FUN_DRV (0 ~ 3) 0: ~5 mA 1: ~10 mA 2: ~20 mAc 3: ~40 mA
· / IO_MUX_FUN_WPU IO_MUX_FUN_WPD / b
· pad b · GPIO46 b · GPIO_FUNCn_OUT_INV_SEL b
5.3.3 GPIO
GPIO GPIO · GPIO GPIO_FUNCn_OUT_SEL 256 (0x100) · GPIO_OUT_REG[31:0] GPIO_OUT1_REG[21:0] GPIO b
· GPIO_OUT_REG[0] ~ GPIO_OUT_REG[31] GPIO0 ~ GPIO31GPIO_OUT_REG[25:22] · GPIO_OUT1_REG[0] ~ GPIO_OUT1_REG[13] GPIO32 ~ GPIO45GPIO_OUT1_REG[21:14] b · W1TS (write 1 to set) W1TC (write 1 to clear) GPIO_OUT_W1TS/GPIO_OUT_W1TC GPIO_OUT_REG GPIO_OUT1_REG b
5.3.4 Sigma Delta (SDM)
5.3.4.1
182 8 1 Sigma Delta 8 100 ~ 107b PDMcb Sigma Delta
H(z) = X(z)z-1 + E(z)(1-z-1)2
E(z) X(z) b Sigma Delta APB_CLK 1 ~ 256
· GPIOSD_FUNCTION_CLK_EN · GPIOSD_SDn_PRESCALE bn 0 ~ 7 8 b b GPIOSD_SDn_IN [-128, 127] PDM 1b
161
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
· GPIOSD_SDn_IN = -128 0% · GPIOSD_SDn_IN = 0 50% · GPIOSD_SDn_IN = 127 100%b PDM
Duty_Cycle = GP IOSD_SDn_IN + 128 256
PDM c 256 b
5.3.4.2
SDM · SDM GPIO pad 5.3.2 b · GPIOSD_FUNCTION_CLK_EN SDM b · GPIOSD_SDn_PRESCALE b · GPIOSD_SDn_IN SDM b
5.4 GPIO
5.4.1
GPIO CPU GPIO IO MUX 8 235 ~ 242 235 ~ 242 b 5.4-1 GPIO b SYSTEM_CPU_PERI_CLK_EN_REG SYSTEM_CLK_EN_DEDICATED_GPIO GPIO SYSTEM_CPU_PERI_RST_EN_REG SYSTEM_RST_EN_DEDICATED_GPIO GPIO b 15 15.3-3 b
5.4.2
GPIO · 8 8 · CPU · ·
162
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
5.4-1. GPIO
5.4.3
GPIO CPU GPIOb 5.4-1 GPIO GPIOb DEDIC_GPIO_OUT_CPU_REG GPIO
· DEDIC_GPIO_OUT_CPU_SELn = 0 GPIO · DEDIC_GPIO_OUT_CPU_SELn = 1 CPU GPIO b GPIO GPIO · GPIO · CPU GPIO b
5.4.3.1 GPIO
GPIO · GPIO DEDIC_GPIO_OUT_DRT_REG · MASK GPIO DEDIC_GPIO_OUT_MSK_REG · BIT GPIO DEDIC_GPIO_OUT_IDV_REG b
DEDIC_GPIO_OUT_SCAN_REG GPIO 5.4-1 gpio_out_statusb DEDIC_GPIO_IN_SCAN_REG GPIO 5.4-1 gpio_in_statusb GPIO // DEDIC_GPIO_IN_DLY_REG b GPIO GPIO b DEDIC_GPIO_INTR_RCGN_REG
163
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
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· 0/1 · 2 · 3 · 4 · 5 · 6/7
5.4.3.2 CPU GPIO
CPU / GPIO
· SET_BIT_GPIO_OUT mask 1 GPIO_OUT mask 8b GPIO_OUT mask 1 bGPIO_OUT 5.4-1 gpio_outb
· CLR_BIT_GPIO_OUT mask 1 GPIO_OUT mask 8b GPIO_OUT mask 1 b
· MASK WR_MASK_GPIO_OUT value, mask mask GPIO_OUT valuebvalue 8mask 8 GPIO_OUTb mask 1 value b mask 0x03 (0000 0011), GPIO_OUT[0] GPIO_OUT[1] b
· art WUR.GPIO_OUT art art GPIO_OUTb art 32 8 b
· arr RUR.GPIO_OUT arr GPIO_OUT arrb arr 32 8 b
· I GET_GPIO_IN I GPIO_IN Ib I 32, 24 0 8 GPIO_IN b
164
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
5.5 IO MUX I/O
5.5.1
SPIaJTAG GPIO b IO MUX b GPIO GPIO pad IO MUX b
5.5.2
I/O GPIO 1. GPIO pad IO_MUX_MCU_SEL pad 5.11 pad b 2. GPIO_SIGn_IN_SEL b
I/O GPIO GPIO pad IO_MUX_MCU_SEL pad b
/ IO MUX / GPIO b
5.6 RTC IO MUX I/O
5.6.1
ESP32-S2 22 GPIO c RTC RTC b IO MUX GPIO RTC IO MUX I/O RTC b RTC GPIO Deep-sleep Deep-sleep b 5.12 RTC_MUX b
5.6.2
pad RTC RTCIO_TOUCH_PADn_REG RTCIO_TOUCH_PADn_MUX_SEL b 0 IO MUX b RTCIO_TOUCH_PADn_MUX_SEL RTC b RTCIO_TOUCH_PADn_REG I/Opad b 5.12 RTC b 5.12 GPIO pad RTC b RTCIO_TOUCH_PADn_REG RTC GPIO GPIO pad b
165
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
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5.7 Light-sleep
ESP32-S2 Light-sleep b GPIO pad IO_MUX_n_REG IO_MUX_SLP_SEL 1 Light-sleep padb
5.7-1. IO MUX Light-sleep
IO MUX
IO_MUX_SLP_SEL = 0 IO_MUX_FUN_DRV IO_MUX_FUN_WPU IO_MUX_FUN_WPD (From GPIO Matrix _OEN field)1
Light-sleep IO_MUX_SLP_SEL = 1 IO_MUX_FUN_DRV IO_MUX_MCU_WPU IO_MUX_MCU_WPD IO_MUX_MCU_OE
IO_MUX_SLP_SEL 0 Light-sleep b
IO_MUX_SLP_SEL = 0 5.3.2 b
5.8 Pad Hold
IO padc RTC pad hold RTC bpad hold pad hold IO MUX GPIO pad b Deep-sleep pad hold b
· pad pad RTC_CNTL_DG_PAD_FORCE_UNHOLD 0b RTC pad RTC_CNTL_PAD_HOLD_REG Hold Unhold pad b · Hold RTC_CNTL_DG_PAD_FORCE_UNHOLD 1b pad RTC_CNTL_PAD_HOLD_REG 1b
5.9 I/O Pad
IO pad uESP32-S2 vb
5.9.1
ESP32-S2 4 b · VDD3P3_RTC_IORTC CPU · VDD3P3_CPUCPU · VDD3P3_RTCRTC
166
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
· VDD_SPI
VDD_SPI LDO LDO 1.8 Vb LDOVDD_SPI VDD3P3_RTC_IO b
VDD_SPI GPIO45 Strapping eFuse VDD_SPI b uESP32-S2 v Strapping b
5.10
5.10-1 GPIO b 5.10-1. GPIO
0
SPIQ_in
1
SPID_in
2
SPIHD_in
3
SPIWP_in
4
-
5
-
6
-
7
SPID4_in
8
SPID5_in
9
SPID6_in
10
SPID7_in
11
SPIDQS_in
14
U0RXD_in
15
U0CTS_in
16
U0DSR_in
17
U1RXD_in
18
U1CTS_in
21
U1DSR_in
23
I2S0O_BCK_in
25
I2S0O_WS_in
27
I2S0I_BCK_in
28
I2S0I_WS_in
29
I2CEXT0_SCL_in
30
I2CEXT0_SDA_in
39
pcnt_sig_ch0_in0
40
pcnt_sig_ch1_in0
41
pcnt_ctrl_ch0_in0
42
pcnt_ctrl_ch1_in0
43
pcnt_sig_ch0_in1
44
pcnt_sig_ch1_in1
*
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
IO MUX
yes yes yes yes
yes yes yes yes yes yes yes no yes yes no no no no no no no no no no no no no
SPIQ_out SPID_out SPIHD_out SPIWP_out SPICLK_out_mux SPICS0_out SPICS1_out SPID4_out SPID5_out SPID6_out SPID7_out SPIDQS_out U0TXD_out U0RTS_out U0DTR_out U1TXD_out U1RTS_out U1DTR_out I2S0O_BCK_out I2S0O_WS_out I2S0I_BCK_out I2S0I_WS_out I2CEXT0_SCL_out I2CEXT0_SDA_out gpio_wlan_prio gpio_wlan_active -
SPIQ_oe SPID_oe SPIHD_oe SPIWP_oe SPICLK_oe SPICS0_oe SPICS1_oe SPID4_oe SPID5_oe SPID6_oe SPID7_oe SPIDQS_oe
1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 I2CEXT0_SCL_oe I2CEXT0_SDA_oe 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1
167
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
45 46 47 48 49 50 51 52 53 54 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 95 96 100 101 102
pcnt_ctrl_ch0_in1 pcnt_ctrl_ch1_in1 pcnt_sig_ch0_in2 pcnt_sig_ch1_in2 pcnt_ctrl_ch0_in2 pcnt_ctrl_ch1_in2 pcnt_sig_ch0_in3 pcnt_sig_ch1_in3 pcnt_ctrl_ch0_in3 pcnt_ctrl_ch1_in3 usb_otg_iddig_in usb_otg_avalid_in usb_srp_bvalid_in usb_otg_vbusvalid_in usb_srp_sessend_in SPI3_CLK_in SPI3_Q_in SPI3_D_in SPI3_HD_in SPI3_CS0_in rmt_sig_in0 rmt_sig_in1 rmt_sig_in2 rmt_sig_in3 I2CEXT1_SCL_in I2CEXT1_SDA_in -
*
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 -
IO MUX
no no no no no no no no no no no no no no no no no no no no no no no no no no -
usb_otg_idpullup usb_otg_dppulldown usb_otg_dmpulldown usb_otg_drvvbus usb_srp_chrgvbus usb_srp_dischrgvbus SPI3_CLK_out_mux SPI3_Q_out SPI3_D_out SPI3_HD_out SPI3_CS0_out SPI3_CS1_out SPI3_CS2_out ledc_ls_sig_out0 ledc_ls_sig_out1 ledc_ls_sig_out2 ledc_ls_sig_out3 ledc_ls_sig_out4 ledc_ls_sig_out5 ledc_ls_sig_out6 ledc_ls_sig_out7 rmt_sig_out0 rmt_sig_out1 rmt_sig_out2 rmt_sig_out3 I2CEXT1_SCL_out I2CEXT1_SDA_out gpio_sd0_out gpio_sd1_out gpio_sd2_out
1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 SPI3_CLK_oe SPI3_Q_oe SPI3_D_oe SPI3_HD_oe SPI3_CS0_oe SPI3_CS1_oe SPI3_CS2_oe 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 I2CEXT1_SCL_oe I2CEXT1_SDA_oe 1'd1 1'd1 1'd1
168
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
103 -
104 -
105 -
106 -
107 -
108 FSPICLK_in
109 FSPIQ_in
110
FSPID_in
111
FSPIHD_in
112
FSPIWP_in
113
FSPIIO4_in
114
FSPIIO5_in
115
FSPIIO6_in
116
FSPIIO7_in
117
FSPICS0_in
118
-
119
-
120 -
121
-
122 -
123 twai_rx
124
-
125 -
126 -
127 SUBSPIQ_in
128 SUBSPID_in
129 SUBSPIHD_in
130 SUBSPIWP_in
131
-
132 -
133 -
134 -
135 -
136 -
137 -
139 -
140 -
143 I2S0I_DATA_in0
144 I2S0I_DATA_in1
145 I2S0I_DATA_in2
146 I2S0I_DATA_in3
147 I2S0I_DATA_in4
*
0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
IO MUX
yes yes yes yes yes yes yes yes yes yes no yes yes yes yes no no no no no
gpio_sd3_out gpio_sd4_out gpio_sd5_out gpio_sd6_out gpio_sd7_out FSPICLK_out_mux FSPIQ_out FSPID_out FSPIHD_out FSPIWP_out FSPIIO4_out FSPIIO5_out FSPIIO6_out FSPIIO7_out FSPICS0_out FSPICS1_out FSPICS2_out FSPICS3_out FSPICS4_out FSPICS5_out twai_tx twai_bus_off_on twai_clkout SUBSPICLK_out_mux SUBSPIQ_out SUBSPID_out SUBSPIHD_out SUBSPIWP_out SUBSPICS0_out SUBSPICS1_out FSPIDQS_out FSPI_HSYNC_out FSPI_VSYNC_out FSPI_DE_out FSPICD_out SPI3_CD_out SPI3_DQS_out I2S0O_DATA_out0 I2S0O_DATA_out1 I2S0O_DATA_out2 I2S0O_DATA_out3 I2S0O_DATA_out4
1'd1 1'd1 1'd1 1'd1 1'd1 FSPICLK_oe FSPIQ_oe FSPID_oe FSPIHD_oe FSPIWP_oe FSPIIO4_oe FSPIIO5_oe FSPIIO6_oe FSPIIO7_oe FSPICS0_oe FSPICS1_oe FSPICS2_oe FSPICS3_oe FSPICS4_oe FSPICS5_oe 1'd1 1'd1 1'd1 SUBSPICLK_oe SUBSPIQ_oe SUBSPID_oe SUBSPIHD_oe SUBSPIWP_oe SUBSPICS0_oe SUBSPICS1_oe FSPIDQS_oe FSPI_HSYNC_oe FSPI_VSYNC_oe FSPI_DE_oe FSPICD_oe SPI3_CD_oe SPI3_DQS_oe 1'd1 1'd1 1'd1 1'd1 1'd1
169
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
148 I2S0I_DATA_in5
149 I2S0I_DATA_in6
150 I2S0I_DATA_in7
151
I2S0I_DATA_in8
152 I2S0I_DATA_in9
153 I2S0I_DATA_in10
154 I2S0I_DATA_in11
155 I2S0I_DATA_in12
156 I2S0I_DATA_in13
157 I2S0I_DATA_in14
158 I2S0I_DATA_in15
159 -
160 -
161
-
162 -
163 -
164 -
165 -
166 -
167 SUBSPID4_in
168 SUBSPID5_in
169 SUBSPID6_in
170 SUBSPID7_in
171
SUBSPIDQS_in
193 I2S0I_H_SYNC
194 I2S0I_V_SYNC
195 I2S0I_H_ENABLE
215 -
216 -
217 -
218 -
219 -
220 -
221 -
222 -
223 sig_in_func_223
224 sig_in_func_224
225 sig_in_func_225
226 sig_in_func_226
227 sig_in_func_227
235 pro_alonegpio_in0
236 pro_alonegpio_in1
*
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IO MUX
no no no no no no no no no no no yes yes yes yes yes no no no no no no no no no no
I2S0O_DATA_out5 I2S0O_DATA_out6 I2S0O_DATA_out7 I2S0O_DATA_out8 I2S0O_DATA_out9 I2S0O_DATA_out10 I2S0O_DATA_out11 I2S0O_DATA_out12 I2S0O_DATA_out13 I2S0O_DATA_out14 I2S0O_DATA_out15 I2S0O_DATA_out16 I2S0O_DATA_out17 I2S0O_DATA_out18 I2S0O_DATA_out19 I2S0O_DATA_out20 I2S0O_DATA_out21 I2S0O_DATA_out22 I2S0O_DATA_out23 SUBSPID4_out SUBSPID5_out SUBSPID6_out SUBSPID7_out SUBSPIDQS_out ant_sel0 ant_sel1 ant_sel2 ant_sel3 ant_sel4 ant_sel5 ant_sel6 ant_sel7 sig_in_func223 sig_in_func224 sig_in_func225 sig_in_func226 sig_in_func227 pro_alonegpio_out0 pro_alonegpio_out1
1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 SUBSPID4_oe SUBSPID5_oe SUBSPID6_oe SUBSPID7_oe SUBSPIDQS_oe 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1
170
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
237 pro_alonegpio_in2 238 pro_alonegpio_in3 239 pro_alonegpio_in4 240 pro_alonegpio_in5 241 pro_alonegpio_in6 242 pro_alonegpio_in7 251 -
*
0 0 0 0 0 0 -
IO MUX
no no no no no no -
pro_alonegpio_out2 pro_alonegpio_out3 pro_alonegpio_out4 pro_alonegpio_out5 pro_alonegpio_out6 pro_alonegpio_out7 clk_i2s_mux
GoBack
1'd1 1'd1 1'd1 1'd1 1'd1 1'd1 1'd1
5.11 IO MUX Pad
5.11-1 I/O pad IO MUX b 5.11-1. IO MUX Pad
GPIO Pad Name Function 0 Function 1
0
GPIO0
GPIO0
GPIO0
1
GPIO1
GPIO1
GPIO1
2
GPIO2
GPIO2
GPIO2
3
GPIO3
GPIO3
GPIO3
4
GPIO4
GPIO4
GPIO4
5
GPIO5
GPIO5
GPIO5
6
GPIO6
GPIO6
GPIO6
7
GPIO7
GPIO7
GPIO7
8
GPIO8
GPIO8
GPIO8
9
GPIO9
GPIO9
GPIO9
10 GPIO10
GPIO10
GPIO10
11 GPIO11
GPIO11
GPIO11
12 GPIO12
GPIO12
GPIO12
13 GPIO13
GPIO13
GPIO13
14 GPIO14
GPIO14
GPIO14
15 XTAL_32K_P XTAL_32K_P GPIO15
16 XTAL_32K_N XTAL_32K_N GPIO16
17 DAC_1
DAC_1
GPIO17
18 DAC_2
DAC_2
GPIO18
19 GPIO19
GPIO19
GPIO19
20 GPIO20
GPIO20
GPIO20
21 GPIO21
GPIO21
GPIO21
26 SPICS1
SPICS1
GPIO26
27 SPIHD
SPIHD
GPIO27
28 SPIWP
SPIWP
GPIO28
29 SPICS0
SPICS0
GPIO29
Function 2 FSPIIO4 FSPIIO5 FSPIIO6 FSPIIO7 FSPIDQS U0RTS U0CTS U1TXD U1RXD U1RTS U1CTS -
Function 3
SUBSPICS1 SUBSPIHD SUBSPICS0 SUBSPID SUBSPICLK SUBSPIQ SUBSPIWP CLK_OUT3 CLK_OUT2 CLK_OUT1 -
Function 4 FSPIHD FSPICS0 FSPID FSPICLK FSPIQ FSPIWP -
Reset Notes
3
R
1
R
1
R
0
R
0
R
0
R
0
R
0
R
0
R
1
R
1
R
1
R
1
R
1
R
1
R
0
R
0
R
1
R
3
R
0
R
0
R
0
R
3
-
3
-
3
-
3
-
171
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
GPIO Pad Name
30 SPICLK 31 SPIQ 32 SPID 33 GPIO33 34 GPIO34 35 GPIO35 36 GPIO36 37 GPIO37 38 GPIO38 39 MTCK 40 MTDO 41 MTDI 42 MTMS 43 U0TXD 44 U0RXD 45 GPIO45 46 GPIO46
Function 0
SPICLK SPIQ SPID GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 MTCK MTDO MTDI MTMS U0TXD U0RXD GPIO45 GPIO46
Function 1
GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 GPIO39 GPIO40 GPIO41 GPIO42 GPIO43 GPIO44 GPIO45 GPIO46
Function Function 3
2
-
-
-
-
-
FSPIHD SUBSPIHD
FSPICS0 SUBSPICS0
FSPID
SUBSPID
FSPICLK SUBSPICLK
FSPIQ
SUBSPIQ
FSPIWP SUBSPIWP
CLK_OUT3 SUBSPICS1
CLK_OUT2 -
CLK_OUT1 -
-
-
CLK_OUT1 -
CLK_OUT2 -
-
-
-
-
Function 4 SPIIO4 SPIIO5 SPIIO6 SPIIO7 SPIDQS -
Reset Notes
3
-
3
-
3
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
3
-
3
-
2
-
2
I
oResetp pad b
· 0 - IE=0c · 1 - IE=1c · 2 - IE=1, WPD=1c · 3 - IE=1, WPU=1c · R - Pad RTC IO MUX RTC/b · I - Pad GPIOb uESP32-S2 vb
5.12 RTC IO MUX
5.12-1 RTC GPIO padb 5.12-1. RTC IO MUX
RTC GPIO Num GPIO Num Pad Name
0
1
0
0
TOUCH_PAD0 1 RTC_GPIO0 -
1
1
TOUCH_PAD1 RTC_GPIO1
-
Analog Function 2 -
3 sar_i2c_scl_02 sar_i2c_sda_02
172
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
RTC GPIO Num GPIO Num Pad Name
0
1
2
2
TOUCH_PAD2 RTC_GPIO2 -
3
3
TOUCH_PAD3 RTC_GPIO3 -
4
4
TOUCH_PAD4 RTC_GPIO4 -
5
5
TOUCH_PAD5 RTC_GPIO5 -
6
6
TOUCH_PAD6 RTC_GPIO6 -
7
7
TOUCH_PAD7 RTC_GPIO7 -
8
8
TOUCH_PAD8 RTC_GPIO8 -
9
9
TOUCH_PAD9 RTC_GPIO9 -
10
10
TOUCH_PAD10 RTC_GPIO10 -
11
11
TOUCH_PAD11 RTC_GPIO11 -
12
12
TOUCH_PAD12 RTC_GPIO12 -
13
13
TOUCH_PAD13 RTC_GPIO13 -
14
14
TOUCH_PAD14 RTC_GPIO14 -
15
15
X32P
RTC_GPIO15 -
16
16
X32N
RTC_GPIO16 -
17
17
PDAC1
RTC_GPIO17 -
18
18
PDAC2
RTC_GPIO18 -
19
19
RTC_PAD19
RTC_GPIO19 -
20
20
RTC_PAD20
RTC_GPIO20 -
21
21
RTC_PAD21
RTC_GPIO21 -
Analog Function 2 -
GoBack
3 sar_i2c_scl_12 sar_i2c_sda_12 -
1. TOUCH_PAD0 b 2. sar_i2c_xx 1 (ULP)RTC I2C b
5.13
5.13-1 b 3 b 5.13-1.
GPIO
IO MUX GPIOSD GPIO RTCIO
PeriBUS1 PeriBUS2 PeriBUS1 PeriBUS2 PeriBUS2 PeriBUS1 PeriBUS1 PeriBUS2
0x3F404000 0x60004000 0x3F409000 0x60009000 0x60004F00 0x3F4CF000 0x3F408400 0x60008400
173
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
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5.14
5.14.1 GPIO
GPIO c 5.13 GPIO b
GPIO GPIO_BT_SELECT_REG GPIO_OUT_REG GPIO_OUT_W1TS_REG GPIO_OUT_W1TC_REG GPIO_OUT1_REG GPIO_OUT1_W1TS_REG GPIO_OUT1_W1TC_REG GPIO_SDIO_SELECT_REG GPIO_ENABLE_REG GPIO_ENABLE_W1TS_REG GPIO_ENABLE_W1TC_REG GPIO_ENABLE1_REG GPIO_ENABLE1_W1TS_REG GPIO_ENABLE1_W1TC_REG GPIO_STRAP_REG GPIO_IN_REG GPIO_IN1_REG GPIO_PIN0_REG GPIO_PIN1_REG GPIO_PIN2_REG ... GPIO_PIN44_REG GPIO_PIN45_REG GPIO_PIN46_REG GPIO_FUNC0_IN_SEL_CFG_REG GPIO_FUNC1_IN_SEL_CFG_REG GPIO_FUNC2_IN_SEL_CFG_REG ... GPIO_FUNC253_IN_SEL_CFG_REG GPIO_FUNC254_IN_SEL_CFG_REG GPIO_FUNC255_IN_SEL_CFG_REG GPIO_FUNC0_OUT_SEL_CFG_REG GPIO_FUNC1_OUT_SEL_CFG_REG GPIO_FUNC2_OUT_SEL_CFG_REG .. GPIO_FUNC43_OUT_SEL_CFG_REG
GPIO GPIO0 ~ 31 GPIO0 ~ 31 GPIO0 ~ 31 GPIO32 ~ 45 GPIO32 ~ 45 GPIO32 ~ 45 GPIO SDIO GPIO0 ~ 31 GPIO0 ~ 31 GPIO0 ~ 31 GPIO32 ~ 45 GPIO32 ~ 45 GPIO32 ~ 45 Bootstrap GPIO0 ~ 31 GPIO32 ~ 53 GPIO pin 0 GPIO pin 1 GPIO pin 2 ... GPIO pin 44 GPIO pin 45 GPIO pin 46 function 0 function 1 function 2 ... function 253 function 254 function 255 GPIO0 GPIO1 GPIO2 ... GPIO43
0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0074 0x0078 0x007C ... 0x0124 0x0128 0x012C 0x0154 0x0158 0x015C ... 0x0548 0x054C 0x0550 0x0554 0x0558 0x055C ... 0x0600
/ / / / / / / / / ... / / / / / / ... / / / / / / ... /
174
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
GPIO_FUNC44_OUT_SEL_CFG_REG GPIO_FUNC45_OUT_SEL_CFG_REG GPIO_CLOCK_GATE_REG GPIO_STATUS_W1TS_REG GPIO_STATUS_W1TC_REG GPIO_STATUS1_W1TS_REG GPIO_STATUS1_W1TC_REG GPIO GPIO_STATUS_NEXT_REG GPIO_STATUS_NEXT1_REG GPIO_STATUS_REG GPIO_STATUS1_REG GPIO_PCPU_INT_REG GPIO_PCPU_NMI_INT_REG GPIO_PCPU_INT1_REG GPIO_PCPU_NMI_INT1_REG
GPIO44 GPIO45 GPIO
0x0604 0x0608 0x062C
/ / /
GPIO0 ~ 31 GPIO0 ~ 31 GPIO32 ~ 46 GPIO32 ~ 46
0x0048 0x004C 0x0054 0x0058
GPIO0 ~ 31 GPIO32 ~ 46
0x014C 0x0150
GPIO0 ~ 31 GPIO32 ~ 46 GPIO0 ~ 31 PRO_CPU GPIO0 ~ 31 PRO_CPU GPIO32 ~ 46 PRO_CPU GPIO 32 ~ 46 PRO_CPU
0x0044 0x0050 0x005C 0x0060 0x0068 0x006C
/ /
5.14.2 IO MUX
IO MUX c 5.13 IO MUX b
IO_MUX_PIN_CTRL_REG IO_MUX_GPIO0_REG IO_MUX_GPIO1_REG IO_MUX_GPIO2_REG IO_MUX_GPIO3_REG IO_MUX_GPIO4_REG IO_MUX_GPIO5_REG IO_MUX_GPIO6_REG IO_MUX_GPIO7_REG IO_MUX_GPIO8_REG IO_MUX_GPIO9_REG IO_MUX_GPIO10_REG IO_MUX_GPIO11_REG IO_MUX_GPIO12_REG IO_MUX_GPIO13_REG IO_MUX_GPIO14_REG IO_MUX_XTAL_GPIO15_REG
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 XTAL_32K_P
0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040
/ / / / / / / / / / / / / / / / /
175
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
IO_MUX_XTAL_GPIO16_REG IO_MUX_GPIO17_REG IO_MUX_GPIO18_REG IO_MUX_GPIO19_REG IO_MUX_GPIO20_REG IO_MUX_GPIO21_REG IO_MUX_GPIO26_REG IO_MUX_GPIO27_REG IO_MUX_GPIO28_REG IO_MUX_GPIO29_REG IO_MUX_GPIO30_REG IO_MUX_GPIO31_REG IO_MUX_GPIO32_REG IO_MUX_GPIO33_REG IO_MUX_GPIO34_REG IO_MUX_GPIO35_REG IO_MUX_GPIO36_REG IO_MUX_GPIO37_REG IO_MUX_GPIO38_REG IO_MUX_GPIO39_REG IO_MUX_GPIO40_REG IO_MUX_GPIO41_REG IO_MUX_GPIO42_REG IO_MUX_GPIO43_REG IO_MUX_GPIO44_REG IO_MUX_GPIO45_REG IO_MUX_GPIO46_REG
XTAL_32K_N DAC_1 DAC_2 GPIO19 GPIO20 GPIO21 SPICS1 SPIHD SPIWP SPICS0 SPICLK SPIQ SPID GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38 MTCK MTDO MTDI MTMS U0TXD U0RXD GPIO45 GPIO46
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0x0044 0x0048 0x004C 0x0050 0x0054 0x0058 0x006C 0x0070 0x0074 0x0078 0x007C 0x0080 0x0084 0x0088 0x008C 0x0090 0x0094 0x0098 0x009C 0x00A0 0x00A4 0x00A8 0x00AC 0x00B0 0x00B4 0x00B8 0x00BC
/ / / / / / / / / / / / / / / / / / / / / / / / / / /
5.14.3 SDM
GPIOSD c 5.13 GPIOSD b
GPIOSD_SIGMADELTA0_REG GPIOSD_SIGMADELTA1_REG GPIOSD_SIGMADELTA2_REG GPIOSD_SIGMADELTA3_REG GPIOSD_SIGMADELTA4_REG GPIOSD_SIGMADELTA5_REG GPIOSD_SIGMADELTA6_REG GPIOSD_SIGMADELTA7_REG
SDM0 SDM1 SDM2 SDM3 SDM4 SDM5 SDM6 SDM7
0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C
/ / / / / / / /
176
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GPIOSD_SIGMADELTA_CG_REG GPIOSD_SIGMADELTA_MISC_REG GPIOSD_SIGMADELTA_VERSION_REG
MISC
GoBack
0x0020 0x0024 0x0028
/ / /
5.14.4 GPIO
GPIO c 5.13 GPIO b
DEDIC_GPIO_OUT_DRT_REG DEDIC_GPIO_OUT_MSK_REG DEDIC_GPIO_OUT_IDV_REG DEDIC_GPIO_OUT_CPU_REG DEDIC_GPIO_IN_DLY_REG DEDIC_GPIO_INTR_RCGN_REG DEDIC_GPIO_OUT_SCAN_REG DEDIC_GPIO_IN_SCAN_REG DEDIC_GPIO_INTR_RAW_REG DEDIC_GPIO_INTR_RLS_REG DEDIC_GPIO_INTR_ST_REG DEDIC_GPIO_INTR_CLR_REG
GPIO GPIO GPIO GPIO GPIO GPIO
GPIO GPIO
0x0000 WO 0x0004 WO 0x0008 WO 0x0010 R/W 0x0014 R/W 0x001C R/W
0x000C RO 0x0018 RO
0x0020 RO 0x0024 R/W 0x0028 RO 0x002C WO
5.14.5 RTC IO MUX
RTCIO c 5.13 RTCIO b
GPIO / RTCIO_RTC_GPIO_OUT_REG RTCIO_RTC_GPIO_OUT_W1TS_REG RTCIO_RTC_GPIO_OUT_W1TC_REG RTCIO_RTC_GPIO_ENABLE_REG RTCIO_RTC_GPIO_ENABLE_W1TS_REG RTCIO_RTC_GPIO_ENABLE_W1TC_REG RTCIO_RTC_GPIO_STATUS_REG RTCIO_RTC_GPIO_STATUS_W1TS_REG RTCIO_RTC_GPIO_STATUS_W1TC_REG RTCIO_RTC_GPIO_IN_REG RTCIO_RTC_GPIO_PIN0_REG
RTC GPIO RTC GPIO RTC GPIO RTC GPIO RTC GPIO RTC GPIO RTC GPIO RTC GPIO RTC GPIO RTC GPIO Pin0 RTC
0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028
/ / / /
177
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
RTCIO_RTC_GPIO_PIN1_REG RTCIO_RTC_GPIO_PIN2_REG RTCIO_RTC_GPIO_PIN3_REG ... RTCIO_RTC_GPIO_PIN19_REG RTCIO_RTC_GPIO_PIN20_REG RTCIO_RTC_GPIO_PIN21_REG RTC GPIO RTCIO_TOUCH_PAD0_REG RTCIO_TOUCH_PAD1_REG RTCIO_TOUCH_PAD2_REG ... RTCIO_TOUCH_PAD13_REG RTCIO_TOUCH_PAD14_REG RTCIO_XTAL_32P_PAD_REG RTCIO_XTAL_32N_PAD_REG RTCIO_PAD_DAC1_REG RTCIO_PAD_DAC2_REG RTCIO_RTC_PAD19_REG RTCIO_RTC_PAD20_REG RTCIO_RTC_PAD21_REG RTCIO_XTL_EXT_CTR_REG RTCIO_SAR_I2C_IO_REG
Pin1 RTC Pin2 RTC Pin3 RTC ... Pin19 RTC Pin20 RTC Pin21 RTC
Touch pad 0 Touch pad 1 Touch pad 2 ... Touch pad 13 Touch pad 14 32KHz crystal P-pad 32KHz crystal N-pad DAC1 DAC2 Touch pad 19 Touch pad 20 Touch pad 21 GPIO RTC I2C pad
5.15
5.15.1 GPIO
Register 5.1. GPIO_BT_SELECT_REG (0x0000)
GPIO_BT_SEL
31
0x000000
GPIO_BT_SEL c/
GoBack
0x002C 0x0030 0x0034 ... 0x0074 0x0078 0x007C
/ / / ... / / /
0x0084 0x0088 0x008C ... 0x00B8 0x00BC 0x00C0 0x00C4 0x00C8 0x00CC 0x00D0 0x00D4 0x00D8 0x00E0 0x00E4
/ / / ... / / / / / / / / / / /
0
Reset
178
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
Register 5.2. GPIO_OUT_REG (0x0004)
GPIO_OUT_DATA_ORIG
31
0
0x000000
Reset
GPIO_OUT_DATA_ORIG GPIO GPIO0 ~ GPIO31 bbit0 ~ bit31 GPIO0 ~ 31 bit22 ~ bit25 bc/
Register 5.3. GPIO_OUT_W1TS_REG (0x0008)
GPIO_OUT_W1TS
31
0
0x000000
Reset
GPIO_OUT_W1TS GPIO0 ~ 31 b 1GPIO_OUT_REG 1b GPIO_OUT_REGbc
Register 5.4. GPIO_OUT_W1TC_REG (0x000C)
GPIO_OUT_W1TC
31
0
0x000000
Reset
GPIO_OUT_W1TC GPIO0 ~ 31 b 1 GPIO_OUT_REG b GPIO_OUT_REGbc
179
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
Register 5.5. GPIO_OUT1_REG (0x0010)
(reserved)
31
22 21
0000000000
GPIO_OUT1_DATA_ORIG 0x0000
0
Reset
GPIO_OUT1_DATA_ORIG GPIO GPIO32 ~ 45 bbit0 ~ bit13 GPIO32 ~ GPIO45 bit14 ~ bit21 bc/
Register 5.6. GPIO_OUT1_W1TS_REG (0x0014)
(reserved)
31
22 21
0000000000
GPIO_OUT1_W1TS 0x0000
0
Reset
GPIO_OUT1_W1TS GPIO32 ~ 45 b 1 GPIO_OUT1_REG 1b GPIO_OUT1_REGbc
Register 5.7. GPIO_OUT1_W1TC_REG (0x0018)
(reserved)
31
22 21
0000000000
GPIO_OUT1_W1TC 0x0000
0
Reset
GPIO_OUT1_W1TC GPIO32 ~ 45 b 1 GPIO_OUT1_REG b GPIO_OUT1_REGbc
Register 5.8. GPIO_SDIO_SELECT_REG (0x001C)
(reserved)
31
87
000000000000000000000000
GPIO_SDIO_SEL c/
GPIO_SDIO_SEL
0
0x0
Reset
180
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
Register 5.9. GPIO_ENABLE_REG (0x0020)
GPIO_ENABLE_DATA
31
0x000000
GPIO_ENABLE_DATA GPIO0 ~ 31 bc/
GoBack
0
Reset
Register 5.10. GPIO_ENABLE_W1TS_REG (0x0024)
GPIO_ENABLE_W1TS
31
0
0x000000
Reset
GPIO_ENABLE_W1TS GPIO0 ~ 31 b 1 GPIO_ENABLE_REG 1b GPIO_ENABLE_REGbc
Register 5.11. GPIO_ENABLE_W1TC_REG (0x0028)
GPIO_ENABLE_W1TC
31
0
0x000000
Reset
GPIO_ENABLE_W1TC GPIO0 ~ 31 b 1 GPIO_ENABLE_REG b GPIO_ENABLE_REGbc
181
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
Register 5.12. GPIO_ENABLE1_REG (0x002C)
(reserved)
31
22 21
0000000000
GPIO_ENABLE1_DATA 0x0000
GPIO_ENABLE1_DATA GPIO32 ~ 45 bc/
GoBack
0
Reset
Register 5.13. GPIO_ENABLE1_W1TS_REG (0x0030)
(reserved)
31
22 21
0000000000
GPIO_ENABLE1_W1TS 0x0000
0
Reset
GPIO_ENABLE1_W1TS GPIO32 ~ 45 b 1 GPIO_ENABLE1_REG 1b GPIO_ENABLE1_REGbc
Register 5.14. GPIO_ENABLE1_W1TC_REG (0x0034)
(reserved)
31
22 21
0000000000
GPIO_ENABLE1_W1TC 0x0000
0
Reset
GPIO_ENABLE1_W1TC GPIO32 ~ 45 b 1 GPIO_ENABLE1_REG b GPIO_ENABLE1_REGbc
182
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
Register 5.15. GPIO_STRAP_REG (0x0038)
(reserved)
31
16 15
0000000000000000
GPIO_STRAPPING 0
0
Reset
GPIO_STRAPPING GPIO Strapping bit4 ~ bit2 GPIO45aGPIO0 GPIO46bc
Register 5.16. GPIO_IN_REG (0x003C)
GPIO_IN_DATA_NEXT
31
0
0
Reset
GPIO_IN_DATA_NEXT GPIO0 ~ 31 b bit pad bit 1 bit 0bc
Register 5.17. GPIO_IN1_REG (0x0040)
(reserved)
31
22 21
0000000000
GPIO_IN_DATA1_NEXT 0
GPIO_IN_DATA1_NEXT GPIO32 ~ 46 b bit pad bc
0
Reset
183
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
Register 5.18. GPIO_PINn_REG (n:0-46) (0x0074+4*n)
(reserved)
31
18 17
00000000000000
GPIO_PINn_INT_ENGAPIO_PIGNPn_IOC_OPNINFnIGG_WPIAOK_EPUINPn__EINN(ATreB_sLTeEYrPveEd) GPIO_PIGNPn_IOS_YPNICGN1Pn__IOBPY_APPDAI_NSDnS_RSIVYENRC2_BYPASS
13 12 11 10 9
76
54
321
0
0x0
0x0 0
0x0 0 0 0x0 0 0x0 Reset
GPIO_PINn_SYNC2_BYPASS GPIO b01 2 3bc/
GPIO_PINn_PAD_DRIVER pad b01bc/
GPIO_PINn_SYNC1_BYPASS GPIO b01 2 3bc/
GPIO_PINn_INT_TYPE bc/
0 GPIO 1 2 3 4 5 GPIO_PINn_WAKEUP_ENABLE GPIO CPU Light-sleep bc/
GPIO_PINn_CONFIG bc/
GPIO_PINn_INT_ENA bbit13 CPU bit14 CPU bc/
184
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
Register 5.19. GPIO_FUNCn_IN_SEL_CFG_REG (n:0-255) (0x0154+4*n)
(reserved)
GPIO_GSPIGIOn__FINU_NSCEnL_IN_INGVP_IOS_ELFUNCn_IN_SEL
31
87 65
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0
0x0
Reset
GPIO_FUNCn_IN_SEL m b 1 GPIO 0x38 0x3C bc/
GPIO_FUNCn_IN_INV_SEL b10bc/
GPIO_SIGn_IN_SEL GPIO b1 GPIO 0 IO MUX bc/
Register 5.20. GPIO_FUNCn_OUT_SEL_CFG_REG (n:0-45) (0x0554+4*n)
(reserved)
GPIO_GFPUION_CGFnPU_IONO_CEFNnU__NOINCEVNn___SOSEEULLT_INV_SEGLPIO_FUNCn_OUT_SEL
31
12 11 10 9 8
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0
0x100
Reset
GPIO_FUNCn_OUT_SEL GPIO n b s (0<=s<256) s GPIO nb 256 GPIO_OUT_REG/GPIO_OUT1_REG GPIO_ENABLE_REG/GPIO_ENABLE1_REG bit n bc/
GPIO_FUNCn_OUT_INV_SEL 01bc/
GPIO_FUNCn_OEN_SEL 01 GPIO_ENABLE_REG bit n bc/
GPIO_FUNCn_OEN_INV_SEL 01bc/
185
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
Register 5.21. GPIO_CLOCK_GATE_REG (0x062C)
(reserved)
GPIO_CLK_EN
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset
GPIO_CLK_EN b 1bc/
Register 5.22. GPIO_STATUS_W1TS_REG (0x0048)
GPIO_STATUS_W1TS
31
0
0x000000
Reset
GPIO_STATUS_W1TS GPIO0 ~ 31 b 1 GPIO_STATUS_INTERRUPT 1b GPIO_STATUS_INTERRUPTbc
Register 5.23. GPIO_STATUS_W1TC_REG (0x004C)
GPIO_STATUS_W1TC
31
0
0x000000
Reset
GPIO_STATUS_W1TC GPIO0 ~ 31 b 1 GPIO_STATUS_INTERRUPT b GPIO_STATUS_INTERRUPTbc
Register 5.24. GPIO_STATUS1_W1TS_REG (0x0054)
(reserved)
31
22 21
0000000000
GPIO_STATUS1_W1TS 0x0000
0
Reset
GPIO_STATUS1_W1TS GPIO32 ~ 46 b 1GPIO_STATUS_INTERRUPT1 1b GPIO_STATUS_INTERRUPT1bc
186
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
Register 5.25. GPIO_STATUS1_W1TC_REG (0x0058)
(reserved)
31
22 21
0000000000
GPIO_STATUS1_W1TC 0x0000
0
Reset
GPIO_STATUS1_W1TC GPIO32 ~ 46 b 1 GPIO_STATUS_INTERRUPT1 b GPIO_STATUS_INTERRUPT1bc
Register 5.26. GPIO_STATUS_NEXT_REG (0x014C)
GPIO_STATUS_INTERRUPT_NEXT
31
0
0x000000
Reset
GPIO_STATUS_INTERRUPT_NEXT GPIO0 ~ 31 aa bc
Register 5.27. GPIO_STATUS_NEXT1_REG (0x0150)
(reserved)
31
22 21
0000000000
GPIO_STATUS1_INTERRUPT_NEXT 0x0000
GPIO_STATUS1_INTERRUPT_NEXT GPIO32 ~ 46 bc
0
Reset
187
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
Register 5.28. GPIO_STATUS_REG (0x0044)
GPIO_STATUS_INTERRUPT
31
0x000000
GPIO_STATUS_INTERRUPT GPIO0 ~ 31 bc/
GoBack
0
Reset
Register 5.29. GPIO_STATUS1_REG (0x0050)
(reserved)
31
22 21
0000000000
GPIO_STATUS1_INTERRUPT 0x0000
GPIO_STATUS1_INTERRUPT GPIO32 ~ 46 bc/
0
Reset
Register 5.30. GPIO_PCPU_INT_REG (0x005C)
GPIO_PROCPU_INT
31
0
0x000000
Reset
GPIO_PROCPU_INT GPIO0 ~ 31 PRO_CPU b GPIO_PINn_REG bit13 CPU GPIO_STATUS_REG bit bc
188
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
Register 5.31. GPIO_PCPU_NMI_INT_REG (0x0060)
GPIO_PROCPU_NMI_INT
31
0
0x000000
Reset
GPIO_PROCPU_NMI_INT GPIO0 ~ 31 PRO_CPU b GPIO_PINn_REG bit14 CPU GPIO_STATUS_REG bit bc
Register 5.32. GPIO_PCPU_INT1_REG (0x0068)
(reserved)
31
22 21
0000000000
GPIO_PROCPU1_INT 0x0000
0
Reset
GPIO_PROCPU1_INT GPIO32 ~ 46 PRO_CPU b GPIO_PINn_REG bit13 CPU GPIO_STATUS1_REG bit bc
Register 5.33. GPIO_PCPU_NMI_INT1_REG (0x006C)
(reserved)
31
22 21
0000000000
GPIO_PROCPU_NMI1_INT 0x0000
0
Reset
GPIO_PROCPU_NMI1_INT GPIO32 ~ 46 PRO_CPU b GPIO_PINn_REG bit14 CPU GPIO_STATUS1_REG bit bc
189
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
5.15.2 IO MUX
Register 5.34. IO_MUX_PIN_CTRL_REG (0x0000)
(reserved)
IO_MUX_PAIOD__MPOUWX_ESRW_CITTCRHL_PIOR_TM_NUUXM_PIN_CTRL_CILOK_3MUX_PIN_CTRL_CILOK_2MUX_PIN_CTRL_CLK1
31
16 15 14
12 11
87
43
0
0x0
0x0 0x2
0x0
0x0
0x0
Reset
IO_MUX_PIN_CTRL_CLK1 I2S0 b IO_MUX_PIN_CTRL1 0 I2S0 CLK_OUT1 IO_MUX_PIN_CTRL1 15 b(R/W)
IO_MUX_PIN_CTRL_CLK2 I2S0 b IO_MUX_PIN_CTRL2 0 I2S0 CLK_OUT2 IO_MUX_PIN_CTRL2 15 b(R/W)
IO_MUX_PIN_CTRL_CLK3 I2S0 b IO_MUX_PIN_CTRL3 0 I2S0 CLK_OUT3 IO_MUX_PIN_CTRL3 15 b(R/W)
bCLK_OUT1 ~ 3 IO_MUX Pad b
IO_MUX_SWITCH_PRT_NUM IO Pad APB b(R/W)
IO_MUX_PAD_POWER_CTRL GPIO33 ~ 37 b1 VDD_SPI 1.8 V 0 VDD3P3_CPU 3.3 V b(R/W)
190
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
Register 5.35. IO_MUX_n_REG (n: GPIO0-GPIO21, GPIO26-GPIO46) (0x0004+4*n)
(reserved)
IO_MUX_FIILOT_EMR_UEXN_MCUIO_S_EMLUX_IOF_UMNU_IODX__RMFVUUIONX___MFIEUUNX__(rWFeUsPeNUr_vWedIPO)D_MUIOX__MMUICOXU___MMIEUICOXU___MMWUICOPXU_U__MSWLUPPXD__SMECLU_OE
31
16 15 14
12 11 10 9 8 7 6
54 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0x0
0x2 0 0 0 00 0 0 0 0 0 Reset
IO_MUX_MCU_OE pad b10bc/ IO_MUX_SLP_SEL Pad b 1 bc/ IO_MUX_MCU_WPD pad b10bc/ IO_MUX_MCU_WPU pad b10bc/ IO_MUX_MCU_IE pad b10bc/ IO_MUX_FUN_WPD Pad b10bc/ IO_MUX_FUN_WPU Pad b10bc/ IO_MUX_FUN_IE Pad b10bc/ IO_MUX_FUN_DRV Pad b0~5 mA1~10 mA2~20 mA3~40 mAbc/ IO_MUX_MCU_SEL IO MUX b0 Function 01 Function 1
bc/ IO_MUX_FILTER_EN Pad b10bc/
5.15.3 SDM
Register 5.36. GPIOSD_SIGMADELTAn_REG (n: 0-7) (0x0000+4*n)
(reserved)
31
16 15
0000000000000000
GPIOSD_SDn_PRESCALE
87
0xff
GPIOSD_SDn_IN
0
0x0
Reset
GPIOSD_SDn_IN SDM bc/ GPIOSD_SDn_PRESCALE APB_CLK bc/
191
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
Register 5.37. GPIOSD_SIGMADELTA_CG_REG (0x0020)
GPIOSD_CLK_EN
(reserved)
31 30
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
GPIOSD_CLK_EN SDM bc/
Register 5.38. GPIOSD_SIGMADELTA_MISC_REG (0x0024)
GPIOSGDP_IOSPSDI__SFWUANPCTION_CLK_EN
(reserved)
31 30 29
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
GPIOSD_FUNCTION_CLK_EN SDM bc/ GPIOSD_SPI_SWAP bc/
(reserved)
31
28 27
0000
Register 5.39. GPIOSD_SIGMADELTA_VERSION_REG (0x0028)
GPIOSD_GPIO_SD_DATE 0x1802260
GPIOSD_GPIO_SD_DATE bc/
0
Reset
192
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
5.15.4 GPIO
Register 5.40. DEDIC_GPIO_OUT_DRT_REG (0x0000)
(reserved)
31
87
000000000000000000000000
DEDIC_GPIO_OUT_DRT_VLAUE
0
0x0
Reset
DEDIC_GPIO_OUT_DRT_VLAUE 8 GPIO bc
Register 5.41. DEDIC_GPIO_OUT_MSK_REG (0x0004)
(reserved)
31
16 15
0000000000000000
DEDIC_GPIO_OUT_MSK
87
0x0
DEDIC_GPIO_OUT_VALUE
0
0x0
Reset
DEDIC_GPIO_OUT_VALUE 8 GPIO bc DEDIC_GPIO_OUT_MSK cb 1 bc
193
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
Register 5.42. DEDIC_GPIO_OUT_IDV_REG (0x0008)
(reserved)
DEDIC_GPIODE_DOIUCT__GIPDIVOD_E_CDOHIUC7T__GIPDIVOD_E_CDOHIUC6T__GIPDIVOD_E_CDOHIUC5T__GIPDIVOD_E_CDOHIUC4T__GIPDIVOD_E_CDOHIUC3T__GIPDIVOD_E_CDOHIUC2T__GIPDIVO__COHU1T_IDV_CH0
31
16 15 14 13 12 11 10 9
87
65
43
21
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Reset
DEDIC_GPIO_OUT_IDV_CH0 0 b0b1b2b 3bc
DEDIC_GPIO_OUT_IDV_CH1 1 b0b1b2b 3bc
DEDIC_GPIO_OUT_IDV_CH2 2 b0b1b2b 3bc
DEDIC_GPIO_OUT_IDV_CH3 3 b0b1b2b 3bc
DEDIC_GPIO_OUT_IDV_CH4 4 b0b1b2b 3bc
DEDIC_GPIO_OUT_IDV_CH5 5 b0b1b2b 3bc
DEDIC_GPIO_OUT_IDV_CH6 6 b0b1b2b 3bc
DEDIC_GPIO_OUT_IDV_CH7 7 b0b1b2b 3bc
194
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
Register 5.43. DEDIC_GPIO_OUT_CPU_REG (0x0010)
(reserved)
DEDICD_EGDPICIOD_E_GDOPIUCIODT_E__GDOCPIUPCIODUT_E___GDOCSPIUPECIODLUT_7E___GDOCSPIUPECIODLUT_6E___GDOCSPIUPECIODLUT_5E___GDOCSPIUPECIOLUT_4___GOCSPUPEIOLUT3___OCSUPELUT2__CSPELU1_SEL0
31
87 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
DEDIC_GPIO_OUT_CPU_SEL0 0 GPIO CPU b0 b1 CPU bc/
DEDIC_GPIO_OUT_CPU_SEL1 1 GPIO CPU b0 b1 CPU bc/
DEDIC_GPIO_OUT_CPU_SEL2 2 GPIO CPU b0 b1 CPU bc/
DEDIC_GPIO_OUT_CPU_SEL3 3 GPIO CPU b0 b1 CPU bc/
DEDIC_GPIO_OUT_CPU_SEL4 4 GPIO CPU b0 b1 CPU bc/
DEDIC_GPIO_OUT_CPU_SEL5 5 GPIO CPU b0 b1 CPU bc/
DEDIC_GPIO_OUT_CPU_SEL6 6 GPIO CPU b0 b1 CPU bc/
DEDIC_GPIO_OUT_CPU_SEL7 7 GPIO CPU b0 b1 CPU bc/
195
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
Register 5.44. DEDIC_GPIO_IN_DLY_REG (0x0014)
(reserved)
DEDIC_GPIODE_DINIC__DGLYP_IODCE_HDI7NIC__DGLYP_IODCE_HDI6NIC__DGLYP_IODCE_HDI5NIC__DGLYP_IODCE_HDI4NIC__DGLYP_IODCE_HDI3NIC__DGLYP_IODCE_HDI2NIC__DGLYP_IOC_HI1N_DLY_CH0
31
16 15 14 13 12 11 10 9
87
65
43
21
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Reset
DEDIC_GPIO_IN_DLY_CH0 GPIO0 b0b1b2 b3bc/
DEDIC_GPIO_IN_DLY_CH1 GPIO1 b0b1b2 b3bc/
DEDIC_GPIO_IN_DLY_CH2 GPIO2 b0b1b2 b3bc/
DEDIC_GPIO_IN_DLY_CH3 GPIO3 b0b1b2 b3bc/
DEDIC_GPIO_IN_DLY_CH4 GPIO4 b0b1b2 b3bc/
DEDIC_GPIO_IN_DLY_CH5 GPIO5 b0b1b2 b3bc/
DEDIC_GPIO_IN_DLY_CH6 GPIO6 b0b1b2 b3bc/
DEDIC_GPIO_IN_DLY_CH7 GPIO7 b0b1b2 b3bc/
196
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
Register 5.45. DEDIC_GPIO_INTR_RCGN_REG (0x001C)
(reserved)
DEDIC_GPIO_INTDRE_DMICO_DGEP_IOCH_I7NTDRE_DMICO_DGEP_IOCH_I6NTDRE_DMICO_DGEP_IOCH_I5NTDRE_DMICO_DGEP_IOCH_I4NTDRE_DMICO_DGEP_IOCH_I3NTDRE_DMICO_DGEP_IOCH_I2NTDRE_DMICO_DGEP_IOCH_I1NTR_MODE_CH0
31
24 23
21 20
18 17
15 14
12 11
98
65
32
0
0 0 0 0 0 0 0 0 0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0 Reset
DEDIC_GPIO_INTR_MODE_CH0 0 b0/1b2b 3b4b5b6/7bc/
DEDIC_GPIO_INTR_MODE_CH1 1 b0/1b2b3 b4b5b6/7bc/
DEDIC_GPIO_INTR_MODE_CH2 2 b0/1b2b 3b4b5b6/7bc/
DEDIC_GPIO_INTR_MODE_CH3 3 b0/1b2b 3b4b5b6/7bc/
DEDIC_GPIO_INTR_MODE_CH4 4 b0/1b2b 3b4b5b6/7bc/
DEDIC_GPIO_INTR_MODE_CH5 5 b0/1b2b 3b4b5b6/7bc/
DEDIC_GPIO_INTR_MODE_CH6 6 b0/1b2b 3b4b5b6/7bc/
DEDIC_GPIO_INTR_MODE_CH7 7 b0/1b2b 3b4b5b6/7bc/
Register 5.46. DEDIC_GPIO_OUT_SCAN_REG (0x000C)
(reserved)
31
87
000000000000000000000000
DEDIC_GPIO_OUT_STATUS
0
0x0
Reset
DEDIC_GPIO_OUT_STATUS DEDIC_GPIO_OUT_DRT_REGaDEDIC_GPIO_OUT_MSK_REG DEDIC_GPIO_OUT_IDV_REG GPIO bc
197
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
Register 5.47. DEDIC_GPIO_IN_SCAN_REG (0x0018)
(reserved)
31
87
000000000000000000000000
DEDIC_GPIO_IN_STATUS
0
0x0
Reset
DEDIC_GPIO_IN_STATUS DEDIC_GPIO_IN_DLY_REG GPIO bc
Register 5.48. DEDIC_GPIO_INTR_RAW_REG (0x0020)
(reserved)
DEDICD_EGDPICIOD_7EG_DPIINCIODT_E6_GD_RPIIACNIODW_TE5G_D_RPIINCAIODW_TE4G_D_RPIINCAIODWT_E3_GD_RPIIANCIODW_TE2G_D_RPIICNAIOW_T1G__RPINAIOTW0_R_AINWT_RAW
31
87 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
DEDIC_GPIO0_INT_RAW GPIO0 DEDIC_GPIO_INTR_RCGN_REG bc
DEDIC_GPIO1_INT_RAW GPIO1 DEDIC_GPIO_INTR_RCGN_REG bc
DEDIC_GPIO2_INT_RAW GPIO2 DEDIC_GPIO_INTR_RCGN_REG bc
DEDIC_GPIO3_INT_RAW GPIO3 DEDIC_GPIO_INTR_RCGN_REG bc
DEDIC_GPIO4_INT_RAW GPIO4 DEDIC_GPIO_INTR_RCGN_REG bc
DEDIC_GPIO5_INT_RAW GPIO5 DEDIC_GPIO_INTR_RCGN_REG bc
DEDIC_GPIO6_INT_RAW GPIO6 DEDIC_GPIO_INTR_RCGN_REG bc
DEDIC_GPIO7_INT_RAW GPIO7 DEDIC_GPIO_INTR_RCGN_REG bc
198
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
Register 5.49. DEDIC_GPIO_INTR_RLS_REG (0x0024)
(reserved)
DEDICD_EGDPICIOD_7EG_DPIINCIODT_E6_GD_EPIINCNIODA_TE5G_D_EPIINNCIOD_TAE4G_D_EPIINNCIODTA_E3_GD_EPIINNCIODA_TE2G_D_EPIINCNIOA_T1G__EPINNIOTA0_E_NINAT_ENA
31
87 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
DEDIC_GPIO0_INT_ENA DEDIC_GPIO0_INT_ST bc/ DEDIC_GPIO1_INT_ENA DEDIC_GPIO1_INT_ST bc/ DEDIC_GPIO2_INT_ENA DEDIC_GPIO2_INT_ST bc/ DEDIC_GPIO3_INT_ENA DEDIC_GPIO3_INT_ST bc/ DEDIC_GPIO4_INT_ENA DEDIC_GPIO4_INT_ST bc/ DEDIC_GPIO5_INT_ENA DEDIC_GPIO5_INT_ST bc/ DEDIC_GPIO6_INT_ENA DEDIC_GPIO6_INT_ST bc/ DEDIC_GPIO7_INT_ENA DEDIC_GPIO7_INT_ST bc/
199
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
Register 5.50. DEDIC_GPIO_INTR_ST_REG (0x0028)
(reserved)
DEDICD_EGDPICIOD_7EG_DPIINCIODT_E6_GD_SPIITCNIOD_TE5G_D_SPIITNCIOD_TE4G_D_SPIITNCIODT_E3_GD_SPIITNCIOD_TE2G_D_SPIITCNIO_T1G__SPINTIOT0_S_TINT_ST
31
87 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
DEDIC_GPIO0_INT_ST DEDIC_GPIO0_INT_RAW DEDIC_GPIO0_INT_ENA = 1 bc
DEDIC_GPIO1_INT_ST DEDIC_GPIO1_INT_RAW DEDIC_GPIO1_INT_ENA = 1 bc
DEDIC_GPIO2_INT_ST DEDIC_GPIO2_INT_RAW DEDIC_GPIO2_INT_ENA = 1 bc
DEDIC_GPIO3_INT_ST DEDIC_GPIO3_INT_RAW DEDIC_GPIO3_INT_ENA = 1 bc
DEDIC_GPIO4_INT_ST DEDIC_GPIO4_INT_RAW DEDIC_GPIO4_INT_ENA = 1 bc
DEDIC_GPIO5_INT_ST DEDIC_GPIO5_INT_RAW DEDIC_GPIO5_INT_ENA = 1 bc
DEDIC_GPIO6_INT_ST DEDIC_GPIO6_INT_RAW DEDIC_GPIO6_INT_ENA = 1 bc
DEDIC_GPIO7_INT_ST DEDIC_GPIO7_INT_RAW DEDIC_GPIO7_INT_ENA = 1 bc
200
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
Register 5.51. DEDIC_GPIO_INTR_CLR_REG (0x002C)
(reserved)
DEDICD_EGDPICIOD_7EG_DPIINCIODT_E6_GD_CPIILCNIODR_TE5G_D_CPIINCLIODR_TE4G_D_CPIINCLIODRT_E3_GD_CPIINLCIODR_TE2G_D_CPIICNLIOR_T1G__CPINLIOTR0_C_LINRT_CLR
31
87 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
DEDIC_GPIO0_INT_CLR DEDIC_GPIO0_INT_RAW bc DEDIC_GPIO1_INT_CLR DEDIC_GPIO1_INT_RAW bc DEDIC_GPIO2_INT_CLR DEDIC_GPIO2_INT_RAW bc DEDIC_GPIO3_INT_CLR DEDIC_GPIO3_INT_RAW bc DEDIC_GPIO4_INT_CLR DEDIC_GPIO4_INT_RAW bc DEDIC_GPIO5_INT_CLR DEDIC_GPIO5_INT_RAW bc DEDIC_GPIO6_INT_CLR DEDIC_GPIO6_INT_RAW bc DEDIC_GPIO7_INT_CLR DEDIC_GPIO7_INT_RAW bc
5.15.5 RTC IO MUX
Register 5.52. RTCIO_RTC_GPIO_OUT_REG (0x0000)
RTCIO_GPIO_OUT_DATA
(reserved)
31
10 9
0
0
0 0 0 0 0 0 0 0 0 0 Reset
RTCIO_GPIO_OUT_DATA GPIO0 ~ 21 bbit10 GPIO0bit11 GPIO1 bc/
201
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
Register 5.53. RTCIO_RTC_GPIO_OUT_W1TS_REG (0x0004)
RTCIO_GPIO_OUT_DATA_W1TS
(reserved)
31
10 9
0
0
0 0 0 0 0 0 0 0 0 0 Reset
RTCIO_GPIO_OUT_DATA_W1TS GPIO0 ~ 21 CIO_RTC_GPIO_OUT_REG CIO_RTC_GPIO_OUT_REGbc
b 1RT1b RT-
Register 5.54. RTCIO_RTC_GPIO_OUT_W1TC_REG (0x0008)
RTCIO_GPIO_OUT_DATA_W1TC
(reserved)
31
10 9
0
0
0 0 0 0 0 0 0 0 0 0 Reset
RTCIO_GPIO_OUT_DATA_W1TC GPIO0 ~ 21 b 1 RTCIO_RTC_GPIO_OUT_REG b RTCIO_RTC_GPIO_OUT_REGbc
Register 5.55. RTCIO_RTC_GPIO_ENABLE_REG (0x000C)
RTCIO_GPIO_ENABLE
(reserved)
31
10 9
0
0
0 0 0 0 0 0 0 0 0 0 Reset
RTCIO_GPIO_ENABLE GPIO0 ~ 21 bbit10 GPIO0, bit11 GPIO1b 1 GPIO pad bc/
202
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
Register 5.56. RTCIO_RTC_GPIO_ENABLE_W1TS_REG (0x0010)
RTCIO_GPIO_ENABLE_W1TS
(reserved)
31
10 9
0
0
0 0 0 0 0 0 0 0 0 0 Reset
RTCIO_GPIO_ENABLE_W1TS GPIO0 ~ 21 b 1 RTCIO_RTC_GPIO_ENABLE_REG 1b RTCIO_RTC_GPIO_ENABLE_REGbc
Register 5.57. RTCIO_RTC_GPIO_ENABLE_W1TC_REG (0x0014)
RTCIO_GPIO_ENABLE_W1TC
(reserved)
31
10 9
0
0
0 0 0 0 0 0 0 0 0 0 Reset
RTCIO_GPIO_ENABLE_W1TC GPIO0 ~ 21 b 1 RTCIO_RTC_GPIO_ENABLE_REG b RTCIO_RTC_GPIO_ENABLE_REGbc
Register 5.58. RTCIO_RTC_GPIO_STATUS_REG (0x0018)
RTCIO_GPIO_STATUS_INT
(reserved)
31
10 9
0
0
0 0 0 0 0 0 0 0 0 0 Reset
RTCIO_GPIO_STATUS_INT GPIO0 ~ 21 bbit10 GPIO0bit11 GPIO1 b RTCIO_RTC_GPIO_PINn_REG RTCIO_RTC_GPIO_PINn_INT_TYPE b01 bc/
203
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
Register 5.59. RTCIO_RTC_GPIO_STATUS_W1TS_REG (0x001C)
RTCIO_GPIO_STATUS_INT_W1TS
(reserved)
31
10 9
0
0
0 0 0 0 0 0 0 0 0 0 Reset
RTCIO_GPIO_STATUS_INT_W1TS GPIO0 ~ 21 b 1 RTCIO_GPIO_STATUS_INT 1b RTCIO_GPIO_STATUS_INTbc
Register 5.60. RTCIO_RTC_GPIO_STATUS_W1TC_REG (0x0020)
RTCIO_GPIO_STATUS_INT_W1TC
(reserved)
31
10 9
0
0
0 0 0 0 0 0 0 0 0 0 Reset
RTCIO_GPIO_STATUS_INT_W1TC GPIO0 ~ 21 b 1 RTCIO_GPIO_STATUS_INT b RTCIO_GPIO_STATUS_INTbc
Register 5.61. RTCIO_RTC_GPIO_IN_REG (0x0024)
RTCIO_GPIO_IN_NEXT
(reserved)
31
10 9
0
0
0 0 0 0 0 0 0 0 0 0 Reset
RTCIO_GPIO_IN_NEXT GPIO0 ~ 21 bbit10 GPIO0bit11 GPIO1b bit pad bit 1 bit 0bc
204
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
Register 5.62. RTCIO_RTC_GPIO_PINn_REG (n: 0-21) (0x0028+4*n)
(reserved)
RTCIO_GPIORT_CPIION_nG_WPIAOK_EPUINPn__E(INrNeATsBe_LTrvEYePdE)
RTCIO_G(PreIOse_rPvIeNdn)_PAD_DRIVER
31
11 10 9
76
321
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00
0
0 0 0 0 0 0 0 Reset
RTCIO_GPIO_PINn_PAD_DRIVER Pad b01bc/
RTCIO_GPIO_PINn_INT_TYPE GPIO bc/
0 GPIO 1 2 3 4 5 RTCIO_GPIO_PINn_WAKEUP_ENABLE GPIO b ESP32-S2 Light-sleep bc/
205
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
Register 5.63. RTCIO_TOUCH_PADn_REG (n: 0-14) (0x0084+4*n)
(reservedR)TCIO_TROTUCCIOHR__TTPCOAIUDO(Cn_reT_HsOD_eURPrvCAVeDHdn_)_PRRATDDCEnI_OR_TUOEURCTHC_IOPRA_TTDCOnIU_ORCD_TTAHCOC_IUOPRCA_TTDHCOn_IU_OPSCA_TTDHAROn_RTU_PCTTCAIIDOHE_n__TO_PROXAPTPUDTCDCnI_OHRM__TTPUCOAXIUDO_RCn_STT_HECOF_LIUUOPRCNA_TTDH_COSn_IU_OEPSLCA_TLDHOPn__U_PSSCAELDHLPn___PISAELDPn__OFEUN_IE
(reserved)
31 30 29 28 27 26 25
23 22 21 20 19 18 17 16 15 14 13 12
0
0 2 1 00
0x4
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTCIO_TOUCH_PADn_FUN_IE bc/ RTCIO_TOUCH_PADn_SLP_OE bc/ RTCIO_TOUCH_PADn_SLP_IE bc/ RTCIO_TOUCH_PADn_SLP_SEL 01bc/ RTCIO_TOUCH_PADn_FUN_SEL Function c/ RTCIO_TOUCH_PADn_MUX_SEL RTC pad pad 0bc/ RTCIO_TOUCH_PADn_XPD bc/ RTCIO_TOUCH_PADn_TIE_OPT b01bc/ RTCIO_TOUCH_PADn_START bc/ RTCIO_TOUCH_PADn_DAC b pad 3-bit 0x4bc/ RTCIO_TOUCH_PADn_RUE pad b10bc/ RTCIO_TOUCH_PADn_RDE pad b10bc/ RTCIO_TOUCH_PADn_DRV pad b0~5 mA1~10 mA2~20 mA3~40
mAbc/
206
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
Register 5.64. RTCIO_XTAL_32P_PAD_REG (0x00C0)
(reservedR)TCIO_XR3T2CPI_ORD_TRXCV3I2OP__XR3D2PE_RUE
(reserved)
RTCIO_XR3T2CPI_OM_XUR3XT2_CPSI_OERF_LTUXCN3I2O_RPS_T_EXCSL3IL2ORPP_T__XCSS3IEL2OLPP___XIS3EL2PP__OFEUN_IE
(reserved)
31 30 29 28 27 26
20 19 18 17 16 15 14 13 12
0
0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTCIO_X32P_FUN_IE pad bc/ RTCIO_X32P_SLP_OE pad bc/ RTCIO_X32P_SLP_IE pad bc/ RTCIO_X32P_SLP_SEL 10bc/ RTCIO_X32P_FUN_SEL Function bc/ RTCIO_X32P_MUX_SEL 1 RTC GPIO0 GPIObc/ RTCIO_X32P_RUE Pad b10bc/ RTCIO_X32P_RDE Pad b10bc/ RTCIO_X32P_DRV pad b0~5 mA1~10 mA2~20 mA3~40 mAbc/
207
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
Register 5.65. RTCIO_XTAL_32N_PAD_REG (0x00C4)
(reservedR)TCIO_XR3T2CNIO_RD_TRXC3VI2ON__X3R2DNE_RUE
(reserved)
RTCIO_XR3T2CNIO_M_XUR3XT2_CNSIO_ERF_LTUXC3NI2O_RNS_T_EXC3SLI2LORPN_T__XCS3SIE2LOLPN___XI3SE2LPN__OFEUN_IE
(reserved)
31 30 29 28 27 26
20 19 18 17 16 15 14 13 12
0
0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTCIO_X32N_FUN_IE bc/ RTCIO_X32N_SLP_OE bc/ RTCIO_X32N_SLP_IE bc/ RTCIO_X32N_SLP_SEL 10bc/ RTCIO_X32N_FUN_SEL Function bc/ RTCIO_X32N_MUX_SEL 1 RTC GPIO0 GPIObc/ RTCIO_X32N_RUE Pad b10bc/ RTCIO_X32N_RDE Pad b10bc/ RTCIO_X32N_DRV pad b0~5 mA1~10 mA2~20 mA3~40 mAbc/
208
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
Register 5.66. RTCIO_PAD_DAC1_REG (0x00C8)
(reservedR)TCIO_PRDTACCIO1R__TDPCRDIVOAC_P1_DRADCE1_RUE (reserved)
31 30 29 28 27 26
RTCIO_PRDTACCIO1__MPRDUTAXCC_IOS1R_E_TFLPCUDINOAR_C_TSP1C_EDISLOARLC_PTP1C__DSISOAERLC_LPTP1C__DIISEOARLC_PTP1C__DOIFOAEUC_NP1__DDIAEACC1__XXPPDD__DFOACRRCTECIO_PDAC1_DAC
20 19 18 17 16 15 14 13 12 11 10
32
0 2 0 00 0 0 0 0 0 00 0 0 0 0 0 0 0
0
0
(reserved)
0
0 0 Reset
RTCIO_PDAC1_DAC RTCIO_PDAC1_DAC_XPD_FORCE 1 DAC_1 bc/ RTCIO_PDAC1_XPD_DAC RTCIO_PDAC1_DAC_XPD_FORCE 1 1 DAC_1 0
DAC_1 bc/ RTCIO_PDAC1_DAC_XPD_FORCE 1 RTCIO_PDAC1_XPD_DAC DAC_1 0
SAR ADC FSM DAC_1 bc/ RTCIO_PDAC1_FUN_IE bc/ RTCIO_PDAC1_SLP_OE bc/ RTCIO_PDAC1_SLP_IE bc/ RTCIO_PDAC1_SLP_SEL 10bc/ RTCIO_PDAC1_FUN_SEL DAC_1 bc/ RTCIO_PDAC1_MUX_SEL 1 RTC GPIO0 GPIObc/ RTCIO_PDAC1_RUE Pad b10bc/ RTCIO_PDAC1_RDE Pad b10bc/ RTCIO_PDAC1_DRV pad b0~5 mA1~10 mA2~20 mA3~40 mAbc/
209
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
Register 5.67. RTCIO_PAD_DAC2_REG (0x00CC)
(reservedR)TCIO_PRDTACCIO2R__TPDCDRIOAVC_P2D_RACD2E_RUE (reserved)
31 30 29 28 27 26
RTCIO_PRDTACCIO2__PMRDUTACXC_IO2SR__ETPFLCUDIONARC__TP2SCD_EIOSLARCL_TPP2C_D_ISOSARECL_TLPP2C_D_IIOSAERCL_TPP2C_D_IOOFAEUC_PN2D__DAIECAC2__XXPPDD__DFOACRRCTECIO_PDAC2_DAC
20 19 18 17 16 15 14 13 12 11 10
32
0 2 0 00 0 0 0 0 0 00 0 0 0 0 0 0 0
0
0
(reserved)
0
0 0 Reset
RTCIO_PDAC2_DAC RTCIO_PDAC2_DAC_XPD_FORCE 1 DAC_2 bc/ RTCIO_PDAC2_XPD_DAC RTCIO_PDAC2_DAC_XPD_FORCE 1 1 DAC_2 0
DAC_2 bc/ RTCIO_PDAC2_DAC_XPD_FORCE 1 RTCIO_PDAC2_XPD_DAC DAC_2 0
SAR ADC FSM DAC_2 bc/ RTCIO_PDAC2_FUN_IE bc/ RTCIO_PDAC2_SLP_OE bc/ RTCIO_PDAC2_SLP_IE bc/ RTCIO_PDAC2_SLP_SEL 10bc/ RTCIO_PDAC2_FUN_SEL DAC_2 bc/ RTCIO_PDAC2_MUX_SEL 1 RTC GPIO0 GPIObc/ RTCIO_PDAC2_RUE Pad b10bc/ RTCIO_PDAC2_RDE Pad b10bc/ RTCIO_PDAC2_DRV pad b0~5 mA1~10 mA2~20 mA3~40 mAbc/
210
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
Register 5.68. RTCIO_RTC_PAD19_REG (0x00D0)
(reservedR)TCIO_RRTTCC_IOPRA_TDRC1T9ICO___DPRRATVDC1_9P_ARDD19E_RU(rEeserved)
RTCIO_RRTTCC_IOPA_DRR1T9TCC__MIOPRUA_TDXRC_1T9ISCO_RE__FTLPRUCATNIDCO_R1__9STPRC_EATSLIDCOL1__P9PR__ATSSDCEL1_LP9P__AISEDL1P9__OFEUN_IE
(reserved)
31 30 29 28 27 26
20 19 18 17 16 15 14 13 12
0
0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTCIO_RTC_PAD19_FUN_IE bc/ RTCIO_RTC_PAD19_SLP_OE bc/ RTCIO_RTC_PAD19_SLP_IE bc/ RTCIO_RTC_PAD19_SLP_SEL 10bc/ RTCIO_RTC_PAD19_FUN_SEL bc/ RTCIO_RTC_PAD19_MUX_SEL 1 RTC GPIO2 GPIObc/ RTCIO_RTC_PAD19_RUE Pad b10bc/ RTCIO_RTC_PAD19_RDE Pad b10bc/ RTCIO_RTC_PAD19_DRV Pad b0~5 mA1~10 mA2~20 mA3~40 mAcb/
211
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
Register 5.69. RTCIO_RTC_PAD20_REG (0x00D4)
(reservedR)TCIO_RRTTCC_IOPRA_TDRC2TI0CO___DPRARTDCV2_0PA_DRD20E_R(UreEserved)
RTCIO_RRTTCC_IOPA_DRR2TT0CC__IMOPRA_UTDRXC2T_I0COSR___ETFPRLCUATIDCNOR2___T0SPRCA_ETIDSLCOL2__P0PR_A_TSDSCEL2_LP0P_A_IDSEL2P0__OFEUN_IE
(reserved)
31 30 29 28 27 26
20 19 18 17 16 15 14 13 12
0
0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTCIO_RTC_PAD20_FUN_IE bc/ RTCIO_RTC_PAD20_SLP_OE bc/ RTCIO_RTC_PAD20_SLP_IE bc/ RTCIO_RTC_PAD20_SLP_SEL 10bc/ RTCIO_RTC_PAD20_FUN_SEL bc/ RTCIO_RTC_PAD20_MUX_SEL 1 RTC GPIO0 GPIObc/ RTCIO_RTC_PAD20_RUE Pad b10bc/ RTCIO_RTC_PAD20_RDE Pad b10bc/ RTCIO_RTC_PAD20_DRV Pad b0~5 mA1~10 mA2~20 mA3~40
mAbc/
212
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
Register 5.70. RTCIO_RTC_PAD21_REG (0x00D8)
(reservedR)TCIO_RRTTCC_IOPRA_TDRC2TI1CO___DPRRATVDC2_1P_ARDD2E1_RU(rEeserved)
RTCIO_RRTTCC_IOPA_DRR2TT1CC__MIOPRUA_TDXRC_2TIS1CO_RE__FTLPRUCATNIDCO_R2__ST1PRC_EATSLIDCOL2__P1PR__ATSSDCEL2_LP1P__AISEDL2P1__OFEUN_IE
(reserved)
31 30 29 28 27 26
20 19 18 17 16 15 14 13 12
0
0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTCIO_RTC_PAD21_FUN_IE bc/ RTCIO_RTC_PAD21_SLP_OE bc/ RTCIO_RTC_PAD21_SLP_IE bc/ RTCIO_RTC_PAD21_SLP_SEL 10bc/ RTCIO_RTC_PAD21_FUN_SEL bc/ RTCIO_RTC_PAD21_MUX_SEL 1 RTC GPIO0 GPIObc/ RTCIO_RTC_PAD21_RUE Pad b10bc/ RTCIO_RTC_PAD21_RDE Pad b10bc/ RTCIO_RTC_PAD21_DRV Pad b0~5 mA1~10 mA2~20 mA3~40 mAcb/
Register 5.71. RTCIO_XTL_EXT_CTR_REG (0x00E0)
RTCIO_XTL_EXT_CTR_SEL
(reserved)
31
27 26
0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTCIO_XTL_EXT_CTR_SEL b0 GPIO01 GPIO1 b RTC_CNTL_EXT_XTL_CONF_REG[30] bc/
213
ESP32-S2 TRM ( 1.3)
5 IO MUX GPIO
GoBack
Register 5.72. RTCIO_SAR_I2C_IO_REG (0x00E4)
RTCIO_SARR_TI2CCIO__SSDAAR__SIE2LC_SCL_SEL
(reserved)
31 30 29 28 27
0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTCIO_SAR_I2C_SCL_SEL RTC I2C SCL padb0 TOUCH_PAD01 TOUCH_PAD2bc/
RTCIO_SAR_I2C_SDA_SEL RTC I2C SDA padb0 TOUCH_PAD11 TOUCH_PAD3bc/
214
ESP32-S2 TRM ( 1.3)
6
GoBack
6
6.1
6.1.1
CPU aab b 6.1-1 b
6.1-1.
· CPU CPU core CPU reset vector · RTC CPUaaWi-Fi GPIO · RTC · b
215
ESP32-S2 TRM ( 1.3)
6
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6.1.2
CPU bCPU RTC_CNTL_RESET_CAUSE_PROCPU b 6.1-1 b
6.1-1.
0x01 0x0F 0x10 0x12 0x13 0x03 0x05 0x07 0x08 0x09 0x14 0x0B 0x0C 0x0D 0x11
RWDT GLITCH Deep-sleep MWDT0 MWDT1 RWDT eFuse MWDT0 CPU CPU RWDT CPU MWDT1 CPU
CPU CPU CPU CPU
12 (WDT) 12 (WDT) RTC_CNTL_SW_SYS_RST 9 12 (WDT) 12 (WDT) 12 (WDT) eFuse CRC 12 (WDT) RTC_CNTL_SW_PROCPU_RST 12 (WDT) 12 (WDT)
· (SWD) · b 9 b
6.2
6.2.1
ESP32-S2 CPUaa RTC b 6.2-1 b
216
ESP32-S2 TRM ( 1.3)
6
GoBack
6.2-1.
6.2.2
ESP32-S2 a PLL b b
· CPU PLL_CLK320 MHz 480 MHz PLL XTAL_CLK40 MHz b
· XTAL32K_CLK32 kHz RC_FAST_CLK 8 MHz N RC_FAST_DIV_CLK RC_FAST_CLK 256 RC_FAST_CLK / 256b RC_FAST_CLK 8 MHz 31.250 kHz RC_SLOW_CLK90 kHz b
·
217
ESP32-S2 TRM ( 1.3)
6
GoBack
APLL_CLK16 MHz ~ 128 MHz Audio PLL b
6.2.3 CPU
6.2-1 CPU_CLK CPU CPU 240 MHzbCPU c 2 MHzb CPU_CLK SYSTEM_SOC_CLK_SEL PLL_CLKaAPLL_CLKaRC_FAST_CLK XTAL_CLK CPU_CLK b 6.2-1 6.2-2b
ESP32-S2 b
SYSTEM_SOC_CLK_SEL 0 1 2 3
6.2-1. CPU_CLK
XTAL_CLK PLL_CLK RC_FAST_CLK APLL_CLK
6.2-2. CPU_CLK
XTAL_CLK
SEL_0* SEL_1* SEL_2*
0
-
-
PLL_CLK (480 MHz)
1
1
0
PLL_CLK (480 MHz)
1
1
1
PLL_CLK (480 MHz)
1
1
2
PLL_CLK (320 MHz)
1
0
0
PLL_CLK (320 MHz)
1
0
1
RC_FAST_CLK
2
-
-
APLL_CLK
3
0
0
APLL_CLK
3
0
1
*SEL_0: SYSTEM_SOC_CLK_SEL
*SEL_1: SYSTEM_PLL_FREQ_SEL
*SEL_2: SYSTEM_CPUPERIOD_SEL b
CPU CPU_CLK = XTAL_CLK / (SYSTEM_PRE_DIV_CNT + 1) SYSTEM_PRE_DIV_CNT 1 0 ~ 1023b CPU_CLK = PLL_CLK / 6 CPU_CLK 80 MHzb CPU_CLK = PLL_CLK / 3 CPU_CLK 160 MHzb CPU_CLK = PLL_CLK / 2 CPU_CLK 240 MHzb CPU_CLK = PLL_CLK / 4 CPU_CLK 80 MHzb CPU_CLK = PLL_CLK / 2 CPU_CLK 160 MHzb CPU_CLK = RC_FAST_CLK / (SYSTEM_PRE_DIV_CNT + 1) SYSTEM_PRE_DIV_CNT 1 0 ~ 1023b CPU_CLK = APLL_CLK / 4 CPU_CLK = APLL_CLK / 2
· CPU XTAL_CLK SYSTEM_PRE_DIV_CNT XTAL_CLK
218
ESP32-S2 TRM ( 1.3)
6
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x cx 1 2 cSYSTEM_PRE_DIV_CNT = 1 1 cSYSTEM_PRE_DIV_CNT = 0 x
cSYSTEM_PRE_DIV_CNT = x - 1
2 x cSYSTEM_PRE_DIV_CNT = x - 1 1 cSYSTEM_PRE_DIV_CNT = 0 2
cSYSTEM_PRE_DIV_CNT = 1
xcSYSTEM_PRE_DIV_CNT = x - 1b
6.2.4
APB_CLKaREF_TICKaLEDC_PWM_CLKaAPLL_CLK PLL_F160M_CLKb 6.2-3 b
6.2-3.
TIMG I2S UHCI UART RMT LED_PWM I2C SPI PCNT eFuse Controller SARADC/DAC USB CRYPTO TWAI Controller System Timer
APB_CLK Y Y Y Y Y Y Y Y Y Y
Y Y
Y Y
REF_TICK Y
Y Y Y Y
LEDC_PWM_CLK Y
APLL_CLK Y
Y
PLL_F160M_CLK Y
Y
6.2.4.1 APB_CLK
6.2-4 APB_CLK CPU_CLK b
6.2-4. APB_CLK
CPU_CLK PLL_CLK APLL_CLK XTAL_CLK RC_FAST_CLK
APB_CLK 80 MHz CPU_CLK / 2 CPU_CLK CPU_CLK
219
ESP32-S2 TRM ( 1.3)
6
GoBack
6.2.4.2 REF_TICK
REF_TICK APB_CLK APB_CLK CPU_CLK bREF_TICK CPU_CLK b 6.2-5
6.2-5. REF_TICK
CPU_CLK PLL_CLK APLL_CLK XTAL_CLK RC_FAST_CLK
APB_CLK 80 MHz CPU_CLK/2 CPU_CLK CPU_CLK
REF_TICK APB_CLK/(SYSCON_XTAL_TICK_NUM + 1) APB_CLK/(SYSCON_XTAL_TICK_NUM + 1) APB_CLK/ (SYSCON_XTAL_TICK_NUM + 1) APB_CLK/(SYSCON_CK8M_TICK_NUM + 1)
REF_TICK 1 MHz CPU_CLK PLL_CLK REF_TICK = 80 MHz/ (SYSCON_XTAL_TICK_NUM + 1) = 1 MHz SYSCON_XTAL_TICK_NUM 79 (0x4F)b
6.2.4.3 LEDC_PWM_CLK
LEDC_PWM_CLK LEDC_APB_CLK_SEL 6.2-6 b
6.2-6. LEDC_PWM_CLK
LEDC_APB_CLK_SEL 0c 1 2 3
LEDC_PWM_CLK APB_CLK RC_FAST_CLK XTAL_CLK
6.2.4.4 APLL_SCLK
APLL_CLK PLL_CLK APLL b 6.2.7 b
6.2.4.5 PLL_F160M_CLK
PLL_F160M_CLK PLL_CLK PLL b
6.2.4.6
c RMTaI2C PLL_CLK b b REF_TICK b 6.2-3b LED RC_FAST_CLK APB_CLK LED b cAPB_CLK LED RC_FAST_CLK b
6.2.5 Wi-Fi
Wi-Fi APB_CLK PLL_CLK b Wi-Fi PLL_CLKb
220
ESP32-S2 TRM ( 1.3)
6
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LOW_POWER_CLK XTAL32K_CLKaXTAL_CLKaRC_FAST_CLKaRTC_SLOW_CLKcRTC Wi-Fi b
6.2.6 RTC
RTC_SLOW_CLK RTC_FAST_CLK bRTC b RTC_SLOW_CLK RC_SLOW_CLKaXTAL32K_CLK RC_FAST_DIV_CLKb RTC_FAST_CLK XTAL_CLK RC_FAST_CLKb
6.2.7 PLL
ab b
ESP32-S2 I2S PLLb APLL I2S b
Audio PLL
fout
=
fxtal(sdm2
+
sdm1 28
+
sdm0 216
2(odiv + 2)
+ 4)
· fxtal 40 MHz · sdm0 0 ~ 255
· sdm1 0 ~ 255
· sdm2 0 ~ 63
· odiv 0 ~ 31
· 350 MHz ~ 500 MHz
350M Hz
<
fxtal(sdm2
+
sdm1 28
+
sdm0 216
+
4)
<
500M Hz
Audio PLL RTC_CNTL_PLLA_FORCE_PU RTC_CNTL_PLLA_FORCE_PD b RTC_CNTL_PLLA_FORCE_PU RTC_CNTL_PLLA_FORCE_PD 0 PLL b
6.3
SYSCON c 3 3.3-5 b
SYSCON_TICK_CONF_REG
REF_TICK
0x0004 R/W
221
ESP32-S2 TRM ( 1.3)
6
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6.4
SYSCON c 3 3.3-5 b
Register 6.1. SYSCON_TICK_CONF_REG (0x0004)
(reserved)
SYSCON_TICK_ENABLE SYSCON_CK8M_TICK_NUM
31
17 16 15
87
0 0 0 0 0 0 0 0 0 0 0 0 0 0 01
7
SYSCON_XTAL_TICK_NUM
0
39
Reset
SYSCON_XTAL_TICK_NUM CPU_CLK PLL_CLKaXTAL_CLK APLL_CLK REF_TICK b 0x0 ~ 0xFFbREF_TICK = APB_CLK/( + 1)b(R/W)
SYSCON_CK8M_TICK_NUM CPU_CLK RC_FAST_CLK REF_TICK b 0x0 ~ 0xFFbREF_TICK = APB_CLK/( + 1)b(R/W)
SYSCON_TICK_ENABLE REF_TICKb10b(R/W)
222
ESP32-S2 TRM ( 1.3)
7 Boot (BOOTCTRL)
GoBack
7 Boot (BOOTCTRL)
7.1
ESP32-S2 Strapping · GPIO0 · GPIO45 · GPIO46
GPIO_STRAPPING Strapping baRTC a a (analog super watchdog) a 6 Strapping b GPIO0aGPIO45 GPIO46 /b / 7.1-1 b
7.1-1. Strapping /
GPIO0
GPIO45
GPIO46
Strapping / MCU GPIO ESP32-S2 Strapping bStrapping b
Strapping b b
7.2 Boot
GPIO0 GPIO46 Boot b 7.2-1.
GPIO0 GPIO46
SPI Boot 1 x
Download Boot 0 0
223
ESP32-S2 TRM ( 1.3)
7 Boot (BOOTCTRL)
GoBack
7.2-1 GPIO0 GPIO46 Strapping b"x" b ESP32-S2 SPI Boot Download Boot bGPIO0aGPIO46 (0, 1) b
SPI Boot CPU SPI Flash Download Boot UART0aUART1aQPI USB SRAM flash SRAM Download Boot b
eFuse
· EFUSE_DIS_FORCE_DOWNLOAD
eFuse 0c RTC_CNTL_FORCE_DOWNLOAD_BOOT CPU SPI Boot Download Boot b GPIO_STRAPPING[3:2] "1x" "00"
eFuse 1 RTC_CNTL_FORCE_DOWNLOAD_BOOTGPIO_STRAPPING b
· EFUSE_DIS_DOWNLOAD_MODE
eFuse 1 Download Boot bGPIO_STRAPPING RTC_CNTL_FORCE_DOWNLOAD_BOOT b
· EFUSE_ENABLE_SECURITY_DOWNLOAD
eFuse 1 Download Boot a flash SRAM b Download Boot eFuseb
7.3 ROM
ROM ·cUART0 · UART1
EFUSE_UART_PRINT_CHANNEL ROM UART0 UART1b · 0: UART0 · 1: UART1
EFUSE_UART_PRINT_CONTROL GPIO46 UART ROM b
7.3-1. UART ROM
UART ROM EFUSE_UART_PRINT_CONTROL
0
1
2
1
2
3
1 b
GPIO46 0 1 1 0
224
ESP32-S2 TRM ( 1.3)
7 Boot (BOOTCTRL)
GoBack
7.4 VDD_SPI
GPIO45 VDD_SPI · GPIO45 = 0 VDD_SPI VDD3P3_RTC_IO RSP I c 3.3 V · GPIO45 = 1 VDD_SPI LDO c 1.8 Vb
EFUSE_VDD_SPI_FORCE 1 b VDD_SPI EFUSE_VDD_SPI_TIEH
· EFUSE_VDD_SPI_FORCE = 1 EFUSE_VDD_SPI_TIEH = 0 VDD_SPI 1.8 V LDO · EFUSE_VDD_SPI_FORCE = 1 EFUSE_VDD_SPI_TIEH = 1 VDD_SPI VDD3P3_RTC_IOb
225
ESP32-S2 TRM ( 1.3)
8
GoBack
8
8.1
ESP32-S2 (Interrupt Matrix) CPU CPU bb
8.2
· 95 · 26 · CPU NMI · 8.2-1 b
8.2-1.
8.3
8.3.1
ESP32-S2 95 b 8.3-1 b 95 CPU b
226
ESP32-S2 TRM ( 1.3)
8
8.3-1. CPU aa
227
No.
0
reserved
1
reserved
2
PWR_INTR
3
reserved
4
reserved
5
reserved
6
reserved
7
reserved
8
reserved
9
reserved
10
reserved
11
reserved
12
reserved
13
UHCI0_INTR
14
reserved
15
TG_T0_LEVEL_INT
16
TG_T1_LEVEL_INT
17
TG_WDT_LEVEL_INT
18
TG_LACT_LEVEL_INT
19
TG1_T0_LEVEL_INT
20
TG1_T1_LEVEL_INT
21
TG1_WDT_LEVEL_INT
22
TG1_LACT_LEVEL_INT
23
GPIO_INTERRUPT_PRO
24 GPIO_INTERRUPT_PRO_NMI
25
reserved
26
reserved
27 DEDICATED_GPIO_IN_INTR
28 CPU_INTR_FROM_CPU_0
29
CPU_INTR_FROM_CPU_1
30 CPU_INTR_FROM_CPU_2
31
CPU_INTR_FROM_CPU_3
32
SPI_INTR_1
33
SPI_INTR_2
34
SPI_INTR_3
reserved reserved INTERRUPT_PRO_PWR_INTR_MAP_REG reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved INTERRUPT_PRO_UHCI0_INTR_MAP_REG reserved INTERRUPT_PRO_TG_T0_LEVEL_INT_MAP_REG INTERRUPT_PRO_TG_T1_LEVEL_INT_MAP_REG INTERRUPT_PRO_TG_WDT_LEVEL_INT_MAP_REG INTERRUPT_PRO_TG_LACT_LEVEL_INT_MAP_REG INTERRUPT_PRO_TG1_T0_LEVEL_INT_MAP_REG INTERRUPT_PRO_TG1_T1_LEVEL_INT_MAP_REG INTERRUPT_PRO_TG1_WDT_LEVEL_INT_MAP_REG INTERRUPT_PRO_TG1_LACT_LEVEL_INT_MAP_REG INTERRUPT_PRO_GPIO_INTERRUPT_PRO_MAP_REG INTERRUPT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_REG reserved reserved INTERRUPT_PRO_DEDICATED_GPIO_IN_INTR_MAP_REG INTERRUPT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG INTERRUPT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG INTERRUPT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG INTERRUPT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG INTERRUPT_PRO_SPI_INTR_1_MAP_REG INTERRUPT_PRO_SPI_INTR_2_MAP_REG INTERRUPT_PRO_SPI_INTR_3_MAP_REG
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 INTERRUPT_PRO_INTR_STATUS_REG_0_REG
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
1 INTERRUPT_PRO_INTR_STATUS_REG_1_REG
2
ESP32-S2 TRM ( 1.3)
GoBack
228
ESP32-S2 TRM ( 1.3)
No.
35
I2S0_INT
36
reserved
37
UART_INTR
38
UART1_INTR
39
reserved
40
reserved
41
reserved
42
reserved
43
reserved
44
reserved
45
LEDC_INT
46
EFUSE_INT
47
CAN_INT
48
USB_INTR
49
RTC_CORE_INTR
50
RMT_INTR
51
PCNT_INTR
52
I2C_EXT0_INTR
53
I2C_EXT1_INTR
54
RSA_INTR
55
SHA_INTR
56
AES_INTR
57
SPI2_DMA_INT
58
SPI3_DMA_INT
59
reserved
60
TIMER_INT
61
TIMER_INT2
62
TG_T0_EDGE_INT
63
TG_T1_EDGE_INT
64
TG_WDT_EDGE_INT
65
TG_LACT_EDGE_INT
66
TG1_T0_EDGE_INT
67
TG1_T1_EDGE_INT
68
TG1_WDT_EDGE_INT
69
TG1_LACT_EDGE_INT
70
CACHE_IA_INT
71
SYSTIMER_TARGET0_INT
INTERRUPT_PRO_I2S0_INT_MAP_REG reserved
INTERRUPT_PRO_UART_INTR_MAP_REG INTERRUPT_PRO_UART1_INTR_MAP_REG
reserved reserved reserved reserved reserved reserved INTERRUPT_PRO_LEDC_INT_MAP_REG INTERRUPT_PRO_EFUSE_INT_MAP_REG INTERRUPT_PRO_CAN_INT_MAP_REG INTERRUPT_PRO_USB_INTR_MAP_REG INTERRUPT_PRO_RTC_CORE_INTR_MAP_REG INTERRUPT_PRO_RMT_INTR_MAP_REG INTERRUPT_PRO_PCNT_INTR_MAP_REG INTERRUPT_PRO_I2C_EXT0_INTR_MAP_REG INTERRUPT_PRO_I2C_EXT1_INTR_MAP_REG INTERRUPT_PRO_RSA_INTR_MAP_REG INTERRUPT_PRO_SHA_INTR_MAP_REG INTERRUPT_PRO_AES_INTR_MAP_REG INTERRUPT_PRO_SPI2_DMA_INT_MAP_REG INTERRUPT_PRO_SPI3_DMA_INT_MAP_REG reserved INTERRUPT_PRO_TIMER_INT1_MAP_REG INTERRUPT_PRO_TIMER_INT2_MAP_REG INTERRUPT_PRO_TG_T0_EDGE_INT_MAP_REG INTERRUPT_PRO_TG_T1_EDGE_INT_MAP_REG INTERRUPT_PRO_TG_WDT_EDGE_INT_MAP_REG INTERRUPT_PRO_TG_LACT_EDGE_INT_MAP_REG INTERRUPT_PRO_TG1_T0_EDGE_INT_MAP_REG INTERRUPT_PRO_TG1_T1_EDGE_INT_MAP_REG INTERRUPT_PRO_TG1_WDT_EDGE_INT_MAP_REG INTERRUPT_PRO_TG1_LACT_EDGE_INT_MAP_REG INTERRUPT_PRO_CACHE_IA_INT_MAP_REG INTERRUPT_PRO_SYSTIMER_TARGET0_INT_MAP_REG
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19 INTERRUPT_PRO_INTR_STATUS_REG_1_REG
20
21
22
23
24
25
26
27
28
29
30
31
0
1
2
3 INTERRUPT_PRO_INTR_STATUS_REG_2_REG
4
5
6
7
GoBack
8
8
No.
72
SYSTIMER_TARGET1_INT
INTERRUPT_PRO_SYSTIMER_TARGET1_INT_MAP_REG
8
73
SYSTIMER_TARGET2_INT
INTERRUPT_PRO_SYSTIMER_TARGET2_INT_MAP_REG
9
74
ASSIST_DEBUG_INTR
INTERRUPT_PRO_ASSIST_DEBUG_INTR_MAP_REG
10
75 PMS_PRO_IRAM0_ILG_INTR INTERRUPT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_REG 11
76 PMS_PRO_DRAM0_ILG_INTR INTERRUPT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_REG 12
77 PMS_PRO_DPORT_ILG_INTR INTERRUPT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_REG 13
78 PMS_PRO_AHB_ILG_INTR
INTERRUPT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_REG 14
79 PMS_PRO_CACHE_ILG_INTR INTERRUPT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_REG 15
80 PMS_DMA_APB_I_ILG_INTR INTERRUPT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_REG 16
81 PMS_DMA_RX_I_ILG_INTR
INTERRUPT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_REG 17
82 PMS_DMA_TX_I_ILG_INTR
INTERRUPT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_REG 18
83
SPI_MEM_REJECT_INTR
INTERRUPT_PRO_SPI_MEM_REJECT_INTR_MAP_REG
19
84
DMA_COPY_INTR
INTERRUPT_PRO_DMA_COPY_INTR_MAP_REG
20
85
reserved
reserved
21
86
reserved
reserved
22
229
87
DCACHE_PRELOAD_INT
INTERRUPT_PRO_DCACHE_PRELOAD_INT_MAP_REG
23 INTERRUPT_PRO_INTR_STATUS_REG_2_REG
88
ICACHE_PRELOAD_INT
INTERRUPT_PRO_ICACHE_PRELOAD_INT_MAP_REG
24
89
APB_ADC_INT
INTERRUPT_PRO_APB_ADC_INT_MAP_REG
25
90
CRYPTO_DMA_INT
INTERRUPT_PRO_CRYPTO_DMA_INT_MAP_REG
26
91
CPU_PERI_ERROR_INT
INTERRUPT_PRO_CPU_PERI_ERROR_INT_MAP_REG
27
92
APB_PERI_ERROR_INT
INTERRUPT_PRO_APB_PERI_ERROR_INT_MAP_REG
28
93
DCACHE_SYNC_INT
INTERRUPT_PRO_DCACHE_SYNC_INT_MAP_REG
29
94
ICACHE_SYNC_INT
INTERRUPT_PRO_ICACHE_SYNC_INT_MAP_REG
30
ESP32-S2 TRM ( 1.3)
GoBack
8
GoBack
8.3.2 CPU
CPU 32 26 b 8.3-2 · CPU b CPU b NMI CPU b · b b b
ESP32-S2 6 bNMI NMI CPU b
8.3-2. CPU
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
0 NMI 1 2
1 1 1 1 1 1 1 1 1 1 1 3 1 1 NMI 3 5 1 1 2 2 2 3 3 4
230
ESP32-S2 TRM ( 1.3)
8
25 26 27 28 29 30 31
4 5 3 4 3 4 5
GoBack
8.3.3 CPU
· Source_X X 8.3-1b · INTERRUPT_PRO_X_MAP_REG CPU b Source_X b 8.3-1 opopb UHCI0_INTR INTERRUPT_PRO_UHCI0_INTR_MAP_REGb · Interrupt_P CPU Num_P Num_P 0 ~ 5a8 ~ 10a12 ~ 14a 17 ~ 28a30 ~ 31 8.3-2b · Interrupt_I CPU Num_I Num_I 6a7a11a15a16a29 8.3-2b
8.3.3.1 Source_X CPU
Source_X INTERRUPT_PRO_X_MAP_REG Num_P Num_P cInterrupt_PbNum_P CPU 0 ~ 5a8 ~ 10a12 ~ 14a17 ~ 28a30 ~ 31b CPU b
8.3.3.2 Source_Xn CPU
INTERRUPT_PRO_Xn_MAP_REG Num_P Source_Xn CPU Interrupt_Pb CPU Interrupt_Pb b
8.3.3.3 CPU Source_X
INTERRUPT_PRO_X_MAP_REG Num_Ib Num_I CPU (6a7a11a15a16a29) b
8.3.4 CPU NMI
Interrupt Reg INTERRUPT_PRO_NMI_MASK_HW CPU 14 NMI b INTERRUPT_PRO_NMI_MASK_HW CPU NMI CPU NMI b 8.2-1 b
231
ESP32-S2 TRM ( 1.3)
8
GoBack
8.3.5
INTERRUPT_PRO_INTR_STATUS_REG_nc Bit b INTERRUPT_PRO_INTR_STATUS_REG_n 8.3-1 b
8.4
8.4-1 b 3 b 8.4-1.
PeriBUS1
0x3F4C2000
8.5
cb 8.4 b
232
ESP32-S2 TRM ( 1.3)
233
ESP32-S2 TRM ( 1.3)
INTERRUPT_PRO_PWR_INTR_MAP_REG INTERRUPT_PRO_UHCI0_INTR_MAP_REG INTERRUPT_PRO_TG_T0_LEVEL_INT_MAP_REG INTERRUPT_PRO_TG_T1_LEVEL_INT_MAP_REG INTERRUPT_PRO_TG_WDT_LEVEL_INT_MAP_REG INTERRUPT_PRO_TG_LACT_LEVEL_INT_MAP_REG INTERRUPT_PRO_TG1_T0_LEVEL_INT_MAP_REG INTERRUPT_PRO_TG1_T1_LEVEL_INT_MAP_REG INTERRUPT_PRO_TG1_WDT_LEVEL_INT_MAP_REG INTERRUPT_PRO_TG1_LACT_LEVEL_INT_MAP_REG INTERRUPT_PRO_GPIO_INTERRUPT_PRO_MAP_REG INTERRUPT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_REG INTERRUPT_PRO_DEDICATED_GPIO_IN_INTR_MAP_REG INTERRUPT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG INTERRUPT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG INTERRUPT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG INTERRUPT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG INTERRUPT_PRO_SPI_INTR_1_MAP_REG INTERRUPT_PRO_SPI_INTR_2_MAP_REG INTERRUPT_PRO_SPI_INTR_3_MAP_REG INTERRUPT_PRO_I2S0_INT_MAP_REG INTERRUPT_PRO_UART_INTR_MAP_REG INTERRUPT_PRO_UART1_INTR_MAP_REG INTERRUPT_PRO_LEDC_INT_MAP_REG INTERRUPT_PRO_EFUSE_INT_MAP_REG INTERRUPT_PRO_CAN_INT_MAP_REG INTERRUPT_PRO_USB_INTR_MAP_REG INTERRUPT_PRO_RTC_CORE_INTR_MAP_REG
PWR_INTR UHCI0_INTR TG_T0_LEVEL_INT TG_T1_LEVEL_INT TG_WDT_LEVEL_INT TG_LACT_LEVEL_INT TG1_T0_LEVEL_INT TG1_T1_LEVEL_INT TG1_WDT_LEVEL_INT TG1_LACT_LEVEL_INT GPIO_INTERRUPT_PRO GPIO_INTERRUPT_PRO_NMI DEDICATED_GPIO_IN_INTR CPU_INTR_FROM_CPU_0 CPU_INTR_FROM_CPU_1 CPU_INTR_FROM_CPU_2 CPU_INTR_FROM_CPU_3 SPI_INTR_1 SPI_INTR_2 SPI_INTR_3 I2S0_INT UART_INTR UART1_INTR LEDC_INT EFUSE_INT CAN_INT USB_INTR RTC_CORE_INTR
0x0008 0x0034 0x003C 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 0x0058 0x005C 0x0060 0x006C 0x0070 0x0074 0x0078 0x007C 0x0080 0x0084 0x0088 0x008C 0x0094 0x0098 0x00B4 0x00B8 0x00BC 0x00C0 0x00C4
/ / / / / / / / / / / / / / / / / / / / / / / / / / / /
GoBack
8
234
ESP32-S2 TRM ( 1.3)
INTERRUPT_PRO_RMT_INTR_MAP_REG INTERRUPT_PRO_PCNT_INTR_MAP_REG INTERRUPT_PRO_I2C_EXT0_INTR_MAP_REG INTERRUPT_PRO_I2C_EXT1_INTR_MAP_REG INTERRUPT_PRO_RSA_INTR_MAP_REG INTERRUPT_PRO_SHA_INTR_MAP_REG INTERRUPT_PRO_AES_INTR_MAP_REG INTERRUPT_PRO_SPI2_DMA_INT_MAP_REG INTERRUPT_PRO_SPI3_DMA_INT_MAP_REG INTERRUPT_PRO_TIMER_INT1_MAP_REG INTERRUPT_PRO_TIMER_INT2_MAP_REG INTERRUPT_PRO_TG_T0_EDGE_INT_MAP_REG INTERRUPT_PRO_TG_T1_EDGE_INT_MAP_REG INTERRUPT_PRO_TG_WDT_EDGE_INT_MAP_REG INTERRUPT_PRO_TG_LACT_EDGE_INT_MAP_REG INTERRUPT_PRO_TG1_T0_EDGE_INT_MAP_REG INTERRUPT_PRO_TG1_T1_EDGE_INT_MAP_REG INTERRUPT_PRO_TG1_WDT_EDGE_INT_MAP_REG INTERRUPT_PRO_TG1_LACT_EDGE_INT_MAP_REG INTERRUPT_PRO_CACHE_IA_INT_MAP_REG INTERRUPT_PRO_SYSTIMER_TARGET0_INT_MAP_REG INTERRUPT_PRO_SYSTIMER_TARGET1_INT_MAP_REG INTERRUPT_PRO_SYSTIMER_TARGET2_INT_MAP_REG INTERRUPT_PRO_ASSIST_DEBUG_INTR_MAP_REG INTERRUPT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_REG INTERRUPT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_REG INTERRUPT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_REG INTERRUPT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_REG INTERRUPT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_REG
RMT_INTR PCNT_INTR I2C_EXT0_INTR I2C_EXT1_INTR RSA_INTR SHA_INTR AES_INTR SPI2_DMA_INT SPI3_DMA_INT TIMER_INT1 TIMER_INT2 TG_T0_EDGE_INT TG_T1_EDGE_INT TG_WDT_EDGE_INT TG_LACT_EDGE_INT TG1_T0_EDGE_INT TG1_T1_EDGE_INT TG1_WDT_EDGE_INT TG1_LACT_EDGE_INT CACHE_IA_INT SYSTIMER_TARGET0_INT SYSTIMER_TARGET1 SYSTIMER_TARGET2 ASSIST_DEBUG_INTR PMS_PRO_IRAM0_ILG_INTR PMS_PRO_DRAM0_ILG_INTR PMS_PRO_DPORT_ILG_INTR PMS_PRO_AHB_ILG_INTR PMS_PRO_CACHE_ILG_INTR
0x00C8 0x00CC 0x00D0 0x00D4 0x00D8 0x00DC 0x00E0 0x00E4 0x00E8 0x00F0 0x00F4 0x00F8 0x00FC 0x0100 0x0104 0x0108 0x010C 0x0110 0x0114 0x0118 0x011C 0x0120 0x0124 0x0128 0x012C 0x0130 0x0134 0x0138 0x013C
/ / / / / / / / / / / / / / / / / / / / / / / / / / / / /
GoBack
8
235
ESP32-S2 TRM ( 1.3)
INTERRUPT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_REG INTERRUPT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_REG INTERRUPT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_REG INTERRUPT_PRO_SPI_MEM_REJECT_INTR_MAP_REG INTERRUPT_PRO_DMA_COPY_INTR_MAP_REG INTERRUPT_PRO_DCACHE_PRELOAD_INT_MAP_REG INTERRUPT_PRO_ICACHE_PRELOAD_INT_MAP_REG INTERRUPT_PRO_APB_ADC_INT_MAP_REG INTERRUPT_PRO_CRYPTO_DMA_INT_MAP_REG INTERRUPT_PRO_CPU_PERI_ERROR_INT_MAP_REG INTERRUPT_PRO_APB_PERI_ERROR_INT_MAP_REG INTERRUPT_PRO_DCACHE_SYNC_INT_MAP_REG INTERRUPT_PRO_ICACHE_SYNC_INT_MAP_REG INTERRUPT_CLOCK_GATE_REG INTERRUPT_PRO_INTR_STATUS_REG_0_REG INTERRUPT_PRO_INTR_STATUS_REG_1_REG INTERRUPT_PRO_INTR_STATUS_REG_2_REG INTERRUPT_DATE_REG
PMS_DMA_APB_I_ILG_INTR PMS_DMA_RX_I_ILG_INTR PMS_DMA_TX_I_ILG_INTR SPI_MEM_REJECT_INTR DMA_COPY_INTR DCACHE_PRELOAD_INT ICACHE_PRELOAD_INT APB_ADC_INT CRYPTO_DMA_INT cpu peri error CPU_PERI_ERROR_INT DCACHE_SYNC_INT ICACHE_SYNC_INT NMI
0 1 2
0x0140 0x0144 0x0148 0x014C 0x0150 0x015C 0x0160 0x0164 0x0168 0x016C 0x0170 0x0174 0x0178 0x0188
/ / / / / / / / / / / / / /
0x017C 0x0180 0x0184
0x0FFC /
GoBack
8
8
GoBack
8.6
cb 8.4 b
Register 8.1. INTERRUPT_PRO_PWR_INTR_MAP_REG (0x0008)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_PWR_INTR_MAP
0
16
Reset
INTERRUPT_PRO_PWR_INTR_MAP PWR_INTR CPU bc/
Register 8.2. INTERRUPT_PRO_UHCI0_INTR_MAP_REG (0x0034)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_UHCI0_INTR_MAP
0
16
Reset
INTERRUPT_PRO_UHCI0_INTR_MAP UHCI0_INTR CPU bc/
236
ESP32-S2 TRM ( 1.3)
8
GoBack
Register 8.3. INTERRUPT_PRO_TG_T0_LEVEL_INT_MAP_REG (0x003C)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_TG_T0_LEVEL_INT_MAP
0
16
Reset
INTERRUPT_PRO_TG_T0_LEVEL_INT_MAP TG_T0_LEVEL_INT CPU bc/
Register 8.4. INTERRUPT_PRO_TG_T1_LEVEL_INT_MAP_REG (0x0040)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_TG_T1_LEVEL_INT_MAP
0
16
Reset
INTERRUPT_PRO_TG_T1_LEVEL_INT_MAP TG_T1_LEVEL_INT CPU bc/
237
ESP32-S2 TRM ( 1.3)
8
GoBack
Register 8.5. INTERRUPT_PRO_TG_WDT_LEVEL_INT_MAP_REG (0x0044)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_TG_WDT_LEVEL_INT_MAP
0
16
Reset
INTERRUPT_PRO_TG_WDT_LEVEL_INT_MAP TG_WDT_LEVEL_INT CPU bc/
Register 8.6. INTERRUPT_PRO_TG_LACT_LEVEL_INT_MAP_REG (0x0048)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_TG_LACT_LEVEL_INT_MAP
0
16
Reset
INTERRUPT_PRO_TG_LACT_LEVEL_INT_MAP TG_LACT_LEVEL_INT CPU bc/
238
ESP32-S2 TRM ( 1.3)
8
GoBack
Register 8.7. INTERRUPT_PRO_TG1_T0_LEVEL_INT_MAP_REG (0x004C)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_TG1_T0_LEVEL_INT_MAP
0
16
Reset
INTERRUPT_PRO_TG1_T0_LEVEL_INT_MAP TG1_T0_LEVEL_INT CPU bc/
Register 8.8. INTERRUPT_PRO_TG1_T1_LEVEL_INT_MAP_REG (0x0050)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_TG1_T1_LEVEL_INT_MAP
0
16
Reset
INTERRUPT_PRO_TG1_T1_LEVEL_INT_MAP TG1_T1_LEVEL_INT CPU bc/
239
ESP32-S2 TRM ( 1.3)
8
GoBack
Register 8.9. INTERRUPT_PRO_TG1_WDT_LEVEL_INT_MAP_REG (0x0054)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_TG1_WDT_LEVEL_INT_MAP
0
16
Reset
INTERRUPT_PRO_TG1_WDT_LEVEL_INT_MAP TG1_WDT_LEVEL_INT CPU bc/
Register 8.10. INTERRUPT_PRO_TG1_LACT_LEVEL_INT_MAP_REG (0x0058)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_TG1_LACT_LEVEL_INT_MAP
0
16
Reset
INTERRUPT_PRO_TG1_LACT_LEVEL_INT_MAP TG1_LACT_LEVEL_INT CPU bc/
240
ESP32-S2 TRM ( 1.3)
8
GoBack
Register 8.11. INTERRUPT_PRO_GPIO_INTERRUPT_PRO_MAP_REG (0x005C)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_GPIO_INTERRUPT_PRO_MAP
0
16
Reset
INTERRUPT_PRO_GPIO_INTERRUPT_PRO_MAP GPIO_INTERRUPT_PRO CPU bc/
Register 8.12. INTERRUPT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_REG (0x0060)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP 0
16
Reset
INTERRUPT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP GPIO_INTERRUPT_PRO_NMI CPU bc/
Register 8.13. INTERRUPT_PRO_DEDICATED_GPIO_IN_INTR_MAP_REG (0x006C)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_DEDICATED_GPIO_IN_INTR_MAP
0
16
Reset
INTERRUPT_PRO_DEDICATED_GPIO_IN_INTR_MAP DEDICATED_GPIO_IN_INTR CPU bc/
241
ESP32-S2 TRM ( 1.3)
8
GoBack
Register 8.14. INTERRUPT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG (0x0070)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_CPU_INTR_FROM_CPU_0_MAP
0
16
Reset
INTERRUPT_PRO_CPU_INTR_FROM_CPU_0_MAP CPU_INTR_FROM_CPU_0 CPU bc/
Register 8.15. INTERRUPT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG (0x0074)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_CPU_INTR_FROM_CPU_1_MAP 0
16
Reset
INTERRUPT_PRO_CPU_INTR_FROM_CPU_1_MAP CPU_INTR_FROM_CPU_1 CPU bc/
Register 8.16. INTERRUPT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG (0x0078)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_CPU_INTR_FROM_CPU_2_MAP 0
16
Reset
INTERRUPT_PRO_CPU_INTR_FROM_CPU_2_MAP CPU_INTR_FROM_CPU_2 CPU bc/
242
ESP32-S2 TRM ( 1.3)
8
GoBack
Register 8.17. INTERRUPT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG (0x007C)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_CPU_INTR_FROM_CPU_3_MAP 0
16
Reset
INTERRUPT_PRO_CPU_INTR_FROM_CPU_3_MAP CPU_INTR_FROM_CPU_3 CPU bc/
Register 8.18. INTERRUPT_PRO_SPI_INTR_1_MAP_REG (0x0080)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_SPI_INTR_1_MAP
0
16
Reset
INTERRUPT_PRO_SPI_INTR_1_MAP SPI_INTR_1 CPU bc/
Register 8.19. INTERRUPT_PRO_SPI_INTR_2_MAP_REG (0x0084)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_SPI_INTR_2_MAP
0
16
Reset
INTERRUPT_PRO_SPI_INTR_2_MAP SPI_INTR_2 CPU bc/
243
ESP32-S2 TRM ( 1.3)
8
GoBack
Register 8.20. INTERRUPT_PRO_SPI_INTR_3_MAP_REG (0x0088)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_SPI_INTR_3_MAP
0
16
Reset
INTERRUPT_PRO_SPI_INTR_3_MAP SPI_INTR_3 CPU bc/
Register 8.21. INTERRUPT_PRO_I2S0_INT_MAP_REG (0x008C)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_I2S0_INT_MAP
0
16
Reset
INTERRUPT_PRO_I2S0_INT_MAP I2S0_INT CPU bc/
Register 8.22. INTERRUPT_PRO_UART_INTR_MAP_REG (0x0094)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_UART_INTR_MAP
0
16
Reset
INTERRUPT_PRO_UART_INTR_MAP UART_INTR CPU bc/
244
ESP32-S2 TRM ( 1.3)
8
GoBack
Register 8.23. INTERRUPT_PRO_UART1_INTR_MAP_REG (0x0098)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_UART1_INTR_MAP
0
16
Reset
INTERRUPT_PRO_UART1_INTR_MAP UART1_INTR CPU bc/
Register 8.24. INTERRUPT_PRO_LEDC_INT_MAP_REG (0x00B4)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_LEDC_INT_MAP
0
16
Reset
INTERRUPT_PRO_LEDC_INT_MAP LEDC_INT CPU bc/
Register 8.25. INTERRUPT_PRO_EFUSE_INT_MAP_REG (0x00B8)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_EFUSE_INT_MAP
0
16
Reset
INTERRUPT_PRO_EFUSE_INT_MAP EFUSE_INT CPU bc/
245
ESP32-S2 TRM ( 1.3)
8
GoBack
Register 8.26. INTERRUPT_PRO_CAN_INT_MAP_REG (0x00BC)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_CAN_INT_MAP
0
16
Reset
INTERRUPT_PRO_CAN_INT_MAP CAN_INT CPU bc/
Register 8.27. INTERRUPT_PRO_USB_INTR_MAP_REG (0x00C0)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_USB_INTR_MAP
0
16
Reset
INTERRUPT_PRO_USB_INTR_MAP USB_INTR CPU bc/
Register 8.28. INTERRUPT_PRO_RTC_CORE_INTR_MAP_REG (0x00C4)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_RTC_CORE_INTR_MAP
0
16
Reset
INTERRUPT_PRO_RTC_CORE_INTR_MAP RTC_CORE_INTR CPU bc/
246
ESP32-S2 TRM ( 1.3)
8
GoBack
Register 8.29. INTERRUPT_PRO_RMT_INTR_MAP_REG (0x00C8)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_RMT_INTR_MAP
0
16
Reset
INTERRUPT_PRO_RMT_INTR_MAP RMT_INTR CPU bc/
Register 8.30. INTERRUPT_PRO_PCNT_INTR_MAP_REG (0x00CC)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_PCNT_INTR_MAP
0
16
Reset
INTERRUPT_PRO_PCNT_INTR_MAP PCNT_INTR CPU bc/
Register 8.31. INTERRUPT_PRO_I2C_EXT0_INTR_MAP_REG (0x00D0)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_I2C_EXT0_INTR_MAP
0
16
Reset
INTERRUPT_PRO_I2C_EXT0_INTR_MAP I2C_EXT0_INTR CPU bc/
247
ESP32-S2 TRM ( 1.3)
8
GoBack
Register 8.32. INTERRUPT_PRO_I2C_EXT1_INTR_MAP_REG (0x00D4)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_I2C_EXT1_INTR_MAP
0
16
Reset
INTERRUPT_PRO_I2C_EXT1_INTR_MAP I2C_EXT1_INTR CPU bc/
Register 8.33. INTERRUPT_PRO_RSA_INTR_MAP_REG (0x00D8)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_RSA_INTR_MAP
0
16
Reset
INTERRUPT_PRO_RSA_INTR_MAP RSA_INTR CPU bc/
Register 8.34. INTERRUPT_PRO_SHA_INTR_MAP_REG (0x00DC)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_SHA_INTR_MAP
0
16
Reset
INTERRUPT_PRO_SHA_INTR_MAP SHA_INTR CPU bc/
248
ESP32-S2 TRM ( 1.3)
8
GoBack
Register 8.35. INTERRUPT_PRO_AES_INTR_MAP_REG (0x00E0)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_AES_INTR_MAP
0
16
Reset
INTERRUPT_PRO_AES_INTR_MAP AES_INTR CPU bc/
Register 8.36. INTERRUPT_PRO_SPI2_DMA_INT_MAP_REG (0x00E4)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_SPI2_DMA_INT_MAP
0
16
Reset
INTERRUPT_PRO_SPI2_DMA_INT_MAP SPI2_DMA_INT CPU bc/
Register 8.37. INTERRUPT_PRO_SPI3_DMA_INT_MAP_REG (0x00E8)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_SPI3_DMA_INT_MAP
0
16
Reset
INTERRUPT_PRO_SPI3_DMA_INT_MAP SPI3_DMA_INT CPU bc/
249
ESP32-S2 TRM ( 1.3)
8
GoBack
Register 8.38. INTERRUPT_PRO_TIMER_INT1_MAP_REG (0x00F0)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_TIMER_INT1_MAP
0
16
Reset
INTERRUPT_PRO_TIMER_INT1_MAP TIMER_INT1 CPU bc/
Register 8.39. INTERRUPT_PRO_TIMER_INT2_MAP_REG (0x00F4)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_TIMER_INT2_MAP
0
16
Reset
INTERRUPT_PRO_TIMER_INT2_MAP TIMER_INT2 CPU bc/
Register 8.40. INTERRUPT_PRO_TG_T0_EDGE_INT_MAP_REG (0x00F8)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_TG_T0_EDGE_INT_MAP
0
16
Reset
INTERRUPT_PRO_TG_T0_EDGE_INT_MAP TG_T0_EDGE_INT CPU bc/
250
ESP32-S2 TRM ( 1.3)
8
GoBack
Register 8.41. INTERRUPT_PRO_TG_T1_EDGE_INT_MAP_REG (0x00FC)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_TG_T1_EDGE_INT_MAP
0
16
Reset
INTERRUPT_PRO_TG_T1_EDGE_INT_MAP TG_T1_EDGE_INT CPU bc/
Register 8.42. INTERRUPT_PRO_TG_WDT_EDGE_INT_MAP_REG (0x0100)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_TG_WDT_EDGE_INT_MAP
0
16
Reset
INTERRUPT_PRO_TG_WDT_EDGE_INT_MAP TG_WDT_EDGE_INT CPU bc/
251
ESP32-S2 TRM ( 1.3)
8
GoBack
Register 8.43. INTERRUPT_PRO_TG_LACT_EDGE_INT_MAP_REG (0x0104)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_TG_LACT_EDGE_INT_MAP
0
16
Reset
INTERRUPT_PRO_TG_LACT_EDGE_INT_MAP TG_LACT_EDGE_INT CPU bc/
Register 8.44. INTERRUPT_PRO_TG1_T0_EDGE_INT_MAP_REG (0x0108)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_TG1_T0_EDGE_INT_MAP
0
16
Reset
INTERRUPT_PRO_TG1_T0_EDGE_INT_MAP TG1_T0_EDGE_INT CPU bc/
252
ESP32-S2 TRM ( 1.3)
8
GoBack
Register 8.45. INTERRUPT_PRO_TG1_T1_EDGE_INT_MAP_REG (0x010C)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_TG1_T1_EDGE_INT_MAP
0
16
Reset
INTERRUPT_PRO_TG1_T1_EDGE_INT_MAP TG1_T1_EDGE_INT CPU bc/
Register 8.46. INTERRUPT_PRO_TG1_WDT_EDGE_INT_MAP_REG (0x0110)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_TG1_WDT_EDGE_INT_MAP
0
16
Reset
INTERRUPT_PRO_TG1_WDT_EDGE_INT_MAP TG1_WDT_EDGE_INT CPU bc/
253
ESP32-S2 TRM ( 1.3)
8
GoBack
Register 8.47. INTERRUPT_PRO_TG1_LACT_EDGE_INT_MAP_REG (0x0114)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_TG1_LACT_EDGE_INT_MAP
0
16
Reset
INTERRUPT_PRO_TG1_LACT_EDGE_INT_MAP TG1_LACT_EDGE_INT CPU bc/
Register 8.48. INTERRUPT_PRO_CACHE_IA_INT_MAP_REG (0x0118)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_CACHE_IA_INT_MAP
0
16
Reset
INTERRUPT_PRO_CACHE_IA_INT_MAP CACHE_IA_INT CPU bc/
Register 8.49. INTERRUPT_PRO_SYSTIMER_TARGET0_INT_MAP_REG (0x011C)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_SYSTIMER_TARGET0_INT_MAP
0
16
Reset
INTERRUPT_PRO_SYSTIMER_TARGET0_INT_MAP SYSTIMER_TARGET0 CPU bc/
254
ESP32-S2 TRM ( 1.3)
8
GoBack
Register 8.50. INTERRUPT_PRO_SYSTIMER_TARGET1_INT_MAP_REG (0x0120)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_SYSTIMER_TARGET1_INT_MAP
0
16
Reset
INTERRUPT_PRO_SYSTIMER_TARGET1_INT_MAP SYSTIMER_TARGET1 CPU bc/
Register 8.51. INTERRUPT_PRO_SYSTIMER_TARGET2_INT_MAP_REG (0x0124)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_SYSTIMER_TARGET2_INT_MAP
0
16
Reset
INTERRUPT_PRO_SYSTIMER_TARGET2_INT_MAP SYSTIMER_TARGET2 CPU bc/
Register 8.52. INTERRUPT_PRO_ASSIST_DEBUG_INTR_MAP_REG (0x0128)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_ASSIST_DEBUG_INTR_MAP
0
16
Reset
INTERRUPT_PRO_ASSIST_DEBUG_INTR_MAP ASSIST_DEBUG_INTR CPU bc/
255
ESP32-S2 TRM ( 1.3)
8
GoBack
Register 8.53. INTERRUPT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_REG (0x012C)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP
0
16
Reset
INTERRUPT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP PMS_PRO_IRAM0_ILG_INTR CPU bc/
Register 8.54. INTERRUPT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_REG (0x0130)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP
0
16
Reset
INTERRUPT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP PMS_PRO_DRAM0_ILG_INTR CPU bc/
Register 8.55. INTERRUPT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_REG (0x0134)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP 0
16
Reset
INTERRUPT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP PMS_PRO_DPORT_ILG_INTR CPU bc/
256
ESP32-S2 TRM ( 1.3)
8
GoBack
Register 8.56. INTERRUPT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_REG (0x0138)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_PMS_PRO_AHB_ILG_INTR_MAP 0
16
Reset
INTERRUPT_PRO_PMS_PRO_AHB_ILG_INTR_MAP PMS_PRO_AHB_ILG_INTR CPU bc/
Register 8.57. INTERRUPT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_REG (0x013C)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP
0
16
Reset
INTERRUPT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP PMS_PRO_CACHE_ILG_INTR CPU bc/
Register 8.58. INTERRUPT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_REG (0x0140)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP
0
16
Reset
INTERRUPT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP PMS_DMA_APB_I_ILG_INTR CPU bc/
257
ESP32-S2 TRM ( 1.3)
8
GoBack
Register 8.59. INTERRUPT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_REG (0x0144)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP 0
16
Reset
INTERRUPT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP PMS_DMA_RX_I_ILG_INTR CPU bc/
Register 8.60. INTERRUPT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_REG (0x0148)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP 0
16
Reset
INTERRUPT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP PMS_DMA_TX_I_ILG_INTR CPU bc/
Register 8.61. INTERRUPT_PRO_SPI_MEM_REJECT_INTR_MAP_REG (0x014C)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_SPI_MEM_REJECT_INTR_MAP
0
16
Reset
INTERRUPT_PRO_SPI_MEM_REJECT_INTR_MAP SPI_MEM_REJECT_INTR CPU bc/
258
ESP32-S2 TRM ( 1.3)
8
GoBack
Register 8.62. INTERRUPT_PRO_DMA_COPY_INTR_MAP_REG (0x0150)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_DMA_COPY_INTR_MAP
0
16
Reset
INTERRUPT_PRO_DMA_COPY_INTR_MAP DMA_COPY_INTR CPU bc/
Register 8.63. INTERRUPT_PRO_DCACHE_PRELOAD_INT_MAP_REG (0x015C)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_DCACHE_PRELOAD_INT_MAP
0
16
Reset
INTERRUPT_PRO_DCACHE_PRELOAD_INT_MAP DCACHE_PRELOAD_INT CPU bc/
259
ESP32-S2 TRM ( 1.3)
8
GoBack
Register 8.64. INTERRUPT_PRO_ICACHE_PRELOAD_INT_MAP_REG (0x0160)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_ICACHE_PRELOAD_INT_MAP
0
16
Reset
INTERRUPT_PRO_ICACHE_PRELOAD_INT_MAP ICACHE_PRELOAD_INT CPU bc/
Register 8.65. INTERRUPT_PRO_APB_ADC_INT_MAP_REG (0x0164)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_APB_ADC_INT_MAP
0
16
Reset
INTERRUPT_PRO_APB_ADC_INT_MAP APB_ADC_INT CPU bc/
Register 8.66. INTERRUPT_PRO_CRYPTO_DMA_INT_MAP_REG (0x0168)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_CRYPTO_DMA_INT_MAP
0
16
Reset
INTERRUPT_PRO_CRYPTO_DMA_INT_MAP CRYPTO_DMA_INT CPU bc/
260
ESP32-S2 TRM ( 1.3)
8
GoBack
Register 8.67. INTERRUPT_PRO_CPU_PERI_ERROR_INT_MAP_REG (0x016C)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_CPU_PERI_ERROR_INT_MAP
0
16
Reset
INTERRUPT_PRO_CPU_PERI_ERROR_INT_MAP CPU_PERI_ERROR_INT CPU bc/
Register 8.68. INTERRUPT_PRO_APB_PERI_ERROR_INT_MAP_REG (0x0170)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_APB_PERI_ERROR_INT_MAP
0
16
Reset
INTERRUPT_PRO_APB_PERI_ERROR_INT_MAP APB_PERI_ERROR_INT CPU bc/
261
ESP32-S2 TRM ( 1.3)
8
GoBack
Register 8.69. INTERRUPT_PRO_DCACHE_SYNC_INT_MAP_REG (0x0174)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_DCACHE_SYNC_INT_MAP
0
16
Reset
INTERRUPT_PRO_DCACHE_SYNC_INT_MAP DCACHE_SYNC_INT CPU bc/
Register 8.70. INTERRUPT_PRO_ICACHE_SYNC_INT_MAP_REG (0x0178)
(reserved)
31
54
000000000000000000000000000
INTERRUPT_PRO_ICACHE_SYNC_INT_MAP
0
16
Reset
INTERRUPT_PRO_ICACHE_SYNC_INT_MAP ICACHE_SYNC_INT CPU bc/
Register 8.71. INTERRUPT_CLOCK_GATE_REG (0x0188)
(reserved)
INTERIRNUTEPRTR_UPRPOT__CNLMKI__EMNASK_HW
31
21 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset
INTERRUPT_CLK_EN b10bc/ INTERRUPT_PRO_NMI_MASK_HW NMI CPUbc/
262
ESP32-S2 TRM ( 1.3)
8
Register 8.72. INTERRUPT_PRO_INTR_STATUS_REG_0_REG (0x017C)
INTERRUPT_PRO_INTR_STATUS_0
31
0x000000
INTERRUPT_PRO_INTR_STATUS_0 32 bc
GoBack
0
Reset
Register 8.73. INTERRUPT_PRO_INTR_STATUS_REG_1_REG (0x0180)
INTERRUPT_PRO_INTR_STATUS_1
31
0x000000
INTERRUPT_PRO_INTR_STATUS_1 32 bc
0
Reset
Register 8.74. INTERRUPT_PRO_INTR_STATUS_REG_2_REG (0x0184)
INTERRUPT_PRO_INTR_STATUS_2
31
0x000000
INTERRUPT_PRO_INTR_STATUS_2 31 bc
0
Reset
263
ESP32-S2 TRM ( 1.3)
8
(reserved)
31
28 27
0000
Register 8.75. INTERRUPT_DATE_REG (0x0FFC)
INTERRUPT_DATE 0x1904180
INTERRUPT_DATE bc/
GoBack
0
Reset
264
ESP32-S2 TRM ( 1.3)
9
GoBack
9
9.1
ESP32-S2 abESP32-S2 5 bESP32-S2 2 b
9.2
ESP32-S2 · · 5 · 16 KB (retention memory) · 8 32 (retention register) · RTC Boot
ESP32-S2 RTC Boot b
9.3
ESP32-S2 · (PMU)aRTC · · b · RTC RTC ULP b 1 (ULP)b b 32 b
265
ESP32-S2 TRM ( 1.3)
9
GoBack
· 8 32 "always-on" 8 b
· 22 "always-on" 22 c 9.4.4 GPIO c 5 IO MUX GPIO b
· RTC 8 KB SRAM ULP b · RTC 8 KB SRAMb · b ESP32-S2 9.3-1b
266
ESP32-S2 TRM ( 1.3)
9
GoBack
9.3-1.
9.3.1
ESP32-S2 · RTC ab · RTC b · RTC b
267
ESP32-S2 TRM ( 1.3)
9
GoBack
· b
ESP32-S2 RTC RTC ab RTC b 9.3-2b
sleep EN GPIO reject
Sleep Controller
Clock Controller
Analog Power Controller
Digital Power Controller
Wi-Fi
Digital Core
Power Controller Power Controller
RTC Memory
ROM / RAM
Power Controller Power Controller
RTC Peripheral Power Controller
Protection Timer
main state wai t done main state
sleep accept main state main state
RTC Main State Machine
Touch done
wakeup
Coprocessor done
wakeup
CPU wakeup
ULP Timer
trig
ULP-
coprocessor
Touch
trig
Touch
Timer
Controller
wakeup
wakeup
Wakeup Controller
RTC GPIO wakeup MAC wakeup UART0 UART1 wakeup
wakeup EXT0 EXT 1 wakeup Digital GPIO wakeup
RTC Main Timer
9.3-2.
9.4.2 b
9.3.2
ESP32-S2 40 MHz PLL aRTC aRTC aRTC
268
ESP32-S2 TRM ( 1.3)
9 Wi-Fi b
RC_SLOW_CLK XTAL32K_CLK RC_FAST_DIV_CLK
RTC Slow Clock
Selection Signal
0
1
RTC_SLOW_CLK
2
PMU RTC Timer
RTC Clock
Selection Signal
XTAL_DIV_CLK
RC_FAST_CLK
div n
0
RTC_FAST_CLK
1
RTC Fast Clock
ULP Coprocessor Sensor Controller RTC Slow Memory
RTC Registers
9.3-3. RTC
Selection Signals
XTAL32K_CLK RC_FAST_CLK RTC_SLOW_CLK XTAL_CLK
LP_MUX
LOW_POWER_CLK
Wireless
Low-power Clock
9.3-4. RTC
GoBack
ESP32-S2
ESP32-S2
269
ESP32-S2 TRM ( 1.3)
9
RTC RTC
RC_SLOW_CLK 1 XTAL32K_CLK RC_FAST_DIV_CLK XTAL_DIV_CLK
RC_FAST_CLK 2
XTAL32K_CLK RC_FAST_CLK RTC_SLOW_CLK XTAL_CLK
9.3-1.
RTC_CNTL_ANA_CLK_RTC_SEL
RTC_CNTL_FAST_CLK_RTC_SEL
SYSTEM_LPCLK_SEL_XTAL32K SYSTEM_LPCLK_SEL_8M SYSTEM_LPCLK_RTC_SLOW SYSTEM_LPCLK_SEL_XTAL
GoBack
RTC RTC RTC (Wi-Fi)
1. RTC b 2. RTC b
6 b
9.3.3
ESP32-S2 · RTC · ULP ·
RTC b ULP 1 (ULP) 32 b RTC 48 RTC b 9.3-2b
9.3-2. RTC
RTC_CNTL_TIMER_XTL_OFF RTC_CNTL_TIMER_SYS_STALL RTC_CNTL_TIMER_SYS_RST RTC_CNTL_TIME_UPDATE
1.RTC 2. 40 MHz b CPU stall b SYS_TIMER b b RTC_CNTL_RTC_TIME_UPDATE b CPU cb
RTC b b
270
ESP32-S2 TRM ( 1.3)
9
GoBack
· 0 RTC b RTC_CNTL_TIME_HIGH0_REG RTC_CNTL_TIME_LOW0_REG
· 1 RTC b RTC_CNTL_TIME_HIGH1_REG RTC_CNTL_TIME_LOW1_REG
0 1c 1 0bRTC b RTC b RTC b 9.4.4 b
9.3.4
ESP32-S2 · · RTC · Flash RTC b
9.4.2 b
9.3.4.1
ESP32-S2 c 3.3 V 1.1 V 9.3-5b
dbias[2:0] VREF
ESP32-S2
VDD3P3_CPU VDD3P3_RTC_IO +
-
1.1V (0.85V - 1.2V)
Digital System
9.3-5.
271
ESP32-S2 TRM ( 1.3)
9
GoBack
1. XPD_DIG_REG == 1 1.1 V XPD_DIG_REG == 0 b
2. DIG_REG_DBIAS[2:0]
VDD_DIG = 0.90 + DBIAS × 0.05V 3. VDD3P3_CPU VDD3P3_RTC_IOb
9.3.4.2
ESP32-S2 c 3.3 V 1.1 V RTC Deep-sleep b 9.3-6b
dbias[2:0] VREF
ESP32-S2
+
-
1.1V
RTC
VDD3P3_RTC_IO
9.3-6.
1. CHIP_PU Deep-sleep b 2. RTC_DBIAS[2:0]
VDD_RTC = 0.90 + DBIAS × 0.05V 3. RTC VDD3P3_RTC_IOb
9.3.4.3 Flash
ESP32-S2 flash RTC c flash 3.3 V 1.8 V flash 9.3-7b
272
ESP32-S2 TRM ( 1.3)
9
GoBack
drefh, drefm, dre: VREF
tieh + -
ESP32-S2
VDD3P3_RTC_IO
VDD_SPI 1uF
Regulator Output
500pF
9.3-7. Flash
1. XPD_SDIO_VREG == 1 3.3 V 1.8 V XPD_SDIO_VREG == 0 b
2. SDIO_TIEH == 1 VDD_SDIO VDD3P3_RTC 3.3 V VDD3P3_RTC b SDIO_TIEH == 0 VREF 1.8 Vb
3. DREFH_SDIOaDREFM_SDIO DREFL_SDIO VREF b
4. 3.3 V 1.8 V VDD3P3_RTC_IOb Flash RTC eFuse b
· XPD_SDIO_VREG Active RTC_CNTL_SDIO_FORCE == 0VDD_SPI_FORCE(EFUSE) == 1 XPD_SDIO_VREG XPD_VDD_SPI_REG(EFUSE) sleep RTC_CNTL_SDIO_REG_PD_EN == 1 XPD_SDIO_VREG 0 RTC_CNTL_SDIO_FORCE == 1 XPD_SDIO_VREG RTC_CNTL_XPD_SDIO_REG b
· SDIO_TIEH RTC_CNTL_SDIO_FORCE == 0 VDD_SPI_FORCE(EFUSE) == 1 SDIO_TIEH = VDD_SDIO_TIEH(EFUSE) SDIO_TIEH = RTC_CNTL_SDIO_TIEHb
9.3.4.4
ESP32-S2 VDD3P3_RTC_IOVDD3P3_CPUVDDA1 VDDA2 c LNA PA ab bESP32-S2 9.3-8b
273
ESP32-S2 TRM ( 1.3)
9
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thres[2:0]
VDD3P3_RTC_IO VDD3P3_CPU VDDA1 VDDA2
VREF
ESP32-S2
+
- comp -
Brownout detected
9.3-8.
1. RTC_CNTL_RTC_BROWN_OUT_DET
2. I2C ULP_CAL_REG5[2:0] 9.3-3
9.3-3.
ULP_CAL_REG5[2:0] 0 1 2 3 4 5 6 7
VDDcV 2.67 3.30 3.19 2.98 2.84 2.67 2.56 2.44
3. RTC_CNTL_BROWN_OUT_RST_SEL b · 0 · 1
6 b
9.4
9.4.1
ESP32-S2 10 · RTC
274
ESP32-S2 TRM ( 1.3)
9
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RTC RTC RTC · Wi-Fi · 8 MHz 40 MHz PLL RF
9.4.2 RTC
ESP32-S2 (Active)a (Monitor) (Sleep) RTC 9.4-1b
Active
ULP done or touch done
Monitor
Sleep
ULP timer or touch timer
9.4-1. RTC
RTC (FPU) (FPD) b 9.4-1b
275
ESP32-S2 TRM ( 1.3)
9
9.4-1. RTC
RTC RTC
RTC
RTC
Wi-Fi
8 MHz
40 MHz
PLL
RF
RTC
Active Monitor
ON
ON
ON
ON
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
ON
ON
OFF
ON
OFF
-
-
Sleep ON OFF OFF OFF OFF OFF OFF OFF OFF -
1 2 3 4 5 6
-
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1. ESP32-S2 "always-on"c FPU FPDb 2. RTC 1 (ULP) 32 ca
SAR ADC b 3. RTC 8 KB SRAM ULP bCPU
PeriBUS2 0x50000000b 4. RTC 8 KB SRAMbCPU IRAM0/DRAM0 b 5. bESP32-S2 ROM SRAM
b ROM SRAMb 6. Wi-Fi Wi-Fi MAC BBcb
9.4.3
ESP32-S2 5 9.4-2b
9.4-2.
Power Modes
Active Modem-sleep Light-sleep Deep-sleep
PMU RTC RTC RTC Wi-Fi 8 MHz 40
PLL
MHz
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON ON
ON
ON
ON
ON
ON
ON
ON
ON OFF OFF OFF
ON
ON
ON
ON
OFF OFF OFF OFF OFF
ON
OFF OFF OFF OFF OFF OFF OFF OFF
RF
ON OFF OFF OFF OFF
276
ESP32-S2 TRM ( 1.3)
9
*
GoBack
ESP32-S2 Modem-sleep Active b CPU Modem-sleepaLight-sleepaDeep-sleep b Active 1a2ab 3 b aab
1. 9.4-2b 2. uESP32-S2 vb 3. 9.4.4 b
9.4.4
ESP32-S2 CPU b RTC_CNTL_RTC_WAKEUP_ENA 9.4-3b
9.4-3.
WAKEUP_ENA 0x1 0x2 0x4 0x8
0x20 0x40 0x80 0x100 0x800 0x1000 0x2000 0x8000
11 EXT0 EXT1 GPIO RTC Wi-Fi UART0 UART1 TOUCH ULP-FSM XTAL_32K ULP-RISCV Trap USB
Light-sleep Y Y Y Y Y Y Y Y Y Y Y Y
Deep-sleep Y Y Y Y Y Y Y Y -
Hibernation Y Y Y -
* 1 2 3 4 5 5 6 7 8 9
10
1. EXT0 Light-sleep/Deep-sleep b RTC_CNTL_EXT_WAKEUP0_LV 1 b RTCIO_EXT_WAKEUP0_SEL RTC b
2. EXT1 b RTC_CNTL_EXT_WAKEUP1_SEL[17:0]b RTC_CNTL_EXT_WAKEUP1_LV == 1 RTC_CNTL_EXT_WAKEUP1_LV == 0 b EXT1 hold RTC_SLOW_CLK RTC_CNTL_EXT_WAKEUP1_STATUS b
277
ESP32-S2 TRM ( 1.3)
9
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3. Deep-sleep RTC GPIO b 4. Wi-Fi ActiveaModem-sleep Light-sleep CPU RF
Wi-Fi b 5. RX b 6. b 7. RTC_CNTL_RTC_SW_CPU_INTb 8. 32 kHz RTC 32 kHz b 9. cb 10. USB USB RESUMING b 11. UART b
9.4.5
ESP32-S2 CPU b ESP32-S2 9.4-3cUART b b
· RTC_CNTL_RTC_SLEEP_REJECT_ENA RTC_CNTL_LIGHT_SLP_REJECT_EN Light_sleep RTC_CNTL_DEEP_SLP_REJECT_EN Deep_sleep
· RTC_CNTL_SLP_REJECT_CAUSE_REG b
9.5 RTC Boot
Deep-sleep ROM RAM ROM SPI c flash b Light-sleep Modem-sleep Deep-sleep b Deep-sleep RTC b c 8 KB "deep sleep wake stub" RTC ROM SPI b RTC
1. RTC_CNTL_PROCPU_STAT_VECTOR_SEL 0b
2. b
3. CPU 0x50000000 0x40000400 ROM SPI bRTC C b
RTC
1. RTC_CNTL_PROCPU_STAT_VECTOR_SEL 1b
2. RTC CRC RTC_CNTL_STORE6_REG[31:0] b
278
ESP32-S2 TRM ( 1.3)
9
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3. RTC_CNTL_STORE7_REG[31:0] RTC b 4. b 5. CPU ROM b RTC CRC b
RTC_CNTL_STORE6_REG[31:0] CPU RTC b ESP32-S2 RTC 9.5-1
Power up
1
Running in ROM
reset_vector@ 0x40000400
Static Vector Sel
0
reset_vector@ 0x50000000
Initialization
Cal CRC in fast RTC mem
Yes
CRC right
No
Run code in RTC mem
Running in RTC memory
Jump to entry point in
RTC fast mem
Running in RTC fast mem
SPI Boot
Run code in CPU RAM Running in CPU RAM
9.5-1. ESP32-S2
ESP32-S2 40 MHz PLL b
9.6
ESP32-S2 9.6-1 b 3 b
279
ESP32-S2 TRM ( 1.3)
9
9.6-1.
PeriBUS1 PeriBUS2
0x3f408000 0x60008000
GoBack
9.7
cb 9.6 b
RTC RTC_CNTL_OPTIONS0_REG
RTC_CNTL_OPTION1_REG RTC RTC_CNTL_SLP_TIMER0_REG RTC_CNTL_SLP_TIMER1_REG RTC_CNTL_TIME_UPDATE_REG RTC_CNTL_TIME_LOW0_REG RTC_CNTL_TIME_HIGH0_REG RTC_CNTL_STATE0_REG RTC_CNTL_TIMER1_REG RTC_CNTL_TIMER2_REG RTC_CNTL_TIMER5_REG RTC_CNTL_TIME_LOW1_REG RTC_CNTL_TIME_HIGH1_REG RTC_CNTL_ANA_CONF_REG RTC_CNTL_REG RTC_CNTL_PWC_REG RTC_CNTL_DIG_PWC_REG RTC_CNTL_DIG_ISO_REG RTC_CNTL_LOW_POWER_ST_REG RTC_CNTL_RESET_STATE_REG RTC_CNTL_WAKEUP_STATE_REG RTC_CNTL_EXT_WAKEUP_CONF_REG RTC_CNTL_SLP_REJECT_CONF_REG RTC_CNTL_EXT_WAKEUP1_REG RTC_CNTL_EXT_WAKEUP1_STATUS_REG
PLL RTC
0x0000 0x0128
/
RTC 0 RTC 1 RTC RTC 0 32 RTC 0 16 sleep / reject / wakeup CPU stall RTC RTC 1 32 RTC 1 16
0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x002C 0x00E8 0x00EC
/ / / /
I2C PLLA RTC ISO RTC
0x0034 0x0084 0x0088 0x008C 0x0090 0x00CC
/ / / /
CPU
0x0038
GPIO / EXT1 EXT1
0x003C 0x0064 0x0068 0x00DC 0x00E0
/ / /
280
ESP32-S2 TRM ( 1.3)
9
RTC_CNTL_SLP_REJECT_CAUSE_REG RTC_CNTL_SLP_WAKEUP_CAUSE_REG RTC_CNTL_INT_ENA_RTC_REG RTC_CNTL_INT_RAW_RTC_REG RTC_CNTL_INT_ST_RTC_REG RTC_CNTL_INT_CLR_RTC_REG RTC_CNTL_STORE0_REG RTC_CNTL_STORE1_REG RTC_CNTL_STORE2_REG RTC_CNTL_STORE3_REG RTC_CNTL_STORE4_REG RTC_CNTL_STORE5_REG RTC_CNTL_STORE6_REG RTC_CNTL_STORE7_REG RTC_CNTL_EXT_XTL_CONF_REG RTC_CNTL_CLK_CONF_REG RTC_CNTL_SLOW_CLK_CONF_REG RTC_CNTL_XTAL32K_CLK_FACTOR_REG RTC_CNTL_XTAL32K_CONF_REG RTC RTC_CNTL_WDTCONFIG0_REG RTC_CNTL_WDTCONFIG1_REG RTC_CNTL_WDTCONFIG2_REG RTC_CNTL_WDTCONFIG3_REG RTC_CNTL_WDTCONFIG4_REG RTC_CNTL_WDTFEED_REG RTC_CNTL_WDTWPROTECT_REG RTC_CNTL_SWD_CONF_REG RTC_CNTL_SWD_WPROTECT_REG RTC_CNTL_SW_CPU_STALL_REG RTC_CNTL_PAD_HOLD_REG RTC_CNTL_DIG_PAD_HOLD_REG RTC_CNTL_BROWN_OUT_REG
RTC RTC RTC RTC
0 1 2 3 4 5 6 7
32 kHz RTC RTC 32 kHz 32 kHz
RTC 1 RTC 2 RTC 3 RTC 4 RTC RTC RTC
CPU stall RTC GPIO GPIO
GoBack
0x0124 0x012C
0x0040 0x0044 0x0048 0x004C
/
0x0050 0x0054 0x0058 0x005C 0x00BC 0x00C0 0x00C4 0x00C8
/ / / / / / / /
0x0060 0x0074 0x0078 0x00F0 0x00F4
/ / / /
0x0094 0x0098 0x009C 0x00A0 0x00A4 0x00A8 0x00AC 0x00B0 0x00B4
/ / / / / / /
0x00B8 0x00D4 0x00D8 0x00E4
/ / /
281
ESP32-S2 TRM ( 1.3)
9
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9.8
cb 9.6 b
Register 9.1. RTC_CNTL_OPTIONS0_REG (0x0000)
RTC_CRNTCT_L_CRSNTWCT_L__CSDNYGST_L_W_RDSRTGA_PW_FROAPRC_FEO_NRCOER_SRTST
31 30 29 28
(reserved)
RTC_CRNTCT_L_CRXNTTCTL_L__CRFXNTOTCTRL_LC__CRFEBNTO_CBTPRP_LUC_CLRELBNT__CBTPFP_LOD_CLRRLBNTC_CBTFEP_LO__CLRPRLBNTCU_CBTIEP_L2__CLCRPLBNT_D_CBTFI__OL2_CIC(R2rBNeC_CBsTFE_e_OL_Fr_IPROv2SeCUCRWdREC_)T__FECPPO__DRPRCOUCNCETP_LUP_(D_rSeRWsSe_TrSvTeAdL)L_PROCPU_C0
14 13 12 11 10 9 8 7 6 5 4 3
21
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_CNTL_SW_STALL_PROCPU_C0 RTC_CNTL_SW_STALL_PROCPU_C1 0x21 0x2 CPU stall b
RTC_CNTL_SW_PROCPU_RST 1 CPUbc RTC_CNTL_BB_I2C_FORCE_PD 1 BB_I2Cbc/ RTC_CNTL_BB_I2C_FORCE_PU 1 BB_I2Cbc/ RTC_CNTL_BBPLL_I2C_FORCE_PD 1 BB_PLL_I2Cbc/ RTC_CNTL_BBPLL_I2C_FORCE_PU 1 BB_PLL_I2Cbc/ RTC_CNTL_BBPLL_FORCE_PD 1 BB_PLLbc/ RTC_CNTL_BBPLL_FORCE_PU 1 BB_PLLbc/ RTC_CNTL_XTL_FORCE_PD 1 bc/ RTC_CNTL_XTL_FORCE_PU 1 bc/ RTC_CNTL_DG_WRAP_FORCE_RST 1 deep sleep bc/ RTC_CNTL_DG_WRAP_FORCE_NORST 1 deep sleep bc/ RTC_CNTL_SW_SYS_RST 1 bc
282
ESP32-S2 TRM ( 1.3)
9
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Register 9.2. RTC_CNTL_OPTION1_REG (0x0128)
(reserved)
RTC_CNTL_FORCE_DOWNLOAD_BOOT
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_CNTL_FORCE_DOWNLOAD_BOOT 1 bc/
Register 9.3. RTC_CNTL_SLP_TIMER0_REG (0x0004)
RTC_CNTL_SLP_VAL_LO
31
0x000000
RTC_CNTL_SLP_VAL_LO RTC 32 bc/
0
Reset
Register 9.4. RTC_CNTL_SLP_TIMER1_REG (0x0008)
(reserved)
RTC_CNTL_RTC_MAIN_TIMER_ALARM_EN
RTC_CNTL_SLP_VAL_HI
31
17 16 15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 00
0x00
RTC_CNTL_SLP_VAL_HI RTC 16 bc/ RTC_CNTL_RTC_MAIN_TIMER_ALARM_EN 1 bc
0
Reset
283
ESP32-S2 TRM ( 1.3)
9
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Register 9.5. RTC_CNTL_TIME_UPDATE_REG (0x000C)
RTC_C(rNesTeLr_RvRTeTCdC_) _CRTNTIMCT_LE_CR_TNTUICMTP_LDE_CARTNT_IMETSLYE_SRT__IMRXSTETLR__OSFYFS_STALL
(reserved)
31 30 29 28 27 26
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_CNTL_TIMER_SYS_STALL RTC bc/ RTC_CNTL_TIMER_XTL_OFF RTC bc/ RTC_CNTL_TIMER_SYS_RST RTC bc/ RTC_CNTL_RTC_TIME_UPDATE RTC bc
9.3-2b
Register 9.6. RTC_CNTL_TIME_LOW0_REG (0x0010)
RTC_CNTL_RTC_TIMER_VALUE0_LOW
31
0x000000
RTC_CNTL_RTC_TIMER_VALUE0_LOW RTC 0 32 bc
0
Reset
284
ESP32-S2 TRM ( 1.3)
9
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Register 9.7. RTC_CNTL_TIME_HIGH0_REG (0x0014)
(reserved)
31
16 15
0000000000000000
RTC_CNTL_RTC_TIMER_VALUE0_HIGH
0
0x00
Reset
RTC_CNTL_RTC_TIMER_VALUE0_HIGH RTC 0 16 bc
Register 9.8. RTC_CNTL_STATE0_REG (0x0018)
RTC_CNTRLT_CS_LCENETPRL_T_ECSN_LCPN_TR(LrEe_JsSEeLCrPvTe_dW)AKEUP 31 30 29 28 27
(reserved)
RTC_CNTRLT_CR_TCCN_TSLL_PR_TRCE_JSEWCT__CCPAUU_SINE_TCLR 21 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_CNTL_RTC_SW_CPU_INT RTC CPUbc RTC_CNTL_RTC_SLP_REJECT_CAUSE_CLR RTC bc RTC_CNTL_SLP_WAKEUP bc/ RTC_CNTL_SLP_REJECT bc/ RTC_CNTL_SLEEP_EN bc/
285
ESP32-S2 TRM ( 1.3)
9
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Register 9.9. RTC_CNTL_TIMER1_REG (0x001C)
RTC_CNTL_PLL_BUF_WAIT
31
24 23
40
RTC_CNTL_XTL_BUF_WAIT
14 13
80
RTC_CNTL_CK8M_WAIT
65
0x10
RTC_CNTL_CPU_RSTTCA_LCLN_TWLA_ITCPU_STALL_EN
10
1
1 Reset
RTC_CNTL_CPU_STALL_EN CPU stallbc/ RTC_CNTL_CPU_STALL_WAIT CPU stall c RTC bc/ RTC_CNTL_CK8M_WAIT 8 MHz c RTC bc/ RTC_CNTL_XTL_BUF_WAIT XTAL c RTC bc/ RTC_CNTL_PLL_BUF_WAIT PLL c RTC bc/
Register 9.10. RTC_CNTL_TIMER2_REG (0x0020)
RTC_CNTL_MIN_TIME_CK8M_OFF
RTC_CNTL_ULPCP_TOUCH_START_WAIT
(reserved)
31
24 23
15 14
0
0x1
0x10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_CNTL_ULPCP_TOUCH_START_WAIT c RTC bc/
RTC_CNTL_MIN_TIME_CK8M_OFF 8 MHz c RTC bc/
286
ESP32-S2 TRM ( 1.3)
9
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Register 9.11. RTC_CNTL_TIMER5_REG (0x002C)
(reserved)
31
16 15
0000000000000000
RTC_CNTL_MIN_SLP_VAL
87
(reserved)
0
0x80
0 0 0 0 0 0 0 0 Reset
RTC_CNTL_MIN_SLP_VAL c RTC bc/
Register 9.12. RTC_CNTL_TIME_LOW1_REG (0x00E8)
RTC_CNTL_RTC_TIMER_VALUE1_LOW
31
0x000000
RTC_CNTL_RTC_TIMER_VALUE1_LOW RTC 1 32 bc
0
Reset
Register 9.13. RTC_CNTL_TIME_HIGH1_REG (0x00EC)
(reserved)
31
16 15
0000000000000000
RTC_CNTL_RTC_TIMER_VALUE1_HIGH
0
0x00
Reset
RTC_CNTL_RTC_TIMER_VALUE1_HIGH RTC 1 16 bc
287
ESP32-S2 TRM ( 1.3)
9
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Register 9.14. RTC_CNTL_ANA_CONF_REG (0x0034)
(reserved)
RTC_CRNTCT_L_CRPNTLCTL_LA_CR_PNTFLCTOL_LRA_CRC_SNTFEACTO_R_LPR__CCUISN2EATC_RL_P__FDIGO2LCRITC_CFEHO__PRRUCSET__PEDN
(reserved)
31
25 24 23 22 21 20 19
0
0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_CNTL_GLITCH_RST_EN 1 bc/ RTC_CNTL_SAR_I2C_FORCE_PD 1 SAR_I2Cbc/ RTC_CNTL_SAR_I2C_FORCE_PU 1 SAR_I2Cbc/ RTC_CNTL_PLLA_FORCE_PD 1 PLLAbc/ RTC_CNTL_PLLA_FORCE_PU 1 PLLAbc/
Register 9.15. RTC_CNTL_REG (0x0084)
RTC_CRNTCT_L_CRNT(TrCLe__sReRErTvGCeU_dRL)AETGOURRLT_ACFT_OOCRRNC_TFELO__PRRCUTEC__RPDTDBCI_ACSN_WTLA_KRTC_DBIAS_SLP RTC_CNTL_SCK_DCAP
RTC_CNTL_DIG_RDTBCIA_SC_NWTAL_KDIG_DBIAS_SLP (reserved)
31 30 29 28 27
25 24
22 21
14 13
11 10
87
0
1 00 0
4
4
0
4
4
0 0 0 0 0 0 0 0 Reset
RTC_CNTL_DIG_DBIAS_SLP CPU Sleep bc/ RTC_CNTL_DIG_DBIAS_WAK CPU Active bc/ RTC_CNTL_SCK_DCAP RTC bc/ RTC_CNTL_RTC_DBIAS_SLP CPU Sleep bc/ RTC_CNTL_RTC_DBIAS_WAK CPU Active bc/ RTC_CNTL_RTC_REGULATOR_FORCE_PD 1 c 0.8 V
bc/ RTC_CNTL_RTC_REGULATOR_FORCE_PU 1 c 0.8 V
bc/
288
ESP32-S2 TRM ( 1.3)
9
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Register 9.16. RTC_CNTL_PWC_REG (0x0088)
(reserved)
RTC_CNTRLT_CR_TCCN_TPRLAT_DCR__TCFCON_RTPRCLDT_EC_R__ETHCNCON_LTFRDLOT_CRR_CTCECN__PTFRULOT_CRR_CTCECN__PTSRDLLT_OCRW_TCMCN_ETSRMLLT__OCRPW_TDCMC_N_EETSRNMLLT__OCRFW_OTCMCRN_CETFRMELAT___SCPRFT_UOTMCCREN_CMTFRELA_T__SPCPRTD_DTMC_CEEN_NMTFRLA_T_SFCRTO_TMRCCCEN_METSR_L_LT_POFCRUOW_TRCMCCN_EETSRM_LLT_P_OCRDFW_OTCMCRN_CETSRMELLT___OCLRFWP_OTCUMCRN_CETFRMELAT___SCLRFTP_OTMCDCLENW_MTFR_LA_TC_SFCPRTO_UTMRCCCEN_METFR_LA_T_LSFCPRTO_UTMRCCCEN_METFR_LO_T_LFCRPRO_CDTLCECWN__N_TFRCLOOT_PICRSRU_COTCECN__ITSSRLLOT_OCRW_TCMCN_ETSRMLLT__OCRFW_OTCMCRN_CETFMELA___SIRSFTOTOMCRE_CMFEA__SFNTOOMRISCEOME__ISFOORCE_NOISO
31
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 1 Reset
RTC_CNTL_RTC_FASTMEM_FORCE_NOISO 1 RTC bc/ RTC_CNTL_RTC_FASTMEM_FORCE_ISO 1 RTC bc/ RTC_CNTL_RTC_SLOWMEM_FORCE_NOISO 1 RTC bc/ RTC_CNTL_RTC_SLOWMEM_FORCE_ISO 1 RTC bc/ RTC_CNTL_RTC_FORCE_ISO 1 RTC bc/ RTC_CNTL_RTC_FORCE_NOISO 1 RTC bc/ RTC_CNTL_RTC_FASTMEM_FOLW_CPU 1 CPU RTC 0 RTC
RTC bc/ RTC_CNTL_RTC_FASTMEM_FORCE_LPD 1 RTC bc/ RTC_CNTL_RTC_FASTMEM_FORCE_LPU 1 RTC bc/ RTC_CNTL_RTC_SLOWMEM_FOLW_CPU 1 CPU RTC 0 RTC
RTC bc/ RTC_CNTL_RTC_SLOWMEM_FORCE_LPD 1 RTC bc/ RTC_CNTL_RTC_SLOWMEM_FORCE_LPU 1 RTC bc/ RTC_CNTL_RTC_FASTMEM_FORCE_PD 1 RTC bc/ RTC_CNTL_RTC_FASTMEM_FORCE_PU 1 RTC bc/ RTC_CNTL_RTC_FASTMEM_PD_EN 1 Sleep RTC bc/ ...
289
ESP32-S2 TRM ( 1.3)
9
Register 9.16. RTC_CNTL_PWC_REG (0x0088)
GoBack
... RTC_CNTL_RTC_SLOWMEM_FORCE_PD 1 RTC bc/ RTC_CNTL_RTC_SLOWMEM_FORCE_PU 1 RTC bc/ RTC_CNTL_RTC_SLOWMEM_PD_EN 1 Sleep RTC bc/ RTC_CNTL_RTC_FORCE_PD 1 RTC bc/ RTC_CNTL_RTC_FORCE_PU 1 RTC bc/ RTC_CNTL_RTC_PD_EN 1 Sleep RTC bc/ RTC_CNTL_RTC_PAD_FORCE_HOLD 1 RTC GPIObc/
Register 9.17. RTC_CNTL_DIG_PWC_REG (0x008C)
RTC_CRNTCT_L_CDNGTL_W_WRIAFPI__PPD(Dr_e_EsENeNrved)
(reser(vreesde)r(vreesde)rRvTeCd_) CRNTCT_L_CRDNTCGT_L_W_CRDNTRCGTA_L_PW_C_WNFROTIAFLPRI__C_WFFEOOI_FRPRIC_CUFEEO__PRPCUDE_PD
31 30 29
24 23 22 21 20 19 18 17 16
(reserved)
RTC_CRNTCT_L_CLNSTLLP_(_rLeMSsLeEPrMv_e_MdFE)OMRC_FEO_PRCUE_PD
54 32
0
0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Reset
RTC_CNTL_LSLP_MEM_FORCE_PD 1 Sleep bc/ RTC_CNTL_LSLP_MEM_FORCE_PU 1 Sleep bc/ RTC_CNTL_WIFI_FORCE_PD 1 Wi-Fi bc/ RTC_CNTL_WIFI_FORCE_PU 1 Wi-Fi bc/ RTC_CNTL_DG_WRAP_FORCE_PD 1 bc/ RTC_CNTL_DG_WRAP_FORCE_PU 1 bc/ RTC_CNTL_WIFI_PD_EN 1 Sleep Wi-Fi bc/ RTC_CNTL_DG_WRAP_PD_EN 1 Sleep bc/
290
ESP32-S2 TRM ( 1.3)
9
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Register 9.18. RTC_CNTL_DIG_ISO_REG (0x0090)
RTC_CRNTCT_L_CRDNTCGT_L_W_CRDNTRCGTA_L_PW_C_WNFROTIAFLPRI__C_WFFEOOI_FRNRIC_COFEEIO_S_ONRISCOOEIS_OISO
31 30 29 28 27
(reserved)
RTC_CRNTCT_L_CRDNTCGT_L__CPRDANTDCGT__L__CFPRODANTDCGRTC__L__CFPERODA_NTDCGHRTC__L_O_CFPERLODA_NDTUDCGRTC__NL__CFPEHCOA_NOLDIRTLSRC_LDO__AEDDU_GGNTO__OPHPISAAOODDL__DAA_UUETTNOOHH(rOOeLsLeDDrved)
16 15 14 13 12 11 10 9 8
0
1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_CNTL_DG_PAD_AUTOHOLD GPIO auto-hold bc RTC_CNTL_CLR_DG_PAD_AUTOHOLD 1 GPIO auto-hold bc RTC_CNTL_DG_PAD_AUTOHOLD_EN 1 GPIO auto-hold bc/ RTC_CNTL_DG_PAD_FORCE_NOISO 1 GPIObc/ RTC_CNTL_DG_PAD_FORCE_ISO 1 GPIObc/ RTC_CNTL_DG_PAD_FORCE_UNHOLD 1 GPIO unhold bc/ RTC_CNTL_DG_PAD_FORCE_HOLD 1 GPIO hold bc/ RTC_CNTL_WIFI_FORCE_ISO 1 Wi-Fi bc/ RTC_CNTL_WIFI_FORCE_NOISO 1 Wi-Fi bc/ RTC_CNTL_DG_WRAP_FORCE_ISO 1 bc/ RTC_CNTL_DG_WRAP_FORCE_NOISO 1 bc/
291
ESP32-S2 TRM ( 1.3)
9
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Register 9.19. RTC_CNTL_LOW_POWER_ST_REG (0x00CC)
(reserved)
RTC_CNTL_MAIN_STA(TreEs_eINrv_eIDd)EL
RTC_CNTL_RTC_RDY_FOR_WAKEUP
(reserved)
31
28 27 26
20 19 18
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_CNTL_RDY_FOR_WAKEUP RTC b(RO) RTC_CNTL_MAIN_STATE_IN_IDLE RTC b
· 0 b RTC_CNTL_RDY_FOR_WAKEUP 1 b bRTC_CNTL_MAIN_STATE_IN_IDLE 1b
· 1cb
Register 9.20. RTC_CNTL_RESET_STATE_REG (0x0038)
(reserved)
RTC_CNTL_PROCPU_(SrTeAsTe_rvVeEdC)TOR_SEL
31
14 13 12
65
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 010 0 0 0 0 0 0
RTC_CNTL_RESET_CAUSE_PROCPU
0
0
Reset
RTC_CNTL_RESET_CAUSE_PROCPU CPU bc RTC_CNTL_PROCPU_STAT_VECTOR_SEL CPU (static vector)bc/
292
ESP32-S2 TRM ( 1.3)
9
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Register 9.21. RTC_CNTL_WAKEUP_STATE_REG (0x003C)
RTC_CNTL_RTC_WAKEUP_ENA
(reserved)
31
15 14
0
12
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_CNTL_RTC_WAKEUP_ENA b 9.4-3bc/
Register 9.22. RTC_CNTL_EXT_WAKEUP_CONF_REG (0x0064)
RTC_CRNTCT_L_CRENTXCTT_L__CWENAXTTKL_E_WUGPAP1KIO_EL_UVWPA0K_ELUVP_FILTER
(reserved)
31 30 29 28
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_CNTL_GPIO_WAKEUP_FILTER 1 GPIO bc/ RTC_CNTL_EXT_WAKEUP0_LV 0 EXT0 1 EXT0 bc/ RTC_CNTL_EXT_WAKEUP1_LV 0 EXT1 1 EXT1 bc/
Register 9.23. RTC_CNTL_SLP_REJECT_CONF_REG (0x0068)
RTC_CRNTCT_L_CDNETELP__LISGLHPT__RSELJPE_CRTE_JEENCT_EN
31 30 29
00
RTC_CNTL_RTC_SLEEP_REJECT_ENA 0
13 12
(reserved)
0
0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_CNTL_RTC_SLEEP_REJECT_ENA 1 opbc/ RTC_CNTL_LIGHT_SLP_REJECT_EN 1 o Light-sleeppbc/ RTC_CNTL_DEEP_SLP_REJECT_EN 1 o Deep-sleeppbc/
293
ESP32-S2 TRM ( 1.3)
9
Register 9.24. RTC_CNTL_EXT_WAKEUP1_REG (0x00DC)
(reserved)
RTC_CNTL_EXT_WAKEUP1_STATUS_CLR
31
23 22 21
0 0 0 0 0 0 0 0 00
RTC_CNTL_EXT_WAKEUP1_SEL 0
RTC_CNTL_EXT_WAKEUP1_SEL RTC GPIO EXT1 bc/ RTC_CNTL_EXT_WAKEUP1_STATUS_CLR EXT1 bc
GoBack
0
Reset
Register 9.25. RTC_CNTL_EXT_WAKEUP1_STATUS_REG (0x00E0)
(reserved)
31
22 21
0000000000
RTC_CNTL_EXT_WAKEUP1_STATUS 0
RTC_CNTL_EXT_WAKEUP1_STATUS EXT1 bc
0
Reset
Register 9.26. RTC_CNTL_SLP_REJECT_CAUSE_REG (0x0124)
(reserved)
31
17 16
000000000000000
RTC_CNTL_REJECT_CAUSE 0
RTC_CNTL_REJECT_CAUSE opbc
0
Reset
294
ESP32-S2 TRM ( 1.3)
9
Register 9.27. RTC_CNTL_SLP_WAKEUP_CAUSE_REG (0x012C)
(reserved)
31
17 16
000000000000000
RTC_CNTL_WAKEUP_CAUSE 0
RTC_CNTL_WAKEUP_CAUSE bc
GoBack
0
Reset
Register 9.28. RTC_CNTL_INT_ENA_RTC_REG (0x0040)
(reserved)
RTC_CRNTCT_L_CRRNTTCTC_L__CRGRNTLTCTIC_LT__CCRTRNHTOTC_TUC_LDC__CREHCRNTT_OTC_TTCC_ILNI__MCPRTXRNUTE_TTCT_OAECT_LUNLR__CR3TASARNT2_WPTCTKICN__LD_I_T_CRND_S_RNTIETNAETCTA_RTNC_LDE_A_A_CRN_DECRNTIANNCOTCTATC2C_L____CPRTEIRNUTNSNTCT_TEAC_LI_NN__CRESTSRNTN__ATCTAIERCN_LNA__CTRADMR_NTCTCETAC1N_LI_N__CARI_NBRNTTRTTCTICM_O_L_E_CWRETNRNTRNOTAC_T_UC_LIONC__CRUTTHRNTO_T_TCTE_UCI_LNNIC__CNRAATHRNTTCO_TC_TTUCA_ELIVCC__NC(ErHUTRNAe_I_LTsTVIPCDNeLE__rO_T_RvTCR_NITeNOPTCEdETU_CN__)_CI_CAIRNNEWHNTTNT_CDT__AS_TLEEC_C_NNASINANANLTTP_L__D_ERSONELNAJPEE__CWITNA_TKI_NEEUTN_PAE_NINAT_ENA
31
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_CNTL_SLP_WAKEUP_INT_ENA opbc/ RTC_CNTL_SLP_REJECT_INT_ENA opbc/ RTC_CNTL_RTC_WDT_INT_ENA RTC bc/ RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA bc/ RTC_CNTL_RTC_ULP_CP_INT_ENA bc/ ...
295
ESP32-S2 TRM ( 1.3)
9 Register 9.28. RTC_CNTL_INT_ENA_RTC_REG (0x0040)
GoBack
... RTC_CNTL_RTC_TOUCH_DONE_INT_ENA bc/ RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA bc/ RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA bc/ RTC_CNTL_RTC_BROWN_OUT_INT_ENA bc/ RTC_CNTL_RTC_MAIN_TIMER_INT_ENA RTC bc/ RTC_CNTL_RTC_SARADC1_INT_ENA SAR ADC 1 bc/ RTC_CNTL_RTC_TSENS_INT_ENA bc/ RTC_CNTL_RTC_COCPU_INT_ENA ULP-RISCV bc/ RTC_CNTL_RTC_SARADC2_INT_ENA SAR ADC 2 bc/ RTC_CNTL_RTC_SWD_INT_ENA bc/ RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA 32 kHz bc/ RTC_CNTL_RTC_COCPU_TRAP_INT_ENA ULP-RISCV bc/ RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA bc/ RTC_CNTL_RTC_GLITCH_DET_INT_ENA bc/
296
ESP32-S2 TRM ( 1.3)
9
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Register 9.29. RTC_CNTL_INT_RAW_RTC_REG (0x0044)
(reserved)
RTC_CRNTCT_L_CRRNTTCTC_L__CRGRNTLTCTIC_LT__CCRTRNHTOTC_TUC_LDC__CREHCRNTT_OTC_TTCC_ILNI__MCPRTXRNUTE_TTCT_OARCT_LULAR__CR3WTSARNT2_WPTCTKICN__LD_I_T_CRND_S_RNTIETNARTCTA_RTCA_LDR_AW__CRA_DRCRNTWINACOTCTWTC2C_L____CPRTRIRNUTNSATCT_TEWC_LI_NN__CRRSTSRNTA__ATCTWIRRCN_LAA__CTRWDMR_NTCTCRTAC1A_LI_N_W_CRI_NBRNTTRTTCTICM_O_L_R_CWRETARNTRNOWTC_T_UC_LIONC__CRUTTHRNTO_T_TCTR_UCI_LNAIC__CNRAWTHRNTTCO_TC_TTUCA_RLIVCC__CA(ErHUTWRNe_I_LTsTVIPCDNeLE__rO_T_RvTCR_NITeNOPTCRdETU_CA__)_CI_WCIRNNRWHNTTAT_CDT_W_S_TLRRC_C_AAASINWNWNLTTP_L__D_RRSOAELNWJPEE__CWITNA_TKI_NERUTA_PWR_AINWT_RAW
31
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_CNTL_SLP_WAKEUP_INT_RAW opbc RTC_CNTL_SLP_REJECT_INT_RAW opbc RTC_CNTL_RTC_WDT_INT_RAW RTC bc RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_RAW bc RTC_CNTL_RTC_ULP_CP_INT_RAW bc RTC_CNTL_RTC_TOUCH_DONE_INT_RAW bc RTC_CNTL_RTC_TOUCH_ACTIVE_INT_RAW bc RTC_CNTL_RTC_TOUCH_INACTIVE_INT_RAW bc RTC_CNTL_RTC_BROWN_OUT_INT_RAW bc RTC_CNTL_RTC_MAIN_TIMER_INT_RAW RTC bc RTC_CNTL_RTC_SARADC1_INT_RAW SAR ADC 1 bc RTC_CNTL_RTC_TSENS_INT_RAW bc RTC_CNTL_RTC_COCPU_INT_RAW ULP-RISCV bc RTC_CNTL_RTC_SARADC2_INT_RAW SAR ADC 2 bc RTC_CNTL_RTC_SWD_INT_RAW bc RTC_CNTL_RTC_XTAL32K_DEAD_INT_RAW 32 kHz bc ...
297
ESP32-S2 TRM ( 1.3)
9 Register 9.29. RTC_CNTL_INT_RAW_RTC_REG (0x0044)
GoBack
... RTC_CNTL_RTC_COCPU_TRAP_INT_RAW ULP-RISCV bc RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_RAW bc RTC_CNTL_RTC_GLITCH_DET_INT_RAW bc
298
ESP32-S2 TRM ( 1.3)
9
GoBack
Register 9.30. RTC_CNTL_INT_ST_RTC_REG (0x0048)
(reserved)
RTC_CRNTCT_L_CRRNTTCTC_L__CRGRNTLTCTIC_LT__CCRTRNHTOTC_TUC_LDC__CREHCRNTT_OTC_TTCC_ILNI__MCPRTXRNUTE_TTCT_OSACT_LUTLR__CR3TSARNT2_WPTCTKICN__LD_I_T_CRND_S_RNTIETNASTCTA_TRTC_LDS_A__CRT_SDCRNTITNCOTCTTC2C_L____CPRTSIRNUTNSTTCT_TEC_LI_NN__CRSSTSRNTT__ATCTISRCN_LTA__CTRDMR_NTCTSCTAC1T_LI_N__CRI_NBRNTTRTTCTICM_O_L_S_CWRETTRNTRNOTC_T_UC_LIONC__CRUTTHRNTO_T_TCTS_UCI_LNTIC__CNRATHRNTTCO_TC_TTUCAS_LIVCC_T_C(ErHUTRNe_I_LTsTVIPCDNeLE__rO_T_RvTCR_NITeNOPTSCdETU_CT__)_CI_CIRNSNWHNTTTT_CDT__S_TLSSC_C_TTASINNNLTTP_L__D_SRSOTELNJPEE__CWITNA_TKI_NESUTT_PS_TINT_ST
31
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_CNTL_SLP_WAKEUP_INT_ST opbc RTC_CNTL_SLP_REJECT_INT_ST opbc RTC_CNTL_RTC_WDT_INT_ST RTC bc RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ST bc RTC_CNTL_RTC_ULP_CP_INT_ST bc RTC_CNTL_RTC_TOUCH_DONE_INT_ST bc RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ST bc RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ST bc RTC_CNTL_RTC_BROWN_OUT_INT_ST bc RTC_CNTL_RTC_MAIN_TIMER_INT_ST RTC bc RTC_CNTL_RTC_SARADC1_INT_ST SAR ADC 1 bc RTC_CNTL_RTC_TSENS_INT_ST bc RTC_CNTL_RTC_COCPU_INT_ST ULP-RISCV bc RTC_CNTL_RTC_SARADC2_INT_ST SAR ADC 2 bc RTC_CNTL_RTC_SWD_INT_ST bc RTC_CNTL_RTC_XTAL32K_DEAD_INT_ST 32 kHz bc ...
299
ESP32-S2 TRM ( 1.3)
9
Register 9.30. RTC_CNTL_INT_ST_RTC_REG (0x0048)
GoBack
... RTC_CNTL_RTC_COCPU_TRAP_INT_ST ULP-RISCV bc RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ST bc RTC_CNTL_RTC_GLITCH_DET_INT_ST bc
300
ESP32-S2 TRM ( 1.3)
9
GoBack
Register 9.31. RTC_CNTL_INT_CLR_RTC_REG (0x004C)
(reserved)
RTC_CRNTCT_L_CRRNTTCTC_L__CRGRNTLTCTIC_LT__CCRTRNHTOTC_TUC_LDC__CREHCRNTT_OTC_TTCC_ILNI__MCPRTXRNUTE_TTCT_OCACT_LULLR__CR3RTSARNT2_WPTCTKICN__LD_I_T_CRND_S_RNTIETNACTCTA_RTCL_LDCR_A__CR_LCDCRNTRINLCOTCTRTC2C_L____CPRTCIRNUTNSLTCT_TERC_LI_NN__CRCSTSRNTL__ATCRTCIRCN_LLA__CTRRDMR_NTCTCCTAC1L_LI_NR__CRI_NBRNTTRTTCTICM_O_LC__CWRETLRNTRNORTC_T_UC_LIONC__CRUTTHRNTO_T_TCTC_UCI_LNLIC__CNRARTHRNTTCO_TC_TTUCAC_LIVCC__CL(ErHUTRRNe_I_LTsTVIPCDNeLE__rO_T_RvTCR_NITeNOPCTCdETU_CL__)_CIR_CIRNCNWHNTTLT_CDT_R_S_TLCCC_C_LLASIRNRNNLTTP_L__D_CRSOLELNRJPEE__CWITNA_TKI_NECUTL_PRC_LINRT_CLR
31
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_CNTL_SLP_WAKEUP_INT_CLR opbc RTC_CNTL_SLP_REJECT_INT_CLR opbc RTC_CNTL_RTC_WDT_INT_CLR RTC bc RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_CLR bc RTC_CNTL_RTC_ULP_CP_INT_CLR ULP bc RTC_CNTL_RTC_TOUCH_DONE_INT_CLR bc RTC_CNTL_RTC_TOUCH_ACTIVE_INT_CLR bc RTC_CNTL_RTC_TOUCH_INACTIVE_INT_CLR bc RTC_CNTL_RTC_BROWN_OUT_INT_CLR bc RTC_CNTL_RTC_MAIN_TIMER_INT_CLR RTC bc RTC_CNTL_RTC_SARADC1_INT_CLR SAR ADC 1 bc RTC_CNTL_RTC_TSENS_INT_CLR bc RTC_CNTL_RTC_COCPU_INT_CLR ULP-RISCV bc RTC_CNTL_RTC_SARADC2_INT_CLR SAR ADC 2 bc RTC_CNTL_RTC_SWD_INT_CLR bc RTC_CNTL_RTC_XTAL32K_DEAD_INT_CLR 32 kHz bc ...
301
ESP32-S2 TRM ( 1.3)
9
Register 9.31. RTC_CNTL_INT_CLR_RTC_REG (0x004C)
... RTC_CNTL_RTC_COCPU_TRAP_INT_CLR ULP-RISCV bc RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_CLR bc RTC_CNTL_RTC_GLITCH_DET_INT_CLR bc
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Register 9.32. RTC_CNTL_STORE0_REG (0x0050)
RTC_CNTL_RTC_SCRATCH0
31
0
RTC_CNTL_RTC_SCRATCH0 0bc/
0
Reset
Register 9.33. RTC_CNTL_STORE1_REG (0x0054)
RTC_CNTL_RTC_SCRATCH1
31
0
RTC_CNTL_RTC_SCRATCH1 1bc/
0
Reset
302
ESP32-S2 TRM ( 1.3)
9
Register 9.34. RTC_CNTL_STORE2_REG (0x0058)
RTC_CNTL_RTC_SCRATCH2
31
0
RTC_CNTL_RTC_SCRATCH2 2bc/
Register 9.35. RTC_CNTL_STORE3_REG (0x005C)
RTC_CNTL_RTC_SCRATCH3
31
0
RTC_CNTL_RTC_SCRATCH3 3bc/
Register 9.36. RTC_CNTL_STORE4_REG (0x00BC)
RTC_CNTL_RTC_SCRATCH4
31
0
RTC_CNTL_RTC_SCRATCH4 4bc/
GoBack
0
Reset
0
Reset
0
Reset
303
ESP32-S2 TRM ( 1.3)
9
Register 9.37. RTC_CNTL_STORE5_REG (0x00C0)
RTC_CNTL_RTC_SCRATCH5
31
0
RTC_CNTL_RTC_SCRATCH5 5bc/
Register 9.38. RTC_CNTL_STORE6_REG (0x00C4)
RTC_CNTL_RTC_SCRATCH6
31
0
RTC_CNTL_RTC_SCRATCH6 6bc/
Register 9.39. RTC_CNTL_STORE7_REG (0x00C8)
RTC_CNTL_RTC_SCRATCH7
31
0
RTC_CNTL_RTC_SCRATCH7 7bc/
GoBack
0
Reset
0
Reset
0
Reset
304
ESP32-S2 TRM ( 1.3)
9
GoBack
Register 9.40. RTC_CNTL_EXT_XTL_CONF_REG (0x0060)
RTC_CRNTCT_L_CXNTTLL__EXXTTL__CETX(RTre__sECeNTrRve_dLV)
RTC_CNTL_RRTTCC__CXNTTALL_3R2TKC__GWPDIOT__SSETLATE
31 30 29
24 23 22
20 19
(reserved)
RTC_CRNTCT_L_CRENTNCTC_L_CKRXINTNTCTIAT_LL__CR3XXNT2TTCTKAA_L_LL_CRX_3XNTP32TCTD2KA_LK__L_CRFA3XNTOU2TCTRTKA_LOC_L_CR_EA3XNTUR2TCTETKA_LOT_L_CRU_A3XNTURR2TCTNETKA_LOS_L_CTE_3XANXB2TRTTAKAT_LC_L_CWK3XLU2DTKKPTA___LFW3RO2EDKST_E_WTCLDKT__FEON
98 7 6 5 4 3 2 1 0
0 00 0 0 0 0 00
0x0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Reset
RTC_CNTL_XTAL32K_WDT_EN 1 32 bc/ RTC_CNTL_XTAL32K_WDT_CLK_FO 1 32 kHz bc/ RTC_CNTL_XTAL32K_WDT_RESET 1 32 kHz bc/ RTC_CNTL_XTAL32K_EXT_CLK_FO 1 32 kHz bc/ RTC_CNTL_XTAL32K_AUTO_BACKUP 1 32 kHz bc/ RTC_CNTL_XTAL32K_AUTO_RESTART 1 32 kHz 32 kHz bc/ RTC_CNTL_XTAL32K_AUTO_RETURN 1 32 kHz 32 kHz bc/
RTC_CNTL_XTAL32K_XPD_FORCE 1 32 kHz 0 FSM 32 kHz bc/
RTC_CNTL_ENCKINIT_XTAL_32K 1 32 kHz bc/ RTC_CNTL_RTC_WDT_STATE 32 kHz bc RTC_CNTL_RTC_XTAL32K_GPIO_SEL 32 kHz b 0 32 kHz 1
RTC GPIO X32P_C bc/ RTC_CNTL_XTL_EXT_CTR_LV 1 XTAL 0 XTAL bc/ RTC_CNTL_XTL_EXT_CTR_EN 1 GPIO bc/
305
ESP32-S2 TRM ( 1.3)
9
GoBack
Register 9.41. RTC_CNTL_CLK_CONF_REG (0x0074)
RTC_CNRTTL_CA_NCAN_(TrCLe_LsKeFA_rvSReTTdR_C)TC_CLS_KECR_LNTRCTT_LC_C_CNSKTE8LLM_C_KF8OMRC_FEO_PRCU(Ere_sPeDrved)
31 30 29 28 27 26 25 24
RTC_CRNTCT_L_CCNKT8LM_RXT_TCFA_OLCR_NCFTEOL_R_(NCrCeOEKs_G8eNAMrRTvOTe_INGCdDAG_)ITVCRI_NNTSGCTE_LL_CRDNTCITG_L__CRCDNTLCITKG_L8__CRMCDNTL_CITKGE_L8_N_CMXENT_NRTADBTLL2_C3_52CE_6NKCK__B8NEEM_RTNNCTL__CKDC8_IVMKC8NMTL__(DrCeIVKs8eMrve_dD)IV_SEL_VLD
17 16 15 14
12 11 10 9 8 7 6 5
432
0
0 00 00 00 0 0 0 0 0 0 00 0
3
00 1 000
1
1 0 0 0 Reset
RTC_CNTL_CK8M_DIV_SEL_VLD reg_ck8m_div_sel b bc/
RTC_CNTL_CK8M_DIV CK8M_D256_OUT b00: 128 01256 10512 111024 bc/
RTC_CNTL_ENB_CK8M 1 CK8M CK8M_D256_OUTbc/ RTC_CNTL_ENB_CK8M_DIV CK8M_D256_OUT b 1 CK8M 0 CK8M
256 bc/ RTC_CNTL_DIG_XTAL32K_EN 1 CK_XTAL_32K bc/ RTC_CNTL_DIG_CLK8M_D256_EN 1 CK8M_D256_OUT bc/ RTC_CNTL_DIG_CLK8M_EN 1 8 MHz bc/ RTC_CNTL_CK8M_DIV_SEL 8 MHz reg_ck8m_div_sel + 1bc/ RTC_CNTL_XTAL_FORCE_NOGATING 1 Sleep bc/ RTC_CNTL_CK8M_FORCE_NOGATING 1 Sleep 8 MHz bc/ RTC_CNTL_CK8M_FORCE_PD 1 8 MHz bc/ RTC_CNTL_CK8M_FORCE_PU 1 8 MHz bc/ RTC_CNTL_FAST_CLK_RTC_SEL RTC b0: XTAL_DIV_CLK1: RC_FAST_CLKbc/
RTC_CNTL_ANA_CLK_RTC_SEL RTC b0: RC_SLOW_CLK1: XTAL32K_CLK2: RC_FAST_DIV_CLKbc/
306
ESP32-S2 TRM ( 1.3)
9
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(reserved)
31 30
0
Register 9.42. RTC_CNTL_SLOW_CLK_CONF_REG (0x0078)
RTC_CNTL_RTC_ANA_CLRKT_CD_ICVNTL_RTC_ANA_CLK_DIV_VLD
(reserved)
23 22 21
0
0
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_CNTL_RTC_ANA_CLK_DIV_VLD reg_rtc_ana_clk_div b b
RTC_CNTL_RTC_ANA_CLK_DIV RTC bc/
Register 9.43. RTC_CNTL_XTAL32K_CLK_FACTOR_REG (0x00F0)
RTC_CNTL_XTAL32K_CLK_FACTOR
31
0x000000
RTC_CNTL_XTAL32K_CLK_FACTOR 32 kHz bc/
0
Reset
307
ESP32-S2 TRM ( 1.3)
9
GoBack
Register 9.44. RTC_CNTL_XTAL32K_CONF_REG (0x00F4)
RTC_CNTL_XTAL32K_STABLE_THRRTECS_CNTL_XTAL32K_WDT_TIMEOUT
31
28 27
20 19
0x0
0xff
RTC_CNTL_XTAL32K_RESTART_WAIT
43
0x00
RTC_CNTL_XTAL32K_RETURN_WAIT
0
0x0
Reset
RTC_CNTL_XTAL32K_RETURN_WAIT 32 kHz bc/
RTC_CNTL_XTAL32K_RESTART_WAIT 32 kHz bc/
RTC_CNTL_XTAL32K_WDT_TIMEOUT b 32 kHz bc/
RTC_CNTL_XTAL32K_STABLE_THRES b 32 kHz 32 kHz bc/
308
ESP32-S2 TRM ( 1.3)
9
GoBack
Register 9.45. RTC_CNTL_WDTCONFIG0_REG (0x0094)
RTC_CNTL_RWTCD_TC_NENTL_WDT_RSTCTG_0CNTL_WDT_RSTCTG_1CNTL_WDT_RSTCTG_2CNTL_WDT_RSTCTG_3CNTL_WDT_RCTCP_UC_NRTELS_ERWTT_CDL_TEC_RNNSTGCYTTS_LH__C(rWRNeEsTDSeLTEr__RvTWTFe_CLdDLA_)TESC_NHNPGBRTTOLOH_OCWTP_DUMT__ROPEDAS_UEESTNE__EINN(_reSsLePrved)
31 30
28 27
25 24
22 21
19 18
16 15
13 12 11 10 9 8
0
0
0x0
0x0
0x0
0x0
0x1
0x1
1 0 0 1 0 0 0 0 0 0 0 0 0 Reset
RTC_CNTL_WDT_PAUSE_IN_SLP 1 opbc/ RTC_CNTL_WDT_PROCPU_RESET_EN 1 CPUbc/ RTC_CNTL_WDT_FLASHBOOT_MOD_EN 1 flash bc/ RTC_CNTL_WDT_SYS_RESET_LENGTH bc/ RTC_CNTL_WDT_CPU_RESET_LENGTH CPU bc/ RTC_CNTL_WDT_STG3 12 CPU 34
RTC bc/ RTC_CNTL_WDT_STG2 12 CPU 34
RTC bc/ RTC_CNTL_WDT_STG1 12 CPU 34
RTC bc/ RTC_CNTL_WDT_STG0 12 CPU 34
RTC bc/ RTC_CNTL_WDT_EN 1 RTC bc/
12 (WDT)b
309
ESP32-S2 TRM ( 1.3)
9
Register 9.46. RTC_CNTL_WDTCONFIG1_REG (0x0098)
RTC_CNTL_WDT_STG0_HOLD
31
200000
RTC_CNTL_WDT_STG0_HOLD 1 RTC bc/
Register 9.47. RTC_CNTL_WDTCONFIG2_REG (0x009C)
RTC_CNTL_WDT_STG1_HOLD
31
80000
RTC_CNTL_WDT_STG1_HOLD 2 RTC bc/
Register 9.48. RTC_CNTL_WDTCONFIG3_REG (0x00A0)
RTC_CNTL_WDT_STG2_HOLD
31
0x000fff
RTC_CNTL_WDT_STG2_HOLD 3 RTC bc/
GoBack
0
Reset
0
Reset
0
Reset
310
ESP32-S2 TRM ( 1.3)
9
Register 9.49. RTC_CNTL_WDTCONFIG4_REG (0x00A4)
RTC_CNTL_WDT_STG3_HOLD
31
0x000fff
RTC_CNTL_WDT_STG3_HOLD 4 RTC bc/
GoBack
0
Reset
Register 9.50. RTC_CNTL_WDTFEED_REG (0x00A8)
RTC_CNTL_RTC_WDT_FEED
(reserved)
31 30
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_CNTL_RTC_WDT_FEED 1 bc
Register 9.51. RTC_CNTL_WDTWPROTECT_REG (0x00AC)
RTC_CNTL_WDT_WKEY
31
0
0x50d83aa1
Reset
RTC_CNTL_WDT_WKEY 0x50d83aa1 RTC (RWDT) bc/
311
ESP32-S2 TRM ( 1.3)
9
GoBack
Register 9.52. RTC_CNTL_SWD_CONF_REG (0x00B0)
RTC_CRNTCT_L_CRSNTWCT_LD_CR_SNTAWCTU_LDT_CO_SND_WTFISLDEA_E_BSDFLW_EEEEDDN_RST_FLAG_CRLTRC_CNTL_SWD_SIGNAL_WIDTH
31 30 29 28 27
18 17
(reserved)
RTC_CRNTCT_L_CSNWTLD__SFWEEDD__RIENSTET_FLAG
21 0
0000
300
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_CNTL_SWD_RESET_FLAG bc RTC_CNTL_SWD_FEED_INT bc RTC_CNTL_SWD_SIGNAL_WIDTH bc/ RTC_CNTL_SWD_RST_FLAG_CLR 1 bc RTC_CNTL_SWD_FEED 1 bc RTC_CNTL_SWD_DISABLE 1 bc/ RTC_CNTL_SWD_AUTO_FEED_EN 1 bc/
Register 9.53. RTC_CNTL_SWD_WPROTECT_REG (0x00B4)
RTC_CNTL_SWD_WKEY
31
0x8f1d312a
RTC_CNTL_SWD_WKEY bc/
0
Reset
312
ESP32-S2 TRM ( 1.3)
9
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Register 9.54. RTC_CNTL_SW_CPU_STALL_REG (0x00B8)
RTC_CNTL_SW_STALL_PROCPU_C1
(reserved)
31
26 25
0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_CNTL_SW_STALL_PROCPU_C1 RTC_CNTL_SW_STALL_PROCPU_C0 0x2 0x21 CPU stall bc/
313
ESP32-S2 TRM ( 1.3)
9
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Register 9.55. RTC_CNTL_PAD_HOLD_REG (0x00D4)
(reserved)
RTC_CRNTCT_L_CRRNTTCTC_L__CRPRNTATCTDC_L2__CR1PRNT_ATCTHDC_LO2__CRL0PPNTDA_DCTDHA_L1OC_CR9PL2NT_DDC_THHA_LOC_CORLX1NTLD_3CDTH2_LON_CRL_XNTD3HCT2O_LP_CLRT_DNTOHCTUO_LCL_CRTDHNTO_CTUP_LCA_CRTDHNTO1_CT4UP_L_CA_CRHTDHNTOO1_CT3LUP_L_DCA_CRHTDHNTOO1_CT2LUP_L_DCA_CRHTDHNTOO1_CT1LUP__LDCA_CHRTDHNTOO1_CTL0UP_DL_CA_CRHTDHNTOO9_CTUL_P_LDCAH_CRTDHONTO8_CLTU_DP_LCHA_CRTDHONTO7_CLT_UDP_LHCA_CRTODHNTOL6_CTUD_P_LCAH_CRTDHONTO5_CLTU_DP_LCAH_CRTDHONTO4_CLTU_DP_LCHA_CTDHONO3_LTU_DPLCAH_TDHOO2_LU_DPCAHDHO1_L_DPHAODL0D_HOLD
31
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_CNTL_TOUCH_PAD0_HOLD 1 GPIO 0 hold bc/ RTC_CNTL_TOUCH_PAD1_HOLD 1 GPIO 1 hold bc/ RTC_CNTL_TOUCH_PAD2_HOLD 1 GPIO 2 hold bc/ RTC_CNTL_TOUCH_PAD3_HOLD 1 GPIO 3 hold bc/ RTC_CNTL_TOUCH_PAD4_HOLD 1 GPIO 4 hold bc/ RTC_CNTL_TOUCH_PAD5_HOLD 1 GPIO 5 hold bc/ RTC_CNTL_TOUCH_PAD6_HOLD 1 GPIO 6 hold bc/ RTC_CNTL_TOUCH_PAD7_HOLD 1 GPIO 7 hold bc/ RTC_CNTL_TOUCH_PAD8_HOLD 1 GPIO 8 hold bc/ RTC_CNTL_TOUCH_PAD9_HOLD 1 GPIO 9 hold bc/ RTC_CNTL_TOUCH_PAD10_HOLD 1 GPIO 10 hold bc/ RTC_CNTL_TOUCH_PAD11_HOLD 1 GPIO 11 hold bc/ RTC_CNTL_TOUCH_PAD12_HOLD 1 GPIO 12 hold bc/ RTC_CNTL_TOUCH_PAD13_HOLD 1 GPIO 13 hold bc/ RTC_CNTL_TOUCH_PAD14_HOLD 1 GPIO 14 hold bc/ RTC_CNTL_X32P_HOLD 1 x32p hold bc/ RTC_CNTL_X32N_HOLD 1 x32n hold bc/ RTC_CNTL_PDAC1_HOLD 1 pdac1 hold bc/ RTC_CNTL_PDAC2_HOLD 1 pdac2 hold bc/ RTC_CNTL_RTC_PAD19_HOLD 1 GPIO 19 hold bc/ RTC_CNTL_RTC_PAD20_HOLD 1 GPIO 20 hold bc/ RTC_CNTL_RTC_PAD21_HOLD 1 GPIO 21 hold bc/
314
ESP32-S2 TRM ( 1.3)
9
GoBack
Register 9.56. RTC_CNTL_DIG_PAD_HOLD_REG (0x00D8)
RTC_CNTL_DIG_PAD_HOLD
31
0
0
Reset
RTC_CNTL_DIG_PAD_HOLD 1 GPIO 21 GPIO 45 hold bGPIO bc/
Register 9.57. RTC_CNTL_BROWN_OUT_REG (0x00E4)
RTC_CRNTCT_L_CRRNTTCTC_L__C(rBBNeRRsTOeOLr_WWRvBTeNNCRd__O_)OOCWRUUNTNTTCT____LODE_CNUEBNTATRT_OLC_WNBNTR__OOCWULNRT__ORUSTT__SRESLTR_TECN_ACNTL_BROWN_OUT_RSTR_TWCA_ICTRNTCT_L_CBNRTOL_WBNR_OOWUNT__OPUDT__RCF_LOERNSTEAC__FCLNATSLH__BERNOAWN_OUT_INT_WAIT(reserved) RTC_CNTL_BROWN_OUT2_ENA
31 30 29 28 27 26 25
16 15 14 13
43
10
000000
0x3ff
00
0x2ff
0 0 0 1 Reset
RTC_CNTL_BROWN_OUT2_ENA 1 bc/ RTC_CNTL_BROWN_OUT_INT_WAIT bc/ RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA 1 flashbc/
RTC_CNTL_BROWN_OUT_PD_RF_ENA 1 RF bc/ RTC_CNTL_BROWN_OUT_RST_WAIT bc/ RTC_CNTL_BROWN_OUT_RST_ENA 1 bc/ RTC_CNTL_BROWN_OUT_RST_SEL b 1 1
bc/ RTC_CNTL_BROWN_OUT_CNT_CLR bc RTC_CNTL_BROWN_OUT_ENA 1 bc/ RTC_CNTL_RTC_BROWN_OUT_DET bc
315
ESP32-S2 TRM ( 1.3)
10 (SYSTIMER)
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10
(SYSTIMER)
10.1
ESP32-S2 64 b b
10.2
· 64 b · APB_CLK b · APB_CLK b · APB_CLK PLL_CLK XTAL_CLK XTAL_CLK PLL_CLK
b · cb · 64 30 b · b Light-sleep RTC
b · CPU b
10.3
XTAL_CLK PLL_CLK b 6 6.2-1 CPU_CLK b 6.2-4 APB_CLK b SYSTIMER_TIMER_XTAL_STEP SYSTIMER_TIMER_PLL_STEP b
10.4
10.4-1 b SYSTEM_PERIP_CLK_EN0_REG SYSTEM_SYSTIMER_CLK_EN SYSTEM_PERIP_RST_EN0_REG SYSTEM_SYSTIMER_RST b 15 15.3-3 b
316
ESP32-S2 TRM ( 1.3)
10 (SYSTIMER)
GoBack
10.4-1.
10.4.1
1. SYSTIMER_TIMER_UPDATE b 2. SYSTIMER_TIMER_VALUE_VALID bb 3. SYSTIMER_TIMER_VALUE_HI 32 SYSTIMER_TIMER_VALUE_LO
32 b
10.4.2
1. 10.4.1b 3 b 2. SYSTIMER_TARGETx_PERIOD_MODEb 3. c 32 SYSTIMER_TIMER_TARGETx_HI 32
SYSTIMER_TIMER_TARGETx_LOb 4. SYSTIMER_TARGETx_WORK_ENb 5. SYSTIMER_INTx_ENA bb
10.4.3
1. SYSTIMER_TARGETx_PERIOD_MODEb 2. c SYSTIMER_TARGETx_PERIODb 3. SYSTIMER_TARGETx_WORK_ENb 4. SYSTIMER_INTx_ENA bb
10.4.4
1. Light-sleep RTC b 2. Light-sleep RTC b 3. 10.4.1b 4. b 5. SYSTIMER_TIMER_LOAD_HIc 32 SYSTIMER_TIMER_LOAD_LOc 32 b
317
ESP32-S2 TRM ( 1.3)
10 (SYSTIMER)
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6. SYSTIMER_TIMER_LOAD 5 b
10.5
10.5-1 b 3 b
10.5-1.
PeriBUS1 PeriBUS2
0x3F423000 0x60023000
10.6
cb 10.5 b
SYSTIMER_CONF_REG SYSTIMER_LOAD_REG SYSTIMER_LOAD_HI_REG SYSTIMER_LOAD_LO_REG SYSTIMER_STEP_REG SYSTIMER_TARGET0_HI_REG SYSTIMER_TARGET0_LO_REG SYSTIMER_TARGET1_HI_REG SYSTIMER_TARGET1_LO_REG SYSTIMER_TARGET2_HI_REG SYSTIMER_TARGET2_LO_REG SYSTIMER_TARGET0_CONF_REG SYSTIMER_TARGET1_CONF_REG SYSTIMER_TARGET2_CONF_REG SYSTIMER_UPDATE_REG SYSTIMER_VALUE_HI_REG SYSTIMER_VALUE_LO_REG SYSTIMER_INT_ENA_REG SYSTIMER_INT_RAW_REG SYSTIMER_INT_CLR_REG SYSTIMER_DATE_REG
32 32 0 32 0 32 1 32 1 32 2 32 2 32 0 1 2 32 32
0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x004C
/ / / / / / / / / / / / / /
0x00FC /
318
ESP32-S2 TRM ( 1.3)
10 (SYSTIMER)
10.7
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Register 10.1. SYSTIMER_CONF_REG (0x0000)
SYSTIMER_CLK_EN
31 30
(reserved)
SYSTIMER_CLK_FO
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTIMER_CLK_FO bc/ SYSTIMER_CLK_EN bc/
Register 10.2. SYSTIMER_LOAD_REG (0x0004)
SYSTIMER_TIMER_LOAD
(reserved)
31 30
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTIMER_TIMER_LOAD 1 SYSTIMER_TIMER_LOAD_HI SYSTIMER_TIMER_LOAD_LO bc
Register 10.3. SYSTIMER_LOAD_HI_REG (0x0008)
SYSTIMER_TIMER_LOAD_HI
31
0
SYSTIMER_TIMER_LOAD_HI 32 bc/
0
Reset
319
ESP32-S2 TRM ( 1.3)
10 (SYSTIMER)
Register 10.4. SYSTIMER_LOAD_LO_REG (0x000C)
SYSTIMER_TIMER_LOAD_LO
31
0
SYSTIMER_TIMER_LOAD_LO 32 bc/
GoBack
0
Reset
Register 10.5. SYSTIMER_STEP_REG (0x0010)
(reserved)
31
20 19
000000000000
SYSTIMER_TIMER_PLL_STEP
10 9
1
SYSTIMER_TIMER_XTAL_STEP
0
80
Reset
SYSTIMER_TIMER_XTAL_STEP XTAL_CLK 1 us/CLK bc/
SYSTIMER_TIMER_PLL_STEP PLL_CLK 1 us/CLK bc/
Register 10.6. SYSTIMER_TARGET0_HI_REG (0x0014)
SYSTIMER_TIMER_TARGET0_HI
31
0
SYSTIMER_TIMER_TARGET0_HI 0 32 bc/
0
Reset
320
ESP32-S2 TRM ( 1.3)
10 (SYSTIMER)
Register 10.7. SYSTIMER_TARGET0_LO_REG (0x0018)
SYSTIMER_TIMER_TARGET0_LO
31
0
SYSTIMER_TIMER_TARGET0_LO 0 32 bc/
Register 10.8. SYSTIMER_TARGET1_HI_REG (0x001C)
SYSTIMER_TIMER_TARGET1_HI
31
0
SYSTIMER_TIMER_TARGET1_HI 1 32 bc/
Register 10.9. SYSTIMER_TARGET1_LO_REG (0x0020)
SYSTIMER_TIMER_TARGET1_LO
31
0
SYSTIMER_TIMER_TARGET1_LO 1 32 bc/
GoBack
0
Reset
0
Reset
0
Reset
321
ESP32-S2 TRM ( 1.3)
10 (SYSTIMER)
Register 10.10. SYSTIMER_TARGET2_HI_REG (0x0024)
SYSTIMER_TIMER_TARGET2_HI
31
0
SYSTIMER_TIMER_TARGET2_HI 2 32 bc/
GoBack
0
Reset
Register 10.11. SYSTIMER_TARGET2_LO_REG (0x0028)
SYSTIMER_TIMER_TARGET2_LO
31
0
SYSTIMER_TIMER_TARGET2_LO 2 32 bc/
0
Reset
Register 10.12. SYSTIMER_TARGET0_CONF_REG (0x002C)
SYSTISMYESRT_IMTAERRG_ETTA0RG_WETO0R_KP_EERNIOD_MODE
31 30 29
00
SYSTIMER_TARGET0_PERIOD 0x000000
0
Reset
SYSTIMER_TARGET0_PERIOD 0 bc/
SYSTIMER_TARGET0_PERIOD_MODE 0 b01 bc/
SYSTIMER_TARGET0_WORK_EN 0 bc/
322
ESP32-S2 TRM ( 1.3)
10 (SYSTIMER)
GoBack
Register 10.13. SYSTIMER_TARGET1_CONF_REG (0x0030)
SYSTISMYESRT_IMTAERRG_ETTA1R_GWEOTR1_KP_EERNIOD_MODE
31 30 29
00
SYSTIMER_TARGET1_PERIOD 0x000000
0
Reset
SYSTIMER_TARGET1_PERIOD 1 bc/
SYSTIMER_TARGET1_PERIOD_MODE 1 b01 bc/
SYSTIMER_TARGET1_WORK_EN 1 bc/
Register 10.14. SYSTIMER_TARGET2_CONF_REG (0x0034)
SYSTISMYESRT_IMTAERRG_ETTA2R_GWETO2R_KP_EERNIOD_MODE
31 30 29
00
SYSTIMER_TARGET2_PERIOD 0x000000
0
Reset
SYSTIMER_TARGET2_PERIOD 2 bc/
SYSTIMER_TARGET2_PERIOD_MODE 2 b01 bc/
SYSTIMER_TARGET2_WORK_EN 2 bc/
323
ESP32-S2 TRM ( 1.3)
10 (SYSTIMER)
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Register 10.15. SYSTIMER_UPDATE_REG (0x0038)
SYSTISMYESRT_IMTIEMRE_RT_IMUPERD_AVTAELUE_VALID
(reserved)
31 30 29
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTIMER_TIMER_VALUE_VALID b0 1bc
SYSTIMER_TIMER_UPDATE bc
Register 10.16. SYSTIMER_VALUE_HI_REG (0x003C)
SYSTIMER_TIMER_VALUE_HI
31
0
SYSTIMER_TIMER_VALUE_HI 32 bc
0
Reset
Register 10.17. SYSTIMER_VALUE_LO_REG (0x0040)
SYSTIMER_TIMER_VALUE_LO
31
0
SYSTIMER_TIMER_VALUE_LO 32 bc
0
Reset
324
ESP32-S2 TRM ( 1.3)
10 (SYSTIMER)
GoBack
Register 10.18. SYSTIMER_INT_ENA_REG (0x0044)
(reserved)
SYSTISMYESRT_ISMINYESTRT2_I_MINEENTR1A__IENNTA0_ENA
31
32 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTIMER_INT0_ENA 0 bc/ SYSTIMER_INT1_ENA 1 bc/ SYSTIMER_INT2_ENA 2 bc/
Register 10.19. SYSTIMER_INT_RAW_REG (0x0048)
(reserved)
SYSTISMYESRT_ISMINYESTRT2_I_MINREATRW1__IRNATW0_RAW
31
32 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTIMER_INT0_RAW 0 bc SYSTIMER_INT1_RAW 1 bc SYSTIMER_INT2_RAW 2 bc
Register 10.20. SYSTIMER_INT_CLR_REG (0x004C)
(reserved)
SYSTISMYESRT_ISMINYESTRT2_I_MICNELTRR1__CINLTR0_CLR
31
32 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTIMER_INT0_CLR 0 bc SYSTIMER_INT1_CLR 1 bc SYSTIMER_INT2_CLR 2 bc
325
ESP32-S2 TRM ( 1.3)
10 (SYSTIMER)
Register 10.21. SYSTIMER_DATE_REG (0x00FC)
SYSTIMER_DATE
31
0x1807160
SYSTIMER_DATE bc/
GoBack
0
Reset
326
ESP32-S2 TRM ( 1.3)
11 (TIMG)
GoBack
11
(TIMG)
11.1
acb 11.1-1ESP32-S2 0 1bc Tx x 0 1b 16 64 b
11.1-1.
12 bop b
· 16 1-65536 · 64 · · · · c ·
327
ESP32-S2 TRM ( 1.3)
11 (TIMG)
GoBack
11.2
11.2.1 16
TIMG_TxCONFIG_REG TIMG_Tx_USE_XTAL APB (APB_CLK) (XTAL_CLK) b 16 (TB_CLK)b16 TIMG_Tx_DIVIDER 1 65536 b TIMG_Tx_DIVIDER 0 65536bc TIMG_Tx_EN 16 b 16 b
11.2.2 64
64 TB_CLK TIMG_Tx_INCREASE b TIMG_Tx_EN b TB_CLK b bTIMG_Tx_EN TIMG_Tx_INCREASE b
64 CPU c CPU 32 b TIMG_TxUPDATE_REG 64 TIMG_TxLO_REG TIMG_TxHI_REG 32 32 b TIMG_TxUPDATE_REG TIMG_TxLO_REG TIMG_TxHI_REG CPU b
11.2.3
bc c 11.2.4 b
64 TIMG_TxALARMLO_REG TIMG_TxALARMHI_REG 32 32 b TIMG_Tx_ALARM_EN b opc b
TIMG_Tx_ALARM_EN TIMG_Tx_ALARM_EN b
11.2.4
32 32 TIMG_Tx_LOAD_LO TIMG_Tx_LOAD_HI b TIMG_Tx_LOAD_LO TIMG_Tx_LOAD_HI bb b
CPU TIMG_TxLOAD_REG b TIMG_Tx_EN b TIMG_Tx_EN b
b bTIMG_Tx_AUTORELOAD 1 b b
328
ESP32-S2 TRM ( 1.3)
11 (TIMG)
GoBack
11.2.5
CPU cb 6
· TIMG_WDT_LEVEL_INT · TIMG_WDT_EDGE_INT · TIMG_Tx_LEVEL_INT · TIMG_Tx_EDGE_INT cbc bcb TIMG_Tx_LEVEL_INT_EN TIMG_Tx_EDGE_INT_EN b b
· TIMG_Tx_INT_RAW 1b TIMG_Tx_INT_CLR b · TIMG_WDT_INT_RAW 1b TIMG_WDT_INT_CLR b · TIMG_Tx_INT_ST TIMG_Tx_INT_ENA TIMG_Tx_INT_RAW
bTIMG_Tx_INT_ST TIMG_Tx_INT_RAW b · TIMG_WDT_INT_ST TIMG_WDT_INT_ENA
TIMG_WDT_INT_RAW bTIMG_WDT_INT_ST TIMG_WDT_INT_RAW b
· TIMG_Tx_INT_ENAb · TIMG_WDT_INT_ENAb · TIMG_Tx_INT_CLR 1 TIMG_Tx_INT_RAW TIMG_Tx_INT_ST
bb
· TIMG_WDT_INT_CLR 1 TIMG_WDT_INT_RAW TIMG_WDT_INT_ST bb
11.3
11.3.1
1. b · TIMG_Tx_USE_XTAL b · TIMG_Tx_DIVIDER 16 b · TIMG_Tx_INCREASE b · TIMG_Tx_LOAD_LO TIMG_Tx_LOAD_HI TIMG_TxLOAD_REG b
2. TIMG_Tx_EN b 3. b
329
ESP32-S2 TRM ( 1.3)
11 (TIMG)
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· TIMG_TxUPDATE_REG b · TIMG_TxLO_REG TIMG_TxHI_REG b
11.3.2
1. 11.3.1 1 b 2. b
· TIMG_TxALARMLO_REG TIMG_TxALARMHI_REG b · TIMG_Tx_LEVEL_INT_EN TIMG_Tx_EDGE_INT_EN b 3. TIMG_Tx_AUTORELOAD b 4. TIMG_Tx_EN b 5. b · TIMG_Tx_INT_CLR b · TIMG_Tx_EN b
11.3.3
1. 11.3.1 1 b 2. 11.3.2 2 b 3. TIMG_Tx_AUTORELOAD TIMG_Tx_LOAD_LO
TIMG_Tx_LOAD_HIb 4. TIMG_Tx_EN b 5. cb
· TIMG_Tx_INT_CLR b · c
TIMG_TxALARMLO_REGaTIMG_TxALARMHI_REGaTIMG_Tx_LOAD_LO TIMG_Tx_LOAD_HI bb · TIMG_Tx_ALARM_EN b 6.cb · TIMG_Tx_INT_CLR b · TIMG_Tx_EN b
11.4
64 11.4-1 b 3 b
330
ESP32-S2 TRM ( 1.3)
11 (TIMG)
11.4-1. 64
TIMG0 TIMG1
PeriBUS1 PeriBUS2 PeriBUS1 PeriBUS2
0x3F41F000 0x6001F000 0x3F420000 0x60020000
GoBack
11.5
64 cb 11.4 64 b
Name 0 TIMG_T0CONFIG_REG TIMG_T0LO_REG TIMG_T0HI_REG TIMG_T0UPDATE_REG
TIMG_T0ALARMLO_REG TIMG_T0ALARMHI_REG TIMG_T0LOADLO_REG TIMG_T0LOADHI_REG TIMG_T0LOAD_REG
1 TIMG_T1CONFIG_REG TIMG_T1LO_REG TIMG_T1HI_REG TIMG_T1UPDATE_REG
TIMG_T1ALARMLO_REG TIMG_T1ALARMHI_REG TIMG_T1LOADLO_REG TIMG_T1LOADHI_REG TIMG_T1LOAD_REG
TIMG_WDTCONFIG0_REG TIMG_WDTCONFIG1_REG TIMG_WDTCONFIG2_REG TIMG_WDTCONFIG3_REG TIMG_WDTCONFIG4_REG
Description
Address Access
0
0 32
0 32
TIMG_T0LO_REG TIMG_T0HI_REG
0 32
0
0 32
0 32
TIMG_T0LOADLO_REG
TIMG_T0LOADHI_REG
0x0000 0x0004 0x0008 0x000C
0x0010 0x0014 0x0018 0x001C 0x0020
/ /
/ / / /
1
1 32
1 32
TIMG_T1LO_REG
TIMG_T1HI_REG
1 32
1
1 32
1 32
TIMG_T1LOADLO_REG
TIMG_T1LOADHI_REG
0x0024 0x0028 0x002C 0x0030
0x0034 0x0038 0x003C 0x0040 0x0044
/ /
/ / / /
0 1 2
0x0048 0x004C 0x0050 0x0054 0x0058
/ / / / /
331
ESP32-S2 TRM ( 1.3)
11 (TIMG)
Name TIMG_WDTCONFIG5_REG TIMG_WDTFEED_REG TIMG_WDTWPROTECT_REG RTC CALI TIMG_RTCCALICFG_REG TIMG_RTCCALICFG1_REG TIMG_RTCCALICFG2_REG LACT TIMG_LACTCONFIG_REG TIMG_LACTRTC_REG TIMG_LACTLO_REG TIMG_LACTHI_REG TIMG_LACTUPDATE_REG TIMG_LACTALARMLO_REG TIMG_LACTALARMHI_REG TIMG_LACTLOADLO_REG TIMG_LACTLOADHI_REG TIMG_LACTLOAD_REG TIMG_INT_ENA_TIMERS_REG TIMG_INT_RAW_TIMERS_REG TIMG_INT_ST_TIMERS_REG TIMG_INT_CLR_TIMERS_REG TIMG_TIMERS_DATE_REG TIMG_REGCLK_REG
Description 3
RTC RTC 1
LACT LACT RTC LACT LACT LACT LACT LACT LACT LACT LACT
GoBack
Address 0x005C 0x0060 0x0064
Access / /
0x0068 0x006C 0x00A8
varies varies
0x0070 0x0074 0x0078 0x007C 0x0080 0x0084 0x0088 0x008C 0x0090 0x0094
/ / / / / /
0x0098 0x009C 0x00A0 0x00A4
/
0x00F8 /
0x00FC /
332
ESP32-S2 TRM ( 1.3)
11 (TIMG)
11.6
GoBack
Register 11.1. TIMG_TxCONFIG_REG (x: 0-1) (0x0000+0x24*x)
TIMG_TTIMx_GE_TNTIMx_GIN_TCxR_EAAUSTEORELOAD
31 30 29 28
01 1
TIMG_Tx_DIVIDER 0x01
TIMG_TTIMx_GE_TDTIGMx_EGL__TEITNIVMxTE_G_LAE__LTNIANxR_TMU_ES_NEE_NXTAL
(reserved)
13 12 11 10 9 8
0
0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TIMG_Tx_USE_XTAL 1 XTAL_CLK b0 APB_CLK b(/)
TIMG_Tx_ALARM_EN 1 bb(/) TIMG_Tx_LEVEL_INT_EN 1 b(/) TIMG_Tx_EDGE_INT_EN 1 b(/) TIMG_Tx_DIVIDER x (Tx_clk) b(/) TIMG_Tx_AUTORELOAD 1 x b(/) TIMG_Tx_INCREASE 1 x b x
b(/) TIMG_Tx_EN 1 x b(/)
Register 11.2. TIMG_TxLO_REG (x: 0-1) (0x0004+0x24*x)
TIMG_Tx_LO
31
0
0x000000
Reset
TIMG_Tx_LO TIMG_TxUPDATE_REG x 32 b()
333
ESP32-S2 TRM ( 1.3)
11 (TIMG)
GoBack
Register 11.3. TIMG_TxHI_REG (x: 0-1) (0x0008+0x24*x)
TIMG_Tx_HI
31
0
0x000000
Reset
TIMG_Tx_HI TIMG_TxUPDATE_REG x 32 b()
Register 11.4. TIMG_TxUPDATE_REG (x: 0-1) (0x000C+0x24*x)
TIMG_Tx_UPDATE
(reserved)
31 30
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TIMG_Tx_UPDATE TIMG_TxUPDATE_REG 0 1b(/)
Register 11.5. TIMG_TxALARMLO_REG (x: 0-1) (0x0010+0x24*x)
TIMG_Tx_ALARM_LO
31
0x000000
TIMG_Tx_ALARM_LO x 32 b(/)
0
Reset
Register 11.6. TIMG_TxALARMHI_REG (x: 0-1) (0x0014+0x24*x)
TIMG_Tx_ALARM_HI
31
0x000000
TIMG_Tx_ALARM_HI x 32 b(/)
0
Reset
334
ESP32-S2 TRM ( 1.3)
11 (TIMG)
Register 11.7. TIMG_TxLOADLO_REG (x: 0-1) (0x0018+0x24*x)
TIMG_Tx_LOAD_LO
31
0x000000
TIMG_Tx_LOAD_LO x 32 b(/)
Register 11.8. TIMG_TxLOADHI_REG (x: 0-1) (0x001C+0x24*x)
TIMG_Tx_LOAD_HI
31
0x000000
TIMG_Tx_LOAD_HI x 32 b(/)
Register 11.9. TIMG_TxLOAD_REG (x: 0-1) (0x0020+0x24*x)
TIMG_Tx_LOAD
31
0x000000
TIMG_Tx_LOAD x b()
GoBack
0
Reset
0
Reset
0
Reset
335
ESP32-S2 TRM ( 1.3)
11 (TIMG)
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Register 11.10. TIMG_WDTCONFIG0_REG (0x0048)
TIMG_WTDITM_GE_NWDT_TISMTGG_0WDT_TISMTGG1_WDT_TISMTGG_2WTDITM_GS_TTWGIM3DGT__WEDDGT_TEI_LMEINGVTE__LWE_DNINT_TC_EPNUT_IRMEGS_EWT_DLTE_TNISMGYTGSH__TWRIMEDSGTE__TTWIFM_LDLGATES__NWHPGBRDTOOTHO_CTAP_PUMP_CROPEDUS__EETRN_EESNET_EN
(reserved)
31 30 29 28 27 26 25 24 23 22 21 20
18 17
15 14 13 12 11
0
00
0
0
0 00
0x1
0x1
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TIMG_WDT_APPCPU_RESET_EN b(/) TIMG_WDT_PROCPU_RESET_EN WDT CPU b(/) TIMG_WDT_FLASHBOOT_MOD_EN 1 , flash b(/) TIMG_WDT_SYS_RESET_LENGTH b0100 ns1200 ns2300 ns3
400 ns4500 ns5800 ns61.6 us73.2 usb(/) TIMG_WDT_CPU_RESET_LENGTH CPU b0100 ns1200 ns2300 ns3
400 ns4500 ns5800 ns61.6 us73.2 usb(/) TIMG_WDT_LEVEL_INT_EN 1 , b(/)
TIMG_WDT_EDGE_INT_EN 1 , b(/)
TIMG_WDT_STG3 3 b012 CPU3b(/) TIMG_WDT_STG2 2 b012 CPU3b(/) TIMG_WDT_STG1 1 b012 CPU3b(/) TIMG_WDT_STG0 0 b012 CPU3b(/) TIMG_WDT_EN 1 MWDT b(/)
336
ESP32-S2 TRM ( 1.3)
11 (TIMG)
GoBack
Register 11.11. TIMG_WDTCONFIG1_REG (0x004C)
TIMG_WDT_CLK_PRESCALER
(reserved)
31
16 15
0
0x01
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TIMG_WDT_CLK_PRESCALER MWDT bMWDT = MWDT * TIMG_WDT_CLK_PRESCALEb(/)
Register 11.12. TIMG_WDTCONFIG2_REG (0x0050)
TIMG_WDT_STG0_HOLD
31
0x18cba80
TIMG_WDT_STG0_HOLD MWDT 0 b(/)
0
Reset
Register 11.13. TIMG_WDTCONFIG3_REG (0x0054)
TIMG_WDT_STG1_HOLD
31
0x7ffffff
TIMG_WDT_STG1_HOLD MWDT 1 b(/)
0
Reset
337
ESP32-S2 TRM ( 1.3)
11 (TIMG)
Register 11.14. TIMG_WDTCONFIG4_REG (0x0058)
TIMG_WDT_STG2_HOLD
31
0x0fffff
TIMG_WDT_STG2_HOLD MWDT 2 b(/)
Register 11.15. TIMG_WDTCONFIG5_REG (0x005C)
TIMG_WDT_STG3_HOLD
31
0x0fffff
TIMG_WDT_STG3_HOLD MWDT 3 b(/)
Register 11.16. TIMG_WDTFEED_REG (0x0060)
TIMG_WDT_FEED
31
0x000000
TIMG_WDT_FEED MWDTb()
Register 11.17. TIMG_WDTWPROTECT_REG (0x0064)
TIMG_WDT_WKEY
31
0x50d83aa1
TIMG_WDT_WKEY b(/)
GoBack
0
Reset
0
Reset
0
Reset
0
Reset
338
ESP32-S2 TRM ( 1.3)
11 (TIMG)
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TIMG_RTC_CALI_START
31 30
0
Register 11.18. TIMG_RTCCALICFG_REG (0x0068)
TIMG_RTC_CALI_MAX 0x01
TIMG_RTTCIM_CGA_LRIT_TCRIM_DCGYA_LRIT_CC_LCKA_LSIE_LSTART_CYCLING (reserved)
16 15 14 13 12 11
0
0 0x1 1 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TIMG_RTC_CALI_START_CYCLING b(/) TIMG_RTC_CALI_CLK_SEL b0RTC_CLKb1RTC20M_D256_CLKb2
XTAL32K_CLKb(/) TIMG_RTC_CALI_RDY b() TIMG_RTC_CALI_MAX b(/) TIMG_RTC_CALI_START b(/)
Register 11.19. TIMG_RTCCALICFG1_REG (0x006C)
TIMG_RTC_CALI_VALUE
(reserved)
TIMG_RTC_CALI_CYCLING_DATA_VLD
31
76
10
0x00000
0 0 0 0 0 0 0 Reset
TIMG_RTC_CALI_CYCLING_DATA_VLD b()
TIMG_RTC_CALI_VALUE TIMG_RTC_CALI_MAX XTAL_CLK b()
339
ESP32-S2 TRM ( 1.3)
11 (TIMG)
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Register 11.20. TIMG_RTCCALICFG2_REG (0x00A8)
TIMG_RTC_CALI_TIMEOUT_THRES
TIMG_RTC_CALI_(rTeIsMeErvOeUdTTI)M_RGS_TR_TCCN_TCALI_TIMEOUT
31
76
32
10
0x1ffffff
0x3
0 0 0 Reset
TIMG_RTC_CALI_TIMEOUT RTC b()
TIMG_RTC_CALI_TIMEOUT_RST_CNT b(/)
TIMG_RTC_CALI_TIMEOUT_THRES RTC b b(/)
TIMG_TLIMACGT_T_LIMEANCGT__LIANCCTR_EAAUSTEORELOAD
31 30 29 28
01 1
Register 11.21. TIMG_LACTCONFIG_REG (0x0070)
TIMG_LACT_DIVIDER 0x01
TIMG_TLIMACGT_T_LIMEADCGGT_T_ELIML_AEICGNVT_TTE_LI_LMAAE_LCGNIANT_TR_TLIMM_LAAECG_CNTE_T__NLIMECANPCGST_T_L_RAETCNCT__OUNSELY_R(EreFsTeICrvKed)
13 12 11 10 9 8 7 6 5
0
0 0 0 1 1 0 0 0 0 0 0 0 0 Reset
TIMG_LACT_USE_REFTICK b(/) TIMG_LACT_RTC_ONLY b(/) TIMG_LACT_CPST_EN b(/) TIMG_LACT_LAC_EN b(/) TIMG_LACT_ALARM_EN b(/) TIMG_LACT_LEVEL_INT_EN b(/) TIMG_LACT_EDGE_INT_EN b(/) TIMG_LACT_DIVIDER b(/) TIMG_LACT_AUTORELOAD b(/) TIMG_LACT_INCREASE b(/) TIMG_LACT_EN b(/)
340
ESP32-S2 TRM ( 1.3)
11 (TIMG)
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Register 11.22. TIMG_LACTRTC_REG (0x0074)
TIMG_LACT_RTC_STEP_LEN
(reserved)
31
65
0
0x00000
0 0 0 0 0 0 Reset
TIMG_LACT_RTC_STEP_LEN b(/)
Register 11.23. TIMG_LACTLO_REG (0x0078)
TIMG_LACT_LO
31
0x000000
TIMG_LACT_LO b()
0
Reset
Register 11.24. TIMG_LACTHI_REG (0x007C)
TIMG_LACT_HI
31
0x000000
TIMG_LACT_HI b()
0
Reset
Register 11.25. TIMG_LACTUPDATE_REG (0x0080)
TIMG_LACT_UPDATE
31
0x000000
TIMG_LACT_UPDATE b()
0
Reset
341
ESP32-S2 TRM ( 1.3)
11 (TIMG)
Register 11.26. TIMG_LACTALARMLO_REG (0x0084)
TIMG_LACT_ALARM_LO
31
0x000000
TIMG_LACT_ALARM_LO b(/)
GoBack
0
Reset
Register 11.27. TIMG_LACTALARMHI_REG (0x0088)
TIMG_LACT_ALARM_HI
31
0x000000
TIMG_LACT_ALARM_HI b(/)
0
Reset
Register 11.28. TIMG_LACTLOADLO_REG (0x008C)
TIMG_LACT_LOAD_LO
31
0x000000
TIMG_LACT_LOAD_LO b(/)
0
Reset
Register 11.29. TIMG_LACTLOADHI_REG (0x0090)
TIMG_LACT_LOAD_HI
31
0x000000
TIMG_LACT_LOAD_HI b(/)
0
Reset
342
ESP32-S2 TRM ( 1.3)
11 (TIMG)
Register 11.30. TIMG_LACTLOAD_REG (0x0094)
TIMG_LACT_LOAD
31
0x000000
TIMG_LACT_LOAD b()
GoBack
0
Reset
Register 11.31. TIMG_INT_ENA_TIMERS_REG (0x0098)
(reserved)
TIMG_TLIMACGT_T_WIMINDGTT__T_TIIEMN1N_TGAI_N_ETTN0_AE_NINAT_ENA
31
43 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TIMG_Tx_INT_ENA TIMG_Tx_INT b(/) TIMG_WDT_INT_ENA TIMG_WDT_INT b(/) TIMG_LACT_INT_ENA TIMG_LACT_INT b(/)
Register 11.32. TIMG_INT_RAW_TIMERS_REG (0x009C)
(reserved)
TIMG_TLIMACGT_T_WIMINDGTT__T_TIIRMN1A_TGWI_N_RTTA0_WR_AINWT_RAW
31
43 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TIMG_Tx_INT_RAW TIMG_Tx_INT b() TIMG_WDT_INT_RAW TIMG_WDT_INT b() TIMG_LACT_INT_RAW TIMG_LACT_INT b()
343
ESP32-S2 TRM ( 1.3)
11 (TIMG)
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Register 11.33. TIMG_INT_ST_TIMERS_REG (0x00A0)
(reserved)
TIMG_TLIMACGT_T_WIMINDGTT__T_TIISMN1T_TGI_N_STTT0_S_TINT_ST
31
43 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TIMG_Tx_INT_ST TIMG_Tx_INT b() TIMG_WDT_INT_ST TIMG_WDT_INT b() TIMG_LACT_INT_ST TIMG_LACT_INT b()
Register 11.34. TIMG_INT_CLR_TIMERS_REG (0x00A4)
(reserved)
TIMG_TLIMACGT_T_WIMINDGTT__T_TICIMN1L_TGRI_N_CTTL0_RC_LINRT_CLR
31
43 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TIMG_Tx_INT_CLR TIMG_Tx_INT b() TIMG_WDT_INT_CLR TIMG_WDT_INT b() TIMG_LACT_INT_CLR TIMG_LACT_INT b()
(reserved)
31
28 27
0000
Register 11.35. TIMG_TIMERS_DATE_REG (0x00F8)
TIMG_TIMERS_DATE 0x1907261
TIMG_TIMERS_DATE b(/)
0
Reset
344
ESP32-S2 TRM ( 1.3)
11 (TIMG)
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Register 11.36. TIMG_REGCLK_REG (0x00FC)
TIMG_CLK_EN
31 30
(reserved)
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TIMG_CLK_EN b1a 0a b(/)
345
ESP32-S2 TRM ( 1.3)
12 (WDT)
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12 (WDT)
12.1
bcb/ cb a/b ESP32-S2 c MWDTRTC c RTC RWDTbc RWDT baCPU ab RWDT RTC b b flash RWDT MWDT b 11 (TIMG)b
12.2
· ba · c MWDT RWDTcaCPU a · 32 · RWDT MWDT · Flash SPI flash
12.3
12.3.1 32
32 bAPB 16 MWDT b RWDT RTC c 32 kHzbMWDT 16 TIMG_WDTCONFIG1_REG TIMG_WDT_CLK_PRESCALER b
346
ESP32-S2 TRM ( 1.3)
12 (WDT)
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MWDT RWDT TIMG_WDT_EN RTC_CNTL_WDT_EN b 32 1cb 0b 0 0b TIMG_WDTFEED_REG RTC_CNTL_RTC_WDT_FEED MDWT RWDT b
12.3.2
b 0bMWDT RWDT c 0 3b c 0 3 0bMWDT TIMG_WDTCONFIGi_REG ci 2 5RWDT RTC_CNTL_WDT_STGj_HOLDcj 0 3 bRWDT 0 (Thold) eFuse EFUSE_WDT_DELAY_SEL RTC_CNTL_WDT_STG0_HOLD
Thold = RTC_CNTL_WDT_STG0_HOLD « cEFUSE_WDT_DELAY_SEL + 1
· b
· CPU CPU b
· MWDT bRTC b
· RTC b RWDT b
· b
MWDT TIMG_WDTCONFIG0_REG bRWDT RTC_CNTL_WDTCONFIG0_REG b
12.3.3
/c bMWDT RWDT b
cMWDT TIMG_WDT_WKEYRWDT RTC_CNTL_WDT_WKEYb 0x50D83AA1 b 0x50D83AA1c b
1. 0x50D83AA1 b
2. b
3. 0x50D83AA1 b
347
ESP32-S2 TRM ( 1.3)
12 (WDT)
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12.3.4 Flash
flash 0cTIMG0 MWDT RWDT bMWDT 0 cbRWDT 0 c RTCb TIMG_WDT_FLASHBOOT_MOD_EN RTC_CNTL_WDT_FLASHBOOT_MOD_EN MWDT RWDT flash b MWDT RWDTb
12.4
(SWD) bSWD 100 ms WD_INTR b SWD SWD SWD_RSTB b
12.4.1
SWD · · SWD · SWD SWD
12.4.2 SWD
12.4.2.1
12.4-1.
348
ESP32-S2 TRM ( 1.3)
12 (WDT)
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12.4.2.2
· SWD SWD b · SWD CPU ULP-RISC-V b · CPU RTC_CNTL_SWD_FEED ULP-RISC-V b · CPU RTC_CNTL_SWD_WKEY 0x8F1D312A SWD b SWDb · RTC_CNTL_SWD_AUTO_FEED_EN 1SWD CPU ULP-RISC-V SWDb
· RTC_CNTL_RESET_CAUSE_PROCPU[5:0] CPU b RTC_CNTL_RESET_CAUSE_PROCPU[5:0] == 0x12 SWD b · RTC_CNTL_SWD_RST_FLAG_CLR SWD b
12.5
MWDT 11 (TIMG) bRWDT SWD RTC 9 RTC b
349
ESP32-S2 TRM ( 1.3)
13 XTAL32K (XTWDT)
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13
XTAL32K (XTWDT)
13.1
ESP32-S2 XTAL32K XTAL32K_CLK XTAL32K_CLK RTC b XTAL32K_CLK RTC XTAL32K_CLK XTAL32K RTC RC_SLOW_CLK ( Deep-sleep CPU) XTAL32K_CLKb
13.1-1. XTAL32K
13.2
13.2.1 XTAL32K
XTAL32K XTAL32K_CLK CPU CPUb
13.2.2 BACKUP32K_CLK
XTAL32K XTAL32K_CLK RC_SLOW_CLK BACKUP32K_CLK ( 32KHz ) XTAL32K_CLK RTC b
350
ESP32-S2 TRM ( 1.3)
13 XTAL32K (XTWDT)
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13.3
13.3.1
1. RTC_CNTL_XTAL32K_WDT_ENXTAL32K XTAL_32K RTC_CNTL_XTAL32K_WDT_TIMEOUT /b
2. XTAL32K BACKUP32K_CLK RTC RTC ( RTC_TIMER ) b 13.3.2 BACKUP32K_CLK b
3. RTC_CNTL_XPD_XTAL_32K XTAL32K_CLK XPD XTAL32K_CLK RTC_CNTL_XTAL32K_WDT_EN 0 RTC BACKUP32K_CLK XTAL32K_CLKb Deep-sleep XTAL32K CPUb
13.3.2 BACKUP32K_CLK
RC_SLOW_CLK BACKUP32K_CLK RTC_TIMER RTC RC_SLOW_CLKc9 BACKUP32K_CLK b
RC_SLOW_CLK f_rc_slow_clk ckHz8 x0x1x2x3x4x5x6 x7b S = x0 + x1 + x2 + x3 + x4 + x5 + x6 + x7b
S = f _rc_slow_clk × (4/32) M + 1 xn M (0 n 7)
M = f _rc_slow_clk/32/2
xn bM S b x0 ~x7 4 RTC_CNTL_XTAL32K_CLK_FACTOR 32 b RC_SLOW_CLK 163 kHz f _rc_slow_clk = 163S = 20, M = 2 {x0, x1, x2, x3, x4, x5, x6, x7} = {2, 3, 2, 3, 2, 3, 2, 3}BACKUP32K_CLK 32.6 kHzb
351
ESP32-S2 TRM ( 1.3)
14 (PMS)
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14 (PMS)
14.1
ESP32-S2 ab b
14.2
· SRAM RTC FAST SRAM RTC SLOW SRAM
· MMU
14.3
14.3.1
ROMSRAMRTC FASTRTC SLOWb
· ROM 128 KB 64 KB b
· SRAM 320 KB 4 8 KB 18 16 KB Block 0 ~ 21 Block 14.3-1 14.3.1.1a14.3.1.2a14.3.1.3b 4 8 KB Block 0 ~ 3 16 KB Block 4 ~ 21 ca Block 4 ~ 5 b
· RTC FAST Memory ab
· RTC SLOW Memory ab
ESP32-S2 b
14.3-1. SRAM Block
SRAM Block Block 0 Block 1
0x0000 0x2000
0x1FFF 0x3FFF
352
ESP32-S2 TRM ( 1.3)
14 (PMS)
SRAM Block Block 2 Block 3 Block 4 Block 5 Block 6 Block 7 Block 8 Block 9 Block 10 Block 11 Block 12 Block 13 Block 14 Block 15 Block 16 Block 17 Block 18 Block 19 Block 20 Block 21
0x4000 0x6000 0x8000 0xC000 0x10000 0x14000 0x18000
0x1C000 0x20000 0x24000 0x28000 0x2C000 0x30000 0x34000 0x38000 0x3C000 0x40000 0x44000 0x48000 0x4C000
0x5FFF 0x7FFF 0xBFFF 0xFFFF 0x13FFF 0x17FFF 0x1BFFF 0x1FFFF
0x23FFF 0x27FFF 0x2BFFF 0x2FFFF 0x33FFF 0x37FFF 0x3BFFF 0x3FFFF 0x43FFF 0x47FFF 0x4BFFF 0x4FFFF
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14.3.1.1 IBUS
IBUS 0x4002_0000 ~ 0x4007_1FFF SRAM aRTC FAST Memorybb
IBUS PMS_PRO_IRAM0_LOCK 1 b PMS_PRO_IRAM0_LOCK 1 b CPU PMS_PRO_IRAM0_LOCK 0b
SRAM
CPU IBUS SRAM R/W/Xc// 0x4002_0000b IBUS SRAM Block b 14.3-2 b
14.3-2. IBUS SRAM
PMS_PRO_IRAM0_1_REG
PMS_PRO_IRAM0_2_REG
[11:9] [8:6] [5:3] [2:0]
[22:20]
IBUS SRAM Block 3 c W/R/X IBUS SRAM Block 2 c W/R/X IBUS SRAM Block 1 c W/R/X IBUS SRAM Block 0 c W/R/ X IBUS SRAM Block 4 ~ 21 c W/R/X
353
ESP32-S2 TRM ( 1.3)
14 (PMS)
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[19:17] [16:0]*
IBUS SRAM Block 4 ~ 21 c W/R/X IBUS SRAM Block 4 ~ 21 0x4000_0000bb
* 32 + ×4b 0x10000 PMS_PRO_IRAM0_2_REG [16:0] IBUS SRAM Block 4 ~ 21 0x4004_0000b IBUS DBUS0 SRAM Block 0 ~ 5 b
CPU IBUS SRAM IBUS SRAM Block5 CPU IBUS Block b
CPU b
·
· b
IBUS SRAM bb bb
RTC FAST Memory
CPU IBUS RTC FAST Memory R/W/X b RTC FAST ab 14.3-3 b
14.3-3. IBUS RTC FAST
PMS_PRO_IRAM0_3_REG
[16:14] [13:11] [10:0]
IBUS RTC FAST c W/ R/X IBUS RTC FAST c W/ R/X IBUS RTC FAST 0x4007_0000bb
CPU IBUS RTC FAST b IBUS RTC FAST SRAM bb bb
14.3.1.2 DBUS0
CPU DBUS0 0x3FFB_0000 ~ 0x3FFF_FFFF 0x3FF9_E000 ~ 0x3FF9_FFFF SRAM aRTC FAST Memoryb
354
ESP32-S2 TRM ( 1.3)
14 (PMS)
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b
DBUS0 PMS_PRO_DRAM0_LOCK 1 b PMS_PRO_DRAM0_LOCK 1b CPU PMS_PRO_DRAM0_LOCK 0b
SRAM
CPU DBUS0 SRAM R/W 0x3FFB_0000b DBUS0 SRAM Block b 14.3-4 b
14.3-4. DBUS0 SRAM
PMS_PRO_DRAM0_1_REG
[28:27]
[26:25]
[24:8]
[7:6] [5:4] [3:2] [1:0]
DBUS0 SRAM Block 4 ~ 21 c W/R DBUS0 SRAM Block 4 ~ 21 c W/R DBUS0 SRAM Block 4 ~ 21 0x3FFB_0000b 14.3.1.1 b DBUS0 SRAM Block3 c W/R DBUS0 SRAM Block2 c W/R DBUS0 SRAM Block1 c W/R DBUS0 SRAM Block0 c W/R
CPU DBUS0 SRAM b DBUS0 SRAM a caab bb b
RTC FAST Memory
CPU DBUS0 RTC FAST Memory R/W b RTC FAST ab 14.3-5 b
14.3-5. DBUS0 RTC FAST
PMS_PRO_DRAM0_2_REG
[14:13] [12:11]
[10:0]
DBUS0 RTC FAST c W/R DBUS0 RTC FAST c W/R DBUS0 RTC FAST 0x3FF9_E000b 14.3.1.1 b
355
ESP32-S2 TRM ( 1.3)
14 (PMS)
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CPU DBUS0 RTC FAST b DBUS0 RTC FAST SRAM acaacaab bb b
14.3.1.3 DMA
ESP32-S2 DMA SRAM 3 Internal DMACopy DMA RXcCopy DMA TXc 0x3FFB_00000x3FFB_0000 ~ 0x3FFF_FFFFb DMA SRAM Block b 14.3-6 XX APBTX RX Internal DMA, TX Copy DMA RX Copy DMA b DMA 2 DMA (DMA)b
DMA PMS_DMA_XX_I_LOCK 1 b PMS_DMA_XX_I_LOCK 1 b CPU PMS_DMA_XX_I_LOCK 0b
14.3-6. DMA SRAM
PMS_DMA_XX_I_1_REG
[28:27]
[26:25]
[24:8]
[7:6] [5:4] [3:2] [1:0]
DMA SRAM Block 4 ~ 21 c W/R DMA SRAM Block 4 ~ 21 c W/R DMA SRAM Block 4 ~ 21 0x3FFB_0000b 14.3.1.1 b DMA SRAM Block3 c W/R DMA SRAM Block2 c W/R DMA SRAM Block1 c W/R DMA SRAM Block0 c W/R
DMA SRAM b Internal DMATX Copy DMA RX Copy DMA SRAM bb bb
14.3.1.4 PeriBus1
CPU PeriBus1 0x3F40_0000 ~ 0x3F4F_FFFF RTC SLOW SRAMbPeriBus1 RTC SLOW /b/b
PeriBus1 0x3F40_0000 ~ 0x3F4B_FFFF b
CPU PeriBus1 FIFO b FIFO FIFO c 14.3-7 b 4
356
ESP32-S2 TRM ( 1.3)
14 (PMS)
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PMS_PRO_DPORT_2~5_REGbPeriBus1 b 14.3-8 b
14.3-7. FIFO
ADDR_RTCSLOW ADDR_FIFO_UART0 ADDR_FIFO_UART1 ADDR_FIFO_UART2 ADDR_FIFO_I2S0 ADDR_FIFO_RMT_CH0 ADDR_FIFO_RMT_CH1 ADDR_FIFO_RMT_CH2 ADDR_FIFO_RMT_CH3 ADDR_FIFO_I2C_EXT0 ADDR_FIFO_I2C_EXT1 ADDR_FIFO_USB_0 ADDR_FIFO_USB_1_L ADDR_FIFO_USB_1_H
FIFO 0x6002_1000 0x6000_0000 0x6001_0000 0x6002_E000 0x6000_F004 0x6001_6000 0x6001_6004 0x6001_6008 0x6001_600C 0x6001_301C 0x6002_701C 0x6008_0020 0x6008_1000 0x6009_0FFF
PeriBus1 PMS_PRO_DPORT_LOCK 1 b PMS_PRO_DPORT_LOCK 1b CPU PMS_PRO_DPORT_LOCK 0b
14.3-8. PeriBus1
PMS_PRO_DPORT_1_REG
[19:16] [15:14] [13:12]
[11:1]
[0] PMS_PRO_DPORT_2_REG [17:0] PMS_PRO_DPORT_3_REG [17:0] PMS_PRO_DPORT_4_REG [17:0] PMS_PRO_DPORT_5_REG [17:0]
FIFO PeriBus1 RTC SLOW c W/R PeriBus1 RTC SLOW c W/R PeriBus1 RTC SLOW 0x3F42_1000 b 14.3.1.1 b PeriBus1 0x3F40_0000 ~ 0x3F4B_FFFF 0 PeriBus1 PMS_PRO_DPORT_RESERVE_FIFO_VALID [16] 1 PeriBus1 PMS_PRO_DPORT_RESERVE_FIFO_VALID [17] 2 PeriBus1 PMS_PRO_DPORT_RESERVE_FIFO_VALID [18] 3 PeriBus1 PMS_PRO_DPORT_RESERVE_FIFO_VALID [19]
357
ESP32-S2 TRM ( 1.3)
14 (PMS)
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PeriBus1 RTC SLOW Memory b PeriBus1 RTC SLOW Memory acaab bb b
14.3.1.5 PeriBus2
PeriBus2 0x5000_0000 ~ 0x5000_1FFF 0x6000_0000 ~ 0x600B_FFFF RTC SLOW ab
PeriBus2 RTC SLOW Memory R/W/X bPeriBus2 RTC SLOW Memory RTCSlow_0aRTCSlow_1b CPU b 14.3-9 b
PeriBus2 bb
PeriBus2 PMS_PRO_AHB_LOCK 1 b PMS_PRO_AHB_LOCK 1b CPU PMS_PRO_AHB_LOCK 0b
14.3-9. PeriBus2 RTC SLOW
PMS_PRO_AHB_1_REG
PMS_PRO_AHB_2_REG
[16:14] [13:11] [10:0] [16:14] [13:11] [10:0]
PeriBus2 RTCSlow_0 c W/R/X PeriBus2 RTCSlow_0 c W/R/X PeriBus2 RTCSlow_0 0x5000_0000b 14.3.1.1 b PeriBus2 RTCSlow_1 c W/R/X PeriBus2 RTCSlow_1 c W/R/X PeriBus2 RTCSlow_1 0x6002_1000b 14.3.1.1 b
CPU PeriBus2 RTCSlow_0 RTCSlow_1 b PeriBus2 bb bb
14.3.1.6 Cache
SRAM Block 0 ~ 3 Icache Dcache b Icache Dcache 16 KB 2 BlockbIcache Dcache 8 KB "_H" "_L" b
358
ESP32-S2 TRM ( 1.3)
14 (PMS)
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PMS_PRO_CACHE_1_REG SRAM Block 0 ~ 3 Icache_H, Icache_L, Dcache_H Dcache_L b FIELD PMS_PRO_CACHE_1_REG PMS_PRO_CACHE_CONNECTb
14.3-10. PMS_PRO_CACHE_1_REG
SRAM Block 0-3 Block 0 Block 1 Block 2 Block 3
Dcache_H FIELD[3] FIELD[7] FIELD[11] FIELD[15]
Dcache_L FIELD[2] FIELD[6] FIELD[10] FIELD[14]
Icache_H FIELD[1] FIELD[5] FIELD[9] FIELD[13]
Icache_L FIELD[0] FIELD[4] FIELD[8] FIELD[12]
· Block Dcache_HaDcache_LaIcache_HaIcache_L 1b
· Dcache_HaDcache_LaIcache_HaIcache_L Block 1b
· cache CPU cache CPU b
14.3.1.7
ESP32-S2 Trace memory CPU ab PMS_PRO_TRACE_1 Trace memory b PMS_PRO_TRACE_LOCK 1 b PMS_PRO_TRACE_LOCK 1b CPU PMS_PRO_TRACE_LOCK 0b Trace memory PMS_OCCUPY_3 SRAM Block 4 ~ 21 Block Trace memory c Block CPU b PMS_OCCUPY_LOCK b 1 b PMS_OCCUPY_LOCK 1b CPU PMS_OCCUPY_LOCK 0b SRAM Block Trace Memory CPU IBUS, DBUS DMA Blockb
14.3.2
CPU SPI1aEDMA cache flash SRAMbSPI1 EDMA cache b
14.3.2.1 Cache MMU
Cache MMU cache EDMA b cache EDMA MMUb cache cache MMU b EDMA SRAM EDMA MMU SRAM b
359
ESP32-S2 TRM ( 1.3)
14 (PMS)
MMU
SRAM
Flash Invalid Page number
[16]
[15] [14] [13:0]
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14.3-11. MMU
, cache/ EDMA flash SRAMb 15 1 flash 16 1 SRAMb 15a16 1b
MMU 0 b op 64 KBb cache/EDMA b
cache EDMA MMU MMU MMU b
14.3.2.2
(flash + SRAM) 64 KB 8 (4+4) b W/R/X bb
8 8 flash SRAM 4 b 3 :
1. : SYSCON_X_ACE_n_ATTR_REG 3 W/R/F
2. : SYSCON_X_ACE_n_ADDR_REG
3. : SYSCON_X_ACE_n_SIZE_REG 64 KB b
oXp flash SRAMonp 0 ~ 3b flash 4 1 GB SRAM 4 1 GBb
CPU CPU b CPU b b
Cache acache cache cache W/R/X b cache b cache b cache R/F cache cache b b
CPU cache CPU CPU CPU b b
b b
14.3.3
ESP32-S2 bPeriBus1 PeriBus2 b IN EX b
360
ESP32-S2 TRM ( 1.3)
14 (PMS)
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14.3-12.
PeriBus2
PeriBus1 0x3F40_0000 - 0x3F4B_FFFF
PeriBus1 0x3F4C_0000 - 0x3F4F_FFFF
0xXXXX_XXX0 0xXXXX_XXX1 0xXXXX_XXX2 0xXXXX_XXX0 0xXXXX_XXX1 0xXXXX_XXX2 0xXXXX_XXX0 0xXXXX_XXX1 0xXXXX_XXX2
IN IN
IN
IN IN
IN IN
IN EX EX IN IN EX
IN EX EX IN IN EX
IN IN
IN IN IN IN IN IN IN IN
IN EX EX IN IN EX
IN EX EX IN IN EX
14.4
14.4-1 b 3 b 14.4-1.
PeriBUS1
0x3F4C1000
14.5
cb 14.4 b
361
ESP32-S2 TRM ( 1.3)
14 (PMS)
PMS_PRO_IRAM0_0_REG PMS_PRO_DRAM0_0_REG PMS_PRO_DPORT_0_REG PMS_PRO_AHB_0_REG PMS_PRO_TRACE_0_REG PMS_PRO_CACHE_0_REG PMS_DMA_APB_I_0_REG PMS_DMA_RX_I_0_REG PMS_DMA_TX_I_0_REG PMS_CACHE_SOURCE_0_REG PMS_APB_PERIPHERAL_0_REG PMS_OCCUPY_0_REG PMS_CACHE_TAG_ACCESS_0_REG PMS_CACHE_MMU_ACCESS_0_REG PMS_CLOCK_GATE_REG_REG PMS_PRO_IRAM0_1_REG PMS_PRO_IRAM0_2_REG PMS_PRO_IRAM0_3_REG PMS_PRO_DRAM0_1_REG PMS_PRO_DRAM0_2_REG PMS_PRO_DPORT_1_REG PMS_PRO_DPORT_2_REG PMS_PRO_DPORT_3_REG PMS_PRO_DPORT_4_REG PMS_PRO_DPORT_5_REG PMS_PRO_AHB_1_REG PMS_PRO_AHB_2_REG PMS_PRO_TRACE_1_REG PMS_PRO_CACHE_1_REG PMS_DMA_APB_I_1_REG PMS_DMA_RX_I_1_REG PMS_DMA_TX_I_1_REG PMS_APB_PERIPHERAL_1_REG PMS_OCCUPY_1_REG PMS_OCCUPY_3_REG PMS_CACHE_TAG_ACCESS_1_REG PMS_CACHE_MMU_ACCESS_1_REG PMS_PRO_IRAM0_4_REG PMS_PRO_IRAM0_5_REG PMS_PRO_DRAM0_3_REG
IBUS 0 DBUS 0 PeriBus1 0 PeriBus2 0 Trace memory 0 Cache 0 DMA 0 RX Copy DMA 0 TX Copy DMA 0 Cache 0 0 0 Cache 0 Cache MMU 0
IBUS 1 IBUS 2 IBUS 3 DBUS 1 DBUS 2 PeriBus1 1 PeriBus1 2 PeriBus1 3 PeriBus1 4 PeriBus1 5 PeriBus2 1 PeriBus2 2 Trace memory 1 Cache 1 DMA 1 RX Copy DMA 1 TX Copy DMA 1 1 1 3 Cache 1 Cache MMU 1
IBUS 4 IBUS DBUS 3
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0x0010 0x0028 0x003C 0x005C 0x0070 0x0078 0x008C 0x009C 0x00AC 0x00C4 0x00CC 0x00D4 0x00E4 0x00EC 0x0104
/ / / / / / / / / / / / / / /
0x0014 0x0018 0x001C 0x002C 0x0030 0x0040 0x0044 0x0048 0x004C 0x0050 0x0060 0x0064 0x0074 0x007C 0x0090 0x00A0 0x00B0 0x00D0 0x00D8 0x00E0 0x00E8 0x00F0
/ / / / / / / / / / / / / / / / / / / / / /
0x0020 0x0024 0x0034
362
ESP32-S2 TRM ( 1.3)
14 (PMS)
PMS_PRO_DRAM0_4_REG PMS_PRO_DPORT_6_REG PMS_PRO_DPORT_7_REG PMS_PRO_AHB_3_REG PMS_PRO_AHB_4_REG PMS_PRO_CACHE_2_REG PMS_PRO_CACHE_3_REG PMS_PRO_CACHE_4_REG PMS_DMA_APB_I_2_REG PMS_DMA_APB_I_3_REG PMS_DMA_RX_I_2_REG PMS_DMA_RX_I_3_REG PMS_DMA_TX_I_2_REG PMS_DMA_TX_I_3_REG PMS_APB_PERIPHERAL_INTR_REG PMS_APB_PERIPHERAL_STATUS_REG PMS_CPU_PERIPHERAL_INTR_REG PMS_CPU_PERIPHERAL_STATUS_REG PMS_DATE
DBUS PeriBus1 6 PeriBus1 PeriBus2 3 PeriBus2 Cache 2 Icache Dcache DMA 2 DMA RX Copy DMA 2 RX Copy DMA TX Copy DMA 2 TX Copy DMA PeriBus2 PeriBus2 PeriBus1 PeriBus1
b
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0x0038 0x0054 0x0058 0x0068 0x006C 0x0080 0x0084 0x0088 0x0094 0x0098 0x00A4 0x00A8 0x00B4 0x00B8 0x00F4 0x00F8 0x00FC 0x0100
0x0FFC /
14.6
Register 14.1. PMS_PRO_IRAM0_0_REG (0x0010)
(reserved)
PMS_PRO_IRAM0_LOCK
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PMS_PRO_IRAM0_LOCK b 1 IBUS bc/
363
ESP32-S2 TRM ( 1.3)
14 (PMS)
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Register 14.2. PMS_PRO_DRAM0_0_REG (0x0028)
(reserved)
PMS_PRO_DRAM0_LOCK
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PMS_PRO_DRAM0_LOCK b 1 DBUS0 bc/
Register 14.3. PMS_PRO_DPORT_0_REG (0x003C)
(reserved)
PMS_PRO_DPORT_LOCK
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PMS_PRO_DPORT_LOCK b 1 PeriBus1 bc/
Register 14.4. PMS_PRO_AHB_0_REG (0x005C)
(reserved)
PMS_PRO_AHB_LOCK
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PMS_PRO_AHB_LOCK b 1 PeriBus2 bc/
364
ESP32-S2 TRM ( 1.3)
14 (PMS)
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Register 14.5. PMS_PRO_TRACE_0_REG (0x0070)
(reserved)
PMS_PRO_TRACE_LOCK
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PMS_PRO_TRACE_LOCK b 1 Trace memory cb/
Register 14.6. PMS_PRO_CACHE_0_REG (0x0078)
(reserved)
PMS_PRO_CACHE_LOCK
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PMS_PRO_CACHE_LOCK b 1 cache bc/
Register 14.7. PMS_DMA_APB_I_0_REG (0x008C)
(reserved)
PMS_DMA_APB_I_LOCK
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PMS_DMA_APB_I_LOCK b 1 DMA bc/
365
ESP32-S2 TRM ( 1.3)
14 (PMS)
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Register 14.8. PMS_DMA_RX_I_0_REG (0x009C)
(reserved)
PMS_DMA_RX_I_LOCK
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PMS_DMA_RX_I_LOCK b 1 RX Copy DMA bc/
Register 14.9. PMS_DMA_TX_I_0_REG (0x00AC)
(reserved)
PMS_DMA_TX_I_LOCK
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PMS_DMA_TX_I_LOCK b 1 TX Copy DMA bc/
Register 14.10. PMS_CACHE_SOURCE_0_REG (0x00C4)
(reserved)
PMS_CACHE_SOURCE_LOCK
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PMS_CACHE_SOURCE_LOCK b 1 cache bc/
366
ESP32-S2 TRM ( 1.3)
14 (PMS)
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Register 14.11. PMS_APB_PERIPHERAL_0_REG (0x00CC)
(reserved)
PMS_APB_PERIPHERAL_LOCK
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PMS_APB_PERIPHERAL_LOCK b 1 TX Copy DMA bc/
Register 14.12. PMS_OCCUPY_0_REG (0x00D4)
(reserved)
PMS_OCCUPY_LOCK
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PMS_OCCUPY_LOCK b 1 bc/
Register 14.13. PMS_CACHE_TAG_ACCESS_0_REG (0x00E4)
(reserved)
PMS_CACHE_TAG_ACCESS_LOCK
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PMS_CACHE_TAG_ACCESS_LOCK b 1 cache bc/
367
ESP32-S2 TRM ( 1.3)
14 (PMS)
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Register 14.14. PMS_CACHE_MMU_ACCESS_0_REG (0x00EC)
(reserved)
PMS_CACHE_MMU_ACCESS_LOCK
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PMS_CACHE_MMU_ACCESS_LOCK b 1 cache MMU bc/
Register 14.15. PMS_CLOCK_GATE_REG_REG (0x0104)
(reserved)
PMS_CLK_EN
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset
PMS_CLK_EN bc/
368
ESP32-S2 TRM ( 1.3)
14 (PMS)
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Register 14.16. PMS_PRO_IRAM0_1_REG (0x0014)
(reserved)
PMS_PPMROS__PPIRMRAOSM__P0PIRM_RASOSMR__PA0PIRMM_RASOS_MR__3PA0PI_RMM_WRASOS_MR__3PA0PI_RMM_RRASOS_MR__3PA0PI_RMM_RFASOS_MR__2PA0PI_RMM_RWASOS_MR__2PA0PI_RMM_RRASOS_MR__2PA0PI_RMM_RFASOS_MR_1_P_A0PIWRMM_RASOS_MR_1__A0PIRRM_RASO_MR1__A0IRFM_AS_MR0A0_M_WS_R0A_MR_0_F
31
12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 Reset
PMS_PRO_IRAM0_SRAM_0_F 1 IBUS SRAM Block 0 bc/
PMS_PRO_IRAM0_SRAM_0_R 1 IBUS SRAM Block 0 bc/ PMS_PRO_IRAM0_SRAM_0_W 1 IBUS SRAM Block 0 bc/ PMS_PRO_IRAM0_SRAM_1_F 1 IBUS SRAM Block 1 bc/
PMS_PRO_IRAM0_SRAM_1_R 1 IBUS SRAM Block 1 bc/ PMS_PRO_IRAM0_SRAM_1_W 1 IBUS SRAM Block 1 bc/ PMS_PRO_IRAM0_SRAM_2_F 1 IBUS SRAM Block 2 bc/
PMS_PRO_IRAM0_SRAM_2_R 1 IBUS SRAM Block 2 bc/ PMS_PRO_IRAM0_SRAM_2_W 1 IBUS SRAM Block 2 bc/ PMS_PRO_IRAM0_SRAM_3_F 1 IBUS SRAM Block 3 bc/
PMS_PRO_IRAM0_SRAM_3_R 1 IBUS SRAM Block 3 bc/ PMS_PRO_IRAM0_SRAM_3_W 1 IBUS SRAM Block 3 bc/
369
ESP32-S2 TRM ( 1.3)
14 (PMS)
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Register 14.17. PMS_PRO_IRAM0_2_REG (0x0018)
(reserved)
PMS_PPMROS__PPIRMRAOSM__P0PIRM_RASOSMR__PA0PIRMM_RASOS_MR__4PA0P_IRMM_RHASOS__MR_W_4A0P_IRM_RHASO__MR_R4A0_IRM_HAS__MRF4A0_M_LS__WR4A_ML__R4_L_F
31
23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0 01 1 1 1 1 1
PMS_PRO_IRAM0_SRAM_4_SPLTADDR 0
0
Reset
PMS_PRO_IRAM0_SRAM_4_SPLTADDR IBUS SRAM Block 4-21 bc/
PMS_PRO_IRAM0_SRAM_4_L_F 1 IBUS SRAM Block 4-21 bc/
PMS_PRO_IRAM0_SRAM_4_L_R 1 IBUS SRAM Block 4-21 bc/
PMS_PRO_IRAM0_SRAM_4_L_W 1 IBUS SRAM Block 4-21 bc/
PMS_PRO_IRAM0_SRAM_4_H_F 1 IBUS SRAM Block 4-21 bc/
PMS_PRO_IRAM0_SRAM_4_H_R 1 IBUS SRAM Block 4-21 bc/
PMS_PRO_IRAM0_SRAM_4_H_W 1 IBUS SRAM Block 4-21 bc/
370
ESP32-S2 TRM ( 1.3)
14 (PMS)
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Register 14.18. PMS_PRO_IRAM0_3_REG (0x001C)
(reserved)
PMS_PPMROS__PPIRMRAOSM__P0PIRM_RAROSMT__PC0PIRMF_RAAROSMST__TPC0PI_RMF_RHAAROSM_ST__WTC0PI_RF_RHAAROM_ST_TRC0I_RF_HAARM_STTFC0_F_LAR_STWTC_FLA_SRT_L_FPMS_PRO_IRAM0_RTCFAST_SPLTADDR
31
17 16 15 14 13 12 11 10
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 01 1 1 1 1 1
0
Reset
PMS_PRO_IRAM0_RTCFAST_SPLTADDR IBUS RTC FAST Memory bc/
PMS_PRO_IRAM0_RTCFAST_L_F 1 IBUS RTC FAST Memory bc/
PMS_PRO_IRAM0_RTCFAST_L_R 1 IBUS RTC FAST Memory bc/
PMS_PRO_IRAM0_RTCFAST_L_W 1 IBUS RTC FAST Memory bc/
PMS_PRO_IRAM0_RTCFAST_H_F 1 IBUS RTC FAST Memory bc/
PMS_PRO_IRAM0_RTCFAST_H_R 1 IBUS RTC FAST Memory bc/
PMS_PRO_IRAM0_RTCFAST_H_W 1 IBUS RTC FAST Memory bc/
371
ESP32-S2 TRM ( 1.3)
14 (PMS)
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Register 14.19. PMS_PRO_DRAM0_1_REG (0x002C)
(reserved) PMS_PPMROS__PPDMRROSA__MPPD0MRR_OSAS__MRPDA0RRM_OAS__MR4DA0_RM_HAS__MRW4A0_M_HS__RR4A_ML__W4_L_R
31
29 28 27 26 25 24
0 0 01 1 1 1
PMS_PRO_DRAM0_SRAM_4_SPLTADDR
PMS_PPMROS__PPDMRROSA__MPPD0MRR_OSAS__MRPPDA0MRRM_OSAS___MRP3PDA0M_RRM_WOSAS___MRP3PDA0M_RRM_ROSAS___MRP2PDA0M_RRM_WOSAS___MR2PDA0_RRM_ROAS__MR1D_A0WRM_AS_MR1_A0RM_S_R0A_MW_0_R
87 6 5 4 3 2 1 0
0
1 1 1 1 1 1 1 1 Reset
PMS_PRO_DRAM0_SRAM_0_R 1 DBUS0 SRAM Block 0 bc/ PMS_PRO_DRAM0_SRAM_0_W 1 DBUS0 SRAM Block 0 bc/ PMS_PRO_DRAM0_SRAM_1_R 1 DBUS0 SRAM Block 1 bc/ PMS_PRO_DRAM0_SRAM_1_W 1 DBUS0 SRAM Block 1 bc/ PMS_PRO_DRAM0_SRAM_2_R 1 DBUS0 SRAM Block 2 bc/ PMS_PRO_DRAM0_SRAM_2_W 1 DBUS0 SRAM Block 2 bc/ PMS_PRO_DRAM0_SRAM_3_R 1 DBUS0 SRAM Block 3 bc/ PMS_PRO_DRAM0_SRAM_3_W 1 DBUS0 SRAM Block 3 bc/ PMS_PRO_DRAM0_SRAM_4_SPLTADDR DBUS0 SRAM Block 4-21 bc/
PMS_PRO_DRAM0_SRAM_4_L_R 1 DBUS0 SRAM Block 4-21 bc/
PMS_PRO_DRAM0_SRAM_4_L_W 1 DBUS0 SRAM Block 4-21 bc/
PMS_PRO_DRAM0_SRAM_4_H_R 1 DBUS0 SRAM Block 4-21 bc/
PMS_PRO_DRAM0_SRAM_4_H_W 1 DBUS0 SRAM Block 4-21 bc/
372
ESP32-S2 TRM ( 1.3)
14 (PMS)
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Register 14.20. PMS_PRO_DRAM0_2_REG (0x0030)
(reserved)
PMS_PPMROS__PPDMRROSA__MPPD0MRR_OSAR__MTPDC0RRF_OAAR_MSTDTC0_RF_HAARM_STWTC0_F_HAR_STTRC_FLA_SWT_L_PRMS_PRO_DRAM0_RTCFAST_SPLTADDR
31
15 14 13 12 11 10
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01 1 1 1
0
Reset
PMS_PRO_DRAM0_RTCFAST_SPLTADDR DBUS0 RTC FAST Memory bc/
PMS_PRO_DRAM0_RTCFAST_L_R 1 DBUS0 RTC FAST Memory bc/
PMS_PRO_DRAM0_RTCFAST_L_W 1 DBUS0 RTC FAST Memory bc/
PMS_PRO_DRAM0_RTCFAST_H_R 1 DBUS0 RTC FAST Memory bc/
PMS_PRO_DRAM0_RTCFAST_H_W 1 DBUS0 RTC FAST Memory bc/
373
ESP32-S2 TRM ( 1.3)
14 (PMS) Register 14.21. PMS_PRO_DPORT_1_REG (0x0040)
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(reserved)
31
20 19
000000000000
PMS_PRO_DPPOMRST__PPRMREOSS__EPPRDMRVPOESO___RPFPDTMIRP_FOSOOR__T_RPVCDTARSP_LOLORIOD_TRWCDTSP__LORHOTR_WCTWS__LRHOT_WCRS_LLO_WW_L_PRMS_PRO_DPORT_RTCSLOW_SPPLMTASD_DPRRO_DPORT_APB_PERIPHERAL_
16 15 14 13 12 11
10
0
1111
0
0 Reset
PMS_PRO_DPORT_APB_PERIPHERAL_FORBID 1 PeriBus1 APB b
PMS_PRO_DPORT_RTCSLOW_SPLTADDR PeriBus1 RTC FAST Memory bc/
PMS_PRO_DPORT_RTCSLOW_L_R 1 PeriBus1 RTC FAST Memory bc/
PMS_PRO_DPORT_RTCSLOW_L_W 1 PeriBus1 RTC FAST Memory bc/
PMS_PRO_DPORT_RTCSLOW_H_R 1 PeriBus1 RTC FAST Memory bc/
PMS_PRO_DPORT_RTCSLOW_H_W 1 PeriBus1 RTC FAST Memory bc/
PMS_PRO_DPORT_RESERVE_FIFO_VALID FIFO bc/
Register 14.22. PMS_PRO_DPORT_2_REG (0x0044)
(reserved)
31
18 17
00000000000000
PMS_PRO_DPORT_RESERVE_FIFO_0 0x000
PMS_PRO_DPORT_RESERVE_FIFO_0 0bc/
0
Reset
374
ESP32-S2 TRM ( 1.3)
14 (PMS)
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Register 14.23. PMS_PRO_DPORT_3_REG (0x0048)
(reserved)
31
18 17
00000000000000
PMS_PRO_DPORT_RESERVE_FIFO_1 0x000
PMS_PRO_DPORT_RESERVE_FIFO_1 1bc/
0
Reset
Register 14.24. PMS_PRO_DPORT_4_REG (0x004C)
(reserved)
31
18 17
00000000000000
PMS_PRO_DPORT_RESERVE_FIFO_2 0x000
PMS_PRO_DPORT_RESERVE_FIFO_2 2bc/
0
Reset
Register 14.25. PMS_PRO_DPORT_5_REG (0x0050)
(reserved)
31
18 17
00000000000000
PMS_PRO_DPORT_RESERVE_FIFO_3 0x000
PMS_PRO_DPORT_RESERVE_FIFO_3 3bc/
0
Reset
375
ESP32-S2 TRM ( 1.3)
14 (PMS)
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Register 14.26. PMS_PRO_AHB_1_REG (0x0060)
(reserved)
PMS_PPMROS__PPAMRHOSB___PPARMRHTOSCB__S_PPLARMORHTOSWCB__S__PPLAR0MORHT_OSWCBH__S___PLARW0ORHT_OWCBH_S___LAR0ROHT_WCBHS___LR0FOT_WCLS__WL0O_WL__R0_L_PFMS_PRO_AHB_RTCSLOW_0_SPLTADDR
31
17 16 15 14 13 12 11 10
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 01 1 1 1 1 1
0
Reset
PMS_PRO_AHB_RTCSLOW_0_SPLTADDR PeriBus2 RTCSlow_0 bc/
PMS_PRO_AHB_RTCSLOW_0_L_F 1 PeriBus2 RTCSlow_0 bc/
PMS_PRO_AHB_RTCSLOW_0_L_R 1 PeriBus2 RTCSlow_0 bc/
PMS_PRO_AHB_RTCSLOW_0_L_W 1 PeriBus2 RTCSlow_0 bc/
PMS_PRO_AHB_RTCSLOW_0_H_F 1 PeriBus2 RTCSlow_0 bc/
PMS_PRO_AHB_RTCSLOW_0_H_R 1 PeriBus2 RTCSlow_0 bc/
PMS_PRO_AHB_RTCSLOW_0_H_W 1 PeriBus2 RTCSlow_0 bc/
376
ESP32-S2 TRM ( 1.3)
14 (PMS)
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Register 14.27. PMS_PRO_AHB_2_REG (0x0064)
(reserved)
PMS_PPMROS__PPAMRHOSB___PPARMRHTOSCB__S_PPLARMORHTOSWCB__S__PPLAR1M_ORHTHOSWCB___S__WPLAR1_ORHTHOWCB__S__RLAR1_OHTHWCB_S__FLR1_OTLWC_S_WL1_OLW__R1_L_PFMS_PRO_AHB_RTCSLOW_1_SPLTADDR
31
17 16 15 14 13 12 11 10
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 01 1 1 1 1 1
0
Reset
PMS_PRO_AHB_RTCSLOW_1_SPLTADDR PeriBus2 RTCSlow_1 bc/
PMS_PRO_AHB_RTCSLOW_1_L_F 1 PeriBus2 RTCSlow_1 bc/
PMS_PRO_AHB_RTCSLOW_1_L_R 1 PeriBus2 RTCSlow_1 bc/
PMS_PRO_AHB_RTCSLOW_1_L_W 1 PeriBus2 RTCSlow_1 bc/
PMS_PRO_AHB_RTCSLOW_1_H_F 1 PeriBus2 RTCSlow_1 bc/
PMS_PRO_AHB_RTCSLOW_1_H_R 1 PeriBus2 RTCSlow_1 bc/
PMS_PRO_AHB_RTCSLOW_1_H_W 1 PeriBus2 RTCSlow_1 bc/
Register 14.28. PMS_PRO_TRACE_1_REG (0x0074)
(reserved)
PMS_PRO_TRACE_DISABLE
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PMS_PRO_TRACE_DISABLE 1 Trace memory bc/
377
ESP32-S2 TRM ( 1.3)
14 (PMS)
GoBack
Register 14.29. PMS_PRO_CACHE_1_REG (0x007C)
(reserved)
31
16 15
0000000000000000
PMS_PRO_CACHE_CONNECT 0
0
Reset
PMS_PRO_CACHE_CONNECT Icache Dcache SRAM block 0-3 bc/
378
ESP32-S2 TRM ( 1.3)
14 (PMS)
GoBack
Register 14.30. PMS_DMA_APB_I_1_REG (0x0090)
(reserved) PMS_PDMMSA__PDAMMPSBA___PDAIM_MPSSBAR___ADAIM_MPS_BAR4__A_AIM_HPS__BRW4_A_IM_HS__RR4A_ML__W4_L_R
31
29 28 27 26 25 24
0 0 01 1 1 1
PMS_DMA_APB_I_SRAM_4_SPLTADDR 0
PMS_PDMMSA__PDAMMPSBA___PDAIM_MPSSBAR___PADAIMM_MPSS_BAR_3__PAD_AIMM_WMPSS_BAR_3__PAD_AIMM_MRPSS_BAR_2__PAD_AIMM_WMPSS_BAR_2__AD_AIM_MRPS_BAR1___AWAIM_PS_BR1__AIRM_S_R0A_MW_0_R
87 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1 Reset
PMS_DMA_APB_I_SRAM_0_R 1 DMA SRAM Block 0 bc/ PMS_DMA_APB_I_SRAM_0_W 1 DMA SRAM Block 0 bc/ PMS_DMA_APB_I_SRAM_1_R 1 DMA SRAM Block 1 bc/ PMS_DMA_APB_I_SRAM_1_W 1 DMA SRAM Block 1 bc/ PMS_DMA_APB_I_SRAM_2_R 1 DMA SRAM Block 2 bc/ PMS_DMA_APB_I_SRAM_2_W 1 DMA SRAM Block 2 bc/ PMS_DMA_APB_I_SRAM_3_R 1 DMA SRAM Block 3 bc/ PMS_DMA_APB_I_SRAM_3_W 1 DMA SRAM Block 3 bc/ PMS_DMA_APB_I_SRAM_4_SPLTADDR DMA SRAM Block 4-21 bc/
PMS_DMA_APB_I_SRAM_4_L_R 1 DMA SRAM Block 4-21 bc/
PMS_DMA_APB_I_SRAM_4_L_W 1 DMA SRAM Block 4-21 bc/
PMS_DMA_APB_I_SRAM_4_H_R 1 DMA SRAM Block 4-21 bc/
PMS_DMA_APB_I_SRAM_4_H_W 1 DMA SRAM Block 4-21 bc/
379
ESP32-S2 TRM ( 1.3)
14 (PMS)
GoBack
Register 14.31. PMS_DMA_RX_I_1_REG (0x00A0)
(reserved) PMS_PDMMSA__PDRMMXS_A_I_P_DRMSMXRS_AA_I_M_DRS_MXR4_AA_I_M_HRS__XRW4_A_IM_HS__RR4A_ML__W4_L_R
31
29 28 27 26 25 24
0 0 01 1 1 1
PMS_DMA_RX_I_SRAM_4_SPLTADDR 0
PMS_PDMMSA__PDRMMXS_A_I_P_DRMSMXRS_AA_I_MP_DRMS_MXR3S_AA__I_MP_WDRMS_MXR3S_AA__I_MP_RDRMS_MXR2S_AA__I_MP_WDRMS_MXR2S_AA__I_M_RDRS_MXR1__AAWI_M_RS_XR1__AIRM_S_R0A_MW_0_R
87 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1 Reset
PMS_DMA_RX_I_SRAM_0_R 1 RX Copy DMA SRAM Block 0 bc/ PMS_DMA_RX_I_SRAM_0_W 1 RX Copy DMA SRAM Block 0 bc/ PMS_DMA_RX_I_SRAM_1_R 1 RX Copy DMA SRAM Block 1 bc/ PMS_DMA_RX_I_SRAM_1_W 1 RX Copy DMA SRAM Block 1 bc/ PMS_DMA_RX_I_SRAM_2_R 1 RX Copy DMA SRAM Block 2 bc/ PMS_DMA_RX_I_SRAM_2_W 1 RX Copy DMA SRAM Block 2 bc/ PMS_DMA_RX_I_SRAM_3_R 1 RX Copy DMA SRAM Block 3 bc/ PMS_DMA_RX_I_SRAM_3_W 1 RX Copy DMA SRAM Block 3 bc/ PMS_DMA_RX_I_SRAM_4_SPLTADDR RX Copy DMA SRAM Block 4-21
bc/ PMS_DMA_RX_I_SRAM_4_L_R 1 RX Copy DMA SRAM Block 4-21
bc/ PMS_DMA_RX_I_SRAM_4_L_W 1 RX Copy DMA SRAM Block 4-21
bc/ PMS_DMA_RX_I_SRAM_4_H_R 1 RX Copy DMA SRAM Block 4-21
bc/ PMS_DMA_RX_I_SRAM_4_H_W 1 RX Copy DMA SRAM Block 4-21
bc/
380
ESP32-S2 TRM ( 1.3)
14 (PMS)
GoBack
Register 14.32. PMS_DMA_TX_I_1_REG (0x00B0)
(reserved) PMS_PDMMSA__PDTMMX_SA_I__PDTSMMXR_SAA_IM__DTS_MXR4_AA_IM__HTS__XRW4_A_IM_HS__RR4A_ML__W4_L_R
31
29 28 27 26 25 24
0 0 01 1 1 1
PMS_DMA_TX_I_SRAM_4_SPLTADDR 0
PMS_PDMMSA__PDTMMX_SA_I__PDTSMMXR_SAA_IM__PDTSM_MXR3_SAA__IM__WPDTSM_MXR3_SAA__IM__PRDTSM_MXR2_SAA__IM__WPDTSM_MXR2_SAA__IM__RDTS_MXR1__AAWIM__TS_XR1__AIRM_S_R0A_MW_0_R
87 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1 Reset
PMS_DMA_TX_I_SRAM_0_R 1 TX Copy DMA SRAM Block 0 bc/ PMS_DMA_TX_I_SRAM_0_W 1 TX Copy DMA SRAM Block 0 bc/ PMS_DMA_TX_I_SRAM_1_R 1 TX Copy DMA SRAM Block 1 bc/ PMS_DMA_TX_I_SRAM_1_W 1 TX Copy DMA SRAM Block 1 bc/ PMS_DMA_TX_I_SRAM_2_R 1 TX Copy DMA SRAM Block 2 bc/ PMS_DMA_TX_I_SRAM_2_W 1 TX Copy DMA SRAM Block 2 bc/ PMS_DMA_TX_I_SRAM_3_R 1 TX Copy DMA SRAM Block 3 bc/ PMS_DMA_TX_I_SRAM_3_W 1 TX Copy DMA SRAM Block 3 bc/ PMS_DMA_TX_I_SRAM_4_SPLTADDR TX Copy DMA SRAM Block 4-21
bc/ PMS_DMA_TX_I_SRAM_4_L_R 1 TX Copy DMA SRAM Block 4-21
bc/ PMS_DMA_TX_I_SRAM_4_L_W 1 TX Copy DMA SRAM Block 4-21
bc/ PMS_DMA_TX_I_SRAM_4_H_R 1 TX Copy DMA SRAM Block 4-21
bc/ PMS_DMA_TX_I_SRAM_4_H_W 1 TX Copy DMA SRAM Block 4-21
bc/
381
ESP32-S2 TRM ( 1.3)
14 (PMS)
GoBack
Register 14.33. PMS_APB_PERIPHERAL_1_REG (0x00D0)
(reserved)
PMS_APB_PERIPHERAL_SPLIT_BURST
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset
PMS_APB_PERIPHERAL_SPLIT_BURST 1 bc/
Register 14.34. PMS_OCCUPY_1_REG (0x00D8)
(reserved)
31
43
0000000000000000000000000000
PMS_OCCUPY_CACHE
0
0
Reset
PMS_OCCUPY_CACHE SRAM Block 0-3 cachebc/
Register 14.35. PMS_OCCUPY_3_REG (0x00E0)
(reserved)
31
18 17
00000000000000
PMS_OCCUPY_PRO_TRACE 0
0
Reset
PMS_OCCUPY_PRO_TRACE SRAM block 4-21 block Trace memorybc/
382
ESP32-S2 TRM ( 1.3)
14 (PMS)
GoBack
Register 14.36. PMS_CACHE_TAG_ACCESS_1_REG (0x00E8)
(reserved)
PMS_PPMROS__PPDMR_TOSA__PGPDM_R_WTOSAR__G_PI__ARTRCOADGS___I_AWTCARSG__ARCDS_ACS
31
43 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PMS_PRO_I_TAG_RD_ACS 1 Icache bc/ PMS_PRO_I_TAG_WR_ACS 1 Icache bc/ PMS_PRO_D_TAG_RD_ACS 1 Dcache bc/ PMS_PRO_D_TAG_WR_ACS 1 Dcache bc/
Register 14.37. PMS_CACHE_MMU_ACCESS_1_REG (0x00F0)
(reserved)
PMS_PPMROS__PMRMOU__MWMRU__ARCDS_ACS
31
21 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Reset
PMS_PRO_MMU_RD_ACS 1 MMU bc/ PMS_PRO_MMU_WR_ACS 1 MMU bc/
Register 14.38. PMS_PRO_IRAM0_4_REG (0x0020)
(reserved)
PMS_PPMROS__PPIRMRAOSM__0PIR_RAIOLMG_0I_R_IANILMTGR0__EINLG_CLR
31
32 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PMS_PRO_IRAM0_ILG_CLR bc/ PMS_PRO_IRAM0_ILG_EN IBUS bc/ PMS_PRO_IRAM0_ILG_INTR IBUS bc
383
ESP32-S2 TRM ( 1.3)
14 (PMS)
GoBack
Register 14.39. PMS_PRO_IRAM0_5_REG (0x0024)
(reserved)
31
22 21
0000000000
PMS_PRO_IRAM0_ILG_ST 0
0
Reset
PMS_PRO_IRAM0_ILG_ST IBUS b[21:2] IBUS [21:2][1]1 0 [0]1 0 bc
Register 14.40. PMS_PRO_DRAM0_3_REG (0x0034)
(reserved)
PMS_PPMROS__PPDMRROSA__MPD0RR_OAIL_MGD0_R_IANILMTGR0__EINLG_CLR
31
32 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PMS_PRO_DRAM0_ILG_CLR DBUS0 bc/ PMS_PRO_DRAM0_ILG_EN DBUS0 bc/ PMS_PRO_DRAM0_ILG_INTR DBUS0 bc
(reserved)
31
26 25
000000
Register 14.41. PMS_PRO_DRAM0_4_REG (0x0038)
PMS_PRO_DRAM0_ILG_ST 0
0
Reset
PMS_PRO_DRAM0_ILG_ST DBUS0 b[25:6] DBUS [21:2][5] 1 0 [4]1 0 [3:0]DBUS0 (byte enables)bc
384
ESP32-S2 TRM ( 1.3)
14 (PMS)
GoBack
Register 14.42. PMS_PRO_DPORT_6_REG (0x0054)
(reserved)
PMS_PPMROS__PPDMRPOSO__RPDTRP_OOIL_RGDT_P_INOILTRGRT__EINLG_CLR
31
32 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PMS_PRO_DPORT_ILG_CLR PeriBus1 bc/ PMS_PRO_DPORT_ILG_EN PeriBus1 bc/ PMS_PRO_DPORT_ILG_INTR PeriBus1 bc
(reserved)
31
26 25
000000
Register 14.43. PMS_PRO_DPORT_7_REG (0x0058)
PMS_PRO_DPORT_ILG_ST 0
0
Reset
PMS_PRO_DPORT_ILG_ST PeriBus1 b[25:6] PeriBus1 [21:2] [5]1 0 [4] PeriBus1 [31:22] 0xfd 1 0[3:0]PeriBus1 bc
Register 14.44. PMS_PRO_AHB_3_REG (0x0068)
(reserved)
PMS_PPMROS__PPAMRHOSB___PAILRHGOB___INAILTHGRB__EINLG_CLR
31
32 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PMS_PRO_AHB_ILG_CLR PeriBus2 bc/ PMS_PRO_AHB_ILG_EN PeriBus2 bc/ PMS_PRO_AHB_ILG_INTR PeriBus2 bc
385
ESP32-S2 TRM ( 1.3)
14 (PMS)
GoBack
Register 14.45. PMS_PRO_AHB_4_REG (0x006C)
PMS_PRO_AHB_ILG_ST
31
0
0
Reset
PMS_PRO_AHB_ILG_ST PeriBus2 b[31:2] PeriBus2 [31:2][1] 1 0 [0]1 0 bc
Register 14.46. PMS_PRO_CACHE_2_REG (0x0080)
(reserved)
PMS_PPMROS__PPCMRAOCS_H_PCER_AOCILH_GCE__AINCILTHGRE__EINLG_CLR
31
32 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PMS_PRO_CACHE_ILG_CLR Cache bc/ PMS_PRO_CACHE_ILG_EN Cache bc/ PMS_PRO_CACHE_ILG_INTR Cache bc
Register 14.47. PMS_PRO_CACHE_3_REG (0x0084)
(reserved)
31
17 16
000000000000000
PMS_PRO_CACHE_ILG_ST_I 0
0
Reset
PMS_PRO_CACHE_ILG_ST_I Icache b[16][15:4] [11:0][3:0]Icache bc
386
ESP32-S2 TRM ( 1.3)
14 (PMS)
GoBack
Register 14.48. PMS_PRO_CACHE_4_REG (0x0088)
(reserved)
31
17 16
000000000000000
PMS_PRO_CACHE_ILG_ST_D 0
0
Reset
PMS_PRO_CACHE_ILG_ST_D Dcache b[16][15:4] [11:0][3:0]Dcache bc
Register 14.49. PMS_DMA_APB_I_2_REG (0x0094)
(reserved)
PMS_PDMMSA__PDAMMPSBA___DAI_MPILBAG___AI_IPNILBTG_R_I_EINLG_CLR
31
32 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PMS_DMA_APB_I_ILG_CLR DMA bc/ PMS_DMA_APB_I_ILG_EN DMA bc/ PMS_DMA_APB_I_ILG_INTR DMA bc
Register 14.50. PMS_DMA_APB_I_3_REG (0x0098)
(reserved)
31
23 22
000000000
PMS_DMA_APB_I_ILG_ST 0
0
Reset
PMS_DMA_APB_I_ILG_ST DMA b[22:6] [18:2][5] [31:19] 0x7ff 1 0[4]1 0 [3:0] DMA bc
387
ESP32-S2 TRM ( 1.3)
14 (PMS)
GoBack
Register 14.51. PMS_DMA_RX_I_2_REG (0x00A4)
(reserved)
PMS_PDMMSA__PDRMMXS_A_I__DRIMLXG_A_I__INRILXTG_R_I_EINLG_CLR
31
32 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PMS_DMA_RX_I_ILG_CLR RX Copy DMA bc/ PMS_DMA_RX_I_ILG_EN RX Copy DMA bc/ PMS_DMA_RX_I_ILG_INTR RX Copy DMA bc
Register 14.52. PMS_DMA_RX_I_3_REG (0x00A8)
(reserved)
31
23 22
000000000
PMS_DMA_RX_I_ILG_ST 0
0
Reset
PMS_DMA_RX_I_ILG_ST RX Copy DMA b[22:6] [18:2][5] [31:19] 0x7ff 1 0[4]1 0 [3:0]RX Copy DMA bc
Register 14.53. PMS_DMA_TX_I_2_REG (0x00B4)
(reserved)
PMS_PDMMSA__PDTMMX_SA_I__DTILMXG_A_I__INTILXTG_R_I_EINLG_CLR
31
32 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PMS_DMA_TX_I_ILG_CLR TX Copy DMA bc/ PMS_DMA_TX_I_ILG_EN TX Copy DMA bc/ PMS_DMA_TX_I_ILG_INTR TX Copy DMA bc
388
ESP32-S2 TRM ( 1.3)
14 (PMS)
GoBack
Register 14.54. PMS_DMA_TX_I_3_REG (0x00B8)
(reserved)
31
23 22
000000000
PMS_DMA_TX_I_ILG_ST 0
0
Reset
PMS_DMA_TX_I_ILG_ST TX Copy DMA b[22:6] [18:2][5] [31:19] 0x7ff 1 0[4]1 0 [3:0]TX Copy DMA bc
Register 14.55. PMS_APB_PERIPHERAL_INTR_REG (0x00F4)
(reserved)
PMS_PAMPBS__PAPMPERBSI___APBPEYRBTI_E_P_BEEYRRTIRE_O_BERYR_TRIENO_TERRR_REONR_CLR
31
32 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PMS_APB_PERI_BYTE_ERROR_CLR APB bc/ PMS_APB_PERI_BYTE_ERROR_EN APB bc/ PMS_APB_PERI_BYTE_ERROR_INTR APB bc
Register 14.56. PMS_APB_PERIPHERAL_STATUS_REG (0x00F8)
PMS_APB_PERI_BYTE_ERROR_ADDR
31
0
PMS_APB_PERI_BYTE_ERROR_ADDR APB b
0
Reset
389
ESP32-S2 TRM ( 1.3)
14 (PMS)
GoBack
Register 14.57. PMS_CPU_PERIPHERAL_INTR_REG (0x00FC)
(reserved)
PMS_PCMPUS__PCPMPEURS_I__CPBPEYURTI_E_P_BEEYRRTIRE_O_BERYR_TRIENO_TERRR_REONR_CLR
31
32 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PMS_CPU_PERI_BYTE_ERROR_CLR CPU bc/ PMS_CPU_PERI_BYTE_ERROR_EN CPU bc/ PMS_CPU_PERI_BYTE_ERROR_INTR CPU bc
Register 14.58. PMS_CPU_PERIPHERAL_STATUS_REG (0x0100)
PMS_CPU_PERI_BYTE_ERROR_ADDR
31
0
PMS_CPU_PERI_BYTE_ERROR_ADDR CPU bc
0
Reset
(reserved)
31
28 27
0000
Register 14.59. PMS_DATE_REG (0x0FFC)
PMS_DATE 0x1905090
PMS_DATE bc/
0
Reset
390
ESP32-S2 TRM ( 1.3)
15
GoBack
15
15.1
ESP32-S2 bESP32-S2 caa bb
15.2
ESP32-S2 · · · · eFuse · ·
15.3
15.3.1
cache b 3 b
· SYSTEM_ROM_CTRL_0_REG · SYSTEM_ROM_CTRL_1_REG · SYSTEM_SRAM_CTRL_0_REG · SYSTEM_SRAM_CTRL_1_REG · SYSTEM_SRAM_CTRL_2_REG · SYSTEM_RSA_PD_CTRL_REG · SYSTEM_MEM_PD_MASK_REG · SYSTEM_CACHE_CONTROL_REG
391
ESP32-S2 TRM ( 1.3)
15
GoBack
· SYSTEM_BUSTOEXTMEM_ENA_REG · SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG
ROM
SYSTEM_ROM_CTRL_0_REG SYSTEM_ROM_CTRL_1_REG ESP32-S2 ROM
· SYSTEM_ROM_CTRL_0_REG SYSTEM_ROM_FO ROM block b
· SYSTEM_ROM_CTRL_1_REG SYSTEM_ROM_FORCE_PD ROM block b
· SYSTEM_ROM_CTRL_1_REG SYSTEM_ROM_FORCE_PU ROM block b
ROM 15.3-1b
15.3-1. ROM
ROM Block0 Block1
1 0x4000_0000 0x4001_2000
1 0x4000_FFFF 0x4001_FFFF
2 0x3FFA_0000
2 0x3FFA_FFFF
Bit0 Bit1
SRAM
SYSTEM_SRAM_CTRL_0_REGaSYSTEM_SRAM_CTRL_1_REG SYSTEM_SRAM_CTRL_2_REG ESP32-S2 SRAM
· SYSTEM_SRAM_CTRL_0_REG SYSTEM_SRAM_FO SRAM block b
· SYSTEM_SRAM_CTRL_1_REG SYSTEM_SRAM_FORCE_PD SRAM block b
· SYSTEM_SRAM_CTRL_2_REG SYSTEM_SRAM_FORCE_PU SRAM block b
SRAM 15.3-2b
15.3-2. SRAM
SRAM Block0 Block1 Block2 Block3 Block4 Block5 Block6 Block7
1 0x4002_0000 0x4002_2000 0x4002_4000 0x4002_6000 0x4002_8000 0x4002_C000 0x4003_0000 0x4003_4000
1 0x4002_1FFF 0x4002_3FFF 0x4002_5FFF 0x4002_7FFF 0x4002_BFFF 0x4002_FFFF 0x4003_3FFF 0x4003_7FFF
2 0x3FFB_0000 0x3FFB_2000 0x3FFB_4000 0x3FFB_6000 0x3FFB_8000 0x3FFB_C000 0x3FFC_0000 0x3FFC_4000
2 0x3FFB_1FFF 0x3FFB_3FFF 0x3FFB_5FFF 0x3FFB_7FFF 0x3FFB_BFFF 0x3FFB_FFFF 0x3FFC_3FFF 0x3FFC_7FFF
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
392
ESP32-S2 TRM ( 1.3)
15
GoBack
SRAM Block8 Block9 Block10 Block11 Block12 Block13 Block14 Block15 Block16 Block17 Block18 Block19 Block20 Block21
1 0x4003_8000 0x4003_C000 0x4004_0000 0x4004_4000 0x4004_8000 0x4004_C000 0x4005_0000 0x4005_4000 0x4005_8000 0x4005_C000 0x4006_0000 0x4006_4000 0x4006_8000 0x4006_C000
1 0x4003_BFFF 0x4003_FFFF 0x4004_3FFF 0x4004_7FFF 0x4004_BFFF 0x4004_FFFF 0x4005_3FFF 0x4005_7FFF 0x4005_BFFF 0x4005_FFFF 0x4006_3FFF 0x4006_7FFF 0x4006_BFFF 0x4006_FFFF
2 0x3FFC_8000 0x3FFC_C000 0x3FFD_0000 0x3FFD_4000 0x3FFD_8000 0x3FFD_C000 0x3FFE_0000 0x3FFE_4000 0x3FFE_8000 0x3FFE_C000 0x3FFF_0000 0x3FFF_4000 0x3FFF_8000 0x3FFF_C000
2 0x3FFC_BFFF 0x3FFC_FFFF 0x3FFD_3FFF 0x3FFD_7FFF 0x3FFD_BFFF 0x3FFD_FFFF 0x3FFE_3FFF 0x3FFE_7FFF 0x3FFE_BFFF 0x3FFE_FFFF 0x3FFF_3FFF 0x3FFF_7FFF 0x3FFF_BFFF 0x3FFF_FFFF
Bit8 Bit9 Bit10 Bit11 Bit12 Bit13 Bit14 Bit15 Bit16 Bit17 Bit18 Bit19 Bit20 Bit21
15.3.2
b 6 b · SYSTEM_CPU_PER_CONF_REG · SYSTEM_SYSCLK_CONF_REG · SYSTEM_BT_LPCK_DIV_FRAC_REG
ESP32-S2 b CLK_EN 1 RST_EN 0b
15.3.3
CPU b 8 b · SYSTEM_CPU_INTR_FROM_CPU_0_REG · SYSTEM_CPU_INTR_FROM_CPU_1_REG · SYSTEM_CPU_INTR_FROM_CPU_2_REG · SYSTEM_CPU_INTR_FROM_CPU_3_REG
15.3.4 JTAG
eFuse JTAG b 19 HMAC (HMAC)b
· SYSTEM_JTAG_CTRL_0_REG · SYSTEM_JTAG_CTRL_1_REG
393
ESP32-S2 TRM ( 1.3)
15
GoBack
· SYSTEM_JTAG_CTRL_2_REG · SYSTEM_JTAG_CTRL_3_REG · SYSTEM_JTAG_CTRL_4_REG · SYSTEM_JTAG_CTRL_5_REG · SYSTEM_JTAG_CTRL_6_REG · SYSTEM_JTAG_CTRL_7_REG
15.3.5
b 9 b · SYSTEM_RTC_FASTMEM_CONFIG_REG · SYSTEM_RTC_FASTMEM_CRC_REG
15.3.6
15.3-3b · SYSTEM_CPU_PERI_CLK_EN_REG · SYSTEM_CPU_PERI_RST_EN_REG · SYSTEM_PERIP_CLK_EN0_REG · SYSTEM_PERIP_RST_EN0_REG · SYSTEM_PERIP_CLK_EN1_REG · SYSTEM_PERIP_RST_EN1_REG 15.3-3.
CPU DEDICATED GPIO Timers Timer Group0 Timer Group1 System Timer UART0 UART1 UART MEM SPI0, SPI1 SPI2 SPI3 SPI2 DMA SPI3 DMA
1 SYSTEM_CPU_PERI_CLK_EN_REG SYSTEM_CLK_EN_DEDICATED_GPIO SYSTEM_PERIP_CLK_EN0_REG SYSTEM_TIMERS_CLK_EN SYSTEM_TIMERGROUP_CLK_EN SYSTEM_TIMERGROUP1_CLK_EN SYSTEM_SYSTIMER_CLK_EN SYSTEM_UART_CLK_EN SYSTEM_UART1_CLK_EN SYSTEM_UART_MEM_CLK_EN 4 SYSTEM_SPI01_CLK_EN SYSTEM_SPI2_CLK_EN SYSTEM_SPI3_DMA_CLK_EN SYSTEM_SPI2_DMA_CLK_EN SYSTEM_SPI3_DMA_CLK_EN
23 SYSTEM_CPU_PERI_RST_EN_REG SYSTEM_RST_EN_DEDICATED_GPIO SYSTEM_PERIP_RST_EN0_REG SYSTEM_TIMERS_RST SYSTEM_TIMERGROUP_RST SYSTEM_TIMERGROUP1_RST SYSTEM_SYSTIMER_RST SYSTEM_UART_RST SYSTEM_UART1_RST SYSTEM_UART_MEM_RST SYSTEM_SPI01_RST SYSTEM_SPI2_RST SYSTEM_SPI3_RST SYSTEM_SPI2_DMA_RST SYSTEM_SPI3_DMA_RST
394
ESP32-S2 TRM ( 1.3)
15
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I2C0 I2C1 I2S TWAI UHCI0 UHCI1 USB RMT PCNT PWM0 PWM1 PWM2 PWM3 LED_PWM eFuse APB SARADC ADC2 ARB WDG DMA HMAC RSA SHA AES
SYSTEM_I2C_EXT0_CLK_EN SYSTEM_I2C_EXT1_CLK_EN SYSTEM_I2S0_CLK_EN SYSTEM_CAN_CLK_EN SYSTEM_UHCI0_CLK_EN SYSTEM_UHCI1_CLK_EN SYSTEM_USB_CLK_EN SYSTEM_RMT_CLK_EN SYSTEM_PCNT_CLK_EN SYSTEM_PWM0_CLK_EN SYSTEM_PWM1_CLK_EN SYSTEM_PWM2_CLK_EN SYSTEM_PWM3_CLK_EN SYSTEM_LEDC_CLK_EN SYSTEM_EFUSE_CLK_EN SYSTEM_APB_SARADC_CLK_EN SYSTEM_ADC2_ARB_CLK_EN SYSTEM_WDG_CLK_EN SYSTEM_PERIP_CLK_EN1_REG SYSTEM_CRYPTO_DMA_CLK_EN SYSTEM_CRYPTO_HMAC_CLK_EN SYSTEM_CRYPTO_DS_CLK_EN SYSTEM_CRYPTO_RSA_CLK_EN SYSTEM_CRYPTO_SHA_CLK_EN SYSTEM_CRYPTO_AES_CLK_EN
SYSTEM_I2C_EXT0_RST SYSTEM_I2C_EXT1_RST SYSTEM_I2S0_RST SYSTEM_CAN_RST SYSTEM_UHCI0_RST SYSTEM_UHCI1_RST SYSTEM_USB_RST SYSTEM_RMT_RST SYSTEM_PCNT_RST SYSTEM_PWM0_RST SYSTEM_PWM1_RST SYSTEM_PWM2_RST SYSTEM_PWM3_RST SYSTEM_LEDC_RST SYSTEM_EFUSE_RST SYSTEM_APB_SARADC_RST SYSTEM_ADC2_ARB_RST SYSTEM_WDG_RST SYSTEM_PERIP_RST_EN1_REG SYSTEM_CRYPTO_DMA_RST 5 SYSTEM_CRYPTO_HMAC_RST 6 SYSTEM_CRYPTO_DS_RST 7 SYSTEM_CRYPTO_RSA_RST SYSTEM_CRYPTO_SHA_RST SYSTEM_CRYPTO_AES_RST
1. 1 0 b 2. 1 0 b 3. b 4. UART UART UART UART b 5. Crypto DMA AES SHA b 6. SHA b 7. AES aSHA RSA b
15.4
15.4-1 b 3 b
395
ESP32-S2 TRM ( 1.3)
15
15.4-1.
PeriBUS1 0x3F4C0000
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15.5
cb 15.4 b
SYSTEM_ROM_CTRL_0_REG SYSTEM_ROM_CTRL_1_REG SYSTEM_SRAM_CTRL_0_REG SYSTEM_SRAM_CTRL_1_REG SYSTEM_SRAM_CTRL_2_REG SYSTEM_RSA_PD_CTRL_REG SYSTEM_MEM_PD_MASK_REG SYSTEM_CACHE_CONTROL_REG SYSTEM_BUSTOEXTMEM_ENA_REG SYSTEM_EXTERNAL_DEVICE_ENCRYPT_ DECRYPT_CONTROL_REG SYSTEM_CPU_PER_CONF_REG SYSTEM_SYSCLK_CONF_REG SYSTEM_BT_LPCK_DIV_FRAC_REG SYSTEM_CPU_INTR_FROM_CPU_0_REG SYSTEM_CPU_INTR_FROM_CPU_1_REG SYSTEM_CPU_INTR_FROM_CPU_2_REG SYSTEM_CPU_INTR_FROM_CPU_3_REG JTAG SYSTEM_JTAG_CTRL_0_REG SYSTEM_JTAG_CTRL_1_REG SYSTEM_JTAG_CTRL_2_REG SYSTEM_JTAG_CTRL_3_REG SYSTEM_JTAG_CTRL_4_REG SYSTEM_JTAG_CTRL_5_REG SYSTEM_JTAG_CTRL_6_REG SYSTEM_JTAG_CTRL_7_REG SYSTEM_RTC_FASTMEM_CONFIG_REG SYSTEM_RTC_FASTMEM_CRC_REG
ROM 0
0x0000
ROM 1
0x0004
SRAM 0
0x0008
SRAM 1
0x000C
SRAM 2
0x0088
RSA
0x0068
clow-sleep 0x003C
Cache
0x0070
EDMA
0x006C
0x0074
CPU
CPU 0 CPU 1 CPU 2 CPU 3
JTAG 0 JTAG 1 JTAG 2 JTAG 3 JTAG 4 JTAG 5 JTAG 6 JTAG 7
RTC RTC CRC
0x0018 0x008C 0x0054
0x0058 0x005C 0x0060 0x0064
0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038
0x0078 0x007C
/ / / / / / / / /
/
/ /
/ / / /
396
ESP32-S2 TRM ( 1.3)
15
SYSTEM_CPU_PERI_CLK_EN_REG SYSTEM_CPU_PERI_RST_EN_REG SYSTEM_PERIP_CLK_EN0_REG SYSTEM_PERIP_CLK_EN1_REG SYSTEM_PERIP_RST_EN0_REG SYSTEM_PERIP_RST_EN1_REG SYSTEM_REG_DATE_REG
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CPU CPU c 0 c 1 c 0 c 1
0x0010 0x0014 0x0040 0x0044 0x0048 0x004C
/ / / / / /
0x0FFC /
15.6
cb 15.4 b
Register 15.1. SYSTEM_ROM_CTRL_0_REG (0x0000)
(reserved)
SYSTEM_ROM_FO
31
21
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x3 Reset
SYSTEM_ROM_FO ROM b 15.3-1bc/
Register 15.2. SYSTEM_ROM_CTRL_1_REG (0x0004)
(reserved)
SYSTEM_ROSYMS_TFEOMR_CREO_MPU_FORCE_PD
31
43
21
0
0000000000000000000000000000 3
0 Reset
SYSTEM_ROM_FORCE_PD ROM b 15.3-1bc/ SYSTEM_ROM_FORCE_PU ROM b 15.3-1bc/
397
ESP32-S2 TRM ( 1.3)
15
Register 15.3. SYSTEM_SRAM_CTRL_0_REG (0x0008)
(reserved)
31
22 21
0000000000
SYSTEM_SRAM_FO 0x3fffff
SYSTEM_SRAM_FO SRAM b 15.3-2bc/
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0
Reset
Register 15.4. SYSTEM_SRAM_CTRL_1_REG (0x000C)
(reserved)
31
22 21
0000000000
SYSTEM_SRAM_FORCE_PD 0
SYSTEM_SRAM_FORCE_PD SRAM b 15.3-2bc/
0
Reset
Register 15.5. SYSTEM_CPU_PERI_CLK_EN_REG (0x0010)
(reserved)
SYSTE(Mres_eCrLvKe_dE) N_DEDIC(AreTsEeDr_vGedP)IO
31
87 65
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTEM_CLK_EN_DEDICATED_GPIO 1 DEDICATED GPIO b 5 IO MUX GPIO bc/
398
ESP32-S2 TRM ( 1.3)
15
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Register 15.6. SYSTEM_CPU_PERI_RST_EN_REG (0x0014)
(reserved)
SYSTE(Mres_eRrSvTe_dE) N_DEDIC(AreTsEeDr_vGedP)IO
31
87 65
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 Reset
SYSTEM_RST_EN_DEDICATED_GPIO 1 DEDICATED GPIOb 5 IO MUX GPIO b(R/W)
Register 15.7. SYSTEM_CPU_PER_CONF_REG (0x0018)
(reserved)
31
87
000000000000000000000000
SYSTEM_CPUS_WYSATITESIMY_SD_TCEELPMAUY_S__WYPNSLAUTLITE_M_MFMR_ECOQPD_UES_PEFELORIROCDE__SOENL
43 21
0
0x0
1 1 0 Reset
SYSTEM_CPUPERIOD_SEL CPU b 6 6.21bc/
SYSTEM_PLL_FREQ_SEL CPU PPL b 6 cb/
SYSTEM_CPU_WAIT_MODE_FORCE_ON 1 CPU b CPU CPU b WAITI CPU bc/
SYSTEM_CPU_WAITI_DELAY_NUM CPU WAITI CPU bc/
399
ESP32-S2 TRM ( 1.3)
15
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Register 15.8. SYSTEM_JTAG_CTRL_0_REG (0x001C)
SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0
31
0
0
Reset
SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 c 256 eFuse JTAG 0 31 b 19 HMAC (HMAC)cb
Register 15.9. SYSTEM_JTAG_CTRL_1_REG (0x0020)
SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1
31
0
0
Reset
SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1 c 256 eFuse JTAG 32 63 b 19 HMAC (HMAC)bc
400
ESP32-S2 TRM ( 1.3)
15
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Register 15.10. SYSTEM_JTAG_CTRL_2_REG (0x0024)
SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2
31
0
0
Reset
SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2 c 256 eFuse JTAG 64 95 b 19 HMAC (HMAC)bc
Register 15.11. SYSTEM_JTAG_CTRL_3_REG (0x0028)
SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3
31
0
0
Reset
SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3 c 256 eFuse JTAG 96 127 b 19 HMAC (HMAC)bc
401
ESP32-S2 TRM ( 1.3)
15
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Register 15.12. SYSTEM_JTAG_CTRL_4_REG (0x002C)
SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4
31
0
0
Reset
SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4 c 256 eFuse JTAG 128 159 b 19 HMAC (HMAC)bc
Register 15.13. SYSTEM_JTAG_CTRL_5_REG (0x0030)
SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5
31
0
0
Reset
SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5 c 256 eFuse JTAG 160 191 b 19 HMAC (HMAC)bc
402
ESP32-S2 TRM ( 1.3)
15
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Register 15.14. SYSTEM_JTAG_CTRL_6_REG (0x0034)
SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6
31
0
0
Reset
SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6 c 256 eFuse JTAG 192 223 b 19 HMAC (HMAC)bc
Register 15.15. SYSTEM_JTAG_CTRL_7_REG (0x0038)
SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7
31
0
0
Reset
SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 c 256 eFuse JTAG 224 255 b 19 HMAC (HMAC)bc
403
ESP32-S2 TRM ( 1.3)
15
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Register 15.16. SYSTEM_MEM_PD_MASK_REG (0x003C)
(reserved)
SYSTEM_LSLP_MEM_PD_MASK
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset
SYSTEM_LSLP_MEM_PD_MASK 1 light-sleep bc/
Register 15.17. SYSTEM_PERIP_CLK_EN0_REG (0x0040)
(reserSvYeSdT)ESMYS_TAEDSMYCS_2TS_EYSAMSYRTS_BITAM_EPSCEMYBLRS_K__TS_SCEPAESLMNRYIK3SA___TDPEDECWSNMMY_MASC_T_3PLCE_KWSMCL_YMKLSE__KTN2U_EE_ASNEMCRYNLST_KT_U_EM(SEMrBeENs__MeSC_rPSLvCKIYe2LS_d_KTE)_DENSEMMYNAS_T_PCEWSMLYMKS__T1C_EEASCNMNYLS__KTCI_2ESLECMKYN_S__ETEPXENWSTMY1M_S_TC0SE_LPSMKCYI3_LS__EKTTCN_EISMLMEYKENS__RTEEGEFSNRMUYOSS_UTTEEPI_SMM1CY_ELS_CRKTULG_ESHKRMEYC_ONS_EI1UTLN_EPESCM_DYLCSC_KLT__PKECECS_MNLYNEKS_TN_TR_EEMSCMNYLTSK__TU_CEESHLMNYCKS__I0TIE2_ESNCCMY_LS_EKTSX_EPSTEMYI02NS___TUCCEASLLMRYKKST___T1IEE2_ESNNCSMY0LS_K_TW_CESDELMYNKGS___TUECEASNLMRYKST__T_SEECPNMLI0K_1_T_EICMNLEKR_SE_NCLK_EN
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 1 1 1 1 Reset
SYSTEM_CPU_PERI_CLK_EN0_REG 15.3-3b
404
ESP32-S2 TRM ( 1.3)
15
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Register 15.18. SYSTEM_PERIP_CLK_EN1_REG (0x0044)
(reserved)
SYSTESMYS_TCERSMYYSP_TTCEORSM_YYSPD_TTCMEORSAM_YY_SPH_CTTCMLEORSKAM_YY_CSPD_E_TTCSNCEO_R(LMrC_YeKPRLs__KeSTCE_OrARNvE__YeNCSPdLHT)KOA___ECANLEKS__ECNLK_EN
31
76 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTEM_CRYPTO_AES_CLK_EN Set this bit to enable clock of cryptography AES. (R/W) SYSTEM_CRYPTO_SHA_CLK_EN Set this bit to enable clock of cryptography SHA. (R/W) SYSTEM_CRYPTO_RSA_CLK_EN Set this bit to enable clock of cryptography RSA. (R/W) SYSTEM_CRYPTO_DS_CLK_EN Set this bit to enable clock of cryptography digital signature. (R/W)
SYSTEM_CRYPTO_HMAC_CLK_EN Set this bit to enable clock of cryptography HMAC. (R/W) SYSTEM_CRYPTO_DMA_CLK_EN Set this bit to enable clock of cryptography DMA. (R/W)
Register 15.19. SYSTEM_PERIP_RST_EN0_REG (0x0048)
(reserSvYeSdT)ESMYS_TAEDSMYCS_2TS_EYSAMSYRTS_BITAM_EPSREMYBSRS__T_TSSREPASSMRYIT3SA__TDPDECWSMMY_MAS_RT_3PSE_RTWSMRSYMTSS_TT2UE_ASMRRYSST_TT_UEM(SMrBeEs__MeSR_rPSSvRIYTe2SSd_TT)DESMMYAS_T_PERWSMSYMTS_T1C_EASRMNYSS__TTIR2ESSCMTY_S_ETPXEWSTMY1M_S_T0RSE_SPSMTRYI3SS__TTTREISMSMYTES_RTEGEFSRMUYOSS_UTTEEPI_SMM1RY_ESS_RRTTUSGESHTRMYCOS_I1UTL_EPESRM_DYSRSC_TST_PTERCSMSYNTS_TTR_EMSRMYSTS_T_TURESHSMYCTS_I0TI2_ESCMRY_SS_ETTSXEPSTMYI02S___TURREASSSMRYTTST_T1I2_ESSRMY0SS_T_TWRESDSMYGTS__TUREASSMRYTST_T_SERPMSI0T_1T_IRMSETRS_RST
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTEM_PERIP_RST_EN0_REG 15.3-3b
405
ESP32-S2 TRM ( 1.3)
15
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Register 15.20. SYSTEM_PERIP_RST_EN1_REG (0x004C)
(reserved)
SYSTESMYS_TCERSMYYSP_TTCEORSM_YYSPD_TTCMEORSAM_YY_SHP_RTTCMSEORSTAM_YYCSPD__TTCSREO_R(SMr_RYeTPRSs_eTSTCOrARv__YeRSPdSHT)TOA__RASETS_RST
31
76 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 Reset
SYSTEM_PERIP_RST_EN1_REG 15.3-3b
Register 15.21. SYSTEM_BT_LPCK_DIV_FRAC_REG (0x0054)
(reserved) SYSTESMYS_TLEPSMCYSL_TKLE_PSMRCYTSL_CTKL_E_PSMESCYNESL_LTKL_E_PXMSCTEL_ALKLL__P3XSC2TEKLALKL__8SMEL_RTC_SLOW (reserved)
31
29 28 27 26 25 24 23
0 0 00 0 0 1 0
1
12 11
(reserved) 1
SYSTEM_LPCLK_SEL_RTC_SLOW 1 RTC_SLOW_CLK bc/ SYSTEM_LPCLK_SEL_8M 1 RC_FAST_CLK bc/ SYSTEM_LPCLK_SEL_XTAL 1 XTAL_CLK bc/ SYSTEM_LPCLK_SEL_XTAL32K 1 XTAL32K_CLK bc/ SYSTEM_LPCLK_RTC_EN 1 RTC bc/
0
Reset
Register 15.22. SYSTEM_CPU_INTR_FROM_CPU_0_REG (0x0058)
(reserved)
SYSTEM_CPU_INTR_FROM_CPU_0
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTEM_CPU_INTR_FROM_CPU_0 1 CPU 0b ISR 0cb/
406
ESP32-S2 TRM ( 1.3)
15
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Register 15.23. SYSTEM_CPU_INTR_FROM_CPU_1_REG (0x005C)
(reserved)
SYSTEM_CPU_INTR_FROM_CPU_1
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTEM_CPU_INTR_FROM_CPU_1 1 CPU 1b ISR 0bc/
Register 15.24. SYSTEM_CPU_INTR_FROM_CPU_2_REG (0x0060)
(reserved)
SYSTEM_CPU_INTR_FROM_CPU_2
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTEM_CPU_INTR_FROM_CPU_2 1 CPU 2b ISR 0cb/
Register 15.25. SYSTEM_CPU_INTR_FROM_CPU_3_REG (0x0064)
(reserved)
SYSTEM_CPU_INTR_FROM_CPU_3
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTEM_CPU_INTR_FROM_CPU_3 1 CPU 3b ISR 0cb/
407
ESP32-S2 TRM ( 1.3)
15
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Register 15.26. SYSTEM_RSA_PD_CTRL_REG (0x0068)
(reserved)
SYSTESMYS_TRESSMAYS__TMRESEMAM___MRFSEOAMR_C_MFEEO_MPRDC_PE_DPU
31
32 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset
SYSTEM_RSA_MEM_PD 1 RSA bb RSA bc/
SYSTEM_RSA_MEM_FORCE_PU 1 RSA bbc/
SYSTEM_RSA_MEM_FORCE_PD 1 RSA bbc/
Register 15.27. SYSTEM_BUSTOEXTMEM_ENA_REG (0x006C)
(reserved)
SYSTEM_BUSTOEXTMEM_ENA
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset
SYSTEM_BUSTOEXTMEM_ENA 1 EDMA bc/
Register 15.28. SYSTEM_CACHE_CONTROL_REG (0x0070)
(reserved)
SYSTESMYS_TPERSMYOS__TPCERAMOC_H_PDER_CORAE_CSIHCEEAT_CCHLEK__COLNK_ON
31
32 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Reset
SYSTEM_PRO_ICACHE_CLK_ON 1 i-cache bc/ SYSTEM_PRO_DCACHE_CLK_ON 1 d-cache bc/ SYSTEM_PRO_CACHE_RESET 1 cachebc/
408
ESP32-S2 TRM ( 1.3)
15
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Register 15.29. SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (0x0074)
(reserved)
SYSTEM_SEYNSATBEMLE__SEYDNSOATWBENMLEL__SOEYDANSODAT_WBEMNMLEAL__ONEDAUNODAA_WLB_GNLE0ELNC_OCBSARP_DYID__PEDMTCBAR_NYEUPNATCLR_YEPNTCRYPT
31
43 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT 1 SPI Boot (Manual Encryption)bc/
SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT 1 Download Boot (Auto Encryption)bc/
SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT 1 Download Boot (Auto Decryption)bc/
SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT 1 Download Boot (Manual Encryption)bc/
Register 15.30. SYSTEM_RTC_FASTMEM_CONFIG_REG (0x0078)
SYSTEM_RTC_MEM_CRC_FINISHSYSTEM_RTC_MEM_CRC_LEN
31 30
20 19
0
0x7ff
SYSTEM_RTC_MEM_CRC_ADDR SYSTEM_RTC_MEM_CRC(r_eSsTeArvReTd)
987
0
0x0
0 0 0 0 0 0 0 0 0 Reset
SYSTEM_RTC_MEM_CRC_START 1 RTC CRC bc/ SYSTEM_RTC_MEM_CRC_ADDR CRC RTC bc/ SYSTEM_RTC_MEM_CRC_LEN CRC RTC cbc/ SYSTEM_RTC_MEM_CRC_FINISH RTC CRC b
bc
409
ESP32-S2 TRM ( 1.3)
15
Register 15.31. SYSTEM_RTC_FASTMEM_CRC_REG (0x007C)
SYSTEM_RTC_MEM_CRC_RES
31
0
SYSTEM_RTC_MEM_CRC_RES RTC CRC bc
GoBack
0
Reset
Register 15.32. SYSTEM_SRAM_CTRL_2_REG (0x0088)
(reserved)
31
22 21
0000000000
SYSTEM_SRAM_FORCE_PU 0x3fffff
SYSTEM_SRAM_FORCE_PU SRAM b 15.3-2bc/
0
Reset
Register 15.33. SYSTEM_SYSCLK_CONF_REG (0x008C)
(reserved)
31
19 18
000000000000
SYSTEM_CLK_XTAL_FRESQYSTEM_SOC_CLK_SEL
12 11 10 9
0
0
SYSTEM_PRE_DIV_CNT
0
0x1
Reset
SYSTEM_PRE_DIV_CNT b 6 6.23bc/
SYSTEM_SOC_CLK_SEL SoC b 6 6.2-1bc/
SYSTEM_CLK_XTAL_FREQ cMHzbc
410
ESP32-S2 TRM ( 1.3)
15
(reserved)
31
28 27
0000
Register 15.34. SYSTEM_DATE_REG (0x0FFC)
SYSTEM_REG_DATE 0x1908020
SYSTEM_DATE bc/
GoBack
0
Reset
411
ESP32-S2 TRM ( 1.3)
GoBack
IV
SHAaAES aa/ b
412
ESP32-S2 TRM ( 1.3)
16 SHA (SHA)
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16 SHA (SHA)
16.1
ESP32-S2 SHAc SHA Typical SHA DMA-SHA b SHA SHA b
16.2
ESP32-S2 SHA · FIPS PUB 180-4 SHA-1 SHA-224 SHA-256 SHA-384 SHA-512 SHA-512/224 SHA-512/256 SHA-512/t · Typical SHA DMA-SHA · (interleave) c Typical SHA · c DMA-SHA
16.3
ESP32-S2 SHA Typical SHA DMA-SHA b · Typical SHA CPU b · DMA-SHA crypto DMA b DMA DMA SHA b CPU b
413
ESP32-S2 TRM ( 1.3)
16 SHA (SHA)
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SHA_START_REG SHA_DMA_START_REG SHA 16.3-1b
16.3-1.
Typical SHA DMA-SHA
SHA_START_REG 1 SHA_DMA_START_REG 1
SHA_MODE_REG SHA 16.3-2b
16.3-2.
SHA-1 SHA-224 SHA-256 SHA-384 SHA-512 SHA-512/224 SHA-512/256 SHA-512/t
SHA_MODE_REG 0 1 2 3 4 5 6 7
ESP32-S2 (DSA) HMAC (HMAC) SHA b SHA b
16.4
SHA (message digest)b
16.4.1
ab
16.4.2
SHA 512 1024 b SHA b M m
· SHA-1aSHA-224 SHA-256 1. 1 "1" 2. k "0"bk m + 1 + k 448 mod 512
414
ESP32-S2 TRM ( 1.3)
16 SHA (SHA)
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3. 64 b m b
· SHA-384aSHA-512aSHA-512/224aSHA-512/256 SHA-512/t 1. 1 "1" 2. k "0"bk m + 1 + k 896 mod 1024 3. 128 b m b
FIPS PUB 180-4 o5.1 Padding the Messagepb
16.4.3
c N 512 1024 b
· SHA-1aSHA-224 SHA-256c N 512 M (1)a M (2)a...aM (N)b 512 16 32 (word) i 32 M(0i) 32 M(1i)... 16 32 M(1i5)b
· SHA-384aSHA-512aSHA-512/224aSHA-512/256 SHA-512/tc N 1024 M (1)aM (2)a...aM (N)b 1024 16 64 (word) i 64 M(0i) 64 M(1i)... 16 64 M(1i5)b
Typical SHA
· SHA-1aSHA-224aSHA-256 M(0i) SHA_M_0_REG M(1i) SHA_M_1_REG...M(1i5) SHA_M_15_REG b
· SHA-384aSHA-512aSHA-512/224aSHA-512/256 M0(i) 32 SHA_M_0_REG 32 SHA_M_1_REGM(1i) 32 SHA_M_2_REG 32 SHA_M_3_REG ...M(1i5) 32 SHA_M_30_REG 32 SHA_M_31_REGb
op FIPS PUB 180-4 o2.1 Glossary of Terms and Acronymspb
DMA-SHA 1. 2. 2 DMA (DMA) c buffer 3. CRYPTO_DMA_OUTLINK_ADDR 4. 1 CRYPTO_DMA_OUTLINK_START DMA 5. 1 CRYPTO_DMA_AES_SHA_SELECT_REG AES SHA DMA SHA b
415
ESP32-S2 TRM ( 1.3)
16 SHA (SHA)
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16.4.4 (Initial Hash Value)
H(0)b SHA-1a SHA-224aSHA-256aSHA-384aSHA-512aSHA-512/224aSHA-512/256 C b
SHA-512/t t bSHA-512/t SHA-512 t t b t o 0 512 384 pb t SHA-512/t "SHA-512/tp SHA-512 b t SHA-512/t t b
SHA-512/t
1. t_string t_lengtht_string t 32-bitbt_length 7-bitb t t_string t_length
· 1 <= t <= 9 t_length = 7h48t_string :
8h3t0
1b1
23b0
t0 = tb
t = 8 t0 = 8t_string = 32h38800000b
· 10 <= t <= 99 t_length = 7h50t_string :
8h3t1
8h3t0
1b1
15b0
t0 = t%10t1 = t/10b
t = 56 t0 = 6t1 = 5t_string = 32h35368000b
· 100 <= t < 512 t_length = 7h58t_string :
8h3t2
8h3t1
8h3t0
1b1
7b0
t0 = t%10t1 = (t/10)%10t2 = t/100b
t = 231 t0 = 1t1 = 3t2 = 2t_string = 32h32333180b
2. t_string t_length SHA_T_STRING_REG SHA_T_LENGTH_REGb
3. SHA_MODE_REG 7 SHA-512/t SHA_START_REG 1 SHA b SHA_BUSY_REG 0 b
FIPS PUB 180-4 Spec "5.3.6 SHA-512/t" SHA-512/t oSHA-512/tpop SHA-512 bop SHA-512 oSHA-512 C 0xa5 8 pb
416
ESP32-S2 TRM ( 1.3)
16 SHA (SHA)
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16.4.5
ESP32-S2 SHA bESP32-S2 SHA Typical SHA DMA-SHA b
16.4.6 Typical SHA
ESP32-S2 SHA Typical SHA ·oalonepb ·ointerleavep SHA_H_n_REG Typical SHA DMA-SHA b SHA_H_n_REG b
Typical SHA cSHA-512/t
1. b · SHA_MODE_REG b 16.3-2b
2. b (a) SHA_M_n_REG (b) SHA 1 · SHA_START_REG 1 SHA bSHA 1 · SHA_CONTINUE_REG 1 SHA bSHA SHA_H_n_REG b (c) SHA_BUSY_REG 0 SHA opb 3b
3. b · SHA (a) SHA_MODE_REG (b) SHA_H_n_REG (c) b Typical SHA DMA-SHA b · 4b
4. · 2b · 5b
5. SHA c · SHA
417
ESP32-S2 TRM ( 1.3)
16 SHA (SHA)
GoBack
(a) SHA_MODE_REG; (b) SHA_H_n_REG (c) 2b · SHA b 6b 6. · SHA_H_n_REG b
Typical SHA cSHA-512/t
1. b · SHA_MODE_REG 7 SHA-512/t b
2. b (a) t_string t_length SHA_T_STRING_REG SHA_T_LENGTH_REG b 16.4.4 b (b) SHA_START_REG 1 SHA b (c) SHA_BUSY_REG 0 SHA b
3. b (a) SHA_M_n_REG (b) SHA 1 · SHA_CONTINUE_REG 1 SHA bSHA SHA_H_n_REG b (c) SHA_BUSY_REG 0 SHA opb 4b
4. b · SHA (a) SHA_MODE_REG (b) SHA_H_n_REG (c) b Typical SHA DMA-SHA b · 5b
5. · 3b · 6b
6. SHA c · SHA (a) SHA_MODE_REG;
418
ESP32-S2 TRM ( 1.3)
16 SHA (SHA)
GoBack
(b) SHA_H_n_REG (c) 3b · SHA b 7b 7. · SHA_H_n_REG b
1. 2b SHA SHA_M_n_REG b
16.4.7 DMA-SHA
ESP32-S2 SHA DMA-SHA ointerleavep b DMA-SHA b DMA-SHA b Typical SHA SHA DMA-SHA b 16.4.3 DMA b 2 DMA (DMA)b DMA-SHA cSHA-512/t
1. b · SHA_MODE_REG b 16.3-2b
2. b SHA_INT_ENA_REG 1 b 3. b
· M SHA_DMA_BLOCK_NUM_REG b 4. DMA-SHA b
· DMA-SHA DMA-SHA SHA_H_n_REG 1 SHA_DMA_CONTINUE_REG
· 1 SHA_DMA_START_REGb 5. DMA-SHA b DMA-SHA
· SHA_BUSY_REG 0b · b SHA_INT_CLEAR_REG 1 b 6. · SHA_H_n_REG b DMA-SHA cSHA-512/t 1. b · SHA_MODE_REG 7 SHA-512/t b 2. b SHA_INT_ENA_REG 1 b
419
ESP32-S2 TRM ( 1.3)
16 SHA (SHA)
GoBack
3. b (a) t_string t_length SHA_T_STRING_REG SHA_T_LENGTH_REG b 16.4.4 b (b) SHA_START_REG 1 SHA b (c) SHA_BUSY_REG 0 SHA b
4. b · M SHA_DMA_BLOCK_NUM_REG b
5. DMA-SHA b · SHA_DMA_CONTINUE_REG 1 SHA b
6. DMA-SHA b DMA-SHA · SHA_BUSY_REG 0b · b SHA_INT_CLEAR_REG 1 b
7. · SHA_H_n_REG b
16.4.8
SHA SHA_H_n_REG (n: 0~15) b 16.4-4
16.4-4.
SHA-1 SHA-224 SHA-256 SHA-384 SHA-512 SHA-512/224 SHA-512/256 SHA-512/t 2
c 1
160
SHA_H_0_REG ~ SHA_H_4_REG
224
SHA_H_0_REG ~ SHA_H_6_REG
256
SHA_H_0_REG ~ SHA_H_7_REG
384
SHA_H_0_REG ~ SHA_H_11_REG
512
SHA_H_0_REG ~ SHA_H_15_REG
224
SHA_H_0_REG ~ SHA_H_6_REG
256
SHA_H_0_REG ~ SHA_H_7_REG
t
SHA_H_0_REG ~ SHA_H_x_REG
1. word SHA_H_0_REG word SHA_H_1_REG b
2. SHA-512/t t bx+1 t 32 x = roundup(t/32)-1b · t = 8 x = 0 8 SHA_H_0_REG 8 · t = 32 x = 0 32 SHA_H_0_REG · t = 132 x = 4 132 SHA_H_0_REGaSHA_H_1_REGa SHA_H_2_REGaSHA_H_3_REG SHA_H_4_REG b
420
ESP32-S2 TRM ( 1.3)
16 SHA (SHA)
GoBack
16.4.9
SHA DMA-SHA b SHA_INT_ENA_REG 1 bSHA b SHA_INT_CLEAR_REG 1 b SHA Typical SHA b
16.5
SHA 16.5-1 b 3 b
16.5-1. SHA
PeriBUS1 PeriBUS2
0x3F43B000 0x6003B000
16.6
SHA_CONTINUE_REG SHA_BUSY_REG SHA_DMA_START_REG SHA_START_REG SHA_DMA_CONTINUE_REG SHA_INT_CLEAR_REG SHA_INT_ENA_REG SHA_DATE_REG SHA_MODE_REG
SHA_T_STRING_REG
SHA_T_LENGTH_REG
SHA_DMA_BLOCK_NUM_REG SHA_H_0_REG SHA_H_1_REG SHA_H_2_REG SHA_H_3_REG SHA_H_4_REG
SHA c Typical SHA SHA op SHA DMA-SHA SHA Typical SHA SHA c DMA-SHA DMA-SHA DMA-SHA
0x0014 0x0018 0x001C 0x0010 0x0020 0x0024 0x0028
/
0x002C /
SHA c SHA-512/t c SHA-512/t
0x0000 0x0004 0x0008
/ / /
c DMA-SHA 0x000C
0x0040
0x0044
0x0048
0x004C
0x0050
/ / / / / /
421
ESP32-S2 TRM ( 1.3)
16 SHA (SHA)
SHA_H_5_REG SHA_H_6_REG SHA_H_7_REG SHA_H_8_REG SHA_H_9_REG SHA_H_10_REG SHA_H_11_REG SHA_H_12_REG SHA_H_13_REG SHA_H_14_REG SHA_H_15_REG SHA_M_0_REG SHA_M_1_REG SHA_M_2_REG SHA_M_3_REG SHA_M_4_REG SHA_M_5_REG SHA_M_6_REG SHA_M_7_REG SHA_M_8_REG SHA_M_9_REG SHA_M_10_REG SHA_M_11_REG SHA_M_12_REG SHA_M_13_REG SHA_M_14_REG SHA_M_15_REG SHA_M_16_REG SHA_M_17_REG SHA_M_18_REG SHA_M_19_REG SHA_M_20_REG SHA_M_21_REG SHA_M_22_REG SHA_M_23_REG SHA_M_24_REG SHA_M_25_REG SHA_M_26_REG SHA_M_27_REG SHA_M_28_REG SHA_M_29_REG SHA_M_30_REG SHA_M_31_REG
422
GoBack
0x0054 0x0058 0x005C 0x0060 0x0064 0x0068 0x006C 0x0070 0x0074 0x0078 0x007C 0x0080 0x0084 0x0088 0x008C 0x0090 0x0094 0x0098 0x009C 0x00A0 0x00A4 0x00A8 0x00AC 0x00B0 0x00B4 0x00B8 0x00BC 0x00C0 0x00C4 0x00C8 0x00CC 0x00D0 0x00D4 0x00D8 0x00DC 0x00E0 0x00E4 0x00E8 0x00EC 0x00F0 0x00F4 0x00F8 0x00FC
/ / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / /
ESP32-S2 TRM ( 1.3)
16 SHA (SHA)
16.7
GoBack
Register 16.1. SHA_START_REG (0x0010)
(reserved)
SHA_START
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SHA_START 1 SHA Typical SHA bc
Register 16.2. SHA_CONTINUE_REG (0x0014)
(reserved)
SHA_CONTINUE
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SHA_CONTINUE 1 SHA Typical SHA bc
Register 16.3. SHA_BUSY_REG (0x0018)
(reserved)
SHA_BUSY_STATE
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SHA_BUSY_STATE SHA opbc1'h0: 1'h1:
Register 16.4. SHA_DMA_START_REG (0x001C)
(reserved)
SHA_DMA_START
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SHA_DMA_START 1 SHA DMA-SHA bc
423
ESP32-S2 TRM ( 1.3)
16 SHA (SHA)
GoBack
Register 16.5. SHA_DMA_CONTINUE_REG (0x0020)
(reserved)
SHA_DMA_CONTINUE
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SHA_DMA_CONTINUE 1 SHA DMA-SHA bc
Register 16.6. SHA_INT_CLEAR_REG (0x0024)
(reserved)
SHA_CLEAR_INTERRUPT
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SHA_CLEAR_INTERRUPT DMA-SHA bc
Register 16.7. SHA_INT_ENA_REG (0x0028)
(reserved)
SHA_INTERRUPT_ENA
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SHA_INTERRUPT_ENA DMA-SHA bc/
(reserved)
31 30 29
00
Register 16.8. SHA_DATE_REG (0x002C)
SHA_DATE 0x20190402
SHA_DATE bc/
0
Reset
424
ESP32-S2 TRM ( 1.3)
16 SHA (SHA)
GoBack
Register 16.9. SHA_MODE_REG (0x0000)
(reserved)
SHA_MODE
31
32
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 Reset
SHA_MODE SHA 16.3-2b(/)
Register 16.10. SHA_T_STRING_REG (0x0004)
SHA_T_STRING
31
0x000000
SHA_T_STRING c SHA-512/t bc/
0
Reset
Register 16.11. SHA_T_LENGTH_REG (0x0008)
(reserved)
31
65
00000000000000000000000000
SHA_T_LENGTH
0
0x0
Reset
SHA_T_LENGTH c SHA-512/t bc/
Register 16.12. SHA_DMA_BLOCK_NUM_REG (0x000C)
(reserved)
31
65
00000000000000000000000000
SHA_DMA_BLOCK_NUM DMA-SHA bc/
SHA_DMA_BLOCK_NUM
0
0x0
Reset
425
ESP32-S2 TRM ( 1.3)
16 SHA (SHA)
Register 16.13. SHA_H_n_REG (n: 0-15) (0x0040+4*n)
SHA_H_n
31
0x000000
SHA_H_n n 32 bc/
Register 16.14. SHA_M_n_REG (n: 0-31) (0x0080+4*n)
SHA_M_n
31
0x000000
SHA_M_n n 32 bc/
GoBack
0
Reset
0
426
ESP32-S2 TRM ( 1.3)
17 AES (AES)
GoBack
17
AES (AES)
17.1
ESP32-S2 AESc AES Typical AES DMA-AES b AES AES b
17.2
ESP32-S2 · Typical AES AES-128/AES-192/AES-256 4 4 · DMA-AES * ECB (Electronic Codebook) * CBC (Cipher Block Chaining) * OFB (Output Feedback) * CTR (Counter) * CFB8 (8-bit Cipher Feedback) * CFB128 (128-bit Cipher Feedback) GCM (Galois/Counter Mode)
17.3
ESP32-S2 AES Typical AES DMA-AES b · Typical AES NIST FIPS 197 AES-128aAES-192aAES-256 b // CPU b
427
ESP32-S2 TRM ( 1.3)
17 AES (AES)
GoBack
· DMA-AES NIST SP 800-38A ECB/CBC/OFB/CTR/CFB8/CFB128 NIST SP 800-38D GCM b/ crypto DMA b
AES_DMA_ENABLE_REG AES 17.3-1b
17.3-1.
AES_DMA_ENABLE_REG 0 1
Typical AES DMA-AES
Typical AES DMA-AES 17.4 17.5 b
ESP32-S2 (DSA) AES b AES b
17.4 Typical AES
Typical AES AES AES-128/AES-192/AES-256 6 b AES_MODE_REG 17.4-1b
17.4-1.
AES_MODE_REG[2:0] 0 1 2 4 5 6
AES-128 AES-192 AES-256 AES-128 AES-192 AES-256
AES AES_STATE_REG 17.4-2 17.4-2.
0 1
IDLE WORK
Typical AES AES 11 ~ 15 21 22 b
17.4.1 aa
AES_KEY_n_REG 8 32 b
428
ESP32-S2 TRM ( 1.3)
17 AES (AES)
GoBack
· AES-128 128 AES_KEY_0_REG ~ AES_KEY_3_REG b · AES-192 192 AES_KEY_0_REG ~ AES_KEY_5_REG b · AES-256 256 AES_KEY_0_REG ~ AES_KEY_7_REG b AES_TEXT_IN_m_REG AES_TEXT_OUT_m_REG 4 32 b
· AES-128/192/265 AES_TEXT_IN_m_REGb AES AES_TEXT_OUT_m_REGb
· AES-128/192/256 AES_TEXT_IN_m_REGb AES AES_TEXT_OUT_m_REGb
17.4.2
Typical AES AES 128 block b AES_ENDIAN_REG Bit 2 Bit 3 Bit 4 Bit 5 bBit 2 Bit 4 word 4 byte Bit 3 Bit 5 block 4 word b
AES_ENDIAN_REG AES b 17.4-3 AES_TEXT_IN_m_REG AES_TEXT_OUT_m_REG word Stateb
17.4-3. Typical AES
Word Endian 0 0 1 1
Byte Endian 0 1 0 1
State1
0 1 r 2 3
State
0 1 r 2 3
State
0 1 r 2 3
State
0 1 r 2 3
0 AES_TEXT_x_3_REG[31:24] AES_TEXT_x_3_REG[23:16] AES_TEXT_x_3_REG[15:8] AES_TEXT_x_3_REG[7:0]
0 AES_TEXT_x_3_REG[7:0] AES_TEXT_x_3_REG[15:8] AES_TEXT_x_3_REG[23:16] AES_TEXT_x_3_REG[31:24]
0 AES_TEXT_x_0_REG[31:24] AES_TEXT_x_0_REG[23:16] AES_TEXT_x_0_REG[15:8] AES_TEXT_x_0_REG[7:0]
0 AES_TEXT_x_0_REG[7:0] AES_TEXT_x_0_REG[15:8] AES_TEXT_x_0_REG[23:16] AES_TEXT_x_0_REG[31:24]
/ 2
1 AES_TEXT_x_2_REG[31:24] AES_TEXT_x_2_REG[23:16] AES_TEXT_x_2_REG[15:8] AES_TEXT_x_2_REG[7:0]
1 AES_TEXT_x_2_REG[7:0] AES_TEXT_x_2_REG[15:8] AES_TEXT_x_2_REG[23:16] AES_TEXT_x_2_REG[31:24]
1 AES_TEXT_x_1_REG[31:24] AES_TEXT_x_1_REG[23:16] AES_TEXT_x_1_REG[15:8] AES_TEXT_x_1_REG[7:0]
1 AES_TEXT_x_1_REG[7:0] AES_TEXT_x_1_REG[15:8] AES_TEXT_x_1_REG[23:16] AES_TEXT_x_1_REG[31:24]
c 2 AES_TEXT_x_1_REG[31:24] AES_TEXT_x_1_REG[23:16] AES_TEXT_x_1_REG[15:8] AES_TEXT_x_1_REG[7:0]
c 2 AES_TEXT_x_1_REG[7:0] AES_TEXT_x_1_REG[15:8] AES_TEXT_x_1_REG[23:16] AES_TEXT_x_1_REG[31:24]
c 2 AES_TEXT_x_2_REG[31:24] AES_TEXT_x_2_REG[23:16] AES_TEXT_x_2_REG[15:8] AES_TEXT_x_2_REG[7:0]
c 2 AES_TEXT_x_2_REG[7:0] AES_TEXT_x_2_REG[15:8] AES_TEXT_x_2_REG[23:16] AES_TEXT_x_2_REG[31:24]
3 AES_TEXT_x_0_REG[31:24] AES_TEXT_x_0_REG[23:16] AES_TEXT_x_0_REG[15:8] AES_TEXT_x_0_REG[7:0]
3 AES_TEXT_x_0_REG[7:0] AES_TEXT_x_0_REG[15:8] AES_TEXT_x_0_REG[23:16] AES_TEXT_x_0_REG[31:24]
3 AES_TEXT_x_3_REG[31:24] AES_TEXT_x_3_REG[23:16] AES_TEXT_x_3_REG[15:8] AES_TEXT_x_3_REG[7:0]
3 AES_TEXT_x_3_REG[7:0] AES_TEXT_x_3_REG[15:8] AES_TEXT_x_3_REG[23:16] AES_TEXT_x_3_REG[31:24]
1. "State" NIST FIPS 197 "3.4 The State" b 2.
· x = IN AES_TEXT_IN_m_REG Word Endian Byte Endian AES_ENDIAN_REG Bit 2 Bit 3
· x = OUT AES_TEXT_OUT_m_REG Word Endian Byte Endian AES_ENDIAN_REG Bit 4 Bit 5b
429
ESP32-S2 TRM ( 1.3)
17 AES (AES)
GoBack
Typical AES AES AES_ENDIAN_REG Bit 0 Bit 1 b
17.4-4a 17.4-5a 17.4-6 AES_KEY_n_REG word "the first Nk words of the expanded key"b
430
ESP32-S2 TRM ( 1.3)
17 AES (AES)
AES_ENDIAN_REG[1] 0 0 1 1
AES_ENDIAN_REG[0] 0 1 0 1
Bit2 [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0]
17.4-4. AES-128
w[0] AES_KEY_3_REG[31:24] AES_KEY_3_REG[23:16] AES_KEY_3_REG[15:8] AES_KEY_3_REG[7:0] AES_KEY_3_REG[7:0] AES_KEY_3_REG[15:8] AES_KEY_3_REG[23:16] AES_KEY_3_REG[31:24] AES_KEY_0_REG[31:24] AES_KEY_0_REG[23:16] AES_KEY_0_REG[15:8] AES_KEY_0_REG[7:0] AES_KEY_0_REG[7:0] AES_KEY_0_REG[15:8] AES_KEY_0_REG[23:16] AES_KEY_0_REG[31:24]
w[1] AES_KEY_2_REG[31:24] AES_KEY_2_REG[23:16] AES_KEY_2_REG[15:8] AES_KEY_2_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_2_REG[15:8] AES_KEY_2_REG[23:16] AES_KEY_2_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_1_REG[23:16] AES_KEY_1_REG[15:8] AES_KEY_1_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_1_REG[15:8] AES_KEY_1_REG[23:16] AES_KEY_1_REG[31:24]
w[2] AES_KEY_1_REG[31:24] AES_KEY_1_REG[23:16] AES_KEY_1_REG[15:8] AES_KEY_1_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_1_REG[15:8] AES_KEY_1_REG[23:16] AES_KEY_1_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_2_REG[23:16] AES_KEY_2_REG[15:8] AES_KEY_2_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_2_REG[15:8] AES_KEY_2_REG[23:16] AES_KEY_2_REG[31:24]
w[3]1 AES_KEY_0_REG[31:24] AES_KEY_0_REG[23:16] AES_KEY_0_REG[15:8] AES_KEY_0_REG[7:0] AES_KEY_0_REG[7:0] AES_KEY_0_REG[15:8] AES_KEY_0_REG[23:16] AES_KEY_0_REG[31:24] AES_KEY_3_REG[31:24] AES_KEY_3_REG[23:16] AES_KEY_3_REG[15:8] AES_KEY_3_REG[7:0] AES_KEY_3_REG[7:0] AES_KEY_3_REG[15:8] AES_KEY_3_REG[23:16] AES_KEY_3_REG[31:24]
431
1. w[0] ~ w[3] NIST FIPS 197 "5.2 Key Expansion" "the first Nk words of the expanded key" b 2. Bit w[0] ~ w[3] word b
17.4-5. AES-192
AES_ENDIAN_REG[1] 0 0 1 1
AES_ENDIAN_REG[0] 0 1 0 1
Bit2 [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0]
w[0] AES_KEY_5_REG[31:24] AES_KEY_5_REG[23:16] AES_KEY_5_REG[15:8] AES_KEY_5_REG[7:0] AES_KEY_5_REG[7:0] AES_KEY_5_REG[15:8] AES_KEY_5_REG[23:16] AES_KEY_5_REG[31:24] AES_KEY_0_REG[31:24] AES_KEY_0_REG[23:16] AES_KEY_0_REG[15:8] AES_KEY_0_REG[7:0] AES_KEY_0_REG[7:0] AES_KEY_0_REG[15:8] AES_KEY_0_REG[23:16] AES_KEY_0_REG[31:24]
w[1] AES_KEY_4_REG[31:24] AES_KEY_4_REG[23:16] AES_KEY_4_REG[15:8] AES_KEY_4_REG[7:0] AES_KEY_4_REG[7:0] AES_KEY_4_REG[15:8] AES_KEY_4_REG[23:16] AES_KEY_4_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_1_REG[23:16] AES_KEY_1_REG[15:8] AES_KEY_1_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_1_REG[15:8] AES_KEY_1_REG[23:16] AES_KEY_1_REG[31:24]
w[2] AES_KEY_3_REG[31:24] AES_KEY_3_REG[23:16] AES_KEY_3_REG[15:8] AES_KEY_3_REG[7:0] AES_KEY_3_REG[7:0] AES_KEY_3_REG[15:8] AES_KEY_3_REG[23:16] AES_KEY_3_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_2_REG[23:16] AES_KEY_2_REG[15:8] AES_KEY_2_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_2_REG[15:8] AES_KEY_2_REG[23:16] AES_KEY_2_REG[31:24]
w[3] AES_KEY_2_REG[31:24] AES_KEY_2_REG[23:16] AES_KEY_2_REG[15:8] AES_KEY_2_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_2_REG[15:8] AES_KEY_2_REG[23:16] AES_KEY_2_REG[31:24] AES_KEY_3_REG[31:24] AES_KEY_3_REG[23:16] AES_KEY_3_REG[15:8] AES_KEY_3_REG[7:0] AES_KEY_3_REG[7:0] AES_KEY_3_REG[15:8] AES_KEY_3_REG[23:16] AES_KEY_3_REG[31:24]
w[4] AES_KEY_1_REG[31:24] AES_KEY_1_REG[23:16] AES_KEY_1_REG[15:8] AES_KEY_1_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_1_REG[15:8] AES_KEY_1_REG[23:16] AES_KEY_1_REG[31:24] AES_KEY_4_REG[31:24] AES_KEY_4_REG[23:16] AES_KEY_4_REG[15:8] AES_KEY_4_REG[7:0] AES_KEY_4_REG[7:0] AES_KEY_4_REG[15:8] AES_KEY_4_REG[23:16] AES_KEY_4_REG[31:24]
w[5]1 AES_KEY_0_REG[31:24] AES_KEY_0_REG[23:16] AES_KEY_0_REG[15:8] AES_KEY_0_REG[7:0] AES_KEY_0_REG[7:0] AES_KEY_0_REG[15:8] AES_KEY_0_REG[23:16] AES_KEY_0_REG[31:24] AES_KEY_5_REG[31:24] AES_KEY_5_REG[23:16] AES_KEY_5_REG[15:8] AES_KEY_5_REG[7:0] AES_KEY_5_REG[7:0] AES_KEY_5_REG[15:8] AES_KEY_5_REG[23:16] AES_KEY_5_REG[31:24]
ESP32-S2 TRM ( 1.3)
GoBack
1. w[0] ~ w[5] NIST FIPS 197 "5.2 Key Expansion" "the first Nk words of the expanded key" b 2. Bit w[0] ~ w[5] word b
17 AES (AES)
17.4-6. AES-256
AES_ENDIAN_REG[1] 0 0 1 1
AES_ENDIAN_REG[0] 0 1 0 1
Bit2 [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0]
w[0] AES_KEY_7_REG[31:24] AES_KEY_7_REG[23:16] AES_KEY_7_REG[15:8] AES_KEY_7_REG[7:0] AES_KEY_7_REG[7:0] AES_KEY_7_REG[15:8] AES_KEY_7_REG[23:16] AES_KEY_7_REG[31:24] AES_KEY_0_REG[31:24] AES_KEY_0_REG[23:16] AES_KEY_0_REG[15:8] AES_KEY_0_REG[7:0] AES_KEY_0_REG[7:0] AES_KEY_0_REG[15:8] AES_KEY_0_REG[23:16] AES_KEY_0_REG[31:24]
w[1] AES_KEY_6_REG[31:24] AES_KEY_6_REG[23:16] AES_KEY_6_REG[15:8] AES_KEY_6_REG[7:0] AES_KEY_6_REG[7:0] AES_KEY_6_REG[15:8] AES_KEY_6_REG[23:16] AES_KEY_6_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_1_REG[23:16] AES_KEY_1_REG[15:8] AES_KEY_1_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_1_REG[15:8] AES_KEY_1_REG[23:16] AES_KEY_1_REG[31:24]
w[2] AES_KEY_5_REG[31:24] AES_KEY_5_REG[23:16] AES_KEY_5_REG[15:8] AES_KEY_5_REG[7:0] AES_KEY_5_REG[7:0] AES_KEY_5_REG[15:8] AES_KEY_5_REG[23:16] AES_KEY_5_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_2_REG[23:16] AES_KEY_2_REG[15:8] AES_KEY_2_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_2_REG[15:8] AES_KEY_2_REG[23:16] AES_KEY_2_REG[31:24]
w[3] AES_KEY_4_REG[31:24] AES_KEY_4_REG[23:16] AES_KEY_4_REG[15:8] AES_KEY_4_REG[7:0] AES_KEY_4_REG[7:0] AES_KEY_4_REG[15:8] AES_KEY_4_REG[23:16] AES_KEY_4_REG[31:24] AES_KEY_3_REG[31:24] AES_KEY_3_REG[23:16] AES_KEY_3_REG[15:8] AES_KEY_3_REG[7:0] AES_KEY_3_REG[7:0] AES_KEY_3_REG[15:8] AES_KEY_3_REG[23:16] AES_KEY_3_REG[31:24]
w[4] AES_KEY_3_REG[31:24] AES_KEY_3_REG[23:16] AES_KEY_3_REG[15:8] AES_KEY_3_REG[7:0] AES_KEY_3_REG[7:0] AES_KEY_3_REG[15:8] AES_KEY_3_REG[23:16] AES_KEY_3_REG[31:24] AES_KEY_4_REG[31:24] AES_KEY_4_REG[23:16] AES_KEY_4_REG[15:8] AES_KEY_4_REG[7:0] AES_KEY_4_REG[7:0] AES_KEY_4_REG[15:8] AES_KEY_4_REG[23:16] AES_KEY_4_REG[31:24]
w[5] AES_KEY_2_REG[31:24] AES_KEY_2_REG[23:16] AES_KEY_2_REG[15:8] AES_KEY_2_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_2_REG[15:8] AES_KEY_2_REG[23:16] AES_KEY_2_REG[31:24] AES_KEY_5_REG[31:24] AES_KEY_5_REG[23:16] AES_KEY_5_REG[15:8] AES_KEY_5_REG[7:0] AES_KEY_5_REG[7:0] AES_KEY_5_REG[15:8] AES_KEY_5_REG[23:16] AES_KEY_5_REG[31:24]
w[6] AES_KEY_1_REG[31:24] AES_KEY_1_REG[23:16] AES_KEY_1_REG[15:8] AES_KEY_1_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_1_REG[15:8] AES_KEY_1_REG[23:16] AES_KEY_1_REG[31:24] AES_KEY_6_REG[31:24] AES_KEY_6_REG[23:16] AES_KEY_6_REG[15:8] AES_KEY_6_REG[7:0] AES_KEY_6_REG[7:0] AES_KEY_6_REG[15:8] AES_KEY_6_REG[23:16] AES_KEY_6_REG[31:24]
w[7]1 AES_KEY_0_REG[31:24] AES_KEY_0_REG[23:16] AES_KEY_0_REG[15:8] AES_KEY_0_REG[7:0] AES_KEY_0_REG[7:0] AES_KEY_0_REG[15:8] AES_KEY_0_REG[23:16] AES_KEY_0_REG[31:24] AES_KEY_7_REG[31:24] AES_KEY_7_REG[23:16] AES_KEY_7_REG[15:8] AES_KEY_7_REG[7:0] AES_KEY_7_REG[7:0] AES_KEY_7_REG[15:8] AES_KEY_7_REG[23:16] AES_KEY_7_REG[31:24]
1. w[0] ~ w[7] NIST FIPS 197 "5.2 Key Expansion" "the first Nk words of the expanded key" b 2. Bit w[0] ~ w[7] word b
432
ESP32-S2 TRM ( 1.3)
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17 AES (AES)
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17.4.3 Typical AES
1. AES_DMA_ENABLE_REG 0b 2. AES_MODE_REGaAES_KEY_n_REGaAES_TEXT_IN_m_REGaAES_ENDIAN_REGb 3. b AES_TRIGGER_REG 1b 4. b AES_STATE_REG 0b 5. AES_TEXT_OUT_m_REG b
AES_TEXT_OUT_m_REG (m: 0-3) AES AES_DMA_ENABLE_REGaAES_MODE_REGaAES_KEY_n_REGaAES_ENDIAN_REG bb
1. AES_DMA_ENABLE_REG 0b 2. AES_MODE_REGaAES_KEY_n_REGaAES_ENDIAN_REGb 3. AES_TEXT_IN_m_REGb 4. b AES_TRIGGER_REG 1b 5. b AES_STATE_REG 0b 6. AES_TEXT_OUT_m_REG b 3b
17.5 DMA-AES
DMA-AES AES ECB/CBC/OFB/CTR/CFB8/CFB128 6 GCM b AES_BLOCK_MODE_REG 17.5-1b
17.5-1.
AES_BLOCK_MODE_REG[2:0] 0 1 2 3 4 5 6
ECB (Electronic Code Book) CBC (Cipher Block Chaining) OFB (Output FeedBack) CTR (Counter) CFB8 (8-bit Cipher FeedBack) CFB128 (128-bit Cipher FeedBack) GCM (Galois/Counter Mode)
AES AES_STATE_REG 17.5-2 17.5-2.
0 IDLE
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ESP32-S2 TRM ( 1.3)
17 AES (AES)
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1
WORK
2 DONE
AES DMA-AES b AES_INT_ENA_REG 1 bAES b
17.5.1 aa
AES (in_stream) DMA (out_stream) DMAb
· DMA memory AESbAES DMAbDMA memoryb
· DMA memory AESbAES DMAbDMA memoryb
AES bDMA AES b
AES DMA-AES 128 128 (bit string) o0p 17.5-3 b
17.5-3. TEXT-PADDING
Function : TEXT-PADDING( ) Input : X, bit string. Output : Y = TEXT-PADDING(X), whose length is the nearest integral multiples of 128 bits. Steps
Let us assume that X is a data-stream that can be split into n parts as following: X = X1||X2|| · · · ||Xn-1||Xn Here, the lengths of X1, X2, · · · , Xn-1 all equals to 128 bits, and the length of Xn is t (0<=t<=127). If t = 0, then
TEXT-PADDING(X) = X; If 0 < t <= 127, define a 128-bit block, Xn, and let Xn = Xn||0128-t, then
TEXT-PADDING(X) = X1||X2|| · · · ||Xn-1||Xn = X||0128-t
17.5.2
DMA-AES DMA memory block b DMA 2 block
· 0102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F20 0x0280 memory 17.5-4 b b
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ESP32-S2 TRM ( 1.3)
17 AES (AES)
17.5-4. DMA AES
0x0280 0x0284 0x0288 0x028C 0x0290 0x0294 0x0298 0x029C
0x01 0x05 0x09 0x0D 0x11 0x15 0x19 0x1D
0x0281 0x0285 0x0289 0x028D 0x0291 0x0295 0x0299 0x029D
0x02 0x06 0x0A 0x0E 0x12 0x16 0x1A 0x1E
0x0282 0x0286 0x028A 0x028E 0x0292 0x0296 0x029A 0x029E
0x03 0x07 0x0B 0x0F 0x13 0x17 0x1B 0x1F
0x0283 0x0287 0x028B 0x028F 0x0293 0x0297 0x029B 0x029F
0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20
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DMA PSRAMb PSRAM DMA b 2 DMA (DMA)b
17.5.3
AES CTR INC32 INC128 b AES_INC_SEL_REG 0 1 INC32 INC128 b NIST SP 800-38A oB.1 The Standard Incrementing Functionpb
17.5.4
AES_BLOCK_NUM_REG (Block Number) length(TEXT-PADDING(P ))/128 length(TEXT-PADDING(C))/128b P cplaintextC cciphertextb DMA-AES b
17.5.5
AES_IV_MEM 16 b CBC/OFB/CFB8/CFB128 AES_IV_MEM (Initialization Vector, IV) b CTR AES_IV_MEM (Initial Counter Block, ICB) b IV ICB 128-bit 16 (Byte0, Byte1, Byte2, · · ·, Byte15) AES_IV_MEM 17.5-4 Byte0 AES_IV_MEM Byte15 AES_IV_MEM b IV ICB NIST SP 800-38A b
17.5.6
1. CRYPTO_DMA_AES_SHA_SELECT_REG 0b 2. Crypto DMA DMAb 2 DMA (DMA)b 3. AES
· AES_DMA_ENABLE_REG 1b
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ESP32-S2 TRM ( 1.3)
17 AES (AES)
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· b AES_INT_ENA_REG b · AES_MODE_REGaAES_KEY_n_REGaAES_ENDIAN_REGb · AES_BLOCK_MODE_REG 17.5-1b · AES_BLOCK_NUM_REG 17.5.4b · AES_INC_SEL_REGc CTR b · AES_IV_MEMc ECB b 4. b AES_TRIGGER_REG 1b 5. b AES_STATE_REG 2b AES_INT b 6. DMA AES b DMA memory b 2 DMA (DMA)b 7. AES_INT_CLR_REG 1 b 8. AES_DMA_EXIT_REG 1 AES b AES_STATE_REG 0b 5 b
17.5.7 GCM
1. CRYPTO_DMA_AES_SHA_SELECT_REG 0b 2. Crypto DMA DMAb 2 DMA (DMA)b 3. AES
· AES_DMA_ENABLE_REG 1b · b AES_INT_ENA_REG b · AES_MODE_REGaAES_KEY_n_REGaAES_ENDIAN_REGb · AES_BLOCK_MODE_REG 6b · AES_BLOCK_NUM_REG 17.5.4b · AES_AAD_BLOCK_NUM_REG 17.6.4b · AES_REMAINDER_BIT_NUM_REG 17.6.5bb 4. b AES_TRIGGER_REG 1b 5. AES_STATE_REG 0b 17.5-2bb 6. AES_H_MEM Hb 7. J0 AES_J0_MEMb 8. b AES_CONTINUE_OP_REG 1b 9. b AES_STATE_REG 2b 17.5-2b AES_INT b 10. T0 b AES_T0_MEM T0b
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ESP32-S2 TRM ( 1.3)
17 AES (AES)
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11. DMA b DMA memoryb 2 DMA (DMA)b
12. AES_INT_CLR_REG 1 b
13. AES_DMA_EXIT_REG 1b AES_STATE_REG 0b 9 b
17.6 GCM
ESP32-S2 AES GCM c NIST SP 800-38D b 232 - 1 AAD aC P AAD aC P 232 - 1 b 17.6-1 ESP32-S2 AES GCM b
17.6-1. GCM
1. ECB (H) 2. GHASH AAD 3. INC32 J0 CTR 4. GCTR P GHASH C 5. GHASH 128
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ESP32-S2 TRM ( 1.3)
17 AES (AES)
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6. GCTR J0 T0 7. T0 MSBt T b GCM GCM 17.6-1 4 GCTR bb
17.6.1 cHash subkey
GCM (H) 128-bit 17.6-1 1 NIST SP 800-38D o7 GCM SpecificationpoStep 1. Let H = CIPHK (0128) pb (H) AES_H_MEM 17.5-4 AES_H_MEM AES_H_MEM b
17.6.2 J0
GCM J0 128-bit 17.6-1 3 6 b NIST SP 800-38D o7 GCM Specificationpb NIST SP 800-38D b J0 AES_J0_MEM 17.5-4 AES_J0_MEM AES_J0_MEM b
17.6.3 cAuthenticated Tag
cAuthenticated Tag Tag GCM 17.6-1 7 t (1 <= t <= 128)
· t = 128 Tag T0bT0 128-bit AES_T0_MEM 17.5-4 AES_T0_MEM AES_T0_MEM b
· 1 <= t < 128 Tag T0 t MSBt(T0) b MSB4(111011010) = 1110MSB5(11010011010) = 11010b MSBt( ) NIST SP 800-38D o6 Mathematical Components of GCMpb
17.6.4 cAAD Block Number
AES_AAD_BLOCK_NUM_REG cAdditional Authenticated Data, AAD length(TEXT-PADDING(AAD))/128b DMA-AES GCM b
17.6.5 (Remainder Bit Number)
AES_REMAINDER_BIT_NUM_REG length(P )%128b DMA-AES GCM b AES_REMAINDER_BIT_NUM_REG Tag c T0 b GCM GCM GCTR GHASH GCTR GHASH Tagb
· GCM C TEXT-PADDING(C) GHASH b AES_REMAINDER_BIT_NUM_REG 0 b
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ESP32-S2 TRM ( 1.3)
17 AES (AES)
· GCM TEXT-PADDING(C) AES_REMAINDER_BIT_NUM_REG b
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17.7
AES 17.7-1 b 3 b
17.7-1. AES
PeriBUS1 PeriBUS2
0x3F43A000 0x6003A000
17.8
AES cb 17.7 AES b
17.8-1. AES
AES_IV_MEM AES_H_MEM AES_J0_MEM AES_T0_MEM
IV H J0 T0
c 16 0x0050 16 0x0060 16 0x0070 16 0x0080
0x005F 0x006F 0x007F 0x008F
/ /
17.9
AES cb 17.7 AES b
AES_KEY_0_REG AES_KEY_1_REG AES_KEY_2_REG AES_KEY_3_REG AES_KEY_4_REG AES_KEY_5_REG AES_KEY_6_REG AES_KEY_7_REG TEXT_IN AES_TEXT_IN_0_REG
AES 0 AES 1 AES 2 AES 3 AES 4 AES 5 AES 6 AES 7
0
0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C
0x0020
/ / / / / / / /
/
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ESP32-S2 TRM ( 1.3)
17 AES (AES)
AES_TEXT_IN_1_REG AES_TEXT_IN_2_REG AES_TEXT_IN_3_REG TEXT_OUT AES_TEXT_OUT_0_REG AES_TEXT_OUT_1_REG AES_TEXT_OUT_2_REG AES_TEXT_OUT_3_REG AES_MODE_REG AES_ENDIAN_REG AES_DMA_ENABLE_REG AES_BLOCK_MODE_REG AES_BLOCK_NUM_REG AES_INC_SEL_REG AES_AAD_BLOCK_NUM_REG AES_REMAINDER_BIT_NUM_REG AES_TRIGGER_REG AES_STATE_REG AES_CONTINUE_OP_REG AES_DMA_EXIT_REG AES_INT_CLR_REG AES_INT_ENA_REG
1 2 3
0 1 2 3
DMA AAD
DMA-AES DMA-AES
0x0024 0x0028 0x002C
0x0030 0x0034 0x0038 0x003C
0x0040 0x0044 0x0090 0x0094 0x0098 0x009C 0x00A0 0x00A4
0x0048 0x004C 0x00A8 0x00B8
0x00AC 0x00B0
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/ / /
/ / / / / / / /
/
17.10
Register 17.1. AES_KEY_n_REG (n: 0-7) (0x0000+4*n)
31
0x000000000
AES_KEY_n_REG (n: 0-7) AES bc/
0
Reset
Register 17.2. AES_TEXT_IN_m_REG (m: 0-3) (0x0020+4*m)
31
0x000000000
AES_TEXT_IN_m_REG (m: 0-3) Typical AES bc/
0
Reset
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ESP32-S2 TRM ( 1.3)
17 AES (AES)
Register 17.3. AES_TEXT_OUT_m_REG (m: 0-3) (0x0030+4*m)
31
0x000000000
AES_TEXT_OUT_m_REG (m: 0-3) Typical AES bc
GoBack
0
Reset
Register 17.4. AES_MODE_REG (0x0040)
(reserved)
31
0x00000000
AES_MODE AES b 17.4-1bc/
AES_MODE
32
0
0
Reset
Register 17.5. AES_ENDIAN_REG (0x0044)
(reserved)
31
0x0000000
AES_ENDIAN b 17.4-3bc/
AES_ENDIAN
65
0
0 0 0 0 0 0 Reset
Register 17.6. AES_DMA_ENABLE_REG (0x0090)
(reserved)
31
0x00000000
AES_DMA_ENABLE b 17.3-1bc/
AES_DMA_ENABLE
10
0 Reset
441
ESP32-S2 TRM ( 1.3)
17 AES (AES)
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Register 17.7. AES_BLOCK_MODE_REG (0x0094)
(reserved)
31
0x00000000
AES_BLOCK_MODE DMA-AES b 17.5-1bc/
AES_BLOCK_MODE
32
0
0
Reset
Register 17.8. AES_BLOCK_NUM_REG (0x0098)
AES_BLOCK_NUM
31
0
0x00000000
Reset
AES_BLOCK_NUM DMA-AES b 17.5.4bc/
Register 17.9. AES_INC_SEL_REG (0x009C)
(reserved)
AES_INC_SEL
31
10
0x00000000
0 Reset
AES_INC_SEL CTR b 0 INC32 1 INC128 bc/
Register 17.10. AES_AAD_BLOCK_NUM_REG (0x00A0)
31
0x00000000
AES_AAD_BLOCK_NUM GCM AAD b 17.6.4bc/
0
Reset
442
ESP32-S2 TRM ( 1.3)
17 AES (AES)
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Register 17.11. AES_REMAINDER_BIT_NUM_REG (0x00A4)
(reserved)
AES_REMAINDER_BIT_NUM
31
76
0
0x0000000
0
Reset
AES_REMAINDER_BIT_NUM GCM b 17.6.5bc/
Register 17.12. AES_TRIGGER_REG (0x0048)
(reserved)
31
0x00000000
AES_TRIGGER 1 AES bc
AES_TRIGGER
10
x Reset
Register 17.13. AES_STATE_REG (0x004C)
(reserved)
AES_STATE
31
21
0
0x00000000
0x0 Reset
AES_STATE AES b 17.4-2cTypical AES 17.5-2cDMA-AES bc
Register 17.14. AES_CONTINUE_OP_REG (0x00A8)
(reserved)
31
0x00000000
AES_CONTINUE_OP GCM 1 bc
AES_CONTINUE
10
x Reset
443
ESP32-S2 TRM ( 1.3)
17 AES (AES)
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Register 17.15. AES_DMA_EXIT_REG (0x00B8)
(reserved)
AES_DMA_EXIT
31
10
0x00000000
x Reset
AES_DMA_EXIT DMA-AES AES 1 AES bc
Register 17.16. AES_INT_CLR_REG (0x00AC)
(reserved)
31
0x00000000
AES_INT_CLR 1 AES bc
AES_INT_CLR
10
0 Reset
Register 17.17. AES_INT_ENA_REG (0x00B0)
(reserved)
31
0x00000000
AES_INT_ENA 1 AES 0 AES bc/
AES_INT_ENA
10
0 Reset
444
ESP32-S2 TRM ( 1.3)
18 RSA (AES)
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18
RSA (AES)
18.1
RSA oRSA p opb
18.2
RSA · c · · · ·
18.3
RSA SYSTEM_PERIP_CLK_EN1_REG SYSTEM_CRYPTO_RSA_CLK_EN SYSTEM_RSA_PD_CTRL_REG SYSTEM_RSA_MEM_PD b RSA RSA b RSA_CLEAN_REG 0 1 b RSA RSA_CLEAN_REG 1 RSA b RSA RSA_INTERRUPT_ENA_REG 1 / 0 / bRSA b
ESP32-S2 (DSA) RSA b RSA b
18.3.1
Z = XY mod M Montgomery Multiplication cb XaY aM r M b b
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ESP32-S2 TRM ( 1.3)
18 RSA (AES)
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RSA N = 32 × x (x {1, 2, 3, . . . , 128}) bZaXaY aM r 128 M 32b
b = 232
b N
n= 32
Z = (Zn-1Zn-2 · · · Z0)b X = (Xn-1Xn-2 · · · X0)b Y = (Yn-1Yn-2 · · · Y0)b M = (Mn-1Mn-2 · · · M0)b
r = (rn-1rn-2 · · · r0)b
Zn-1 · · · Z0aXn-1 · · · X0aYn-1 · · · Y0aMn-1 · · · M0arn-1 · · · r0 b 32b Zn-1aXn-1aYn-1aMn-1arn-1 ZaXaY aM ar b Z0aX0aY0aM0ar0 ZaXaY aM ar b b R = bn r = R2 mod M b M
M -1 × M + 1 = R × R-1 M = M -1 mod b
GCD b
1. RSA_INTERRUPT_ENA_REG 1 / 0 / b
2. b
(a)
RSA_MODE_REG
(
N 32
- 1)b
(b) RSA_M_PRIME_REG M b
(c) b 18.3.4 b
3. XiaYiaMiari(i {0, 1, . . . , n}) RSA_X_MEMaRSA_Y_MEMaRSA_M_MEMa RSA_Z_MEMb 128 (word)b b b b
b
4. RSA_MODEXP_START_REG 1 b
5. b RSA_IDLE_REG 1 RSA b
6. RSA_Z_MEM Zi(i {0, 1, . . . , n} )b
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ESP32-S2 TRM ( 1.3)
18 RSA (AES)
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7. RSA_CLEAR_INTERRUPT_REG 1 b
RSA_MODE_REG RSA_Y_MEM Yia RSA_M_MEM Mia RSA_M_PRIME_REG M b RSA_X_MEM Xi RSA_Z_MEM ri b b
18.3.2
Montgomery Multiplication Z = X × Y mod M r M b
RSA 128 b
1. RSA_INTERRUPT_ENA_REG 1 / 0 / b
2. b
(a)
RSA_MODE_REG
(
N 32
- 1)b
(b) RSA_M_PRIME_REG M b
3. XiaYiaMiari (i {0, 1, . . . , n}) RSA_X_MEMaRSA_Y_MEMaRSA_M_MEMa RSA_Z_MEMb 128 (word)b
b b b
b
4. RSA_MODMULT_START_REG 1b
5. b RSA_IDLE_REG 1 RSA b
6. RSA_Z_MEM Zi (i {0, 1, . . . , n})b 7. RSA_CLEAR_INTERRUPT_REG 1 b
RSA_MODE_REG RSA_X_MEM Xia RSA_Y_MEM Yia RSA_M_MEM Mia RSA_M_PRIME_REG M b RSA_Z_MEM ri b b
18.3.3
Z = X × Y b Z XaY b RSA N = 32 × x (x {1, 2, . . . , 64}) b Z N^ 2 × N b
1. RSA_INTERRUPT_ENA_REG 1 / 0 / b
2.
b
RSA_MODE_REG
(
N^ 32
-
1)
(
N 16
- 1)b
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ESP32-S2 TRM ( 1.3)
18 RSA (AES)
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3. XiaYi (i {0, 1, . . . , n}) RSA_X_MEMaRSA_Z_MEMb 128
b b b
bn
N 32
b
Xi (i {0, 1, . . . , n}) RSA_X_MEM i Yi (i {0, 1, . . . , n}) RSA_Z_MEM i RSA_Z_MEM n + i RSA_Z_MEM 4 × (n + i)b
b
4. RSA_MULT_START_REG 1b
5. b RSA_IDLE_REG 1 RSA b
6. RSA_Z_MEM Zi (i {0, 1, . . . , n})bn^ 2 × n b 7. RSA_CLEAR_INTERRUPT_REG 1 b
RSA_MODE_REG RSA_X_MEM Xi b RSA_Z_MEM Yi b b
18.3.4
ESP32-S2 RSA SEARCH CONSTANT_TIME bb
Z = XY mod M b Y 0/1 b
Y
Y = (YN-1YN-2 · · · Yt+1YtYt-1 · · · Y0)2
· N Y
· Yt 1 · YN-1, YN-2, ..., Yt+1 0 · Yt-1, Yt-2, ..., Y0 m 0 t-m 1 Yt-1Yt-2, · · · , Y0 (Hamming
weight) t - mb
· SEARCH
RSA Yici > b RSA_SEARCH_POS_REG b N -1 t Z = XY mod M b t bYN-1, YN-2, ..., Yt+1 0 b
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ESP32-S2 TRM ( 1.3)
18 RSA (AES)
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· CONSTANT_TIME
RSA Y 0 bY 0 b
b Z = XY mod M N 3072Y 65537b 18.3-1 4 b b SEARCH 16b
18.3-1.
SEARCH
CONSTANT_TIME
376.405 ms
2.260 ms 1.203 ms 1.165 ms
0%
99.41% 99.68% 99.69%
18.4
RSA 18.4-1 b 3 b
18.4-1. RSA
PeriBUS1 PeriBUS2
0x3F43C000 0x6003C000
18.5
RSA cb 18.4 RSA b
18.5-1. RSA
RSA_M_MEM RSA_Z_MEM RSA_Y_MEM RSA_X_MEM
M Z Y X
c 512 0x0000 512 0x0200 512 0x0400 512 0x0600
0x01FF 0x03FF 0x05FF 0x07FF
/
18.6
RSA cb 18.4 RSA b
449
ESP32-S2 TRM ( 1.3)
18 RSA (AES)
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RSA_M_PRIME_REG RSA_MODE_REG RSA_CONSTANT_TIME_REG RSA_SEARCH_ENABLE_REG RSA_SEARCH_POS_REG / RSA_CLEAN_REG RSA_MODEXP_START_REG RSA_MODMULT_START_REG RSA_MULT_START_REG RSA_IDLE_REG RSA_CLEAR_INTERRUPT_REG RSA_INTERRUPT_ENA_REG RSA_DATE_REG
M' RSA search search
RSA RSA
RSA RSA
RSA
0x0800 0x0804 0x0820 0x0824 0x0828
0x0808 0x080C 0x0810 0x0814 0x0818
0x081C 0x082C
0x0830
/ / / / /
/
/
18.7
RSA cb 18.4 RSA b
Register 18.1. RSA_M_PRIME_REG (0x0800)
31
0x000000000
0
Reset
RSA_M_PRIME_REG M'bc/
Register 18.2. RSA_MODE_REG (0x0804)
(reserved)
RSA_MODE
31
76
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RSA_MODE bc/
450
ESP32-S2 TRM ( 1.3)
18 RSA (AES)
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Register 18.3. RSA_CLEAN_REG (0x0808)
(reserved)
RSA_CLEAN
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RSA_CLEAN 1bc
Register 18.4. RSA_MODEXP_START_REG (0x080C)
(reserved)
RSA_MODEXP_START
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RSA_MODEXP_START 1 bc
Register 18.5. RSA_MODMULT_START_REG (0x0810)
(reserved)
RSA_MODMULT_START
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RSA_MODMULT_START 1 bc
Register 18.6. RSA_MULT_START_REG (0x0814)
(reserved)
RSA_MULT_START
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RSA_MULT_START 1 bc
451
ESP32-S2 TRM ( 1.3)
18 RSA (AES)
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Register 18.7. RSA_IDLE_REG (0x0818)
(reserved)
RSA_IDLE
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RSA_IDLE RSA 1bc
Register 18.8. RSA_CLEAR_INTERRUPT_REG (0x081C)
(reserved)
RSA_CLEAR_INTERRUPT
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RSA_CLEAR_INTERRUPT RSA b 1 bc
Register 18.9. RSA_CONSTANT_TIME_REG (0x0820)
(reserved)
RSA_CONSTANT_TIME
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset
RSA_CONSTANT_TIME_REG constant_time b01ccb/
Register 18.10. RSA_SEARCH_ENABLE_REG (0x0824)
(reserved)
RSA_SEARCH_ENABLE
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RSA_SEARCH_ENABLE search b10cbc/
452
ESP32-S2 TRM ( 1.3)
18 RSA (AES)
GoBack
Register 18.11. RSA_SEARCH_POS_REG (0x0828)
(reserved)
31
12 11
00000000000000000000
RSA_SEARCH_POS 0x000
0
Reset
RSA_SEARCH_POS search b search c/b
Register 18.12. RSA_INTERRUPT_ENA_REG (0x082C)
(reserved)
RSA_INTERRUPT_ENA
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset
RSA_INTERRUPT_ENA RSA b 1 bc/
(reserved)
31 30 29
00
Register 18.13. RSA_DATE_REG (0x0830)
RSA_DATE 0x20190425
RSA_DATE c/b
0
Reset
453
ESP32-S2 TRM ( 1.3)
19 HMAC (HMAC)
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19 HMAC (HMAC)
19.1
RFC 2104 ,HMAC hash (MAC)b hash SHA-256 256-bit HMAC eFuse b HMAC opopbop HMAC opHMAC (KDF)b
19.2
· HMAC-SHA-256 · HMAC hash c · - · c · JTAGc
19.3
19.3.1
HMAC b eFuse cb HMAC-SHA-256 -b -
· A M · A M B · B HMAC c M A · A HMAC c M · A b B 1. 256-bit HMAC eFuse
EFUSE_KEY_PURPOSE_HMAC_UPb 4b
454
ESP32-S2 TRM ( 1.3)
19 HMAC (HMAC)
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2. eFuse bb HMAC
1. HMAC b 2. b 3. HMAC b 19.3.5b
19.3.2 JTAG
eFuse memory JTAG EFUSE_HARD_DIS_JTAG EFUSE_SOFT_DIS_JTAGb 1JTAG 1JTAG b 4b
EFUSE_SOFT_DIS_JTAG HMAC JTAGb
1. 256-bit HMAC eFuse EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG EFUSE_KEY_PURPOSE_HMAC_DOWN_ALLb EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL DS JTAG b
2. eFuse b b
3. EFUSE_SOFT_DIS_JTAG 1b
JTAG
1. SHA-256 32 0x00 HMAC SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 ~ SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 b
2. HMAC , TJAG b
3. HMAC SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 ~ SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 JTAG bJTAG b
4. 1 HMAC_SET_INVALIDATE_JTAG_REG JTAG 3 b
19.3.5b
19.3.3
(DS) AES-CBC bHMAC (KDF) AES b
1. 256-bit HMAC eFuse
455
ESP32-S2 TRM ( 1.3)
19 HMAC (HMAC)
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EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE EFUSE_KEY_PURPOSE_HMAC_DOWN_ALLb EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL DS JTAG b
2. eFuse bb
DS HMAC DS b DS b 20b
19.3.4 HMAC eFuse
HMAC eFuse HMAC b
HMAC
HMAC 3 JTAG DS HMAC b 19.3-1 HMAC_SET_PARA_PURPOSE_REGc 19.3.5b
19.3-1. HMAC
JTAG DS HMAC JTAG DS
6 7 8 5
EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE EFUSE_KEY_PURPOSE_HMAC_UP EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL
eFuse
eFuse 6 KEY0 ~ 5 b n HMAC_SET_PARA_KEY_REG KEYn HMAC b
eFuse memory HMAC KEYn HMAC b
4b
KEY3 KEY_PURPOSE_3 6 (EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG) 19.3-1 KEY3 JTAG b HMAC_SET_PARA_PURPOSE_REG 6HMAC JTAG b
19.3.5 HMAC c
ESP32-S2 HMAC 1. HMAC (a) HMAC SHA b (b) 1 HMAC_SET_START_REGb
456
ESP32-S2 TRM ( 1.3)
19 HMAC (HMAC)
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2. HMAC
(a) m HMAC_SET_PARA_PURPOSE_REGb 4.3-2 m 19.3.4b
(b) n HMAC_SET_PARA_KEY_REG eFuse memory KEYn cn 0 - 5 19.3.4b
(c) 1 HMAC_SET_PARA_FINISH_REGb
(d) HMAC_QUERY_ERROR_REGb 1 0 b
(e) HMAC_SET_PARA_PURPOSE_REG 8 HMAC 3 8 HMAC 4b
3.
(a) HMAC_QUERY_BUSY_REG 0 HMAC b
(b) JTAG DS b 1 HMAC_SET_INVALIDATE_JTAG_REG JTAG 1 HMAC_SET_INVALIDATE_DS_REG b
(c) b
4. Block_ncn >= 1
(a) HMAC_QUERY_BUSY_REG 0 b
(b) 512-bit Block_n HMAC_WDATA0~15_REG 1 HMAC_SET_MESSAGE_ONE_REGHMAC b
(c) HMAC_QUERY_BUSY_REG 0 b
(d) 512 b
· 512 3
i. Block_n+1 1 HMAC_SET_MESSAGE_ING_REG n = n + 1 4.(b)b
ii. Block_n SHA 1 HMAC_SET_MESSAGE_END_REG 6b
iii. Block_n SHA 1 HMAC_SET_MESSAGE_PAD_REG 5b
· 512 3 b SHA 512 b
i. Block_n n = 1 Block_1 1 HMAC_ONE_BLOCK_REG 6b
ii. Block_n 1 HMAC_SET_MESSAGE_PAD_REG 5b
457
ESP32-S2 TRM ( 1.3)
19 HMAC (HMAC)
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iii. Block_n 1 HMAC_SET_MESSAGE_ING_REG n = n + 1 4.(b)b
5. SHA (a) 19.4.1 SHA HMAC_WDATA0~15_REG 1 HMAC_SET_MESSAGE_ONE_REGHMAC b (b) 6b
6. hash (a) HMAC_QUERY_BUSY_REG 0 b (b) HMAC_RDATA0~7_REG hash b (c) 1 HMAC_SET_RESULT_FINISH_REGb
DS HMAC SHA b HMAC SHA CPU DS b
19.4 HMAC
19.4.1
HMAC SHA-256 HASH b 512 SHA-256 bSHA-256 oFIPS PUB 180-4po5.1 Padding the Messagepb 19.4-1 m
1. 1 o1pb 2. k o0pbk m + 1 + k448(mod512) b 3. 64 b m
b
19.4-1. HMAC
b 512 SHA 512 SHA b 19.3.5b
458
ESP32-S2 TRM ( 1.3)
19 HMAC (HMAC)
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19.4.2 HMAC
HMAC 19.4-2 b RFC 2104 HMAC b
19.4-2. HMAC
19.4-2 1. ipad 64 0x36 512-bit b 2. opad 64 0x5c 512-bit b
HMAC 256-bit K 256-bit 0 512-bit K0b K0 ipad 512-bit S1b 512 512-bit S1 SHA-256 256-bit H1b HMAC K0 opad S2 256-bit hash 512-bit S2 768-bit 19.4.1 SHA 1024-bit SHA-256 hash b
19.5
HMAC 19.5-1 b 3 b
19.5-1. HMAC
PeriBUS1 PeriBUS2
0x3F43E000 0x6003E000
459
ESP32-S2 TRM ( 1.3)
19 HMAC (HMAC)
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19.6
()b 19.5 b
Control/Status Registers HMAC_SET_START_REG HMAC_SET_PARA_FINISH_REG HMAC_SET_MESSAGE_ONE_REG HMAC_SET_MESSAGE_ING_REG HMAC_SET_MESSAGE_END_REG HMAC_SET_RESULT_FINISH_REG HMAC_SET_INVALIDATE_JTAG_REG HMAC_SET_INVALIDATE_DS_REG HMAC_QUERY_ERROR_REG HMAC_QUERY_BUSY_REG configuration Registers HMAC_SET_PARA_PURPOSE_REG HMAC_SET_PARA_KEY_REG HMAC Message Block HMAC_WR_MESSAGE_0_REG HMAC_WR_MESSAGE_1_REG HMAC_WR_MESSAGE_2_REG HMAC_WR_MESSAGE_3_REG HMAC_WR_MESSAGE_4_REG HMAC_WR_MESSAGE_5_REG HMAC_WR_MESSAGE_6_REG HMAC_WR_MESSAGE_7_REG HMAC_WR_MESSAGE_8_REG HMAC_WR_MESSAGE_9_REG HMAC_WR_MESSAGE_10_REG HMAC_WR_MESSAGE_11_REG HMAC_WR_MESSAGE_12_REG HMAC_WR_MESSAGE_13_REG HMAC_WR_MESSAGE_14_REG HMAC_WR_MESSAGE_15_REG HMAC Upstream Result HMAC_RD_RESULT_0_REG HMAC_RD_RESULT_1_REG HMAC_RD_RESULT_2_REG HMAC_RD_RESULT_3_REG HMAC_RD_RESULT_4_REG HMAC_RD_RESULT_5_REG
HMAC HMAC HMAC HMAC HMAC HMAC JTAG HMAC
HMAC HMAC
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Hash 0 Hash 1 Hash 2 Hash 3 Hash 4 Hash 5
0x0040 0x004C 0x0050 0x0054 0x0058 0x005C 0x0060 0x0064 0x0068 0x006C
0x0044 0x0048
0x0080 0x0084 0x0088 0x008C 0x0090 0x0094 0x0098 0x009C 0x00A0 0x00A4 0x00A8 0x00AC 0x00B0 0x00B4 0x00B8 0x00BC
0x00C0 0x00C4 0x00C8 0x00CC 0x00D0 0x00D4
460
ESP32-S2 TRM ( 1.3)
19 HMAC (HMAC)
HMAC_RD_RESULT_6_REG HMAC_RD_RESULT_7_REG Control/Status Registers HMAC_SET_MESSAGE_PAD_REG HMAC_ONE_BLOCK_REG Version Register HMAC_DATE_REG
Hash 6 Hash 7
One block
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0x00D8 0x00DC
0x00F0 0x00F4
0x00F8
19.7
Register 19.1. HMAC_SET_START_REG (0x0040)
(reserved)
HMAC_SET_START
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
HMAC_SET_START 1 HMACbc
Register 19.2. HMAC_SET_PARA_FINISH_REG (0x004C)
(reserved)
HMAC_SET_PARA_END
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
HMAC_SET_PARA_END 1 HMAC bc
461
ESP32-S2 TRM ( 1.3)
19 HMAC (HMAC)
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Register 19.3. HMAC_SET_MESSAGE_ONE_REG (0x0050)
(reserved)
HMAC_SET_TEXT_ONE
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
HMAC_SET_TEXT_ONE SHA bc
Register 19.4. HMAC_SET_MESSAGE_ING_REG (0x0054)
(reserved)
HMAC_SET_TEXT_ING
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
HMAC_SET_TEXT_ING 1 bc
Register 19.5. HMAC_SET_MESSAGE_END_REG (0x0058)
(reserved)
HMAC_SET_TEXT_END
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
HMAC_SET_TEXT_END 1 bc
Register 19.6. HMAC_SET_RESULT_FINISH_REG (0x005C)
(reserved)
HMAC_SET_RESULT_END
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
HMAC_SET_RESULT_END 1 bc
462
ESP32-S2 TRM ( 1.3)
19 HMAC (HMAC)
GoBack
Register 19.7. HMAC_SET_INVALIDATE_JTAG_REG (0x0060)
(reserved)
HMAC_SET_INVALIDATE_JTAG
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
HMAC_SET_INVALIDATE_JTAG 1 JTAG bc
Register 19.8. HMAC_SET_INVALIDATE_DS_REG (0x0064)
(reserved)
HMAC_SET_INVALIDATE_DS
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
HMAC_SET_INVALIDATE_DS 1 DS bc
Register 19.9. HMAC_QUERY_ERROR_REG (0x0068)
(reserved)
HMAC_QUREY_CHECK
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
HMAC_QUREY_CHECK HMAC b0: HMAC b1: bc
463
ESP32-S2 TRM ( 1.3)
19 HMAC (HMAC)
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Register 19.10. HMAC_QUERY_BUSY_REG (0x006C)
(reserved)
HMAC_BUSY_STATE
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
HMAC_BUSY_STATE HMAC opb1'b0: 1'b1: c
Register 19.11. HMAC_SET_PARA_PURPOSE_REG (0x0044)
(reserved)
31
43
0000000000000000000000000000
HMAC_PURPOSE_SET
0
0
Reset
HMAC_PURPOSE_SET HMAC bc
Register 19.12. HMAC_SET_PARA_KEY_REG (0x0048)
(reserved)
31
32
00000000000000000000000000000
HMAC_KEY_SET
0
0
Reset
HMAC_KEY_SET HMAC bc
Register 19.13. HMAC_WR_MESSAGE_n_REG (n: 0-15) (0x0080+4*n)
HMAC_WDATA_0
31
0
HMAC_WDATA_n n 32 bc
0
Reset
464
ESP32-S2 TRM ( 1.3)
19 HMAC (HMAC)
Register 19.14. HMAC_RD_RESULT_n_REG (n: 0-7) (0x00C0+4*n)
HMAC_RDATA_0
31
0
HMAC_RDATA_n hash n 32 bc
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0
Reset
Register 19.15. HMAC_SET_MESSAGE_PAD_REG (0x00F0)
(reserved)
HMAC_SET_TEXT_PAD
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
HMAC_SET_TEXT_PAD 1 bc
Register 19.16. HMAC_ONE_BLOCK_REG (0x00F4)
(reserved)
HMAC_SET_ONE_BLOCK
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
HMAC_SET_ONE_BLOCK 1 bc
(reserved)
31 30 29
00
Register 19.17. HMAC_DATE_REG (0x00F8)
HMAC_DATE 0x20190402
HMAC_DATE bc
0
Reset
465
ESP32-S2 TRM ( 1.3)
20 (DSA)
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20
(DSA)
20.1
ab b ESP32-S2 (DS) RSA RSA b
20.2
· RSA 4096 · DS · SHA-256
20.3
20.3.1
DS RSA Z = XY mod M Z X Y M RSA b flash b DS HMAC eFuse HMAC b DS b X DS b Zb
20.3.2
Y c M cb RSA c 4096 b DS b r M b Y M b Y aM ar M C b C DS b 20.3.4b DS RSA Z = XY mod M 18 RSA (AES) 18.3.1 b
466
ESP32-S2 TRM ( 1.3)
20 (DSA)
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20.3.3
b
· 1s
o1p s b
· [x]s s b x (x < 2s)bx [Y ]4096 [0x0C]8b[x] 0 s b[0x5]4 = 0101[0x5]8 = 00000101[0x5]16 = 0000010100000000[0x13]8 = 00010011 [0x13]16 = 0001001100000000b
· ||
b
20.3.4
DS · 20.3.2 RSA (Y , M ) r M b · 256 HMAC ([HM AC_KEY ]256) eFuse bHMAC HMAC DS_KEY = HMAC-SHA256([HM AC_KEY ]256, 1256) RSA b 19 HMAC (HMAC)b · C 1584 b
b
1 Y, M, [KEY]256 [IV]128
2
¯r , M'
3
Y, M, ¯r
4
SHA256 MD
5
[P]12672
6
CBC C
12
Z
11
RSA
10
MD
9
SHA256 CALC_MD
8
[P]12672
7
CBC
[C]12672 X IV
[C]12672 X IV
20.3-1.
20.3-1 C b 20.3-1 Cb
467
ESP32-S2 TRM ( 1.3)
20 (DSA)
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·
1 Y
M b [L]32
=
N 32
- 1c RSA 4096
[L]32 == [0x80-1]32b [DS_KEY ]256 [IV ]128 AES-CBC
b AES 17 AES (AES)b
· 2 M r M b
· 3 Y aM r [Y ]4096a[M ]4096 [r]4096b Y aM r 4096 4096 4096 4096 b
· 4 SHA-256 MD [M D]256 = SHA256 ( [Y ]4096||[M ]4096||[r]4096||[M ]32||[L]32||[IV ]128)
· 5 [P ]12672 = ( [Y ]4096||[M ]4096||[r]4096||[M D]256||[M ]32||[L]32||[]64) []64 PKCS#7 8 0x08 64 [0x0808080808080808]64 P 128 b
· 6 C = [C]12672 = AES-CBC-ENC ([P ]12672, [DS_KEY ]256, [IV ]128)bC RSA Y aM araM L MD []64 b 20.3.4 DS_KEY eFuse HM AC_KEY b
20.3.5
b Ca X IV b
DS 20.3.4 C b
1. 20.3-1 7 8
20.3-1 6 bDS AES CBC C b P = AES-CBC-DEC (C, DS_KEY , IV ) IV [IV ]128[DS_KEY ]256 HMAC eFuse HM AC_KEY b 19 HMAC (HMAC) b
DS P [Y ]4096a[M ]4096a[r]4096a[M ]32a[L]32aMD []64 5 b
2. 20.3-1 9 10
DS MD (padding) b MD 20.3-1 b
· MD iiDS SHA-256 [CALC_M D]256c 4 [CALC_M D]256 MD [M D]256 MD b
· iiDS []64 PKCS#7 b
MD DS DS b DS b
3. 20.3-1 11 12
DS X Y aM r M XY mod M b L bDS RSA Z = XY mod M Z b
468
ESP32-S2 TRM ( 1.3)
20 (DSA)
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20.3.6 DS
b Ca X IV b 20.3.5 b
1. DS DS_SET_START_REG 1b 2. DS_KEY DS_QUERY_BUSY_REG 0b
DS_QUERY_BUSY_REG 1 ms 0 HMAC b DS_QUERY_KEY_WRONG_REGb
· HMAC b
· (1 ~ 15) HMAC DS DS_KEY b
3. IV block DS_IV_m_REG (m: 0-3)b IV block 17 AES (AES)b
4. X DS_X_MEM Xi (i [0, n) N) DS_X_MEM 128 (word)b b b b X 128 DS_X_MEM b
5. C DS_C_MEM Ci (i [0, 396) N) DS_C_MEM 396 b b b
6. DS_SET_ME_REG 1b 7. DS_QUERY_BUSY_REG 0b 8. DS_QUERY_CHECK_REGb
· 0MD Z b
· 1 MD bZ 10b
· 2 MD Z b
· 3 MD Z 10b 9. DS_Z_MEM Zi (i {0, 1, 2..., n})bZ
b 10. DS_SET_FINISH_REG 1 DS_QUERY_BUSY_REG
0b
DS /cb
20.4
DS 20.4-1 b 3 b
469
ESP32-S2 TRM ( 1.3)
20 (DSA)
20.4-1. DS
PeriBUS1 PeriBUS2
0x3F43D000 0x6003D000
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20.5
cb 20.4-1 DS b
20.5-1. DS
DS_C_MEM DS_X_MEM DS_Z_MEM
C X Z
c 1584 0x0000 512 0x0800 512 0x0A00
0x062F 0x09FF 0x0BFF
20.6
cb 20.4-1 DS b
DS_IV_0_REG DS_IV_1_REG DS_IV_2_REG DS_IV_3_REG / DS_SET_START_REG DS_SET_ME_REG DS_SET_FINISH_REG DS_QUERY_BUSY_REG DS_QUERY_KEY_WRONG_REG DS_QUERY_CHECK_REG DS_DATE_REG
IV block IV block IV block IV block
DS DS DS_KEY
0x0630 0x0634 0x0638 0x063C
0x0E00 0x0E04 0x0E08 0x0E0C 0x0E10 0x0E14
0x0E20 /
470
ESP32-S2 TRM ( 1.3)
20 (DSA)
20.7
Register 20.1. DS_IV_m_REG (m: 0-3) (0x0630+4*m)
31
0x000000000
DS_IV_m_REG (m: 0-3) IV block bc
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0
Reset
Register 20.2. DS_SET_START_REG (0x0E00)
(reserved)
DS_SET_START
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
DS_SET_START 1 DS bc
Register 20.3. DS_SET_ME_REG (0x0E04)
(reserved)
DS_SET_ME
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
DS_SET_ME 1 bc
Register 20.4. DS_SET_FINISH_REG (0x0E08)
(reserved)
DS_SET_FINISH
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
DS_SET_FINISH 1 bc
471
ESP32-S2 TRM ( 1.3)
20 (DSA)
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Register 20.5. DS_QUERY_BUSY_REG (0x0E0C)
(reserved)
DS_QUERY_BUSY
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
DS_QUERY_BUSY 1DS 0DS bc
Register 20.6. DS_QUERY_KEY_WRONG_REG (0x0E10)
(reserved)
31
43
0000000000000000000000000000
DS_QUERY_KEY_WRONG
0
0x0
Reset
DS_QUERY_KEY_WRONG 1-15HMAC DS DS_KEY c 150 HMAC bc
Register 20.7. DS_QUERY_CHECK_REG (0x0E14)
(reserved)
DS_PADDSD_MINDG__EBRARDOR
31
21 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
DS_PADDING_BAD 10bc DS_MD_ERROR 1MD 0MD bc
(reserved)
31 30 29
00
Register 20.8. DS_DATE_REG (0x0E20)
DS_DATE 0x20190418
DS_DATE c/b
0
Reset
472
ESP32-S2 TRM ( 1.3)
21 (XTS_AES)
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21
(XTS_AES)
21.1
ESP32-S2 IEEE Std 1619-2007 XTS-AES cflash RAMba c flash RAM b
21.2
· XTS-AES IEEE Std 1619-2007 · · · · aeFuse a (boot)
21.3
(Manual Encryption) a (Auto Encryption) a (Auto Decryption) b 21.3-1 b
21.3-1.
473
ESP32-S2 TRM ( 1.3)
21 (XTS_AES)
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// SPI1 flashb CPU cache RAM RAMb CPU cache flash RAM b System SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG 4
· SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT · SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT · SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT · SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT eFuse 2 EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT EFUSE_SPI_BOOT_CRYPT_CNTb
21.3.1 XTS
/iiXTS b 1024 (data unit)odata unitp XTS-AES Tweakable Block Cipher XTS-AES encryption procedure b XTS-AES IEEE Std 1619-2007 b
21.3.2 Key
XTS a Keyb Key eFuseb
Key 256 a512 bKey eFuse BLOCK4 ~ BLOCK9 BLOCK BLOCK b
· BlockA BLOCK4 ~ BLOCK9 key purposec EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 BLOCKbBlockA 256 KeyAb
· BlockB BLOCK4 ~ BLOCK9 EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 BLOCKbBlockB 256 KeyBb
· BlockC BLOCK4 ~ BLOCK9 EFUSE_KEY_PURPOSE_XTS_AES_128_KEY BLOCKbBlockC 256 KeyC b
BlockAaBlockB BlockC Key 21.3-1 b
21.3-1. Key
BlockA Yes Yes No No
BlockB Yes No Yes No
BlockC
Yes
Key K eyA ||K eyB K eyA ||0256 0256 ||K eyB
K eyC
Key c 512 512 512 256
474
ESP32-S2 TRM ( 1.3)
21 (XTS_AES)
BlockA BlockB BlockC
No
No
No
Key 0256
Key c 256
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21.3-1 oYespoNopo0256p 256 "0" o||p b
4 eFuse (eFuse)b
21.3.3
b aab
· (type) flash RAMb 0 flash 1 RAMb
· (size)b 16a32 64 b
· (base_addr) base_addr%size == 0b
16 flash 0x130 ~ 0x13F 0x130 ~ 0x13F 0 (flash) 16 () 0x130b
c 16 / b
/b b
21.3.4
/bb 16 XTS_AES_PLAIN_n_REG (n: 0-15) 512 /b
b bopopb b
word
address
of f set
=
address%64
n
=
of f set 4
word
n XTS_AES_PLAIN_n_REG b
64 21.3-2 b
475
ESP32-S2 TRM ( 1.3)
21 (XTS_AES)
21.3-2.
of f set 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C
XTS_AES_PLAIN_0_REG XTS_AES_PLAIN_1_REG XTS_AES_PLAIN_2_REG XTS_AES_PLAIN_3_REG XTS_AES_PLAIN_4_REG XTS_AES_PLAIN_5_REG XTS_AES_PLAIN_6_REG XTS_AES_PLAIN_7_REG
of f set 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C
XTS_AES_PLAIN_8_REG XTS_AES_PLAIN_9_REG XTS_AES_PLAIN_10_REG XTS_AES_PLAIN_11_REG XTS_AES_PLAIN_12_REG XTS_AES_PLAIN_13_REG XTS_AES_PLAIN_14_REG XTS_AES_PLAIN_15_REG
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21.3.5
CPU ba System aeFuse aboot b flashb
1. XTS_AES
· XTS_AES_DESTINATION_REG type = 0b
· XTS_AES_PHYSICAL_ADDRESS_REG base_addrb
·
XTS_AES_LINESIZE_REG
size 32
b
typeabase_addrasize 21.3.3b
2. XTS_AES_PLAIN_n_REG (n: 0-15)b 21.3.4 b b
3. XTS_AES_STATE_REG 0b
4. b XTS_AES_TRIGGER_REG 1b
5. b XTS_AES_STATE_REG 2b 1 5 b Key b
6. SPI1b XTS_AES_RELEASE_REG 1 SPI1 b XTS_AES_STATE_REG 3b
7. SPI1 flashb
8. b XTS_AES_DESTROY_REG 1b XTS_AES_STATE_REG 0b
/b
b
· SPI Boot
SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT 1 b
476
ESP32-S2 TRM ( 1.3)
21 (XTS_AES)
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· Download Boot SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT 1 eFuse EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT 0 b
· CPU cache / K ey b
· AES AESb
21.3.6
CPU b System aeFuse aboot b b
· SPI Boot SPI_BOOT_CRYPT_CNTc3 1 b
· Download Boot SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT 1 b
· CPU cache RAM RAMb cache b Key b
· CPU cache RAMb
21.3.7
CPU b System aeFuse aboot b b
· SPI Boot SPI_BOOT_CRYPT_CNTc3 1 b
· Download Boot SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG
477
ESP32-S2 TRM ( 1.3)
21 (XTS_AES)
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SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT 1 b
· CPU cache / /b cache b Key b
· CPU cache b
21.4
21.4-1 b 3 b
21.4-1.
PeriBUS1 PeriBUS2
0x3F43A000 0x6003A000
21.5
cb 21.4 b
XTS_AES_PLAIN_0_REG XTS_AES_PLAIN_1_REG XTS_AES_PLAIN_2_REG XTS_AES_PLAIN_3_REG XTS_AES_PLAIN_4_REG XTS_AES_PLAIN_5_REG XTS_AES_PLAIN_6_REG XTS_AES_PLAIN_7_REG XTS_AES_PLAIN_8_REG XTS_AES_PLAIN_9_REG XTS_AES_PLAIN_10_REG XTS_AES_PLAIN_11_REG XTS_AES_PLAIN_12_REG XTS_AES_PLAIN_13_REG XTS_AES_PLAIN_14_REG XTS_AES_PLAIN_15_REG
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0x0100 0x0104 0x0108 0x010C 0x0110 0x0114 0x0118 0x011C 0x0120 0x0124 0x0128 0x012C 0x0130 0x0134 0x0138 0x013C
/ / / / / / / / / / / / / / / /
478
ESP32-S2 TRM ( 1.3)
21 (XTS_AES)
XTS_AES_LINESIZE_REG XTS_AES_DESTINATION_REG XTS_AES_PHYSICAL_ADDRESS_REG / XTS_AES_TRIGGER_REG XTS_AES_RELEASE_REG XTS_AES_DESTROY_REG XTS_AES_STATE_REG XTS_AES_DATE_REG
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0x0140 0x0144 0x0148
/ / /
0x014C 0x0150 0x0154 0x0158
0x015C
21.6
Register 21.1. XTS_AES_PLAIN_n_REG (n: 0-15) (0x0100+4*n)
XTS_AES_PLAIN_n
31
0x000000
XTS_AES_PLAIN_n n 32 bc/
0
Reset
Register 21.2. XTS_AES_LINESIZE_REG (0x0140)
(reserved)
31
0x00000000
XTS_AES_LINESIZE bc/ · 0 128 · 1 256 · 2 512 b
XTS_AES_LINESIZE
21
0
0 Reset
479
ESP32-S2 TRM ( 1.3)
21 (XTS_AES)
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Register 21.3. XTS_AES_DESTINATION_REG (0x0144)
(reserved)
XTS_AES_DESTINATION
31
10
0x00000000
0 Reset
XTS_AES_DESTINATION flash 0b 1b0 flash1 RAMbc/
(reserved)
31 30 29
0x0
Register 21.4. XTS_AES_PHYSICAL_ADDRESS_REG (0x0148)
XTS_AES_PHYSICAL_ADDRESS 0x00000000
XTS_AES_PHYSICAL_ADDRESS bc/
0
Reset
Register 21.5. XTS_AES_TRIGGER_REG (0x014C)
(reserved)
31
0x00000000
XTS_AES_TRIGGER 1 bc
XTS_AES_TRIGGER
10
x Reset
480
ESP32-S2 TRM ( 1.3)
21 (XTS_AES)
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Register 21.6. XTS_AES_RELEASE_REG (0x0150)
(reserved)
XTS_AES_RELEASE
31
10
0x00000000
x Reset
XTS_AES_RELEASE 1 SPI1 SPI1 bc
Register 21.7. XTS_AES_DESTROY_REG (0x0154)
(reserved)
31
0x00000000
XTS_AES_DESTROY 1 bc
XTS_AES_DESTROY
10
x Reset
Register 21.8. XTS_AES_STATE_REG (0x0158)
(reserved)
31
0x00000000
XTS_AES_STATE bc · 0x0 (XTS_AES_IDLE) · 0x1 (XTS_AES_BUSY) · 0x2 (XTS_AES_DONE) SPI · 0x3 (XTS_AES_RELEASE) SPI b
XTS_AES_STATE
21
0
0x0 Reset
481
ESP32-S2 TRM ( 1.3)
21 (XTS_AES)
(reserved)
31 30 29
00
Register 21.9. XTS_AES_DATE_REG (0x015C)
XTS_AES_DATE 0x20190416
XTS_AES_DATE bc
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0
Reset
482
ESP32-S2 TRM ( 1.3)
22 (RNG)
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22 (RNG)
22.1
ESP32-S2 32 b
22.2
ESP32-S2 b
22.3
RNG_DATA_REG 32 b SAR ADC ADC b SAR ADC ADC (XOR) b RC_FAST_CLK RC_FAST_CLK (8 MHz) bRC_FAST_CLK b ADC b
SAR ADC
Random bit seeds
High Speed ADC
Random bit seeds
XOR
XOR
Random Number Generator
RNG_DATA_REG
RC_FAST_CLK
Random bit seeds
22.3-1.
SAR ADC RC_FAST_CLK c8 MHzc RC 6 2 b RNG_DATA_REG 500 kHzb
483
ESP32-S2 TRM ( 1.3)
22 (RNG)
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ADC APB c 80 MHz 2 b RNG_DATA_REG 5 MHzb
22.4
ESP32-S2 SAR ADC ADC RC_FAST_CLK b
· SAR ADC DIG ADC 32 b · ADC Wi-Fi b · RC_FAST_CLK RTC_CNTL_CLK_CONF_REG RTC_CNTL_DIG_CLK8M_EN
b
Wi-Fi ADC b Wi-Fi DIG ADC1 SAR ADC b
RNG_DATA_REG b 22.3 b
22.5
22.5-1 b 3 b
22.5-1.
PeriBUS1 PeriBUS2
0x3F435000 0x60035000
22.6
cb 22.5 b
RNG_DATA_REG
0x0110
22.7
cb 22.5 b
484
ESP32-S2 TRM ( 1.3)
22 (RNG)
Register 22.1. RNG_DATA_REG (0x0110)
31
0x00000000
RNG_DATA bc
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0
Reset
485
ESP32-S2 TRM ( 1.3)
GoBack
V
I2CaI2SaSPIaUARTaUSB aaLED b
486
ESP32-S2 TRM ( 1.3)
23 UART (UART)
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23
UART (UART)
23.1
b (UART) b 2 UART UART bUART (IrDA) RS485 b 2 UART b UARTn 2 UART n 0a1b
23.2
· · 2 UART FIFO FIFO 512 x 8-bit RAM · · · 5/6/7/8 · 1/1.5/2 · · AT_CMD · RS485 · IrDA · DMA · UART ·
23.3
23.3.1 UART
UART b baab
487
ESP32-S2 TRM ( 1.3)
23 UART (UART)
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UART cb UART b DMA b UART b
23.3.2 UART
23.3-1. UART
23.3-1 UART bUART 80-MHz APB_CLK REF_TICK c 6 b UART_TICK_REF_ALWAYS_ON b UART bUART_CLKDIV_REG UART_CLKDIV UART_CLKDIV_FRAG b
UART b
FIFO b APB Tx_FIFO DMA Tx_FIFObTx_FIFO_Ctrl Tx_FIFO Tx_FIFO Tx_FSM Tx_FIFO_Ctrl b txd_out UART_TXD_INV b
FIFO b rxd_in UART b UART_RXD_INV bBaudrate_Detect bStart_Detect START START Rx_FSM Rx_FIFO_Ctrl Rx_FIFO b APB Rx_FIFO DMA b
HW_Flow_Ctrl UART RTS CTScrtsn_out ctsn_in rxd_in txd_out b SW_Flow_Ctrl b
488
ESP32-S2 TRM ( 1.3)
23 UART (UART)
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UART Light-sleepc 9 Wakeup_Ctrl rxd_in cUART_ACTIVE_THRESHOLD + 3 wake_up RTC RTC b
23.3.3 UART RAM
23.3-2. UART RAM
2 UART 512x8-bit RAM b 23.3-2 RAM block 1 block 128x8 bitsb 23.3-2 2 UART Tx_FIFO Rx_FIFO RAM b UART_TX_SIZE UARTn Tx_FIFO UART_RX_SIZE UARTn Rx_FIFO UART0 Tx_FIFO 0 RAM UART1 Tx_FIFO 128 RAM UART0 Rx_FIFO 256 RAM UART1 Rx_FIFO 1 block b UART FIFO UART FIFO b UART0 UART_TX_SIZE 2, UART0 Tx_FIFO 0 255bUART1 Tx_FIFO UART1 b
2 UART UART_MEM_FORCE_PD RAM b
UART0 UART1 Tx_FIFO UART_TXFIFO_RST , UART0 UART1 Rx_FIFO UART_RXFIFO_RST b
Tx FIFO APB DMA Tx_FSM Rx FIFO APB DMA Rx_FSM Rx FIFOb UART DMAb
UART_TXFIFO_EMPTY_THRHD Tx_FIFO Tx_FIFO UART_TXFIFO_EMPTY_THRHD UART_TXFIFO_EMPTY_INT UART_RXFIFO_FULL_THRHD Rx_FIFO Rx_FIFO UART_RXFIFO_FULL_THRHD UART_RXFIFO_FULL_INTb Rx_FIFO UART_RXFIFO_OVF_INT b
UARTn UART_FIFO_REG FIFOb
23.3.4
489
ESP32-S2 TRM ( 1.3)
23 UART (UART)
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23.3.4.1
UART b bUART_CLKDIV_REG UART_CLKDIV UART_CLKDIV_FRAG b 80 MHz UART 5 MBaudb
UART_CLKDIV + (UART_CLKDIV_FRAG/16) b INPUT_FREQ/ (UART_CLKDIV + (UART_CLKDIV_FRAG/16))b UART_CLKDIV = 694UART_CLKDIV_FRAG = 7 (694 + 7/16) = 694.4375b
UART_CLKDIV_FRAG 0 UART_CLKDIV b
UART_CLKDIV_FRAG 0 b 23.3-3 16 (UART_CLKDIV + 1) UART_CLKDIV b (UART_CLKDIV + 1) UART_CLKDIV_FRAG UART_CLKDIV (16 - UART_CLKDIV_FRAG) b
23.3-3 b
23.3-3. UART
IrDA c 23.3.8 IrDAIrDA 16× UART_CLKDIV_REG IrDA b IrDA UART_CLKDIV/16 UART_CLKDIV 4 b
23.3.4.2
UART_AUTOBAUD_EN UART b 23.3-1 Baudrate_Detect UART_GLITCH_FILT b UART b UART_LOWPULSE_MIN_CNT UART_HIGHPULSE_MIN_CNT UART_POSEDGE_MIN_CNT UART_NEGEDGE_MIN_CNT bb
490
ESP32-S2 TRM ( 1.3)
23 UART (UART)
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23.3-4. UART
1. UART_LOWPULSE_MIN_CNT UART_HIGHPULSE_MIN_CNT b
Buart
=
(UART_LOWPULSE_MIN_CNT
+
fclk UART_HIGHPULSE_MIN_CNT
+
2)/2
2. UART 23.3-4 UART_LOWPULSE_MIN_CNT
UART_HIGHPULSE_MIN_CNT UART_POSEDGE_MIN_CNT
b
Buart
=
fclk (UART_POSEDGE_MIN_CNT
+
1)/2
3. UART UART_NEGEDGE_MIN_CNT b
Buart
=
fclk (UART_NEGEDGE_MIN_CNT
+
1)/2
23.3.5 UART
23.3-5. UART
23.3-5 START STOP bSTART 1 bitSTOP UART_STOP_BIT_NUM 1a1.5a2 cRS485 23.3.7.2b START STOP b
(BIT0 ~ BITn) 5 ~ 8 bit UART_BIT_NUM b UART_PARITY_EN bUART_PARITY b UART_PARITY_ERR_INT Rx_FIFOb UART_FRM_ERR_INT Rx_FIFOb
491
ESP32-S2 TRM ( 1.3)
23 UART (UART)
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Tx_FIFO UART_TX_DONE_INT b UART_TXD_BRK Tx_FIFO (break condition) NULL NULL TX bNULL UART_TX_BRK_NUM b NULL UART_TX_BRK_DONE_INT b UART_TX_IDLE_NUM b UART_TX_IDLE_NUM UART_TX_BRK_IDLE_DONE_INT b
NULL RX UART_BRK_DET_INT b
UART_RXFIFO_TOUT_INT b UART_RX_TOUT_THRHD UART_RXFIFO_TOUT_INT b b
23.3.6 AT_CMD
23.3-6. AT_CMD
23.3-6 AT_CMD b AT_CMD_CHAR UART_AT_CMD_CHAR_DET_INT b
· AT_CMD_CHAR AT_CMD_CHAR UART_PRE_IDLE_NUM b
· AT_CMD_CHAR UART_RX_GAP_TOUT b
· AT_CMD_CHAR UART_CHAR_NUMb
· AT_CMD_CHAR AT_CMD_CHAR UART_POST_IDLE_NUM b
23.3.7 RS485
UART RS485 RS485 RS232 bRS485 UART b RS485 multidrop 32 slaveb
23.3.7.1
23.3-7 RS485 multidrop RS485 bRS485 b UART bDE 1 DE 0 b
UART bRE RE 0 RE 1, b RE 0 UART UART b
492
ESP32-S2 TRM ( 1.3)
23 UART (UART)
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DE bDE b 23.3-7 DE UART dtrn_out c 23.3.10.1 b
transceiver
23.3-7. RS485
23.3.7.2
UART bRS485 turn around dealybUART b UART_DL1_EN DL0_ENb
23.3.7.3
RS485 multidrop UART b UART b UART_RS485TX_RX_EN RS485 UART b UART b UART_RS485RXBY_TX_EN b
UART UART bUART UART UART UART_RS485_CLASH_INT UART_RS485_FRM_ERR_INT UART_RS485_PARITY_ERR_INT b
23.3.8 IrDA
IrDA bUART b IrDA 115.2 Kbit/s SIR b 23.3-8 IrDA UART cNRZcRZI LED 3/16 Bit Time o0po1pbIrDA UART NRZ b b b
IrDA 16 9,10,11 0 IrDA b
493
ESP32-S2 TRM ( 1.3)
23 UART (UART)
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23.3-8. SIR
IrDA b23.3-9 UART_IRDA_EN IrDA b UART_IRDA_TX_EN c IrDA IrDA UART_IRDA_TX_ENc IrDA IrDA b
23.3-9. IrDA
23.3.9
UART0 UART1 b UART Light-sleep Wakeup_Ctrl rxd_in cUART_ACTIVE_THRESHOLD + 3 wake_up RTC RTC b UART Active UART UART wake_up b
23.3.10
UART b rtsn_out dsrn_in b b
494
ESP32-S2 TRM ( 1.3)
23 UART (UART)
23.3.10.1
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23.3-10.
23.3-10 UART b rtsn_out ctsn_inb 23.3-11 UART b ESP32-S2 UART IU0External UART EU0 UARTb rtsn_out cIU0cEU0rtsn_outcIU0 cEU0 rtsn_out cIU0brtsn_out b
· UART_RX_FLOW_EN 0 b UART_SW_RTS rtsn_out b
· UART_RX_FLOW_EN 1 b Rx_FIFO UART_RX_FLOW_THRHD rtsn_out b
23.3-11.
ctsn_incIU0cIU0ctsn_incIU0 cIU0b UART ctsn_in cIU0 UART_CTS_CHG_INT
b
495
ESP32-S2 TRM ( 1.3)
23 UART (UART)
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UART cIU0 dtrn_out bdtrn_out UART_SW_DTR bUART cIU0 dsrn_in UART_DSR_CHG_INT b UART_DSRN dsrn_in UART_DSRN cEU0b
RS485 multidrop dtrn_out b UART_RS485_EN RS485 dtrn_out bdtrn_out dtrn_out bdtrn_out b
UART_LOOPBACK UART b UART txd_out rxd_in rtsn_out ctsn_in dtrn_out dsrn_out b UART b
23.3.10.2
CTS/RTS XON/XOFF b UART_SW_FLOW_CON_EN 1 b
XON/XOFF UART_SW_XOFF_INT UART_SW_XON_INT b XOFF XON b UART_FORCE_XOFF UART_FORCE_XON b
Rx_FIFO b UART_SEND_XOFF XOFF UART_XOFF_CHAR UART_SEND_XON XON UART_XON_CHAR b UART FIFO UART_XOFF_THRESHOLD UART_SEND_XOFFUART XOFF UART_XOFF_CHAR b UART FIFO UART_XON_THRESHOLD UART_SEND_XONUART XON UART_XON_CHAR b
23.3.11 UDMA
UART UDMA (UART DMA)UDMA HCI cdecoder cencoderb 2 DMA b
23.3.12 UART
· UART_AT_CMD_CHAR_DET_INT AT_CMD b · UART_RS485_CLASH_INT RS485 b · UART_RS485_FRM_ERR_INT RS485 b · UART_RS485_PARITY_ERR_INT RS485 b · UART_TX_DONE_INT FIFO b · UART_TX_BRK_IDLE_DONE_INTb
496
ESP32-S2 TRM ( 1.3)
23 UART (UART)
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· UART_TX_BRK_DONE_INT FIFO NULL b · UART_GLITCH_DET_INT glitch b · UART_SW_XOFF_INTUART_SW_FLOW_CON_EN Xoff b · UART_SW_XON_INTUART_SW_FLOW_CON_EN Xon b · UART_RXFIFO_TOUT_INT UART_RX_TOUT_THRHD b · UART_BRK_DET_INT NULL c NULL
b · UART_CTS_CHG_INT CTSn b · UART_DSR_CHG_INT DSRn b · UART_RXFIFO_OVF_INT FIFO b · UART_FRM_ERR_INTb · UART_PARITY_ERR_INTb · UART_TXFIFO_EMPTY_INT FIFO UART_TXFIFO_EMPTY_THRHD
b · UART_RXFIFO_FULL_INT UART_RXFIFO_FULL_THRHD
b · UART_WAKEUP_INTUART b
23.3.13 UCHI
· UHCI_DMA_INFIFO_FULL_WM_INT DMA FIFO UHCI_DMA_INFIFO_FULL_THRS b
· UHCI_SEND_A_REG_Q_INT always_send DMA b · UHCI_SEND_S_REG_Q_INT single_send DMA b · UHCI_OUT_TOTAL_EOF_INTb · UHCI_OUTLINK_EOF_ERR_INT EOF b · UHCI_IN_DSCR_EMPTY_INT DMA b · UHCI_OUT_DSCR_ERR_INTb · UHCI_IN_DSCR_ERR_INTb · UHCI_OUT_EOF_INT EOF 1 b · UHCI_OUT_DONE_INTb · UHCI_IN_ERR_EOF_INT EOF b · UHCI_IN_SUC_EOF_INTb · UHCI_IN_DONE_INTb · UHCI_TX_HUNG_INT DMA RAM b · UHCI_RX_HUNG_INT DMA b
497
ESP32-S2 TRM ( 1.3)
23 UART (UART)
· UHCI_TX_START_INT DMA b · UHCI_RX_START_INTb
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23.4
UART 23.4-1 b 3 b
23.4-1. UART0aUART1 UHCI
UART0 UART1 UHCI
PeriBUS1 PeriBUS2 PeriBUS1 PeriBUS2 PeriBUS1 PeriBUS2
0x3F400000 0x60000000 0x3F410000 0x60010000 0x3F414000 0x60014000
23.5
UART0aUART1 UHCI cb UART0aUART1 UHCI 23.4 b
FIFO UART_FIFO_REG UART_MEM_CONF_REG UART_INT_RAW_REG UART_INT_ST_REG UART_INT_ENA_REG UART_INT_CLR_REG UART_CLKDIV_REG UART_CONF0_REG UART_CONF1_REG UART_FLOW_CONF_REG UART_SLEEP_CONF_REG UART_SWFC_CONF0_REG UART_SWFC_CONF1_REG UART_IDLE_CONF_REG UART_RS485_CONF_REG UART_AUTOBAUD_REG
FIFO UART
0 1 RS485
0x0000 / 0x005C /
0x0004 0x0008 0x000C 0x0010
/
0x0014 0x0020 0x0024 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048
/ / / / / / / / /
0x0018 /
498
ESP32-S2 TRM ( 1.3)
23 UART (UART)
UART_LOWPULSE_REG
UART_HIGHPULSE_REG
UART_RXD_CNT_REG UART_POSPULSE_REG UART_NEGPULSE_REG UART_STATUS_REG UART_MEM_TX_STATUS_REG UART_MEM_RX_STATUS_REG UART_FSM_STATUS_REG AT UART_AT_CMD_PRECNT_REG UART_AT_CMD_POSTCNT_REG UART_AT_CMD_GAPTOUT_REG UART_AT_CMD_CHAR_REG UART_DATE_REG
UHCI_CONF0_REG UHCI_CONF1_REG UHCI_AHB_TEST_REG UHCI_ESCAPE_CONF_REG UHCI_HUNG_CONF_REG UHCI_QUICK_SENT_REG UHCI_Q0_WORD0_REG UHCI_Q0_WORD1_REG UHCI_Q1_WORD0_REG UHCI_Q1_WORD1_REG UHCI_Q2_WORD0_REG UHCI_Q2_WORD1_REG UHCI_Q3_WORD0_REG UHCI_Q3_WORD1_REG UHCI_Q4_WORD0_REG UHCI_Q4_WORD1_REG UHCI_Q5_WORD0_REG UHCI_Q5_WORD1_REG UHCI_Q6_WORD0_REG UHCI_Q6_WORD1_REG UHCI_ESC_CONF0_REG
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0x0028
0x002C
0x0030 0x006C 0x0070
UART TX FIFO a RX FIFO a UART
0x001C 0x0060 0x0064 0x0068
AT_CMD AT_CMD AT
0x004C 0x0050 0x0054 0x0058
/ / / /
UART
0x0074 /
UHCI UHCI AHB UHCI Q0_WORD0 Q0_WORD1 Q1_WORD0 Q1_WORD1 Q2_WORD0 Q2_WORD1 Q3_WORD0 Q3_WORD1 Q4_WORD0 Q4_WORD1 Q5_WORD0 Q5_WORD1 Q6_WORD0 Q6_WORD1 0
499
0x0000 0x002C 0x0048 0x0064 0x0068 0x0074 0x0078 0x007C 0x0080 0x0084 0x0088 0x008C 0x0090 0x0094 0x0098 0x009C 0x00A0 0x00A4 0x00A8 0x00AC 0x00B0
/ / / / / / / / / / / / / / / / / / / / /
ESP32-S2 TRM ( 1.3)
23 UART (UART)
UHCI_ESC_CONF1_REG
1
UHCI_ESC_CONF2_REG
2
UHCI_ESC_CONF3_REG
3
UHCI_PKT_THRES_REG
UHCI_INT_RAW_REG
UHCI_INT_ST_REG
UHCI_INT_ENA_REG
UHCI_INT_CLR_REG DMA
UHCI_DMA_OUT_STATUS_REG
DMA
UHCI_DMA_IN_STATUS_REG
UHCI
UHCI_STATE0_REG
UHCI
UHCI_STATE1_REG
UHCI
UHCI_DMA_OUT_EOF_DES_ADDR
EOF
_REG
UHCI_DMA_IN_SUC_EOF_DES_ADDR EOF
_REG
UHCI_DMA_IN_ERR_EOF_DES_ADDR
_REG
UHCI_DMA_OUT_EOF_BFR_DES_ADDR
_REG
UHCI_DMA_IN_DSCR_REG
UHCI_DMA_IN_DSCR_BF0_REG
UHCI_DMA_OUT_DSCR_REG
UHCI_DMA_OUT_DSCR_BF0_REG
UHCI_RX_HEAD_REG DMA
UHCI
UHCI_DMA_OUT_PUSH_REG
FIFO
UHCI_DMA_IN_POP_REG
FIFO
UHCI_DMA_OUT_LINK_REG
UHCI_DMA_IN_LINK_REG
UHCI_DATE_REG
UHCI
GoBack
0x00B4 0x00B8 0x00BC 0x00C0
/ / / /
0x0004 0x0008 0x000C 0x0010
/
0x0014 0x001C 0x0030 0x0034 0x0038
0x003C
0x0040
0x0044
0x004C 0x0050 0x0058 0x005C 0x0070
0x0018 0x0020 0x0024 0x0028
/
0x00FC /
500
ESP32-S2 TRM ( 1.3)
23 UART (UART)
23.6
Register 23.1. UART_FIFO_REG (0x0000)
(reserved)
31
87
000000000000000000000000
UART_RXFIFO_RD_BYTE UART n FIFOb(/)
GoBack
UART_RXFIFO_RD_BYTE
0
0x0
Reset
Register 23.2. UART_MEM_CONF_REG (0x005C)
(reserved)
UART_UMARETM__MFEOMRC_FEO_PRCUE_PD
UART_RX_TOUT_THRHD
31
28 27 26 25
16 15
0 0 0 00 0
0xa
UART_RX_FLOW_THRHD
76
UART_TX_SIZE UART_RX_S(rIeZsEerved)
43
10
0x0
0x1
1
0 Reset
UART_RX_SIZE RX FIFO RAM b 128 b(/) UART_TX_SIZE TX FIFO RAM b 128 b(/) UART_RX_FLOW_THRHD b(/) UART_RX_TOUT_THRHD c
bb UART_RX_TOUT_EN 1 UART_RXFIFO_TOUT_INT b(/) UART_MEM_FORCE_PD UART RAMb(/) UART_MEM_FORCE_PU UART RAMb(/)
501
ESP32-S2 TRM ( 1.3)
23 UART (UART)
GoBack
Register 23.3. UART_INT_RAW_REG (0x0004)
(reserved)
UART_UWARATK_EUUAATPR_T_C_IUNMRATSRD_4T_R8_UCA5RAHW_SRAC4TRL8_U_A5RADS_SREHF4TT_R8_U_IMT5NAINX_R_T_TPTE_D_A_RURORRTRAAIAXNW_TRW_EYITNB___UTRTIEAN_KXRRTR__RT_AIB_D_URWRIGLANAKELRWT__ITT_DD_UCROOSAHANWNRW_ETED____UXEISIAONTNWR_FTTTFI___N_U_RXRTRIAOAAN_XRWNWTRFT__AI_UFIRWNBOAATRR_W_TKTOR__UACUDAWTTERS_TT__I_UNCIDANTHSR_TGRT_R___URACRIAWANXHRWTFTG_I_UF_RFOAIANRR_WTMTO__UV_RPAFEAA_RRWRTIRNI_U_TTTAYI_NXR_RFTTEIA_F_RWRORRA_X_WFEINIMFTOP__TRYFA_UWILNLT__INRTA_WRAW
31
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UART_RXFIFO_FULL_INT_RAW UART_RXFIFO_FULL_THRHD b()
UART_TXFIFO_EMPTY_INT_RAW TX FIFO UART_TXFIFO_EMPTY_THRHD b()
UART_PARITY_ERR_INT_RAW b ()
UART_FRM_ERR_INT_RAW b()
UART_RXFIFO_OVF_INT_RAW RX FIFO b()
UART_DSR_CHG_INT_RAW DSRn b( )
UART_CTS_CHG_INT_RAW CTSn b( )
UART_BRK_DET_INT_RAW 0 b()
UART_RXFIFO_TOUT_INT_RAW UART_RX_TOUT_THRHD b()
UART_SW_XON_INT_RAW XON UART_SW_FLOW_CON_EN 1 b()
UART_SW_XOFF_INT_RAW XOFF UART_SW_FLOW_CON_EN 1 b()
UART_GLITCH_DET_INT_RAW b()
UART_TX_BRK_DONE_INT_RAW TX FIFO NULL b()
UART_TX_BRK_IDLE_DONE_INT_RAW b()
UART_TX_DONE_INT_RAW FIFO b()
...
502
ESP32-S2 TRM ( 1.3)
23 UART (UART) Register 23.3. UART_INT_RAW_REG (0x0004)
GoBack
...
UART_RS485_PARITY_ERR_INT_RAW RS485 b()
UART_RS485_FRM_ERR_INT_RAW RS485 b()
UART_RS485_CLASH_INT_RAW RS485 b()
UART_AT_CMD_CHAR_DET_INT_RAW UART_AT_CMD CHAR b()
UART_WAKEUP_INT_RAW RXD Light-sleep UART_ACTIVE_THRESHOLD 3 b()
503
ESP32-S2 TRM ( 1.3)
23 UART (UART)
GoBack
Register 23.4. UART_INT_ST_REG (0x0008)
(reserved)
UART_UWARATK_EUUAATPR_T_C_IUNMRATSRD_4T_S8_UCT5RAH_SRAC4TRL8_U_A5RADS_SREHF4TT_R8_U_IMT5NAINX_R_T_TPTE_D_A_RSUSORTTRATIXN_TR_EYITNB___UTRTIEAN_KXRRTS__RT_TIB_D_USRIGLATNKELRT__ITT_DD_UCSOOSATHNWNR_ETED____UXEISIAONTNWR_FTTTFI___N_U_SXSTRIATOTN_XRNTSFT__TI_UFISNBOATTRR__TKTSO__UTCUDATTERS_TT__I_UNCIDANTHSR_TGRT_S___UTSCRIATNXHRTFTG_I_UF_SFOAITNRR_TMTO__UV_SPAFETA_RRRTIRNI_U_TTTAYI_NXR_SFTTETI_F_RSORRT_X_FEINIMFTOP__TSYFT_UILNLT__INSTT_ST
31
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UART_RXFIFO_FULL_INT_ST UART_RXFIFO_FULL_INT_ENA 1 UART_RXFIFO_FULL_INT b()
UART_TXFIFO_EMPTY_INT_ST UART_TXFIFO_EMPTY_INT_ENA
1
UART_TXFIFO_EMPTY_INT b()
UART_PARITY_ERR_INT_ST UART_PARITY_ERR_INT_ENA 1 UART_PARITY_ERR_INT b()
UART_FRM_ERR_INT_ST UART_FRM_ERR_INT_ENA 1 UART_FRM_ERR_INT b( )
UART_RXFIFO_OVF_INT_ST UART_RXFIFO_OVF_INT_ENA 1 UART_RXFIFO_OVF_INT b()
UART_DSR_CHG_INT_ST UART_DSR_CHG_INT_ENA 1 UART_DSR_CHG_INT b( )
UART_CTS_CHG_INT_ST UART_CTS_CHG_INT_ENA 1 UART_CTS_CHG_INT b( )
UART_BRK_DET_INT_ST UART_BRK_DET_INT_ENA 1 UART_BRK_DET_INT b( )
UART_RXFIFO_TOUT_INT_ST UART_RXFIFO_TOUT_INT_ENA 1 UART_RXFIFO_TOUT_INT b()
UART_SW_XON_INT_ST UART_SW_XON_INT_ENA 1 UART_SW_XON_INT b()
UART_SW_XOFF_INT_ST UART_SW_XOFF_INT_ENA 1 UART_SW_XOFF_INT b( )
UART_GLITCH_DET_INT_ST UART_GLITCH_DET_INT_ENA 1 UART_GLITCH_DET_INT b()
UART_TX_BRK_DONE_INT_ST UART_TX_BRK_DONE_INT_ENA 1 UART_TX_BRK_DONE_INT b()
UART_TX_BRK_IDLE_DONE_INT_ST UART_TX_BRK_IDLE_DONE_INT_ENA
1
UART_TX_BRK_IDLE_DONE_INT b()
...
504
ESP32-S2 TRM ( 1.3)
23 UART (UART) Register 23.4. UART_INT_ST_REG (0x0008)
GoBack
... UART_TX_DONE_INT_ST UART_TX_DONE_INT_ENA 1 UART_TX_DONE_INT b()
UART_RS485_PARITY_ERR_INT_ST UART_RS485_PARITY_INT_ENA
1
UART_RS485_PARITY_ERR_INT b()
UART_RS485_FRM_ERR_INT_ST UART_RS485_FM_ERR_INT_ENA
1
UART_RS485_FRM_ERR_INT b()
UART_RS485_CLASH_INT_ST UART_RS485_CLASH_INT_ENA 1 UART_RS485_CLASH_INT b()
UART_AT_CMD_CHAR_DET_INT_ST UART_AT_CMD_CHAR_DET_INT_ENA 1 UART_AT_CMD_DET_INT b()
UART_WAKEUP_INT_ST UART_WAKEUP_INT_ENA 1 UART_WAKEUP_INT b()
505
ESP32-S2 TRM ( 1.3)
23 UART (UART)
GoBack
Register 23.5. UART_INT_ENA_REG (0x000C)
(reserved)
UART_UWARATK_EUUAATPR_T_C_IUNMRATSRD_4T_E8_UCN5RAHA_SRAC4TRL8_U_A5RADS_SREHF4TT_R8_U_IMT5NAINX_R_T_TPTE_D_A_RUEORETRNANIXN_TRA_AEIYTNB___UTRTIEAN_KXRRTE__RT_NIB_D_UEARIGLANNKELRAT__ITT_DD_UCEOOSAHNNWNR_AETED____UXEISIAONTNWR_FTTTFI___N_U_EXETRIAONNN_XRANATEFT__NI_UFIEANBOANTRR_A_TKTOE__UNCUDAATTERS_TT__I_UNCIDANTHSR_TGRT_E___UNECRIANNAXHRATFTG_I_UF_EFOAINNRR_ATMTO__UV_EPAFENA_RRARTIRNI_U_TTTAYI_NXR_EFTTENI_F_RAEORRN_X_AFEINIMFTOP__TEYFN_UAILNLT__INETN_AENA
31
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UART_RXFIFO_FULL_INT_ENA UART_RXFIFO_FULL_INT b(/) UART_TXFIFO_EMPTY_INT_ENA UART_TXFIFO_EMPTY_INT b(/) UART_PARITY_ERR_INT_ENA UART_PARITY_ERR_INT b(/) UART_FRM_ERR_INT_ENA UART_FRM_ERR_INT b(/) UART_RXFIFO_OVF_INT_ENA UART_RXFIFO_OVF_INT b(/) UART_DSR_CHG_INT_ENA UART_DSR_CHG_INT b(/) UART_CTS_CHG_INT_ENA UART_CTS_CHG_INT b(/) UART_BRK_DET_INT_ENA UART_BRK_DET_INT b(/) UART_RXFIFO_TOUT_INT_ENA UART_RXFIFO_TOUT_INT b(/) UART_SW_XON_INT_ENA UART_SW_XON_INT b(/) UART_SW_XOFF_INT_ENA UART_SW_XOFF_INT b(/) UART_GLITCH_DET_INT_ENA UART_GLITCH_DET_INT b(/) UART_TX_BRK_DONE_INT_ENA UART_TX_BRK_DONE_INT b(/) UART_TX_BRK_IDLE_DONE_INT_ENA UART_TX_BRK_IDLE_DONE_INT b(/) UART_TX_DONE_INT_ENA UART_TX_DONE_INT b(/) UART_RS485_PARITY_ERR_INT_ENA UART_RS485_PARITY_ERR_INT b(/) UART_RS485_FRM_ERR_INT_ENA UART_RS485_PARITY_ERR_INT b(/) UART_RS485_CLASH_INT_ENA UART_RS485_CLASH_INT b(/) UART_AT_CMD_CHAR_DET_INT_ENA UART_AT_CMD_CHAR_DET_INT b(/) UART_WAKEUP_INT_ENA UART_WAKEUP_INT b(/)
506
ESP32-S2 TRM ( 1.3)
23 UART (UART)
GoBack
Register 23.6. UART_INT_CLR_REG (0x0010)
(reserved)
UART_UWARATK_EUUAATPR_T_C_IUNMRATSRD_4T_C8_UCL5RAHR_SRAC4TRL8_U_A5RADS_SREHF4TT_R8_U_IMT5NAINX_R_T_TPTE_D_A_RCUCORTRLAILXNR_TRR_EYITNB___UTRTIEAN_KXRRTC__RT_LIB_D_UCRRIGLANLKELRRT__ITT_DD_UCCOOSAHLNWNRR_ETED____UXEISIAONTNWR_FTTTFI___N_U_CXCTRIAOLNL_XRRNRTCFT__LI_UFICRNBOALTRR_R_TKTCO__ULCUDARTTERS_TT__I_UNCIDANTHSR_TGRTC____UCLCRIARLNXHRRTFTG_I_UF_CFOAILNRR_RTMTO__UV_CPAFELA_RRRRTIRNI_U_TTTAYI_NXR_CFTTEIL_F_RRCORRL_X_RFEINIMFTOP__TCYFL_URILNLT__INCTL_RCLR
31
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UART_RXFIFO_FULL_INT_CLR UART_RXFIFO_FULL_INT b() UART_TXFIFO_EMPTY_INT_CLR UART_TXFIFO_EMPTY_INT b() UART_PARITY_ERR_INT_CLR UART_PARITY_ERR_INT b() UART_FRM_ERR_INT_CLR UART_FRM_ERR_INT b() UART_RXFIFO_OVF_INT_CLR UART_RXFIFO_OVF_INT b() UART_DSR_CHG_INT_CLR UART_DSR_CHG_INT b() UART_CTS_CHG_INT_CLR UART_CTS_CHG_INT b() UART_BRK_DET_INT_CLR UART_BRK_DET_INT b() UART_RXFIFO_TOUT_INT_CLR UART_RXFIFO_TOUT_INT b() UART_SW_XON_INT_CLR UART_SW_XON_INT b() UART_SW_XOFF_INT_CLR UART_SW_XOFF_INT b() UART_GLITCH_DET_INT_CLR UART_GLITCH_DET_INT b() UART_TX_BRK_DONE_INT_CLR UART_TX_BRK_DONE_INT b() UART_TX_BRK_IDLE_DONE_INT_CLR UART_TX_BRK_IDLE_DONE_INT b()
UART_TX_DONE_INT_CLR UART_TX_DONE_INT b() UART_RS485_PARITY_ERR_INT_CLR UART_RS485_PARITY_ERR_INT b()
UART_RS485_FRM_ERR_INT_CLR UART_RS485_FRM_ERR_INT b() UART_RS485_CLASH_INT_CLR UART_RS485_CLASH_INT b() UART_AT_CMD_CHAR_DET_INT_CLR UART_AT_CMD_CHAR_DET_INT b()
UART_WAKEUP_INT_CLR UART_WAKEUP_INT b()
507
ESP32-S2 TRM ( 1.3)
23 UART (UART)
Register 23.7. UART_CLKDIV_REG (0x0014)
(reserved)
31
24 23
00000000
UART_CLKDIV_FRAG
20 19
0x0
UART_CLKDIV 0x2b6
UART_CLKDIV b(/) UART_CLKDIV_FRAG b(/)
GoBack
0
Reset
508
ESP32-S2 TRM ( 1.3)
23 UART (UART)
GoBack
Register 23.8. UART_CONF0_REG (0x0020)
(reserved) UART_UMARETM__TCI(CrLeKKs__eRErEvNFe_dUA)ALRWT_AUYDASTR_RTO__UNIRANTRVST__UTIANXRVDT__UIDNASRVTR__UCIANTRVST__UIRANXRVDT__UTIANXRVFTIF_UORA_XRFRTIS_UFTIOARR_DTRA_US_TTAEXRN_TF_ULLAOORWOT__PUEIBARNARDCTA_KU_IARRRXDT_A_UI_NIATRVRXD_TAI_UN_IAWRVRDCTAT_U_LIATRRXD_TAE_U_TNADXRPDTL__UXBSARWRKT__DSTWURA_RRTT_SSTOPU_ABRITT__BNIUUTA_MRNTU_UMPAARRTI_TPYA_REINTY
31
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5
43
21 0
0 0 0 1 1 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
3 0 0 Reset
UART_PARITY b0b1b(/) UART_PARITY_EN UART b(/) UART_BIT_NUM b05 b16 b27 b38 b(/) UART_STOP_BIT_NUM b0:
1: 1 2: 1.5 3: 2 (/) UART_SW_RTS RTS b(/) UART_SW_DTR DTR b(/) UART_TXD_BRK NULLb(/) UART_IRDA_DPLX IrDA b(/) UART_IRDA_TX_EN IrDA b(/) UART_IRDA_WCTL 1IrDA 11 10 b0 IrDA 11 0b(/)
UART_IRDA_TX_INV IrDA b(/)
UART_IRDA_RX_INV IrDA b(/)
UART_LOOPBACK UART b(/)
UART_TX_FLOW_EN b(/)
UART_IRDA_EN IrDA b(/)
UART_RXFIFO_RST UART RX FIFOb(/)
UART_TXFIFO_RST UART TX FIFOb(/)
UART_RXD_INV UART RXD b(/)
UART_CTS_INV UART CTS b(/)
UART_DSR_INV UART DSR b(/)
UART_TXD_INV UART TXD b(/)
...
509
ESP32-S2 TRM ( 1.3)
23 UART (UART) Register 23.8. UART_CONF0_REG (0x0020)
GoBack
... UART_RTS_INV UART RTS b(/) UART_DTR_INV UART DTR b(/) UART_TICK_REF_ALWAYS_ON b1APB_CLKb0REF_TICKb(/) UART_MEM_CLK_EN UART RAM b1UART RAM ab0UART
RAM b(/)
Register 23.9. UART_CONF1_REG (0x0024)
UART_URAXR_TT_UORAUXRT_T_F_ELRONXW_T_OEUNT_FLOW_DIS
31 30 29 28
(reserved)
18 17
0 0 00 0 0 0 0 0 0 0 0 0 0
UART_TXFIFO_EMPTY_THRHD
98
0x60
UART_RXFIFO_FULL_THRHD
0
0x60
Reset
UART_RXFIFO_FULL_THRHD UART_RXFIFO_FULL_INT b(/)
UART_TXFIFO_EMPTY_THRHD TX FIFO UART_TXFIFO_EMPTY_INT b(/)
UART_RX_TOUT_FLOW_DIS idle_cntb(/)
UART_RX_FLOW_EN UART b1 sw_rts b0 b(/)
UART_RX_TOUT_EN UART b(/)
510
ESP32-S2 TRM ( 1.3)
23 UART (UART)
GoBack
Register 23.10. UART_FLOW_CONF_REG (0x0034)
(reserved)
UART_USAERNTD_US_AEXRNOTD_FUFF_AOXRORTC_NUFEAO_RXRTOC_UFXEAOF_RNXTO_ONSFWF__DFELLOW_CON_EN
31
65 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UART_SW_FLOW_CON_EN bUART UART_XON_CHAR UART_XOFF_CHAR XON XOFF UART_SW_XON_INT UART_SW_XOFF_INT b(/)
UART_XONOFF_DEL b(/) UART_FORCE_XON b(/) UART_FORCE_XOFF b(/) UART_SEND_XON XON bb(/) UART_SEND_XOFF XOFF bb(/)
Register 23.11. UART_SLEEP_CONF_REG (0x0038)
(reserved)
31
10 9
0000000000000000000000
UART_ACTIVE_THRESHOLD
0
0xf0
Reset
UART_ACTIVE_THRESHOLD RXD 3 UART Light-sleep b(/)
511
ESP32-S2 TRM ( 1.3)
23 UART (UART)
GoBack
Register 23.12. UART_SWFC_CONF0_REG (0x003C)
(reserved)
31
17 16
000000000000000
UART_XOFF_CHAR
98
0x13
UART_XOFF_THRESHOLD
0
0xe0
Reset
UART_XOFF_THRESHOLD RX FIFO UART_SW_FLOW_CON_EN 1 XOFF b(/)
UART_XOFF_CHAR XOFF b(/)
Register 23.13. UART_SWFC_CONF1_REG (0x0040)
(reserved)
31
17 16
000000000000000
UART_XON_CHAR
98
0x11
UART_XON_THRESHOLD
0
0x0
Reset
UART_XON_THRESHOLD RX FIFO UART_SW_FLOW_CON_EN 1 XON b(/)
UART_XON_CHAR XON b(/)
(reserved)
31
28 27
0000
Register 23.14. UART_IDLE_CONF_REG (0x0044)
UART_TX_BRK_NUM
20 19
0xa
UART_TX_IDLE_NUM
10 9
0x100
UART_RX_IDLE_THRHD
0
0x100
Reset
UART_RX_IDLE_THRHD cb(/)
UART_TX_IDLE_NUM c bb(/)
UART_TX_BRK_NUM NULL bUART_TXD_BRK 1 b (/)
512
ESP32-S2 TRM ( 1.3)
23 UART (UART)
GoBack
Register 23.15. UART_RS485_CONF_REG (0x0048)
(reserved)
31
10 9
0000000000000000000000
UART_RS485_UTAXR_TD_ULRYAS_R4NT8_UU5RAM_SRR4TX8_U_5RADRSRLX4TYB8_U_Y5DAN_TLRTUX1TXM___U_ERDAENXLRN_0TE__NERNS485_EN
65 4 3 2 1 0
0x0
0 0 0 0 0 0 Reset
UART_RS485_EN RS485 b(/) UART_DL0_EN 1 b(/) UART_DL1_EN 1 b(/) UART_RS485TX_RX_EN RS485 b
(/) UART_RS485RXBY_TX_EN 1RS485 RS485 b0RS485
RS485 b(/) UART_RS485_RX_DLY_NUM b(/) UART_RS485_TX_DLY_NUM b(/)
Register 23.16. UART_AUTOBAUD_REG (0x0018)
(reserved)
31
16 15
0000000000000000
UART_GLITCH_FILT
87
(reserved)
UART_AUTOBAUD_EN
10
0x10
0 0 0 0 0 0 0 0 Reset
UART_AUTOBAUD_EN b(/)
UART_GLITCH_FILT bb (/)
513
ESP32-S2 TRM ( 1.3)
23 UART (UART)
GoBack
Register 23.17. UART_LOWPULSE_REG (0x0028)
(reserved)
31
20 19
000000000000
UART_LOWPULSE_MIN_CNT 0xfffff
UART_LOWPULSE_MIN_CNT b()
0
Reset
Register 23.18. UART_HIGHPULSE_REG (0x002C)
(reserved)
31
20 19
000000000000
UART_HIGHPULSE_MIN_CNT 0xfffff
UART_HIGHPULSE_MIN_CNT bb()
0
Reset
Register 23.19. UART_RXD_CNT_REG (0x0030)
(reserved)
31
10 9
0000000000000000000000
UART_RXD_EDGE_CNT
0
0x0
Reset
UART_RXD_EDGE_CNT RXD b b
UART_REG_LOWPULSE_MIN_CNTaUART_REG_HIGHPULSE_MIN_CNTa
UART_REG_POSEDGE_MIN_CNT UART_REG_NEGEDGE_MIN_CNT
UART_RXD_EDGE_CNT RXD b()
514
ESP32-S2 TRM ( 1.3)
23 UART (UART)
GoBack
Register 23.20. UART_POSPULSE_REG (0x006C)
(reserved)
31
20 19
000000000000
UART_POSEDGE_MIN_CNT 0xfffff
0
Reset
UART_POSEDGE_MIN_CNT bb()
Register 23.21. UART_NEGPULSE_REG (0x0070)
(reserved)
31
20 19
000000000000
UART_NEGEDGE_MIN_CNT 0xfffff
0
Reset
UART_NEGEDGE_MIN_CNT bb()
UART_UTAXRDT_URATRSTN_DTRN(reserved)
31 30 29 28
26 25
0x0 0 0 0 0 0
Register 23.22. UART_STATUS_REG (0x001C)
UART_TXFIFO_CNT 0x0
UART_URAXRDT_UCATRSTN_DSRN(reserved)
16 15 14 13 12
10 9
0 0 00 0 0
UART_RXFIFO_CNT RX FIFO b() UART_DSRN UART DSR b() UART_CTSN UART CTS b() UART_RXD UART RXD b() UART_TXFIFO_CNT TX FIFO b() UART_DTRN UART DTR b() UART_RTSN UART RTS b() UART_TXD UART TXD b()
UART_RXFIFO_CNT 0x0
0
Reset
515
ESP32-S2 TRM ( 1.3)
23 UART (UART)
GoBack
Register 23.23. UART_MEM_TX_STATUS_REG (0x0060)
(reserved)
31
21 20
00000000000
UART_TX_RADDR 0x0
(reserved)
11 10 9
0
UART_APB_TX_WADDR
0
0x0
Reset
UART_APB_TX_WADDR APB TX FIFO TX FIFO b() UART_TX_RADDR TX FSM Tx_FIFO_Ctrl TX FIFO b()
Register 23.24. UART_MEM_RX_STATUS_REG (0x0064)
(reserved)
31
21 20
00000000000
UART_RX_WADDR 0x0
(reserved)
11 10 9
0
UART_APB_RX_RADDR
0
0x0
Reset
UART_APB_RX_RADDR APB RX FIFO RX FIFO b( )
UART_RX_WADDR Rx_FIFO_Ctrl RX FIFO RX FIFO b()
Register 23.25. UART_FSM_STATUS_REG (0x0068)
(reserved)
31
87
000000000000000000000000
UART_ST_UTX_OUT UART_ST_URX_OUT
43
0
0x0
0x0
Reset
UART_ST_URX_OUT b() UART_ST_UTX_OUT b()
516
ESP32-S2 TRM ( 1.3)
23 UART (UART)
GoBack
Register 23.26. UART_AT_CMD_PRECNT_REG (0x004C)
(reserved)
31
16 15
0000000000000000
UART_PRE_IDLE_NUM 0x901
0
Reset
UART_PRE_IDLE_NUM AT_CMD b AT_CMD b(/)
Register 23.27. UART_AT_CMD_POSTCNT_REG (0x0050)
(reserved)
31
16 15
0000000000000000
UART_POST_IDLE_NUM 0x901
0
Reset
UART_POST_IDLE_NUM AT_CMD b AT_CMD b(/)
Register 23.28. UART_AT_CMD_GAPTOUT_REG (0x0054)
(reserved)
31
16 15
0000000000000000
UART_RX_GAP_TOUT 11
0
Reset
UART_RX_GAP_TOUT AT_CMD b/ AT_CMD b(/)
517
ESP32-S2 TRM ( 1.3)
23 UART (UART)
Register 23.29. UART_AT_CMD_CHAR_REG (0x0058)
(reserved)
31
16 15
0000000000000000
UART_CHAR_NUM
87
0x3
UART_AT_CMD_CHAR AT_CMD b(/) UART_CHAR_NUM AT_CMD b(/)
GoBack
UART_AT_CMD_CHAR
0
0x2b
Reset
Register 23.30. UART_DATE_REG (0x0074)
UART_DATE
31
0x18082800
UART_DATE b(/)
0
Reset
518
ESP32-S2 TRM ( 1.3)
23 UART (UART)
GoBack
Register 23.31. UHCI_CONF0_REG (0x0000)
(reserved)
UHCI_UUHACRIT_U_CHRLCXKI___UBEEHNRNCKCI__OUELDHOEECFN_I___CUEEURHNOACCFR_I_T_EUE_CNHNIRDCCLI__EUH_RHEEECCOAID__FUS__EHENEECPNNIE_(RrMe_sEEeMNrUv_eHTdRC)AI_NUINHS_DCESI_(NCOreRUs_TeBDrUvUSeHRCdCSR)IT__U_UBHEAUCNRRIT_SU1UT_HA_CCREEIT_NU0OH_UCCTIE__UOEHOUCFTI___UOMNHUOOCT_DI__RUEOAEHUUSCTTTIAO__URIL_NHTOW_C_ORLIC_POBULA_AOHRTHCCPEBK_IS_MTUTAEH_HSRCBTSI_MUTOH_UFCTIIF__OIRN_S_RTRSSTT
31
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Reset
UHCI_IN_RST DMA FSMb(/) UHCI_OUT_RST DMA FSMb(/) UHCI_AHBM_FIFO_RST DMA cmdFIFO AHB b(/) UHCI_AHBM_RST DMA AHB b(/) UHCI_IN_LOOP_TEST b(/) UHCI_OUT_LOOP_TEST b(/) UHCI_OUT_AUTO_WRBACK TX FIFO b
(/) UHCI_OUT_NO_RESTART_CLR b(/) UHCI_OUT_EOF_MODE UHCI_OUT_EOF_INT b1DMA FIFO
b0AHB FIFO b(/) UHCI_UART0_CE UHCI UART0 b(/) UHCI_UART1_CE UHCI UART1 b(/) UHCI_OUTDSCR_BURST_EN DMA b1b0b
(/) UHCI_INDSCR_BURST_EN DMA b1b0b
(/) UHCI_MEM_TRANS_EN 1UHCI DMA INFIFOb(/) UHCI_SEPER_EN b(/) UHCI_HEAD_EN b(/) UHCI_CRC_REC_EN UHCI 16 CRCb(/) UHCI_UART_IDLE_EOF_EN 1UHCI UART b(/) UHCI_LEN_EOF_EN 1UHCI b
UHCI_HEAD_EN 1 UCHI UHCI_HEAD_EN 0 b 0UHCI 0xC0 b(/) ...
519
ESP32-S2 TRM ( 1.3)
23 UART (UART) Register 23.31. UHCI_CONF0_REG (0x0000)
GoBack
...
UHCI_ENCODE_CRC_EN 16 CCITT-CRC b (/)
UHCI_CLK_EN 1b0b(/)
UHCI_UART_RX_BRK_EOF_EN 1UART NULL UHCI b (/)
Register 23.32. UHCI_CONF1_REG (0x002C)
(reserved)
31
21 20
00000000000
UHCI_DMA_INFIFO_FULL_THRS
UHCI_USHWC_I_SUWTHAACRITIT_U_CSHHWCEI_C_USTKHTX_AC_ORIA_WUTCTNHKXCE__RCNI_UHUSHEMACCV_IKE_RU__CEHSHRCUECIMA__UDC_DHHRICSEEAIC_BCKL_HESEECQK__ESNUM_EN
98 7 6 5 4 3 2 1 0
0
0 0 0 1 1 0 0 1 1 Reset
UHCI_CHECK_SUM_EN UHCI b(/) UHCI_CHECK_SEQ_EN UHCI b(/) UHCI_CRC_DISABLE CRC bUHCI 1b(/) UHCI_SAVE_HEAD UHCI b(/) UHCI_TX_CHECK_SUM_RE b(/) UHCI_TX_ACK_NUM_RE ACK b(/) UHCI_CHECK_OWNER 1 DMA 0b
(/) UHCI_WAIT_SW_START 1 UHCI ST_SW_WAIT b(/) UHCI_SW_START UHCI_ENCODE_STATE ST_SW_WAIT 1 UHCI
b(/) UHCI_DMA_INFIFO_FULL_THRS RX FIFO
UHCI_DMA_INFIFO_FULL_WM_INT b(/)
520
ESP32-S2 TRM ( 1.3)
23 UART (UART)
GoBack
Register 23.33. UHCI_AHB_TEST_REG (0x0048)
(reserved)
UHCI_AH(rBe_sTeErvSeTdA)DUDHRCI_AHB_TESTMODE
31
65
432
0
00000000000000000000000000 0 0
0
Reset
UHCI_AHB_TESTMODE b(/) UHCI_AHB_TESTADDR b(/)
Register 23.34. UHCI_ESCAPE_CONF_REG (0x0064)
(reserved)
UHCI_URHXC_I1_3UR_HXEC_SI1_C1U_R_HEXECS_NICD_U_BRHEX_CN_EICS_UT0CHX__C_EE1ISN3_UTC_HX_EC_SE1ICN1_U_T_HEXESC_NCDI__BTEX_N_ECS0C__EESNC_EN
31
87 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 Reset
UHCI_TX_C0_ESC_EN DMA 0xC0b(/) UHCI_TX_DB_ESC_EN DMA 0xDBb(/) UHCI_TX_11_ESC_EN DMA 0x11b(/) UHCI_TX_13_ESC_EN DMA 0x13b(/) UHCI_RX_C0_ESC_EN DMA 0xC0b(/) UHCI_RX_DB_ESC_EN DMA 0xDBb(/) UHCI_RX_11_ESC_EN DMA 0x11b(/) UHCI_RX_13_ESC_EN DMA 0x13b(/)
521
ESP32-S2 TRM ( 1.3)
23 UART (UART)
GoBack
Register 23.35. UHCI_HUNG_CONF_REG (0x0068)
(reserved)
UHCI_RXFIFUOH_CTII_MREXOFUIFTO__ETNIMAEOUT_SHIFTUHCI_RXFIFO_TIMEOUT UHCI_TXFIFUOH_CTII_MTEXOFUIFTO__ETNIMAEOUT_SHIFTUHCI_TXFIFO_TIMEOUT
31
24 23 22
20 19
12 11 10
87
0
0 0 0 0 0 0 0 01
0
0x10
1
0
0x10
Reset
UHCI_TXFIFO_TIMEOUT bDMA UHCI_TX_HUNG_INT b(/)
UHCI_TXFIFO_TIMEOUT_SHIFT b(/) UHCI_TXFIFO_TIMEOUT_ENA TX FIFO b(/) UHCI_RXFIFO_TIMEOUT bDMA RAM UHCI_RX_HUNG_INT b
(/) UHCI_RXFIFO_TIMEOUT_SHIFT b(/) UHCI_RXFIFO_TIMEOUT_ENA DMA b(/)
Register 23.36. UHCI_QUICK_SENT_REG (0x0074)
(reserved)
UHCI_ALWAUYHSC_IS_EANLDW_AUEYHNSC_IS_ESNINDG_ULNEHU_CMSI_ESNIDN_GELNE_SEND_NUM
31
876
432
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00
0x0
0
0x0 Reset
UHCI_SINGLE_SEND_NUM single_send b(/) UHCI_SINGLE_SEND_EN single_send b(/) UHCI_ALWAYS_SEND_NUM always_send b(/) UHCI_ALWAYS_SEND_EN always_send b(/)
522
ESP32-S2 TRM ( 1.3)
23 UART (UART)
GoBack
Register 23.37. UHCI_Q0_WORD0_REG (0x0078)
UHCI_SEND_Q0_WORD0
31
0
0x000000
Reset
UHCI_SEND_Q0_WORD0 UHCI_ALWAYS_SEND_NUM UHCI_SINGLE_SEND_NUM b(/)
Register 23.38. UHCI_Q0_WORD1_REG (0x007C)
UHCI_SEND_Q0_WORD1
31
0
0x000000
Reset
UHCI_SEND_Q0_WORD1 UHCI_ALWAYS_SEND_NUM UHCI_SINGLE_SEND_NUM b(/)
Register 23.39. UHCI_Q1_WORD0_REG (0x0080)
UHCI_SEND_Q1_WORD0
31
0
0x000000
Reset
UHCI_SEND_Q1_WORD0 UHCI_ALWAYS_SEND_NUM UHCI_SINGLE_SEND_NUM b(/)
523
ESP32-S2 TRM ( 1.3)
23 UART (UART)
GoBack
Register 23.40. UHCI_Q1_WORD1_REG (0x0084)
UHCI_SEND_Q1_WORD1
31
0
0x000000
Reset
UHCI_SEND_Q1_WORD1 UHCI_ALWAYS_SEND_NUM UHCI_SINGLE_SEND_NUM b(/)
Register 23.41. UHCI_Q2_WORD0_REG (0x0088)
UHCI_SEND_Q2_WORD0
31
0
0x000000
Reset
UHCI_SEND_Q2_WORD0 UHCI_ALWAYS_SEND_NUM UHCI_SINGLE_SEND_NUM b(/)
Register 23.42. UHCI_Q2_WORD1_REG (0x008C)
UHCI_SEND_Q2_WORD1
31
0
0x000000
Reset
UHCI_SEND_Q2_WORD1 UHCI_ALWAYS_SEND_NUM UHCI_SINGLE_SEND_NUM b(/)
524
ESP32-S2 TRM ( 1.3)
23 UART (UART)
GoBack
Register 23.43. UHCI_Q3_WORD0_REG (0x0090)
UHCI_SEND_Q3_WORD0
31
0
0x000000
Reset
UHCI_SEND_Q3_WORD0 UHCI_ALWAYS_SEND_NUM UHCI_SINGLE_SEND_NUM b(/)
Register 23.44. UHCI_Q3_WORD1_REG (0x0094)
UHCI_SEND_Q3_WORD1
31
0
0x000000
Reset
UHCI_SEND_Q3_WORD1 UHCI_ALWAYS_SEND_NUM UHCI_SINGLE_SEND_NUM b(/)
Register 23.45. UHCI_Q4_WORD0_REG (0x0098)
UHCI_SEND_Q4_WORD0
31
0
0x000000
Reset
UHCI_SEND_Q4_WORD0 UHCI_ALWAYS_SEND_NUM UHCI_SINGLE_SEND_NUM b(/)
525
ESP32-S2 TRM ( 1.3)
23 UART (UART)
GoBack
Register 23.46. UHCI_Q4_WORD1_REG (0x009C)
UHCI_SEND_Q4_WORD1
31
0
0x000000
Reset
UHCI_SEND_Q4_WORD1 UHCI_ALWAYS_SEND_NUM UHCI_SINGLE_SEND_NUM b(/)
Register 23.47. UHCI_Q5_WORD0_REG (0x00A0)
UHCI_SEND_Q5_WORD0
31
0
0x000000
Reset
UHCI_SEND_Q5_WORD0 UHCI_ALWAYS_SEND_NUM UHCI_SINGLE_SEND_NUM b(/)
Register 23.48. UHCI_Q5_WORD1_REG (0x00A4)
UHCI_SEND_Q5_WORD1
31
0
0x000000
Reset
UHCI_SEND_Q5_WORD1 UHCI_ALWAYS_SEND_NUM UHCI_SINGLE_SEND_NUM b(/)
526
ESP32-S2 TRM ( 1.3)
23 UART (UART)
GoBack
Register 23.49. UHCI_Q6_WORD0_REG (0x00A8)
UHCI_SEND_Q6_WORD0
31
0
0x000000
Reset
UHCI_SEND_Q6_WORD0 UHCI_ALWAYS_SEND_NUM UHCI_SINGLE_SEND_NUM b(/)
Register 23.50. UHCI_Q6_WORD1_REG (0x00AC)
UHCI_SEND_Q6_WORD1
31
0
0x000000
Reset
UHCI_SEND_Q6_WORD1 UHCI_ALWAYS_SEND_NUM UHCI_SINGLE_SEND_NUM b(/)
Register 23.51. UHCI_ESC_CONF0_REG (0x00B0)
(reserved)
31
24 23
00000000
UHCI_SEPER_ESC_CHAR1
16 15
0xdc
UHCI_SEPER_ESC_CHAR0
87
0xdb
UHCI_SEPER_CHAR
0
0xc0
Reset
UHCI_SEPER_CHAR 0xC0b(/) UHCI_SEPER_ESC_CHAR0 SLIP 0xDBb(/) UHCI_SEPER_ESC_CHAR1 SLIP 0xDCb(/)
527
ESP32-S2 TRM ( 1.3)
23 UART (UART)
GoBack
Register 23.52. UHCI_ESC_CONF1_REG (0x00B4)
(reserved)
31
24 23
00000000
UHCI_ESC_SEQ0_CHAR1
16 15
0xdd
UHCI_ESC_SEQ0_CHAR0
87
0xdb
UHCI_ESC_SEQ0
0
0xdb
Reset
UHCI_ESC_SEQ0 SLIP 0xDBb(/)
UHCI_ESC_SEQ0_CHAR0 SLIP UHCI_ESC_SEQ0 0xDBb (/)
UHCI_ESC_SEQ0_CHAR1 SLIP UHCI_ESC_SEQ0 0xDDb (/)
Register 23.53. UHCI_ESC_CONF2_REG (0x00B8)
(reserved)
31
24 23
00000000
UHCI_ESC_SEQ1_CHAR1
16 15
0xde
UHCI_ESC_SEQ1_CHAR0
87
0xdb
UHCI_ESC_SEQ1
0
0x11
Reset
UHCI_ESC_SEQ1 0x11b(/) UHCI_ESC_SEQ1_CHAR0 SLIP UHCI_ESC_SEQ1 0xDBb(/)
UHCI_ESC_SEQ1_CHAR1 SLIP UHCI_ESC_SEQ1 0xDEb(/)
528
ESP32-S2 TRM ( 1.3)
23 UART (UART)
GoBack
Register 23.54. UHCI_ESC_CONF3_REG (0x00BC)
(reserved)
31
24 23
00000000
UHCI_ESC_SEQ2_CHAR1
16 15
0xdf
UHCI_ESC_SEQ2_CHAR0
87
0xdb
UHCI_ESC_SEQ2
0
0x13
Reset
UHCI_ESC_SEQ2 0x13b(/)
UHCI_ESC_SEQ2_CHAR0 SLIP UHCI_ESC_SEQ2 0xDBb (/)
UHCI_ESC_SEQ2_CHAR1 SLIP UHCI_ESC_SEQ2 0xDFb (/)
Register 23.55. UHCI_PKT_THRES_REG (0x00C0)
(reserved)
31
13 12
0000000000000000000
UHCI_PKT_THRS 0x80
UHCI_PKT_THRS UHCI_HEAD_EN 0 b(/)
0
Reset
529
ESP32-S2 TRM ( 1.3)
23 UART (UART)
GoBack
Register 23.56. UHCI_INT_RAW_REG (0x0004)
(reserved)
UHCI_UDHMCAI_U_SIHNECNFIID_FUS_OHEA_CN_FID_RUUOE_LHGSULC___TIWQR__UTOE_MHOGUINC_T_TIATIQN_LU_LII_TN_NHR_IENK_ACRO_WDTIA_UFE_SWO_OHRCUIFACRNT_WI_T__EUE_IDRNHMRSR_CAPC_DIWT_RIUSNYO_HCT_UECR_IRTNI_R__RTUEAOE__HRWOUIRCNRFTA_IT___WUI_NIIDNNHRTO_TCA_N_WEIR_UERRAI_NRHAWIW__CNESIT_OUU_INFHCR__C_AIDIEWN_UOOTTHFNX_C__REIHI_AN_UUWIRTNHN_XTCG_R_IH_A_RUTWIUANHXNWTC_G_SI__RTRIAANXRWT_T_S_RTINAARWTT__RIANWT_RAW
31
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UHCI_RX_START_INT_RAW UHCI_RX_START_INT b b()
UHCI_TX_START_INT_RAW UHCI_TX_START_INT bDMA b()
UHCI_RX_HUNG_INT_RAW UHCI_RX_HUNG_INT bDMA b()
UHCI_TX_HUNG_INT_RAW UHCI_TX_HUNG_INT bDMA RAM b()
UHCI_IN_DONE_INT_RAW UHCI_IN_DONE_INT b b()
UHCI_IN_SUC_EOF_INT_RAW UHCI_IN_SUC_EOF_INT b b()
UHCI_IN_ERR_EOF_INT_RAW UHCI_IN_ERR_EOF_INT b EOF b()
UHCI_OUT_DONE_INT_RAW UHCI_OUT_DONE_INT b b()
UHCI_OUT_EOF_INT_RAW UHCI_OUT_EOF_INT b EOF b()
UHCI_IN_DSCR_ERR_INT_RAW UHCI_IN_DSCR_ERR_INT b b()
UHCI_OUT_DSCR_ERR_INT_RAW UHCI_OUT_DSCR_ERR_INT b b()
UHCI_IN_DSCR_EMPTY_INT_RAW UHCI_IN_DSCR_EMPTY_INT bDMA b()
UHCI_OUTLINK_EOF_ERR_INT_RAW
...
530
ESP32-S2 TRM ( 1.3)
23 UART (UART) Register 23.56. UHCI_INT_RAW_REG (0x0004)
GoBack
... UHCI_OUTLINK_EOF_ERR_INT b EOF b()
UHCI_OUT_TOTAL_EOF_INT_RAW UHCI_OUT_TOTAL_EOF_INT b b()
UHCI_SEND_S_REG_Q_INT_RAW UHCI_SEND_S_REG_Q_INT bDMA single_send b()
UHCI_SEND_A_REG_Q_INT_RAW UHCI_SEND_A_REG_Q_INT bDMA always_send b()
UHCI_DMA_INFIFO_FULL_WM_INT_RAW UHCI_DMA_INFIFO_FULL_WM_INT b DMA RX FIFO b()
531
ESP32-S2 TRM ( 1.3)
23 UART (UART)
GoBack
Register 23.57. UHCI_INT_ST_REG (0x0008)
(reserved)
UHCI_UDHMCAI_U_SIHNECNFIID_FUS_OHEA_CN_FID_RUUOE_LHGSULC___TIWQR__UTOE_MHOGUINC_T_TIATIQN_LU_LII_TN_NHS_IETNK_CSO_DTIT_UFE_SO_OSHCUITFCRNT_I_T__EUE_IDRNHMSSR_CTPC_DIT_RIUSNYO_HCT_UECR_IRTNI_S__RTUTEOE__HROUISCNRFTT_IT___UI_NIIDNNHSTOT_TC_N_EIS_UERSTI_TNRHI__CNESIT_OUU_INFHCS__C_TIDIEN_UOOTTHFNX_C__SEIHIT_N_UUIRTNHN_XTCG_S_ITH__SUTIUTNHXNTC_G_SI__STRIATNXRT_T_S_STINATRTT__SITNT_ST
31
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UHCI_RX_START_INT_ST UHCI_RX_START_INT_ENA 1 UHCI_RX_START_INT b()
UHCI_TX_START_INT_ST UHCI_TX_START_INT_ENA 1 UHCI_TX_START_INT b()
UHCI_RX_HUNG_INT_ST UHCI_RX_HUNG_INT_ENA 1 UHCI_RX_HUNG_INT b()
UHCI_TX_HUNG_INT_ST UHCI_TX_HUNG_INT_ENA 1 UHCI_TX_HUNG_INT b()
UHCI_IN_DONE_INT_ST UHCI_IN_DONE_INT_ENA 1 UHCI_IN_DONE_INT b()
UHCI_IN_SUC_EOF_INT_ST UHCI_IN_SUC_EOF_INT_ENA 1 UHCI_IN_SUC_EOF_INT b()
UHCI_IN_ERR_EOF_INT_ST UHCI_IN_ERR_EOF_INT_ENA 1 UHCI_IN_ERR_EOF_INT b()
UHCI_OUT_DONE_INT_ST UHCI_OUT_DONE_INT_ENA 1 UHCI_OUT_DONE_INT b()
...
532
ESP32-S2 TRM ( 1.3)
23 UART (UART) Register 23.57. UHCI_INT_ST_REG (0x0008)
GoBack
...
UHCI_OUT_EOF_INT_ST UHCI_OUT_EOF_INT_ENA 1 UHCI_OUT_EOF_INT b()
UHCI_IN_DSCR_ERR_INT_ST UHCI_IN_DSCR_ERR_INT_ENA 1 UHCI_IN_DSCR_ERR_INT b()
UHCI_OUT_DSCR_ERR_INT_ST UHCI_OUT_DSCR_ERR_INT_ENA
1
UHCI_OUT_DSCR_ERR_INT b()
UHCI_IN_DSCR_EMPTY_INT_ST UHCI_IN_DSCR_EMPTY_INT_ENA
1
UHCI_IN_DSCR_EMPTY_INT b()
UHCI_OUTLINK_EOF_ERR_INT_ST UHCI_OUTLINK_EOF_ERR_INT_ENA
1
UHCI_OUTLINK_EOF_ERR_INT b()
UHCI_OUT_TOTAL_EOF_INT_ST UHCI_OUT_TOTAL_EOF_INT_ENA
1
UHCI_OUT_TOTAL_EOF_INT b()
UHCI_SEND_S_REG_Q_INT_ST UHCI_SEND_S_REG_Q_INT_ENA
1
UHCI_SEND_S_REG_Q_INT b()
UHCI_SEND_A_REG_Q_INT_ST UHCI_SEND_A_REG_Q_INT_ENA
1
UHCI_SEND_A_REG_Q_INT b()
UHCI_DMA_INFIFO_FULL_WM_INT_ST UHCI_DMA_INFIFO_FULL_WM_INT_ENA 1 UHCI_DMA_INFIFO_FULL_WM_INT b()
533
ESP32-S2 TRM ( 1.3)
23 UART (UART)
GoBack
Register 23.58. UHCI_INT_ENA_REG (0x000C)
(reserved)
UHCI_UDHMCAI_U_SIHNECNFIID_FUS_OHEA_CN_FID_RUUOE_LHGSULC___TIWQR__UTOE_MHOGUINC_T_TIATIQN_LU_LII_TN_NHE_IENNK_CEO_DTAIN_UFE_SOA_OHECUINFCRNT_AI_T__EUE_IDRNHMESR_CNPC_DIAT_RIUSNYO_HCT_UECR_IRTNI_E__RTUNEOE__HRAOUIECNRFTN_IT___AUI_NIIDNNHETO_NTC_N_EIAE_UERENI_NNRHAI_A_CNESIT_OUU_INFHCE__C_NIDIENA_UOOTTHFNX_C__EEIHIN_N_UUIARTNHN_XTCG_E_IHN__EUTIUANNHXNATC_G_SI__ETRIANNXRAT_T_S_ETINANRTAT__EINNAT_ENA
31
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UHCI_RX_START_INT_ENA UHCI_RX_START_INT b(/) UHCI_TX_START_INT_ENA UHCI_TX_START_INT b(/) UHCI_RX_HUNG_INT_ENA UHCI_RX_HUNG_INT b(/) UHCI_TX_HUNG_INT_ENA UHCI_TX_HUNG_INT b(/) UHCI_IN_DONE_INT_ENA UHCI_IN_DONE_INT b(/) UHCI_IN_SUC_EOF_INT_ENA UHCI_IN_SUC_EOF_INT b(/) UHCI_IN_ERR_EOF_INT_ENA UHCI_IN_ERR_EOF_INT b(/) UHCI_OUT_DONE_INT_ENA UHCI_OUT_DONE_INT b(/) UHCI_OUT_EOF_INT_ENA UHCI_OUT_EOF_INT b(/) UHCI_IN_DSCR_ERR_INT_ENA UHCI_IN_DSCR_ERR_INT b(/) UHCI_OUT_DSCR_ERR_INT_ENA UHCI_OUT_DSCR_ERR_INT b(/) UHCI_IN_DSCR_EMPTY_INT_ENA UHCI_IN_DSCR_EMPTY_INT b(/) UHCI_OUTLINK_EOF_ERR_INT_ENA UHCI_OUTLINK_EOF_ERR_INT b(/) UHCI_OUT_TOTAL_EOF_INT_ENA UHCI_OUT_TOTAL_EOF_INT b(/) UHCI_SEND_S_REG_Q_INT_ENA UHCI_SEND_S_REG_Q_INT b(/) UHCI_SEND_A_REG_Q_INT_ENA UHCI_SEND_A_REG_Q_INT b(/) UHCI_DMA_INFIFO_FULL_WM_INT_ENA UHCI_DMA_INFIFO_FULL_WM_INT b
(/)
534
ESP32-S2 TRM ( 1.3)
23 UART (UART)
GoBack
Register 23.59. UHCI_INT_CLR_REG (0x0010)
(reserved)
UHCI_UDHMCAI_U_SIHNECNFIID_FUS_OHEA_CN_FID_RUUOE_LHGSULC___TIWQR__UTOE_MHOGUINC_T_TIATIQN_LU_LII_TN_NCH_IENK_LCCOR_DTIL_UFE_SRO_OCHCUIFLCRNTR_I_T__EUE_IDRNHMCSR_CLPC_DRIT_RIUSNYO_HCT_UECR_IRTNIC___RTUELOE__HRROUICCNRFTL_IT___RUI_NIIDNNHCTO_TCL_NR_EIC_UECRLI_NRHLRIR__CNESIT_OUU_INFHCC__C_LIDIERN_UOOTTHFNX_C__CEIHI_LN_URUIRTNHN_XTCG_C_IH_L_CUTRIULNHXRNTC_G_SI__CTRIALNXRRT_T_S_CTINALRRTT__CILNRT_CLR
31
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UHCI_RX_START_INT_CLR UHCI_RX_START_INT b() UHCI_TX_START_INT_CLR UHCI_TX_START_INT b() UHCI_RX_HUNG_INT_CLR UHCI_RX_HUNG_INT b() UHCI_TX_HUNG_INT_CLR UHCI_TX_HUNG_INT b() UHCI_IN_DONE_INT_CLR UHCI_IN_DONE_INT b() UHCI_IN_SUC_EOF_INT_CLR UHCI_IN_SUC_EOF_INT b() UHCI_IN_ERR_EOF_INT_CLR UHCI_IN_ERR_EOF_INT b() UHCI_OUT_DONE_INT_CLR UHCI_OUT_DONE_INT b() UHCI_OUT_EOF_INT_CLR UHCI_OUT_EOF_INT b() UHCI_IN_DSCR_ERR_INT_CLR UHCI_IN_DSCR_ERR_INT b() UHCI_OUT_DSCR_ERR_INT_CLR UHCI_OUT_DSCR_ERR_INT b() UHCI_IN_DSCR_EMPTY_INT_CLR UHCI_IN_DSCR_EMPTY_INT b() UHCI_OUTLINK_EOF_ERR_INT_CLR UHCI_OUTLINK_EOF_ERR_INT b() UHCI_OUT_TOTAL_EOF_INT_CLR UHCI_OUT_TOTAL_EOF_INT b() UHCI_SEND_S_REG_Q_INT_CLR UHCI_SEND_S_REG_Q_INT b() UHCI_SEND_A_REG_Q_INT_CLR UHCI_SEND_A_REG_Q_INT b() UHCI_DMA_INFIFO_FULL_WM_INT_CLR UHCI_DMA_INFIFO_FULL_WM_INT b
()
535
ESP32-S2 TRM ( 1.3)
23 UART (UART)
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Register 23.60. UHCI_DMA_OUT_STATUS_REG (0x0014)
(reserved)
UHCI_UOHUCTI__OEMUTP_TFYULL
31
21 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Reset
UHCI_OUT_FULL 1DMA TX FIFO b() UHCI_OUT_EMPTY 1DMA TX FIFO b()
Register 23.61. UHCI_DMA_IN_STATUS_REG (0x001C)
(reserved)
UHCI_RX_ERR(_reCsAeUrvSeEdU)HCI_UINH_CEI_MINP_TFYULL
31
76
43
21 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0 0 1 0 Reset
UHCI_IN_FULL RX FIFO b()
UHCI_IN_EMPTY RX FIFO b()
UHCI_RX_ERR_CAUSE DMA b3'b001HCI 3'b010 HCI b3'b011HCI CRC 3'b100 0xC0 HCI 3'b101 0xC0 HCI 3'b110CRC b()
536
ESP32-S2 TRM ( 1.3)
23 UART (UART)
Register 23.62. UHCI_STATE0_REG (0x0030)
(reserved) UHCI_DECODE_STATEUHCI_INFIFO_CNT_DEUBHUCGI_IN_STATUEHCI_IN_DSCR_STATE
31 30
28 27
23 22
20 19 18 17
0
0
0
0
0
UHCI_INLINK_DSCR_ADDR 0
UHCI_INLINK_DSCR_ADDR b() UHCI_IN_DSCR_STATE b() UHCI_IN_STATE b() UHCI_INFIFO_CNT_DEBUG RX FIFO b() UHCI_DECODE_STATE UHCI b()
GoBack
0
Reset
Register 23.63. UHCI_STATE1_REG (0x0034)
(reserved) UHCI_ENCODE_STATEUHCI_OUTFIFO_CNT UHCI_OUT_STUAHTECI_OUT_DSCR_STATE
31 30
28 27
23 22
20 19 18 17
0
0
0
0
0
UHCI_OUTLINK_DSCR_ADDR 0
UHCI_OUTLINK_DSCR_ADDR b() UHCI_OUT_DSCR_STATE b() UHCI_OUT_STATE b() UHCI_OUTFIFO_CNT TX FIFO b() UHCI_ENCODE_STATE UHCI b()
0
Reset
537
ESP32-S2 TRM ( 1.3)
23 UART (UART)
GoBack
Register 23.64. UHCI_DMA_OUT_EOF_DES_ADDR_REG (0x0038)
UHCI_OUT_EOF_DES_ADDR
31
0
0x000000
Reset
UHCI_OUT_EOF_DES_ADDR EOF 1 b()
Register 23.65. UHCI_DMA_IN_SUC_EOF_DES_ADDR_REG (0x003C)
UHCI_IN_SUC_EOF_DES_ADDR
31
0x000000
UHCI_IN_SUC_EOF_DES_ADDR EOF b()
0
Reset
Register 23.66. UHCI_DMA_IN_ERR_EOF_DES_ADDR_REG (0x0040)
UHCI_IN_ERR_EOF_DES_ADDR
31
0x000000
UHCI_IN_ERR_EOF_DES_ADDR b()
0
Reset
538
ESP32-S2 TRM ( 1.3)
23 UART (UART)
GoBack
Register 23.67. UHCI_DMA_OUT_EOF_BFR_DES_ADDR_REG (0x0044)
UHCI_OUT_EOF_BFR_DES_ADDR
31
0x000000
UHCI_OUT_EOF_BFR_DES_ADDR b()
0
Reset
Register 23.68. UHCI_DMA_IN_DSCR_REG (0x004C)
UHCI_INLINK_DSCR
31
0
UHCI_INLINK_DSCR b()
0
Reset
Register 23.69. UHCI_DMA_IN_DSCR_BF0_REG (0x0050)
UHCI_INLINK_DSCR_BF0
31
0
UHCI_INLINK_DSCR_BF0 b()
0
Reset
539
ESP32-S2 TRM ( 1.3)
23 UART (UART)
Register 23.70. UHCI_DMA_OUT_DSCR_REG (0x0058)
UHCI_OUTLINK_DSCR
31
0
UHCI_OUTLINK_DSCR b()
Register 23.71. UHCI_DMA_OUT_DSCR_BF0_REG (0x005C)
UHCI_OUTLINK_DSCR_BF0
31
0
UHCI_OUTLINK_DSCR_BF0 b()
Register 23.72. UHCI_RX_HEAD_REG (0x0070)
UHCI_RX_HEAD
31
0x000000
UHCI_RX_HEAD ()
GoBack
0
Reset
0
Reset
0
Reset
540
ESP32-S2 TRM ( 1.3)
23 UART (UART)
GoBack
Register 23.73. UHCI_DMA_OUT_PUSH_REG (0x0018)
(reserved)
UHCI_OUTFIFO_PUSH(reserved)
31
17 16 15
98
0 0 0 0 0 0 0 0 0 0 0 0 0 0 000 0 0 0 0 0 0
UHCI_OUTFIFO_WDATA
0
0x0
Reset
UHCI_OUTFIFO_WDATA TX FIFO b(/) UHCI_OUTFIFO_PUSH TX FIFOb(/)
Register 23.74. UHCI_DMA_IN_POP_REG (0x0020)
(reserved)
UHCI_INFIFO_(PreOsPerved)
31
17 16 15
12 11
0 0 0 0 0 0 0 0 0 0 0 0 0 0 000 0 0 0
UHCI_INFIFO_RDATA 0x0
UHCI_INFIFO_RDATA RX FIFO b() UHCI_INFIFO_POP RX FIFO b(/)
0
Reset
Register 23.75. UHCI_DMA_OUT_LINK_REG (0x0024)
UHCI_UOHUCTI_LUOINHUKCT_I_LUPOIANHURKCTK_I_LROINEUSKTT_ALSIRTNTAKR_TSTOP
(reserved)
31 30 29 28 27
20 19
0 0 0 00 0 0 0 0 0 0 0
UHCI_OUTLINK_ADDR 0x000
0
Reset
UHCI_OUTLINK_ADDR 20 b(/) UHCI_OUTLINK_STOP b(/) UHCI_OUTLINK_START b(/) UHCI_OUTLINK_RESTART b(/) UHCI_OUTLINK_PARK 1 FSM b0 FSM b(
)
541
ESP32-S2 TRM ( 1.3)
23 UART (UART)
GoBack
Register 23.76. UHCI_DMA_IN_LINK_REG (0x0028)
UHCI_UINHLCIIN_UKINH_LCPIIAN_URKINHK_LCRIINE_SKINT_ALSIRTNTAKR_TSTOP (reserved)
31 30 29 28 27
UHCI_INLINK_AUTO_RET
21 20 19
0 0 0 00 0 0 0 0 0 0 1
UHCI_INLINK_ADDR 0x000
0
Reset
UHCI_INLINK_ADDR 20 b(/) UHCI_INLINK_AUTO_RET b(/) UHCI_INLINK_STOP b(/) UHCI_INLINK_START b(/) UHCI_INLINK_RESTART b(/) UHCI_INLINK_PARK 1 FSM b0 FSM b()
Register 23.77. UHCI_DATE_REG (0x00FC)
UHCI_DATE
31
0x18073001
UHCI_DATE b(/)
0
Reset
542
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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24
SPI (SPI)
24.1
ESP32-S2 SPI SPI0aSPI1a SPI2 (GP-SPI2) SPI3 (GP-SPI3) 24.1-1 b
24.1-1. SPI
SPI SPI
· SPI0 (CS)CS0 CS1bCS0 flashCS1 RAMbSPI0 cache EDMA
RAM b
RAMb
flash b cacheb
· SPI1 CS0 CS1bSPI1 CPU flashb · GP-SPI2 SPI DMA bGP-SPI2 b
GP-SPI2 CS CS0 ~ CS5b
· GP-SPI3 SPI ADC DAC DMA bGP-SPI3 bGP-SPI3 CS CS0 ~ CS2b
SPI0 SPI1 SPI bSPI0 SPI1 SPI SPICLKaSPICS0 ~ SPICS1aSPIDaSPIQaSPIWPaSPIHDaSPIIO4 ~ SPIIO7 SPIDQSbGP-SPI2 GP-SPI3 FSPI (Fast SPI) SPI3 b FSPI GP-SPI2 SPI b
SPI/FSPI/SPI3 I/O GPIO
· SPI GPIO IO MUX GPIO b
543
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
· FSPI GPIO IO MUX GPIO b · SPI3 GPIO GPIO b 5 IO MUX GPIO b
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24.2
SPI0 SPI1 b GP-SPI2 GP-SPI3 bSPI ESP32-S2 24.10-1b
24.2.1 GP-SPI2
24.2.1.1 GP-SPI2
GP-SPI2 · CMDaADDR DATA · SPI flasha RAM LCD b 1-bit SPI FSPICLKaFSPICS0 ~ FSPICS5aFSPID / FSPIQb 1-bit SPI b SPI FSPID SPI FSPID FSPIQb 2-bit Dual SPI FSPICLKaFSPICS0 ~ FSPICS5aFSPID FSPIQb FSPID FSPIQb 4-bit Quad SPI FSPICLKaFSPICS0 ~ FSPICS5aFSPIDaFSPIQaFSPIWP FSPIHDb FSPIDaFSPIQaFSPIWP FSPIHDb QPI FSPICLKaFSPICS0 ~ FSPICS5aFSPIDaFSPIQaFSPIWP FSPIHDb 8-bit Octal SPI FSPICLKaFSPICS0 ~ FSPICS5aFSPIDaFSPIQaFSPIWPa FSPIHD FSPIIO4 ~ FSPIIO7b FSPIDaFSPIQaFSPIWPa FSPIHD FSPIIO4 ~ FSPIIO7b OPI FSPICLKaFSPICS0 ~ FSPICS5aFSPIDaFSPIQaFSPIWPaFSPIHD FSPIIO4 ~ FSPIIO7b · Moto6800/I8080/ RGB 8-bit LCD · SPI APB 1 ~ n · SPI_CD CMD ADDR · SPI_CS SPI bca/aCMDa ADDRaDUMMY b · CS (Setup Time) (Hold Time) · DMA (Segmented Configure Transfer, SCT)
544
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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24.2.1.2 GP-SPI2
GP-SPI2 · bCMDaADDR DATA 24.3-1b 1-bit SPI FSPICLKaFSPICS0aFSPID / FSPIQb 1-bit SPI b SPI FSPID SPI FSPID FSPIQb 2-bit Dual SPI FSPICLKaFSPICS0aFSPID FSPIQb 4-bit Quad SPI FSPICLKaFSPICS0aFSPIDaFSPIQaFSPIWP FSPIHDb QPI FSPICLKaFSPICS0aFSPIDaFSPIQaFSPIWP FSPIHDb · SPI 40 MHz · 24.5.1 · (Segmented Transfer, ST)
24.2.1.3 GP-SPI2
GP-SPI2 · CPU 1 ~ 64 DMA 1 ~ n · (MSB) (LSB) · · SPI CPU GP-SPI2 buffer DMA RAM EDMA RAM b · a · SPI 0 ~ 3
24.2.2 GP-SPI3
24.2.2.1 GP-SPI3
GP-SPI3 · SPI APB 1 ~ n · 1-bit LCD · SPI_CD CMD ADDR
545
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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· SPI_CS SPI bca/aCMDa ADDRaDUMMY b
· CS · DMA
24.2.2.2 GP-SPI3
GP-SPI3 · SPI 40 MHz · 24.5.1 ·
24.2.2.3 GP-SPI3
GP-SPI3 · 1-bit SPI b 1-bit SPI b SPI SPI3_D SPI SPI3_D SPI3_Qb · CPU 1 ~ 64 DMA 1 ~ n · (MSB) (LSB) · · SPI CPU GP-SPI3 buffer DMA RAM · a · SPI 0 ~ 3
24.2.3 SPI
· SPI · SPI DMA
24.3 SPI
GP-SPI2 GP-SPI3 SPI SPI 24.3-1bGP-SPI2 GP-SPI3 24.3-1b
546
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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24.3-1. GP-SPI2/GP-SPI3
24.3-1. GP-SPI2 GP-SPI3
1-bit SPI Dual SPI
Quad SPI
Octal SPI QPI OPI
Dual Output Read Dual I/O Read Quad Output Read Quad I/O Read Octal Output Read Octal I/O Read
1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 4-bit 8-bit
1-bit 1-bit 2-bit 1-bit 4-bit 1-bit 8-bit 4-bit 8-bit
1-bit 2-bit 2-bit 4-bit 4-bit 8-bit 8-bit 4-bit 8-bit
GP-SPI2
GP-SPI3 _ _ _ _ _ _ _ _
GP-SPI3 GP-SPI2 bGP-SPI2 24.4 24.5 bGP-SPI2 GP-SPI3 24.6 bGP-SPI2
· SPI_USER_REG SPI_DOUTDIN 0b 1b
· SPI_SLAVE_REG SPI_SLAVE_MODE b 0b 1b
· SPI_CTRL_REG SPI_RD_BIT_ORDER SPI_WR_BIT_ORDER / b 0/ LSBb 1/ MSBb
GP-SPI2 DMA b ESP32-S2 CPU b DMA CPU SPI bDMA 24.4.7b
547
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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GP-SPI2 b SPI GP-SPI2 b En_SEG_TRANS b 24.5.4b
GP-SPI2 SPI 24.5-1 24.5-2 b
24.4 GP-SPI2
GP-SPI2 bGP-SPI2 b b
· 24.4.1 · 24.4.2 · 24.4.3 24.4.8 GP-SPI2 · 24.4.9 CS · 24.9 FSPICLK a
· b 8 b · CMD ADDR b
24.4.1
GP-SPI2 1/2/4/8-bit SPI flasha RAM LCD bGP-SPI2 flasha RAM LCD bGP-SPI2 24.4-1 GP-SPI2 b
548
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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24.4-1. GP-SPI2
GP-SPI2 1. IDLEGP-SPI2 b 2. CONF DMA b SPI_USR SPI_USR_CONF b CONF b 3. PREP SPI SPI CS b SPI_USR SPI_CS_SETUP b 4. CMDb SPI_USR SPI_USR_COMMAND b 5. ADDRb SPI_USR SPI_USR_ADDR b 6. DUMMYc DUMMY b SPI_USR SPI_USR_DUMMY b
549
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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7. DATA · DOUTb SPI_USR SPI_USR_MOSI b · DINb SPI_USR SPI_USR_MISO b
8. DONE SPI CS b SPI_USR b 24.4-1 GP-SPI2 gpc[22:0] bCONFaPREPaCMDa ADDRaDUMMYaDOUT DIN b GP-SPI2 b
24.4.2
GP-SPI2 GP-SPI2 b GP-SPI2 24.4-1 24.4-2b SPI_USER_REG SPI_OPI_MODE SPI_QPI_MODE OPI QPI b SPI_OPI_MODE SPI_QPI_MODEb
24.4-1. 1/2-bit
GP-SPI2 CMD
ADDR DUMMY DIN DOUT
1-bit FSPI
SPI_USR_COMMAND_VALUE SPI_USR_COMMAND_BITLEN SPI_USR_COMMAND
SPI_USR_ADDR_VALUE SPI_USR_ADDR_BITLEN SPI_USR_ADDR
SPI_USR_DUMMY_CYCLELEN SPI_USR_DUMMY
SPI_USR_MISO SPI_USR_MISO_DBITLEN
SPI_USR_MOSI SPI_USR_MOSI_DBITLEN
2-bit FSPI SPI_USR_COMMAND_VALUE SPI_USR_COMMAND_BITLEN SPI_FCMD_DUAL SPI_USR_COMMAND SPI_USR_ADDR_VALUE SPI_USR_ADDR_BITLEN SPI_USR_ADDR SPI_FADDR_DUAL SPI_USR_DUMMY_CYCLELEN SPI_USR_DUMMY SPI_USR_MISO SPI_USR_MISO_DBITLEN SPI_FREAD_DUAL SPI_USR_MOSI SPI_USR_MOSI_DBITLEN SPI_FWRITE_DUAL
GP-SPI2 CMD ADDR
24.4-2. 4/8-bit
4-bit FSPI SPI_USR_COMMAND_VALUE SPI_USR_COMMAND_BITLEN SPI_FCMD_QUAD SPI_USR_COMMAND SPI_USR_ADDR_VALUE SPI_USR_ADDR_BITLEN SPI_USR_ADDR SPI_FADDR_QUAD
8-bit FSPI SPI_USR_COMMAND_VALUE SPI_USR_COMMAND_BITLEN SPI_FCMD_OCT SPI_USR_COMMAND SPI_USR_ADDR_VALUE SPI_USR_ADDR_BITLEN SPI_USR_ADDR SPI_FADDR_OCT
550
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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GP-SPI2 DUMMY DIN
DOUT
24.4-2. 4/8-bit
4-bit FSPI SPI_USR_DUMMY_CYCLELEN SPI_USR_DUMMY SPI_USR_MISO SPI_USR_MISO_DBITLEN SPI_FREAD_QUAD SPI_USR_MOSI SPI_USR_MOSI_DBITLEN SPI_FWRITE_QUAD
8-bit FSPI SPI_USR_DUMMY_CYCLELEN SPI_USR_DUMMY SPI_USR_MISO SPI_USR_MISO_DBITLEN SPI_FREAD_OCT SPI_USR_MOSI SPI_USR_MOSI_DBITLEN SPI_FWRITE_OCT
24.4-1 24.4-2 FSPI c b GP-SPI2
· CMD 4-bit · ADDR 2-bit · DUMMY n · DIN 8-bit b 1. CMD b
· SPI_USR_COMMAND_VALUE · SPI_USR_COMMAND_BITLEN SPI_USR_COMMAND_BITLEN =
- 1 · SPI_FCMD_QUAD SPI_USR_COMMAND · SPI_FCMD_DUAL SPI_FCMD_OCTb 2. ADDR b · SPI_USR_ADDR_VALUE · SPI_USR_ADDR_BITLEN SPI_USR_ADDR_BITLEN = -
1 · SPI_USR_ADDR SPI_FADDR_DUAL · SPI_FADDR_QUAD SPI_FADDR_OCT 3. DUMMY b · SPI_USR_DUMMY_CYCLELEN DUMMY
SPI_USR_DUMMY_CYCLELEN = DUMMY (n) - 1 · SPI_USR_DUMMYb 4. DIN b
551
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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· SPI_USR_MISO_DBITLEN SPI_USR_MISO_DBITLEN = - 1
· SPI_FREAD_OCT SPI_USR_MISO
· SPI_FREAD_DUAL SPI_FREAD_QUAD
· DMA GP-SPI2 DMACPU b
5. SPI_USR_MOSI
6. SPI_USR GP-SPI2 b
cDOUT SPI_USR_MOSI SPI_USR_MOSI_DBITLEN SPI_USR_MISOb = SPI_USR_MOSI_DBITLEN + 1b CPU GP-SPI2 SPI_W0_REG ~ SPI_W17_REG DMA DMA TX buffer b LSBc 0 MSBb
SPI_USR_COMMAND_VALUE SPI_USR_ADDR_VALUE b
· SPI_USR_COMMAND_BITLEN < 8 SPI_USR_COMMAND_VALUE[7:0]
SPI_WR_BIT_ORDER SPI_USR_COMMAND_VALUE[7:0] SPI_USR_COMMAND_VALUE[SPI_USR_COMMAND_BITLEN:0]b
SPI_WR_BIT_ORDER SPI_USR_COMMAND_VALUE[7:0] SPI_USR_COMMAND_VALUE[7: 7-SPI_USR_COMMAND_BITLEN]b
· 7 < SPI_USR_COMMAND_BITLEN < 16 SPI_USR_COMMAND_VALUE[15:0]
SPI_WR_BIT_ORDER SPI_USR_COMMAND_VALUE[7:0] SPI_USR_COMMAND_VALUE[15:8] SPI_USR_COMMAND_VALUE[SPI_USR_COMMAND_BITLEN:8]b
SPI_WR_BIT_ORDER SPI_USR_COMMAND_VALUE[7:0] SPI_USR_COMMAND_VALUE[15:8] SPI_USR_COMMAND_VALUE[15: 15-SPI_USR_COMMAND_BITLEN]b
· SPI_USR_ADDR_BITLEN < 8 SPI_USR_ADDR_VALUE[7:0]
SPI_WR_BIT_ORDER SPI_USR_ADDR_VALUE[7:0] SPI_USR_ADDR_VALUE[SPI_USR_ADDR_BITLEN:0]b
SPI_WR_BIT_ORDER SPI_USR_ADDR_VALUE[7:0] SPI_USR_ADDR_VALUE[7: 7-SPI_USR_ADDR_BITLEN]b
· 7 < SPI_USR_ADDR_BITLEN < 16 SPI_USR_ADDR_VALUE[15:0]
SPI_WR_BIT_ORDER SPI_USR_ADDR_VALUE[7:0] SPI_USR_ADDR_VALUE[15:8] SPI_USR_ADDR_VALUE[SPI_USR_ADDR_BITLEN:8]b
552
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
GoBack
SPI_WR_BIT_ORDER SPI_USR_ADDR_VALUE[7:0] SPI_USR_ADDR_VALUE[15:8] SPI_USR_ADDR_VALUE[15: 15-SPI_USR_ADDR_BITLEN]b
GP-SPI2 1/2/4/8 ba 24.4-1 24.4-2b
24.4.3 c 1-bit
GP-SPI2 bSPI CLK CS 1-bit
· MOSIcFSPID · MISOcFSPIQ 24.4-2b
24.4-2. GP-SPI2 SPI
CMDaADDRaDUMMYaDOUT DIN b CMDaADDRaDUMMY b SPI_USR_MOSI_DBITLEN SPI_USR_MISO_DBITLEN b = SPI_USR_MOSI_DBITLEN/SPI_USR_MISO_DBITLEN + 1b
· SPI_DOUTDIN SPI_SLAVE_MODE 24.3b · SPI_CMD_REG SPI_USR b CPU / SPI_USER_REG SPI_RD_BYTE_ORDER SPI_WR_BYTE_ORDER bDMA 24.8b
24.4.4 c 1/2/4/8-bit
SPI bSPI CLK CS bSPI bSPI CMD + [ADDR +] [DUMMY +] [DOUT or DIN]ADDRaDUMMYaDOUT DIN b 24.4.2 CMDaADDRaDUMMYaDOUT DIN a b 24.4-1 24.4-2b GP-SPI2
1. CMD0 ~ 16 (MOSI)b
553
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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2. ADDR0 ~ 32 b 3. DUMMY0 ~ 256 FSPICLK b 4. DOUTCPU 0 ~ 576 c72 DMA 0 ~ 8 Mbitb 5. DINCPU 0 ~ 576 c72 DMA 0 ~ 8 Mbit
(MISO)b
1. 24.4-1 24.4-2 GP-SPI2 2. 24.4.9 CS 3. 24.9 FSPICLK 4.
· CPU MOSI SPI_W0_REG ~ SPI_W17_REG · DMA DMA TX/RX 24.8 5. FSPI b 6. SPI 7. SPI_CMD_REG SPI_USR 5 b GP-SPI2 fapb FSPICLK 24.9b GP-SPI2 I/O Tapb/2 b 24.9.4b GPIO DUMMY GP-SPI2 b
24.4.5 Flash RAM
GP-SPI2 1/2/4 flash RAM 24.4-3b
24.4-3. 4-bit GP-SPI2 Flash RAM
GP-SPI2 flash Quad Read 24.4-4 b GP-SPI2 SPI b
554
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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24.4-4. GP-SPI2 Flash SPI Quad
1/2/4/8 (Double Transfer Rate, DTR) SPI
· SPI_CMD_DTR_EN CMD DTR CMD (Single Transfer Rate, STR)b
· SPI_ADDR_DTR_EN ADDR DTR ADDR STR b · SPI_DATA_DTR_EN DIN DOUT DTR
STR b SPI_CMD_DTR_ENaSPI_ADDR_DTR_EN SPI_DATA_DTR_EN CMD STR ADDR DOUT/DIN DTR b GP-SPI2 FSPIDQS b DUMMY flash RAM DUMMY b
24.4.6 8-bit I8080/MT6800 LCD
GP-SPI2 8-bit LCD 24.4-5b
24.4-5. GP-SPI2 8-bit LCD
GP-SPI2 8-bit LCD I8080 24.4-6b 1. SPI_FCMD_OCT = 1SPI_USR_COMMAND = 1SPI_USR_COMMAND_VALUE[15:0] = 0x2C SPI_USR_COMMAND_BITLEN = 0xF 2. SPI_USR_ADDR = 0SPI_USR_DUMMY = 0SPI_USR_MISO = 0
555
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
GoBack
3. SPI_FWRITE_OCT = 1SPI_USR_MOSI = 1 SPI_USR_MOSI_DBITLEN = 1
4. 24.4.9 CS 5. CPU MOSI SPI_W0_REG ~ SPI_W17_REG DMA
DMA TX 6. 24.9 FSPICLK SPI 3 FSPICLK 7. FSPI 8. LCD 9. SPI_CMD_REG SPI_USR 7 b
24.4-6. 8-bit LCD
RDX FSPICLK WRX GPIO I8080 LCD b Moto6800 LCD I8080 b
24.4.7 DMA
SPI GP-SPI2 CPU b CPU GP-SPI2 GP-SPI2 DMA b CPU b GP-SPI2 CPU 24.4-7b
24.4-7. DMA
556
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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24.4-7 SPI (SCTi) GP-SPI2 CONF GP-SPI2 Conf_bufi b
SCT CONF DMA CONF CONF bufferb DMA TX CONF buffer TX data buffer SCT FSPI b
SCT GP-SPI2 a FSPI aDMA b SCT GP-SPI2 SPI_DMA_SEG_TRANS_DONEb
24.4-7 SCTi SCTj MISO SCTk MOSI biajak SCT b
SCT GP-SPI2 CS 24.4.9bCONF CS SPI_CMD_REG SPI_CONF_BITLEN[22:0] SPI_SLV_WRBUF_DLEN_REG SPI_CONF_BASE_BITLEN[6:0] bfapb 80 MHz FSPICLK APB_CLK 1 CONF CS 2 us ~ 0.2 sb FSPICLK cn n > 1CS b
1. SCT DMA CONF buffer TX data cb CONF buffer TX buffer b
2. SCT RX buffer b
3. CONF bufferaTX buffer RX bufferb
4. SPI_OUTLINK_ADDR CONF Head TX buffer SPI_DMA_OUT_LINK_REG SPI_OUTLINK_START TX DMAb
5. SPI_DMA_CONF_REG SPI_RX_EOF_EN b SPI_INLINK_ADDR RX buffer SPI_DMA_IN_LINK_REG SPI_INLINK_START RX DMAb
6. SPI_SLV_RD_BYTE_REG SPI_USR_CONF CONF b
7. SPI_SLAVE_REG SPI_INT_DMA_SEG_TRANS_EN SPI_DMA_SEG_TRANS_DONE b 24.11b
8. SCT b
9. SPI_CMD_REG SPI_USR DMA b
10. SPI_DMA_SEG_TRANS_DONE DMA b
CONF b DMA CONF bufferi SPI_BIT_MAP_WORD SCTi SPI b
SPI_BIT_MAP_WORD GP-SPI2 24.4-3 (BM) b 1b 0b
24.4-3. CONF GP-SPI
BM 0
SPI_CMD_REG
BM 14
SPI_HOLD_REG
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ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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1
SPI_ADDR_REG
15
SPI_DMA_INT_ENA_REG
2
SPI_CTRL_REG
16
SPI_DMA_INT_RAW_REG
3
SPI_CTRL1_REG
17
SPI_DMA_INT_CLR_REG
4
SPI_CTRL2_REG
18
SPI_DIN_MODE_REG
5
SPI_CLOCK_REG
19
SPI_DIN_NUM_REG
6
SPI_USER_REG
20
SPI_DOUT_MODE_REG
7
SPI_USER1_REG
21
SPI_DOUT_NUM_REG
8
SPI_USER2_REG
22
SPI_LCD_CTRL_REG
9
SPI_MOSI_DLEN_REG 23
SPI_LCD_CTRL1_REG
10
SPI_MISO_DLEN_REG 24
SPI_LCD_CTRL2_REG
11
SPI_MISC_REG
25
SPI_LCD_D_MODE_REG
12
SPI_SLAVE_REG
26
SPI_LCD_D_NUM_REG
13
SPI_FSM_REG
-
-
SPI_BIT_MAP_WORD CONF buffer b
CONF buffer SPI_BIT_MAP_WORD[31:28] Magic SPI_SLV_RD_BYTE_REG SPI_DMA_SEG_MAGIC_VALUE[3:0] b SPI_DMA_SEG_MAGIC_VALUE[3:0] b
· SPI_BIT_MAP_WORD[31:28] == SPI_DMA_SEG_MAGIC_VALUE[3:0] SPI_DMA_SEG_TRANS_DONE b
· SPI_BIT_MAP_WORD[31:28] != SPI_DMA_SEG_MAGIC_VALUE[3:0] GP-SPI2 spi_st IDLE b SPI_DMA_SEG_TRANS_DONE SPI_SLV_RDBUF_DLEN_REG SPI_SEG_MAGIC_ERR 1b
SPI_ADDR_REGaSPI_CTRL_REGaSPI_CLOCK_REGaSPI_USER_REG SPI_USER1_REG CONF buffer 24.4-4 24.4-5b
24.4-4. CONF bufferi
CONF bufferi SPI_BIT_MAP_WORD
SPI_ADDR_REG SPI_CTRL_REG SPI_CLOCK_REG SPI_USER_REG SPI_USER1_REG
CONF bufferi c
0x000000E6
b 24.4-5
SPI_BIT_MAP_WORD 1 1a2a5a
6a7 b
CONF bufferi SPI_ADDR_REG
b
CONF bufferi SPI_CTRL_REG
b
CONF bufferi SPI_CLOCK_REG
b
CONF bufferi SPI_USER_REG
b
CONF bufferi SPI_USER1_REG
b
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ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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BM
0
0
1
1
2
1
3
0
4
0
5
1
6
1
7
1
8
0
9
0
10
0
11
0
12
0
13
0
24.4-5. VS
BM
SPI_CMD_REG
14
0
SPI_ADDR_REG
15
0
SPI_CTRL_REG
16
0
SPI_CTRL1_REG
17
0
SPI_CTRL2_REG
18
0
SPI_CLOCK_REG
19
0
SPI_USER_REG
20
0
SPI_USER1_REG
21
0
SPI_USER2_REG
22
0
SPI_MOSI_DLEN_REG 23
0
SPI_MISO_DLEN_REG 24
0
SPI_MISC_REG
25
0
SPI_SLAVE_REG
26
0
SPI_FSM_REG
-
-
SPI_HOLD_REG SPI_DMA_INT_ENA_REG SPI_DMA_INT_RAW_REG SPI_DMA_INT_CLR_REG SPI_DIN_MODE_REG SPI_DIN_NUM_REG SPI_DOUT_MODE_REG SPI_DOUT_NUM_REG SPI_LCD_CTRL_REG SPI_LCD_CTRL1_REG SPI_LCD_CTRL2_REG SPI_LCD_D_MODE_REG SPI_LCD_D_NUM_REG -
DMA · SPI_SLV_RD_BYTE_REG SPI_USR_CONF · SPI_USER_REG SPI_USR_CONF_NXT · SPI_CMD_REG SPI_CONF_BITLEN[22:0]
SPI_USR SPI_USR_CONFb CONF buffer SPI_USR_CONF_NXT 1SPI_USR_CONF_NXT b
24.4.8 8-bit RGB LCD
ab 8-bit RGB LCD bb 8-bit RGB LCD 24.4-8 24.4-9b
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ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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24.4-8. RGB 8-bit LCD
24.4-9. RGB 8-bit LCD
24.4-7a 24.4-8 24.4-9 8 RGB
· b SPI_LCD_VA_HEIGHT[9:0] SPI_LCD_VA_HEIGHT[9:0] b
· TX buffer CONF bufferbGP-SPI2 FSPI_VSYNCaFSPI_HSYNCaFSPI_DE / FSPICLK b
· CONF CS aCS 24.4.7 24.4.9b
GP-SPI2 24.4-8 24.4-9 SPI CPU b
1. SPI_LCD_CTRL_REG SPI_LCD_MODE_EN RGB LCD
2. 24.4-8 24.4-9b n SPI_LCD_VA_HEIGHT[9:0] n
3. CS
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ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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4. SPI_USR_COMMANDaSPI_USR_ADDRaSPI_USR_DUMMY SPI_USR_MISO 5. SPI_FWRITE_OCT SPI_USR_MOSI SPI_USR_MOSI_DBITLEN
SPI_LCD_HA_WIDTH[11:0] * 8 -1 6. DMA TX TX buffer b ring-buffer ping-pang buffer
buffer 7. I/O b SPI_INT_TRANS_DONE_EN 8. LCD 9. SPI_USR b SPI_TRANS_DONE b
24.4.9 CS
SPI CS SPI c flash PSRAMbCS CS SPI CLK b 0 3 2 4 bCS CS b
SPI_USER_REG SPI_CS_SETUP SPI_CTRL2_REG SPI_CS_SETUP_TIME CS b
· SPI_CS_SETUP = 0 SPI CS 0.5 x T _SP I_CLK T _SP I_CLK SPI_CLK b
· SPI_CS_SETUP = 1 SPI CS (SPI_CS_SETUP_TIME + 1.5) x T _SP I_CLKb
SPI_USER_REG SPI_CS_HOLD SPI_CTRL2_REG SPI_CS_HOLD_TIME CS b
· SPI_CS_HOLD = 0 SPI CS 0.5 x T _SP I_CLK
· SPI_CS_HOLD = 1 SPI CS (SPI_CS_HOLD_TIME + 1.5) x T _SP I_CLKb
24.4-10 24.4-11 Flash RAM CS b
24.4-10. GP-SPI2 RAM CS
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ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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24.4-11. GP-SPI2 Flash CS
GP-SPI2 b 24.13b
24.5 GP-SPI2
GP-SPI2 SPI bGP-SPI2 1-bit SPIa2-bit Dual SPIa4-bit Quad SPI QPI 24.5.1 b SPI_SLAVE_REG SPI_SLAVE_MODE b CS CS b b
24.5.1
GP-SPI2 SPI b SPI_USER_REG SPI_DOUTDIN 1 0 b b/ a DUMMY b SPI_TRANS_DONE b CMD+ADDR+DUMMY+DATAcb SPI GP-SPI2 SPI GP-SPI2 bopb
1. CMD SPI 24.5-1 24.5-2 CMD 1-bit 4-bit QPI
2. ADDR CPU CMD1 CMD2 1/2/4-bit
3. DUMMYSPI b
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ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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4. CPU 0 ~ 72 DMA 0 ~ 2 MB CMD 1/2/4-bit b
ADDR DUMMY DMA b
CMD ADDR SPI_SLAVE1_REG SPI_SLV_LAST_COMMAND SPI_SLV_LAST_ADDR b GP-SPI2 CMD SPI_SLAVE1_REG SPI_SLV_CMD_ERR bSPI_SLV_CMD_ERR b
DMA CPU 24.7 24.8b
24.5.2 CMD
CMD b CMD SPI_SLV_CMD_ERR 1bCMD (8 bits) + ADDR (8 bits) + DUMMY + DATA 1-bit SPI DUMMY SPI SPI SPI DATA b CMD[3:0]
1. 0x1 (Wr_BUF)CPU bGP-SPI2 b SPI_W0_REG ~ SPI_W17_REGb
2. 0x2 (Rd_BUF)CPU b GP-SPI2 b SPI_W0_REG ~ SPI_W17_REGb
3. 0x3 (Wr_DMA)DMA bGP-SPI2 b GP-SPI2 DMA RX buffer b
4. 0x4 (Rd_DMA)DMA b GP-SPI2 b GP-SPI2 DMA TX bufferb
5. 0x7 (CMD7) SPI_SLV_CMD7_INT b DMA RX SPI_IN_SUC_EOF_INT b GP-SPI2 b
6. 0x8 (CMD8) SPI_SLV_CMD8_INT GP-SPI2 b
7. 0x9 (CMD9) SPI_SLV_CMD9_INT GP-SPI2 b
8. 0xA (CMDA) SPI_SLV_CMDA_INT GP-SPI2 b
CMDaADDR DATA 1/2/4-bit CMD[7:4] bDUMMY 1-bit 1-bit SPI SPI SPI SPI bCMD[7:4]
1. 0x0CMDaADDR DATA 1-bit b
2. 0x1CMD ADDR 1-bit bDATA 2-bit b
3. 0x2CMD ADDR 1-bit bDATA 4-bit b
4. 0x5CMD 1-bit bADDR DATA 2-bit b
5. 0xACMD 1-bit ADDR DATA 4-bit b QPI bCMD 0xA7a0xA8a 0xA9 0xAA QPI b
CMD[7:0] 0x05a0xA5a0x06 0xDD ADDRaDUMMY DATA b
1. 0x05 (End_SEG_TRANS) 0x05 SPI b
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24 SPI (SPI)
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2. 0xA5 (End_SEG_TRANS) 0xA5 QPI b 3. 0x06 (En_QPI)GP-SPI2 0x06 QPI b SPI_USER_REG
SPI_QPI_MODE b 4. 0xDD (Ex_QPI)GP-SPI2 0xDD QPI bSPI_QPI_MODE b GP-SPI2 CMD 24.5-1 24.5-2b
24.5-1. GP-SPI2 SPI CMD
Wr_BUF Rd_BUF Wr_DMA Rd_DMA CMD7 CMD8 CMD9 CMDA
CMD[7:0] 0x01 0x11 0x21 0x51 0xA1 0x02 0x12 0x22 0x52 0xA2 0x03 0x13 0x23 0x53 0xA3 0x04 0x14 0x24 0x54 0xA4 0x07 0x17 0x27 0x57 0x08 0x18 0x28 0x58 0x09 0x19 0x29 0x59 0x0A 0x1A 0x2A 0x5A
CMD 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit
ADDR 1-bit 1-bit 1-bit 2-bit 4-bit 1-bit 1-bit 1-bit 2-bit 4-bit 1-bit 1-bit 1-bit 2-bit 4-bit 1-bit 1-bit 1-bit 2-bit 4-bit -
DUMMY 8 4 4 4 4 8 4 4 4 4 8 4 4 4 4 8 4 4 4 4 -
DATA 1-bit 2-bit 4-bit 2-bit 4-bit 1-bit 2-bit 4-bit 2-bit 4-bit 1-bit 2-bit 4-bit 2-bit 4-bit 1-bit 2-bit 4-bit 2-bit 4-bit -
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ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
End_SEG_TRANS En_QPI
24.5-1. GP-SPI2 SPI CMD
CMD[7:0] 0x05 0x06
CMD 1-bit 1-bit
ADDR -
DUMMY -
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DATA -
Wr_BUF Rd_BUF Wr_DMA Rd_DMA CMD7 CMD8 CMD9 CMDA End_SEG_TRANS Ex_QPI
24.5-2. GP-SPI2 QPI CMD
CMD[7:0] 0xA1 0xA2 0xA3 0xA4 0xA7 0xA8 0xA9 0xAA 0xA5 0xDD
CMD 4-bit 4-bit 4-bit 4-bit 4-bit 4-bit 4-bit 4-bit 4-bit 4-bit
ADDR 4-bit 4-bit 4-bit 4-bit -
DUMMY 4 4 4 4 -
DATA 4-bit 4-bit 4-bit 4-bit -
GP-SPI2 0x06 CMD (En_QPI) QPI bGP-SPI2 QPI 24.5-2 4-bit b 0xDD CMD (Ex_QPI) GP-SPI2 SPI b 24.5-2 b 8 GP-SPI2 b 8 SPI_TRANS_DONE b 24.11b
24.5.3
GP-SPI2 CPU DMA b 1. 24.3 SPI_DOUTDIN SPI_SLAVE_MODE 2. · CPU SPI_W0_REG ~ SPI_W17_REG · DMA DMA DMA 24.8 3. SPI_DMA_CONF_REG SPI_DMA_SLV_SEG_TRANS_EN b 4. SPI_SLAVE_REG SPI_INT_TRANS_DONE_EN SPI_TRANS_DONE b DMA DMA RX buffer SPI_IN_SUC_EOF_INT b
24.5.4
GP-SPI2 b SPI_W0_REG ~ SPI_W17_REG CPU GP-SPI2 CPU DMA b
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ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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GP-SPI2 24.5-1 24.5-2 CPU DMA b
· CPU 24.11b · DMA 24.11b GP-SPI2 End_SEG_TRANScSPI 0x05QPI 0xA5 SPI_DMA_SEG_TRANS_DONE b 1. SPI_SLAVE_REG SPI_SLAVE_MODE 2.
· CPU SPI_W0_REG ~ SPI_W17_REG · DMA DMA DMAb SPI_DMA_CONF_REG
SPI_RX_EOF_EN 3. SPI_DMA_CONF_REG SPI_DMA_SLV_SEG_TRANS_EN 4. SPI_SLAVE_REG SPI_INT_DMA_SEG_TRANS_EN
SPI_DMA_SEG_TRANS_DONE b 24.11 b
DMA DMA buffer CPU b SPI_IN_SUC_EOF_INT_ST b
1. SPI_USER_REG SPI_DOUTDIN SPI_SLAVE_REG SPI_SLAVE_MODE 2. DMA DMA 3. SPI_DMA_CONF_REG SPI_RX_EOF_EN b SPI_SLV_RDBUF_DLEN_REG
SPI_SLV_DMA_RD_BYTELEN[19:0] DMA 4. SPI_DMA_CONF_REG SPI_DMA_SLV_SEG_TRANS_EN 5. SPI_DMA_INT_ENA_REG SPI_IN_SUC_EOF_INT_ENA
SPI_IN_SUC_EOF_INT_ST b
24.6 GP-SPI2 GP-SPI3
GP-SPI2 GP-SPI3 · GP-SPI2 CMDaADDRaDOUT DINb 1-bita2-bita4-bit 8-bit 1-bita2-bit 4-bit b GP-SPI3 1-bit b · GP-SPI2 CMD 24.5-1 24.5-2bGP-SPI3 CMD 0x01a 0x02a0x03a0x04a0x05a0x07a0x08a0x09 0x0Ab · GP-SPI2 I/O GPIO IO MUX b GP-SPI3 GPIO b
· GP-SPI2 CS bGP-SPI3 CS b
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ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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GP-SPI2 GP-SPI3 bGP-SPI2 GP-SPI GP-SPI3 GP-SPI 24.6-1b
24.6-1. GP-SPI3
SPI_USER_REG
SPI_CTRL_REG
SPI_MISC_REG SPI_SLAVE1_REG SPI_DMA_INT_ENA_REG SPI_DMA_INT_RAW_REG SPI_DMA_INT_ST_REG SPI_DMA_INT_CLR_REG SPI_DIN_MODE_REG
SPI_DIN_NUM_REG
SPI_QPI_MODE SPI_OPI_MODE SPI_FWRITE_DUAL SPI_FWRITE_QUAD SPI_FWRITE_OCT SPI_FADDR_DUAL SPI_FADDR_QUAD SPI_FADDR_OCT SPI_FCMD_DUAL SPI_FCMD_QUAD SPI_FCMD_OCT SPI_FREAD_DUAL SPI_FREAD_QUAD SPI_FREAD_OCT SPI_CS3_DIS SPI_CS4_DIS SPI_CS5_DIS SPI_MASTER_CS_POL[5:3] SPI_QUAD_DIN_PIN_SWAP SPI_SLV_NO_QPI_EN SPI_SLV_CMD6_INT_ENA SPI_SLV_CMD6_INT_RAW SPI_SLV_CMD6_INT_ST SPI_SLV_CMD6_INT_CLR SPI_DIN2_MODE SPI_DIN3_MODE SPI_DIN4_MODE SPI_DIN5_MODE SPI_DIN6_MODE SPI_DIN7_MODE SPI_DIN2_NUM SPI_DIN3_NUM SPI_DIN4_NUM SPI_DIN5_NUM SPI_DIN6_NUM SPI_DIN7_NUM
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ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
24.6-1. GP-SPI3
SPI_DOUT_MODE_REG
SPI_DOUT_NUM_REG
SPI_DOUT2_MODE SPI_DOUT3_MODE SPI_DOUT4_MODE SPI_DOUT5_MODE SPI_DOUT6_MODE SPI_DOUT7_MODE SPI_DOUT2_NUM SPI_DOUT3_NUM SPI_DOUT4_NUM SPI_DOUT5_NUM SPI_DOUT6_NUM SPI_DOUT7_NUM
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GP-SPI3 1-bit GP-SPI2 bGP-SPI3 1-bit GP-SPI2 bGP-SPI3 24.4 24.5b
24.7 CPU
GP-SPI CPU GP-SPI buffer GP-SPI bufferbCPU a 24.4 24.5 b 24.7-1 buffer 18 x 32 bit SPI_W0_REG ~ SPI_W17_REGb b
24.7-1. CPU Buffer
24.7.1 CPU
CPU // SPI_W0_REG[7:0] ~ SPI_W17_REG[31:24] SPI_W8_REG[7:0] ~ SPI_W17_REG[7:0]cb SPI_USER_REG SPI_USR_MOSI_HIGHPART SPI_USR_MISO_HIGHPART /b
· SPI_USR_MOSI_HIGHPART = 0 SPI_W0_REG[7:0] ~ SPI_W17_REG[31:24] 1b 72 72 bSPI_W0_REG ~ SPI_W17_REG b
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ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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· SPI_USR_MOSI_HIGHPART = 1 SPI_W8_REG[7:0] ~ SPI_W17_REG[31:24] 1b 40SPI_W8_REG[7:0] ~ SPI_W17_REG[31:24] b
· SPI_USR_MISO_HIGHPART = 0 SPI_W0_REG[7:0] ~ SPI_W17_REG[31:24] 1b 72 72 bSPI_W0_REG ~ SPI_W17_REG b
· SPI_USR_MISO_HIGHPART = 1 SPI_W8_REG[7:0] ~ SPI_W17_REG[31:24] 1b 40 SPI_W0_REG ~ SPI_W17_REG b
SPI_DMA_IN_LINK_REG SPI_DMA_RX_ENA SPI_DMA_OUT_LINK_REG SPI_DMA_TX_ENA bSPI_DMA_RX_ENA 1 DMA CPU bSPI_DMA_TX_ENA 1 DMA CPU b
24.7.2 CPU
CPU SPI_W0_REG ~ SPI_W17_REG 0 1b 71 SPI_W17_REG[31:24] b
CPU SPI_W0_REG ~ SPI_W17_REG b ADDR SPI_W0_REG ~ SPI_W17_REGb SPI_W0_REG ~ SPI_W17_REGb SPI_W17_REG[31:24] 71 71 SPI_W17_REG[31:24] b SPI_SLAVE1_REG SPI_SLV_ADDR_ERR 1b
SPI_W0_REG ~ SPI_W17_REG buffer buffer buffer bufferb CPU SPI_DMA_RX_ENA SPI_DMA_TX_ENA 1b
24.8 DMA
GP-SPI DMA DMA RX DMA TX bDMA DMA CPU b DMA a 24.4 24.5 b DMA RX DMA TX
· DMA DMA b · DMA CPU b · CPU DMA b · CPU CPU b GP-SPI Wr_BUFaRd_BUFaWr_DMA Rd_DMA 24.5.4b DMA
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ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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· DMA TX SPI_DMA_OUT_LINK_REG SPI_OUTLINK_START DMA TX b DMA TX buffer DMA TX SPI_OUTLINK_RESTART TX buffer TX buffer b
· DMA RX buffer DMA TX buffer SPI_INLINK_START SPI_INLINK_RESTART b
· DMA TX buffer DMA RX buffer 0 ~ 2 MBb
· DMA DMA b SPI_DMA_IN_LINK_REG SPI_DMA_RX_ENA SPI_DMA_OUT_LINK_REG SPI_DMA_TX_ENA b
DMA DMA RX
· SPI_RX_EOF_EN b
DMA SPI_IN_SUC_EOF_INT b
SPI_DMA_SLV_SEG_TRANS_EN 0 SPI_IN_SUC_EOF_INT b SPI_DMA_SLV_SEG_TRANS_EN 1 CMD7 End_SEG_TRANS SPI_IN_SUC_EOF_INT b
· SPI_RX_EOF_EN b
GP-SPI DMA DMA SPI_MST_DMA_RD_BYTELEN SPI_IN_SUC_EOF_INT b
DMA SPI_SLV_DMA_RD_BYTELEN b SPI_DMA_SLV_SEG_TRANS_EN 0 SPI_IN_SUC_EOF_INT b SPI_DMA_SLV_SEG_TRANS_EN 1 CMD7 End_SEG_TRANS SPI_IN_SUC_EOF_INT b
DMA TX buffer b SPI_DMA_INT_RAW_REG SPI_OUTFIFO_EMPTY_ERR_INT_RAW SPI_OUT_EOF_INT_RAW b
DMA TX buffer TX buffer TX buffer TX buffer b DMAb
DMA RX buffer b SPI_DMA_INT_RAW_REG SPI_INFIFO_FULL_ERR_INT_RAW SPI_SLAVE_REG SPI_TRANS_DONE b SPI_IN_SUC_EOF_INT_RAW b
DMA RX buffer RX buffer RX buffer buffer b DMAb
24.9 GP-SPI
GP-SPI fapbb
fspi
=
fapb (SPI_CLKCNT_N+1)(SPI_CLKDIV_PRE+1)
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ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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SPI_CLOCK_REG SPI_CLKCNT_N SPI_CLKDIV_PRE b SPI_CLOCK_REG SPI_CLK_EQU_SYSCLK 1 GP-SPI fapbb SPI_CLK_EQU_SYSCLK 0b GP-SPI fapb/2b
24.9.1 GP-SPI
SPI 0 ~ 3 24.9-1 24.9-2b
24.9-1. SPI 0 2
24.9-1 24.9-2 SPI 1. 0CPOL = 0CPHA = 0SPI SCK 0 SCK b 2. 1CPOL = 0CPHA = 1SPI SCK 0 SCK b 3. 2CPOL = 1CPHA = 0SPI SCK 1 SCK b 4. 3CPOL = 1CPHA = 1SPI SCK 1 SCK b
24.9.2 GP-SPI
GP-SPI SPI 0 ~ 3bGP-SPI SPI_MISC_REG SPI_CK_IDLE_EDGE SPI_USER_REG SPI_CK_OUT_EDGE bSPI 0 ~ 3 24.9-1b
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ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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24.9-2. SPI 1 3
24.9-1. GP-SPI
SPI_CK_IDLE_EDGE SPI_CK_OUT_EDGE
0 0 0
1 0 1
2 1 1
3 1 0
SPI_CTRL1_REG SPI_CLK_MODE[1:0] CS FSPICLK 0a1a2 FSPICLK b
24.9.3 GP-SPI
GP-SPI SPI 0 ~ 3b SPI_USER_REG SPI_TSCK_I_EDGE SPI_RSCK_I_EDGE b SPI_CTRL1_REG SPI_CLK_MODE_13 b 24.9-2b
24.9-2. GP-SPI
SPI_TSCK_I_EDGE SPI_RSCK_I_EDGE SPI_CLK_MODE_13
0 0 0 0
1 1 1 1
2 1 1 0
3 0 0 1
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ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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24.9.4 GP-SPI
SPI GPIO IO MUX IO MUX b GPIO 0a1a 2 APB_CLK b 5 IO MUX GPIO b
GP-SPI APB_CLK b SPI_DIN_MODE_REG SPI_DIN_NUM_REG b SPI_DOUT_MODE_REG SPI_DOUT_NUM_REG 24.14b DUMMY I/O GP-SPI b
GP-SPI SPI_CTRL1_REG SPI_RSCK_DATA_OUT 1 SPI bb
24.10 SPI
GP-SPI2 GPIO I/O 24.4-2a 24.4-3 24.4-5bSPI0/1 GP-SPI3 I/O GP-SPI2 b
SPI/FSPI/SPI3 GPIO 24.10-1bb GP-SPI2 FSPID MOSIFSPIQ MISO 24.4-2b GP-SPI3 SPI3_Q MISO b
24.10-1. SPI
SPI
SPI SPI
MOSI
MOSI
MISO
(MISO)
CS
CS
CLK
CLK
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
D Q CS CLK WP HD CD DQS IO4 ~ 7 VSYNC HSYNC DE
SPI SPID SPIQ SPICS0 ~ 1 SPICLK SPIWP SPIHD SPIDQS SPIIO4 ~ 7 -
SPI FSPI FSPID FSPIQ FSPICS0 ~ 5 FSPICLK FSPIWP FSPIHD FSPICD FSPIDQS FSPIIO4 ~ 7 FSPI_VSYNC FSPI_HSYNC FSPI_DE
SPI3 SPI3_D SPI3_Q SPI3_CS0 ~ 2 SPI3_CLK SPI3_HD SPI3_CD SPI3_DQS -
24.11 GP-SPI
GP-SPI2 SPI (SPI_INT) SPI DMA (SPI_DMA_INTR)bSPI b
GP-SPI 24.11-1 24.11-2b SPI_SLAVE_REG SPI_INT_*_EN SPI_DMA_INT_ENA_REG SPI_*_INT_ENA SPI_INT SPI_DMA_INTR b
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ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
GoBack
bb
24.11-1. GP-SPI
DMA CPU DMA CPU DMA CPU DMA CPU DMA CPU DMA CPU
SPI_IN_SUC_EOF_INT 1 SPI_TRANS_DONE 2 SPI_TRANS_DONE SPI_TRANS_DONE SPI_IN_SUC_EOF_INT SPI_TRANS_DONE SPI_DMA_SEG_TRANS_DONE 3 SPI_DMA_SEG_TRANS_DONE SPI_DMA_SEG_TRANS_DONE
1. SPI_IN_SUC_EOF_INT RX bufferb 2. CS SPI_TRANS_DONE W0 ~ W17 b 3. SPI_DMA_SEG_TRANS_DONE RX buffer
b
24.11-2. GP-SPI
DMA CPU DMA (Wr_DMA) CPU (Wr_BUF) DMA (Rd_DMA) CPU (Rd_BUF) DMA CPU DMA (Wr_DMA) CPU (Wr_BUF) DMA (Rd_DMA) CPU (Rd_BUF)
SPI_IN_SUC_EOF_INT 1 SPI_TRANS_DONE 2 SPI_IN_SUC_EOF_INT3 SPI_TRANS_DONE4 SPI_TRANS_DONE5 SPI_TRANS_DONE6 SPI_IN_SUC_EOF_INT7 8 SPI_DMA_SEG_TRANS_DONE9 10 SPI_DMA_SEG_TRANS_DONE11 12
1. SPI_IN_SUC_EOF_INT RX bufferb 2. CS SPI_TRANS_DONE W0 ~ W17 b
574
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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3. SPI_SLV_WR_DMA_DONE SPI RX bufferb SPI_IN_SUC_EOF_INT b
4. SPI_SLV_WR_BUF_DONE b 5. SPI_SLV_RD_DMA_DONE b 6. SPI_SLV_RD_BUF_DONE b 7. SPI_SLV_DMA_RD_BYTELEN[19:0]
SPI_RX_EOF_EN 01b 8. GPIO b 9. COM5 SPI_SLV_DMA_RD_BYTELEN[19:0]
SPI_IN_SUC_EOF_INT b 10. Wr_BUF DMA b 11. COM5 b 12. Rd_BUF DMA b
24.11.1 GP-SPI
SPI_INT · SPI_TRANS_DONESPI b · SPI_SLV_WR_DMA_DONEWr_DMA b · SPI_SLV_RD_DMA_DONERd_DMA b · SPI_SLV_WR_BUF_DONEWr_BUF b · SPI_SLV_RD_BUF_DONERd_BUF b · SPI_DMA_SEG_TRANS_DONEGP-SPI End_SEG_TRANS b b · SPI_SEG_MAGIC_ERR_INT DMA CONF buffer Magic b
24.11.2 GP-SPI DMA
SPI_DMA_INTR · SPI_SLV_CMDA_INTGP-SPI CMDA SPI b · SPI_SLV_CMD9_INTGP-SPI CMD9 SPI b · SPI_SLV_CMD8_INTGP-SPI CMD8 SPI b · SPI_SLV_CMD7_INTGP-SPI CMD7 SPI b · SPI_SLV_CMD6_INTGP-SPI En_QPI Ex_QPI SPI b · SPI_OUTFIFO_EMPTY_ERR_INTDMA TX FIFO b · SPI_INFIFO_FULL_ERR_INTDMA RX FIFO b · SPI_OUT_TOTAL_EOF_INT buffer b · SPI_OUT_EOF_INT buffer b
575
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
· SPI_OUT_DONE_INT 0 b · SPI_IN_SUC_EOF_INT buffer b · SPI_IN_ERR_EOF_INTb · SPI_IN_DONE_INT 0 b · SPI_INLINK_DSCR_ERROR_INTb · SPI_OUTLINK_DSCR_ERROR_INTb · SPI_INLINK_DSCR_EMPTY_INTb
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24.12
SPI0aSPI1aGP-SPI2 GP-SPI3 b 3 b
24.12-1. SPI0aSPI1aGP-SPI2 GP-SPI3
SPI SPI0 SPI1 GP-SPI2 GP-SPI3
PeriBUS1 PeriBUS2 PeriBUS1 PeriBUS2 PeriBUS1 PeriBUS2 PeriBUS1 PeriBUS2
0x3F403000 0x60003000 0x3F402000 0x60002000 0x3F424000 0x60024000 0x3F425000 0x60025000
24.13
SPI cb SPI 24.12
SPI_CMD_REG SPI_ADDR_REG SPI_USER_REG SPI_USER1_REG SPI_USER2_REG SPI_MOSI_DLEN_REG SPI_MISO_DLEN_REG SPI_CTRL_REG SPI_CTRL1_REG
SPI USER SPI USER 1 SPI USER 2 MOSI MISO
SPI SPI 1
0x0000 0x0004 0x0018 0x001C 0x0020 0x0024 0x0028
/ / / / / / /
0x0008 / 0x000C /
576
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
SPI_CTRL2_REG SPI_CLOCK_REG SPI_MISC_REG SPI_FSM_REG SPI_HOLD_REG SPI_SLAVE_REG SPI_SLAVE1_REG SPI_SLV_WRBUF_DLEN_REG SPI_SLV_RDBUF_DLEN_REG SPI_SLV_RD_BYTE_REG DMA SPI_DMA_CONF_REG SPI_DMA_OUT_LINK_REG SPI_IN_ERR_EOF_DES_ADDR_REG SPI_IN_SUC_EOF_DES_ADDR_REG SPI_INLINK_DSCR_REG SPI_INLINK_DSCR_BF0_REG SPI_OUT_EOF_BFR_DES_ADDR_REG SPI_OUT_EOF_DES_ADDR_REG SPI_OUTLINK_DSCR_REG SPI_OUTLINK_DSCR_BF0_REG SPI_DMA_OUTSTATUS_REG SPI_DMA_INSTATUS_REG DMA SPI_DMA_IN_LINK_REG SPI_DMA_INT_ENA_REG SPI_DMA_INT_RAW_REG SPI_DMA_INT_ST_REG SPI_DMA_INT_CLR_REG CPU buffer SPI_W0_REG SPI_W1_REG SPI_W2_REG SPI_W3_REG SPI_W4_REG SPI_W5_REG SPI_W6_REG SPI_W7_REG SPI_W8_REG SPI_W9_REG SPI_W10_REG SPI_W11_REG
SPI 2 SPI SPI MISC SPI DMA SPI Hold
SPI SPI 1 SPI Wr_BUF CONF SPI Magic SPI
SPI DMA SPI DMA TX Link SPI DMA RX SPI DMA EOF RX SPI DMA RX SPI DMA RX SPI DMA EOF TX buffer SPI DMA EOF TX SPI DMA TX SPI DMA TX SPI DMA TX SPI DMA RX
SPI DMA RX Link SPI DMA SPI DMA SPI DMA SPI DMA
buffer 0 buffer 1 buffer 2 buffer 3 buffer 4 buffer 5 buffer 6 buffer 7 buffer 8 buffer 9 buffer 10 buffer 11
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0x0010 0x0014 0x002C 0x0044 0x0048
/ / / /
0x0030 0x0034 0x0038 0x003C 0x0040
/ / /
0x004C 0x0050 0x0068 0x006C 0x0070 0x0074 0x007C 0x0080 0x0084 0x0088 0x0090 0x0094
/ /
0x0054 0x0058 0x005C 0x0060 0x0064
/ / /
0x0098 0x009C 0x00A0 0x00A4 0x00A8 0x00AC 0x00B0 0x00B4 0x00B8 0x00BC 0x00C0 0x00C4
/ / / / / / / / / / / /
577
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
SPI_W12_REG SPI_W13_REG SPI_W14_REG SPI_W15_REG SPI_W16_REG SPI_W17_REG SPI_DIN_MODE_REG SPI_DIN_NUM_REG SPI_DOUT_MODE_REG SPI_DOUT_NUM_REG LCD SPI_LCD_CTRL_REG SPI_LCD_CTRL1_REG SPI_LCD_CTRL2_REG SPI_LCD_D_MODE_REG SPI_LCD_D_NUM_REG SPI_DATE_REG
buffer 12 buffer 13 buffer 14 buffer 15 buffer 16 buffer 17
SPI SPI SPI SPI
LCD LCD 1 LCD 2 LCD LCD
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0x00C8 0x00CC 0x00D0 0x00D4 0x00D8 0x00DC
/ / / / / /
0x00E0 0x00E4 0x00E8 0x00EC
/ / / /
0x00F0 0x00F4 0x00F8 0x00FC 0x0100
/ / / / /
0x03FC /
24.14
Register 24.1. SPI_CMD_REG (0x0000)
(reserved)
SPI_U(SreRserved)
31
25 24 23 22
0 0 0 0 0 0 00 0
SPI_CONF_BITLEN 0
0
Reset
SPI_CONF_BITLEN SPI CONF SPI CLK b CONF bc/
SPI_USR b SPI bb1 0bCONF_buf bc/
578
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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Register 24.2. SPI_ADDR_REG (0x0004)
SPI_USR_ADDR_VALUE
31
0
0x000000
Reset
SPI_USR_ADDR_VALUE [31:8] [7:0] b CONF bc/
579
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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Register 24.3. SPI_USER_REG (0x0018)
SPI_USSPRI__CUSOSPRMI__MUASADSPNRDID__RUDSSUPRMI__MUMSYSIPSRIO__UMSSOPRSI__IUDSSUPRMI__MUMYSO_RSI_DI_MLHEISIGOH_PHAIGR(rTHePsAerRvTed)
SPI_USSPRI__SHSIOOPLI_DU_SSPPROI__LCFSWOPNRI_FITF_SEWN_PXROI_TICTFTSEW_PRQI_IUTWSEAR_DP_DI_BURYSADTPLE_I__BOCYSTKRPE_DI_O_EORURSRSTPDC_IE_KERCD_SSIG_P_EEIS_DECGSTSEPU_IPH_TOSSLPCDIK__OSIP_PIE_I_DMQGOPEDI_(ErMesOeDrvEedS)PI_DOUTDIN
31 30 29 28 27 26 25 24 23
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2
10
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 Reset
SPI_DOUTDIN b10b CONF bc/
SPI_QPI_MODE QPI b1SPI QPI 0SPI b CONF bc/
SPI_OPI_MODE OPI b1SPI OPI c 8 b 0SPI b CONF bc/
SPI_TSCK_I_EDGE TSCK b0TSCK = SPI_CK_Ib1TSCK = ! SPI_CK_Ibc/
SPI_CS_HOLD SPI SPI CS b10b CONF bc/
SPI_CS_SETUP SPI SPI CSb10b CONF bc/
SPI_RSCK_I_EDGE RSCK b0RSCK = !SPI_CK_Ib1RSCK = SPI_CK_Ibc/
SPI_CK_OUT_EDGE SPI_DOUT_MODE_REG MOSI b CONF bc/
SPI_RD_BYTE_ORDER (MISO) b1 0b CONF bc/
SPI_WR_BYTE_ORDER a (MOSI) b10b CONF bc/
SPI_FWRITE_DUAL 2 b CONF bc/
SPI_FWRITE_QUAD 4 b CONF bc/
SPI_FWRITE_OCT 8 b CONF bc/
SPI_USR_CONF_NXT 1 DMA CONF b0 b CONF bc/
SPI_SIO bMOSI MISO b10 b CONF bc/
580
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
Register 24.3. SPI_USER_REG (0x0018)
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SPI_USR_HOLD_POL SPI b1SPI 0SPI b CONF bc/
SPI_USR_MISO_HIGHPART bufferSPI_BUF8 ~ SPI_BUF17b1 0b CONF bc/
SPI_USR_MOSI_HIGHPART bufferSPI_BUF8 ~ SPI_BUF17b1 0b CONF bc/
SPI_USR_DUMMY_IDLE DUMMY SPI b CONF bc/
SPI_USR_MOSI SPI b CONF bc/ SPI_USR_MISO SPI b CONF bc/ SPI_USR_DUMMY SPI DUMMY b CONF bc/ SPI_USR_ADDR SPI b CONF bc/ SPI_USR_COMMAND SPI b CONF bc/
Register 24.4. SPI_USER1_REG (0x001C)
SPI_USR_ADDR_BITLEN
31
27 26
(reserved)
87
23
0000000000000000000
SPI_USR_DUMMY_CYCLELEN
0
7
Reset
SPI_USR_DUMMY_CYCLELEN DUMMY spi_clk b cycle_numc- 1b CONF bc/
SPI_USR_ADDR_BITLEN b bit_numc- 1b CONF bc/
581
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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Register 24.5. SPI_USER2_REG (0x0020)
SPI_USR_COMMAND_BITLEN
31
28 27
(reserved)
16 15
7
000000000000
SPI_USR_COMMAND_VALUE 0
0
Reset
SPI_USR_COMMAND_VALUE b CONF bc/
SPI_USR_COMMAND_BITLEN b bit_numc- 1b CONF bc/
Register 24.6. SPI_MOSI_DLEN_REG (0x0024)
(reserved)
31
23 22
000000000
SPI_USR_MOSI_DBITLEN 0x0000
0
Reset
SPI_USR_MOSI_DBITLEN b bit_numc- 1b CONF bc/
Register 24.7. SPI_MISO_DLEN_REG (0x0028)
(reserved)
31
23 22
000000000
SPI_USR_MISO_DBITLEN 0x0000
0
Reset
SPI_USR_MISO_DBITLEN b bit_numc- 1b CONF bc/
582
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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Register 24.8. SPI_CTRL_REG (0x0008)
(reserved)
SPI_WSRP_I_BRITD__OBRIT(Dr_eEOsReRrDvEeRd) SPI_W(Pre_sReErSvGPeId_)DS_PPI_OQL(_rePsOeLrSvPeId_)FSRPEIA_DFS_RPOEIAC_DTF_RQEAUDA(_DreDsUeArvLed) SPI_FSCPMI_DF_SCOPMCI_DTF_SCQPMUI_DAF_DSADPDUID_ARFLSA_PDOIDC_RTF(A_reDQsDUeRArSv_DPeDId_U)DALUMM(Yre_sOeUrvTed)
31
27 26 25 24
22 21 20 19 18 17 16 15 14 13
11 10 9 8 7 6 5 4 3 2
0
0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SPI_DUMMY_OUT DUMMY SPI SPI b CONF bc/
SPI_FADDR_DUAL 2 b1 2 0 2 b CONF bc/
SPI_FADDR_QUAD 4 b1 4 0 4 b CONF bc/
SPI_FADDR_OCT 8 b1 8 0 8 b CONF bc/
SPI_FCMD_DUAL 2 b1 2 0 2 b CONF bc/
SPI_FCMD_QUAD 4 b1 4 0 4 b CONF bc/
SPI_FCMD_OCT 8 b1 8 0 8 b CONF bc/
SPI_FREAD_DUAL 2 b1 2 0 2 b CONF bc/
SPI_FREAD_QUAD 4 b1 4 0 4 b CONF bc/
SPI_FREAD_OCT 8 b1 8 0 8 b CONF bc/
SPI_Q_POL MISO 10b CONF bc/
SPI_D_POL MOSI 10b CONF bc/
SPI_WP_REG SPI b10b CONF bc/
SPI_RD_BIT_ORDER (MISO) b1 (LSB)0 (MSB)b CONF bc/
SPI_WR_BIT_ORDER a (MOSI) b1 (LSB)0 (MSB)b CONF bc/
583
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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Register 24.9. SPI_CTRL1_REG (0x000C)
(reserved)
31
20 19
000000000000
SPI_CS_HOLD_DELAY
14 13
(reserved)
SPI_WS1P6I__1R7SS_PWCI_KRC__LDEKANS_TAPAM_I_OOCDULETK__13MODE
54 3 21
0
0x1
0 0 0 0 0 0 0 0 0 1 0 0 0x0 Reset
SPI_CLK_MODE SPI b0CS SPI 1CS SPI 2CS SPI 3SPI b CONF bc/
SPI_CLK_MODE_13 CPOL, CPHA 1 SPI CLK 1 3 B[0]/B[7]b1 SPI CLK 0 2 B[1]/B[6]bc/
SPI_RSCK_DATA_OUT TSCK RSCK b1 RSCK 0 TSCK bc/
SPI_W16_17_WR_ENA 1 SPI_BUF16 ~ SPI_BUF170 SPI_BUF16 ~ SPI_BUF17b CONF bc/
SPI_CS_HOLD_DELAY SPI CS SPI b CONF bc/
(reservedS)PI_CS_DELASYP_IN_UCMS_DELAY_MODE
31 30 29 28
26 25
0 0x0
0x0
Register 24.10. SPI_CTRL2_REG (0x0010)
SPI_CS_HOLD_TIME 0x01
13 12
SPI_CS_SETUP_TIME 0x00
0
Reset
SPI_CS_SETUP_TIME + 1 SPI b SPI_CS_SETUP b CONF bc/
SPI_CS_HOLD_TIME CS SPI b SPI_CS_HOLD b CONF bc/
SPI_CS_DELAY_MODE SPI CS SPI CLKb0 0 1 SPI_CK_OUT_EDGE SPI_CK_IDLE_EDGE2 SPI_CK_OUT_EDGE SPI_CK_IDLE_EDGE3 b CONF bc/
SPI_CS_DELAY_NUM SPI CS b CONF bc/
584
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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SPI_CLK_EQU_SYSCLK
31 30
1
Register 24.11. SPI_CLOCK_REG (0x0014)
SPI_CLKDIV_PRE 0
18 17
SPI_CLKCNT_N
12 11
0x3
SPI_CLKCNT_H
65
0x1
SPI_CLKCNT_L
0
0x3
Reset
SPI_CLKCNT_L SPI_CLKCNT_N b 0b CONF bc/
SPI_CLKCNT_H (SPI_CLKCNT_N + 1)/2-1 b 0b CONF bc/
SPI_CLKCNT_N SPI CLK b SPI CLK fapb/(SPI_CLKDIV_PRE + 1)/(SPI_CLKCNT_N + 1)b CONF bc/
SPI_CLKDIV_PRE SPI CLK b CONF bc/
SPI_CLK_EQU_SYSCLK 1SPI CLK APB CLK 0SPI CLK APB CLK b CONF bc/
585
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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Register 24.12. SPI_MISC_REG (0x002C)
SPI_QSUPAI_DC_SSDP_INIK__CEPEKIP_N(_I_rDeASLsCWEeT_rAIvVEPeEDdSG)PEI_CSDP_I_IDCLSDEP__I_CEDMDSQGDPSE_I__SSIEDSLTPLAEIV__ECE_SDDCP_GSI_AE_CDPSDDOP_RIL_D_CUSSDEMP_TIM_DCYAST_MPASDI_E__STADESDTTPDRI_R_D_ESADNPTTIA_R_C_DLETKNR__DE(ArNTeAs_erDvTeRd_) EN
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15
13 12
0 0 00 00 0 0 0 0 0 0 0 0 0 00 0 0
SPI_MASTER_CS_PSOPLI_CSKP_ID_CISSSP5I__CDSSISP4I__DCSISSP3I__CDSSISP2I__CDSSISP1_I_DCISS0_DIS
76 5 4 3 2 1 0
0
0 1 1 1 1 1 0 Reset
SPI_CS0_DIS SPI CS0 1 CS00SPI CS0 / CS0 b CONF bc/
SPI_CS1_DIS SPI CS1 1 CS10SPI CS1 / CS1 b CONF bc/
SPI_CS2_DIS SPI CS2 1 CS20SPI CS2 / CS2 b CONF bc/
SPI_CS3_DIS SPI CS3 1 CS30SPI CS3 / CS3 b CONF bc/
SPI_CS4_DIS SPI CS4 1 CS40SPI CS4 / CS4 b CONF bc/
SPI_CS5_DIS SPI CS5 1 CS50SPI CS5 / CS5 b CONF bc/
SPI_CK_DIS 1 SPI CLK 0 SPI CLK b CONF bc/
SPI_MASTER_CS_POL SPI CS SPI_CS^ SPI_MASTER_CS_POLb CONF bc/
SPI_CLK_DATA_DTR_EN 1SPI CLKaSPI SPI DQS SPI DTR b0 SPI DQS SPI DTR b SPI_DATA_DTR_ENaSPI_ADDR_DTR_ENaSPI_CMD_DTR_EN bc/
SPI_DATA_DTR_EN 1SPI CLK SPI DOUT SPI DIN DTR 1/2/4/8 b0SPI CLK SPI DOUT SPI DIN STR b CONF bc/
SPI_ADDR_DTR_EN 1SPI CLK SPI_SEND_ADDR DTR 1/2/4/8 b0SPI CLK SPI_SEND_ADDR STR b CONF cb/
SPI_CMD_DTR_EN 1SPI CLK SPI_SEND_CMD DTR 1/2/4/8 b0SPI CLK SPI_SEND_CMD STR b CONF bc/
SPI_CD_DATA_SET 1SPI_ST[3:0] SPI_DOUT SPI_DIN SPI_CD = ! SPI_CD_IDLE_EDGEb0SPI_CD = SPI_CD_IDLE_EDGEb CONF bc/
586
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
Register 24.12. SPI_MISC_REG (0x002C)
GoBack
SPI_CD_DUMMY_SET 1: SPI_ST[3:0] SPI_DUMMY SPI_CD = !SPI_CD_IDLE_EDGEb 0SPI_CD = SPI_CD_IDLE_EDGEb CONF bc/
SPI_CD_ADDR_SET 1: SPI_ST[3:0] SPI_SEND_ADDR SPI_CD = !SPI_CD_IDLE_EDGEb 0SPI_CD = SPI_CD_IDLE_EDGEb CONF bc/
SPI_SLAVE_CS_POL SPI CS b10b CONF cb/
SPI_DQS_IDLE_EDGE SPI_DQSb CONF bc/
SPI_CD_CMD_SET 1: SPI_ST[3:0] SPI_SEND_CMD SPI_CD = !SPI_CD_IDLE_EDGEb 0SPI_CD = SPI_CD_IDLE_EDGEb CONF bc/
SPI_CD_IDLE_EDGE SPI_CDb CONF bc/
SPI_CK_IDLE_EDGE 1SPI CLK 0SPI CLK b CONF bc/
SPI_CS_KEEP_ACTIVE SPI CS b CONF bc/
SPI_QUAD_DIN_PIN_SWAP 1 SPI Quad 0 SPI Quad b CONF bc/
Register 24.13. SPI_FSM_REG (0x0044)
SPI_MST_DMA_RD_BYTELEN
(reserved)
SPI_ST
31
12 11
43
0
0x000
00000000
0
Reset
SPI_ST SPI b01234 567bc
SPI_MST_DMA_RD_BYTELEN DMA bSPI_RX_EOF_EN 0 b CONF bc/
587
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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Register 24.14. SPI_HOLD_REG (0x0048)
(reserved)
SPI_DMA_SSEPGI__HTROALNDS_SO_PDUI_OTH_NSTOEPILMI_DEH_OOUL(DrTe__sVEeANrLv_eRdE) G
31
876
43 21
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00
0
0 0 0 0 Reset
SPI_HOLD_VAL_REG SPI SPI_HOLD_OUT_EN b CONF bc/
SPI_HOLD_OUT_EN SPI SPI_HOLD_ENb SPI_EXT_HOLD_EN USR b CONF bc/
SPI_HOLD_OUT_TIME SPI_HOLD_OUT_EN SPI b CONF bc/
SPI_DMA_SEG_TRANS_DONE 1SPI DMA / bb0/b CONF_buf bc/
588
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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Register 24.15. SPI_SLAVE_REG (0x0030)
SPI_SSOPFIT__SSRLPAEIVS_ETE_RTMA(NOreSDs_EeDrOveNdE)_AUTOS_PCIL_TRR_AENNS_CNT
31 30 29 28 27 26
23 22
(reserved)
SPI_SSEPGI__MINSATPG_I_IDCINMS_TPEA_IR__TRSIRNS_EATPIGNN_I__TSWTI__NRSREDATP_NO_NID_NRSMINDE_SA_T_EP_E_NDI_DWNMIONSRANTP__E_IBD__RUTOEDRFNN_A_EBND_USOEF_NN_DED(O_rOeENsNNEeEr_veEdN)
12 11 10 9 8 7 6 5 4 3
0
0 0 00 0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Reset
SPI_TRANS_DONE bbCONF_buf bc/
SPI_INT_RD_BUF_DONE_EN SPI_SLV_RD_BUF_DONE b10 b CONF bc/
SPI_INT_WR_BUF_DONE_EN SPI_SLV_WR_BUF_DONE b10 b CONF bc/
SPI_INT_RD_DMA_DONE_EN SPI_SLV_RD_DMA_DONE b10 b CONF bc/
SPI_INT_WR_DMA_DONE_EN SPI_SLV_WR_DMA_DONE b10 b CONF bc/
SPI_INT_TRANS_DONE_EN SPI_TRANS_DONE b10b CONF bc/
SPI_INT_DMA_SEG_TRANS_EN SPI_DMA_SEG_TRANS_DONE b10 b CONF bc/
SPI_SEG_MAGIC_ERR_INT_EN 1 Magic b0b CONF bc/
SPI_TRANS_CNT bc
SPI_TRANS_DONE_AUTO_CLR_EN SPI_TRANS_DONE SPI_TRANS_DONE 3 APB SPI_TRANS_DONEb0b1b CONF bc/
SPI_SLAVE_MODE SPI b10bc/
SPI_SOFT_RESET SPI aCS b CONF bc/
589
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
GoBack
Register 24.16. SPI_SLAVE1_REG (0x0034)
SPI_SLV_LAST_ADDR
SPI_SLV_LAST_COMMANSDPI_SSLVP_I_WSSRLVP__ID_CMSMSLAVPD__I__DASEODSRLNVPDRE_IR_N_SSOELVPR__IRQ_CPSMIL_VDE__NAEDRDRR__CELRRR_CLR
(reserved)
31
24 23
16 15 14 13 12 11 10 9
0
0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SPI_SLV_ADDR_ERR_CLR 1 SPI_SLV_ADDR_ERRb0 bCONF_buf bc/
SPI_SLV_CMD_ERR_CLR 1 SPI_SLV_CMD_ERRb0bCONF_buf cb/
SPI_SLV_NO_QPI_EN 1 QPI b0 QPI bc/
SPI_SLV_ADDR_ERR 1SPI SPI b0 SPI bc
SPI_SLV_CMD_ERR 1SPI SPI b0 bc
SPI_SLV_WR_DMA_DONE DMA b CONF_buf bc/
SPI_SLV_LAST_COMMAND bc/
SPI_SLV_LAST_ADDR bc/
Register 24.17. SPI_SLV_WRBUF_DLEN_REG (0x0038)
SPI_CONF_BASE_BITLSEPNI_SLV_WR_BUF_DONE
(reserved)
31
25 24 23
0
108
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SPI_SLV_WR_BUF_DONE DMA buffer b CONF_buf bc/
SPI_CONF_BASE_BITLEN CONF SPI CLKb SPI_USR_CONF CONF SPI_CONF_BASE_BITLEN[6:0] + SPI_CONF_BITLEN[23:0]bc/
590
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
GoBack
Register 24.18. SPI_SLV_RDBUF_DLEN_REG (0x003C)
(reserved)
SPI_SSEPGI__MSLAVG_IRCD__EB(RrUeRsFe_rDveOdN)E
31
26 25 24 23
20 19
0 0 0 0 0 00 00 0 0 0
SPI_SLV_DMA_RD_BYTELEN 0x000
0
Reset
SPI_SLV_DMA_RD_BYTELEN b byte_num 1bc/
SPI_SLV_RD_BUF_DONE DMA buffer b CONF_buf bc/
SPI_SEG_MAGIC_ERR 1 DMA CONF buffer Magic b0 bc/
591
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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Register 24.19. SPI_SLV_RD_BYTE_REG (0x0040)
SPI_USSPRI__CSLOVN_(FrReDse_rDveMdA)_DONESPI_DMA_SEGS_PMI_ASSGLVPIC_I__WSVSRALVPBL_IUU_REFSDS_LVPBB_IUY_WTFSE_RLLVBDE_YMNRTA_ED_LEDBENMYNAT_E_ELBNEYNT_ELEENN_EN
31 30 29 28 27
24 23 22 21 20 19
0 00 0
10
0000
SPI_SLV_DATA_BYTELEN 0
0
Reset
SPI_SLV_DATA_BYTELEN SPI b SPI_SLV_RDDMA_BYTELEN_ENaSPI_SLV_WRDMA_BYTELEN_ENa SPI_SLV_RDBUF_BYTELEN_ENaSPI_SLV_WRBUF_BYTELEN_EN bc/
SPI_SLV_RDDMA_BYTELEN_EN 1DMA (Rd_DMA)SPI_SLV_DATA_BYTELEN b0bc/
SPI_SLV_WRDMA_BYTELEN_EN 1DMA (Wr_DMA)SPI_SLV_DATA_BYTELEN b0bc/
SPI_SLV_RDBUF_BYTELEN_EN 1CPU (Rd_BUF)SPI_SLV_DATA_BYTELEN b0bc/
SPI_SLV_WRBUF_BYTELEN_EN 1CPU (Wr_BUF)SPI_SLV_DATA_BYTELEN b0bc/
SPI_DMA_SEG_MAGIC_VALUE DMA Magic bc/
SPI_SLV_RD_DMA_DONE Rd_DMA b CONF_buf bc/
SPI_USR_CONF 1 DMA CONF b0 bc/
592
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
GoBack
Register 24.20. SPI_DMA_CONF_REG (0x004C)
(reserved) SPI_DMAS_PSI_EEGX_TT_RMA(NEreMSs_e_CrBvLKeR_dSS)PIIZ_EDSMPAI__DOSMUPATI__FRIISNFXPO_FI_IE_FOESOSMFL_VP_PF_IE_TUTNSYLXSL_L_VP_CS_IC_LERRLGDXSR_M_PTSAIR_E_ASGSSNL_LVPSVT_I___RLCSDAASLENMSPRGSTAI______ETDCSCNRSMLEOAPRGANNI____STEDPTI_SNNMOXPE_UPANIS_E__TMCRSOLEXPPR_MI_S_OTTSUORPTPAI__NIDNSSA_DPTESIA_NC_OSRBUP_UTIBR_DUSOSTRUC_STRTE__N_EBE(OrUNeFRs_SeMTrv_OeEDdN)ESPI_ASHPBI_MA_SHRPBSI_MTO_SUFPTIIF__OIRN_S_RTR(SrSeTTserved)
31
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
65 4 3 21
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Reset
SPI_IN_RST inDMA FSM indata FIFO bc/
SPI_OUT_RST outDMA FSM outdata FIFO bc/
SPI_AHBM_FIFO_RST SPI DMA AHB FIFO bc/
SPI_AHBM_RST SPI DMA AHB bc/
SPI_OUT_EOF_MODE OUT_EOF b1DMA FIFO OUT_EOF 0AHB FIFO OUT_EOF bc/
SPI_OUTDSCR_BURST_EN burst bc/
SPI_INDSCR_BURST_EN burst bc/
SPI_OUT_DATA_BURST_EN SPI DMA burst bc/
SPI_MEM_TRANS_EN 1b DMA RX buffer DMA TX bufferb0 bc/
SPI_DMA_RX_STOP SPI DMA SPI DMA bc/
SPI_DMA_TX_STOP SPI DMA SPI DMA bc/
SPI_DMA_CONTINUE SPI DMA bc/
SPI_SLV_LAST_SEG_POP_CLR DMA TX bc/
SPI_DMA_SLV_SEG_TRANS_EN SPI DMA b1 0bc/
SPI_SLV_RX_SEG_TRANS_CLR_EN SPI DMA DMA RX buffer 10, DMA RX Buffer bc/
SPI_SLV_TX_SEG_TRANS_CLR_EN SPI DMA DMA TX buffer 10 , DMA TX FIFO bc/
593
ESP32-S2 TRM ( 1.3)
24 SPI (SPI) Register 24.20. SPI_DMA_CONF_REG (0x004C)
GoBack
SPI_RX_EOF_EN 1 SPI DMA DMA SPI_SLV_DMA_RD_BYTELEN[19:0] SPI_MST_DMA_RD_BYTELEN[19:0] SPI_IN_SUC_EOF_INT_RAWb0 SPI_IN_SUC_EOF_INT_RAW SPI_TRANS_DONE SPI_DMA_SEG_TRANS_DONE bc/
SPI_DMA_INFIFO_FULL_CLR SPI_SLV_RX_SEG_TRANS_CLR_EN SPI DMA DMA RX buffer [SPI_DMA_INFIFO_FULL_CLR] b c/
SPI_DMA_OUTFIFO_EMPTY_CLR SPI_SLV_TX_SEG_TRANS_CLR_EN SPI DMA DMA TX buffer [SPI_DMA_OUTFIFO_EMPTY_CLR] bc/
SPI_EXT_MEM_BK_SIZE bc/
SPI_DMA_SEG_TRANS_CLR 1 0x05 b DMA RX b0b APB CLK bc/
Register 24.21. SPI_DMA_OUT_LINK_REG (0x0050)
SPI_DSMPAI__OTSUXP_TI_ELONINSAUKPT_I_LROINEUSKTT_ALSIRTNTAKR_TSTOP
31 30 29 28 27
(reserved)
20 19
0 0 0 00 0 0 0 0 0 0 0
SPI_OUTLINK_ADDR 0x000
0
Reset
SPI_OUTLINK_ADDR outlink bc/ SPI_OUTLINK_STOP outlink bc/ SPI_OUTLINK_START outlink bc/ SPI_OUTLINK_RESTART outlink bc/ SPI_DMA_TX_ENA DMA CPU
bc/
594
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
GoBack
Register 24.22. SPI_IN_ERR_EOF_DES_ADDR_REG (0x0068)
SPI_DMA_IN_ERR_EOF_DES_ADDR
31
0
0
Reset
SPI_DMA_IN_ERR_EOF_DES_ADDR SPI DMA inlink bc
Register 24.23. SPI_IN_SUC_EOF_DES_ADDR_REG (0x006C)
SPI_DMA_IN_SUC_EOF_DES_ADDR
31
0
0
Reset
SPI_DMA_IN_SUC_EOF_DES_ADDR SPI DMA FROM_SUC_EOF inlink bc
Register 24.24. SPI_INLINK_DSCR_REG (0x0070)
SPI_DMA_INLINK_DSCR
31
0
SPI_DMA_INLINK_DSCR inlink bc
0
Reset
595
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
Register 24.25. SPI_INLINK_DSCR_BF0_REG (0x0074)
SPI_DMA_INLINK_DSCR_BF0
31
0
SPI_DMA_INLINK_DSCR_BF0 inlink bc
GoBack
0
Reset
Register 24.26. SPI_OUT_EOF_BFR_DES_ADDR_REG (0x007C)
SPI_DMA_OUT_EOF_BFR_DES_ADDR
31
0
0
Reset
SPI_DMA_OUT_EOF_BFR_DES_ADDR EOF buffer bc
Register 24.27. SPI_OUT_EOF_DES_ADDR_REG (0x0080)
SPI_DMA_OUT_EOF_DES_ADDR
31
0
0
Reset
SPI_DMA_OUT_EOF_DES_ADDR SPI DMA TO_EOF outlink bc
596
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
Register 24.28. SPI_OUTLINK_DSCR_REG (0x0084)
SPI_DMA_OUTLINK_DSCR
31
0
SPI_DMA_OUTLINK_DSCR outlink bc
GoBack
0
Reset
Register 24.29. SPI_OUTLINK_DSCR_BF0_REG (0x0088)
SPI_DMA_OUTLINK_DSCR_BF0
31
0
SPI_DMA_OUTLINK_DSCR_BF0 outlink bc
0
Reset
Register 24.30. SPI_DMA_OUTSTATUS_REG (0x0090)
SPI_DSMPAI__DOMUAT_FOIFUOT_FEIMFOP_TFYSUPLIL_DMA_OUTFIFO_CNT SPI_DMA_OUTS_PSI_TDATMEA_OUTDSCR_STATE
31 30 29
23 22
20 19 18 17
10
0
0
0
SPI_DMA_OUTDSCR_ADDR 0
SPI_DMA_OUTDSCR_ADDR SPI DMA out bc SPI_DMA_OUTDSCR_STATE SPI DMA out bc SPI_DMA_OUT_STATE SPI DMA out bc SPI_DMA_OUTFIFO_CNT SPI DMA outFIFO bc SPI_DMA_OUTFIFO_FULL SPI DMA outFIFO bc SPI_DMA_OUTFIFO_EMPTY SPI DMA outFIFO bc
0
Reset
597
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
Register 24.31. SPI_DMA_INSTATUS_REG (0x0094)
SPI_DSMPAI__DINMFAIF_OIN_FEIMFOP_TFYULSLPI_DMA_INFIFO_CNT
31 30 29
23 22
SPI_DMA_IN_SSPTAI_TDEMA_INDSCR_STATE
20 19 18 17
10
0
0
0
SPI_DMA_INDSCR_ADDR 0
SPI_DMA_INDSCR_ADDR SPI DMA in bc SPI_DMA_INDSCR_STATE SPI DMA in bc SPI_DMA_IN_STATE SPI DMA in bc SPI_DMA_INFIFO_CNT SPI DMA inFIFO bc SPI_DMA_INFIFO_FULL SPI DMA inFIFO bc SPI_DMA_INFIFO_EMPTY SPI DMA inFIFO bc
GoBack
0
Reset
Register 24.32. SPI_DMA_IN_LINK_REG (0x0054)
SPI_DSMPAI__INRSXLP_IIN_EKINNS_ALPRIINE_SKINT_ALSIRTNTAKR_TSTOP
31 30 29 28 27
(reserved)
SPI_INLINK_AUTO_RET
21 20 19
0 0 0 00 0 0 0 0 0 00
SPI_INLINK_ADDR 0x000
0
Reset
SPI_INLINK_ADDR inlink bc/ SPI_INLINK_AUTO_RET inlink link
bc/ SPI_INLINK_STOP inlink bc/ SPI_INLINK_START inlink bc/ SPI_INLINK_RESTART inlink bc/ SPI_DMA_RX_ENA DMA CPU
bc/
598
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
GoBack
Register 24.33. SPI_DMA_INT_ENA_REG (0x0058)
(reserved)
SPI_SSLVP_I_CSMSLVPD_IA_C_SMSILNVPDT_I_9_CS_EMSLINNVPDAT_I_8_C_SEMSLINNVPDTA_I7__C_OEMSIUNNPDTTAI_6F_II_EFNSINONFPA_ITIF_E_OOMES_UNPPFTAITU__YLTO_SLOU_EPTTREAI__RRLOE_R_SOUE_IPNFTOIIN_T__FT_IID_NNS_EOI_TPNNEN_SITNA_EUE_AI_NNCSEIA_P_NNEIEAT_RO_INRSFE___PNEDIIAN_OOITNFSN__LPEEIII_NNN_ITKOANS__UTPEDT_INS_LEACIINNNRAKL_I_NEDKRS_RCDORSR_C_ERINR_RTE_OMERPN_TAINYT__INETN_AENA
31
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SPI_INLINK_DSCR_EMPTY_INT_ENA Inlink b CONF bc/
SPI_OUTLINK_DSCR_ERROR_INT_ENA Outlink b CONF bc/
SPI_INLINK_DSCR_ERROR_INT_ENA Inlink b CONF bc/
SPI_IN_DONE_INT_ENA inlink b CONF bc/
SPI_IN_ERR_EOF_INT_ENA b CONF bc/
SPI_IN_SUC_EOF_INT_ENA b CONF bc/
SPI_OUT_DONE_INT_ENA outlink b CONF bc/
SPI_OUT_EOF_INT_ENA b CONF bc/
SPI_OUT_TOTAL_EOF_INT_ENA b CONF bc/
SPI_INFIFO_FULL_ERR_INT_ENA Infifo bc/
SPI_OUTFIFO_EMPTY_ERR_INT_ENA Outfifo bc/
SPI_SLV_CMD6_INT_ENA SPI CMD6 bc/
SPI_SLV_CMD7_INT_ENA SPI CMD7 bc/
SPI_SLV_CMD8_INT_ENA SPI CMD8 bc/
SPI_SLV_CMD9_INT_ENA SPI CMD9 bc/
SPI_SLV_CMDA_INT_ENA SPI CMDA bc/
599
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
GoBack
Register 24.34. SPI_DMA_INT_RAW_REG (0x005C)
(reserved)
SPI_SSLVP_I_CSMSLVPD_IA_C_SMSILNVPDT_I_9_CS_RMSLINAVPDWT_I_8_C_SRMSLINAVPDWT_I7__C_ORMSIUNAPDTWTI_6F_II_RFNSIAONFPW_ITIF_E_OOMRS_UAPPFTWITU__YLTO_SLOU_EPTTREAI__RRLOE_R_SOUE_IPNFTOIIN_T__FT_IID_NNS_ROI_TPNRAN_SITWA_EUR_WI_NACSRIW_P_NAEIEWT_RO_INRSFR___PAEDIIWN_OOITNFSN__LPERIII_NNA_ITKWONS__UTPRDT_IAS_LRWCIIANNRWKL_I_NEDKRS_RCDORSR_C_ERINR_RTE_OMRRPA_TWINYT__INRTA_WRAW
31
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SPI_INLINK_DSCR_EMPTY_INT_RAW Inlink b CONF bc
SPI_OUTLINK_DSCR_ERROR_INT_RAW Outlink b CONF bc
SPI_INLINK_DSCR_ERROR_INT_RAW Inlink b CONF bc
SPI_IN_DONE_INT_RAW inlink b CONF bc
SPI_IN_ERR_EOF_INT_RAW b CONF bc
SPI_IN_SUC_EOF_INT_RAW b CONF bc
SPI_OUT_DONE_INT_RAW outlink b CONF bc
SPI_OUT_EOF_INT_RAW b CONF bc
SPI_OUT_TOTAL_EOF_INT_RAW b CONF bc
SPI_INFIFO_FULL_ERR_INT_RAW DMA RX buffer b CONF bc
SPI_OUTFIFO_EMPTY_ERR_INT_RAW DMA TX buffer b CONF bc
SPI_SLV_CMD6_INT_RAW SPI CMD6 bc/
SPI_SLV_CMD7_INT_RAW SPI CMD7 bc/
SPI_SLV_CMD8_INT_RAW SPI CMD8 bc/
SPI_SLV_CMD9_INT_RAW SPI CMD9 bc/
SPI_SLV_CMDA_INT_RAW SPI CMDA bc/
600
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
GoBack
Register 24.35. SPI_DMA_INT_ST_REG (0x0060)
(reserved)
SPI_SSLVP_I_CSMSLVPD_IA_C_SMSILNVPDT_I_9_CS_SMSLITNVPDT_I_8_C_SSMSLITNVPDT_I7__C_OSMSIUNTPDTTI_6F_II_SFNSITONFP_ITIF_E_OOMSS_UTPPFTITU__YLTO_SLOU_EPTTREAI__RRLOE_R_SOUE_IPNFTOIIN_T__FT_IID_NNS_SOI_TPNTSN_SITT_ESU_I_TNCSSI_P_TNEIET_RO_INRSFS___PTEDIIN_OOITNFSN__LPESIII_NNT_ITKONS__UTPSDT_ITS_LSCIITNNRKL_I_NEDKRS_RCDORSR_C_ERINR_RTE_OMSRPT_TINYT__INSTT_ST
31
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SPI_INLINK_DSCR_EMPTY_INT_ST Inlink bc
SPI_OUTLINK_DSCR_ERROR_INT_ST Outlink bc SPI_INLINK_DSCR_ERROR_INT_ST Inlink bc SPI_IN_DONE_INT_ST inlink bc SPI_IN_ERR_EOF_INT_ST bc SPI_IN_SUC_EOF_INT_ST bc
SPI_OUT_DONE_INT_ST outlink bc
SPI_OUT_EOF_INT_ST bc SPI_OUT_TOTAL_EOF_INT_ST
bc SPI_INFIFO_FULL_ERR_INT_ST Infifo bc SPI_OUTFIFO_EMPTY_ERR_INT_ST Outfifo bc SPI_SLV_CMD6_INT_ST SPI CMD6 bc/ SPI_SLV_CMD7_INT_ST SPI CMD7 bc/ SPI_SLV_CMD8_INT_ST SPI CMD8 bc/ SPI_SLV_CMD9_INT_ST SPI CMD9 bc/ SPI_SLV_CMDA_INT_ST SPI CMDA bc/
601
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
GoBack
Register 24.36. SPI_DMA_INT_CLR_REG (0x0064)
(reserved)
SPI_SSLVP_I_CSMSLVPD_IA_C_SMSILNVPDT_I_9_CS_CMSLINLVPDRT_I_8_C_SCMSLINLVPDRT_I7__C_OCMSIUNLPDTRTI_6F_II_CFNSILONFPR_ITIF_E_OOMCS_ULPPFTRITU__YLTO_SLOU_EPTTREAI__RRLOE_R_SOUE_IPNFTOIIN_T__FT_IID_NNS_COI_TPNCLN_SITRL_ECUR_I_NLCSCIR_P_NLERIET_RO_INRSFC___PLEDIIRN_OOITNFSN__LPECIII_NNL_IRTKONS__UTPCDT_ILS_LCRCIILNNRRKL_I_NEDKRS_RCDORSR_C_ERINR_RTE_OMCRPL_TRINYT__INCTL_RCLR
31
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SPI_INLINK_DSCR_EMPTY_INT_CLR Inlink b CONF bc/
SPI_OUTLINK_DSCR_ERROR_INT_CLR Outlink b CONF bc/
SPI_INLINK_DSCR_ERROR_INT_CLR Inlink b CONF bc/
SPI_IN_DONE_INT_CLR inlink b CONF bc/
SPI_IN_ERR_EOF_INT_CLR b CONF bc/
SPI_IN_SUC_EOF_INT_CLR b CONF bc/
SPI_OUT_DONE_INT_CLR outlink b CONF bc/
SPI_OUT_EOF_INT_CLR b CONF bc/
SPI_OUT_TOTAL_EOF_INT_CLR b CONF bc/
SPI_INFIFO_FULL_ERR_INT_CLR 1 SPI_INFIFO_FULL_ERR_INT_RAWb0bCONF_buf bc/
SPI_OUTFIFO_EMPTY_ERR_INT_CLR 1 SPI_OUTFIFO_EMPTY_ERR_INT_RAW b0 bCONF_buf bc/
SPI_SLV_CMD6_INT_CLR SPI CMD6 bc/
SPI_SLV_CMD7_INT_CLR SPI CMD7 bc/
SPI_SLV_CMD8_INT_CLR SPI CMD8 bc/
SPI_SLV_CMD9_INT_CLR SPI CMD9 bc/
SPI_SLV_CMDA_INT_CLR SPI CMDA bc/
602
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
GoBack
Register 24.37. SPI_W0_REG (0x0098)
SPI_BUF0
31
0
0
Reset
SPI_BUF0 buffer 032 bbc/
Register 24.38. SPI_W1_REG (0x009C)
SPI_BUF1
31
0
0
Reset
SPI_BUF1 buffer 132 bbc/
Register 24.39. SPI_W2_REG (0x00A0)
SPI_BUF2
31
0
0
Reset
SPI_BUF2 buffer 232 bbc/
Register 24.40. SPI_W3_REG (0x00A4)
SPI_BUF3
31
0
0
Reset
SPI_BUF3 buffer 332 bbc/
603
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
GoBack
Register 24.41. SPI_W4_REG (0x00A8)
SPI_BUF4
31
0
0
Reset
SPI_BUF4 buffer 432 bbc/
Register 24.42. SPI_W5_REG (0x00AC)
SPI_BUF5
31
0
0
Reset
SPI_BUF5 buffer 532 bbc/
Register 24.43. SPI_W6_REG (0x00B0)
SPI_BUF6
31
0
0
Reset
SPI_BUF6 buffer 632 bbc/
Register 24.44. SPI_W7_REG (0x00B4)
SPI_BUF7
31
0
0
Reset
SPI_BUF7 buffer 732 bbc/
604
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
GoBack
Register 24.45. SPI_W8_REG (0x00B8)
SPI_BUF8
31
0
0
Reset
SPI_BUF8 buffer 832 bbc/
Register 24.46. SPI_W9_REG (0x00BC)
SPI_BUF9
31
0
0
Reset
SPI_BUF9 buffer 932 bbc/
Register 24.47. SPI_W10_REG (0x00C0)
SPI_BUF10
31
0
0
Reset
SPI_BUF10 buffer 1032 bbc/
Register 24.48. SPI_W11_REG (0x00C4)
SPI_BUF11
31
0
0
Reset
SPI_BUF11 buffer 1132 bbc/
605
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
GoBack
Register 24.49. SPI_W12_REG (0x00C8)
SPI_BUF12
31
0
0
Reset
SPI_BUF12 buffer 1232 bbc/
Register 24.50. SPI_W13_REG (0x00CC)
SPI_BUF13
31
0
0
Reset
SPI_BUF13 buffer 1332 bbc/
Register 24.51. SPI_W14_REG (0x00D0)
SPI_BUF14
31
0
0
Reset
SPI_BUF14 buffer 1432 bbc/
Register 24.52. SPI_W15_REG (0x00D4)
SPI_BUF15
31
0
0
Reset
SPI_BUF15 buffer 1532 bbc/
606
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
GoBack
Register 24.53. SPI_W16_REG (0x00D8)
SPI_BUF16
31
0
0
Reset
SPI_BUF16 buffer 1632 bbc/
Register 24.54. SPI_W17_REG (0x00DC)
SPI_BUF17
31
0
0
Reset
SPI_BUF17 buffer 1732 bbc/
607
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
GoBack
Register 24.55. SPI_DIN_MODE_REG (0x00E0)
(reserved)
SPI_TIMINGS_PCI_LKD_INE7N_AMODESPI_DIN6_MODESPI_DIN5_MODESPI_DIN4_MODESPI_DIN3_MODESPI_DIN2_MODESPI_DIN1_MODESPI_DIN0_MODE
31
25 24 23
21 20
18 17
15 14
12 11
98
65
32
0
0 0 0 0 0 0 00
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0 Reset
SPI_DIN0_MODE FSPID b0 1APB_CLK 2APB_CLK 3HCLK 4: HCLK b CONF bc/
SPI_DIN1_MODE FSPIQ b0 1APB_CLK 2APB_CLK 3HCLK 4: HCLK b CONF bc/
SPI_DIN2_MODE FSPIWP b0 1APB_CLK 2APB_CLK 3HCLK 4: HCLK b CONF bc/
SPI_DIN3_MODE FSPIHD b0 1APB_CLK 2APB_CLK 3HCLK 4: HCLK b CONF bc/
SPI_DIN4_MODE FSPIIO4 b0 1APB_CLK 2APB_CLK 3HCLK 4: HCLK b CONF bc/
SPI_DIN5_MODE FSPIIO5 b0 1APB_CLK 2APB_CLK 3HCLK 4: HCLK b CONF bc/
SPI_DIN6_MODE FSPIIO6 b0 1APB_CLK 2APB_CLK 3HCLK 4: HCLK b CONF bc/
SPI_DIN7_MODE FSPIIO7 b0 1APB_CLK 2APB_CLK 3HCLK 4: HCLK b CONF bc/
SPI_TIMING_CLK_ENA 1 HCLK 160 MHz0b CONF bc/
608
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
GoBack
Register 24.56. SPI_DIN_NUM_REG (0x00E4)
(reserved)
SPI_DIN7_NSUPIM_DIN6_NSPUIM_DIN5_NSPUIM_DIN4_NSPUIM_DIN3_NSPUIM_DIN2_NSPUIM_DIN1_NSUPMI_DIN0_NUM
31
16 15 14 13 12 11 10 9
87
65
43
21
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Reset
SPI_DIN0_NUM SPI_DIN0_MODE FSPID b0 1 1 2 b CONF bc/
SPI_DIN1_NUM SPI_DIN1_MODE FSPIQ b0 1 1 2 b CONF bc/
SPI_DIN2_NUM SPI_DIN2_MODE FSPIWP b0 1 1 2 b CONF bc/
SPI_DIN3_NUM SPI_DIN3_MODE FSPIHD b0 1 1 2 b CONF bc/
SPI_DIN4_NUM SPI_DIN4_MODE FSPIIO4 b0 1 1 2 b CONF bc/
SPI_DIN5_NUM SPI_DIN5_MODE FSPIIO5 b0 1 1 2 b CONF bc/
SPI_DIN6_NUM SPI_DIN6_MODE FSPIIO6 b0 1 1 2 b CONF bc/
SPI_DIN7_NUM SPI_DIN7_MODE FSPIIO7 b0 1 1 2 b CONF bc/
609
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
GoBack
Register 24.57. SPI_DOUT_MODE_REG (0x00E8)
(reserved)
SPI_DOUT7_MOSDPEI_DOUT6_MOSDPEI_DOUT5_MOSDPEI_DOUT4_MODSPEI_DOUT3_MOSDPEI_DOUT2_MOSDPEI_DOUT1_MODSEPI_DOUT0_MODE
31
24 23
21 20
18 17
15 14
12 11
98
65
32
0
0 0 0 0 0 0 0 0 0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0 Reset
SPI_DOUT0_MODE FSPID b0 1APB_CLK 2APB_CLK 3HCLK 4: HCLK b CONF bc/
SPI_DOUT1_MODE FSPIQ b0 1APB_CLK 2APB_CLK 3HCLK 4: HCLK b CONF bc/
SPI_DOUT2_MODE FSPIWP b0 1APB_CLK 2APB_CLK 3HCLK 4: HCLK b CONF bc/
SPI_DOUT3_MODE FSPIHD b0 1APB_CLK 2APB_CLK 3HCLK 4: HCLK b CONF bc/
SPI_DOUT4_MODE FSPIIO4 b0 1APB_CLK 2APB_CLK 3HCLK 4: HCLK b CONF bc/
SPI_DOUT5_MODE FSPIIO5 b0 1APB_CLK 2APB_CLK 3HCLK 4: HCLK b CONF bc/
SPI_DOUT6_MODE FSPIIO6 b0 1APB_CLK 2APB_CLK 3HCLK 4: HCLK b CONF bc/
SPI_DOUT7_MODE FSPIIO7 b0 1APB_CLK 2APB_CLK 3HCLK 4: HCLK b CONF bc/
610
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
GoBack
Register 24.58. SPI_DOUT_NUM_REG (0x00EC)
(reserved)
SPI_DOUT7S_PNI_UDMOUT6S_PNI_UDMOUT5S_PNI_UDMOUT4S_PNI_UDMOUT3S_PNI_UDMOUT2S_PNI_UDMOUT1S_PNIU_DMOUT0_NUM
31
16 15 14 13 12 11 10 9
87
65
43
21
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Reset
SPI_DOUT0_NUM SPI_DOUT0_MODE FSPID b 0 1 1 2 b CONF bc/
SPI_DOUT1_NUM SPI_DOUT1_MODE FSPIQ b 0 1 1 2 b CONF bc/
SPI_DOUT2_NUM SPI_DOUT2_MODE FSPIWP b0 1 1 2 b CONF bc/
SPI_DOUT3_NUM SPI_DOUT3_MODE FSPIHD b 0 1 1 2 b CONF bc/
SPI_DOUT4_NUM SPI_DOUT4_MODE FSPIIO4 b 0 1 1 2 b CONF bc/
SPI_DOUT5_NUM SPI_DOUT5_MODE FSPIIO5 b0 1 1 2 b CONF bc/
SPI_DOUT6_NUM SPI_DOUT6_MODE FSPIIO6 b0 1 1 2 b CONF bc/
SPI_DOUT7_NUM SPI_DOUT7_MODE FSPIIO7 b 0 1 1 2 b CONF bc/
611
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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SPI_LCD_MODE_EN
31 30
0
Register 24.59. SPI_LCD_CTRL_REG (0x00F0)
SPI_LCD_VT_HEIGHT
21 20
0
SPI_LCD_VA_HEIGHT
11 10
0
SPI_LCD_HB_FRONT 0
0
Reset
SPI_LCD_HB_FRONT (HSYNC_POSITION + HSYNC_WIDTH + ) b CONF bc/
SPI_LCD_VA_HEIGHT b CONF bc/
SPI_LCD_VT_HEIGHT b CONF bc/
SPI_LCD_MODE_EN 1 LCD VSYNCaHSYNC DEb0b CONF bc/
Register 24.60. SPI_LCD_CTRL1_REG (0x00F4)
SPI_LCD_HT_WIDTH
SPI_LCD_HA_WIDTH
SPI_LCD_VB_FRONT
31
20 19
87
0
0
0
0
Reset
SPI_LCD_VB_FRONT (VSYNC_WIDTH + ) b CONF bc/ SPI_LCD_HA_WIDTH b CONF bc/ SPI_LCD_HT_WIDTH b CONF bc/
612
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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Register 24.61. SPI_LCD_CTRL2_REG (0x00F8)
SPI_LCD_HSYNC_POSITISOPNI_HSYNC_IDLE_POLSPI_LCD_HSYNC_WIDTH
(reserved)
SPI_VSYNC_IDLE_POLSPI_LCD_VSYNC_WIDTH
31
24 23 22
16 15
876
0
0
0
1
0 0 0 0 0 0 0 00
1
Reset
SPI_LCD_VSYNC_WIDTH SPI_VSYNC b CONF bc/
SPI_VSYNC_IDLE_POL SPI_VSYNC b CONF bc/
SPI_LCD_HSYNC_WIDTH SPI_HSYNC b CONF b = + 1bc/
SPI_HSYNC_IDLE_POL SPI_HSYNC b CONF bc/
SPI_LCD_HSYNC_POSITION SPI_HSYNC b CONF b = + 1bbc/
613
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
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Register 24.62. SPI_LCD_D_MODE_REG (0x00FC)
(reserved)
SPI_HSSP_I_BDLAEN_IKD_LSEEPN_I_PDO_LVSYNC_MSOPDI_ED_HSYNC_MSOPID_ED_DE_MODSEPI_D_CD_MODSEPI_D_DQS_MODE
31
17 16 15 14
12 11
98
65
32
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0
0x0
0x0
0x0
0x0
0x0 Reset
SPI_D_DQS_MODE FSPIDQS b0 1APB_CLK 2APB_CLK 3HCLK 4: HCLK b CONF bc/
SPI_D_CD_MODE FSPICD b0 1APB_CLK 2APB_CLK 3HCLK 4: HCLK b CONF bc/
SPI_D_DE_MODE FSPI_DE b0 1APB_CLK 2APB_CLK 3HCLK 4: HCLK b CONF bc/
SPI_D_HSYNC_MODE FSPI_HSYNC b0 1APB_CLK 2APB_CLK 3HCLK 4: HCLK b CONF bc/
SPI_D_VSYNC_MODE FSPI_VSYNC b0 1APB_CLK 2APB_CLK 3HCLK 4: HCLK b CONF bc/
SPI_DE_IDLE_POL SPI_DE bc/
SPI_HS_BLANK_EN 1 SPI_HSYNCb 0SPI_HSYNC bc/
614
ESP32-S2 TRM ( 1.3)
24 SPI (SPI)
GoBack
Register 24.63. SPI_LCD_D_NUM_REG (0x0100)
(reserved)
SPI_D_VSYSNPCI__NDU_MHSYSNPCI__DN_UDME_SNPUI_MD_CD_SNPUI_MD_DQS_NUM
31
10 9
87
65
43
21
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0x0 0x0 0x0 0x0 Reset
SPI_D_DQS_NUM SPI_D_DQS_MODE FSPIDQS b0 1 1 2 b CONF bc/
SPI_D_CD_NUM SPI_D_CD_MODE FSPI_CD b 0 1 1 2 b CONF bc/
SPI_D_DE_NUM SPI_D_DE_MODE FSPI_DE b 0 1 1 2 b CONF bc/
SPI_D_HSYNC_NUM SPI_D_HSYNC_MODE FSPI_HSYNC b0 1 1 2 b CONF bc/
SPI_D_VSYNC_NUM SPI_D_VSYNC_MODE FSPI_VSYNC b0 1 1 2 b CONF bc/
(reserved)
31
28 27
0000
Register 24.64. SPI_DATE_REG (0x03FC)
SPI_DATE 0x1907240
SPI_DATE bc/
0
Reset
615
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
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25
I2C (I2C)
ESP32-S2 I2C (Inter-Integrated Circuit) ESP32-S2 b I2C b
25.1
I2C b · · · (100 Kbit/s) · (400 Kbit/s) · 7-bit 10-bit · SCL · ·
25.2 I2C
25.2.1 I2C
I2C SDA SCL b (open-drain) bI2C b b SCL SDA SCL 9 b 8 7-bit 1 b 7-bit 9 SDA b bbSDA SCL b SCL SDA b ab
616
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
25.2.2 I2C
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25.2-1. I2C Master
25.2-2. I2C Slave
I2C Master Slave I2C_MS_MODE b 25.2-1 I2C Master 25.2-2 I2C Slave bI2C TX/RX RAMa CMD_ControlleraSCL_FSMaSCL_MAIN_FSMaDATA_ShifteraSCL_Filter SDA_Filter b
617
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
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25.2.2.1 TX/RX RAM
TX/RX RAM 32 x 8 bitsbTX RAM I2C b I2C I2C c ACK TX RAM SDA b I2C TX RAM b aacab I2C TX RAM b
RX RAM I2C I2C b I2C c RX RAM b I2C RX RAM b
TX RAM RX RAM FIFO (non-FIFO) I2C_NONFIFO_EN b
TX RAM CPU bCPU TX RAM: FIFO bFIFO I2C_DATA_REG TX RAM TX RAM b (I2C + 0x100) ~(I2C + 0x17C) TX RAMbTX RAM word b I2C + 0x100, I2C + 0x104, I2C + 0x108 bCPU TX RAM TX RAM TX RAM 0x80 b
RX RAM CPU bCPU RX RAM: FIFO bFIFO I2C_DATA_REG RX RAM RX RAM b (I2C + 0x100) ~(I2C + 0x17C) RX RAMbRX RAM word b I2C + 0x100, I2C + 0x104, I2C + 0x108 b
TX RAM RX RAM TX RAM RX RAM 32 x 8 bits RAMb RAM TX RAM RX RAMb
25.2.2.1.1 CMD_Controller
I2C CMD_Controller 16 SCL_FSM SDA_FSMb
25.2-3. I2C
I2C 25.2-3 b :
1. CMD_DONE: b CMD_DONE 1b CMD_DONE b CMD_DONE b
618
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
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2. op_code: 5 b
· RSTART: op_code 0 RSTART I2C I2C START RESTART b
· WRITE: op_code 1 WRITE I2C a cab
· READ: op_code 2 READ I2C b
· STOP: op_code 3 STOP I2C I2C STOP b CMD_Controller b CMD_Controller 0 b
· END:op_code 4 END I2C SCL I2C b CMD_Controller b RAM CMD_Controller I2C b CMD_Controller 0 b
3. ack_value: I2C I2C ACK bRSTART aSTOP aEND a WRITE b
4. ack_exp: I2C I2C ACK bRSTART aSTOP aEND aREAD b
5. ack_check_en: I2C ACK ack_exp b ACK WRITE ack_exp I2C Master I2C_NACK_INT STOPb1: ACK ; 0: ACK b RSTART aSTOP aEND aREAD b
6. byte_num: () 255 1bRSTART aSTOP aEND byte_num b
0 STOP END b 16 STOP END b
I2C START STOP b END I2C baaa b RAM I2C b
25.2.2.2 SCL_FSM
SCL_FSM SCL bI2C_SCL_LOW_PERIOD_REGaI2C_SCL_HIGH_PERIOD_REG I2C_SCL_WAIT_HIGH_PERIOD SCL b SCL_FSM I2C_SCL_ST_TO I2C_SCL_ST_TO_INT b
25.2.2.3 SCL_MAIN_FSM
SCL_MAIN_FSM SDA b SCL_MAIN_FSM I2C_SCL_MAIN_ST_TO I2C_SCL_MAIN_ST_TO_INT b
619
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
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25.2.2.4 DATA_Shifter
DATA_Shifter b I2C_RX_LSB_FIRST I2C_TX_LSB_FIRST b
25.2.2.5 SCL_Filter SDA_Filter
SCL_Filter SDA_Filter SCL SDA b I2C_SCL_FILTER_EN I2C_SDA_FILTER_EN b
SCL_Filter SCL_Filter SCL, I2C_SCL_FILTER_THRES APB , , b b, SCL_Filter SDA_Filter I2C_SCL_FILTER_THRES I2C_SDA_FILTER_THRES APB b
25.2.3 I2C
I2C APB_CLK REF_TICKbI2C_REF_ALWAYS_ON 1 APB_CLK REF_TICKb
25.2-4. I2C
25.2-4 I2C (I2C_CLK) I2C_REF_ALWAYS_ON 1 TAP B_CLK I2C_REF_ALWAYS_ON 0 TREF _T ICK bI2C START a STOP aaaSCL 25.2-4 b25.2-4 :
1. I2C_SCL_START_HOLD_TIME I2C start SDA SCL b cI2C_SCL_START_HOLD_TIME +1bb
2. I2C_SCL_LOW_PERIOD SCL bSCL cI2C_SCL_LOW_PERIOD + 1 b SCL I2C END SCL SCL SCL bb
3. I2C_SCL_WAIT_HIGH_PERIOD SCL b SCL b SCL bb
4. I2C_SCL_HIGH_PERIOD SCL b b SCL I2C_SCL_WAIT_HIGH_PERIOD + 1 SCL
620
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
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fscl
=
fI2C_CLK I2C_SCL_LOW_PERIOD+1+I2C_SCL_HIGH_PERIOD+I2C_SCL_WAIT_HIGH_PERIOD
5. I2C_SDA_SAMPLE_TIME SCL SDA b SCL SDA bb
6. I2C_SDA_HOLD_TIME SDA SCL b b
SCL SDA open-drain bI2C open-drain
1. I2C_SCL_FORCE_OUTaI2C_SDA_FORCE _OUT SCL SDA PAD GPIO_PINn_PAD_DRIVER open-drain b
2. I2C_SCL_FORCE_OUT I2C_SDA_FORCE_OUTb
SCL SDA bI2C SCL SDA SCL b
I2C_SCL_FORCE_OUT I2C_SCL_PD_EN 1 SCL ; I2C_SDA_FORCE_OUT I2C_SDA_PD_EN 1 SDA b
25.3
I2C Master Slave I2C b
25.3.1 I2C 7-bit
25.3-1. I2C Master 7-bit Slave
25.3-1 I2C Master 7-bit N I2C Slave RAMb 25.3-1 RAM 7-bit Slave + 1-bit 0 bcmd b RAM I2C_TRANS_START b
1. SCL SCL Master Slave b
621
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
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2. RSTART START b
3. WRITE RAM N+1 b
4. STOPb I2C Master STOP I2C_TRANS_COMPLETE_INT b
32 RAM b b I2C Master RAM I2C_TXFIFO_WM_THRHD I2C_TXFIFO_WM_INT b
RAM b RAM non-FIFO I2C_TX_UPDATE RAM I2C_FIFO_ST_REG I2C_TXFIFO_START_ADDR I2C_TXFIFO_END_ADDR RAM RAM b RAM FIFO I2C_DATA_REG b
1. I2C Master WRITE ack_check_en 1 I2C Master ACK b ACK WRITE ack_exp I2C Master I2C_NACK_INT STOPb
2. I2C Master SCL SDA SDA I2C Master I2C_ARBITRATION_LOST_INT IDLE SCL SDA b
I2C Slave I2C Master START b I2C Slave I2C_SLAVE_ADDR[6:0] I2C Slave bI2C Slave RAM b
32 RAM b b I2C Slave RAM I2C_RXFIFO_WM_THRHD I2C_RXFIFO_WM_INT b
RAM b RAM non-FIFO I2C _RX_UPDATE RAM RD_FIFO_ST_REG RXFIFO_START_ADDR RXFIFO_END_ADDR RAM RAM b RAM FIFO I2C_DATA_REG b
622
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
25.3.2 I2C 10-bit
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25.3-2. I2C Master 10-bit Slave
SLV_ADDR bESP32-S2 I2C 7-bit cSLV_ADDR[6:0]) 10-bit cSLV_ADDR[9:0]) b 25.3-2 I2C Master N 10-bit I2C Slave b 7-bit 10-bit b 7 bits slave_addr_first_7bits RAM addr0 slave_addr_first_7bits (0x78 | SLV_ADDR[9:8])b slave_addr_second_byte RAM addr1 slave_addr_second_byte SLV_ADDR[7:0] b I2C_ADDR_10BIT_EN 10-bit bI2C_SLAVE_ADDR I2C Slave bI2C_SLAVE_ADDR[14:7] SLV_ADDR[7:0] I2C_SLAVE_ADDR[6:0] (0x78 | SLV_ADDR[9:8]) b 10-bit Slave 7-bit , WRITE byte_num RAM 1b
25.3.3 I2C 7-bit
25.3-3. I2C Master 7-bit Slave M RAM
slave b I2C I2C bRAM non-FIFO b I2C
623
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
GoBack
_FIFO_ADDR_CFG_EN b 25.3-3 I2C Slave byte0 ~ byte(N-1) Slave RAM addrM b 31 0 b
25.3.4 I2C 7-bit
25.3-4. I2C Master 7-bit Slave
RAM 32 RAM b END END SCL RAM b
25.3-4 I2C Master Slaveb I2C Master Master RAM I2C_TRANS_STARTI2C Master b END I2C Master SCL SCL I2C b I2C_END_DETECT_INT b
I2C_END_DETECT_INT RAM I2C_END_DETECT_INT b cmd1 STOP , Slaveb I2C_TRANS_START I2C Master STOP b Slave ,I2C Master I2C Master I2C_END_DETECT_INT cmd b I2C_TRANS_START I2C Master STOP b
I2C Master b STOP b I2C_FSM_RST I2C I2C_FSM_RSTb
I2C Master I2C_SCL_RST_SLV_EN, I2C_ SCL_RST_SLV_NUM SCL I2C_SCL_RST_SLV_EN b
624
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
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Master Slave ESP32-S2 I2C I2C b
25.3.5 I2C 7-bit
25.3-5. I2C Master 7-bit Slave
25.3-5 I2C Master 7-bit I2C Slave N RAM bcmd1 WRITE I2C Master I2C Slave b 7-bit I2C Slave b 1 bI2C Slave I2C MasterbI2C Master READ ack_value ACKb 25.3-5 READ I2C Master cmd2 N-1 ACK cmd3 NACK bI2C Master RAM byte0 cSlave +1-bit b
25.3.6 I2C 10-bit
25.3-6. I2C Master 10-bit Slave
625
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
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25.3-6 I2C Master 10-bit I2C Slave RAM b 7-bit I2C Master 2 RAM 2 I2C Slave 10-bit b 7-bit I2C Slave I2C_ADDR_10BIT_EN I2C_SLAVE_ADDR[140]b 25.3.2 b
25.3.7 I2C 7-bit
25.3-7. I2C Master 7-bit Slave M N
25.3-7 I2C Master I2C Slave RAM b 1. I2C Slave I2C_FIFO_ADDR_CFG_EN RAM b 2. I2C Master I2C Slave Mb 3. I2C Master I2C_TRANS_STARTI2C Slave RAM M N I2C Masterb
626
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
25.3.8 I2C 7-bit
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25.3-8. I2C Master 7-bit Slave
25.3-8 I2C Master END I2C Slave N+M b
1. RAM b 2. Slave RAM I2C_TRANS_STARTI2C b END
I2C Master RAM , I2C_END_DETECT_INT b cmd2 STOP I2C Slave, I2C_TRANS_STARTI2C Master , STOP b 3. cmd2 END I2C Master I2C Master I2C_END_DETECT_INT cmd b I2C_TRANS_STARTI2C Master STOP b
25.3.9 SCL
SCL b I2C_SLAVE_SCL_STRETCH_EN I2C_STRETCH_PROTECT_NUM b SCL
627
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
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1. I2C SDA b 2. I2C RX RAM b 3. I2C TX RAM b SCL I2C_STRETCH_CAUSE b I2C_SLAVE_SCL_STRETCH_CLR SCL b
25.4
· I2C_SLAVE_STRETCH_INT: I2C SCL b · I2C_DET_START_INT I2C START b · I2C_SCL_MAIN_ST_TO_INT: I2C SCL_MAIN_FSM
I2C_SCL_MAIN_ST_TO[23:0] b · I2C_SCL_ST_TO_INT: I2C SCL_FSM I2C_SCL_ST_TO[23:0]
b · I2C_RXFIFO_UDF_INT: I2C I2C_NONFIFO_RX_THRES
b · I2C_TXFIFO_OVF_INT: I2C I2C_NONFIFO_TX_THRES b · I2C_NACK_INT: I2C Master ACK ACK
I2C Slave ACK 1 b · I2C_TRANS_START_INT: I2C START b · I2C_TIME_OUT_INT: I2C SCL I2C_TIME_OUT
b · I2C_TRANS_COMPLETE_INT: I2C STOP b · I2C_MST_TXFIFO_UDF_INT: I2C TX FIFO b · I2C_ARBITRATION_LOST_INT: I2C Master SCL SDA
b · I2C_BYTE_TRANS_DONE_INT: I2C b · I2C_END_DETECT_INT I2C op_code END I2C END b · I2C_RXFIFO_OVF_INT I2C RX FIFO b · I2C_TXFIFO_WM_INTI2C TX FIFO bI2C_FIFO_PRT_EN 1 TX FIFO
I2C_TXFIFO_WM_THRHD[4:0] b · I2C_RXFIFO_WM_INTI2C RX FIFO bI2C_FIFO_PRT_EN 1 RX FIFO
I2C_RXFIFO_WM_THRHD[4:0] b
25.5
I2C 25.5-1 b 3 b
628
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
25.5-1. I2C
I2C0 I2C1
PeriBUS1 PeriBUS2 PeriBUS1 PeriBUS2
0x3F413000 0x60013000 0x3F427000 0x60027000
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25.6
I2C cb I2C 25.5 b
I2C_SCL_LOW_PERIOD_REG I2C_SDA_HOLD_REG I2C_SDA_SAMPLE_REG I2C_SCL_HIGH_PERIOD_REG I2C_SCL_START_HOLD_REG
I2C_SCL_RSTART_SETUP_REG I2C_SCL_STOP_HOLD_REG I2C_SCL_STOP_SETUP_REG
I2C_SCL_ST_TIME_OUT_REG I2C_SCL_MAIN_ST_TIME_OUT_REG I2C_CTR_REG I2C_TO_REG I2C_SLAVE_ADDR_REG I2C_FIFO_CONF_REG I2C_SCL_SP_CONF_REG I2C_SCL_STRETCH_CONF_REG I2C_SR_REG I2C_FIFO_ST_REG I2C_DATA_REG I2C_INT_RAW_REG I2C_INT_CLR_REG I2C_INT_ENA_REG I2C_INT_STATUS_REG
SCL SCL SCL SCL START SDA SCL SCL SDA STOP SCL STOP SDA SCL SCL SCL
0x0000 0x0030 0x0034 0x0038 0x0040
0x0044 0x0048 0x004C
0x0098 0x009C
/ / / / /
/ / /
/ /
FIFO I2C SCL
0x0004 0x000C 0x0010 0x0018 0x00A0 0x00A4
/ / / / /
I2C FIFO / FIFO
0x0008 0x0014 0x001C
/
I2C
0x0020 0x0024 0x0028 0x002C
/
629
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
I2C_SCL_FILTER_CFG_REG I2C_SDA_FILTER_CFG_REG I2C_COMD0_REG I2C_COMD1_REG I2C_COMD2_REG I2C_COMD3_REG I2C_COMD4_REG I2C_COMD5_REG I2C_COMD6_REG I2C_COMD7_REG I2C_COMD8_REG I2C_COMD9_REG I2C_COMD10_REG I2C_COMD11_REG I2C_COMD12_REG I2C_COMD13_REG I2C_COMD14_REG I2C_COMD15_REG I2C_DATE_REG
SCL SDA
I2C 0 I2C 1 I2C 2 I2C 3 I2C 4 I2C 5 I2C 6 I2C 7 I2C 8 I2C 9 I2C 10 I2C 11 I2C 12 I2C 13 I2C 14 I2C 15
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0x0050 0x0054
/ /
0x0058 0x005C 0x0060 0x0064 0x0068 0x006C 0x0070 0x0074 0x0078 0x007C 0x0080 0x0084 0x0088 0x008C 0x0090 0x0094
/ / / / / / / / / / / / / / / /
0x00F8 /
25.7
Register 25.1. I2C_SCL_LOW_PERIOD_REG (0x0000)
(reserved)
31
14 13
000000000000000000
I2C_SCL_LOW_PERIOD 0x00
0
Reset
I2C_SCL_LOW_PERIOD SCL I2C b(/)
630
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
GoBack
Register 25.2. I2C_SDA_HOLD_REG (0x0030)
(reserved)
31
10 9
0000000000000000000000
I2C_SDA_HOLD_TIME
0
0x0
Reset
I2C_SDA_HOLD_TIME SCL I2C b (/)
Register 25.3. I2C_SDA_SAMPLE_REG (0x0034)
(reserved)
31
10 9
0000000000000000000000
I2C_SDA_SAMPLE_TIME
0
0x0
Reset
I2C_SDA_SAMPLE_TIME SDA I2C b(/)
(reserved)
31
28 27
0000
Register 25.4. I2C_SCL_HIGH_PERIOD_REG (0x0038)
I2C_SCL_WAIT_HIGH_PERIOD 0x00
14 13
I2C_SCL_HIGH_PERIOD 0x00
0
Reset
I2C_SCL_HIGH_PERIOD SCL I2C b(/)
I2C_SCL_WAIT_HIGH_PERIOD SCL_FSM SCL I2C b(/)
631
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
GoBack
Register 25.5. I2C_SCL_START_HOLD_REG (0x0040)
(reserved)
31
10 9
0000000000000000000000
I2C_SCL_START_HOLD_TIME
0
8
Reset
I2C_SCL_START_HOLD_TIME START SDA SCL I2C b(/)
Register 25.6. I2C_SCL_RSTART_SETUP_REG (0x0044)
(reserved)
31
10 9
0000000000000000000000
I2C_SCL_RSTART_SETUP_TIME
0
8
Reset
I2C_SCL_RSTART_SETUP_TIME RESTART SCL SDA I2C b(/)
Register 25.7. I2C_SCL_STOP_HOLD_REG (0x0048)
(reserved)
31
14 13
000000000000000000
I2C_SCL_STOP_HOLD_TIME 0x00
0
Reset
I2C_SCL_STOP_HOLD_TIME STOP I2C b(/)
632
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
GoBack
Register 25.8. I2C_SCL_STOP_SETUP_REG (0x004C)
(reserved)
31
10 9
0000000000000000000000
I2C_SCL_STOP_SETUP_TIME
0
0x0
Reset
I2C_SCL_STOP_SETUP_TIME SCL SDA I2C b(/)
Register 25.9. I2C_SCL_ST_TIME_OUT_REG (0x0098)
(reserved)
31
24 23
00000000
I2C_SCL_ST_TO 0x0100
I2C_SCL_ST_TO SCL_FSM b(/)
0
Reset
Register 25.10. I2C_SCL_MAIN_ST_TIME_OUT_REG (0x009C)
(reserved)
31
24 23
00000000
I2C_SCL_MAIN_ST_TO 0x0100
I2C_SCL_MAIN_ST_TO SCL_MAIN_FSM b(/)
0
Reset
633
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
GoBack
Register 25.11. I2C_CTR_REG (0x0004)
(reserved)
I2C_RI2EFC__AFILS2WMCA__YARIS2RS_CBTO_ITNCRI2LAKCT__IOERINN2X__CEL_NSTIXB2__CLF_SITRBIR2S_ACTFN_ISRMI_S2STSC_T_MARRIO2XTD_CFE_USILA2LMC__PASLIC2CEKCL____SLFSCEODLVR_AECL_LEEFVO_EORLUCTE_OUT
31
12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 1 Reset
I2C_SDA_FORCE_OUT SDA b 0: 1: (/)
I2C_SCL_FORCE_OUT SCL b 0: 1: (/)
I2C_SAMPLE_SCL_LEVEL b1SCL SDA b0SCL SDA b(/)
I2C_RX_FULL_ACK_LEVEL rx_fifo_cnt ACK b(/)
I2C_MS_MODE I2C b I2C b(/)
I2C_TRANS_START TX FIFO b(/)
I2C_TX_LSB_FIRST b10 b(/)
I2C_RX_LSB_FIRST b10 b(/)
I2C_CLK_EN (/)
I2C_ARBITRATION_EN I2C b(/)
I2C_FSM_RST SCL_FSMb(/)
I2C_REF_ALWAYS_ON REF_TICKb(/)
634
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
GoBack
Register 25.12. I2C_TO_REG (0x000C)
(reserved)
I2C_TIME_OUT_EN
31
25 24 23
0 0 0 0 0 0 00
I2C_TIME_OUT_VALUE 0x0000
0
Reset
I2C_TIME_OUT_VALUE APB b(/) I2C_TIME_OUT_EN b(/)
Register 25.13. I2C_SLAVE_ADDR_REG (0x0010)
I2C_ADDR_10BIT_EN
31 30
(reserved)
15 14
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2C_SLAVE_ADDR 0x00
I2C_SLAVE_ADDR Slave b(/) I2C_ADDR_10BIT_EN 10 b(/)
0
Reset
635
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
GoBack
Register 25.14. I2C_FIFO_CONF_REG (0x0018)
(reserved)
I2C_FIFO_PRT_EN I2C_NONFIFO_TX_THRES
31
27 26 25
20 19
0 0 0 0 01
0x15
I2C_NONFIFO_RX_TI2HCR_ETSIX2_CF_IFRIO2X__CFR_ISFFITI2OFCO__R_NSAOTDNDFRI_FCOF_GE_IN2ECN_TXFIFO_WM_THRHD
I2C_RXFIFO_WM_THRHD
14 13 12 11 10 9
54
0
0x15
0000
0x4
0xb
Reset
I2C_RXFIFO_WM_THRHD non-FIFO RX FIFO bI2C_FIFO_PRT_EN 1 RX FIFO I2C_TXFIFO_WM_THRHD[4:0] I2C_TXFIFO_WM_INT_RAW b(/)
I2C_TXFIFO_WM_THRHD non-FIFO TX FIFO bI2C_FIFO_PRT_EN 1 TX FIFO I2C_TXFIFO_WM_THRHD[4:0] I2C_TXFIFO_WM_INT_RAW b(/)
I2C_NONFIFO_EN APB non-FIFO b(/)
I2C_FIFO_ADDR_CFG_EN 1 RAM b(/)
I2C_RX_FIFO_RST RX FIFO b(/)
I2C_TX_FIFO_RST TX FIFO b(/)
I2C_NONFIFO_RX_THRES I2C I2C_NONFIFO_TX_THRES I2C_RXFIFO_UDF_INT b(/)
I2C_NONFIFO_TX_THRES I2C I2C_NONFIFO_TX_THRES I2C_TXFIFO_OVF_INT b(/)
I2C_FIFO_PRT_EN non-FIFO FIFO b TX FIFO RX FIFO aaab(/)
636
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
GoBack
Register 25.15. I2C_SCL_SP_CONF_REG (0x00A0)
(reserved)
I2C_SI2DCA__PSCDL__EPND_ENI2C_SCL_RST_SIL2VC__NSUCML_RST_SLV_EN
31
87 65
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0
0x0
0 Reset
I2C_SCL_RST_SLV_EN I2C SCL b I2C_SCL_RST_SLV_NUM[4:0]b(/)
I2C_SCL_RST_SLV_NUM SCL bI2C_SCL_RST_SLV_EN 1 b (/)
I2C_SCL_PD_EN I2C SCL b1b0b I2C_SCL_FORCE_OUT I2C_SCL_PD_EN 1 SCL b(/)
I2C_SDA_PD_EN I2C SDA b1b0b I2C_SDA_FORCE_OUT I2C_SDA_PD_EN 1 SDA b(/)
Register 25.16. I2C_SCL_STRETCH_CONF_REG (0x00A4)
(reserved)
I2C_SI2LACV_ES_LSACVLE__SSTCRLE_TSCTHR_ECTCLRH_ENI2C_STRETCH_PROTECT_NUM
31
12 11 10 9
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0
0x0
Reset
I2C_STRETCH_PROTECT_NUM I2C SCL b(/)
I2C_SLAVE_SCL_STRETCH_EN SCL b1 b0 b I2C_SLAVE_SCL_STRETCH_EN 1 SCL b I2C_STRETCH_CAUSEb(/)
I2C_SLAVE_SCL_STRETCH_CLR I2C SCL b()
637
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
GoBack
Register 25.17. I2C_SR_REG (0x0008)
(reserved) I2C_SCL_S(TrAeTsEe_rvLeAdS)TI2C_SCL_MAIN_STATE_LIA2SCT_TXFIFO_CNT
(reserved) I2C_STRETCH_CAUSEI2C_RXFIFO_CNT (reserIv2eCd_)BI2YTCE__SIT2LRACAV_NEBIS_2UACSD__DABIR2RUECBSS__YSTLIEIO2MDCSET__SOI2LUACTV_ER_ERSWP_REC
31 30
28 27 26
24 23
18 17 16 15 14 13
87 6 5 4 3 2 1 0
0
0x0
0
0x0
0x0
0 0 0x0
0x0
0 0 0 0 0 0 0 0 Reset
I2C_RESP_REC ACK b0ACK1NACKb() I2C_SLAVE_RW 10b() I2C_TIME_OUT I2C I2C_TIME_OUT 1b()
I2C_ARB_LOST I2C SCL 1 b()
I2C_BUS_BUSY 1I2C 0I2C b()
I2C_SLAVE_ADDRESSED I2C ab ()
I2C_BYTE_TRANS 1b()
I2C_RXFIFO_CNT b()
I2C_STRETCH_CAUSE SCL b0I2C SCL b1 TX FIFO SCL b2 RX FIFO SCL b()
I2C_TXFIFO_CNT RAM b()
I2C_SCL_MAIN_STATE_LAST I2C b012ACK 345 ACK6 ACK ()
I2C_SCL_STATE_LAST SCL b0123 456 ()
638
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
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(reserved)
31 30 29
00
Register 25.18. I2C_FIFO_ST_REG (0x0014)
I2C_SLAVE_RW_POINT I2C_TIX2_CU_PRDXA_TUEPDATEI2C_TXFIFO_END_ADDR
I2C_TXFIFO_START_ADDR I2C_RXFIFO_END_ADDR
I2C_RXFIFO_START_ADDR
22 21 20 19
15 14
10 9
54
0
0x0
00
0x0
0x0
0x0
0x0
Reset
I2C_RXFIFO_START_ADDR I2C_NONFIFO_RX_THRES b ()
I2C_RXFIFO_END_ADDR I2C_NONFIFO_RX_THRES b I2C_RX_REC_FULL_INT I2C_TRANS_COMPLETE_INT b()
I2C_TXFIFO_START_ADDR I2C_NONFIFO_TX_THRES b( )
I2C_TXFIFO_END_ADDR I2C_NONFIFO_TX_THRES b I2C_TX_SEND_EMPTY_INT I2C_TRANS_COMPLETE_INT b()
I2C_RX_UPDATE I2C_RX_UPDATE 0 1 I2C_RXFIFO_END_ADDR I2C_RXFIFO_START_ADDR b()
I2C_TX_UPDATE I2C_TX_UPDATE 0 1 I2C_TXFIFO_END_ADDR I2C_TXFIFO_START_ADDR b()
I2C_SLAVE_RW_POINT b()
Register 25.19. I2C_DATA_REG (0x001C)
(reserved)
31
87
000000000000000000000000
I2C_FIFO_RDATA RX FIFO TX FIFO b(/)
I2C_FIFO_RDATA
0
0x0
Reset
639
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
GoBack
Register 25.20. I2C_INT_RAW_REG (0x0020)
(reserved)
I2C_SI2LACV_EDI_2ESCTT__RSSEIT2CTACLCR__HTMS__I2CAIINNCLINT_T___S_RISTR2RXT_AFCAT_WIW_FTOTOO_IX2__IFNCUIINFT_DOT_NFI__R2A_ROACCINAWV_KWTTF_I_R_2INRAICNTAN_T_WTS_RII_2MRASCAWET_WA_TORIR2TUAC_TN_I_NSMII_TN2SC_CTTRO___AMRTAIW2XARPFWCBLI_IEFTBTORI2EY_A_TCUTEI_IDNO_EFTITNN2__R_CDIRANL__ANOTRDWIS_S2XE_TRFCTD_AI_EFWIOTNCOIXN2TT_FE_C_OI_IFR_VNIOARNFTW_X_T_WFI_RNIMFRATOAW__W_IRNWATMW__RIANWT_RAW
31
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_RXFIFO_WM_INT_RAW I2C_RXFIFO_WM_INT b() I2C_TXFIFO_WM_INT_RAW I2C_TXFIFO_WM_INT b() I2C_RXFIFO_OVF_INT_RAW I2C_RXFIFO_OVF_INT b() I2C_END_DETECT_INT_RAW I2C_END_DETECT_INT b() I2C_BYTE_TRANS_DONE_INT_RAW I2C_BYTE_TRANS_DONE_INT b() I2C_ARBITRATION_LOST_INT_RAW I2C_ARBITRATION_LOST_INT b() I2C_MST_TXFIFO_UDF_INT_RAW I2C_MST_TXFIFO_UDF_INT b() I2C_TRANS_COMPLETE_INT_RAW I2C_TRANS_COMPLETE_INT b() I2C_TIME_OUT_INT_RAW I2C_TIME_OUT_INT b() I2C_TRANS_START_INT_RAW I2C_TRANS_START_INT b() I2C_NACK_INT_RAW I2C_NACK_INT b() I2C_TXFIFO_OVF_INT_RAW I2C_TXFIFO_OVF_INT b() I2C_RXFIFO_UDF_INT_RAW I2C_RXFIFO_UDF_INT b() I2C_SCL_ST_TO_INT_RAW I2C_SCL_ST_TO_INT b() I2C_SCL_MAIN_ST_TO_INT_RAW I2C_SCL_MAIN_ST_TO_INT b() I2C_DET_START_INT_RAW I2C_DET_START_INT b() I2C_SLAVE_STRETCH_INT_RAW I2C_SLAVE_STRETCH_INT b()
640
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
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Register 25.21. I2C_INT_CLR_REG (0x0024)
(reserved)
I2C_SI2LACV_EDI_2ESCTT__RSSEIT2CTACLCR__HTMS__I2CAIINNCLINT_T___S_RISCTC2XT_LFCLT_RRI_FTOTOO_IX2__IFNCUIINFT_DOT_NFI_C_2A_COLCCINRLV_KRTTF_I_R_2INCAICNTLN_TR_TS_CII_2MCLSCLRET_RA_TORIR2TUAC_TN_I_NSMII_TN2SC_CTTCO___LMCTAIR2XLRPRFCBLI_IEFTBTORI2EY_A_TCUTEI_IDNO_EFTITNN2__R_CDICANL__LNOTRDRIS_S2XE_CTFCTD_LI_EFRIOTNCOIXN2TT_FE_C_OI_IFC_VNIOLRNFTR_X_T_WFI_CNIMCFLTORL__R_CINWLTRM__CILNRT_CLR
31
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_RXFIFO_WM_INT_CLR I2C_RXFIFO_WM_INT b() I2C_TXFIFO_WM_INT_CLR I2C_TXFIFO_WM_INT b() I2C_RXFIFO_OVF_INT_CLR I2C_RXFIFO_OVF_INT b() I2C_END_DETECT_INT_CLR I2C_END_DETECT_INT b() I2C_BYTE_TRANS_DONE_INT_CLR I2C_BYTE_TRANS_DONE_INT b() I2C_ARBITRATION_LOST_INT_CLR I2C_ARBITRATION_LOST_INT b() I2C_MST_TXFIFO_UDF_INT_CLR I2C_MST_TXFIFO_UDF_INT b() I2C_TRANS_COMPLETE_INT_CLR I2C_TRANS_COMPLETE_INT b() I2C_TIME_OUT_INT_CLR I2C_TIME_OUT_INT b() I2C_TRANS_START_INT_CLR I2C_TRANS_START_INT b() I2C_NACK_INT_CLR I2C_NACK_INT b() I2C_TXFIFO_OVF_INT_CLR I2C_TXFIFO_OVF_INT b() I2C_RXFIFO_UDF_INT_CLR I2C_RXFIFO_UDF_INT b() I2C_SCL_ST_TO_INT_CLR I2C_SCL_ST_TO_INT b() I2C_SCL_MAIN_ST_TO_INT_CLR I2C_SCL_MAIN_ST_TO_INT b() I2C_DET_START_INT_CLR I2C_DET_START_INT b() I2C_SLAVE_STRETCH_INT_CLR I2C_SLAVE_STRETCH_INT b()
641
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
GoBack
Register 25.22. I2C_INT_ENA_REG (0x0028)
(reserved)
I2C_SI2LACV_EDI_2ESCTT__RSSEIT2CTACLCR__HTMS__I2CAIINNCLINT_T___S_RISTE2EXT_NNFCT_IAA_FTOTOO_IX2__IFNCUIINFT_DOT_NFI__E2A_EONCCINNVA_KTTAF_I_R_2INEAICNTNN_T_ATS_EII_2MENSCNEAT_AA_TORIR2TUAC_TN_I_NSMII_TN2SC_CTTEO___NMETAIAN2XRPFCABLI_IEFTBTORI2EY_A_TCUTEI_IDNO_EFTITNN2__R_CDIEANL__NNOTRDAIS_S2XE_TEFCTD_NI_EFIOATNCOIXN2TT_FE_C_OI_IFE_VNIONRNFT_AX_T_WFI_ENIMFENTONA___AIENWNTMA__EINNAT_ENA
31
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_RXFIFO_WM_INT_ENA I2C_RXFIFO_WM_INT b(/) I2C_TXFIFO_WM_INT_ENA I2C_TXFIFO_WM_INT b(/) I2C_RXFIFO_OVF_INT_ENA I2C_RXFIFO_OVF_INT b(/) I2C_END_DETECT_INT_ENA I2C_END_DETECT_INT b(/) I2C_BYTE_TRANS_DONE_INT_ENA I2C_BYTE_TRANS_DONE_INT b(/) I2C_ARBITRATION_LOST_INT_ENA I2C_ARBITRATION_LOST_INT b(/) I2C_MST_TXFIFO_UDF_INT_ENA I2C_MST_TXFIFO_UDF_INT b(/) I2C_TRANS_COMPLETE_INT_ENA I2C_TRANS_COMPLETE_INT b(/) I2C_TIME_OUT_INT_ENA I2C_TIME_OUT_INT b(/) I2C_TRANS_START_INT_ENA I2C_TRANS_START_INT b(/) I2C_NACK_INT_ENA I2C_NACK_INT b(/) I2C_TXFIFO_OVF_INT_ENA I2C_TXFIFO_OVF_INT b(/) I2C_RXFIFO_UDF_INT_ENA I2C_RXFIFO_UDF_INT b(/) I2C_SCL_ST_TO_INT_ENA I2C_SCL_ST_TO_INT b(/) I2C_SCL_MAIN_ST_TO_INT_ENA I2C_SCL_MAIN_ST_TO_INT b(/) I2C_DET_START_INT_ENA I2C_DET_START_INT b(/) I2C_SLAVE_STRETCH_INT_ENA I2C_SLAVE_STRETCH_INT b(/)
642
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
GoBack
Register 25.23. I2C_INT_STATUS_REG (0x002C)
(reserved)
I2C_SI2LACV_EDI_2ESCTT__RSSEIT2CTACLCR__HTMS__I2CAIINNCLINT_T___S_RISTSS2XTT_TFCT_I_FTOTOO_IX2__IFNCUIINFT_DOT_NFI_S_2A_STOCCINTV_KTTF_I_R_2INSAICNTTN_T_TS_SII_2MSTSCTET_A_TORIR2TUAC_TN_I_NSMII_TN2SC_CTTSO___TMSTAIT2XRPFCBLI_IEFTBTORI2EY_A_TCUTEI_IDNO_EFTITNN2__R_CDISANL__TNOTRDIS_S2XE_TSFCTTD_I_EFIOTNCOIXN2TT_FE_C_OI_IFS_VNIOTRNFT_X_T_WFI_SNIMSFTTOT___SINWTTM__SITNT_ST
31
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_RXFIFO_WM_INT_ST I2C_RXFIFO_WM_INT b() I2C_TXFIFO_WM_INT_ST I2C_TXFIFO_WM_INT b() I2C_RXFIFO_OVF_INT_ST I2C_RXFIFO_OVF_INT b() I2C_END_DETECT_INT_ST I2C_END_DETECT_INT b() I2C_BYTE_TRANS_DONE_INT_ST I2C_BYTE_TRANS_DONE_INT b() I2C_ARBITRATION_LOST_INT_ST I2C_ARBITRATION_LOST_INT b() I2C_MST_TXFIFO_UDF_INT_ST I2C_MST_TXFIFO_UDF_INT b() I2C_TRANS_COMPLETE_INT_ST I2C_TRANS_COMPLETE_INT b() I2C_TIME_OUT_INT_ST I2C_TIME_OUT_INT b() I2C_TRANS_START_INT_ST I2C_TRANS_START_INT b() I2C_NACK_INT_ST I2C_NACK_INT b() I2C_TXFIFO_OVF_INT_ST I2C_TXFIFO_OVF_INT b() I2C_RXFIFO_UDF_INT_ST I2C_RXFIFO_UDF_INT b() I2C_SCL_ST_TO_INT_ST I2C_SCL_ST_TO_INT b() I2C_SCL_MAIN_ST_TO_INT_ST I2C_SCL_MAIN_ST_TO_INT b() I2C_DET_START_INT_ST I2C_DET_START_INT b() I2C_SLAVE_STRETCH_INT_ST I2C_SLAVE_STRETCH_INT b()
643
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
GoBack
Register 25.24. I2C_SCL_FILTER_CFG_REG (0x0050)
(reserved)
I2C_SCL_FILTIE2RC__ESNCL_FILTER_THRES
31
543
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01
0x0
Reset
I2C_SCL_FILTER_THRES SCL I2C b I2C b(/)
I2C_SCL_FILTER_EN SCL b(/)
Register 25.25. I2C_SDA_FILTER_CFG_REG (0x0054)
(reserved)
I2C_SDA_FILTIE2RC__ESNDA_FILTER_THRES
31
543
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01
0x0
Reset
I2C_SDA_FILTER_THRES SDA I2C b I2C b(/)
I2C_SDA_FILTER_EN SDA b(/)
Register 25.26. I2C_COMD0_REG (0x0058)
I2C_COMMAND0_DONE
31 30
(reserved)
14 13
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2C_COMMAND0 0x00
0
Reset
I2C_COMMAND0 0 bop_code 0RSTART1WRITE 2READ3STOP4ENDbbyte_num back_check_enaack_exp ack ACK b I2C cmd b(/)
I2C_COMMAND0_DONE I2C 0 b(/)
644
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
GoBack
Register 25.27. I2C_COMD1_REG (0x005C)
I2C_COMMAND1_DONE
31 30
(reserved)
14 13
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2C_COMMAND1 0x00
0
Reset
I2C_COMMAND1 1 bop_code 0RSTART1WRITE 2READ3STOP4ENDbbyte_num back_check_enaack_exp ack ACK b I2C cmd b(/)
I2C_COMMAND1_DONE I2C 1 b(/)
Register 25.28. I2C_COMD2_REG (0x0060)
I2C_COMMAND2_DONE
31 30
(reserved)
14 13
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2C_COMMAND2 0x00
0
Reset
I2C_COMMAND2 2 bop_code 0RSTART1WRITE 2READ3STOP4ENDbbyte_num back_check_enaack_exp ack ACK b I2C cmd b(/)
I2C_COMMAND2_DONE I2C 2 b(/)
Register 25.29. I2C_COMD3_REG (0x0064)
I2C_COMMAND3_DONE
31 30
(reserved)
14 13
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2C_COMMAND3 0x00
0
Reset
I2C_COMMAND3 3 bop_code 0RSTART1WRITE 2READ3STOP4ENDbbyte_num back_check_enaack_exp ack ACK b I2C cmd b(/)
I2C_COMMAND3_DONE I2C 3 b(/)
645
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
GoBack
Register 25.30. I2C_COMD4_REG (0x0068)
I2C_COMMAND4_DONE
31 30
(reserved)
14 13
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2C_COMMAND4 0x00
0
Reset
I2C_COMMAND4 4 bop_code 0RSTART1WRITE 2READ3STOP4ENDbbyte_num back_check_enaack_exp ack ACK b I2C cmd b(/)
I2C_COMMAND4_DONE I2C 4 b(/)
Register 25.31. I2C_COMD5_REG (0x006C)
I2C_COMMAND5_DONE
31 30
(reserved)
14 13
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2C_COMMAND5 0x00
0
Reset
I2C_COMMAND5 5 bop_code 0RSTART1WRITE 2READ3STOP4ENDbbyte_num back_check_enaack_exp ack ACK b I2C cmd b(/)
I2C_COMMAND5_DONE I2C 5 b(/)
Register 25.32. I2C_COMD6_REG (0x0070)
I2C_COMMAND6_DONE
31 30
(reserved)
14 13
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2C_COMMAND6 0x00
0
Reset
I2C_COMMAND6 6 bop_code 0RSTART1WRITE 2READ3STOP4ENDbbyte_num back_check_enaack_exp ack ACK b I2C cmd b(/)
I2C_COMMAND6_DONE I2C 6 b(/)
646
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
GoBack
Register 25.33. I2C_COMD7_REG (0x0074)
I2C_COMMAND7_DONE
31 30
(reserved)
14 13
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2C_COMMAND7 0x00
0
Reset
I2C_COMMAND7 7 bop_code 0RSTART1WRITE 2READ3STOP4ENDbbyte_num back_check_enaack_exp ack ACK b I2C cmd b(/)
I2C_COMMAND7_DONE I2C 7 b(/)
Register 25.34. I2C_COMD8_REG (0x0078)
I2C_COMMAND8_DONE
31 30
(reserved)
14 13
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2C_COMMAND8 0x00
0
Reset
I2C_COMMAND8 8 bop_code 0RSTART1WRITE 2READ3STOP4ENDbbyte_num back_check_enaack_exp ack ACK b I2C cmd b(/)
I2C_COMMAND8_DONE I2C 8 b(/)
Register 25.35. I2C_COMD9_REG (0x007C)
I2C_COMMAND9_DONE
31 30
(reserved)
14 13
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2C_COMMAND9 0x00
0
Reset
I2C_COMMAND9 9 bop_code 0RSTART1WRITE 2READ3STOP4ENDbbyte_num back_check_enaack_exp ack ACK b I2C cmd b(/)
I2C_COMMAND9_DONE I2C 9 b(/)
647
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
GoBack
Register 25.36. I2C_COMD10_REG (0x0080)
I2C_COMMAND10_DONE
31 30
(reserved)
14 13
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2C_COMMAND10 0x00
0
Reset
I2C_COMMAND10 10 bop_code 0RSTART1WRITE 2READ3STOP4ENDbbyte_num back_check_enaack_exp ack ACK b I2C cmd b(/)
I2C_COMMAND10_DONE I2C 10 b(/)
Register 25.37. I2C_COMD11_REG (0x0084)
I2C_COMMAND11_DONE
31 30
(reserved)
14 13
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2C_COMMAND11 0x00
0
Reset
I2C_COMMAND11 11 bop_code 0RSTART1WRITE 2READ3STOP4ENDbbyte_num back_check_enaack_exp ack ACK b I2C cmd b(/)
I2C_COMMAND11_DONE I2C 11 b(/)
Register 25.38. I2C_COMD12_REG (0x0088)
I2C_COMMAND12_DONE
31 30
(reserved)
14 13
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2C_COMMAND12 0x00
0
Reset
I2C_COMMAND12 12 bop_code 0RSTART1WRITE 2READ3STOP4ENDbbyte_num back_check_enaack_exp ack ACK b I2C cmd b(/)
I2C_COMMAND12_DONE I2C 12 b(/)
648
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
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Register 25.39. I2C_COMD13_REG (0x008C)
I2C_COMMAND13_DONE
31 30
(reserved)
14 13
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2C_COMMAND13 0x00
0
Reset
I2C_COMMAND13 13 bop_code 0RSTART1WRITE 2READ3STOP4ENDbbyte_num back_check_enaack_exp ack ACK b I2C cmd b(/)
I2C_COMMAND13_DONE I2C 13 b(/)
Register 25.40. I2C_COMD14_REG (0x0090)
I2C_COMMAND14_DONE
31 30
(reserved)
14 13
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2C_COMMAND14 0x00
0
Reset
I2C_COMMAND14 14 bop_code 0RSTART1WRITE 2READ3STOP4ENDbbyte_num back_check_enaack_exp ack ACK b I2C cmd b(/)
I2C_COMMAND14_DONE I2C 14 b(/)
Register 25.41. I2C_COMD15_REG (0x0094)
I2C_COMMAND15_DONE
31 30
(reserved)
14 13
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2C_COMMAND15 0x00
0
Reset
I2C_COMMAND15 15 bop_code 0RSTART1WRITE 2READ3STOP4ENDbbyte_num back_check_enaack_exp ack ACK b I2C cmd b(/)
I2C_COMMAND15_DONE I2C 15 b(/)
649
ESP32-S2 TRM ( 1.3)
25 I2C (I2C)
Register 25.42. I2C_DATE_REG (0x00F8)
I2C_DATE
31
0x19052000
I2C_DATE b(/)
GoBack
0
Reset
650
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
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26
I2S (I2S)
26.1
I2S bESP32-S2 I2S I2S0b I2S BCKa WS SDb I2S bbESP32-S2 I2S b I2S ESP32-S2 I2S LCD Camera b
26.2
26.2-1. ESP32-S2 I2S
26.2-1 ESP32-S2 I2S bESP32-S2 I2S (TX control)a (RX control)a (I/O Timing)a (Clock Generator)a FIFO (TX FIFO) FIFO (RX FIFO)bTX/RX FIFO 64 x 32-bitbESP32-S2 I2S DMA RAM RAM cache DMA b DMA bESP32-S2 I2S I2S aLCD Camera b
I2S BCK WS SDb SD SD b BCK WS b
651
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
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LCD I2S0O_BCK_out LCD I2S0O_Data_out[23:0] LCD LCD b Camera
· I2S0I_V_SYNC Camera · I2S0I_H_SYNC Camera · I2S0I_H_ENABLE Camera · I2S0I_WS_in Camera · I2S0I_Data_in[15:0] Camera b 26.2-1 I2S bRX TX I2S0A_B_C I2S0I_BCK_inb · "A" I2S
"I" "O" · "B" BCK WS SD · "C" "in" I2S "out" I2S 26.2-1b
26.2-1.
I2S0I_BCK_in I2S0I_BCK_out I2S0I_WS_in I2S0I_WS_out
I2S0I_Data_in
I2S0O_Data_out
I2S0O_BCK_in I2S0O_BCK_out I2S0O_WS_in I2S0O_WS_out
I2S BCK RX I2S BCK RX I2S WS RX I2S WS RX I2S I2S0I_Data_in I2S Camera 16 b I2S I2S0O_Data_out I2S LCD 24 b I2S BCK TX I2S BCK TX I2S WS TX I2S WS TX
652
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
I2S0_CLK I2S0I_H_SYNC I2S0I_V_SYNC I2S0I_H_ENABLE
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Camera HSYNCaVSYNC HREF 26.11-1b
1. LCD/Camera / N I2S0I_Data_in[N-1:0] I2S0O_Data_out[23:23-N+1]b N = 8 j 16 N = 8 j 24b
2. I2S GPIO Padb 5 IO MUX GPIO b
26.3
I2S · · · TX RX · Philips I2S PCM MSB · 8 kHza16 kHza32 kHza44.1 kHza48 kHza88.2 kHza96 kHza128 kHz 192 kHzb 192 kHz 32 b · 8/16/24/32
LCD Camera · LCD 8 j 24 I2S LCD DMA * LCD 8 j 16 40 MHz * LCD 17 j 24 26.7 MHz I2S LCD EDMA RAM * LCD 8 25 MHz * LCD 9 j 16 12.5 MHz * LCD 17 j 24 6.25 MHz MOTO6800aI8080 LCD · Camerac DVP 8 j 16 I2S Camera DMA * 8 j 16 40 MHz I2S Camera EDMA RAM
653
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
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* 8 25 MHz * 9 j 16 12.5 MHz · LCD Camera DMA 80 b RAM EDMA 25 b I2S · I2S · I2S DMA b
26.4 I2S
ESP32-S2 I2S b
26.4.1 Philips
26.4-1. Philips
26.4-1 Philips BCK WS SD BCK WS BCK bSD b I2S_CONF_REG I2S_RX_MSB_SHIFT I2S_TX_MSB_SHIFT I2S Philips b
26.4.2 MSB
26.4-2. MSB
654
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
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26.4-2 MSB BCK WS SD bWS SD b I2S_CONF_REG I2S_RX_MSB_SHIFT I2S_TX_MSB_SHIFT I2S MSB b
26.4.3 PCM
26.4-3. PCM
26.4-3 PCM BCK WS SD BCK WS 1 BCK bSD b I2S_CONF_REG I2S_RX_SHORT_SYNC I2S_TX_SHORT_SYNC 1 I2S b
26.5 I2S
I2S0_CLK I2S 160 MHz PLL_F160M_CLK PLL APLL_CLK bI2S BCK I2S0_CLK 26.5-1 b I2S_CLKM_CONF_REG I2S_CLK_SEL[1:0] PLL_F160M_CLK APLL_CLK I2S0 I2S b
26.5-1. I2S
I2S0_CLK fi2s fI2S_CLK_S
fi2s
=
fI2S_CLK_S
N
+
b a
N>=2N I2S_CLKM_CONF_REG I2S_CLKM_DIV_NUM[7:0] · I2S_CLKM_DIV_NUM[7:0] = 0 N = 256 · I2S_CLKM_DIV_NUM[7:0] = 1 N = 2b · I2S_CLKM_DIV_NUM[7:0] N = I2S_CLKM_DIV_NUM[7:0] b
655
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
GoBack
b I2S_CLKM_DIV_B[5:0] a I2S_CLKM_DIV_A[5:0] bI2S_CLKM_DIV_A[5:0] I2S_CLKM_DIV_B[5:0] I2S_CLKM_DIV_B[5:0] I2S_CLKM_DIV_A[5:0] b
I2S BCK I2S0O_BCK_out I2S0_CLK b
fI2S0O_BCK_out
=
fi2s MO
MO I2S_SAMPLE_RATE_CONF_REG I2S_TX_BCK_DIV_NUM[5:0]
· I2S_TX_BCK_DIV_NUM[5:0] = 0 MO = 128
· I2S_TX_BCK_DIV_NUM[5:0] MO = I2S_TX_BCK_DIV_NUM[5:0] b
I2S_TX_BCK_DIV_NUM[5:0] 1b
I2S BCK I2S0I_BCK_out I2S0_CLK b
fI2S0I_BCK_out
=
fi2s MI
MI I2S_SAMPLE_RATE_CONF_REG I2S_RX_BCK_DIV_NUM[5:0]
· I2S_RX_BCK_DIV_NUM[5:0] = 0 MI 128
· I2S_RX_BCK_DIV_NUM[5:0] = 2 ~ 63 MI = I2S_RX_BCK_DIV_NUM[5:0] b
· I2S_RX_BCK_DIV_NUM[5:0] 1
· b I2S0_CLK BCK PLL_F160M_CLK APLL_CLK 6 b
· I2S fi2s >= 8 * fBCKb I2S0_CLK b
26.6 I2S
I2S I2S_CONF_REG · I2S TX/RX I2S_TX_RESET I2S_RX_RESET · I2S TX/RX FIFO I2S_TX_FIFO_RESET I2S_RX_FIFO_RESET b
I2S_CONF_REG I2S_TX_RESET_STaI2S_RX_RESET_STaI2S_TX_FIFO_RESET_ST I2S_RX_FIFO_RESET_ST
· 0 · 1b · I2S_TX_RESETaI2S_RX_RESETaI2S_TX_FIFO_RESET I2S_RX_FIFO_RESET · I2S_TX_RESET_STaI2S_RX_RESET_STaI2S_TX_FIFO_RESET_STa
I2S_RX_FIFO_RESET_ST
656
ESP32-S2 TRM ( 1.3)
26 I2S (I2S) FIFO I2S b
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26.7 I2S /
ESP32-S2 I2S b I2S_CONF_REG I2S_RX_SLAVE_MOD I2S_TX_SLAVE_MOD b
· I2S_TX_SLAVE_MOD 0 1
· I2S_RX_SLAVE_MOD 0 1
26.7.1 /
· I2S_CONF_REG I2S_TX_START b b I2S_TX_STOP_EN FIFO b I2S_TX_STOP_EN FIFO b I2S_TX_START b
· I2S_TX_STARTb BCK b I2S_TX_STOP_EN FIFO BCK b I2S_TX_STOP_EN FIFO b I2S_TX_START BCK b
26.7.2 /
· I2S_CONF_REG I2S_RX_START b b I2S_RX_STARTb
·
657
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
I2S_RX_STARTb BCK b
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26.8
26.4 ESP32-S2 I2S MSB b
ESP32-S2 I2S DMA I2S ESP32-S2 EDMA I2S RAM bESP32-S2 I2S
· TX FIFO
· TX FIFO 64 bit
· I2S LCD b
I2S_TX_FIFO_MODaI2S_TX_BITS_MOD[5:0]aI2S_TX_BIG_ENDIANa I2S_TX_MSB_RIGHTaI2S_TX_DMA_EQUALaI2S_TX_CHAN_MOD[2:0] I2S_TX_RIGHT_FIRST b
ESP32-S2 I2S WS 0 WS 1 b ESP32-S2 I2S D0c/aD1aD2aD3c/ /c D0aD2/c D1aD3b
26.8.1 I2S_TX_DMA_EQUAL = 0
I2S_TX_DMA_EQUAL = 0 26.8-1 b 26.8-1 Dn cn 0j3 Dn cn 0j3 I2S_TX_BIG_ENDIAN Dncn 0j3 Dn cn 0j3
I2S_TX_CHAN_MOD[2:0] TX Data2 single I2S_CONF_SINGLE_DATA_REG[31:0] bI2S_TX_BITS_MOD[5:0] 8a16a24a32 single I2S_CONF_SINGLE_DATA_REG[31:0] 8 a 16 a 24 a 32 b
I2S_TX_BIG_ENDIAN b 26.8-1 32a24a16 8 D0 {B3aB2aB1aB0}a{B2aB1aB0}a{B1aB0} B0 Dn cn 0j3 Dncn 0j3 26.8-1 b
658
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
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26.8-1. I2S_TX_DMA_EQUAL ESP32-S2 I2S
659
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
26.8-1.
I2S_TX_BITS_MOD[5:0] 32 24 16 8
I2S_TX_BIG_ENDIAN 0 1 0 1 0 1 -
Dn {B3aB2aB1aB0} {B0aB1aB2aB3} {B2aB1aB0} {B0aB1aB2} {B1aB0} {B0aB1} B0
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I2S_TX_MSB_RIGHT bI2S_TX_MSB_RIGHT I2S_TX_CHAN_MOD[2:0] bI2S_TX_RIGHT_FIRST b
26.8-1 I2S_TX_DMA_EQUAL 26.8-2 b I2S_TX_CHAN_MOD[2:0] = 0 I2S_TX_DMA_EQUAL = 0 26.8-2 b
26.8-2. I2S_TX_CHAN_MOD[2:0] = 0 I2S_TX_DMA_EQUAL = 0 ESP32-S2 I2S
660
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
GoBack
26.8-2. I2S_TX_DMA_EQUAL = 0
I2S_TX_CHAN_MOD[2:0]
0
1
2
3
4
I2S_TX_MSB_RIGHT = 0 c/ c/b I2S_TX_MSB_RIGHT = 1 //b I2S_TX_MSB_RIGHT = 0 a /b I2S_TX_MSB_RIGHT = 1 a /b I2S_TX_MSB_RIGHT = 0 a /b I2S_TX_MSB_RIGHT = 1 a /b I2S_TX_MSB_RIGHT = 0 single[31:0]/b I2S_TX_MSB_RIGHT = 1 single[31:0]/b I2S_TX_MSB_RIGHT = 0 / single[31:0]b I2S_TX_MSB_RIGHT = 1 / single[31:0]b
26.8.2 I2S_TX_DMA_EQUAL = 1
I2S_TX_DMA_EQUAL = 1 I2S I2S_TX_MSB_RIGHT b I2S_TX_CHAN_MOD[2:0] I2S_CONF_SINGLE_DATA_REG[31:0]bESP32-S2 I2S 26.8-3 26.8-3b
661
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
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26.8-3. I2S_TX_DMA_EQUAL = 1 ESP32-S2 I2S
26.8-3. I2S_TX_DMA_EQUAL = 1
I2S_TX_CHAN_MOD[2:0] 0/1/2 3 4
ab single[31:0]b single[31:0]b
662
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
GoBack
26.8.3 I2S
I2S 1. 26.5 b 2. 26.2-1 b 3. I2S_CONF2_REG I2S_LCD_EN I2S b 4. I2S_CONF_REG I2S_TX_SLAVE_MOD · 0 · 1 5. 26.8 I2S_TX_FIFO_MODaI2S_TX_BITS_MOD[5:0]aI2S_TX_BIG_ENDIANa I2S_TX_MSB_RIGHTaI2S_TX_DMA_EQUALaI2S_TX_CHAN_MOD[2:0] I2S_TX_RIGHT_FIRST b 6. I2S_FIFO_CONF_REG I2S_DSCR_EN I2S DMAb 7. 26.6 FIFOb 8. 26.12 b 9. DMA I2S_OUTLINK_START DMAb
10. I2S_TX_STOP_EN 26.7.1b 11.
· I2S I2S_TX_START · I2S_TX_START bI2S BCK WS b 12. 8 I2S_TX_IDLE · 0 · 1b 13. I2S_TX_STARTb
26.9
26.4 ESP32-S2 I2S MSB b
ESP32-S2 I2S WS 0 SD WS 1 SD b ESP32-S2 I2S D0c/aD1aD2aD3c/ b
I2S_RX_FIFO_MODaI2S_RX_BITS_MOD[5:0]aI2S_RX_BIG_ENDIANa I2S_RX_MSB_RIGHTaI2S_RX_DMA_EQUALaI2S_RX_CHAN_MOD[1:0] I2S_RX_RIGHT_FIRST b
663
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
GoBack
26.9.1 I2S_RX_DMA_EQUAL = 0
I2S_RX_DMA_EQUAL = 0 I2S RX b I2S_RX_CHAN_MOD[1:0] 26.9-1 b
26.9-1. I2S_RX_DMA_EQUAL = 0 ESP32-S2 I2S
26.9-1 Dn cn 0j3 Dn cn 0j3 I2S_RX_MSB_RIGHT bDncn 0j3 Dn cn 0j3 I2S_RX_BIG_ENDIAN bI2S_RX_BIG_ENDIAN 26.8-1b 26.9-1 I2S_RX_DMA_EQUAL ESP32-S2 I2S 26.9-2 26.9-1 b
664
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
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26.9-2. I2S_RX_DMA_EQUAL = 0 ESP32-S2 I2S
26.9-1. I2S_RX_DMA_EQUAL = 0
I2S_RX_MSB_RIGHT 0
1
I2S_RX_RIGHT_FIRST ESP32-S2 ESP32-S2 b I2S_RX_RIGHT_FIRST ESP32-S2 ESP32-S2 b
26.9.2 I2S_RX_DMA_EQUAL = 1
I2S_RX_DMA_EQUAL = 1 I2S b 26.9-3 26.9-2 b
665
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
GoBack
26.9-3. I2S_RX_DMA_EQUAL = 1 ESP32-S2 I2S
26.9-2. I2S_RX_DMA_EQUAL = 1
I2S_RX_MSB_RIGHT 0
1
I2S_RX_CHAN_MOD[2:0] 0/3 1 2 0/3 1 2
26.9.3 I2S
I2S 1. 26.5 b
666
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
GoBack
2. 26.2-1 b 3. I2S_CONF2_REG I2S_LCD_EN I2S_CAMERA_EN I2S b 4. I2S_CONF_REG I2S_RX_SLAVE_MOD
· 0 · 1 5. 26.9 I2S_RX_FIFO_MODaI2S_RX_DMA_EQUALaI2S_RX_BITS_MOD[5:0]a I2S_RX_BIG_ENDIANaI2S_RX_MSB_RIGHTaI2S_RX_CHAN_MOD[2:0] I2S_RX_RIGHT_FIRST b 6. I2S_FIFO_CONF_REG I2S_DSCR_EN I2S DMAb 7. 26.6 FIFOb 8. 26.12 b 9. DMA I2S_RXEOF_NUM_REG I2S_INLINK_START DMAb 10. · I2S_RX_START · I2S_RX_START BCK WS b 11. ESP32-S2 b 8 b
26.10 LCD
26.10.1
26.10-1 LCD LCD WR I2S WS 24 I2S_TX_BITS_MOD[5:0] 8/16/24 bLCD WS
fWS
=
fi2s W2
W>=1 I2S_SAMPLE_RATE_CONF_REG I2S_TX_BCK_DIV_NUM[5:0]
· I2S_TX_BCK_DIV_NUM[5:0] 0 W 64
· I2S_TX_BCK_DIV_NUM[5:0] 1 ~ 63 W I2S_TX_BCK_DIV_NUM[5:0] b
667
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
GoBack
26.10-1. LCD
26.10-2. LCD 1
26.10.2 LCD
ESP32-S2 I2S LCD 26.10-2
1. b 2. 26.2-1 26.10-1 b 3. I2S_CONF2_REG I2S_LCD_EN I2S_CONF_REG
I2S_TX_SLAVE_MOD LCD b 4. I2S_TX_DMA_EQUAL I2S_TX_RIGHT_FIRSTaI2S_LCD_TX_WRX2_ENa
I2S_LCD_TX_SDX2_EN I2S_TX_CHAN_MOD[2:0] b 5. 26.8 I2S_TX_BITS_MOD[5:0] I2S_TX_BIG_ENDIAN
b 6. I2S_FIFO_CONF_REG I2S_DSCR_EN I2S DMAb 7. 26.6 FIFOb 8. 26.12 b 9. DMA I2S_OUTLINK_START DMAb 10. LCD I2S_TX_STARTb 11. 8 I2S_TX_IDLE
· 0 · 1b 12. I2S_TX_STARTb LCD 26.10-3 b 26.10-2 I2S_LCD_TX_SDX2_ENb
668
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
GoBack
26.10-3. LCD 2
26.11 Camera
26.11.1
ESP32-S2 I2S Camera camera b I2S 16 I2S0I_Data_in[15:0] I2S0I_H_SYNCa I2S0I_V_SYNC I2S0I_H_ENABLE 26.11-1 b
26.11-1. Camera
NN = 8 ~ 16b
26.11.2 Camera
Camera 1. 26.5 bI2S fi2s I2S0I_WS_in PLL 2 b 2. 26.2-1 26.11-1 b 3. I2S_CONF2_REG I2S_LCD_EN I2S_CAMERA_EN Camera b 4. I2S_CONF_REG I2S_RX_SLAVE_MODb 5. I2S_RX_DMA_EQUAL 26.9 I2S_RX_BITS_MOD[5:0]a I2S_RX_BIG_ENDIANaI2S_RX_MSB_RIGHTaI2S_RX_CHAN_MOD[2:0] I2S_RX_RIGHT_FIRST b
669
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
GoBack
6. I2S_FIFO_CONF_REG I2S_DSCR_EN b 7. 26.6 FIFOb 8. 26.12 b 9. DMA I2S_RXEOF_NUM_REG I2S_INLINK_START
DMAb 10. I2S_RX_START transmission_start b 11. ESP32-S2 b 8 b Camera I2S0I_V_SYNC I2S0I_H_SYNC I2S0I_H_ENABLE I2S0I_V_SYNC Camera I2S
transmission_start = ((I2S0I_V _SY N C == 0)&&(I2S0I_H_SY N C == 1)&&(I2S0I_H_EN ABLE == 1)
transmission_start GPIO b 5 IO MUX GPIO b I2S0I_V_SYNC I2S_VSYNC_FILTER_EN I2S0I_V_SYNC b I2S_VSYNC_FILTER_THRES PCLK b b I2S0I_V_SYNC I2S_VSYNC_FILTER_THRES PCLK b Camera I2S0I_V_SYNC 8 PCLK I2S I2S0I_V_SYNC b
26.12 I2S
26.12.1 FIFO
· I2S_TX_HUNG_INTb · I2S_RX_HUNG_INTb · I2S_TX_REMPTY_INT FIFO b · I2S_TX_WFULL_INT FIFO b · I2S_RX_REMPTY_INT FIFO b · I2S_RX_WFULL_INT FIFO b · I2S_TX_PUT_DATA_INT FIFO I2S_TX_DATA_NUM[5:0] c
b · I2S_RX_TAKE_DATA_INT FIFO I2S_RX_DATA_NUM[5:0] c
b · I2S_V_SYNC_INT transmission_start I2S0I_V_SYNC
b
670
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
26.12.2 DMA
· I2S_OUT_TOTAL_EOF_INT: b · I2S_IN_DSCR_EMPTY_INT: b · I2S_OUT_DSCR_ERR_INT: b · I2S_IN_DSCR_ERR_INT: b · I2S_OUT_EOF_INT: b · I2S_OUT_DONE_INT: b · I2S_IN_SUC_EOF_INT: b · I2S_IN_DONE_INT: b
26.13
I2S 26.13-1 b
26.13-1. ESP32-S2 I2S
PeriBUS1 PeriBUS2
0x3F40F000 0x6000F000
GoBack
26.14
I2S_CONF_REG I2S_FIFO_CONF_REG I2S_CONF_SIGLE_DATA_REG I2S_CONF_CHAN_REG I2S_LC_HUNG_CONF_REG I2S_CONF1 _REG I2S_PD_CONF_REG I2S_CONF2_REG I2S_INT_RAW_REG I2S_INT_ST_REG I2S_INT_ENA_REG I2S_INT_CLR_REG I2S_TIMING_REG DMA
I2S I2S FIFO I2S I2S Hung I2S 1 I2S I2S 2
I2S
671
0x0008 0x0020 0x0028 0x002C 0x0074 0x00A0 0x00A4 0x00A8
/ / / / / / /
0x000C 0x0010 0x0014 0x0018
/
0x001C /
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
GoBack
I2S_RXEOF_NUM_REG I2S_OUT_LINK_REG I2S_IN_LINK_REG I2S_OUT_EOF_DES_ADDR_REG I2S_IN_EOF_DES_ADDR_REG I2S_OUT_EOF_BFR_DES_ADDR_REG I2S_INLINK_DSCR_REG I2S_INLINK_DSCR_BF0_REG I2S_INLINK_DSCR_BF1_REG I2S_OUTLINK_DSCR_REG I2S_OUTLINK_DSCR_BF0_REG I2S_OUTLINK_DSCR_BF1_REG I2S_LC_CONF_REG DMA I2S_LC_STATE0_REG I2S_LC_STATE1_REG I2S_STATE_REG I2S_CLKM_CONF_REG I2S_SAMPLE_RATE_CONF_REG I2S_DATE_REG
I2S DMA RX EOF I2S DMA TX I2S DMA RX EOF EOF EOF I2S DMA
I2S DMA TX I2S DMA RX I2S TX
I2S I2S
0x0024 0x0030 0x0034 0x0038 0x003C 0x0040 0x0048 0x004C 0x0050 0x0054 0x0058 0x005C 0x0060
/ / / /
0x006C 0x0070 0x00BC
0x00AC / 0x00B0 /
0x00FC /
672
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
26.15
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Register 26.1. I2S_CONF_REG (0x0008)
(reservedI2)S_RIX2_SR_ERISX2E_STB__TIGSIX2_T_SEB_NIPGDIR2_IAESEN__NRRDIEX2IAQ_SND__TEMIXN2A_S_D_EMTQ(XArU_e_ARsELeEQrS(vUrEeeATsdL_e)SrIv2TeSd_)SII2GS__LROIX2O_SPL_BSTAIXB2C__SKLF_SIRRBIX2S__TSFM__ITRDSIXSM2B_TS_AM__RDSRIIGMBX2H__SATMR_TIOGIX2NH_SOTM_ORIX2N_SOS_THIXO2_SRST_H_ROISX2RY_STNM__TCSSIX2BY_S_NM_SCSRHIBX2IF__STRS_TIHGIXI2HF_STTR__IGRFIX2HIR_STSS__TTLFIXAI2RV_SSES_T_LRAMIX2VO_SESD__TTMAIX2RO_STSD_TRAIX2R_STF_TIFIX2O_S_F_RIFREIOX2S__SERR_TTEEXSS_EERTTESET
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 Reset
I2S_TX_RESET 1bc I2S_RX_RESET 1bc I2S_TX_FIFO_RESET 1 TX FIFObc I2S_RX_FIFO_RESET 1 RX FIFObc I2S_TX_START 1bc/ I2S_RX_START 1bc/ I2S_TX_SLAVE_MOD 1bc/ I2S_RX_SLAVE_MOD 1bc/ I2S_TX_RIGHT_FIRST 1bc/ I2S_RX_RIGHT_FIRST 1bc/ I2S_TX_MSB_SHIFT 1 Phillips bc/ I2S_RX_MSB_SHIFT 1 Phillips bc/ I2S_TX_SHORT_SYNC 1 PCM bc/ I2S_RX_SHORT_SYNC 1 PCM bc/ I2S_TX_MONO 1bc/ I2S_RX_MONO 1bc/ I2S_TX_MSB_RIGHT 1 TX FIFO bc/ I2S_RX_MSB_RIGHT 1 RX FIFO bc/ I2S_SIG_LOOPBACK 1 WS BCK bc/
673
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
Register 26.1. I2S_CONF_REG (0x0008)
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I2S_TX_FIFO_RESET_ST I2S TX FIFO b1I2S_TX_FIFO_RESET b0 I2S_TX_FIFO_RESET bc
I2S_RX_FIFO_RESET_ST I2S RX FIFO b1I2S_RX_FIFO_RESET b0 I2S_RX_FIFO_RESET bc
I2S_TX_RESET_ST I2S TX b1I2S_TX_RESET b0I2S_TX_RESET bc
I2S_TX_DMA_EQUAL 1b0 bc/
I2S_RX_DMA_EQUAL 1b0 bc/
I2S_PRE_REQ_EN I2S bc/
I2S_TX_BIG_ENDIAN I2S TX bc/
I2S_RX_BIG_ENDIAN I2S RX bc/
I2S_RX_RESET_ST I2S RX b1I2S_RX_RESET b0I2S_RX_RESET bc
674
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
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Register 26.2. I2S_FIFO_CONF_REG (0x0020)
(reserved)
I2S_RIX2_SF_TIFXO__FMIFOIO2D_S_M_FROOXDR__CFFIEFO_ORE_CNME_OI2EDSN_TX_FIFIO2_SM_DOSDCR_EN
I2S_RX_DATA_NUM
31
21 20 19 18
16 15
13 12 11
65
0 0 0 0 0 0 0 0 0 0 00 0
0
0
1
32
I2S_RX_DATA_NUM
0
32
Reset
I2S_RX_DATA_NUM FIFO I2S_RX_DATA_NUM[5:0] c I2S_RX_TAKE_DATA_INT bc/
I2S_TX_DATA_NUM FIFO I2S_TX_DATA_NUM[5:0] c I2S_TX_PUT_DATA_INT bc/
I2S_DSCR_EN I2S DMA bc/
I2S_TX_FIFO_MOD TX FIFO b 08/16 bit 18/16 bit 224/32 bit 324/32 bit 4-7 TX FIFO I2S_TX_BITS_MOD a I2S_TX_CHAN_MOD / 26.8.3b
c/
I2S_RX_FIFO_MOD RX FIFO b 08/16 bit 18/16 bit 224/32 bit 324/32 bit 4-7 RX FIFO I2S_RX_BITS_MOD a I2S_RX_CHAN_MOD / 26.9.3b
c/
I2S_TX_FIFO_MOD_FORCE_EN 1bc/
I2S_RX_FIFO_MOD_FORCE_EN 1bc/
675
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
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Register 26.3. I2S_CONF_SIGLE_DATA_REG (0x0028)
I2S_SIGLE_DATA
31
0
0
Reset
I2S_SIGLE_DATA TX_CHAN_MOD I2S_TX_MSB_RIGHT bc/
Register 26.4. I2S_CONF_CHAN_REG (0x002C)
(reserved)
I2S_RX_CHANI_2SM_OTDX_CHAN_MOD
31
54
32
0
000000000000000000000000000 0
0
Reset
I2S_TX_CHAN_MOD I2S bc/ I2S_RX_CHAN_MOD I2S bc/
Register 26.5. I2S_LC_HUNG_CONF_REG (0x0074)
(reserved)
I2S_LC_FIFI2OS_T_ILMCE_OFUIFTO__ETNIMAEOUT_SHIFTI2S_LC_FIFO_TIMEOUT
31
12 11 10
87
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01
0
0x10
Reset
I2S_LC_FIFO_TIMEOUT FIFO hung I2S_TX_HUNG_INT I2S_RX_HUNG_INT bc/
I2S_LC_FIFO_TIMEOUT_SHIFT b APB_CLKb 88000/2I2S_LC_F IF O_T IMEOUT _SHIF T bc/
I2S_LC_FIFO_TIMEOUT_ENA FIFO bc/
676
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
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Register 26.6. I2S_CONF1 _REG (0x00A0)
(reserved)
I2S_TX_STOP_EN
(reserved)
31
987
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2S_TX_STOP_EN 1 TX FIFO BCK WS bc/
Register 26.7. I2S_PD_CONF_REG (0x00A4)
(reserved)
I2S_DI2MSA__DRI2MASMA___DRIC2MALSMAK____PRFIFL2AOOCSMR__C_MPIFEL2EO_CSMPR___UCMFFIEI2EFO_SMORP__C_DFFFEIOFO_ORPRC_CUFEEO__PRPCUDE_PD
31
76 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 Reset
I2S_FIFO_FORCE_PD FIFO bc/ I2S_FIFO_FORCE_PU FIFO bc/ I2S_PLC_MEM_FORCE_PD I2S bc/ I2S_PLC_MEM_FORCE_PU I2S bc/ I2S_DMA_RAM_FORCE_PD DMA FIFO bc/ I2S_DMA_RAM_FORCE_PU DMA FIFO bc/ I2S_DMA_RAM_CLK_FO DMA RAM bc/
677
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
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Register 26.8. I2S_CONF2_REG (0x00A8)
(reserved)
I2S_VSYNCI_2FSI_LTVIES2RYSN__TCCHI_A2RFMSEI_LS_TCCIEA2LRMSK____EILSNN(OYrTeONEsPCReB__rIv2VAFeASCIdFL_KO)ILD_C_RDEE(_NrSeEEsNeTrvedI2)S_LIC2DS__TLIXC2_DSS__DTCXXA2_MW_EERRNXA2__EENN
31
14 13
11 10 9 8 7 6 5 4
32 1 0
000000000000000000
0
0 0 0 0 0 0 0 0 0 0 0 Reset
I2S_CAMERA_EN camera bc/ I2S_LCD_TX_WRX2_EN LCD bc/ I2S_LCD_TX_SDX2_EN LCD cForm 2bc/ I2S_LCD_EN LCD bc/ I2S_INTER_VALID_EN Camera 4 2
Camera VGA bc/ I2S_CAM_SYNC_FIFO_RESET Camera FIFObc/ I2S_CAM_CLK_LOOPBACK I2S0I_WS_out PCLKbc/ I2S_VSYNC_FILTER_EN I2S VSYNC bc/ I2S_VSYNC_FILTER_THRES I2S VSYNC bc/
678
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
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Register 26.9. I2S_INT_RAW_REG (0x000C)
(reserved)
I2S_VI_2SSY_NOIC2U_STI__NTITNIO2__TSRDA_ALSOW_CI2UERSTO___FEID_NMI2SI_NPSCDTT_RS_YO_CIR_2UERAISRTN_W__RTEOE__R(OUIrRNReFTA_sT__WeI_NIDrNRIv2TOTAe_SN_WdR_ER)AI_NAIW2IW_NSST_U_INCIR2__ASDEW_OOTIFXN2__ESIH_N_UIRTNIN_X2TG_RS_H_A_RTWIUANIX2NWT_SG_R__RETIAMINX2W_TPSW_T_RFYRIAU_X2WIL_SNLR_T_ER_IIMNX2R_TSPAW__WTTRFYIXAU2__WSILNPL_TU_R_TIXNR__TADT_WAARKTAAEW__IDNATT_AR_AINWT_RAW
31
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2S_RX_TAKE_DATA_INT_RAW I2S_RX_TAKE_DATA_INT bc I2S_TX_PUT_DATA_INT_RAW I2S_TX_PUT_DATA_INT c I2S_RX_WFULL_INT_RAW I2S_RX_WFULL_INT c I2S_RX_REMPTY_INT_RAW I2S_RX_REMPTY_INT c I2S_TX_WFULL_INT_RAW I2S_TX_WFULL_INT c I2S_TX_REMPTY_INT_RAW I2S_TX_REMPTY_INT c I2S_RX_HUNG_INT_RAW I2S_RX_HUNG_INT c I2S_TX_HUNG_INT_RAW I2S_TX_HUNG_INT c I2S_IN_DONE_INT_RAW I2S_IN_DONE_INT c I2S_IN_SUC_EOF_INT_RAW I2S_IN_SUC_EOF_INT c I2S_OUT_DONE_INT_RAW I2S_OUT_DONE_INT c I2S_OUT_EOF_INT_RAW I2S_OUT_EOF_INT c I2S_IN_DSCR_ERR_INT_RAW I2S_IN_DSCR_ERR_INT c I2S_OUT_DSCR_ERR_INT_RAW I2S_OUT_DSCR_ERR_INT c I2S_IN_DSCR_EMPTY_INT_RAW I2S_IN_DSCR_EMPTY_INT c I2S_OUT_TOTAL_EOF_INT_RAW I2S_OUT_TOTAL_EOF_INT c I2S_V_SYNC_INT_RAW I2S_V_SYNC_INT c
679
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
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Register 26.10. I2S_INT_ST_REG (0x0010)
(reserved)
I2S_VI_2SSY_NOIC2U_STI__NTITNIO2__TSSDA_TLSO_CI2UERSTO___FEID_NMI2SI_NPSCDTT_RS_YO_CIS_2UETRISRTN___RTEOE__R(OUISrNReFTT_sT__eI_NIDrNSIv2TOTTe_SN_dS_ES)TI_TNI2I_NSST_U_INCIS2__TSDE_OOTIFXN2__ESIH_N_UIRTNIN_X2TG_SS_TH__STIUTNIX2NT_SG_R__SETITMINX2_TPSW_T_SFYRTIU_X2IL_SNLR_T_ER_IIMNX2S_TSTPW__TTSFYIXTU2__SILNPL_TU_R_TIXNS__TTDT_AASKTTAE__IDNATT_AS_TINT_ST
31
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2S_RX_TAKE_DATA_INT_ST I2S_RX_TAKE_DATA_INT c I2S_TX_PUT_DATA_INT_ST I2S_TX_PUT_DATA_INT c I2S_RX_WFULL_INT_ST I2S_RX_WFULL_INT c I2S_RX_REMPTY_INT_ST I2S_RX_REMPTY_INT c I2S_TX_WFULL_INT_ST I2S_TX_WFULL_INT c I2S_TX_REMPTY_INT_ST I2S_TX_REMPTY_INT c I2S_RX_HUNG_INT_ST I2S_RX_HUNG_INT c I2S_TX_HUNG_INT_ST I2S_TX_HUNG_INT c I2S_IN_DONE_INT_ST I2S_IN_DONE_INT c I2S_IN_SUC_EOF_INT_ST I2S_IN_SUC_EOF_INT c I2S_OUT_DONE_INT_ST I2S_OUT_DONE_INT c I2S_OUT_EOF_INT_ST I2S_OUT_EOF_INT c I2S_IN_DSCR_ERR_INT_ST I2S_IN_DSCR_ERR_INT c I2S_OUT_DSCR_ERR_INT_ST I2S_OUT_DSCR_ERR_INT c I2S_IN_DSCR_EMPTY_INT_ST I2S_IN_DSCR_EMPTY_INT c I2S_OUT_TOTAL_EOF_INT_ST I2S_OUT_TOTAL_EOF_INT c I2S_V_SYNC_INT_ST I2S_V_SYNC_INT c
680
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
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Register 26.11. I2S_INT_ENA_REG (0x0014)
(reserved)
I2S_VI_2SSY_NOIC2U_STI__NTITNIO2__TSEDA_NLSOA_CI2UERSTO___FEID_NMI2SI_NPSCDTT_RS_YO_CIE_2UERNISRTN_A__RTEOE__R(OUIrENReFTN_sT__AeI_NIDrNEIv2TONTe_SN_AdE_EE)NI_NNIA2IA_NSST_U_INCIE2__NSDEA_OOTIFXN2__ESIH_N_UIRTNIN_X2TG_ES_HN__ETIUANNIX2NAT_SG_R__EETINMNIX2A_TPSW_T_EFYRNIU_X2AIL_SNLR_T_ER_IIMNX2E_TSNPW__TATEFYIXNU2__ASILNPL_TU_R_TIXNE__TNDT_AAAEKTNAE__AIDNATT_AE_NINAT_ENA
31
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2S_RX_TAKE_DATA_INT_ENA I2S_RX_TAKE_DATA_INTbc/ I2S_TX_PUT_DATA_INT_ENA I2S_TX_PUT_DATA_INT bc/ I2S_RX_WFULL_INT_ENA I2S_RX_WFULL_INT bc/ I2S_RX_REMPTY_INT_ENA I2S_RX_REMPTY_INT bc/ I2S_TX_WFULL_INT_ENA I2S_TX_WFULL_INT bc/ I2S_TX_REMPTY_INT_ENA I2S_TX_REMPTY_INT bc/ I2S_RX_HUNG_INT_ENA I2S_RX_HUNG_INT bc/ I2S_TX_HUNG_INT_ENA I2S_TX_HUNG_INT bc/ I2S_IN_DONE_INT_ENA I2S_IN_DONE_INT bc/ I2S_IN_SUC_EOF_INT_ENA I2S_IN_SUC_EOF_INT bc/ I2S_OUT_DONE_INT_ENA I2S_OUT_DONE_INT bc/ I2S_OUT_EOF_INT_ENA I2S_OUT_EOF_INT bc/ I2S_IN_DSCR_ERR_INT_ENA I2S_IN_DSCR_ERR_INT bc/ I2S_OUT_DSCR_ERR_INT_ENA I2S_OUT_DSCR_ERR_INT bc/ I2S_IN_DSCR_EMPTY_INT_ENA I2S_IN_DSCR_EMPTY_INT bc/ I2S_OUT_TOTAL_EOF_INT_ENA I2S_OUT_TOTAL_EOF_INT bc/ I2S_V_SYNC_INT_ENA I2S_V_SYNC_INT bc/
681
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
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Register 26.12. I2S_INT_CLR_REG (0x0018)
(reserved)
I2S_VI_2SSY_NOIC2U_STI__NTITNIO2__TSCDA_LLSOR_CI2UERSTO___FEID_NMI2SI_NPSCDTT_RS_YO_CIC_2UERLISRTNR___RTEOE__R(OUICrNReFTL_sT__ReI_NIDrNCIv2TOTLe_SNR_dC_EC)LI_NLIR2IR_NSST_U_INCIC2__LSDER_OOTIFXN2__ESIH_N_UIRTNIN_X2TG_CS_H__LCTRIULNIXR2NT_SG_R__CETILMINX2R_TPSW_T_CFYRILU_X2RIL_SNLR_T_ER_IIMNX2C_TSPLW__RTCPFYILUU2_RSITLNL__TT_D_AIANCKTTELA_R__CDINLARTTA__CILNRT_CLR
31
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2S_TAKE_DATA_INT_CLR I2S_RX_TAKE_DATA_INT bc I2S_PUT_DATA_INT_CLR I2S_TX_PUT_DATA_INT bc I2S_RX_WFULL_INT_CLR I2S_RX_WFULL_INT bc I2S_RX_REMPTY_INT_CLR I2S_RX_REMPTY_INT bc I2S_TX_WFULL_INT_CLR I2S_TX_WFULL_INT bc I2S_TX_REMPTY_INT_CLR I2S_TX_REMPTY_INT bc I2S_RX_HUNG_INT_CLR I2S_RX_HUNG_INT bc I2S_TX_HUNG_INT_CLR I2S_TX_HUNG_INT bc I2S_IN_DONE_INT_CLR I2S_IN_DONE_INT bc I2S_IN_SUC_EOF_INT_CLR I2S_IN_SUC_EOF_INT bc I2S_OUT_DONE_INT_CLR I2S_OUT_DONE_INT bc I2S_OUT_EOF_INT_CLR I2S_OUT_EOF_INT bc I2S_IN_DSCR_ERR_INT_CLR I2S_IN_DSCR_ERR_INT bc I2S_OUT_DSCR_ERR_INT_CLR I2S_OUT_DSCR_ERR_INT bc I2S_IN_DSCR_EMPTY_INT_CLR I2S_IN_DSCR_EMPTY_INT bc I2S_OUT_TOTAL_EOF_INT_CLR I2S_OUT_TOTAL_EOF_INT bc I2S_V_SYNC_INT_CLR I2S_V_SYNC_INT bc
682
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
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Register 26.13. I2S_TIMING_REG (0x001C)
(reserved)
I2S_TX_BI2CSK__DIANT_AI2IN_SEV_NRAIX2B_SLD_ETS_XYD_NEDIC2LS_SAYS_YNWRCX__SBWCIK2_SO_RUXT__WDSEI2L_AOSY_UTTX__DSEDL_I2AOYSU_TT_X_DWELSAI_2YOSU_TTX__DBECLIKA2Y_SO_URTX__DSDEIL_2AISNY__RDXE_LWASYI2_SIN__RDXE_LBACYIK2_SI_NT_XD_WELSAI_2YISN__TDXE_LBACYK_IN_DELAY
31
25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
87
65
43
21
0
0 0 0 0 0 0 00 0 0 0 0
0
0
0
0
0
0
0
0
0 Reset
I2S_TX_BCK_IN_DELAY BCK I2S0_CLKbc/
· 0 1.5
· 1 2.5
· 2 3.5
· 3 4.5 b
I2S_TX_WS_IN_DELAY WS I2S0_CLKbc/
· 0 1.5
· 1 2.5
· 2 3.5
· 3 4.5 b
I2S_RX_BCK_IN_DELAY BCK I2S0_CLKbc/
· 0 1.5
· 1 2.5
· 2 3.5
· 3 4.5 b
I2S_RX_WS_IN_DELAY WS I2S0_CLKbc/
· 0 1.5
· 1 2.5
· 2 3.5
· 3 4.5 b
I2S_RX_SD_IN_DELAY SD I2S0_CLKbc/
· 0 1.5
· 1 2.5
· 2 3.5
· 3 4.5 b
683
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
Register 26.13. I2S_TIMING_REG (0x001C)
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I2S_TX_BCK_OUT_DELAY BCK I2S0_CLKbc/
· 0 0 · 1 1 · 2 2 · 3 3 b I2S_TX_WS_OUT_DELAY WS I2S0_CLKbc/ · 0 0 · 1 1 · 2 2 · 3 3 b I2S_TX_SD_OUT_DELAY SD I2S0_CLKbc/ · 0 0 · 1 1 · 2 2 · 3 3 b I2S_RX_WS_OUT_DELAY WS I2S0_CLKbc/ · 0 0 · 1 1 · 2 2 · 3 3 b I2S_RX_BCK_OUT_DELAY BCK I2S0_CLKbc/ · 0 0 · 1 1 · 2 2 · 3 3 b
684
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
Register 26.13. I2S_TIMING_REG (0x001C)
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I2S_TX_DSYNC_SW 1 (two flip-flop synchronizer)
bc/ · 0 · 1b
I2S_RX_DSYNC_SW 1 (two flip-flop synchronizer) bc/ · 0 · 1b
I2S_DATA_ENABLE_DELAY I2S0_CLKbc/ · 0 1.5 · 1 2.5 · 2 3.5 · 3 4.5 b
I2S_TX_BCK_IN_INV 1 BCK bc/
Register 26.14. I2S_RXEOF_NUM_REG (0x0024)
I2S_RX_EOF_NUM
31
0
64
Reset
I2S_RX_EOF_NUM I2S_RX_EOF_NUM[31:0] I2S_IN_SUC_EOF_INT bc/
685
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
Register 26.15. I2S_OUT_LINK_REG (0x0030)
(reserIv2eSd_)OI2UST_LOINI2UKST__LROINEUSKTT_ALSIRTNTAKR_TSTOP
31 30 29 28 27
(reserved)
20 19
0 0 0 00 0 0 0 0 0 0 0
I2S_OUTLINK_ADDR 0x000
I2S_OUTLINK_ADDR bc/ I2S_OUTLINK_STOP bc/ I2S_OUTLINK_START bc/ I2S_OUTLINK_RESTART 1bc/
Register 26.16. I2S_IN_LINK_REG (0x0034)
(reserIv2eSd_)INI2LSIN_KINI_2LRSINE_SKINT_ALSIRTNTAKR_TSTOP
31 30 29 28 27
(reserved)
20 19
0 0 0 00 0 0 0 0 0 0 0
I2S_INLINK_ADDR 0x000
I2S_INLINK_ADDR bc/ I2S_INLINK_STOP bc/ I2S_INLINK_START bc/ I2S_INLINK_RESTART bc/
Register 26.17. I2S_OUT_EOF_DES_ADDR_REG (0x0038)
I2S_OUT_EOF_DES_ADDR
31
0x000000
I2S_OUT_EOF_DES_ADDR EOF bc
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0
Reset
0
Reset
0
Reset
686
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
Register 26.18. I2S_IN_EOF_DES_ADDR_REG (0x003C)
I2S_IN_SUC_EOF_DES_ADDR
31
0x000000
I2S_IN_SUC_EOF_DES_ADDR EOF bc
GoBack
0
Reset
Register 26.19. I2S_OUT_EOF_BFR_DES_ADDR_REG (0x0040)
I2S_OUT_EOF_BFR_DES_ADDR
31
0x000000
I2S_OUT_EOF_BFR_DES_ADDR EOF bc
0
Reset
Register 26.20. I2S_INLINK_DSCR_REG (0x0048)
I2S_INLINK_DSCR
31
0
I2S_INLINK_DSCR c
0
Reset
687
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
Register 26.21. I2S_INLINK_DSCR_BF0_REG (0x004C)
I2S_INLINK_DSCR_BF0
31
0
I2S_INLINK_DSCR_BF0 c
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0
Reset
Register 26.22. I2S_INLINK_DSCR_BF1_REG (0x0050)
I2S_INLINK_DSCR_BF1
31
0
I2S_INLINK_DSCR_BF1 c
0
Reset
Register 26.23. I2S_OUTLINK_DSCR_REG (0x0054)
I2S_OUTLINK_DSCR
31
0
I2S_OUTLINK_DSCR c
0
Reset
Register 26.24. I2S_OUTLINK_DSCR_BF0_REG (0x0058)
I2S_OUTLINK_DSCR_BF0
31
0
I2S_OUTLINK_DSCR_BF0 c
0
Reset
688
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
Register 26.25. I2S_OUTLINK_DSCR_BF1_REG (0x005C)
I2S_OUTLINK_DSCR_BF1
31
0
I2S_OUTLINK_DSCR_BF1 c
GoBack
0
Reset
689
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
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Register 26.26. I2S_LC_CONF_REG (0x0060)
(reserved)
I2S_EXTI_2MS_EMMI2E_SMB_K_CT_IH2RSSEAIZC_NEOKSI_2U_OSTE_W_NIDNNI2ADETSRSA_C_ORIB2U_USTBR_DUSOS(TRUCr_eSTRsTE__eN_EBrEIvO2UNeSFRd__S)OMTI2U_OSTED__NEIANIU2_STLO_OO_OIW2UPSTR___TBALEAIOH2SCOSBTK_MPA__ITH2RESBSS_MTTO_I2UFSTIF__OIRN_S_RTRSSTT
31
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Reset
I2S_IN_RST DMA in-DMA FSMbc/ I2S_OUT_RST DMA out-DMA FSMbc/ I2S_AHBM_FIFO_RST DMA DMA AHB cmdFIFObc/ I2S_AHBM_RST DMA DMA AHB bc/ I2S_OUT_LOOP_TEST bc/ I2S_IN_LOOP_TEST bc/ I2S_OUT_AUTO_WRBACK 1 buffer
bc/ I2S_OUT_EOF_MODE DMA out EOF b1DMA FIFO
b0AHB FIFO bc/ I2S_OUTDSCR_BURST_EN DMA b1 burst
b0bc/ I2S_INDSCR_BURST_EN DMA b1 burst
0bc/ I2S_OUT_DATA_BURST_EN b1 burst 0
bc/ I2S_CHECK_OWNER owner bitbc/ I2S_MEM_TRANS_EN bc/ I2S_EXT_MEM_BK_SIZE DMA b016 b132 b264 b3
bc/
690
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
Register 26.27. I2S_LC_STATE0_REG (0x006C)
I2S_OI2UST__OEMUTP_TFYULL
31 30 29
00
I2S_OUTFIFO_CNT
23 22
I2S_OUT_STATI2ES_OUT_DSCR_STATE
20 19 18 17
0
0
0
I2S_OUTLINK_DSCR_ADDR 0x000
I2S_OUTLINK_DSCR_ADDR I2S DMA bc I2S_OUT_DSCR_STATE I2S DMA bc I2S_OUT_STATE I2S DMA bc I2S_OUTFIFO_CNT I2S DMA outFIFO bc I2S_OUT_FULL I2S DMA outFIFO bc I2S_OUT_EMPTY I2S DMA outFIFO bc
GoBack
0
Reset
I2S_INI2_SE_MINP_TFYULL
31 30 29
00
Register 26.28. I2S_LC_STATE1_REG (0x0070)
I2S_INFIFO_CNT_DEBUG I2S_IN_STATEI2S_IN_DSCR_STATE
23 22
20 19 18 17
0
0
0
I2S_INLINK_DSCR_ADDR 0x000
I2S_INLINK_DSCR_ADDR I2S DMA bc I2S_IN_DSCR_STATE I2S DMA bc I2S_IN_STATE I2S DMA bc I2S_INFIFO_CNT_DEBUG I2S DMA inFIFO bc I2S_IN_FULL I2S DMA inFIFO bc I2S_IN_EMPTY I2S DMA inFIFO bc
0
Reset
691
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
GoBack
Register 26.29. I2S_STATE_REG (0x00BC)
(reserved)
I2S_TX_IDLE
31
10
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset
I2S_TX_IDLE 1I2S TX b0I2S TX bc
Register 26.30. I2S_CLKM_CONF_REG (0x00AC)
(reserved)
I2S_CLKI_2SSE_LCLK_EN
I2S_CLKM_DIV_A
31
23 22 21 20 19
14 13
000000000 0 0
0x0
I2S_CLKM_DIV_B
87
0x0
I2S_CLKM_DIV_NUM
0
4
Reset
I2S_CLKM_DIV_NUM I2S bc/ I2S_CLKM_DIV_B bc/ I2S_CLKM_DIV_A bc/ I2S_CLK_EN bc/ I2S_CLK_SEL I2S b0 I2S b1 APLL_CLKb
2 PLL_160M_CLKb3 I2S bc/
Register 26.31. I2S_SAMPLE_RATE_CONF_REG (0x00B0)
(reserved)
31
24 23
00000000
I2S_RX_BITS_MOD
18 17
16
I2S_TX_BITS_MOD
12 11
16
I2S_RX_BCK_DIV_NUM
65
6
I2S_TX_BCK_DIV_NUM
0
6
Reset
I2S_TX_BCK_DIV_NUM BCK bc/
I2S_RX_BCK_DIV_NUM BCK bc/
I2S_TX_BITS_MOD 8a16a24a32 8a16a24a32 bc/
I2S_RX_BITS_MOD 8a16a24a32 8a16a24a32 bc/
692
ESP32-S2 TRM ( 1.3)
26 I2S (I2S)
Register 26.32. I2S_DATE_REG (0x00FC)
I2S_DATE
31
0x19052500
I2S_DATE c/
GoBack
0
Reset
693
ESP32-S2 TRM ( 1.3)
27 (PCNT)
GoBack
27
(PCNT)
(Pulse Count Controller, PCNT) bPCNT op b n 0~ 3 b cch0 ch1b 0 (ch0) b 27.0-1
1. c ctrl_ch0_un ch0 2. c sig_ch0_un ch0
27.0-1. PCNT
27.1
PCNT · c · · c sig_ch0_unc ctrl_ch0_un · csig_ch0_un sig_ch1_un cctrl_ch0_un ctrl_ch1_un
694
ESP32-S2 TRM ( 1.3)
27 (PCNT)
· 1. 2. ab
· 40 MHz
27.2
GoBack
27.2-1. PCNT
27.2-1 PCNT bctrl_ch0_un ch0 ctrl_ch0_un sig_ch0_un b
· sig_ch0_un pulse_cnt 1bpulse_cnt PCNT_CNT_H_LIM_Un b pulse_cnt PCNT_CNT_H_LIM_Un PCNT_CNT_PAUSE_Un pulse_cnt b
· sig_ch0_un pulse_cnt 1bpulse_cnt PCNT_CNT_L_LIM_Un b pulse_cnt PCNT_CNT_H_LIM_Un PCNT_CNT_PAUSE_Un pulse_cnt b
· pulse_cnt b
27.2-1 27.2-4 0 b
695
ESP32-S2 TRM ( 1.3)
27 (PCNT)
27.2-1.
PCNT_CH0_POS_MODE_Un 1
2
PCNT_CH0_LCTRL_MODE_Un 0 1 0 1 N/A
GoBack
27.2-2.
PCNT_CH0_POS_MODE_Un 1
2
PCNT_CH0_HCTRL_MODE_Un 0 1 0 1 N/A
27.2-3.
PCNT_CH0_NEG_MODE_Un 1
2
PCNT_CH0_LCTRL_MODE_Un 0 1 0 1 N/A
27.2-4.
PCNT_CH0_NEG_MODE_Un 1
2
PCNT_CH0_HCTRL_MODE_Un 0 1 0 1 N/A
b PCNT_FILTER_EN_Un
696
ESP32-S2 TRM ( 1.3)
27 (PCNT)
GoBack
b PCNT_FILTER_THRES_Un APB b
0 1 inc_dec b adder badder 16 b PCNT_CNT_PAUSE_Un adder PCNT_PULSE_CNT_RST_Un adderb
PCNT b
· : pulse_cnt PCNT_CNT_H_LIM_Un PCNT_CNT_THR_H_LIM_LAT_Un b
· : pulse_cnt PCNT_CNT_L_LIM_Un PCNT_CNT_THR_L_LIM_LAT_Un b
· : pulse_cnt PCNT_CNT_THRES0_Un PCNT_CNT_THRES1_Un PCNT_CNT_THR_THRES0_LAT_Un PCNT_CNT_THR_THRES1_LAT_Un b
· : pulse_cnt 0 PCNT_CNT_THR_ZERO_LAT_Un b
27.3
0 1 b 0 a 0 bc 1 a b
27.3.1 0
27.3-1. 0
27.3-1 0 sig_ch0_un 1 c 27.2 1b 0 b
· PCNT_CH0_LCTRL_MODE_Un=0 ctrl_ch0_un b · PCNT_CH0_HCTRL_MODE_Un=2 ctrl_ch0_un b · PCNT_CH0_POS_MODE_Un=1 sig_ch0_un b · PCNT_CH0_NEG_MODE_Un=0 sig_ch0_un b · PCNT_CNT_H_LIM_Un=5pulse_cnt PCNT_CNT_H_LIM_Un b
697
ESP32-S2 TRM ( 1.3)
27 (PCNT)
27.3.2 0
GoBack
27.3-2. 0 27.3-2 0 sig_ch0_un 1 b 0 27.3-1
· PCNT_CH0_POS_MODE_Un=2 sig_ch0_un b · PCNT_CNT_L_LIM_Un=-5pulse_cnt PCNT_CNT_L_LIM_Un b
27.3.3 0 1
27.3-3.
27.3-3 0 1 sig_ch0_un sig_ch1_un b 27.3-3 ctrl_ch0_un ctrl_ch1_un sig_ch0_un sig_ch1_un b
· 0 PCNT_CH0_LCTRL_MODE_Un=0 ctrl_ch0_un b PCNT_CH0_HCTRL_MODE_Un=2 ctrl_ch0_un b PCNT_CH0_POS_MODE_Un=1 sig_ch0_un b PCNT_CH0_NEG_MODE_Un=0 sig_ch0_un b
· 1 PCNT_CH1_LCTRL_MODE_Un=0 ctrl_ch1_un b PCNT_CH1_HCTRL_MODE_Un=2 ctrl_ch1_un b PCNT_CH1_POS_MODE_Un=1 sig_ch1_un b
698
ESP32-S2 TRM ( 1.3)
27 (PCNT)
PCNT_CH1_NEG_MODE_Un=0 sig_ch1_un b · PCNT_CNT_H_LIM_Un=10pulse_cnt PCNT_CNT_H_LIM_Un b
GoBack
27.4
PCNT 27.4-1 b 3 b
27.4-1. PCNT
PeriBUS1 PeriBUS2
0x3F417000 0x60017000
27.5
PCNT cb PCNT 27.4 b
PCNT_U0_CONF0_REG PCNT_U0_CONF1_REG PCNT_U0_CONF2_REG PCNT_U1_CONF0_REG PCNT_U1_CONF1_REG PCNT_U1_CONF2_REG PCNT_U2_CONF0_REG PCNT_U2_CONF1_REG PCNT_U2_CONF2_REG PCNT_U3_CONF0_REG PCNT_U3_CONF1_REG PCNT_U3_CONF2_REG PCNT_CTRL_REG PCNT_U0_CNT_REG PCNT_U1_CNT_REG PCNT_U2_CNT_REG PCNT_U3_CNT_REG PCNT_U0_STATUS_REG PCNT_U1_STATUS_REG PCNT_U2_STATUS_REG PCNT_U3_STATUS_REG
0 0 0 1 0 2 1 0 1 1 1 2 2 0 2 1 2 2 3 0 3 1 3 2
0 1 2 3 0 1 2 3
0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0060
/ / / / / / / / / / / / /
0x0030 0x0034 0x0038 0x003C 0x0050 0x0054 0x0058 0x005C
699
ESP32-S2 TRM ( 1.3)
27 (PCNT)
PCNT_INT_RAW_REG PCNT_INT_ST_REG PCNT_INT_ENA_REG PCNT_INT_CLR_REG PCNT_DATE_REG
GoBack
0x0040 0x0044 0x0048 0x004C
/
0x00FC /
700
ESP32-S2 TRM ( 1.3)
27 (PCNT)
GoBack
27.6
Register 27.1. PCNT_Un_CONF0_REG (n: 0-3) (0x0000+0xC*n)
PCNT_CH1_PLCCNTTR_LC_HM1O_PHDCCENT_TUR_L0C_HM1_POPCDONEST__U_MC0HO1D_PENC_ENUGT0__MCHO0DP_ECL_CNUTT0R_LC_HM0PO_CHDNCETT__RUCL0_HM0P_OCPDNOETS___UCM0PHOC0DN_ETN_P_EUTCGH0N_RTM_P_TOTCHHDNRRETE__P_STUTC1HH0N_RRETE_PN_STLC_0_HNU_LRT0IE_MP_NTHC__H_NEURLTN0I__M_ZFU_EI0LERTNOE__RUE_0NEN_U_U00
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0 0 1 1 1 1
PCNT_FILTER_THRES_U0
0
0x10
Reset
PCNT_FILTER_THRES_Un APB_CLK b b(/)
PCNT_FILTER_EN_Un n b(/) PCNT_THR_ZERO_EN_Un n b(/) PCNT_THR_H_LIM_EN_Un n b(/) PCNT_THR_L_LIM_EN_Un n b(/) PCNT_THR_THRES0_EN_Un n 0 b(/) PCNT_THR_THRES1_EN_Un n 1 b(/) PCNT_CH0_NEG_MODE_Un 0 b
120a3b(/) PCNT_CH0_POS_MODE_Un 0 b
120a3b(/) PCNT_CH0_HCTRL_MODE_Un CHn_POS_MODE
CHn_NEG_MODE b 01c2a3b(/) PCNT_CH0_LCTRL_MODE_Un CHn_POS_MODE CHn_NEG_MODE b 01c2a3b(/) PCNT_CH1_NEG_MODE_Un 1 b 120a3b(/) PCNT_CH1_POS_MODE_Un 1 b 120a3b(/) ...
701
ESP32-S2 TRM ( 1.3)
27 (PCNT) Register 27.1. PCNT_Un_CONF0_REG (n: 0-3) (0x0000+0xC*n)
GoBack
...
PCNT_CH1_HCTRL_MODE_Un CHn_POS_MODE CHn_NEG_MODE b
01c2a3b(/)
PCNT_CH1_LCTRL_MODE_Un CHn_POS_MODE CHn_NEG_MODE b
01c2a3b(/)
Register 27.2. PCNT_Un_CONF1_REG (n: 0-3) (0x0004+0xC*n)
PCNT_CNT_THRES1_U0
PCNT_CNT_THRES0_U0
31
16 15
0x00
0x00
PCNT_CNT_THRES0_Un n 0 b(/) PCNT_CNT_THRES1_Un n 1 b(/)
0
Reset
Register 27.3. PCNT_Un_CONF2_REG (n: 0-3) (0x0008+0xC*n)
PCNT_CNT_L_LIM_U0
PCNT_CNT_H_LIM_U0
31
16 15
0x00
0x00
PCNT_CNT_H_LIM_Un n b(/) PCNT_CNT_L_LIM_Un n b(/)
0
Reset
702
ESP32-S2 TRM ( 1.3)
27 (PCNT)
GoBack
Register 27.4. PCNT_CTRL_REG (0x0060)
(reserved)
PCNT_CLK_EN
(reserved)
PCNTP_CCNNTTP__CPPNAUUTLPSS_CEEC__NNCUTTN3P__CTPP_NAUURTLPSSS_TCEEC___NNUCUTT3N2P__CTPP_NAUURTLPSSS_TCEEC___NNUCUTT2N1__TPP_AUURLSSSTEE___UCU1N0T_RST_U0
31
17 16 15
87 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 Reset
PCNT_PULSE_CNT_RST_Un n b(/)
PCNT_CNT_PAUSE_Un n b(/)
PCNT_CLK_EN 1ab0 ab(/)
Register 27.5. PCNT_Un_CNT_REG (n: 0-3) (0x0030+0x4*n)
(reserved)
31
16 15
0000000000000000
PCNT_PULSE_CNT_U0 0x00
PCNT_PULSE_CNT_Un n b()
0
Reset
703
ESP32-S2 TRM ( 1.3)
27 (PCNT)
GoBack
Register 27.6. PCNT_Un_STATUS_REG (n: 0-3) (0x0050+0x4*n)
(reserved)
PCNTP_CCNNTTP__TCCHNNRTT_P__TZCCHENNRRTTO_P__TH_CCHL_NNARLTTTI___M_TLCU__HPN0LLRCTAI_MN_TTTT__HH_ULRRC0AE_TNST_T0HU__RT0LEHASRT1___ZLUEA0RT_OU_0MODE_U0
31
76 5 4 3 21
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 Reset
PCNT_CNT_THR_ZERO_MODE_Un PCNT_Un 0 b0 0b1 0b2b3b()
PCNT_CNT_THR_THRES1_LAT_Un PCNT_Un 1 b1 1 1 b0b()
PCNT_CNT_THR_THRES0_LAT_Un PCNT_Un 0 b1 0 0 b0b()
PCNT_CNT_THR_L_LIM_LAT_Un PCNT_Un b1 b0b()
PCNT_CNT_THR_H_LIM_LAT_Un PCNT_Un b1 b0b()
PCNT_CNT_THR_ZERO_LAT_Un PCNT_Un 0 b1 0 0 b0b()
Register 27.7. PCNT_INT_RAW_REG (0x0040)
(reserved)
PCNTP_CCNNTTP__TCCHNNRTT_P__TECCVHNNERTTN___TTEC_VHNUERTN3___TTE_IVHNUERTN2___TER_IVNAUEWTN1__TRI_NAUTW0_R_AINWT_RAW
31
43 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PCNT_CNT_THR_EVENT_Un_INT_RAW n b()
704
ESP32-S2 TRM ( 1.3)
27 (PCNT)
GoBack
Register 27.8. PCNT_INT_ST_REG (0x0044)
(reserved)
PCNTP_CCNNTTP__TCCHNNRTT_P__TECCVHNNERTTN___TTEC_VHNUERTN3___TTE_IVHNUERTN2___TES_IVTNUETN1__TSI_NTUT0_S_TINT_ST
31
43 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PCNT_CNT_THR_EVENT_Un_INT_ST n b()
Register 27.9. PCNT_INT_ENA_REG (0x0048)
(reserved)
PCNTP_CCNNTTP__TCCHNNRTT_P__TECCVHNNERTTN___TTEC_VHNUERTN3___TTE_IVHNUERTN2___TEE_IVNNUEATN1__TEI_NNUTA0_E_NINAT_ENA
31
43 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PCNT_CNT_THR_EVENT_Un_INT_ENA n b(/)
Register 27.10. PCNT_INT_CLR_REG (0x004C)
(reserved)
PCNTP_CCNNTTP__TCCHNNRTT_P__TECCVHNNERTTN___TTEC_VHNUERTN3___TTE_IVHNUERTN2___TEC_IVNLUERTN1__TCI_NLUTR0_C_LINRT_CLR
31
43 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PCNT_CNT_THR_EVENT_Un_INT_CLR n b()
705
ESP32-S2 TRM ( 1.3)
27 (PCNT)
Register 27.11. PCNT_DATE_REG (0x00FC)
PCNT_DATE
31
0x19072601
PCNT_DATE b(/)
GoBack
0
Reset
706
ESP32-S2 TRM ( 1.3)
28 USB OTG
GoBack
28
USB OTG
28.1
ESP32-S2 USB On-The-Go (OTG_FS) b OTG_FS USB 2.0 b (Full-Speed, FS) 12 Mbit/s (Low-Speed, LS) 1.5 Mbit/s (Host Negotiation Protocol, HNP) (Session Request Protocol, SRP)b
28.2
28.2.1
· · (HNP) (SRP) A B · FIFO (DFIFO) ·
Scatter/Gather DMA (Buffer) DMA Slave ·
28.2.2 (Device)
· 1 0c EP0 IN EP0 OUT · 6 (1 ~ 6) IN OUT · 5 IN c EP0 IN · OUT RX FIFO · IN TX FIFO
28.2.3 (Host)
· 8 c IN OUT IN OUT b
707
ESP32-S2 TRM ( 1.3)
28 USB OTG
GoBack
7 IN OUTaab · RX FIFOa TX FIFOa TX FIFOb FIFO b
28.3
28.3.1
28.3-1. OTG_FS
OTG_FS USB b 28.3-1 4
· CPU CPU FIFOb AHB b FIFO Slave b
· APB CPU USB (USB external controller) USB b
· DMA DMA c DMA b AHB b
· USB 2.0 USB 2.0 bESP32-S2 USB USB_WRAP_OTG_CONF USB_PHY_SEL ESP32-S2 GPIO b
· USB USB USB 2.0 bUSB cAHB , SPRAM b SRP b
· FIFO RAM FIFO SPRAMc RAMb FIFO SPRAM bCPUaDMA FIFOb
708
ESP32-S2 TRM ( 1.3)
28 USB OTG
GoBack
28.3.2
28.3-2 USB bUSB c wrap b
28.3-2.
28.3.2.1 & (CSR)
· CSR / OTG_FS c b OTG cHNPSRP A/B USB cPHY b CSR b
· CSR //b b
· CSR //b b
· b
709
ESP32-S2 TRM ( 1.3)
28 USB OTG
GoBack
28.3.2.2 FIFO
OTG_FS FIFO bFIFO c 28.3.3bFIFO DMA Slave Slave CPU DFIFO (push/pop) FIFObFIFO
· 4 KB RX FIFO (pop) b
· 4 KB TX FIFOc IN OUT b
IN TX FIFOb
TX FIFO TX FIFOb
· 128 KB /bb
Slave CPU FIFO b DMA DMA TX FIFO RX FIFO b
28.3.3 FIFO
OTG_FS FIFO cUSB bTX FIFO OUT IN bRX FIFO IN OUT b Slave RX FIFO b FIFO SPRAM 256×35 c35 32 3 bc c FIFO SPRAM b
28.3.3.1 FIFO
28.3-3 FIFO · TX FIFO OUT b · TX FIFO OUT b · RX FIFO IN /c b
FIFO b IN/OUT cb b FIFO b b USB b
· c 4 b · c 8 b b
710
ESP32-S2 TRM ( 1.3)
28 USB OTG
GoBack
28.3-3. FIFO
28.3-4. FIFO
28.3.3.2 FIFO
28.3-4 FIFO · RX FIFOcb
711
ESP32-S2 TRM ( 1.3)
28 USB OTG
GoBack
· TX FIFO IN TX FIFO IN c IN b
FIFObIN b
28.3.4
OTG_FS CPUb USB_GLBLINTRMSK bOTG_FS USB_GINTSTS_REG (OR) USB_GINTMSK_REG USB_GINTSTS_REG bUSB_GINTSTS_REG OTG bOTG_FS b
28.3-5. OTG_FS
USB_GINTSTS_REG
· USB_PRTINT bUSB_HPRT_REG b
· USB_HCHINT b USB_HAINT_REG USB_HCINTn_REG b
· USB_OEPINT OUT b USB_DAINT_REG OUT OUT USB_DOEPINTn_REG b
· USB_IEPINT IN b USB_DAINT_REG IN IN USB_DIEPINTn_REG b
712
ESP32-S2 TRM ( 1.3)
28 USB OTG
GoBack
· USB_OTGINT OTG b USB_GOTGINT_REG OTG b
28.3.5 DMA Slave
USB OTG 3 Scatter/Gather DMA a (Buffer) DMA Slave b
28.3.5.1 Slave
Slave FIFO FIFO CPU b · IN OUT TX FIFO b · USB_GRXSTSP_REG RX FIFO cb CPU RX FIFO c RX FIFO b
28.3.5.2 DMA
Slave DMA FIFO FIFO b · IN OUT USB_HCDMAn_REGc USB_DIEPDMAn_REGcb DMA TX FIFO b · OUT IN USB_HCDMAn_REGc USB_DOEPDMAn_REGcb DMA RX FIFO b
28.3.5.3 Scatter/Gather DMA
28.3-6. Scatter/Gather DMA
Scatter/Gather DMA b DMA b 32 32 (BufferStatus Quadlet)bc < 1 MPS c> 1 MPS bMPS (maximum packet size) b DMA b
713
ESP32-S2 TRM ( 1.3)
28 USB OTG
GoBack
· IN OUT /DMA TX FIFOb
· OUT IN /DMA RX FIFO DMA b
28.3.6
b
28.3.6.1 DMA
DMA b a STALL c3 b DMA b
DMA cb
28.3.6.2 Slave
Slave b USB c ACK NAKb Slave IN OUT b
28.3-1. Slave IN OUT
OUT
1. USB_HCTSIZn_REG c1 TX FIFO b
2. DWORD b
3. USB_XFERCOMPL b
c USB_H_NACKnb
1. USB_DIEPTSIZn_REG (1 MPS) c1 b b
2. RX FIFOb
3. c RX FIFO NAKb
IN
1. USB_HCTSIZn_REG c1 b
2. b
3. RX FIFObc USB_H_NACKnb
1. USB_DOEPTSIZn_REG c1 b b
2. USB_XFERCOMPL b
714
ESP32-S2 TRM ( 1.3)
28 USB OTG
GoBack
Slave DMA b FIFO b
Slave USB_HCTSIZn_REG USB_DOEPTSIZn_REG b TX FIFO RX FIFO cb
28.4 OTG
USB OTG OTG USB USB bOTG Mini-AB Micro-AB A-plug B-plugb OTG A-plug/B-plug A /B b
· A cA B cB b · (NHP)AaB A B b · A Vbus bB A Vbus A b
(SRP)b · Vbus A A b OTG ID A-plug B-plugbA-plug ID B-plug ID b
28.4.1 ID
USB_GOTGCTL_REG USB_CONIDSTS OTG A (1'b0) B (1'b1)b USB_CONIDSTS c USB_CONIDSTSCHNG b
28.4.2 OTG
OTG_FS OTG Revision 1.3 SRP HNP bOTG_FS UTMI+ OTG cbUTMI+ OTG c/ HNP
OTG OTG b UTMI+ OTG ESP32-S2 GPIOb 28.4-1 UTMI+ OTG b
28.4-1. UTMI OTG
usb_otg_iddig_in
usb_otg_avalid_in
I/O
A/B b mini-A mini-Bb
usb_otg_idpullup b
I
1'b0 mini-A
1'b1 mini-B
A b Vbus A b
I
1'b0: Vbus <0.8 V
1'b1: Vbus >2.0 V
715
ESP32-S2 TRM ( 1.3)
28 USB OTG
GoBack
I/O
B b Vbus B b
usb_otg_bvalid_in
I
1'b0: Vbus <0.8 V
1'b1: Vbus >4 V
Vbus b Vbus A/B /b
usb_otg_vbusvalid_in I
1'b0: Vbus <4.4 V
1'b1: Vbus >4.75 V
B b Vbus B b
usb_srp_sessend_in I
1'b0: Vbus >0.8 V
1'b1: Vbus <0.2 V
usb_otg_idpullup
ID b ID b O
1'b0: ID
1'b1: ID
usb_otg_dppulldown O D+ b D+ 15 k b
usb_otg_dmpulldown O D- b D- 15 k b
Vbusb Vbus 5 Vb
usb_otg_drvvbus
O 1'b0 Vbus
1'b1 Vbus
Vbus b PHY Vbus b
usb_srp_chrgvbus
O 1'b0 Vbus
1'b1 Vbus c 30 ms
Vbus b PHY Vbus b
usb_srp_dischrgvbus O 1'b0 Vbus
1'b1 Vbus c 50 ms
28.4.3 (SRP)
28.4.3.1 A SRP
28.4-1 OTG_FS A c Vbus SRP b
28.4-1. A SRP
716
ESP32-S2 TRM ( 1.3)
28 USB OTG
GoBack
1. cUSB_PRTSUSP 1'b0cUSB_PRTPWR 1'b0b
2. PHY usb_otg_vbusvalid_in b 3. Vbus A SE0 2 ms SRPb 4. SRPB 5 10 msbOTG_FS b 5. Vbus A c 2.0 V Vbus bOTF_FS SRP
b (USB_SESSREQINT) b 6.
bPHY usb_otg_vbusvalid_in b 7. USB B SRP b
28.4.3.2 B SRP
28.4-2 OTG_FS B c Vbus SRP b
28.4-2. B SRP
1. cA bPHY usb_otg_vbusvalid_in b 3 ms OTG_FS cUSB_ERLYSUSP 1bOTF_FS USB (USB_USBSUSP) 1bPHY usb_otg_bvalid_in B b
2. OTG_FS usb_otg_dischrgvbus PHY Vbus b
3. PHY usb_otg_sessend_in b SRP bOTG_FS SRP SE0 2 msb USB 2.0 USB_BSESVLD Vbus 0.2 Vb
4. 1.5 cTB_SE0_SRP OTG (USB_SESREQ) SRPbOTG_FS Vbus b
717
ESP32-S2 TRM ( 1.3)
28 USB OTG
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5. cA Vbus SRP VbusbPHY usb_otg_vbusvalid_in Vbus b
6. OTG_FS usb_srp_chrgvbus Vbus bcA Vbus SRP bOTG_FS OTG (USB_SESREQSC) b OTG b
7. USB OTG_FS SRP b
28.4.4 (HNP)
28.4.4.1 A HNP
28.4-3 OTG_FS A HNP b
28.4-3. A HNP
1. OTG_FS B SetFeature b_hnp_enable HNP bB ACK HNPb OTG HNP (USB_HSTSETHNPEN) OTG_FS B HNPb
2. (USB_PRTSUSP) b
3. B USB HNP bB HNPbOTG_FS OTG (USB_HSTNEGDET) HNP bOTG_FS usb_otg_dppulldown usb_otg_dmpulldown bPHY D+ B b OTG (USB_CURMOD_INT) b
4. B USB OTG_FS b
5. B bOTG_FS 3 ms (USB_ERLYSUSP) 1bOTG_FS USB (USB_USBSUSP) 1b
6. OTG_FS bOTG_FS usb_otg_dppulldown usb_otg_dmpulldown b
7. OTG_FS OTG ID (USB_CONIDSTS) b OTG ID OTG_FS A b HNPb OTG b
718
ESP32-S2 TRM ( 1.3)
28 USB OTG 8. B HNP b
28.4.4.2 B HNP
28.4-4 OTG_FS B HNP b
GoBack
28.4-4. B HNP
1. A SetFeature b_hnp_enable HNP bOTG_FS ACK HNPb OTG HNP (USB_DEVHNPEN) 1 HNPb OTG HNP (USB_DEVHNPEN) 1 OTG_FS HNPb
2. A b
(a) OTG_FS 3 ms (USB_ERLYSUSP) 1b OTG_FS USB (USB_USBSUSP) 1bOTG_FS A SE0 HNPb
(b) OTG_FS usb_otg_dppulldown usb_otg_dmpulldown b
(c) A SE0 3 ms D+ bOTG_FS b
(d) OTG_FS OTG (USB_CONIDSTS) 1 HNP b OTG (USB_HSTNEGSCS) b (USB_CURMOD_INT) b
3. USB_PRTPWR 1'b1 USB Vbusb
4. USB_PRTCONNDET bb
5. (USB_PRTRST) 1OTG_FS USB A b
6. USB_PRTENCHNG b
7. OTG_FS (USB_PRTSUSP) b
8. A bOTG_FS usb_otg_dppulldown usb_otg_dmpulldown b
719
ESP32-S2 TRM ( 1.3)
28 USB OTG
GoBack
9. (USB_CURMOD_INT)b 10. OTG_FS HNP b
28.5
28.5-1 USB OTG USB c wrap b 3 b
28.5-1. USB
USB USB
PeriBUS1 PeriBUS2 PeriBUS1 PeriBUS2
0x3F480000 0x60080000 0x3F439000 0x60039000
28.6
USB OTG IP (NDA) b Technical Inquires b
720
ESP32-S2 TRM ( 1.3)
29 (TWAI)
GoBack
29
(TWAI)
(Two-wire Automotive Interface, TWAI®) aa bTWAI c TWAI b ESP32-S2 TWAI TWAI bTWAI aab
29.1
ESP32-S2 TWAI · ISO 11898-1 cCAN 2.0 · c11-bit c29-bit · 1 Kbit/s ~ 1 Mbit/s · c c · 64-byte FIFO · c cTWAI · c ·
29.2
721
ESP32-S2 TRM ( 1.3)
29 (TWAI)
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29.2.1 TWAI
TWAI bTWAI
TWAI b cbTWAI (NRZ) b
0 1b bc b
TWAI bc b 5 b SOFaaa CRC c 29.2.2 b
b c 29.2.3 b
b b
TWAI bb
b
/b b
TWAI b b
TWAI b
· bb b
· b
29.2.2 TWAI
TWAI b b TWAI
· · · · · TWAI
722
ESP32-S2 TRM ( 1.3)
29 (TWAI)
GoBack
· (SFF) 11-bit · (EFF) 29-bit
29.2.2.1
0 ~ 8 b bb 29.2-1 b
29.2-1.
b bb
b 0 1:
· ID b
· ID RTR b
· ID 11 SRR b (DLC) DLC bDLC b
723
ESP32-S2 TRM ( 1.3)
29 (TWAI)
GoBack
bb
CRC CRC CRC bCRC 15-bit c SOF b
(ACK) b
29.2-1. SFF EFF
/ SOF Base ID
RTR
SRR IDE
Extd ID r1 r0 DLC
CRC CRC
EOF
(SOF) b (ID.28 ~ ID.18) SFF 11-bit EFF 29-bit 11-bitb (RTR) ccb b EFF (SRR) SFF RTR b (IED) SFF c EFFcb SFF EFF SFF EFF b (ID.17 ~ ID.0) EFF 29-bit 18-bitb r1c 1b r0c 0b (DLC) 4-bits 0 ~ 8 b DLC b DLC b b DLC b 0b CRC 15-bit b CRC CRC b b b b (EOF) b
29.2.2.2
b b b b
b CRC c 29.2.3 b 29.2-2
724
ESP32-S2 TRM ( 1.3)
29 (TWAI)
GoBack
29.2-2.
29.2-2.
: 6 6 cb b b 0 ~ 6 c b / 8 b
bb 29.2-3
29.2-3.
29.2-3.
6 bb b 8 bb
1. b 2. b 3. cb TEC REC c 29.2.3 b
· 1 b
725
ESP32-S2 TRM ( 1.3)
29 (TWAI)
GoBack
· 2a3 b · b
29.2.2.3
b caaabb
29.2-4
29.2-4.
29.2-4.
3 b 8 b b b SOF b SOF b
29.2.3 TWAI
29.2.3.1
TWAI
cc b b
6 cb
CRC CRC b CRC CRC b
br1 r0 b
b
726
ESP32-S2 TRM ( 1.3)
29 (TWAI)
GoBack
29.2.3.2
TWAI b (TEC) (REC)bTWAI b
b
b b
cb
29.2.3.3
TEC REC /bb 1. REC 1b b
2. REC 8b 3. TEC 8b
· TEC b
· TEC b
4. TEC 8b 5. REC 8b 6. / 7 bc
14 8 TEC 8 REC 8b 8 c TEC cREC 8b 7. c ACK EOF TEC 1 TEC 0b 8. c ACK REC b
· REC 1 ~ 127 1b · REC 127 127b · REC 0 0b 9. TEC / REC 128 b b REC 128 REC 128 b 10. TEC 256 b
727
ESP32-S2 TRM ( 1.3)
29 (TWAI)
GoBack
11. TEC REC 127b
12. 128 11 cTEC REC 0b
29.2.4 TWAI
29.2.4.1
TWAI TWAI bb · b · 1/b
(Time Quanta) b b 29.2-5 b TWAI TWAI b c-bPBS1 PBS2 b
29.2-5.
29.2-5.
(SS)
1 (PBS1) 2 (PBS2)
SSc 1 b b PBS1 1 ~ 16 b PBS1 b PBS2 1 ~ 8 b PBS2 b
29.2.4.2
bb TWAI b TQcoep SS b
· (e > 0)cb
· (e < 0)cb
728
ESP32-S2 TRM ( 1.3)
29 (TWAI)
GoBack
b
· b
· b c SOF b b
b (e > 0) PBS1 b (e < 0) PBS2 b
PBS1/PBS2 (SJW) b
· SJW PBS1/PBS2 / e b b
· SJW PBS1/PBS2 / SJW b b
29.3
29.3-1. TWAI ESP32-S2 TWAI b 29.3-1 TWAI b
729
ESP32-S2 TRM ( 1.3)
29 (TWAI)
GoBack
29.3.1
ESP32-S2 CPU 32-bit bTWAI (bits [7:0]) bbits [31:8] 0b
TWAI aab TWAI c 29.4.1 b
CPU TWAI b TWAI c 29.4.1 b
& TWAI cb TWAI b
b TEC REC b TWAI b
13 TWAI b
13 b FIFO FIFO b
ac 0x0040 ~ 0x0070b
· TWAI b
· TWAI
b
b
29.3.2
(BSP) ( CRC ) (BTL) bBSP BTL c CRC FIFObBSP TWAI (EML)b
29.3.3
(EML) TEC REC c BSP b TWAI bit b
730
ESP32-S2 TRM ( 1.3)
29 (TWAI)
GoBack
29.3.4
(BTL) bBTL b TQc b
29.3.5
TWAI b FIFO bab
29.3.6 FIFO
FIFO 64-byte c TWAI b FIFO c3 ~ 13 byte b FIFO c FIFO b FIFO 13-byte cb FIFO FIFO b
29.4
29.4.1
ESP32-S2 TWAI b TWAI_RESET_MODE 1 0b
29.4.1.1
TWAI bTWAI TWAI bTWAI cb bTWAI b
29.4.1.2
TWAI bTWAI c TWAI bTWAI
· TWAI cb · TWAI CRC
b TWAI b · TWAI TWAI bTWAI
abb TWAI b cTWAI 11 TWAI cb
731
ESP32-S2 TRM ( 1.3)
29 (TWAI)
GoBack
29.4.2
TWAI b TWAI_BUS_TIMING_0_REG TWAI_BUS_TIMING_1_REG 29.4-1 TWAI_BUS_TIMING_0_REG b
29.4-1. TWAI_CLOCK_DIVIDER_REG bit ; TWAI 0x18
Bit 31-16
Bit 15 SJW.1
Bit 14
Bit 13
Bit 12
......
SJW.0
BRP.13
BRP.12
......
Bit 1 BRP.1
Bit 0 BRP.0
· (BRP)TWAI APB APB 80 MHzb tT q tCLK APB tT q = 2 × tCLK × (213 × BRP.13 + 212 × BRP.12 + ... + 21 × BRP.1 + 20 × BRP.0 + 1)
· (SJW)SJW SJW.0 SJW.1 SJW = (2 x SJW.1 + SJW.0 + 1)b
29.4-2 TWAI_BUS_TIMING_1_REG b
29.4-2. TWAI_BUS_TIMING_1_REG bit ; TWAI 0x1c
Bit 31-8
Bit 7 SAM
Bit 6 PBS2.2
Bit 5 PBS2.1
Bit 4 PBS2.0
Bit 3 PBS1.3
Bit 2 PBS1.2
Bit 1 PBS1.1
Bit 0 PBS1.0
· PBS1: 1 (8 x PBS1.3 + 4 x PBS1.2 + 2 x PBS1.1 + PBS1.0 + 1)b
· PBS2: 2 (4 x PBS2.2 + 2 x PBS2.1 + PBS2.0 + 1)b
· SAM: 1 b/b
29.4.3
ESP32-S2 TWAI TWAI_INT_RAW_REG b TWAI_INT ENA_REG b TWAI
· · · · · · ·
732
ESP32-S2 TRM ( 1.3)
29 (TWAI)
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TWAI_INT_RAW_REG 1TWAI TWAI_INT_RAW_REG TWAI b TWAI_INT_RAW_REG b TWAI_RELEASE_BUF b
29.4.3.1 (RXI)
TWAI FIFO cTWAI_RX_MESSAGE_CNT_REG > 0 RXIb TWAI_RX_MESSAGE_CNT_REG FIFO b TWAI_RELEASE_BUF RXI b
29.4.3.2 (TXI)
TXIb TXI
· cbb · cTWAI_TX_COMPLETE b · TWAI_ABORT_TX b
29.4.3.3 (EWI)
TWAI_STATUS_REG TWAI_ERR_ST TWAI_BUS_OFF_ST c 0 1 EWIb EWI TWAI_ERR_ST TWAI_BUS_OFF_ST
· TWAI_ERR_ST = 0 TWAI_BUS_OFF_ST = 0
TWAI TEC REC TWAI_ERR_WARNING_LIMIT_REG b
TWAI b
· TWAI_ERR_ST = 1 TWAI_BUS_OFF_ST = 0 TEC REC TWAI_ERR_WARNING_LIMIT_REG b
· TWAI_ERR_ST = 1 TWAI_BUS_OFF_ST = 1 TWAI BUS_OFF c TEC >= 256b
· TWAI_ERR_ST = 0 TWAI_BUS_OFF_ST = 1 BUS_OFF TWAI TEC TWAI_ERR_WARNING_LIMIT_REG b
29.4.3.4 (DOI)
FIFO DOIbDOI FIFO b
FIFO DOIc FIFO b DOIbc DOIb
29.4.3.5 (TXI)
TWAI EPIb
733
ESP32-S2 TRM ( 1.3)
29 (TWAI)
GoBack
29.4.3.6 (ALI)
TWAI ALIbTWAI bit (TWAI_ARB LOST CAP_REG) bc CPU bit b
29.4.3.7 (BEI)
TWAI TWAI BEIb bit (TWAI_ERR_CODE_CAP_REG) bc CPU b
29.4.4
29.4.4.1
29.4-3. SFF EFF
(SFF) TWAI 0x40 0x44 0x48 0x4c 0x50 0x54 0x58 0x5c 0x60 0x64 0x68 0x6c 0x70
TX/RX TX/RX identifier 1 TX/RX identifier 2 TX/RX data byte 1 TX/RX data byte 2 TX/RX data byte 3 TX/RX data byte 4 TX/RX data byte 5 TX/RX data byte 6 TX/RX data byte 7 TX/RX data byte 8
(EFF) TWAI 0x40 0x44 0x48 0x4c 0x50 0x54 0x58 0x5c 0x60 0x64 0x68 0x6c 0x70
TX/RX TX/RX identifier 1 TX/RX identifier 2 TX/RX identifier 3 TX/RX identifier 4 TX/RX data byte 1 TX/RX data byte 2 TX/RX data byte 3 TX/RX data byte 4 TX/RX data byte 5 TX/RX data byte 6 TX/RX data byte 7 TX/RX data byte 8
29.4-3 b TWAI bCPU CPU b
TWAI bCPU a a ID cbCPU TWAI_CMD_REG TWAI_TX_REQ 1b
· TWAI_SELF_RX_REQ 1b
· TWAI_TX_REQ TWAI_ABORT_TX 1b
FIFO bCPU aa ID cbCPU
734
ESP32-S2 TRM ( 1.3)
29 (TWAI)
GoBack
TWAI_CMD_REG TWAI_RELEASE_BUF 1 FIFO b
29.4.4.2
1-byteab 29.4-4 b
29.4-4. TX/RX (SFF/EFF)TWAI 0x40
Bit 31-8 Bit 7
FF
Bit 6 RTR
Bit 5 X
Bit 4 X
Bit 3 XDLC.3
Bit 2 DLC.2
Bit 1 DLC.1
Bit 0 DLC.0
· FF: EFF SFFb FF 1 EFF FF 0 SFFb
· RTR: b RTR 1 RTR 0 b
· DLC: bTWAI 8 DLC 0 ~ 8b
· X: bitb
29.4.4.3
SFF 2-bytes (11-bits) EFF 4-bytes (29-bits)b Table 29.4-5-29.4-6 SFF (11-bits) b
29.4-5. TX/RX 1 (SFF); TWAI 0x44
Bit 31-8
Bit 7 ID.28
Bit 6 ID.27
Bit 5 ID.26
Bit 4 ID.25
Bit 3 ID.24
Bit 2 ID.23
Bit 1 ID.22
Bit 0 ID.21
29.4-6. TX/RX 2 (SFF); TWAI 0x48
Bit 31-8 Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ID.20
ID.19
ID.18
X1
X2
X2
X2
Bit 0 X2
29.4-7-29.4-10 EFF (29-bits) b 29.4-7. TX/RX 1 (EFF); TWAI 0x44
Bit 31-8
Bit 7 ID.28
Bit 6 ID.27
Bit 5 ID.26
Bit 4 ID.25
Bit 3 ID.24
Bit 2 ID.23
Bit 1 ID.22
Bit 0 ID.21
Bit 31-8 Bit 7
29.4-8. TX/RX 2 (EFF); TWAI 0x48
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
735
ESP32-S2 TRM ( 1.3)
29 (TWAI)
GoBack
ID.20
ID.19
ID.18
ID.17
ID.16
ID.15
ID.14
ID.13
Bit 31-8
Bit 7 ID.12
29.4-9. TX/RX 3 (EFF); TWAI 0x4c
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ID.11
ID.10
ID.9
ID.8
ID.7
ID.6
Bit 0 ID.5
Bit 31-8 Bit 7
ID.4
29.4-10. TX/RX 4 (EFF); TWAI 0x50
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ID.3
ID.2
ID.1
ID.0
X1
X2
Bit 0 X2
29.4.4.4
0 ~ 8 bytesb DLC b DLC 8 8bb 5 CPU DLC 5 1 ~ 5 b DLC 5 1 ~ 5 CPU b
29.4.5 FIFO
FIFO 64-bytes b FIFO 3 ~ 13 bytes b FIFO b TWAI TWAI_RX_MESSAGE_COUNTER 1 64b FIFO FIFO b TWAI_RELEASE_BUF 1 FIFO TWAI_RX_MESSAGE_COUNTER 1b FIFO b TWAI FIFO c FIFO FIFO b
· FIFO b FIFO b · FIFO b · TWAI_RX_MESSAGE_COUNTER 64b · FIFO b TWAI_MISS_ST
b
FIFO TWAI_RELEASE_BUF TWAI_RX_MESSAGE_COUNTER 0b FIFO b
736
ESP32-S2 TRM ( 1.3)
29 (TWAI)
GoBack
29.4.6
TWAI ID cb FIFO b TWAI c FIFO TWAI b
TWAI / b
32-bit Code 32-bit Mask bCode bMask Code c opb 29.4-1 ID Code Mask b
29.4-1.
TWAI 32-bit Code Mask c cb 32-bit code mask c
SFF EFFb
29.4.6.1
TWAI_RX_FILTER_MODE 1b32-bit code/mask b
· SFF 11-bit ID RTR bit 1 2
· EFF 29-bit ID RTR bit
29.4-2 32-bit code/mask b
29.4.6.2
TWAI_RX_FILTER_MODE 0b32-bit code/mask 1 2b b
737
ESP32-S2 TRM ( 1.3)
29 (TWAI)
GoBack
29.4-2.
· SFF 11-bit ID RTR bit 1 ( 1)
· EFF 29-bit ID 16-bit
29.4-3 32-bit code/mask b
29.4.7
TWAI TWAI (TEC) (REC)b TWAI caabTWAI TEC REC TWAI_TX_ERR_CNT_REG TWAI_RX_ERR_CNT_REG CPU b TWAI (EWL) TWAI b
TWAI TECaRECaTWAI_ERR_ST TWAI_BUS_OFF_STbc 29.4.3 b 29.4-4 ab
29.4.7.1
(EWL) TEC REC EWI bEWL TWAI TWAI bEWL TWAI_ERR_WARNING_LIMIT_REG TWAI b TWAI_ERR_WARNING_LIMIT_REG 96b
TEC / REC EWL TWAI_ERR_ST 1b TEC REC EWL TWAI_ERR_ST 0b TWAI_ERR_STc TWAI_BUS_OFF_ST b
738
ESP32-S2 TRM ( 1.3)
29 (TWAI)
GoBack
29.4-3.
29.4-4.
739
ESP32-S2 TRM ( 1.3)
29 (TWAI)
GoBack
29.4.7.2
TEC REC 127 TWAI b TEC REC 127 TWAI b TWAI b
29.4.7.3
TEC 255 TWAI bTWAI
· REC 0 · TEC 127 · TWAI_BUS_OFF_ST 1 · TWAI_BUS_OFF_ST c TWAI_ERR_ST b TWAI b b TWAI 128 11 b TWAI 11 TEC b cTEC 127 0TWAI_BUS_OFF_ST 0b
29.4.8
(ECC) TWAI TWAI bit b TWAI TWAI_ERR_CODE_CAP_REG b TWAI_ERR_CODE_CAP_REG b
29.4-11 TWAI_ERR_CODE_CAP_REG
29.4-11. TWAI_ERR_CODE_CAP_REG bit ; TWAI 0x30
Bit 31-8
Bit 7 ERRC.1
Bit 6
Bit 5
ERRC.0 DIR
Bit 4 SEG.4
Bit 3 SEG.3
Bit 2 SEG.2
Bit 1 SEG.1
Bit 0 SEG.0
· (ERRC)b00 01 10 11 b
· (DIR)TWAI b0 1 b
· (SEG) TWAI b
29.4-12 SEG.0 ~ SEG.4 b
740
ESP32-S2 TRM ( 1.3)
29 (TWAI)
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29.4-12. SEG.4 - SEG.0
Bit SEG.4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
Bit SEG.3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1
Bit SEG.2 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1
· Bit SRTR: RTR bitb · Bit IDE: b0 b
Bit SEG.1 1 1 1 0 0 1 1 1 0 0 0 1 1 0 0 0 1 1 1 0 1 1 1 0
Bit SEG.0 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 1 1 0 0 1 0 1 1 0
ID.28 ~ ID.21 ID.20 ~ ID.18 bit SRTR bit IDE ID.17 ~ ID.13 ID.12 ~ ID.5 ID.4 ~ ID.0 bit RTR 1 0 CRC CRC
29.4.9
(ALC) TWAI bit b TWAI bit TWAI_ARB LOST CAP_REG b
bit TWAI_ARB LOST CAP_REG TWAI_ERR_CODE_CAP_REG b
29.4-13 TWAI_ERR_CODE_CAP_REG 29.4-5 TWAI bit b
29.4-13. TWAI_ARB LOST CAP_REG ; TWAI 0x2c
Bit 31-5
Bit 4 BITNO.4
Bit 3 BITNO.3
Bit 2 BITNO.2
Bit 1 BITNO.1
Bit 0 BITNO.0
741
ESP32-S2 TRM ( 1.3)
29 (TWAI)
· (BITNO) TWAI n b
GoBack
29.4-5. bit
29.5
TWAI 29.5-1 b 3 b
29.5-1. TWAI
PeriBUS1 PeriBUS2
0x6002B000 0x3FC2B000
29.6
TWAI_MODE_REG TWAI_BUS_TIMING_0_REG TWAI_BUS_TIMING_1_REG TWAI_ERR_WARNING_LIMIT_REG TWAI_DATA_0_REG TWAI_DATA_1_REG TWAI_DATA_2_REG TWAI_DATA_3_REG TWAI_DATA_4_REG TWAI_DATA_5_REG TWAI_DATA_6_REG TWAI_DATA_7_REG TWAI_DATA_8_REG TWAI_DATA_9_REG TWAI_DATA_10_REG TWAI_DATA_11_REG
0 1 0 1 2 3 4 5 6 7 8 9 10 11
0x0000 0x0018 0x001C 0x0034 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 0x0058 0x005C 0x0060 0x0064 0x0068 0x006C
/ | / | / | / | / | / | / | / | / | / | / | / | | | |
742
ESP32-S2 TRM ( 1.3)
29 (TWAI)
TWAI_DATA_12_REG TWAI_CLOCK_DIVIDER_REG TWAI_CMD_REG TWAI_STATUS_REG TWAI_ARB LOST CAP_REG TWAI_ERR_CODE_CAP_REG TWAI_RX_ERR_CNT_REG TWAI_TX_ERR_CNT_REG TWAI_RX_MESSAGE_CNT_REG TWAI_INT_RAW_REG TWAI_INT ENA_REG
12
GoBack
0x0070 0x007C
|
0x0004
0x0008 0x002C 0x0030 0x0038 0x003C 0x0074
| / | /
0x000C 0x0010 /
29.7
Register 29.1. TWAI_MODE_REG (0x0000)
(reserved)
TWAI_TRWXA_IF_TISLWTEAELIFR_T__LWTMISEAOTSI_ETDRN_EEM_SOOENDTLE_YM_MOODDEE
31
43 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset
TWAI_RESET_MODE TWAI b10c/
TWAI_LISTEN_ONLY_MODE 1 bc/
TWAI_SELF_TEST_MODE 1 b bc/
TWAI_RX_FILTER_MODE b0: 1: c/
743
ESP32-S2 TRM ( 1.3)
29 (TWAI)
GoBack
Register 29.2. TWAI_BUS_TIMING_0_REG (0x0018)
(reserved)
TWAI_SYNC_JUMP_WIDTH
31
16 15 14 13
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0
TWAI_BAUD_PRESC 0x00
TWAI_BAUD_PRESC bc | / TWAI_SYNC_JUMP_WIDTH ( SJW ) 1 ~ 4 bc | /
0
Reset
Register 29.3. TWAI_BUS_TIMING_1_REG (0x001C)
(reserved)
TWAI_TIMET_WSAAMI_PTIME_SEG2 TWAI_TIME_SEG1
31
876
43
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00
0x0
0x0
Reset
TWAI_TIME_SEG1 1 bc | / TWAI_TIME_SEG2 2 bc | / TWAI_TIME_SAMP b0 1 1c | /
Register 29.4. TWAI_ERR_WARNING_LIMIT_REG (0x0034)
(reserved)
31
87
000000000000000000000000
TWAI_ERR_WARNING_LIMIT
0
0x60
Reset
TWAI_ERR_WARNING_LIMIT cbc | /
744
ESP32-S2 TRM ( 1.3)
29 (TWAI)
GoBack
Register 29.5. TWAI_DATA_0_REG (0x0040)
(reserved)
31
87
000000000000000000000000
TWAI_TX_BYTE_0 | TWAI_ACCEPTANCE_CODE_0
0
0x0
Reset
TWAI_TX_BYTE_0 0 bc TWAI_ACCEPTANCE_CODE_0 0 bc/
Register 29.6. TWAI_DATA_1_REG (0x0044)
(reserved)
31
87
000000000000000000000000
TWAI_TX_BYTE_1 | TWAI_ACCEPTANCE_CODE_1
0
0x0
Reset
TWAI_TX_BYTE_1 1 bc TWAI_ACCEPTANCE_CODE_1 1 bc/
745
ESP32-S2 TRM ( 1.3)
29 (TWAI)
GoBack
Register 29.7. TWAI_DATA_2_REG (0x0048)
(reserved)
31
87
000000000000000000000000
TWAI_TX_BYTE_2 | TWAI_ACCEPTANCE_CODE_2
0
0x0
Reset
TWAI_TX_BYTE_2 2 bc TWAI_ACCEPTANCE_CODE_2 2 bc/
Register 29.8. TWAI_DATA_3_REG (0x004C)
(reserved)
31
87
000000000000000000000000
TWAI_TX_BYTE_3 | TWAI_ACCEPTANCE_CODE_3
0
0x0
Reset
TWAI_TX_BYTE_3 3 bc TWAI_ACCEPTANCE_CODE_3 3 bc/
746
ESP32-S2 TRM ( 1.3)
29 (TWAI)
GoBack
Register 29.9. TWAI_DATA_4_REG (0x0050)
(reserved)
31
87
000000000000000000000000
TWAI_TX_BYTE_4 | TWAI_ACCEPTANCE_MASK_0
0
0x0
Reset
TWAI_TX_BYTE_4 4 bc TWAI_ACCEPTANCE_MASK_0 0 bc/
Register 29.10. TWAI_DATA_5_REG (0x0054)
(reserved)
31
87
000000000000000000000000
TWAI_TX_BYTE_5 | TWAI_ACCEPTANCE_MASK_1
0
0x0
Reset
TWAI_TX_BYTE_5 5 bc TWAI_ACCEPTANCE_MASK_1 1 bc/
747
ESP32-S2 TRM ( 1.3)
29 (TWAI)
GoBack
Register 29.11. TWAI_DATA_6_REG (0x0058)
(reserved)
31
87
000000000000000000000000
TWAI_TX_BYTE_6 | TWAI_ACCEPTANCE_MASK_2
0
0x0
Reset
TWAI_TX_BYTE_6 6 bc TWAI_ACCEPTANCE_MASK_2 2 bc/
Register 29.12. TWAI_DATA_7_REG (0x005C)
(reserved)
31
87
000000000000000000000000
TWAI_TX_BYTE_7 | TWAI_ACCEPTANCE_MASK_3
0
0x0
Reset
TWAI_TX_BYTE_7 7 bc TWAI_ACCEPTANCE_MASK_3 3 bc/
Register 29.13. TWAI_DATA_8_REG (0x0060)
(reserved)
31
87
000000000000000000000000
TWAI_TX_BYTE_8
0
0x0
Reset
TWAI_TX_BYTE_8 8 bc
748
ESP32-S2 TRM ( 1.3)
29 (TWAI)
GoBack
Register 29.14. TWAI_DATA_9_REG (0x0064)
(reserved)
31
87
000000000000000000000000
TWAI_TX_BYTE_9
0
0x0
Reset
TWAI_TX_BYTE_9 9 bc
Register 29.15. TWAI_DATA_10_REG (0x0068)
(reserved)
31
87
000000000000000000000000
TWAI_TX_BYTE_10
0
0x0
Reset
TWAI_TX_BYTE_10 10 bc
Register 29.16. TWAI_DATA_11_REG (0x006C)
(reserved)
31
87
000000000000000000000000
TWAI_TX_BYTE_11
0
0x0
Reset
TWAI_TX_BYTE_11 11 bc
Register 29.17. TWAI_DATA_12_REG (0x0070)
(reserved)
31
87
000000000000000000000000
TWAI_TX_BYTE_12
0
0x0
Reset
TWAI_TX_BYTE_12 12 bc
749
ESP32-S2 TRM ( 1.3)
29 (TWAI)
GoBack
Register 29.18. TWAI_CLOCK_DIVIDER_REG (0x007C)
(reserved)
TWAI_CLOCK_OFF
TWAI_CD
31
987
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00
0x0
0
Reset
TWAI_CD CLKOUT bc/
TWAI_CLOCK_OFF b1 CLKOUT 0 CLKOUT c | /
Register 29.19. TWAI_CMD_REG (0x0004)
(reserved)
TWAI_TSWEALIF_T_CWRLXAR_I__TRORWEVEQAELIRE_TARAWSUBEANO_I_RBTTUX__FTRXEQ
31
54 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TWAI_TX_REQ 1 bc TWAI_ABORT_TX 1 bc TWAI_RELEASE_BUF 1 bc TWAI_CLR_OVERRUN 1 bc TWAI_SELF_RX_REQ b 1 bc
750
ESP32-S2 TRM ( 1.3)
29 (TWAI)
GoBack
Register 29.20. TWAI_STATUS_REG (0x0008)
(reserved)
TWAI_TMWIASIS_T_BWSUTASI__TEOWRFARFI___TTSSWXTT_ASI_TTRWXA_IS_TTTWX_ACI_TOTWXM_APBI_LTUOEWFTV_AEEISR_TRRUX_NB_USTF_ST
31
98 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 Reset
TWAI_RX_BUF_ST 1bc
TWAI_OVERRUN_ST 1 FIFO bc TWAI_TX_BUF_ST 1bc TWAI_TX_COMPLETE 1bc TWAI_RX_ST 1bc TWAI_TX_ST 1bc TWAI_ERR_ST 1
TWAI_ERR_WARNING_LIMIT_REG c TWAI_BUS_OFF_ST 1bc TWAI_MISS_ST FIFO b1: 0
c
Register 29.21. TWAI_ARB LOST CAP_REG (0x002C)
(reserved)
31
54
000000000000000000000000000
TWAI_ARB_LOST_CAP bit bc
TWAI_ARB_LOST_CAP
0
0x0
Reset
751
ESP32-S2 TRM ( 1.3)
29 (TWAI)
GoBack
Register 29.22. TWAI_ERR_CODE_CAP_REG (0x0030)
(reserved)
TWAI_ECTCW_ATIY_PEECC_DIRETCWTIAOIN_ECC_SEGMENT
31
87
654
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0
0x0
Reset
TWAI_ECC_SEGMENT 29.4-11bc TWAI_ECC_DIRECTION b10
c
TWAI_ECC_TYPE 00011011-c
Register 29.23. TWAI_RX_ERR_CNT_REG (0x0038)
(reserved)
31
87
000000000000000000000000
TWAI_RX_ERR_CNT
0
0x0
Reset
TWAI_RX_ERR_CNT bc | /
Register 29.24. TWAI_TX_ERR_CNT_REG (0x003C)
(reserved)
31
87
000000000000000000000000
TWAI_TX_ERR_CNT
0
0x0
Reset
TWAI_TX_ERR_CNT bc | /
752
ESP32-S2 TRM ( 1.3)
29 (TWAI) Register 29.25. TWAI_RX_MESSAGE_CNT_REG (0x0074)
(reserved)
31
76
0000000000000000000000000
TWAI_RX_MESSAGE_COUNTER FIFO bc
GoBack
TWAI_RX_MESSAGE_COUNTER
0
0x0
Reset
Register 29.26. TWAI_INT_RAW_REG (0x000C)
(reserved)
TWAI_TBWUASI__TAEWRRABRI___(rEILeNORsTRSe_T_rTSv_PWTeIANdAST)IS__TIOVSWVETAE_IRI_NTREWTUR_ARNSI___TTWTIWNXAT_AR_IIN_NSRT_TX_IN_STITN_TS_TST
31
87 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TWAI_RX_INT_ST b 1 FIFO bc TWAI_TX_INT_ST b 1cb
TWAI_ERR_WARN_INT_ST b 1 c0 1 1 0bc
TWAI_OVERRUN_INT_ST b 1 FIFO bc TWAI_ERR_PASSIVE_INT_ST b 1
bc
TWAI_ARB_LOST_INT_ST b 1bc TWAI_BUS_ERR_INT_ST b 1bc
753
ESP32-S2 TRM ( 1.3)
29 (TWAI)
GoBack
Register 29.27. TWAI_INT ENA_REG (0x0010)
(reserved)
TWAI_TBWUASI__TAEWRRABRI___(rEILeNORsTRSe_T_rTEv_PWNeIANdAAST)IS__TIOVEWVENAE_AIRI_NTREWTUR_ARNEI___NTWTIWANXAT_AR_IIN_NERT_NX_INA_ETINN_ATE_NEANA
31
87 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TWAI_RX_INT_ENA 1 bc/ TWAI_TX_INT_ENA 1 bc/ TWAI_ERR_WARN_INT_ENA 1 bc/ TWAI_OVERRUN_INT_ENA 1 bc/ TWAI_ERR_PASSIVE_INT_ENA 1 bc/ TWAI_ARB_LOST_INT_ENA 1 bc/ TWAI_BUS_ERR_INT_ENA 1 bc/
754
ESP32-S2 TRM ( 1.3)
30 LED PWM (LEDC)
GoBack
30 LED PWM (LEDC)
30.1
LED PWM LED PWM b 14 b
30.2
LED PWM : · · 8 PWM · PWM b · PWM · PWM
PWM PWMn Timerxb
30.3
30.3.1
30.3-1 LED PWM b 30.3-2 PWM b
30.3.2
LED PWM LEDC_PWM_CLK APB_CLKaRC_FAST_CLK XTAL_CLK LEDC_APB_CLK_SEL[1:0] bLED PWM LEDC_CLKx LEDC_PWM_CLK REF_TICKb REF_TICK LEDC_APB_CLK_SEL[1:0] 1REF_TICK APB_CLK b b
LEDC_CLKx b LEDC_CLK_DIV_TIMERx b 10 A 8 Bb LEDC_CLK_DIVx
LE DC _C LK _DI V
x
=
A
+
B 256
B 0 30.3-3b256 B (A+1) (256-B) A b (A+1) B 256 b
755
ESP32-S2 TRM ( 1.3)
30 LED PWM (LEDC)
GoBack
30.3-1. LED_PWM
30.3-2. LED_PWM
LED PWM 14 2LEDC_T IMERx_DUT Y _RES - 1b 2LEDC_T IMERx_DUT Y _RES - 1 0 ba b LEDC_TIMERx_OVF_INT (LEDC_OVF_NUM_CHn + 1) b
1. LEDC_OVF_CNT_EN_CHn
2. LEDC_OVF_NUM_CHn 1
3. LEDC_OVF_CNT_CHn_INT_ENA
4. LEDC_TIMERx_DUTY_RES LEDC_OVF_CNT_CHn_INT
PWM sig_outn LEDC_CLKx a LEDC_CLK_DIVx c hyperref[fielddesc:LEDCTIMERXDUTYRES]LEDC_TIMERx_DUTY_RES
PWM sig_outn
fsig_outn
=
fLEDC_CLKx LEDC_CLK_DIVx · 2hyperref [f ielddesc:LEDCT IMERXDUT Y RES]LEDC_T IMERx_DUT Y _RES
756
ESP32-S2 TRM ( 1.3)
30 LED PWM (LEDC)
GoBack
30.3-3. LED_PWM
hyperref[fielddesc:LEDCTIMERXDUTYRES]LEDC_TIMERx_DUTY_RES = log2
fLEDC_CLKx fsig_outn · LEDC_CLK_DIVx
30.3-1 b
30.3-1.
LEDC_CLKx
PWM c1 c2
APB_CLK (80 MHz)
1 kHz
14
7
APB_CLK (80 MHz)
5 kHz
13
4
APB_CLK (80 MHz)
10 kHz
12
3
RC_FAST_CLK (8 MHz) 1 kHz
12
3
RC_FAST_CLK (8 MHz) 2 kHz
11
2
REF_TICK (1 MHz)
1 kHz
9
1
1 LEDC_CLK_DIVx 1 b
14 14b
2
LEDC_CLK_DIVx
1023
+
255 256
b 0 1b
LEDC_CLK_DIV_TIMERx LEDC_TIMERx_DUTY_RES LEDC_TIMERx_PARA_UPb b
30.3.3 PWM
30.3-2 PWM bPWM LED PWM 14 Hpointn Lpointn PWM b
· Timerx_cnt == Hpointn sig_outn 1b · Timerx_cnt == Lpointn sig_outn 0b
757
ESP32-S2 TRM ( 1.3)
30 LED PWM (LEDC)
GoBack
Hpointn LEDC_HPOINT_CHn bLpointn LEDC_DUTY_CHn[18..4] LEDC_HPOINT_CHn b PWM b
30.3-4 PWM b
30.3-4. LED_PWM
LEDC_DUTY_CHn bLEDC_DUTY_CHn[18..4] PWM bLEDC_DUTY_CHn[3..0] b LEDC_DUTY_CHn[3..0] 0 sig_outn 16 LEDC_DUTY_CHn[3..0] PWM (16 LEDC_DUTY_CHn[3..0]) b PWM 18 b
30.3.4
LED PWM b LEDC_DUTY_CHna LEDC_DUTY_START_CHnaLEDC_DUTY_INC_CHn aLEDC_DUTY_NUM_CHn LEDC_DUTY_SCALE_CHn b
LEDC_DUTY_START_CHn Lpointn b Lpointn b LEDC_DUTY_INC_CHn b
sig_outn LEDC_DUTY_CYCLE_CHn PWM LEDC_DUTY_SCALE_CHnb
LEDC_DUTY_NUM_CHn LEDC_DUTY_CHNG_END_CHn_INTb 30.3-5b LEDC_DUTY_CYCLE_CHn PWM sig_outn LEDC_DUTY_SCALE_CHnb
30.3-5.
LEDC_SIG_OUT_EN_CHn PWM bLEDC_SIG_OUT_EN_CHn 0 sig_outn LEDC_IDLE_LV_CHnb
758
ESP32-S2 TRM ( 1.3)
30 LED PWM (LEDC)
LEDC_HPOINT_CHnaLEDC_DUTY_START_CHnaLEDC_SIG_OUT_EN_CHna LEDC_TIMER_SEL_CHna LEDC_DUTY_NUM_CHnaLEDC_DUTY_CYCLE_CHnaLEDC_DUTY_SCALE_CHna LEDC_DUTY_INC_CHn LEDC_OVF_CNT_EN_CHn LEDC_PARA_UP_CHn b
30.3.5
· LEDC_OVF_CNT_CHn_INT (LEDC_OVF_NUM_CHn + 1) LEDC_OVF_CNT_EN_CHn 1 b
· LEDC_DUTY_CHNG_END_CHn_INTLED PWM b · LEDC_TIMERx_OVF_INTLED PWM b
GoBack
30.4
LED PWM 30.4-1 b 3 b
30.4-1. LED PWM
PeriBUS1 PeriBUS2
0x3F419000 0x60019000
30.5
LED PWM cb 30.4 LED PWM b LED PWM cb LED PWM 30.4 b
LEDC_CH0_CONF0_REG LEDC_CH0_CONF1_REG LEDC_CH1_CONF0_REG LEDC_CH1_CONF1_REG LEDC_CH2_CONF0_REG LEDC_CH2_CONF1_REG LEDC_CH3_CONF0_REG LEDC_CH3_CONF1_REG LEDC_CH4_CONF0_REG LEDC_CH4_CONF1_REG LEDC_CH5_CONF0_REG LEDC_CH5_CONF1_REG
0 0 0 1 1 0 1 1 2 0 2 1 3 0 3 1 4 0 4 1 5 0 5 1
0x0000 0x000C 0x0014 0x0020 0x0028 0x0034 0x003C 0x0048 0x0050 0x005C 0x0064 0x0070
/ / / / / /
759
ESP32-S2 TRM ( 1.3)
30 LED PWM (LEDC)
LEDC_CH6_CONF0_REG LEDC_CH6_CONF1_REG LEDC_CH7_CONF0_REG LEDC_CH7_CONF1_REG LEDC_CONF_REG LEDC_CH0_HPOINT_REG LEDC_CH1_HPOINT_REG LEDC_CH2_HPOINT_REG LEDC_CH3_HPOINT_REG LEDC_CH4_HPOINT_REG LEDC_CH5_HPOINT_REG LEDC_CH6_HPOINT_REG LEDC_CH7_HPOINT_REG LEDC_CH0_DUTY_REG LEDC_CH0_DUTY_R_REG LEDC_CH1_DUTY_REG LEDC_CH1_DUTY_R_REG LEDC_CH2_DUTY_REG LEDC_CH2_DUTY_R_REG LEDC_CH3_DUTY_REG LEDC_CH3_DUTY_R_REG LEDC_CH4_DUTY_REG LEDC_CH4_DUTY_R_REG LEDC_CH5_DUTY_REG LEDC_CH5_DUTY_R_REG LEDC_CH6_DUTY_REG LEDC_CH6_DUTY_R_REG LEDC_CH7_DUTY_REG LEDC_CH7_DUTY_R_REG LEDC_TIMER0_CONF_REG LEDC_TIMER0_VALUE_REG LEDC_TIMER1_CONF_REG LEDC_TIMER1_VALUE_REG LEDC_TIMER2_CONF_REG LEDC_TIMER2_VALUE_REG LEDC_TIMER3_CONF_REG LEDC_TIMER3_VALUE_REG LEDC_INT_RAW_REG LEDC_INT_ST_REG
6 0 6 1 7 0 7 1 LEDC
0 1 2 3 4 5 6 7
0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7
0 0 1 1 2 2 3 3
760
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0x0078 0x0084 0x008C 0x0098 0x00D0
/ / /
0x0004 0x0018 0x002C 0x0040 0x0054 0x0068 0x007C 0x0090
/ / / / / / / /
0x0008 0x0010 0x001C 0x0024 0x0030 0x0038 0x0044 0x004C 0x0058 0x0060 0x006C 0x0074 0x0080 0x0088 0x0094 0x009C
/ / / / / / / /
0x00A0 0x00A4 0x00A8 0x00AC 0x00B0 0x00B4 0x00B8 0x00BC
0x00C0 0x00C4
ESP32-S2 TRM ( 1.3)
30 LED PWM (LEDC)
LEDC_INT_ENA_REG LEDC_INT_CLR_REG LEDC_DATE_REG
GoBack
0x00C8 0x00CC
/
0x00FC /
30.6
Register 30.1. LEDC_CHn_CONF0_REG (n: 0-7) (0x0000+0x14*n)
(reserved)
LEDC_LEODVCF__LCEODNVCFT___CRONEVSFTE__TCR_NESSTTE__TEC_NHC_nHCnHn
LEDC_OVF_NUM_CHn
LEDC_LEPDARCA_L_EIDUDLPCE___CSLHVILG_nE_CDOHCUn_TT_IMENER__CSHEnL_CHn
31
18 17 16 15 14
54 3 21
0
0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0
0x0
0 0 0 0x0 Reset
LEDC_TIMER_SEL_CHn n b 0 0b 1 1b 2 2b 3 3b()
LEDC_SIG_OUT_EN_CHn n b() LEDC_IDLE_LV_CHn n b() LEDC_PARA_UP_CHn n LEDC_CHn_HPOINT LEDC_CHn_DUTY b()
LEDC_OVF_NUM_CHn 1b n (LEDC_OVF_NUM_CHn +1) LEDC_OVF_CNT_CHn_INT b()
LEDC_OVF_CNT_EN_CHn n ovf_cntb() LEDC_OVF_CNT_RESET_CHn n ovf_cntb() LEDC_OVF_CNT_RESET_ST_CHn LEDC_OVF_CNT_RESET_CHn b()
761
ESP32-S2 TRM ( 1.3)
30 LED PWM (LEDC)
GoBack
Register 30.2. LEDC_CHn_CONF1_REG (n: 0-7) (0x000C+0x14*n)
LEDC_LEDDUCT_YD_SUTTAYR_TIN_CCH_CnHn
31 30 29
01
LEDC_DUTY_NUM_CHn
20 19
0x0
LEDC_DUTY_CYCLE_CHn
10 9
0x0
LEDC_DUTY_SCALE_CHn
0
0x0
Reset
LEDC_DUTY_SCALE_CHn n b() LEDC_DUTY_CYCLE_CHn n LEDC_DUTY_CYCLE_CHn b() LEDC_DUTY_NUM_CHn b() LEDC_DUTY_INC_CHn n b10b() LEDC_DUTY_START_CHn 1 LEDC_CHn_CONF1_REG b()
Register 30.3. LEDC_CONF_REG (0x00D0)
LEDC_CLK_EN
31 30
(reserved)
LEDC_APB_CLK_SEL
21
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 Reset
LEDC_APB_CLK_SEL 4 b1APB_CLK2RTC8M_CLK3XTAL_CLKb ()
LEDC_CLK_EN b1b0b( )
Register 30.4. LEDC_CHn_HPOINT_REG (n: 0-7) (0x0004+0x14*n)
(reserved)
31
14 13
000000000000000000
LEDC_HPOINT_CHn 0x00
LEDC_HPOINT_CHn b()
0
Reset
762
ESP32-S2 TRM ( 1.3)
30 LED PWM (LEDC)
GoBack
Register 30.5. LEDC_CHn_DUTY_REG (n: 0-7) (0x0008+0x14*n)
(reserved)
31
19 18
0000000000000
LEDC_DUTY_CHn 0x000
0
Reset
LEDC_DUTY_CHn b b()
Register 30.6. LEDC_CHn_DUTY_R_REG (n: 0-7) (0x0010+0x14*n)
(reserved)
31
19 18
0000000000000
LEDC_DUTY_R_CHn 0x000
LEDC_DUTY_R_CHn n b()
0
Reset
Register 30.7. LEDC_TIMERx_CONF_REG (x: 0-3) (0x00A0+0x8*x)
(reserved)
LEDC_LTEIDMCE_LRTExIDC_CKP_LA_TERSIDAEMCL_E_U_RTTPxIIMM_REESRRTxx_PAUSE
31
26 25 24 23 22 21
0 0 0 0 0 00 0 1 0
LEDC_CLK_DIV_TIMERx 0x000
LEDC_TIMERx_DUTY_RES
43
0
0x0
Reset
LEDC_TIMERx_DUTY_RES x b() LEDC_CLK_DIV_TIMERx x b 8 b() LEDC_TIMERx_PAUSE x b() LEDC_TIMERx_RST xb 0b() LEDC_TICK_SEL_TIMERx x b 1 LEDC_APB_CLK_SEL[1:0]
1b0LEDC_PWM_CLK1REF_TICKb() LEDC_TIMERx_PARA_UP LEDC_CLK_DIV_TIMERx LEDC_TIMERx_DUTY_RESb
()
763
ESP32-S2 TRM ( 1.3)
30 LED PWM (LEDC)
Register 30.8. LEDC_TIMERx_VALUE_REG (x: 0-3) (0x00A4+0x8*x)
(reserved)
31
14 13
000000000000000000
LEDC_TIMERx_CNT 0x00
LEDC_TIMERx_CNT x ()
GoBack
0
Reset
Register 30.9. LEDC_INT_RAW_REG (0x00C0)
(reserved)
LEDC_LEODVCF__LCEODNVCFT___LCCEODNHVCFT7____LCCIEONDNHVTCFT6_____LRCCEOIANDNHVWTCFT5_____LRCCEOINADNHVWTCFT4_____LRCCEOINADNHVWTCFT3_____LRCCEOIANDNHVWTCFT2_____LRCCEIDNADNHUWTCT1T____LYRICEND_ADHCUTWC0H_T_R_LYNED_AIGNDWCU_TCHTE__LYNNRED_GDADCU__WCHTEC_LYNNHED_GD7DCU___CHTECIN_LYNNHTED_GD6_DCU___RCHTECIAN_LYNNHWETD_GD5D_CU___CRHTECINA_LYNNHWETD_GD4D_CU___RCHTECINA_LYNNHTWTE_GD3ID_CM___RCHECIEAN_LNNHRWTETGD32ID_M____RCEOCIENA_LNVHRTWETDF21ID__M___RCIIOCNENA_VHRTTTWF10_I__M_R_ROIEAINANVRWWTFT0____RIRNOAATVWW_FR_AINWT_RAW
31
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
LEDC_TIMERx_OVF_INT_RAW x b()
LEDC_DUTY_CHNG_END_CHn_INT_RAW n bb()
LEDC_OVF_CNT_CHn_INT_RAW n bovf_cnt LEDC_OVF_NUM_CHn b()
764
ESP32-S2 TRM ( 1.3)
30 LED PWM (LEDC)
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Register 30.10. LEDC_INT_ST_REG (0x00C4)
(reserved)
LEDC_LEODVCF__LCEODNVCFT___LCCEODNHVCFT7____LCCIEONDNHVTCFT6_____LSCCEOITNDNHVTCFT5_____LSCCEOITNDNHVTCFT4_____LSCCEOITNDNHVTCFT3_____LSCCEOITNDNHVTCFT2_____LSCCEIDTNDNHUTCT1T____LYSICEND_TDHCUTC0H_T_S_LYNETD_IGNDCU_TCHTE__LYNNSED_GDTDCU__CHTEC_LYNNHED_GD7DCU___CHTECIN_LYNNHTED_GD6_DCU___SCHTECITN_LYNNHETD_GD5D_CU___SCHTECITN_LYNNHETD_GD4D_CU___SCHTECITN_LYNNHTTE_GD3ID_CM___SCHECIETN_LNNHRTETGD32ID_M____SCEOCIETN_LNVHRTETDF21ID__M___SCIIOCNENT_VHRTTTF10_I__M_S_SOITEITNNVRTFT0____SISNOTTTV_FS_TINT_ST
31
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
LEDC_TIMERx_OVF_INT_ST LEDC_TIMERx_OVF_INT_ENA 1 LEDC_TIMERx_OVF_INT b()
LEDC_DUTY_CHNG_END_CHn_INT_ST LEDC_DUTY_CHNG_END_CHn_INT_ENA 1 LEDC_DUTY_CHNG_END_CHn_INT b()
LEDC_OVF_CNT_CHn_INT_ST LEDC_OVF_CNT_CHn_INT_ENA 1 LEDC_OVF_CNT_CHn_INT b()
Register 30.11. LEDC_INT_ENA_REG (0x00C8)
(reserved)
LEDC_LEODVCF__LCEODNVCFT___LCCEODNHVCFT7____LCCIEONDNHVTCFT6_____LECCEOINNDNHVATCFT5_____LECCEOINNDNHVTACFT4_____LECCEOINNDNHVTACFT3_____LECCEOINNDNHVATCFT2_____LECCEIDNNDNHUATCT1T____LYEICEND_NDHCUTAC0H_T_E_LYNEND_IGNDCAU_TCHTE__LYNNEED_GDNDCU__ACHTEC_LYNNHED_GD7DCU___CHTECIN_LYNNHTED_GD6_DCU___ECHTECINN_LYNNHAETD_GD5D_CU___CEHTECINN_LYNNHETAD_GD4D_CU___ECHTECINN_LYNNHTTAE_GD3ID_CM___ECHECIENN_LNNHRTAETGD32ID_M____ECEOCIENN_LNVHRTAETDF21ID__M___ECIIOCNENN_VHRTTTAF10_I__M_E_EOINEINNNVRAATFT0____EIENONNTVAA_FE_NINAT_ENA
31
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
LEDC_TIMERx_OVF_INT_ENA LEDC_TIMERx_OVF_INT b()
LEDC_DUTY_CHNG_END_CHn_INT_ENA LEDC_DUTY_CHNG_END_CHn_INT b( )
LEDC_OVF_CNT_CHn_INT_ENA LEDC_OVF_CNT_CHn_INT b()
765
ESP32-S2 TRM ( 1.3)
30 LED PWM (LEDC)
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Register 30.12. LEDC_INT_CLR_REG (0x00CC)
(reserved)
LEDC_LEODVCF__LCEODNVCFT___LCCEODNHVCFT7____LCCIEONDNHVTCFT6_____LCCCEOILNDNHVRTCFT5_____LCCCEOINLDNHVRTCFT4_____LCCCEOINLDNHVRTCFT3_____LCCCEOINLDNHVRTCFT2_____LCCCEIDNLDNHURTCT1T____LYCICEND_LDHCUTRC0H_TC__LYNED_LIGNDRCU_TCHTE__LYNNCED_GDLDCU_R_CHTEC_LYNNHED_GD7DCU___CHTECIN_LYNNHTED_GD6_DCU___CCHTECILN_LYNNHRETD_GD5D_CU___CCHTECINL_LYNNHRETD_GD4D_CU___CCHTECINL_LNYNHRTTE_GD3ID_CM___CCHECIENL_LNNHRRTETGD32ID_M____CCEOCIENL_LNVHRRTETDF21ID__M___CCIIOCNENL_VHRTTTRF10_I__M_C_COIELINLNVRRRTFT0____CICNOLLTVRR_FC_LINRT_CLR
31
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
LEDC_TIMERx_OVF_INT_CLR LEDC_TIMERx_OVF_INT b()
LEDC_DUTY_CHNG_END_CHn_INT_CLR LEDC_DUTY_CHNG_END_CHn_INT b()
LEDC_OVF_CNT_CHn_INT_CLR LEDC_OVF_CNT_CHn_INT b()
Register 30.13. LEDC_DATE_REG (0x00FC)
LEDC_DATE
31
0x19072601
LEDC_DATE b()
0
Reset
766
ESP32-S2 TRM ( 1.3)
31 (RMT)
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31
(RMT)
31.1
RMTcbRMT RAM RAM bRMT b
31.2
31.2.1 RMT
RMT 0 ~ 3b n b 0 block 0 block 0 1 block 1 block 1 b b b 256 x 32 RAMb
31.2-1. RMT
767
ESP32-S2 TRM ( 1.3)
31 (RMT)
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31.2.2 RMT RAM
31.2-2. RMT
31.2-3. RAM
RAM 31.2-3 b 16 level period b level c0 1period c31.2-1 clk_divbPeriod 0 b
768
ESP32-S2 TRM ( 1.3)
31 (RMT)
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RAM 64 x 32 blockb blockc 0 block 0 1 block 1b n block RMT_MEM_SIZE_CHn blockb RMT_MEM_SIZE_CHn > 1 n block (n) ~ block (n + RMT_MEM_SIZE_CHn -1) b n +1 ~ n + RMT_MEM_SIZE_CHn - 1 RAM block b RAM 0 RMT_MEM_SIZE_CHn 1a2a3 RAM 3 0a1 2 RAM b
RAM APB RAM RMT_MEM_OWNER_CHn RAM b RMT_MEM_OWNER_ERR_CHn b
RMT RMT_MEM_FORCE_PD RAM b
31.2.3
RMT_REF_ALWAYS_ON_CHn APB_CLK REF_TICK bRMT_DIV_CNT_CHn 0 256 RMT_DIV_CNT_CHn b RMT_REF_CNT_RST_CHn b b
31.2.4
RMT_TX_START_CHn 1 n RAM block bcperiod 0 RMT_CHn_TX_END_INT b RMT_TX_STOP_CHn b level RMT_IDLE_OUT_LV_CHn b RMT_IDLE_OUT_EN_CHn b
RMT_MEM_TX_WRAP_EN b RAM b RMT_MEM_SIZE_CHn = 1 64 * n RAM b (64 * (n +1) - 1) 64 * n b RMT_MEM_SIZE_CHn > 1 b
RMT_TX_LIM_CHn RMT_CHn_TX_THR_EVENT_INT b RMT_TX_LIM_CHn RAM b RMT_CHn_TX_THR_EVENT_INT RAM b
RMT_CARRIER_EN_CHn b b ( RMT_CARRIER_HIGH_CHn +1) APB_CLK REF_TICK (RMT_CARRIER_LOW_CHn +1) APB_CLK REF_TICK b RMT_CARRIER_OUT_LV_CHn RMT_CARRIER_OUT_LV_CHn b cRAM b RMT_CARRIER_EFF_EN_CHn b
RMT_TX_CONTI_MODE_CHn b RAM b RMT_TX_LOOP_CNT_EN_CHn b
769
ESP32-S2 TRM ( 1.3)
31 (RMT)
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RMT_TX_LOOP_NUM_CHn RMT_CHn_TX_LOOP_INT b
RMT_TX_SIM_EN b RMT_TX_SIM_CHn b
31.2.5
RMT_RX_EN_CHn 1 b RAM b RMT_IDLE_THRES_CHn RMT_CHn_RX_END_INT b
RMT_RX_FILTER_EN_CHn b RMT_RX_FILTER _THRES_CHn APB bb RMT_RX_FILTER_THRES_CHn APB b
31.2.6
· RMT_CHn_ERR_INT n b · RMT_CHn_TX_THR_EVENT_INT RMT_CHn_TX_LIM_REG b · RMT_CHn_TX_END_INT, b · RMT_CHn_RX_END_INT, b · RMT_CHn_TX_LOOP_INT RMT_TX_LOOP_NUM_CHn
b
31.3
RMT 31.3-1 b 3 b
31.3-1. RMT
PeriBUS1 PeriBUS2
0x3F416000 0x60016000
31.4
RMT cb RMT 31.3 b
RMT_CH0CONF0_REG RMT_CH0CONF1_REG
0 0 0 1
0x0010 0x0014
/
770
ESP32-S2 TRM ( 1.3)
31 (RMT)
RMT_CH1CONF0_REG RMT_CH1CONF1_REG RMT_CH2CONF0_REG RMT_CH2CONF1_REG RMT_CH3CONF0_REG RMT_CH3CONF1_REG RMT_APB_CONF_REG RMT_REF_CNT_RST_REG RMT_CH0_RX_CARRIER_RM_REG RMT_CH1_RX_CARRIER_RM_REG RMT_CH2_RX_CARRIER_RM_REG RMT_CH3_RX_CARRIER_RM_REG RMT_CH0CARRIER_DUTY_REG RMT_CH1CARRIER_DUTY_REG RMT_CH2CARRIER_DUTY_REG RMT_CH3CARRIER_DUTY_REG RMT_CH0_TX_LIM_REG RMT_CH1_TX_LIM_REG RMT_CH2_TX_LIM_REG RMT_CH3_TX_LIM_REG RMT_TX_SIM_REG RMT_CH0STATUS_REG RMT_CH1STATUS_REG RMT_CH2STATUS_REG RMT_CH3STATUS_REG RMT_CH0ADDR_REG RMT_CH1ADDR_REG RMT_CH2ADDR_REG RMT_CH3ADDR_REG RMT_DATE_REG FIFO / RMT_CH0DATA_REG RMT_CH1DATA_REG RMT_CH2DATA_REG RMT_CH3DATA_REG RMT_INT_RAW_REG RMT_INT_ST_REG RMT_INT_ENA_REG
1 0 1 1 2 0 2 1 3 0 3 1 RMT APB RMT 0 1 2 3
0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0080 0x0088 0x008C 0x0090 0x0094 0x0098
0 1 2 3
0x0060 0x0064 0x0068 0x006C
0 Tx 1 Tx 2 Tx 3 Tx RMT
0x0070 0x0074 0x0078 0x007C 0x0084
0 1 2 3 0 1 2 3
0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x004C
0x00FC
APB FIFO 0 APB FIFO 1 APB FIFO 2 APB FIFO 3
0x0000 0x0004 0x0008 0x000C
0x0050 0x0054 0x0058
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/ / / / / / / / /
/ / / /
/
/
/
771
ESP32-S2 TRM ( 1.3)
31 (RMT)
RMT_INT_CLR_REG
0x005C
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31.5
Register 31.1. RMT_CHnCONF0_REG (n: 0-3) (0x0010+8*n)
(reservedR)MT_RCMARTR_RICEMARRT_R_OICUEARTR__RELRIVNEM_R_CTC_H_EHMnFnFE_ME_NS_ICZHE_nCHn
31 30 29 28 27 26
24 23
0 01 1 1
0x1
RMT_IDLE_THRES_CHn
87
RMT_DIV_CNT_CHn
0
0x1000
0x2
Reset
RMT_DIV_CNT_CHn n bc/
RMT_IDLE_THRES_CHn bc/
RMT_MEM_SIZE_CHn n block 1 ~ 4-nbc/
RMT_CARRIER_EFF_EN_CHn 1 n 0 n ca RAM b RMT_CARRIER_EN_CHn 1 bc/
RMT_CARRIER_EN_CHn n b10 bc/
RMT_CARRIER_OUT_LV_CHn n b1'h0 1'h1bc/
772
ESP32-S2 TRM ( 1.3)
31 (RMT)
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Register 31.2. RMT_CHnCONF1_REG (n: 0-3) (0x0014+8*n)
(reserved)
RMT_RTMX_TS_TRIODMPLTE___CRIODHMULnTET___RROEMENUFT_T__C_ACLHLVHnW_KCA_YHRSnX__OCNA_RCRHIEnR_REMNT__CRHXn_FILTER_THRES_RCMHTn_RRMX_TF_RTILMXT_ETCR_OR_MMNEENTTMI___R_CAMOMHPOWnBTD__NREMMEM_REECT_MMH_CR__nMHMRRnEDSTMT___R_RRCWMSXHT_RT_nE__CTNRHXS__nTCS_HTCnAHRnT_CHn
31
21 20 19 18 17 16 15
87 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 00 0 0 0 0
0xf
0 0 1 0 0 0 0 0 Reset
RMT_TX_START_CHn n bbc/ RMT_RX_EN_CHn n bbc/ RMT_MEM_WR_RST_CHn n RAM bc RMT_MEM_RD_RST_CHn n RAM bc RMT_MEM_OWNER_CHn n RAM b1'h1 RAM1'h0
RAMbc/ RMT_TX_CONTI_MODE_CHn n
bc/ RMT_RX_FILTER_EN_CHn n bc/ RMT_RX_FILTER_THRES_CHn RMT_RX_FILTER_THRES_CHn APB
bc/ RMT_CHK_RX_CARRIER_EN_CHn RAM c n
bc/ RMT_REF_ALWAYS_ON_CHn n b1'h1APB_CLK1'h0REF_TICKc/
RMT_IDLE_OUT_LV_CHn n bc/ RMT_IDLE_OUT_EN_CHn n bc/ RMT_TX_STOP_CHn n bc/
773
ESP32-S2 TRM ( 1.3)
31 (RMT)
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Register 31.3. RMT_APB_CONF_REG (0x0080)
RMT_CLK_EN
31 30
(reserved)
RMT_RMMETM_R_MMFEOTMR_RC_MMFEEO_TMPR_RCU_MCMEE_LTMKP__D_ATFPOXB_R_WCFREIFA_OOP__NMENASK
54 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Reset
RMT_APB_FIFO_MASK 1'h1 RAM1'h0 APB FIFO RAMbc/
RMT_MEM_TX_WRAP_EN b block bc/
RMT_MEM_CLK_FORCE_ON RMT RAM RMT RAM bc/
RMT_MEM_FORCE_PD RMT RAM bc/
RMT_MEM_FORCE_PU 1 RMT RAM Light-sleep 0RMT Light-sleep RAM bc/
RMT_CLK_EN RMT RMT b1 RMT 0 RMT bc/
Register 31.4. RMT_REF_CNT_RST_REG (0x0088)
(reserved)
RMT_RRMEFT__RCRMNEFTT___RCRRMNSETFTT____CCRRHNSET3FT___CCRHNST2T__CRHST1 _CH0
31
43 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RMT_REF_CNT_RST_CHn n bc/
774
ESP32-S2 TRM ( 1.3)
31 (RMT)
GoBack
Register 31.5. RMT_CHn_RX_CARRIER_RM_REG (n: 0-3) (0x008C+4*n)
RMT_CARRIER_HIGH_THRES_CHn
RMT_CARRIER_LOW_THRES_CHn
31
16 15
0
0x00
0x00
Reset
RMT_CARRIER_LOW_THRES_CHn n (RMT_CARRIER_LOW_THRES_CHn + 1) bc/
RMT_CARRIER_HIGH_THRES_CHn
n
(RMT_CARRIER_HIGH_THRES_CHn + 1) bc/
Register 31.6. RMT_CHnCARRIER_DUTY_REG (n: 0-3) (0x0060+4*n)
RMT_CARRIER_HIGH_CHn
RMT_CARRIER_LOW_CHn
31
16 15
0x40
0x40
RMT_CARRIER_LOW_CHn n bc/ RMT_CARRIER_HIGH_CHn n bc/
0
Reset
775
ESP32-S2 TRM ( 1.3)
31 (RMT)
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Register 31.7. RMT_CHn_TX_LIM_REG (n: 0-3) (0x0070+4*n)
(reserved)
RMT_RLMOOT_PT_XC_OLUONOTP__RCENSTE_TE_NC_HCnHnRMT_TX_LOOP_NUM_CHn
31
21 20 19 18
98
0 0 0 0 0 0 0 0 0 0 00 0
0x0
RMT_TX_LIM_CHn
0
0x80
Reset
RMT_TX_LIM_CHn n b RMT_MEM_SIZE_CHn = 1 0 ~ 128 (64 * 32 /16 = 128) RMT_MEM_SIZE_CHn > 1 (0 ~ 128) * RMT_MEM_SIZE_CHn bc/
RMT_TX_LOOP_NUM_CHn bc/
RMT_TX_LOOP_CNT_EN_CHn bc/
RMT_LOOP_COUNT_RESET_CHn RMT_TX_CONTI_MODE_CHn bc
Register 31.8. RMT_TX_SIM_REG (0x0084)
(reserved)
RMT_RTMX_TS_IRTMMX__TES_NIRTMMX__TCS_HIRTM3MX__TCS_HITM2X__CSHIM1 _CH0
31
54 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RMT_TX_SIM_CHn n bc/ RMT_TX_SIM_EN bc/
776
ESP32-S2 TRM ( 1.3)
31 (RMT)
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Register 31.9. RMT_CHnSTATUS_REG (n: 0-3) (0x0030+4*n)
(reserved)
RMT_RAMPBT__RAMMPEBTM__R_MMMREEDTMM__R__EMWMEREMRRTM___PC_EMTFHRYEUnR_MLC_LR_CH_OMHnCWnTH_NnSETRA_TEE(Rr_eRCs_HeCnrvHend)
31
28 27 26 25 24 23 22
20 19 18
0 0 0 00 0 0 0 0
0x0
0
RMT_MEM_RADDR_EX_CH(nreserved)
10 9 8
0x0
0
RMT_MEM_WADDR_EX_CHn
0
0x0
Reset
RMT_MEM_WADDR_EX_CHn n RAM bc RMT_MEM_RADDR_EX_CHn n RAM bc RMT_STATE_CHn n FSM bc RMT_MEM_OWNER_ERR_CHn RAM block bc RMT_MEM_FULL_CHn RAM block bc RMT_MEM_EMPTY_CHn RAM block
bc
RMT_APB_MEM_WR_ERR_CHn APB RAM block bc
RMT_APB_MEM_RD_ERR_CHn APB RAM block bc
Register 31.10. RMT_CHnADDR_REG (n: 0-3) (0x0040+4*n)
(reserved)
31
19 18
0000000000000
RMT_APB_MEM_RADDR_C(Hrenserved)
10 9 8
0x0
0
RMT_APB_MEM_WADDR_CHn
0
0x0
Reset
RMT_APB_MEM_WADDR_CHn APB RAM bc RMT_APB_MEM_RADDR_CHn APB RAM bc
777
ESP32-S2 TRM ( 1.3)
31 (RMT)
Register 31.11. RMT_DATE_REG (0x00FC)
RMT_DATE
31
0x19072601
RMT_DATE c/
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0
Reset
Register 31.12. RMT_CHnDATA_REG (n: 0-3) (0x0000+4*n)
RMT_CHn_DATA_REG
31
0x000000
RMT_CHn_DATA_REG APB FIFO n bc
0
Reset
Register 31.13. RMT_INT_RAW_REG (0x0050)
(reserved)
RMT_RCMHT3__RTCMXH_T2L__ORTCOMXH_PT1L___TORICNXOMHT_PT0_L__O_RRITCNAOMXHWTP_T3__L__RIORNTCAOMXTHW__PT2TR___HRAITCNRWMXHT__T1_TE__RVHTRCAEXRMHWN__TT0TEH___VRTCRIEMNXH_N_TET3TT_V___HRRECEIRMNANRH_WTTRT3E_____VRRICIRNNEMAHXNTTW_T3_T_E__R_RRTNCAIAMXNDHWW_T_T2E__I_NNRRCETMDARH_W_RT2RI___NARCIRTNWMHX_T_T2R_E__ARRTNCWAMXDHW__T1E__INNRECTRMDH_R_T1R__I_NAIRRCNTWMXHT___T1RE__RATNRCAWXDMWH__T0EI_N_NRCETDMHR__TR0RIN__A_TCWIRN_HXTR_0_AE_RWTNAXDW__EINNTD__RINATW_RAW
31
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RMT_CHn_TX_END_INT_RAW n bbc RMT_CHn_RX_END_INT_RAW n bbc RMT_CHn_ERR_INT_RAW n bbc RMT_CHn_TX_THR_EVENT_INT_RAW n b
bc
RMT_CHn_TX_LOOP_INT_RAW n b bc
778
ESP32-S2 TRM ( 1.3)
31 (RMT)
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Register 31.14. RMT_INT_ST_REG (0x0054)
(reserved)
RMT_RCMHT3__RTCMXH_T2L__ORTCOMXH_PT1L___TORICNXOMHT_PT0_L__OS_RITCTNOMXHTP_T3__L__SIORNTCTOMXTH__PT2TS___HTRITCNRMXHT__T1_TE__SVHTRCTEXRMHN__TT0TEH___VRTCRIEMNXH_N_TET3TT_V___HRSECEIRTMNNRH_TTRT3E_____VRSICIRNNETMHXNTT_T3_T_E__S_SRTNCTTIMXNDH_T_T2E__I_NNRSCETMDTRH__RT2SI___NTRCIRTNMHX_T_T2S_E__TSRTNCTMXDH__T1E__INNRECTRMDH_R_T1S__I_NTIRRCNTMXHT___T1SE__STTNRTCXDMH__T0EI_N_NRCETDMHR__TR0SINT___TCIRN_HXTS_0_TE_STNTXD__EINNTD__SINTT_ST
31
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RMT_CHn_TX_END_INT_ST RMT_CHn_TX_END_INT bc RMT_CHn_RX_END_INT_ST RMT_CHn_RX_END_INT bc RMT_CHn_ERR_INT_ST RMT_CHn_ERR_INT bc RMT_CHn_TX_THR_EVENT_INT_ST RMT_CHn_TX_THR_EVENT_INT bc RMT_CHn_TX_LOOP_INT_ST RMT_CHn_TX_LOOP_INT bc
Register 31.15. RMT_INT_ENA_REG (0x0058)
(reserved)
RMT_RCMHT3__RTCMXH_T2L__ORTCOMXH_PT1L___TORICNXOMHT_PT0_L__O_ERITCNNOMXHATP_T3__L__EIORNTCNOMXTHA__PT2TE___HRNITCNRMXAHT__T1_TE__EVHTRCNEXRMHNA__TT0TEH___VRTCRIEMNXH_N_TET3TT_V___HREECEIRNMNNRH_ATTRT3E_____VREICIRNNEMNHXNTTA_T3_T_E__E_ERTNCNNIMXNDHAA_T_T2E__I_NNRECETMDNRH__ART2EI___NNRCIRTNAMHX_T_T2E_E__NERTNCANMXDHA__T1E__INNRECTRMDH_R_T1E__I_NNIRRCNTAMXHT___T1EE__ENTNRCNAXDMHA__T0EI_N_NRCETDMHR__TR0EIN_N__TCIARN_HXTE_0_NE_EATNNXDA__EINNTD__EINNTA_ENA
31
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RMT_CHn_TX_END_INT_ENA RMT_CHn_TX_END_INT bc/ RMT_CHn_RX_END_INT_ENA RMT_CHn_RX_END_INT bc/ RMT_CHn_ERR_INT_ENA RMT_CHn_ERR_INT bc/ RMT_CHn_TX_THR_EVENT_INT_ENA RMT_CHn_TX_THR_EVENT_INT bc/ RMT_CHn_TX_LOOP_INT_ENA RMT_CHn_TX_LOOP_INT bc/
779
ESP32-S2 TRM ( 1.3)
31 (RMT)
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Register 31.16. RMT_INT_CLR_REG (0x005C)
(reserved)
RMT_RCMHT3__RTCMXH_T2L__ORTCOMXH_PT1L___TORICNXOMHT_PT0_L__OC_RITCNLOMXRHTP_T3__L__CIORNTCLOMXTRH__PT2TC___HRLITCNRRMXHT__T1_TE__CVHTRCLEXRMHRN__TT0TEH___VRTCRIEMNXH_N_TET3TT_V___HCRECEIRMNLNRH_RTTRT3E_____VRCICIRNNEMLHXNTTR_T3_T_E__CC_RTNCLILMXNDHRR_T_T2E__I_NNRCCETMDLRH_R_RT2CI___NLRCIRTRNMHX_T_T2C_E__LCRTNCRLMXDHR__T1E__INNRECTRMDH_R_T1C__I_NLIRRCNTRMXHT___T1CE_C_LTNRCLRXDMRH__T0EI_N_NRCETDMHR__CTR0IN__L_TCRIRN_HXTC_0_LE_CRTNLXDR__EINNTD__CINLTR_CLR
31
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RMT_CHn_TX_END_INT_CLR RMT_CHn_TX_END_INT bc RMT_CHn_RX_END_INT_CLR RMT_CHn_RX_END_INT bc RMT_CHn_ERR_INT_CLR RMT_CHn_ERR_INT bc RMT_CHn_TX_THR_EVENT_INT_CLR RMT_CHn_TX_THR_EVENT_INT bc RMT_CHn_TX_LOOP_INT_CLR RMT_CHn_TX_LOOP_INT bc
780
ESP32-S2 TRM ( 1.3)
GoBack
VI
a b
781
ESP32-S2 TRM ( 1.3)
32
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32
32.1
ESP32-S2 · ESP32-S2 b · 12 * (SAR ADC) 20 b 5 ADC b · 8 (DAC)b v0.0 SAR ADC 13 b ESP32-S2 b
32.2
32.2.1
ESP32-S2 12 20 vdd33 bSAR ADC
· 2 DIG ADC DIG ADC1 CTRL DIG ADC2 CTRL DMA b · 2 RTC ADC RTC ADC1 CTRL RTC ADC2 CTRLb · 1 PWDET/PKDET CTRL Wi-Fi cb SAR ADC 32.2-1b
782
ESP32-S2 TRM ( 1.3)
32
GoBack
32.2-1. SAR ADC
32.2.2
· SAR ADC · 12 · 20 · · RTC ADC
Deep-sleep ULP · DIG ADC IIR · PWDET/PKDET Wi-Fi c
ULP ULP-FSMb
32.2-1 b
783
ESP32-S2 TRM ( 1.3)
32
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DAC Deep-sleep ULP vdd33 PWDET/PKDET DMA
32.2-1. ADC
RTC ADC1 Y Y Y -
RTC ADC2 Y Y Y -
DIG ADC1 Y
DIG ADC2 Y Y
PWDET Y -
32.2.3
SAR ADC 32.2-2b
Analog
pad_in[9:0]
en_pad[9:0]
SARADC1
internal_mux internal_signal
en_pad[9:0] pad_in[9:0]
SARADC2
RTC
SENS_SAR1_DIG_FORCE
0
RTC ADC1 CTRL
1
SENS_SAR2_RTC_FORCE
0
1
RTC ADC2 CTRL
Digital
SAR2ARB
DIG ADC1 CTRL
DIG ADC2 CTRL
PWDET CTRL
32.2-2. SAR ADC
32.2.3.1
SAR ADC b 32.2-2 SAR ADC1/2 b
32.2-2. SAR ADC
GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6
0 1 2 3 4 5
ADC SAR ADC1
784
ESP32-S2 TRM ( 1.3)
32
GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 pa_pkdet1 pa_pkdet2 vdd33
6 7 8 9 0 1 2 3 4 5 6 7 8 9 n/a n/a n/a
ADC SAR ADC2
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32.2.3.2 ADC
SAR ADC cc12 0 mV ~ Vref bVref SAR ADC 1100 mVb (data) Vdata
Vdata
=
Vref 4095
× data
Vref SAR ADC b 0 dBa2.5 dBa6 dB 11 dBb
32.2.4 RTC ADC
RTC ADC RTC SAR ADC ADC bRTC ADC 32.2-3b
32.2-3. RTC ADC
ULP (ULP-FSM) RTC ADC SENS_MEASn_START_FORCE b
785
ESP32-S2 TRM ( 1.3)
32
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SENS_MEASn_START_SAR RTC ADC b SENS_MEASn_DONE_SAR SENS_MEASn_DATA_SARb
ULP ADC ADC bRTC ADC ULP b
· Deep-sleep RTC ADC ULP ADC bULP RTC ADC b
· b RTC ADC b
32.2.5 DIG ADC
RTC ADC DIG ADC · · 12 · ab SAR ADC b
· DIG ADC APB_SARADC_START_FORCE bDIG ADC APB_SARADC_TIMER_TARGET APB_SARADC_TIMER_EN b
· DMA b · b
32.2.5.1 DIG ADC
SAR ADC opb DIG ADC bopop DIG ADC b
32.2-4 DIG ADC b
786
ESP32-S2 TRM ( 1.3)
32
GoBack
32.2-4. DIG ADC
ADC b DIG ADC 16 bb 16 b
8 3 32.2-3b
32.2-3.
ch_sel[3:0]
[7:0] null reserved
atten[1:0]
APB_SARADC_WORK_MODE DIG ADC
· SAR ADC1 SAR ADC2 b · SAR ADC1 SAR ADC2 DIG ADC b · SAR ADC1 SAR ADC2 DIG ADC b ADC DMA 16 12/11 ADC · 4 b · 4 1 SAR ADC b
787
ESP32-S2 TRM ( 1.3)
32
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I II b 32.2-4 32.2-5b
32.2-4. I DMA
ch_sel[3:0]
I DMA [15:0] data[11:0] SAR ADC
sar_sel SAR ADCncn = 1 2
32.2-5. II DMA
II DMA [15:0] ch_sel[3:0]
data[10:0] SAR ADC
DIG ADC 12 I 12 II 11 b
32.2.5.2 DMA
DIG ADC SPI3 DMA DIG ADC bSPI3 DMA DIG ADC b APB_SARADC_APB_ADC_TRANS DMA DIG ADCb DMA SPI3 DMA b
32.2.5.3 ADC
DIG ADC ADC b
· datacur
datacur
=
(k
-
1)dataprev k
+
datain k
- 0.5
· datain ADC
· dataprev
· k
APB_SARADC_ADCn_FILTER_FACTOR APB_SARADC_ADCn_FILTER_EN b DIG ADC dataprev DIG ADC b b
32.2.5.4
DIG ADC ADC cb · APB_SARADC_ADCn_THRES_EN · APB_SARADC_ADCn_THRES · APB_SARADC_ADCn_THRES_MODE
788
ESP32-S2 TRM ( 1.3)
32
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0: ADC_DATA < APB_SARADC_ADCn_THRES 1: ADC_DATA >= APB_SARADC_ADCn_THRESb SAR ADC1 SAR ADC2 ADC b
32.2.6 SAR ADC2
SAR ADC2 RTC ADC2 CTRLaDIG ADC2 CTRL PWDET/PKDET CTRLb SAR ADC2 ESP32-S2 SAR ADC2 b b
· b APB_SARADC_ARB_CTRL_REG APB_SARADC_ADC_ARB_FIX_PRIORITY b
· APB_SARADC_ARB_CTRL_REG APB_SARADC_ADC_ARB_RTC_PRIORITY (RTC ADC2 CTRL)a APB_SARADC_ADC_ARB_APB_PRIORITY (DIG ADC2 CTRL) APB_SARADC_ADC_ARB_WIFI_PRIORITY (PWDET/PKDET CTRL) b b
b ADC b b
b
· RTC ADC2 CTRL SENS_MEAS2_DATA_SAR
2'b10
2'b01
2'b00
· DIG ADC2 CTRL DMA ch_sel[3:0]
4'b1111
4'b1110
· PWDET/PKDET CTRL
2'b10
2'b01
2'b00
APB_SARADC_ADC_ARB_GRANT_FORCE APB_SARADC_ADC_ARB_RTC_FORCEaAPB_SARADC_ADC_ARB_WIFI_FORCEa APB_SARADC_ADC_ARB_APB_FORCE b
789
ESP32-S2 TRM ( 1.3)
32
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· APB_SARADC_ADC_ARB_XXX_FORCE 1b · APB_CLK APB_CLK 8 MHz b · SENS_SAR_MEAS2_MUX_REG SENS_SAR2_RTC_FORCE 1
RTC b
32.3
32.3.1
ESP32S-S2 8 (DAC)bb
32.3.2
DAC · 2 8 DAC · · VDD3P3_RTC_IO · · DMA · ULP 1 (ULP)b
32.3.3 DAC
DAC 2 8
DACn_OUT = VDD3P3_RTC_IO · PDACn_DAC/255
· VDD3P3_RTC_IO VDD3P3_RTC_IO c 3.3 Vb · PDACn_DAC a
RTCIO_PAD_DACn_REG DMAb RTCIO_PDACn_XPD_DAC SAR ADC FSM 32.3-1b
32.3.4
/ 32.3-2b
· SENS_SW_FSTEP
freq = dig_clk_rtc_freq · SENS_SW_FSTEP/65535
dig_clk_rtc 8 MHzb
790
ESP32-S2 TRM ( 1.3)
32
GoBack
SENS_DAC_DIG_FORCE SENS_DAC_CW_ENn
CW generator
DMA
1
1
0
RTCIO_PDACn_DAC[7:0]
0
pdacn_dac[7:0]
RTCIO_PDACn_XPD_DAC
1
pdacn_xpd_dac
SAR ADC FSM
0
pdac_clk
DACn
dacn_out
RTCIO_PDACn_DAC_XPD_FORCE
32.3-1. DAC
· SENS_DAC_SCALEn 1a1/2a1/4 1/8 b
· SENS_DAC_DCn b
· SENS_DAC_INVn 0° 180° b
2 : 0°
3 : 180°
32.3-2.
32.3.5 DMA
DAC (DMA) 2 DAC b SENS_DAC_DIG_FORCE APB_SARADC_APB_DAC_CTRL_REG APB_SARADC_APB_DAC_TRANS DIG_SARADC_CLK DAC CLKSPI3_DMA_OUT DAC_DATA b
2 DMA (DMA)b
791
ESP32-S2 TRM ( 1.3)
32
32.4
32.4.1
ESP32-S2 b
32.4.2
· ULP · ULP · ·
32.4.3
ANALOG
SENS_TSENS_OUT[7:0] SENS_TSENS_READY
SENS_TSENS_POWER_UP_FORCE
dump_out_fsm
power_up_fsm
ULP
Tsensor
parameter tsens_data
XPD_SAR_ POWER_DOMAIN
Tsensor_cntl
0 1
SENS_TSENS_POWER_UP SENS_TSENS_DUMP_OUT
RTC_REG_ FILE
SENS_TSENS_IN_INV
GoBack RTC
32.4-1.
32.4-1 ULP-FSM · CPU ULP-RISC-V SENS_TSENS_POWER_UP_FORCEaSENS_TSENS_POWER_UP SENS_TSENS_CLKGATE_EN c SENS_TSENS_DUMP_OUT SENS_TSENS_READY SENS_TSENS_OUT b
792
ESP32-S2 TRM ( 1.3)
32
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· ULP-FSM
SENS_TSENS_POWER_UP_FORCE ULP-FSM 1
(ULP)b
32.4.4
(°C)b T(°C) = 0.4386 * VALUE 27.88 * offset 20.52
VALUE offset bc 32.4-1b
32.4-1.
(°C) 50 ~ 125 20 ~ 100 -10 ~ 80 -30 ~ 50 -40 ~ 20
(°C) -2 -1 0 1 2
32.5
· APB_SARADC_ADC1_THRES_INTSAR ADC1 ADC_DATA
· APB_SARADC_ADC2_THRES_INTSAR ADC2 ADC_DATA
· APB_SARADC_ADC1_DONE_INTSAR ADC1 · APB_SARADC_ADC2_DONE_INTSAR ADC2 b 1 (ULP) ULP-RISC-V b
32.6
32.6-1 b 3 b
32.6-1.
SENSOR (RTC_PERI)
PeriBUS1 PeriBUS2
0x3F408800 0x60008800
793
ESP32-S2 TRM ( 1.3)
32
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SENSOR (DIGITAL)
PeriBUS1 0x3F440000 PeriBUS2 0x60040000
· SENSOR (RTC_PERI) RTC_PERI RTC_PERI c 9 b
· SENSOR (DIG_PERI) c 9 b
32.7
cb 32.6 b
32.7.1 SENSOR (RTC_PERI)
RTC ADC1 SENS_SAR_READER1_CTRL_REG SENS_SAR_MEAS1_CTRL1_REG SENS_SAR_MEAS1_CTRL2_REG SENS_SAR_MEAS1_MUX_REG SAR ADC SENS_SAR_ATTEN1_REG SENS_SAR_ATTEN2_REG RTC ADC AMP SENS_SAR_AMP_CTRL3_REG RTC ADC2 SENS_SAR_READER2_CTRL_REG SENS_SAR_MEAS2_CTRL2_REG SENS_SAR_MEAS2_MUX_REG
SENS_SAR_TSENS_CTRL_REG SENS_SAR_TSENS_CTRL2_REG DAC SENS_SAR_DAC_CTRL1_REG SENS_SAR_DAC_CTRL2_REG IO MUX SENS_SAR_IO_MUX_CONF_REG
RTC ADC1 RTC ADC1 RTC ADC1 SAR ADC1
SAR ADC1 SAR ADC2
AMP
RTC ADC2 RTC ADC2 SAR ADC2
RTC DAC RTC DAC
IO MUX
0x0000 0x0008 0x000C 0x0010
/ / /
0x0014 / 0x0038 /
0x0020 R/W
0x0024 0x0030 0x0034
/ /
0x0050 0x0054 /
0x011C 0x0120
/ /
0x0144 /
32.7.2 SENSOR (DIG_PERI)
794
ESP32-S2 TRM ( 1.3)
32
DIG ADC APB_SARADC_CTRL_REG APB_SARADC_CTRL2_REG APB_SARADC_CLKM_CONF_REG DIG ADC1 APB_SARADC_SAR1_PATT_TAB1_REG APB_SARADC_SAR1_PATT_TAB2_REG APB_SARADC_SAR1_PATT_TAB3_REG APB_SARADC_SAR1_PATT_TAB4_REG DIG ADC2 APB_SARADC_SAR2_PATT_TAB1_REG APB_SARADC_SAR2_PATT_TAB2_REG APB_SARADC_SAR2_PATT_TAB3_REG APB_SARADC_SAR2_PATT_TAB4_REG DIG ADC2 APB_SARADC_ARB_CTRL_REG DIG ADC APB_SARADC_FILTER_CTRL_REG APB_SARADC_FILTER_STATUS_REG DIG ADC APB_SARADC_THRES_CTRL_REG DIG ADC APB_SARADC_INT_ENA_REG APB_SARADC_INT_RAW_REG APB_SARADC_INT_ST_REG APB_SARADC_INT_CLR_REG DIG ADC DMA APB_SARADC_DMA_CONF_REG DIG DAC APB_SARADC_APB_DAC_CTRL_REG
APB_SARADC_APB_CTRL_DATE_REG
DIG ADC DIG ADC DIG ADC
1 0 ~ 3 1 1 4 ~ 7 1 1 8 ~ 11 1 1 12 ~ 15 1
2 0 ~ 3 1 2 4 ~ 7 1 2 8 ~ 11 1 2 12 ~ 15 1
DIG ADC2
DIG ADC DIG ADC
DIG ADC DIG ADC DIG ADC DIG ADC
DIG ADC DMA
DIG DAC
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0x0000 0x0004 0x005C
/ / /
0x0018 0x001C 0x0020 0x0024
/ / / /
0x0028 0x002C 0x0030 0x0034
/ / / /
0x0038 /
0x003C / 0x0040
0x0044 /
0x0048 0x004C 0x0050 0x0054
/
0x0058 /
0x0060 /
0x03FC /
795
ESP32-S2 TRM ( 1.3)
32
GoBack
32.8
32.8.1 SENSOR (RTC_PERI)
Register 32.1. SENS_SAR_READER1_CTRL_REG (0x0000)
(reservedS)ENS_SSEANRS1__SINART1__EDNATA_INV
(reserved)
31 30 29 28 27
87
0 0 1 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SENS_SAR1_CLK_DIV
0
2
Reset
SENS_SAR1_CLK_DIV bc/ SENS_SAR1_DATA_INV SAR ADC1 bc/ SENS_SAR1_INT_EN SAR ADC1 b0b1bc/
Register 32.2. SENS_SAR_MEAS1_CTRL1_REG (0x0008)
(reserved)
SENS_SERNTCS__SRATRCA_DSCAR_ACDLKCG_ARTEES_EETN
(reserved)
31
24 23 22 21
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SENS_RTC_SARADC_RESET SAR ADCbc/ SENS_RTC_SARADC_CLKGATE_EN SAR ADC bc/
796
ESP32-S2 TRM ( 1.3)
32
GoBack
Register 32.3. SENS_SAR_MEAS1_CTRL2_REG (0x000C)
SENS_SAR1_EN_PAD_FORCE
31 30
0
SENS_SAR1_EN_PAD 0
SENS_SEMNESA_SSEM1_NESSAT_SAM1R_TESA_TSFA1OR_RTDC_OSENAER_SAR
19 18 17 16 15
000
SENS_MEAS1_DATA_SAR 0
0
Reset
SENS_MEAS1_DATA_SAR SAR ADC1 bc SENS_MEAS1_DONE_SAR SAR ADC1 bc SENS_MEAS1_START_SAR RTC ADC1 bc/ SENS_MEAS1_START_FORCE 1 RTC ADC1 bc/ SENS_SAR1_EN_PAD SAR ADC1 Pad bc/ SENS_SAR1_EN_PAD_FORCE 1 SAR ADC1 Pad bc/
Register 32.4. SENS_SAR_MEAS1_MUX_REG (0x0010)
SENS_SAR1_DIG_FORCE
(reserved)
31 30
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SENS_SAR1_DIG_FORCE 1 SAR ADC1 DIG ADC1 CTRL bc/
Register 32.5. SENS_SAR_ATTEN1_REG (0x0014)
SENS_SAR1_ATTEN
31
0xffffffff
SENS_SAR1_ATTEN Pad 2 b 0 ~ 9bc/
0
Reset
797
ESP32-S2 TRM ( 1.3)
32
GoBack
Register 32.6. SENS_SAR_ATTEN2_REG (0x0038)
SENS_SAR2_ATTEN
31
0xffffffff
SENS_SAR2_ATTEN Pad 2 b 0 ~ 9bc/
0
Reset
Register 32.7. SENS_SAR_AMP_CTRL3_REG (0x0020)
(reserved)
31
43
0000000000000000000000000000
SENS_SAR1_DAC_XPD_FSM
0
3
Reset
SENS_SAR1_DAC_XPD_FSM DAC b4'b0010 DACb4'b0000 DAC b4'b0011 DAC bc/
Register 32.8. SENS_SAR_READER2_CTRL_REG (0x0024)
(reserSvEeNd)S_SSEANRS2__SIANRT2__EDNATA_INV
31 30 29 28
(reserved)
SENS_SAR2_WAIT_ARB_CY(CreLsEerved)
18 17 16 15
87
0 1 00 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
SENS_SAR2_CLK_DIV
0
2
Reset
SENS_SAR2_CLK_DIV bc/ SENS_SAR2_WAIT_ARB_CYCLE SAR ADC2 bc/ SENS_SAR2_DATA_INV SAR ADC2 bc/ SENS_SAR2_INT_EN SAR ADC2 bc/
798
ESP32-S2 TRM ( 1.3)
32
GoBack
Register 32.9. SENS_SAR_MEAS2_CTRL2_REG (0x0030)
SENS_SAR2_EN_PAD_FORCE
31 30
0
SENS_SAR2_EN_PAD 0
SENS_SEMNESA_SSEM2N_ESSA_TSAM2R_ETSA_TSFA2OR_RTDC_OSENAER_SAR
19 18 17 16 15
000
SENS_MEAS2_DATA_SAR 0
0
Reset
SENS_MEAS2_DATA_SAR SAR ADC2 bc SENS_MEAS2_DONE_SAR SAR ADC2 bc SENS_MEAS2_START_SAR RTC ADC2 bc/ SENS_MEAS2_START_FORCE 1 RTC ADC2 bc/ SENS_SAR2_EN_PAD SAR ADC2 Pad bc/ SENS_SAR2_EN_PAD_FORCE 1 SAR ADC2 Pad bc/
Register 32.10. SENS_SAR_MEAS2_MUX_REG (0x0034)
SENS_SAR2S_ERNTSC__SFAORR2C_EPWDET_CCT
(reserved)
31 30
28 27
0
0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SENS_SAR2_PWDET_CCT SAR2_PWDET_CCTPA bc/ SENS_SAR2_RTC_FORCE RTC ADC bc/
799
ESP32-S2 TRM ( 1.3)
32
GoBack
Register 32.11. SENS_SAR_TSENS_CTRL_REG (0x0050)
(reserved)
SENS_STESNESN_SSTE_SNEDSNU_STM_SPEP_NOOSWU_ETPRO_WUPER__FOUSPRECNES_TSENS_CLK_DIV SENS_STESNESN_ST_SEINN(_rSeIN_sIVeNrTve_dE)NSENS_TSENS_READY
SENS_TSENS_OUT
31
25 24 23 22 21
14 13 12 11
987
0
0 0 0 0 0 0 00 0 0
6
0 1 0 0 00
0x0
Reset
SENS_TSENS_OUT bc SENS_TSENS_READY bc SENS_TSENS_INT_EN bc/ SENS_TSENS_IN_INV bc/ SENS_TSENS_CLK_DIV bc/ SENS_TSENS_POWER_UP bc/ SENS_TSENS_POWER_UP_FORCE 0 FSM b1
bc/ SENS_TSENS_DUMP_OUT SENS_TSENS_POWER_UP_FORCE = 1
bc/
Register 32.12. SENS_SAR_TSENS_CTRL2_REG (0x0054)
(reserved)
SENS_STESNESN_ST_SERNESSE_TCLKGATE_EN
(reserved)
31
17 16 15 14
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SENS_TSENS_CLKGATE_EN bc/ SENS_TSENS_RESET bc/
800
ESP32-S2 TRM ( 1.3)
32
GoBack
Register 32.13. SENS_SAR_DAC_CTRL1_REG (0x011C)
(reserved)
SENS_SEDNACS_S_CEDNALKCSG_S_AEDRTNAEESCS_E_S_ETCEDNNALKCS__S_ICEDNNALVKCS___FCDOALRKCC__FEDO_IGHR_CI(GFrEeHO_sReLCOrvEWed)
SENS_SW_TONE_EN
31
28 27 26 25 24 23 22 21
17 16 15
0 0 0 00 0 0 0 0 00 0 0 0 00
SENS_SW_FSTEP 0
0
Reset
SENS_SW_FSTEP bc/ SENS_SW_TONE_EN 01bc/ SENS_DAC_DIG_FORCE 0DAC1 DAC2 DMA1DAC1 DAC2 DMAbc/
SENS_DAC_CLK_FORCE_LOW 1 PDAC_CLK bc/ SENS_DAC_CLK_FORCE_HIGH 1 PDAC_CLK bc/ SENS_DAC_CLK_INV 1 PDAC_CLKbc/ SENS_DAC_RESET DACbc/ SENS_DAC_CLKGATE_EN DAC bc/
801
ESP32-S2 TRM ( 1.3)
32
GoBack
Register 32.14. SENS_SAR_DAC_CTRL2_REG (0x0120)
(reserved)
SENS_SEDNACS__CDSAWCE_N_ECSN_W2D_AECNS_1EINNVS2_DACS_EINNVS1_DACS_ESNCSAL_ED2AC_SCALE1
31
26 25 24 23 22 21 20 19 18 17 16 15
0 0 0 0 0 01 1 0
0
0
0
SENS_DAC_DC2
87
0
SENS_DAC_DC1
0
0
Reset
SENS_DAC_DC1 DAC1 bc/
SENS_DAC_DC2 DAC2 bc/
SENS_DAC_SCALE1 DAC1 b0001 1/210 1/411 1/8bc/
SENS_DAC_SCALE2 DAC2 b0001 1/210 1/411 1/8bc/
SENS_DAC_INV1 DAC1b00011011 bc/
SENS_DAC_INV2 DAC2b00011011 bc/
SENS_DAC_CW_EN1 0 RTCIO_PDAC1_DAC PDAC1_DAC 1 PDAC1_DAC bc/
SENS_DAC_CW_EN2 0 RTCIO_PDAC2_DAC PDAC2_DAC 1 PDAC2_DAC bc/
Register 32.15. SENS_SAR_IO_MUX_CONF_REG (0x0144)
SENS_SEIONMSU_IXO_MCLUKX__GRAETSEE_TEN
(reserved)
31 30 29
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SENS_IOMUX_RESET IO MUXbc/ SENS_IOMUX_CLK_GATE_EN IO MUX bc/
802
ESP32-S2 TRM ( 1.3)
32
GoBack
32.8.2 SENSOR (DIG_PERI)
Register 32.16. APB_SARADC_CTRL_REG (0x0000)
APB_SAR(rAeDseCr_vWedAA)PITB__ASRABR(_rAeCDsYeCCr_AvLPXeEPBdD)__SASAPARBRA__DSAFCAPORB_RAD_CDSATECAAR__ASSDAARCR2_A__SPSPABEAR_LT1S_TA_PRAPAT_DTCC_L_PES_AACRRL2EA_RPAAPTBT__SLAERNADC_SAR1_PATT_LEN APB_SARADC_SAR_CLK_ADPIBV_SAAPRBA_DSCAR_AASPDABRC__S_CASLRA(rKRAe_D_sGeSCArE_AvTLWPeEBdOD)_RSAKAP_RBMA_ODSDCAER_ASDTACR_TSTART_FORCE
31 30 29 28 27 26 25 24 23 22
19 18
15 14
76 54
32 1 0
1 0 0 0000
15
15
4
1 0 0 0 0 0 Reset
APB_SARADC_START_FORCE 0 FSM SAR ADC1 SAR ADCbc/
APB_SARADC_START 1 SAR ADCb APB_SARADC_START_FORCE = 1 bc/
APB_SARADC_WORK_MODE b012bc/
APB_SARADC_SAR_SEL SAR ADCb0 SAR ADC11 SAR ADC2b bc/
APB_SARADC_SAR_CLK_GATED SAR ADC bc/ APB_SARADC_SAR_CLK_DIV SAR ADC bc/ APB_SARADC_SAR1_PATT_LEN SAR ADC10 ~ 15 1 ~ 16bc/ APB_SARADC_SAR2_PATT_LEN SAR ADC20 ~ 15 1 ~ 16bc/ APB_SARADC_SAR1_PATT_P_CLEAR DIG ADC1 CTRL bc/ APB_SARADC_SAR2_PATT_P_CLEAR DIG ADC2 CTRL bc/ APB_SARADC_DATA_SAR_SEL 1 sar_sel 16
11-bitbc/ APB_SARADC_XPD_SAR_FORCE XPD SARbc/ APB_SARADC_WAIT_ARB_CYCLE SAR_DONE
bc/
803
ESP32-S2 TRM ( 1.3)
32
GoBack
Register 32.17. APB_SARADC_CTRL2_REG (0x0004)
(reserved)
APB_SARADC_TIMER_EN
31
25 24 23
0 0 0 0 0 0 00
APB_SARADC_TIMER_TARGET
(reserAvPeBd)_SAAPRBA_DSCAR_ASDARC2__SIANRV1_INVAPB_SARADC_MAX_MEAASP_BN_USMARADC_MEAS_NUM_LIMIT
12 11 10 9 8
10
10
000
255
0 Reset
APB_SARADC_MEAS_NUM_LIMIT SAR ADC bc/ APB_SARADC_MAX_MEAS_NUM bc/ APB_SARADC_SAR1_INV 1 DIG ADC1 CTRL bc/ APB_SARADC_SAR2_INV 1 DIG ADC2 CTRL bc/ APB_SARADC_TIMER_TARGET SAR ADC bc/ APB_SARADC_TIMER_EN SAR ADC bc/
Register 32.18. APB_SARADC_CLKM_CONF_REG (0x005C)
(reserved)
APB_SAR(rAeDseCr_vCedLK) _SEL
APB_SARADC_CLKM_DIV_A
APB_SARADC_CLKM_DIV_B
31
23 22 21 20 19
14 13
87
000000000 0 0
0x0
0x0
APB_SARADC_CLKM_DIV_NUM
0
4
Reset
APB_SARADC_CLKM_DIV_NUM DIG_ADC bc/ APB_SARADC_CLKM_DIV_B bc/ APB_SARADC_CLKM_DIV_A bc/ APB_SARADC_CLK_SEL 1 APLLb2 APB_CLKbbc/
804
ESP32-S2 TRM ( 1.3)
32
Register 32.19. APB_SARADC_SAR1_PATT_TAB1_REG (0x0018)
APB_SARADC_SAR1_PATT_TAB1
31
0xf0f0f0f
APB_SARADC_SAR1_PATT_TAB1 1 0 ~ 3 1 bc/
Register 32.20. APB_SARADC_SAR1_PATT_TAB2_REG (0x001C)
APB_SARADC_SAR1_PATT_TAB2
31
0xf0f0f0f
APB_SARADC_SAR1_PATT_TAB2 1 4 ~ 7 1 bc/
Register 32.21. APB_SARADC_SAR1_PATT_TAB3_REG (0x0020)
APB_SARADC_SAR1_PATT_TAB3
31
0xf0f0f0f
APB_SARADC_SAR1_PATT_TAB3 1 8 ~ 11 1 bc/
GoBack
0
Reset
0
Reset
0
Reset
805
ESP32-S2 TRM ( 1.3)
32
Register 32.22. APB_SARADC_SAR1_PATT_TAB4_REG (0x0024)
APB_SARADC_SAR1_PATT_TAB4
31
0xf0f0f0f
APB_SARADC_SAR1_PATT_TAB4 1 12 ~ 15 1 bc/
GoBack
0
Reset
Register 32.23. APB_SARADC_SAR2_PATT_TAB1_REG (0x0028)
APB_SARADC_SAR2_PATT_TAB1
31
0xf0f0f0f
APB_SARADC_SAR2_PATT_TAB1 2 0 ~ 3 1 bc/
0
Reset
Register 32.24. APB_SARADC_SAR2_PATT_TAB2_REG (0x002C)
APB_SARADC_SAR2_PATT_TAB2
31
0xf0f0f0f
APB_SARADC_SAR2_PATT_TAB2 2 4 ~ 7 1 bc/
0
Reset
806
ESP32-S2 TRM ( 1.3)
32
Register 32.25. APB_SARADC_SAR2_PATT_TAB3_REG (0x0030)
APB_SARADC_SAR2_PATT_TAB3
31
0xf0f0f0f
APB_SARADC_SAR2_PATT_TAB3 2 8 ~ 11 1 bc/
GoBack
0
Reset
Register 32.26. APB_SARADC_SAR2_PATT_TAB4_REG (0x0034)
APB_SARADC_SAR2_PATT_TAB4
31
0xf0f0f0f
APB_SARADC_SAR2_PATT_TAB4 2 12 ~ 15 1 bc/
0
Reset
807
ESP32-S2 TRM ( 1.3)
32
GoBack
Register 32.27. APB_SARADC_ARB_CTRL_REG (0x0038)
(reserved)
APB_SARAAPDBC_S_AARDACDA_CPAB_R_ABSD_ACFRI_XAA_DARPCPBRB__IO_WARSDIFIACTIRA__YAPPADBRRC_IBOS_A_RAPARIRBDTTAY_CCDSA__CAPPARB_RRA_AIBODSDA_RCAPCAIRB_T_PAY_ABADSDR_CACBPR_(__RrAAeGAIODsDRRReCCBAIr_TN__vWAeYATDdR_IF)CBFIO___FARRORTCCRBE_C_FEAOPRBC_EFORCE
31
13 12 11 10 9
87
65 4 3 21
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 2
1
0 0 0 0 0 0 0 Reset
APB_SARADC_ADC_ARB_APB_FORCE SAR ADC2 DIG ADC2 CTRLbc/ APB_SARADC_ADC_ARB_RTC_FORCE SAR ADC2 RTC ADC2 CTRLbc/ APB_SARADC_ADC_ARB_WIFI_FORCE SAR ADC2 PWDET CTRLbc/ APB_SARADC_ADC_ARB_GRANT_FORCE SAR ADC2 bc/ APB_SARADC_ADC_ARB_APB_PRIORITY DIG ADC2 CTRL bc/ APB_SARADC_ADC_ARB_RTC_PRIORITY RTC ADC2 CTRL bc/ APB_SARADC_ADC_ARB_WIFI_PRIORITY PWDET/PKDET CTRL bc/ APB_SARADC_ADC_ARB_FIX_PRIORITY SAR ADC2 bc/
Register 32.28. APB_SARADC_FILTER_CTRL_REG (0x003C)
APB_SAAPRBA_DSCAR_AADDCC_1_AFDILCT2E_RAF_PILEBTN_ESRA_REANDC_ADC1_FILTER_FACTOR APB_SARADC_ADC2_FILTER_FACTOR
31 30 29
23 22
16 15
(reserved)
APB_SAAPRBA_DSCAR_AADDCC_1_AFDILCT2E_RF_ILRTEESRE_TRESET
21 0
00
64
64
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
APB_SARADC_ADC2_FILTER_RESET SAR ADC2 bc/ APB_SARADC_ADC1_FILTER_RESET SAR ADC1 bc/ APB_SARADC_ADC2_FILTER_FACTOR DIG ADC2 CTRL bc/ APB_SARADC_ADC1_FILTER_FACTOR DIG ADC1 CTRL bc/ APB_SARADC_ADC2_FILTER_EN DIG ADC2 CTRL bc/ APB_SARADC_ADC1_FILTER_EN DIG ADC1 CTRL bc/
808
ESP32-S2 TRM ( 1.3)
32
GoBack
Register 32.29. APB_SARADC_FILTER_STATUS_REG (0x0040)
APB_SARADC_ADC1_FILTER_DATA
APB_SARADC_ADC2_FILTER_DATA
31
16 15
0
0
0
Reset
APB_SARADC_ADC2_FILTER_DATA SAR ADC2 bc APB_SARADC_ADC1_FILTER_DATA SAR ADC1 bc
Register 32.30. APB_SARADC_THRES_CTRL_REG (0x0044)
APB_SAAPRBA_DSCAR_AADDCC_1_ATDHCR2E_ST_HERNES_EN
31 30 29
00
APB_SARADC_ADC1_THRES 0
17 16
APB_SARADC_ADC2_THRES 0
APB_SAAPRBA_DS(rCAeRs_eAArDDAvCPeCBd_1_)_ATSDHACRR2EA_SDT_HCMR_OECSDL_KEM_EONDE
43 2 1 0
0 0 0 0 Reset
APB_SARADC_CLK_EN bc/ APB_SARADC_ADC2_THRES_MODE SAR ADC2 b0 ADC_DATA
b1 ADC_DATA bc/ APB_SARADC_ADC1_THRES_MODE SAR ADC1 b0 ADC_DATA
b1 ADC_DATA bc/ APB_SARADC_ADC2_THRES SAR ADC2 bc/ APB_SARADC_ADC1_THRES SAR ADC1 bc/ APB_SARADC_ADC2_THRES_EN SAR ADC2 bc/ APB_SARADC_ADC1_THRES_EN SAR ADC1 bc/
809
ESP32-S2 TRM ( 1.3)
32
GoBack
Register 32.31. APB_SARADC_INT_ENA_REG (0x0048)
APB_SAAPRBA_DSACAPRB_A_ADSDACAPCRB_1_A_ADDSDOCACRN_2AAE_D_DDCICON_1NT_A_ETD_EHCNIRN2AET_S_T_EHINNRAETS__ENINAT_ENA
(reserved)
31 30 29 28 27
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
APB_SARADC_ADC2_THRES_INT_ENA APB_SARADC_ADC2_THRES_INT bc/ APB_SARADC_ADC1_THRES_INT_ENA APB_SARADC_ADC1_THRES_INT bc/ APB_SARADC_ADC2_DONE_INT_ENA APB_SARADC_ADC2_DONE_INT bc/ APB_SARADC_ADC1_DONE_INT_ENA APB_SARADC_ADC1_DONE_INT bc/
Register 32.32. APB_SARADC_INT_RAW_REG (0x004C)
APB_SAAPRBA_DSACAPRB_A_ADSDACAPCRB_1_A_ADDSDOCACRN_2AAE_D_DDCICON_1NT_A_ETD_RHCIARN2WET_S_T_RHIANRWETS__RIANWT_RAW
(reserved)
31 30 29 28 27
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
APB_SARADC_ADC2_THRES_INT_RAW APB_SARADC_ADC2_THRES_INT bc APB_SARADC_ADC1_THRES_INT_RAW APB_SARADC_ADC1_THRES_INT bc APB_SARADC_ADC2_DONE_INT_RAW APB_SARADC_ADC2_DONE_INT bc APB_SARADC_ADC1_DONE_INT_RAW APB_SARADC_ADC1_DONE_INT bc
810
ESP32-S2 TRM ( 1.3)
32
GoBack
Register 32.33. APB_SARADC_INT_ST_REG (0x0050)
APB_SAAPRBA_DSACAPRB_A_ADSDACAPCRB_1_A_ADDSDOCACRN_2AAE_D_DDCICON_1NT_A_ETD_SHCTIRN2ET_S_T_SHITNRETS__STINT_ST
(reserved)
31 30 29 28 27
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
APB_SARADC_ADC2_THRES_INT_ST APB_SARADC_ADC2_THRES_INT bc APB_SARADC_ADC1_THRES_INT_ST APB_SARADC_ADC1_THRES_INT bc APB_SARADC_ADC2_DONE_INT_ST APB_SARADC_ADC2_DONE_INT bc APB_SARADC_ADC1_DONE_INT_ST APB_SARADC_ADC1_DONE_INT bc
Register 32.34. APB_SARADC_INT_CLR_REG (0x0054)
APB_SAAPRBA_DSACAPRB_A_ADSDACAPCRB_1_A_ADDSDOCACRN_2AAE_D_DDCICON_1NT_A_ETDC_HCILRN2RET_S_T_CHILNRRETS_C_ILNRT_CLR
(reserved)
31 30 29 28 27
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
APB_SARADC_ADC2_THRES_INT_CLR APB_SARADC_ADC2_THRES_INT bc APB_SARADC_ADC1_THRES_INT_CLR APB_SARADC_ADC1_THRES_INT bc APB_SARADC_ADC2_DONE_INT_CLR APB_SARADC_ADC2_DONE_INT bc APB_SARADC_ADC1_DONE_INT_CLR APB_SARADC_ADC1_DONE_INT bc
811
ESP32-S2 TRM ( 1.3)
32
GoBack
Register 32.35. APB_SARADC_DMA_CONF_REG (0x0058)
APB_SAAPRBA_DSCAR_AADPCB__AAPDBC__TARDACN_SRESET_FSM (reserved)
31 30 29
16 15
0 00 0 0 0 0 0 0 0 0 0 0 0 0 0
APB_SARADC_APB_ADC_EOF_NUM 255
0
Reset
APB_SARADC_APB_ADC_EOF_NUM = spi_eof_num dma_in_suc_eofbc/
APB_SARADC_APB_ADC_RESET_FSM DIG ADC CTRL bc/ APB_SARADC_APB_ADC_TRANS DIG DAC CTRL SPI DMAbc/
Register 32.36. APB_SARADC_APB_DAC_CTRL_REG (0x0060)
(reserved)
APB_SAAPRBA_DSACAPRB_A_ADSPACAPBRB__AD_DDSAAACACPCRB___A_ARRDSPESCASTBRE__TAAD_DPAFCBCI___FTODDRAAACCN__TSAILMTEERR__EMNODE APB_SARADC_DAC_TIMER_TARGET
31
17 16 15 14 13 12 11
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 1 0
100
Reset
APB_SARADC_DAC_TIMER_TARGET DAC bc/ APB_SARADC_DAC_TIMER_EN DAC bc/ APB_SARADC_APB_DAC_ALTER_MODE DAC ALTER bc/ APB_SARADC_APB_DAC_TRANS DMA_DACbc/ APB_SARADC_DAC_RESET_FIFO DIG DAC FIFObc/ APB_SARADC_APB_DAC_RST DIG DACbc/
812
ESP32-S2 TRM ( 1.3)
32
Register 32.37. APB_SARADC_APB_CTRL_DATE_REG (0x03FC)
APB_SARADC_APB_CTRL_DATE
31
0x1907162
APB_SARADC_APB_CTRL_DATE bc/
GoBack
0
Reset
813
ESP32-S2 TRM ( 1.3)
· · · · ·
VII
GoBack
814
ESP32-S2 TRM ( 1.3)
· uESP32-S2 v ESP32-S2 b · uESP32-S2 v ESP32-S2 b · uESP32-S2 v ESP32-S2 b ·
https://espressif.com/zh-hans/support/documents/certificates · ESP32-S2 / (PCN)
https://espressif.com/zh-hans/support/documents/pcns?keys=ESP32-S2 · ESP32-S2 abugaa
https://espressif.com/zh-hans/support/documents/advisories?keys=ESP32-S2 ·
https://espressif.com/zh-hans/support/download/documents
· uESP32-S2 ESP-IDF v ESP-IDF b · ESP-IDF GitHub
https://github.com/espressif · ESP32 (E2E) aaab
https://esp32.com/ · ESP-FAQ b
https://espressif.com/projects/esp-faq/zh_CN/latest/index.html · The ESP Journal ab
https://blog.espressif.com/ · SDK aAppaaAT
https://espressif.com/zh-hans/support/download/sdks-demos
· ESP32-S2 ESP32-S2 b https://espressif.com/zh-hans/products/socs?id=ESP32-S2
· ESP32-S2 ESP32-S2 b https://espressif.com/zh-hans/products/modules?id=ESP32-S2
· ESP32-S2 ESP32-S2 b https://espressif.com/zh-hans/products/devkits?id=ESP32-S2
· ESP Product Selectorc ab https://products.espressif.com/#/product-selector?language=zh
· aa & PCB acaa https://espressif.com/zh-hans/contact-us/sales-questions
815
ESP32-S2 TRM ( 1.3)
AES BOOTCTRL DS DMA eFuse HMAC I2C I2S LEDC MMU PCNT PERI RMT RNG RSA RTC SHA SPI SYSTIMER TIMG TWAI UART ULP USB OTG WDT
AES Boot DMA eFuse HMAC I2C I2S LED PWM RSA bSoC SHA SPI UART USB On-The-Go
REG SYSREG
ISO
NMI W1TS
W1TC
b aaaaa b bcbISO /b CPU b b // b GPIO_ENABLE_W1TS_REG GPIO_ENABLE_REG b W1TS b
816
ESP32-S2 TRM ( 1.3)
TRM b
· RO · WO · WT · R/W · R/W1 · WL · R/W/SC
· R/W/SS · R/W/SS/SC · R/WC/SS · R/WC/SC · R/WC/SS/SC · R/WS/SC · R/WS/SS
· R/WS/SS/SC · R/SS/WTC · R/SC/WTC · R/SS/SC/WTC · RF/WF · R/SS/RC · varies
b
R b/b RO b/b HRO b/b W b/b WO b/b W1 b/ 1 0 b SS b 1 /b SC b 0 /
b SM b/
b SU b/b RS b/ 1b RC b/ 0b RF FIFOb FIFO/b WF FIFOb//
APB FIFOb WS b//b W1S 1 b 1 //
b W0S 0 b 0 //
b WC b//b W1C 1 b 1 //
b W0C 0 b 0 //
b WT b 1
cAPB WTC c WTCb
817
ESP32-S2 TRM ( 1.3)
WTC W1T W0T WL varies
b 1 WT c WTb 1 b 1 b 0 b 0 b b/b bb
818
ESP32-S2 TRM ( 1.3)
ab
b
1. b
2. boResetpb X Field_A 1b
Register 32.38. X ()
(reserved)
Field_C
31
20 19
16 15
(reserved)
Field_FBield_A
21 0
000000000000
0000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset
X Field_AaField_B Field_C 0x0a0x1 0x2
· 1 b 0x0000_0003 0x0002_0002 b
· 2 0x0002_0002 b
819
ESP32-S2 TRM ( 1.3)
· RAWcb RAW 1b
· ENAcb ENA bc RAW b
· STcbST 1 RAW ENA 1bRAW ENA ST 0b ENA/RAW/ST 32.8-4b
· CLRcCLR b 1 b
32.8-4. ENA/RAW/ST
ENA 0
1
RAW 0 1
ST 0 0 1
820
ESP32-S2 TRM ( 1.3)
2025-08-06 v1.3
· 6 6.2.3 CPU
821
ESP32-S2 TRM ( 1.3)
2025-02-17 v1.2
· 1 (ULP) SENS_SAR_I2C_CTRL_REG
· 3 3.3-5 · 4 eFuse (eFuse) 4.4-1 eFuse
· 5 IO MUX GPIO 5.8 · 6 SYSCON_TICK_CONF_REG · 7 Boot (BOOTCTRL)
EFUSE_DIS_FORCE_DOWNLOAD
EFUSE_DIS_DOWNLOAD_MODE Boot
ROM
· 9
9.4-3 EXT1
op
RTC_CNTL_WDT_WKEY
9.4-3 EXT1
· 11 (TIMG) TIMG_WDT_CLK_PRESCALER · 14 (PMS) APB_CTRL to SYSCON
· 15
SPI4 I2S1
15.3.2
· 23 UART (UART) (break condition)
wake_up
· 24 SPI (SPI) SPI_LCD_HB_FRONTa
SPI_LCD_VB_FRONTaSPI_LCD_VSYNC_WIDTHa
SPI_LCD_HSYNC_WIDTHaSPI_LCD_HSYNC_POSITION · 25 I2C (I2C) I2C_COMD0_REGa
I2C_SDA_FORCE_OUT I2C_SCL_FORCE_OUT
· 26 I2S (I2S) I2S_TX_FIFO_MODa
I2S_RX_FIFO_MODaI2S_TX_FIFO_MOD_FORCE_ENa
I2S_RX_FIFO_MOD_FORCE_EN
· 28 USB OTG USB OTG
· 30 LED PWM (LEDC)
· 32
822
ESP32-S2 TRM ( 1.3)
2022-09-23 v1.1
2021-06-11 v1.0 2020-12-28 v0.7
· 1 (ULP) 1.9 · 4 eFuse (eFuse) · 9
RTC_CNTL_MAIN_STATE_IN_IDLE · 19 HMAC (HMAC) · USB OTG · 29 (TWAI) · 31 (RMT) 31.2-1 31.2-2 · 32 · ·
RTC8M_CLK RC_FAST_CLK RTC8M_D256_CLK RC_FAST_DIV_CLK RTC_CLK RC_SLOW_CLK SLOW_CLK RTC_SLOW_CLK FAST_CLK RTC_FAST_CLK PLL_160M_CLK PLL_F160M_CLK · 6.1-1 eFuse
· 4 eFuse (eFuse) EFUSE_DIS_RTC_RAM_BOOT
· 9 · 14.3.2.2 · 23 UART (UART) LEDC_TIMERx_CONF_REG (x: 0-3)
· 28.5 USB OTG
24 SPI (SPI)
· 2 DMA (DMA) DMA EDMA · 9 9.3-1 · 11 (TIMG) TIMG_RTCCALICFG_REG
TIMG_RTCCALICFG1_REG · 19 HMAC (HMAC) · 23 UART (UART) 23.3-1
UART_RXD_CNT_REG · 29 (TWAI)
823
ESP32-S2 TRM ( 1.3)
2020-08-12 v0.6
2020-06-19 v0.5
2020-05-21 v0.4
2020-04-01 v0.3
2020-01-20 v0.2 2019-11-27 v0.1
· 26 I2S (I2S) · 28 USB OTG · 6 6.2-1 · 22 (RNG) 22.4 · 23 UART (UART) 23.3.4.2
· 29 (TWAI) 29.5
32
· 2 DMA (DMA) Copy DMA DMA Internal DMA EMDA
· 12 (WDT) 12.4
· 9 · 29 (TWAI)
· 4 eFuse (eFuse) EFUSE_PGM_DATA1_REG[16] EFUSE_RPT4_RESERVED5 EFUSE_RPT4_RESERVED5_ERR · 5 IO MUX GPIO 5.4 GPIO · 22 (RNG)
· 1 (ULP) · 10 (SYSTIMER) · 13 XTAL32K (XTWDT) · 14 (PMS) · 19 HMAC (HMAC)
RTC_CLK
· 2 DMA (DMA) · 5 IO MUX GPIO · 23 UART (UART) eFuse a
824
ESP32-S2 TRM ( 1.3)
URL b opab aa b b b Wi-Fi Wi-Fi b Bluetooth SIG b ab © 2025 cbb www.espressif.com
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