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User Guide for GOWIN models including: GW5AS-25, GW5AS-138, GW5AS Series of FPGA Products Package and Pinout, GW5AS Series, GW5AS Series FPGA Products, FPGA Products Package and Pinout, FPGA Products, FPGA
2 Overview 2.1 PB-Free Package UG1106-1.0.4E 3(13) 2 Overview GOWINSEMI GW5AS-25 and GW5AS-138 devices are the 5 series products of Arora family, with abundant internal resources, a new
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DocumentDocumentGW5AS series of FPGA Products Package & Pinout User Guide UG1106-1.0.2E, 02/02/2024 Copyright © 2024 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. is a trademark of Guangdong Gowin Semiconductor Corporation and is registered in China, the U.S. Patent and Trademark Office, and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders. No part of this document may be reproduced or transmitted in any form or by any denotes, electronic, mechanical, photocopying, recording or otherwise, without the prior written consent of GOWINSEMI. Disclaimer GOWINSEMI assumes no liability and provides no warranty (either expressed or implied) and is not responsible for any damage incurred to your hardware, software, data, or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms and Conditions of Sale. GOWINSEMI may make changes to this document at any time without prior notice. Anyone relying on this documentation should contact GOWINSEMI for the current documentation and errata. Revision History Date 09/28/2023 11/30/2023 Version 1.0E 1.0.1E 02/02/2024 1.0.2E Description Initial version published. The pin info. of UG256 package for GW5AS-25 devices added. "2.5 I/O BANK Introduction" updated. The quantity of GW5AS-138 pins updated. The note of "Table 2-3 Quantity of GW5AS-138 Pins" added. Contents Contents Contents ................................................................................................................. i List of Figures ..................................................................................................... ii List of Tables...................................................................................................... iii 1 About This Guide .......................................................................................... 1 1.1 Purpose .............................................................................................................................. 1 1.2 Related Documents ............................................................................................................ 1 1.3 Terminology and Abbreviations........................................................................................... 1 1.4 Support and Feedback ....................................................................................................... 1 2 Overview ........................................................................................................ 2 2.1 PB-Free Package ............................................................................................................... 2 2.2 Package and Max. User I/O Information ............................................................................ 2 2.3 Power Pins.......................................................................................................................... 3 2.4 Pin Quantity ........................................................................................................................ 3 2.4.1 Quantity of GW5AS-138 Pins .......................................................................................... 3 2.4.2 Quantity of GW5AS-25 Pins ............................................................................................ 4 2.5 I/O BANK Introduction ........................................................................................................ 5 3 View of Pin Distribution ................................................................................ 6 3.1 View of GW5AS-138 Pin Distribution ................................................................................. 6 3.1.1 View of UG324A Pin Distribution ..................................................................................... 6 3.2 View of GW5AS-25 Pin Distribution ................................................................................... 7 3.2.1 View of UG256 Pin Distribution ....................................................................................... 7 4 Package Diagram .......................................................................................... 9 4.1 UG324A Package Outline (15mm x 15mm, GW5AS-138) ................................................. 9 4.2 UG256 Package Outline (14mm x 14mm, GW5AS-25) ................................................... 11 UG1106-1.0.2E i List of Figures List of Figures Figure 3-1 View of GW5AS-138 UG324A Pin Distribution (Top View) .............................................. 6 Figure 3-2 View of GW5AS-138 UG324A Pin Distribution (Top View) .............................................. 7 Figure 4-1 Package Outline UG324A ................................................................................................ 9 Figure 4-2 Recommended PCB Layout UG324A .............................................................................. 10 Figure 4-3 Package Outline UG256................................................................................................... 11 Figure 4-4 Recommended PCB Layout UG256 ................................................................................ 12 UG1106-1.0.2E ii List of Tables List of Tables Table 1-1 Terminology and Abbreviations .......................................................................................... 1 Table 2-1 Package, Max. User I/O Information, and LVDS Pairs ...................................................... 2 Table 2-2 GW5AS Power Pins ........................................................................................................... 3 Table 2-3 Quantity of GW5AS-138 Pins ............................................................................................ 3 Table 2-4 Quantity of GW5AS-25 Pins .............................................................................................. 4 Table 3-1 Other Pins in GW5AS-138 UG324A .................................................................................. 7 Table 3-2 Other Pins in GW5AS-25 UG256....................................................................................... 8 UG1106-1.0.2E iii 1 About This Guide 1.1 Purpose 1 About This Guide 1.1 Purpose This manual introduces Gowin GW5AS series of FPGA products package and provides pin definitions, a list of pin numbers, pin distribution view, and package diagrams. 1.2 Related Documents The latest user guides are available on the GOWINSEMI Website. You can find the related documents at www.gowinsemi.com: DS1114, GW5AS-138 Data Sheet UG1107, GW5AS-138 Pinout DS1105, GW5AS-25 Data Sheet UG1115, GW5AS-25 Pinout 1.3 Terminology and Abbreviations The terminology and abbreviations used in this manual are as shown in Table 1-1. Table 1-1 Terminology and Abbreviations Terminology and Abbreviations Meaning FPGA Field Programmable Gate Array GPIO Gowin Programmable Input/Output UG UBGA Package 1.4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly by the following ways. Website: www.gowinsemi.com E-mail: support@gowinsemi.com UG1106-1.0.2E 1(12) 2 Overview 2.1 PB-Free Package 2 Overview GOWINSEMI GW5AS-138 devices are the 5th-generation of Arora family, with abundant internal resources, a new-architecture and highperformance DSP supporting AI operations, high-speed LVDS interfaces, and abundant BSRAM resources. At the same time, GW5AS-138 devices integrate a hardcore processor RiscV AE350_SOC, self-developed DDR3, and provide a variety of packages. They are suitable for applications such as low power, high performance and compatibility designs. Gowin provides a new generation of FPGA hardware development environment that supports FPGA synthesis, placement & routing, bitstream generation and download, etc. 2.1 PB-Free Package GW5AS series of FPGA products are PB free in line with the EU RoHS environmental directives. The substances used in the GW5AS series of FPGA products are in full compliance with the IPC-1752 standards. 2.2 Package and Max. User I/O Information Table 2-1 Package, Max. User I/O Information, and LVDS Pairs Package Pitch (mm) Size (mm) E-pad Size (mm) GW5AS-25 GW5AS-138 UG324A 0.8 15 x 15 - - 221 (106) UG256 0.8 14 x 14 - 144 (68) - Note! For package type abbreviations employed in this manual, see 1.3 Terminology and Abbreviations. UG1106-1.0.2E 2(12) 2 Overview 2.3 Power Pins 2.3 Power Pins Table 2-2 GW5AS Power Pins VCCIO0 VCCIO1 VCCIO4 VCCIO5 VCCIO10 VCC VCCC VCC_REG M0_VDD_12 VQPS VCCIO2 VCCIO6 VCCX M0_VDDX VSS 2.4 Pin Quantity 2.4.1 Quantity of GW5AS-138 Pins Table 2-3 Quantity of GW5AS-138 Pins Pin Type BANK0 BANK1 BANK2 Single-ended IO/ Differential pair/LVDS[1] BANK3 BANK4 BANK5 BANK6 BANK7 BANK10 BANK11 Max. User I/O[2] Differential Pair True LVDS Output VCCIO2 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCC/VCCC VCC_REG VCCIO10 VCCX/M0_VDDX/M1_VDDX VSS MODE0 MODE1 MODE2 GW5AS-138 UG324A 0/0/0 0/0/0 50/24/24 0/0/0 50/24/24 50/24/24 50/24/24 10/4/4 12/6/6 0/0/0 221 106 106 6 6 6 6 1 14 1 1 4 48 1 1 1 VCCIO3 VCCIO7 VCC_EXT M1_VDDX - UG1106-1.0.2E 3(12) 2 Overview 2.4 Pin Quantity Pin Type NC GW5AS-138 UG324A 5 Note! [1] Single-ended/Differential I/O quantity includes CLK pins and download pins. [2] RECONFIG_N pin cannot be multiplexed as I/O. 2.4.2 Quantity of GW5AS-25 Pins Table 2-4 Quantity of GW5AS-25 Pins Pin Type GW5AS-25 UG256 BANK0 1/0/0 BANK1 8/4/4 BANK2 19/9/9 Single-ended IO/ Differential pair/LVDS[1] BANK3 BANK4 BANK5 BANK6 28/14/14 35/17/17 27/13/13 12/6/6 BANK7 10/5/5 BANK10 4/2/0 BANK11 0/0/0 Max. User I/O 144 Differential Pair 70 True LVDS Output 68 VCCIO0/VCCIO1/VCCIO10/VCCIO2/ VCCIO6/VCCIO7 3 VCCIO3/VCCIO4 2 VCCIO5 2 M0_VDDX/VCCX 1 M0_VDD_12 1 VCC_EXT 8 VCC_REG 1 VQPS 1 VSS 23 MODE0 1 MODE1 1 MODE2 1 NC 0 MCU 30 Note! [1] Single-ended/Differential I/O quantity includes CLK pins and download pins. UG1106-1.0.2E 4(12) 2 Overview 2.5 I/O BANK Introduction 2.5 I/O BANK Introduction GW5AS-25 has eight GPIO Banks. In addition, Bank 10 is JTAG Bank, Bank 11 is a Reserved Bank. See DS1105, GW5AS-25 Data Sheet > 2.3 Input/Output Blocks for details. GW5AS-138 has six GPIO Banks (Bank2~7) and a Bank for configuration (Bank 10). See DS1114, GW5AS-138 Data Sheet > 2.3 Input/Output Blocks for details. This manual provides the pin distribution view of GW5AS series of FPGA products. For details, please refer to Chapter 3 View of Pin Distribution. The I/O Banks that form GW5AS series of FPGA products are marked with different colors. Various symbols and colors are used for the user I/O, power, and ground. The various symbols and colors used for the various pins are defined as follows: " " denotes the I/O in BANK0 " " denotes the I/O in BANK1 " " denotes the I/O in BANK2 " " denotes the I/O in BANK3 " " denotes the I/O in BANK4 " " denotes the I/O in BANK5 " " denotes the I/O in BANK6 " " denotes the I/O in BANK7 " " denotes the I/O in BANK10 " " denotes the I/O in BANK11 " " denotes the DIO in MIPI and ADC " " denotes VCC, VCCX, VCCIO, and the filling color does not change " " denotes VSS, and the filling color does not change " " denotes NC UG1106-1.0.2E 5(12) 3 View of Pin Distribution 3.1 View of GW5AS-138 Pin Distribution 3 View of Pin Distribution 3.1 View of GW5AS-138 Pin Distribution 3.1.1 View of UG324A Pin Distribution Figure 3-1 View of GW5AS-138 UG324A Pin Distribution (Top View) UG1106-1.0.2E 6(12) 3 View of Pin Distribution 3.2 View of GW5AS-25 Pin Distribution Table 3-1 Other Pins in GW5AS-138 UG324A VCCIO2 C13,H18,G15,K14,A17,D16 VCCIO4 N13,U15,T12,P16,L17,V18 VCCIO5 K4,V8,T2,N3,U5P6 VCCIO6 D6,F2,G5,A7,J1,C3 VCCIO7 B10 VCCIO10 R9 VCC/VCCC N7,F8,G7,L7,H8,L11,N9,M10,J11,K8,J7,G9,N11,M 8 VCC_REG H10 VCCX/M0_VDDX/M1_VDDX H12,K12,F12,M12 VSS A12,A2,B15,B5,C18,C8,D11,D1,E14,E4,F17,F11,F 9,F7,G12,G10,G8,H13,H11,H7,H3,J16,J12,J8,J6, K11,K7,L12,L8,L2,M15,M11,M9,M7,M5,N18,N12,N 10,N8,P1,R14,R4,T17,T7,U10,V13,H9,V3 3.2 View of GW5AS-25 Pin Distribution 3.2.1 View of UG256 Pin Distribution Figure 3-2 View of GW5AS-138 UG324A Pin Distribution (Top View) UG1106-1.0.2E 7(12) 3 View of Pin Distribution 3.2 View of GW5AS-25 Pin Distribution Table 3-2 Other Pins in GW5AS-25 UG256 VCCIO0/VCCIO1/VCCIO10/ VCCIO2/VCCIO6/VCCIO7 H10,K9,G9 VCCIO3/VCCIO4 M4,N5 VCCIO5 D5,J7 M0_VDDX/VCCX G8 M0_VDD_12 E4 VCC_EXT G10,A1,G7,T16,T1,K10,K7,A16 VCC_REG H7 VQPS K8 VSS B15,C3,C14,D4,E5,E12,F6,F11,H8,H9,J8,J9,L6,L 11,M5,M12,N4,N13,P3,P14,R2,R15,B2 UG1106-1.0.2E 8(12) 4 Package Diagram 4.1 UG324A Package Outline (15mm x 15mm, GW5AS138) 4 Package Diagram 4.1 UG324A Package Outline (15mm x 15mm, GW5AS-138) Figure 4-1 Package Outline UG324A UG1106-1.0.2E 9(12) 4 Package Diagram 4.1 UG324A Package Outline (15mm x 15mm, GW5AS138) Figure 4-2 Recommended PCB Layout UG324A E A1 TOP VIEW b e Unit:mm D 15.00 E 15.00 D e 0.80 b 0.40 UG1106-1.0.2E 10(12) 4 Package Diagram 4.2 UG256 Package Outline (14mm x 14mm, GW5AS25) 4.2 UG256 Package Outline (14mm x 14mm, GW5AS-25) Figure 4-3 Package Outline UG256 UG1106-1.0.2E 11(12) 4 Package Diagram 4.2 UG256 Package Outline (14mm x 14mm, GW5AS25) Figure 4-4 Recommended PCB Layout UG256 E A1 D TOP VIEW b e Unit:mm D 14.00 E 14.00 e 0.80 b 0.35 UG1106-1.0.2E 12(12)