ADM-VPX3-9Z5-RTM
User Manual
Document Revision: 1.0
8th June 2021
Introduction
The ADM-VPX3-9Z5-RTM is a 3U, VPX, Rear Transition Module (RTM) designed to interface with Alpha Data ADM-VPX3-9Z5 Zynq Ultrascale+ FPGA board.
The ADM-VPX3-9Z5-RTM provides complete breakout of all backplane signals providing the user with complete flexibility during development and debug.
Figure 1: ADM-VPX3-9Z5-RTM
Key Features
PS GTR IO
- IO Connectors from the GTR lanes from the PS side of the ADM-VPX3-9Z5:
• One Gigabit Ethernet RJ45 port, available on the front panel
• 1 SATA interface, via an internal standard connector
• 1 DisplayPort interface, 2 lanes wide, available via the front panel - 1 Serial COM port interfaces, available on the front panel
- 1 Serial CAN BUS interfaces, available on an internal header
- RTC Battery connection header
- GPIOs routed to an internal header which can be looped back via jumper links (for internal testing).
- 12 HSSIO differential pairs – connected to GTH lanes on the PL side of the ADM-VPX3-9Z5:
• Two Firefly connectors (8 HSSIO pairs)
• 4 SATA interfaces, via internal standard connectors (4 HSSIO pairs) - Xilinx JTAG programming header
References & Specifications
| ANSI/VITA 46.0 | VPX Baseline Standard, October 2007, VITA, ISBN 1-885731-44-2 |
| ad_ug_1341 | ADM-VPX3-9Z5 User Manual, June 2021, Alpha Data, |
Table 1: References
Installation
Software Installation
Please refer to the ADM-VPX3-9Z5 area on the Alpha-Data support site for access to system monitoring utilities, documentation and FPGA reference designs.
Hardware Installation
Handling Instructions
The components on this board can be damaged by electrostatic discharge (ESD). To prevent damage, observe ESD precautions:
– Always wear a wrist-strap when handling the card
– Hold the board by the edges
– Avoid touching any components
– Store in ESD safe bag.
Functional Description
Block Diagram
Figure 2 : ADM-VPX3-9Z5-RTM Block Diagram
Assembly Drawing
Figure 3 : ADM-VPX3-9Z5-RTM Top View
Connector Definitions
The description of the connectors on the board status shown below:
| Comp. Ref. | Function |
| JP1 | NVMRO – not required on ADM-VPX3-9Z5 |
| JP2 | GPIO Enable. position 1-2 = GPIO Headers Disabled : 2-3 = Enabled |
| J12 | CANBUS Header |
| J10 | DisplayPort Connector |
| BT1 | RTC Battery Holder |
| J1+J3 | GPIO Headers |
| J11 | Xilinx Programming cable Connector |
| J4 | PS side SATA interface |
| J16-J19 | PL side SATA connectors |
| J5 | RS232 Serial Port |
| J6-J7 | Firefly Connector 0 |
| J13-J14 | Firefly Connector 1 |
| J8 | Ethernet |
| J15 | GPIO Header |
Table 2 : Connector Definitions
LED Definitions
The position and description of the board status LED is shown in LED Locations:
Figure 4 : LED Locations
| Comp. Ref. | Function | ON State | Off State |
| D3(Green) | Display Port 3.3V Supply Status | Normal operation | Fault |
| D4(Green) | PSMIO31 LED | PSMIO=Logic Low | PSMIO=Logic High |
| D5(Green) | 3.3V Supply Status | Normal operation | Power Off |
Table 3 : LED Definitions
JTAG Interface
On-board Interface
The JTAG boundary scan chain can be accessed via a standard header (J11).
This allows the connection of the Xilinx JTAG cable for FPGA debug and Flash programming via the Xilinx toolchain.
JTAG Voltages
The Vcc supply provided to the JTAG cable on the config header is +3.3V and is protected by a poly fuse rated at 350mA.
SATA Connectors
The ADM-VPX3-9Z5-RTM board has five standard right angle SATA receptacles for use with SATA compliant storage devices.
One of the SATA devices is connected to the PS side and the remainder are connected to the PL side.
| Connector | Signal | FPGA Bank | P pin | N pin |
| PS_SATA (J4) | PS_TX0 | PS Bank 505 | AH39 | AH40 |
| PS_RX0 | PS Bank 505 | AG41 | AG42 | |
| PL_SATA0 (J16) | DP2_C2M | MGT Quad 226 | AL6 | AL5 |
| DP2_M2C | MGT Quad 226 | AM4 | AM3 | |
| PL_SATA1 (J17) | DP3_C2M | MGT Quad 226 | AK8 | AK7 |
| DP3_M2C | MGT Quad 226 | AL2 | AL1 | |
| PL_SATA2 (J18) | DP2_C2M | MGT Quad 226 | AJ6 | AJ5 |
| DP2_M2C | MGT Quad 226 | AK4 | AK3 | |
| PL_SATA3 (J19) | DP3_C2M | MGT Quad 226 | AH8 | AH7 |
| DP3_M2C | MGT Quad 226 | AJ2 | AJ1 |
Table 4 : SATA Connections
FireFly Connectors
| Connector | Ref Des | FPGA Bank |
| 0 | J6-J7 | MGT Quad 227 |
| 1 | J13-J14 | MGT Quad 228 |
Table 5 : Firefly Connectors
CAN BUS Header
| Pin | Signal Name |
| 1 | GND |
| 2 | GND |
| 3 | CAN_GND |
| 4 | CAN_H |
| 5 | CAN_L |
| 6 | CAN_GND |
| 7 | CAN_L |
| 8 | CAN_H |
Table 6 : Header J12
RS232 Dtype
| Pin | Signal Name |
| 1 | – |
| 2 | TXD |
| 3 | RXD |
| 4 | – |
| 5 | GND |
| 6 | – |
| 7 | – |
| 8 | – |
| 9 | – |
Table 7 : Header J5
GPIO Headers
| Pin | Signal Name | FPGA Pin |
| 1 | P1_GP_1V8_P_10 | AU11 |
| 2 | P1_GP_1V8_P_9 | AW11 |
| 3 | P1_GP_1V8_N_10 | AV11 |
| 4 | P1_GP_1V8_N_9 | AW10 |
| 5 | GP4_1V8_P | AJ15 |
| 6 | GP3_1V8_P | AM13 |
| 7 | GP4_1V8_N | AK15 |
| 8 | GP3_1V8_N | AN13 |
| 9 | GP2_1V8_P | AN14 |
| 10 | GP1_1V8_P | AJ14 |
| 11 | GP2_1V8_N | AP14 |
| 12 | GP1_1V8_N | AK14 |
Table 8 : Header J1
| Pin | Signal Name | FPGA Pin |
| 1 | P1_GP_1V8_P_12 | BB5 |
| 2 | P1_GP_1V8_P_11 | AV12 |
| 3 | P1_GP_1V8_N_12 | BB4 |
| 4 | P1_GP_1V8_N_11 | AW12 |
| 5 | GP8_1V8_P | AM11 |
| 6 | GP7_1V8_P | AM10 |
| 7 | GP8_1V8_N | AN11 |
| 8 | GP7_1V8_N | AN10 |
| 9 | GP6_1V8_P | AL15 |
| 10 | GP5_1V8_P | AL14 |
| 11 | GP6_1V8_N | AM15 |
| 12 | GP5_1V8_N | AM14 |
Table 9 : Header J2
| Pin | Signal Name | FPGA Pin |
| 1 | GP_SE_3V3_5 | D2 |
| 2 | GP_SE_3V3_2 | C3 |
| 3 | GP_SE_3V3_4 | C5 |
| 4 | GP_SE_3V3_3 | C6 |
| 5 | GP_SE_3V3_6 | C1 |
| 6 | GP_SE_3V3_1 | C4 |
| 7 | GP_SE_3V3_7 | D4 |
| 8 | GP_SE_3V3_0 | B1 |
Table 10 : Header J15
Revision History
| Date | Revision | Nature of Change |
| 8-Jun-21 | 1 | Initial Release |
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Documents / Resources
 | ALPHA DATA ADM-VPX3-9Z5-RTM Rear Transition Module [pdf] User Manual ADM-VPX3-9Z5-RTM, Rear Transition Module, ADM-VPX3-9Z5-RTM Rear Transition Module, Transition Module, Module |
 | ALPHA DATA ADM-VPX3-9Z5-RTM Rear Transition Module [pdf] User Manual ADM-VPX3-9Z5-RTM Rear Transition Module, ADM-VPX3-9Z5-RTM, Rear Transition Module, Transition Module, Module |
